1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include <net/busy_poll.h> 29 #include "i40e.h" 30 #include "i40e_prototype.h" 31 32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 33 u32 td_tag) 34 { 35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 40 } 41 42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 43 #define I40E_FD_CLEAN_DELAY 10 44 /** 45 * i40e_program_fdir_filter - Program a Flow Director filter 46 * @fdir_data: Packet data that will be filter parameters 47 * @raw_packet: the pre-allocated packet buffer for FDir 48 * @pf: The PF pointer 49 * @add: True for add/update, False for remove 50 **/ 51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, 52 struct i40e_pf *pf, bool add) 53 { 54 struct i40e_filter_program_desc *fdir_desc; 55 struct i40e_tx_buffer *tx_buf, *first; 56 struct i40e_tx_desc *tx_desc; 57 struct i40e_ring *tx_ring; 58 unsigned int fpt, dcc; 59 struct i40e_vsi *vsi; 60 struct device *dev; 61 dma_addr_t dma; 62 u32 td_cmd = 0; 63 u16 delay = 0; 64 u16 i; 65 66 /* find existing FDIR VSI */ 67 vsi = NULL; 68 for (i = 0; i < pf->num_alloc_vsi; i++) 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) 70 vsi = pf->vsi[i]; 71 if (!vsi) 72 return -ENOENT; 73 74 tx_ring = vsi->tx_rings[0]; 75 dev = tx_ring->dev; 76 77 /* we need two descriptors to add/del a filter and we can wait */ 78 do { 79 if (I40E_DESC_UNUSED(tx_ring) > 1) 80 break; 81 msleep_interruptible(1); 82 delay++; 83 } while (delay < I40E_FD_CLEAN_DELAY); 84 85 if (!(I40E_DESC_UNUSED(tx_ring) > 1)) 86 return -EAGAIN; 87 88 dma = dma_map_single(dev, raw_packet, 89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 90 if (dma_mapping_error(dev, dma)) 91 goto dma_fail; 92 93 /* grab the next descriptor */ 94 i = tx_ring->next_to_use; 95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 96 first = &tx_ring->tx_bi[i]; 97 memset(first, 0, sizeof(struct i40e_tx_buffer)); 98 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 100 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 102 I40E_TXD_FLTR_QW0_QINDEX_MASK; 103 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & 105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK; 106 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & 108 I40E_TXD_FLTR_QW0_PCTYPE_MASK; 109 110 /* Use LAN VSI Id if not programmed by user */ 111 if (fdir_data->dest_vsi == 0) 112 fpt |= (pf->vsi[pf->lan_vsi]->id) << 113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 114 else 115 fpt |= ((u32)fdir_data->dest_vsi << 116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & 117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK; 118 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; 120 121 if (add) 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 123 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 124 else 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 126 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 127 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & 129 I40E_TXD_FLTR_QW1_DEST_MASK; 130 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & 132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK; 133 134 if (fdir_data->cnt_index != 0) { 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 136 dcc |= ((u32)fdir_data->cnt_index << 137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 139 } 140 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); 142 fdir_desc->rsvd = cpu_to_le32(0); 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); 145 146 /* Now program a dummy descriptor */ 147 i = tx_ring->next_to_use; 148 tx_desc = I40E_TX_DESC(tx_ring, i); 149 tx_buf = &tx_ring->tx_bi[i]; 150 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 152 153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 154 155 /* record length, and DMA address */ 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 157 dma_unmap_addr_set(tx_buf, dma, dma); 158 159 tx_desc->buffer_addr = cpu_to_le64(dma); 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 161 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 163 tx_buf->raw_buf = (void *)raw_packet; 164 165 tx_desc->cmd_type_offset_bsz = 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 167 168 /* Force memory writes to complete before letting h/w 169 * know there are new descriptors to fetch. 170 */ 171 wmb(); 172 173 /* Mark the data descriptor to be watched */ 174 first->next_to_watch = tx_desc; 175 176 writel(tx_ring->next_to_use, tx_ring->tail); 177 return 0; 178 179 dma_fail: 180 return -1; 181 } 182 183 #define IP_HEADER_OFFSET 14 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 185 /** 186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 187 * @vsi: pointer to the targeted VSI 188 * @fd_data: the flow director data required for the FDir descriptor 189 * @add: true adds a filter, false removes it 190 * 191 * Returns 0 if the filters were successfully added or removed 192 **/ 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 194 struct i40e_fdir_filter *fd_data, 195 bool add) 196 { 197 struct i40e_pf *pf = vsi->back; 198 struct udphdr *udp; 199 struct iphdr *ip; 200 bool err = false; 201 u8 *raw_packet; 202 int ret; 203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 206 207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 208 if (!raw_packet) 209 return -ENOMEM; 210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 211 212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 214 + sizeof(struct iphdr)); 215 216 ip->daddr = fd_data->dst_ip[0]; 217 udp->dest = fd_data->dst_port; 218 ip->saddr = fd_data->src_ip[0]; 219 udp->source = fd_data->src_port; 220 221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 223 if (ret) { 224 dev_info(&pf->pdev->dev, 225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 226 fd_data->pctype, fd_data->fd_id, ret); 227 err = true; 228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 229 if (add) 230 dev_info(&pf->pdev->dev, 231 "Filter OK for PCTYPE %d loc = %d\n", 232 fd_data->pctype, fd_data->fd_id); 233 else 234 dev_info(&pf->pdev->dev, 235 "Filter deleted for PCTYPE %d loc = %d\n", 236 fd_data->pctype, fd_data->fd_id); 237 } 238 if (err) 239 kfree(raw_packet); 240 241 return err ? -EOPNOTSUPP : 0; 242 } 243 244 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 245 /** 246 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 247 * @vsi: pointer to the targeted VSI 248 * @fd_data: the flow director data required for the FDir descriptor 249 * @add: true adds a filter, false removes it 250 * 251 * Returns 0 if the filters were successfully added or removed 252 **/ 253 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 254 struct i40e_fdir_filter *fd_data, 255 bool add) 256 { 257 struct i40e_pf *pf = vsi->back; 258 struct tcphdr *tcp; 259 struct iphdr *ip; 260 bool err = false; 261 u8 *raw_packet; 262 int ret; 263 /* Dummy packet */ 264 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 265 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 267 0x0, 0x72, 0, 0, 0, 0}; 268 269 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 270 if (!raw_packet) 271 return -ENOMEM; 272 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 273 274 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 275 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 276 + sizeof(struct iphdr)); 277 278 ip->daddr = fd_data->dst_ip[0]; 279 tcp->dest = fd_data->dst_port; 280 ip->saddr = fd_data->src_ip[0]; 281 tcp->source = fd_data->src_port; 282 283 if (add) { 284 pf->fd_tcp_rule++; 285 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { 286 if (I40E_DEBUG_FD & pf->hw.debug_mask) 287 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 288 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 289 } 290 } else { 291 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? 292 (pf->fd_tcp_rule - 1) : 0; 293 if (pf->fd_tcp_rule == 0) { 294 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 295 if (I40E_DEBUG_FD & pf->hw.debug_mask) 296 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); 297 } 298 } 299 300 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 301 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 302 303 if (ret) { 304 dev_info(&pf->pdev->dev, 305 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 306 fd_data->pctype, fd_data->fd_id, ret); 307 err = true; 308 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 309 if (add) 310 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 311 fd_data->pctype, fd_data->fd_id); 312 else 313 dev_info(&pf->pdev->dev, 314 "Filter deleted for PCTYPE %d loc = %d\n", 315 fd_data->pctype, fd_data->fd_id); 316 } 317 318 if (err) 319 kfree(raw_packet); 320 321 return err ? -EOPNOTSUPP : 0; 322 } 323 324 /** 325 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 326 * a specific flow spec 327 * @vsi: pointer to the targeted VSI 328 * @fd_data: the flow director data required for the FDir descriptor 329 * @add: true adds a filter, false removes it 330 * 331 * Returns 0 if the filters were successfully added or removed 332 **/ 333 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 334 struct i40e_fdir_filter *fd_data, 335 bool add) 336 { 337 return -EOPNOTSUPP; 338 } 339 340 #define I40E_IP_DUMMY_PACKET_LEN 34 341 /** 342 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 343 * a specific flow spec 344 * @vsi: pointer to the targeted VSI 345 * @fd_data: the flow director data required for the FDir descriptor 346 * @add: true adds a filter, false removes it 347 * 348 * Returns 0 if the filters were successfully added or removed 349 **/ 350 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 351 struct i40e_fdir_filter *fd_data, 352 bool add) 353 { 354 struct i40e_pf *pf = vsi->back; 355 struct iphdr *ip; 356 bool err = false; 357 u8 *raw_packet; 358 int ret; 359 int i; 360 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 361 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 362 0, 0, 0, 0}; 363 364 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 365 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 366 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 367 if (!raw_packet) 368 return -ENOMEM; 369 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 370 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 371 372 ip->saddr = fd_data->src_ip[0]; 373 ip->daddr = fd_data->dst_ip[0]; 374 ip->protocol = 0; 375 376 fd_data->pctype = i; 377 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 378 379 if (ret) { 380 dev_info(&pf->pdev->dev, 381 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 382 fd_data->pctype, fd_data->fd_id, ret); 383 err = true; 384 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 385 if (add) 386 dev_info(&pf->pdev->dev, 387 "Filter OK for PCTYPE %d loc = %d\n", 388 fd_data->pctype, fd_data->fd_id); 389 else 390 dev_info(&pf->pdev->dev, 391 "Filter deleted for PCTYPE %d loc = %d\n", 392 fd_data->pctype, fd_data->fd_id); 393 } 394 } 395 396 if (err) 397 kfree(raw_packet); 398 399 return err ? -EOPNOTSUPP : 0; 400 } 401 402 /** 403 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 404 * @vsi: pointer to the targeted VSI 405 * @cmd: command to get or set RX flow classification rules 406 * @add: true adds a filter, false removes it 407 * 408 **/ 409 int i40e_add_del_fdir(struct i40e_vsi *vsi, 410 struct i40e_fdir_filter *input, bool add) 411 { 412 struct i40e_pf *pf = vsi->back; 413 int ret; 414 415 switch (input->flow_type & ~FLOW_EXT) { 416 case TCP_V4_FLOW: 417 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 418 break; 419 case UDP_V4_FLOW: 420 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 421 break; 422 case SCTP_V4_FLOW: 423 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 424 break; 425 case IPV4_FLOW: 426 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 427 break; 428 case IP_USER_FLOW: 429 switch (input->ip4_proto) { 430 case IPPROTO_TCP: 431 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 432 break; 433 case IPPROTO_UDP: 434 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 435 break; 436 case IPPROTO_SCTP: 437 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 438 break; 439 default: 440 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 441 break; 442 } 443 break; 444 default: 445 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", 446 input->flow_type); 447 ret = -EINVAL; 448 } 449 450 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ 451 return ret; 452 } 453 454 /** 455 * i40e_fd_handle_status - check the Programming Status for FD 456 * @rx_ring: the Rx ring for this descriptor 457 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 458 * @prog_id: the id originally used for programming 459 * 460 * This is used to verify if the FD programming or invalidation 461 * requested by SW to the HW is successful or not and take actions accordingly. 462 **/ 463 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 464 union i40e_rx_desc *rx_desc, u8 prog_id) 465 { 466 struct i40e_pf *pf = rx_ring->vsi->back; 467 struct pci_dev *pdev = pf->pdev; 468 u32 fcnt_prog, fcnt_avail; 469 u32 error; 470 u64 qw; 471 472 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 473 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 474 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 475 476 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 477 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); 478 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 479 (I40E_DEBUG_FD & pf->hw.debug_mask)) 480 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 481 pf->fd_inv); 482 483 /* Check if the programming error is for ATR. 484 * If so, auto disable ATR and set a state for 485 * flush in progress. Next time we come here if flush is in 486 * progress do nothing, once flush is complete the state will 487 * be cleared. 488 */ 489 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) 490 return; 491 492 pf->fd_add_err++; 493 /* store the current atr filter count */ 494 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 495 496 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && 497 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { 498 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; 499 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); 500 } 501 502 /* filter programming failed most likely due to table full */ 503 fcnt_prog = i40e_get_global_fd_count(pf); 504 fcnt_avail = pf->fdir_pf_filter_count; 505 /* If ATR is running fcnt_prog can quickly change, 506 * if we are very close to full, it makes sense to disable 507 * FD ATR/SB and then re-enable it when there is room. 508 */ 509 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 510 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 511 !(pf->auto_disable_flags & 512 I40E_FLAG_FD_SB_ENABLED)) { 513 if (I40E_DEBUG_FD & pf->hw.debug_mask) 514 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 515 pf->auto_disable_flags |= 516 I40E_FLAG_FD_SB_ENABLED; 517 } 518 } 519 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 520 if (I40E_DEBUG_FD & pf->hw.debug_mask) 521 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 522 rx_desc->wb.qword0.hi_dword.fd_id); 523 } 524 } 525 526 /** 527 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 528 * @ring: the ring that owns the buffer 529 * @tx_buffer: the buffer to free 530 **/ 531 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 532 struct i40e_tx_buffer *tx_buffer) 533 { 534 if (tx_buffer->skb) { 535 dev_kfree_skb_any(tx_buffer->skb); 536 if (dma_unmap_len(tx_buffer, len)) 537 dma_unmap_single(ring->dev, 538 dma_unmap_addr(tx_buffer, dma), 539 dma_unmap_len(tx_buffer, len), 540 DMA_TO_DEVICE); 541 } else if (dma_unmap_len(tx_buffer, len)) { 542 dma_unmap_page(ring->dev, 543 dma_unmap_addr(tx_buffer, dma), 544 dma_unmap_len(tx_buffer, len), 545 DMA_TO_DEVICE); 546 } 547 548 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 549 kfree(tx_buffer->raw_buf); 550 551 tx_buffer->next_to_watch = NULL; 552 tx_buffer->skb = NULL; 553 dma_unmap_len_set(tx_buffer, len, 0); 554 /* tx_buffer must be completely set up in the transmit path */ 555 } 556 557 /** 558 * i40e_clean_tx_ring - Free any empty Tx buffers 559 * @tx_ring: ring to be cleaned 560 **/ 561 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 562 { 563 unsigned long bi_size; 564 u16 i; 565 566 /* ring already cleared, nothing to do */ 567 if (!tx_ring->tx_bi) 568 return; 569 570 /* Free all the Tx ring sk_buffs */ 571 for (i = 0; i < tx_ring->count; i++) 572 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 573 574 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 575 memset(tx_ring->tx_bi, 0, bi_size); 576 577 /* Zero out the descriptor ring */ 578 memset(tx_ring->desc, 0, tx_ring->size); 579 580 tx_ring->next_to_use = 0; 581 tx_ring->next_to_clean = 0; 582 583 if (!tx_ring->netdev) 584 return; 585 586 /* cleanup Tx queue statistics */ 587 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 588 tx_ring->queue_index)); 589 } 590 591 /** 592 * i40e_free_tx_resources - Free Tx resources per queue 593 * @tx_ring: Tx descriptor ring for a specific queue 594 * 595 * Free all transmit software resources 596 **/ 597 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 598 { 599 i40e_clean_tx_ring(tx_ring); 600 kfree(tx_ring->tx_bi); 601 tx_ring->tx_bi = NULL; 602 603 if (tx_ring->desc) { 604 dma_free_coherent(tx_ring->dev, tx_ring->size, 605 tx_ring->desc, tx_ring->dma); 606 tx_ring->desc = NULL; 607 } 608 } 609 610 /** 611 * i40e_get_tx_pending - how many tx descriptors not processed 612 * @tx_ring: the ring of descriptors 613 * @in_sw: is tx_pending being checked in SW or HW 614 * 615 * Since there is no access to the ring head register 616 * in XL710, we need to use our local copies 617 **/ 618 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw) 619 { 620 u32 head, tail; 621 622 if (!in_sw) 623 head = i40e_get_head(ring); 624 else 625 head = ring->next_to_clean; 626 tail = readl(ring->tail); 627 628 if (head != tail) 629 return (head < tail) ? 630 tail - head : (tail + ring->count - head); 631 632 return 0; 633 } 634 635 #define WB_STRIDE 0x3 636 637 /** 638 * i40e_clean_tx_irq - Reclaim resources after transmit completes 639 * @vsi: the VSI we care about 640 * @tx_ring: Tx ring to clean 641 * @napi_budget: Used to determine if we are in netpoll 642 * 643 * Returns true if there's any budget left (e.g. the clean is finished) 644 **/ 645 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 646 struct i40e_ring *tx_ring, int napi_budget) 647 { 648 u16 i = tx_ring->next_to_clean; 649 struct i40e_tx_buffer *tx_buf; 650 struct i40e_tx_desc *tx_head; 651 struct i40e_tx_desc *tx_desc; 652 unsigned int total_bytes = 0, total_packets = 0; 653 unsigned int budget = vsi->work_limit; 654 655 tx_buf = &tx_ring->tx_bi[i]; 656 tx_desc = I40E_TX_DESC(tx_ring, i); 657 i -= tx_ring->count; 658 659 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 660 661 do { 662 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 663 664 /* if next_to_watch is not set then there is no work pending */ 665 if (!eop_desc) 666 break; 667 668 /* prevent any other reads prior to eop_desc */ 669 read_barrier_depends(); 670 671 /* we have caught up to head, no work left to do */ 672 if (tx_head == tx_desc) 673 break; 674 675 /* clear next_to_watch to prevent false hangs */ 676 tx_buf->next_to_watch = NULL; 677 678 /* update the statistics for this packet */ 679 total_bytes += tx_buf->bytecount; 680 total_packets += tx_buf->gso_segs; 681 682 /* free the skb */ 683 napi_consume_skb(tx_buf->skb, napi_budget); 684 685 /* unmap skb header data */ 686 dma_unmap_single(tx_ring->dev, 687 dma_unmap_addr(tx_buf, dma), 688 dma_unmap_len(tx_buf, len), 689 DMA_TO_DEVICE); 690 691 /* clear tx_buffer data */ 692 tx_buf->skb = NULL; 693 dma_unmap_len_set(tx_buf, len, 0); 694 695 /* unmap remaining buffers */ 696 while (tx_desc != eop_desc) { 697 698 tx_buf++; 699 tx_desc++; 700 i++; 701 if (unlikely(!i)) { 702 i -= tx_ring->count; 703 tx_buf = tx_ring->tx_bi; 704 tx_desc = I40E_TX_DESC(tx_ring, 0); 705 } 706 707 /* unmap any remaining paged data */ 708 if (dma_unmap_len(tx_buf, len)) { 709 dma_unmap_page(tx_ring->dev, 710 dma_unmap_addr(tx_buf, dma), 711 dma_unmap_len(tx_buf, len), 712 DMA_TO_DEVICE); 713 dma_unmap_len_set(tx_buf, len, 0); 714 } 715 } 716 717 /* move us one more past the eop_desc for start of next pkt */ 718 tx_buf++; 719 tx_desc++; 720 i++; 721 if (unlikely(!i)) { 722 i -= tx_ring->count; 723 tx_buf = tx_ring->tx_bi; 724 tx_desc = I40E_TX_DESC(tx_ring, 0); 725 } 726 727 prefetch(tx_desc); 728 729 /* update budget accounting */ 730 budget--; 731 } while (likely(budget)); 732 733 i += tx_ring->count; 734 tx_ring->next_to_clean = i; 735 u64_stats_update_begin(&tx_ring->syncp); 736 tx_ring->stats.bytes += total_bytes; 737 tx_ring->stats.packets += total_packets; 738 u64_stats_update_end(&tx_ring->syncp); 739 tx_ring->q_vector->tx.total_bytes += total_bytes; 740 tx_ring->q_vector->tx.total_packets += total_packets; 741 742 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { 743 unsigned int j = 0; 744 745 /* check to see if there are < 4 descriptors 746 * waiting to be written back, then kick the hardware to force 747 * them to be written back in case we stay in NAPI. 748 * In this mode on X722 we do not enable Interrupt. 749 */ 750 j = i40e_get_tx_pending(tx_ring, false); 751 752 if (budget && 753 ((j / (WB_STRIDE + 1)) == 0) && (j != 0) && 754 !test_bit(__I40E_DOWN, &vsi->state) && 755 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 756 tx_ring->arm_wb = true; 757 } 758 759 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, 760 tx_ring->queue_index), 761 total_packets, total_bytes); 762 763 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 764 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 765 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 766 /* Make sure that anybody stopping the queue after this 767 * sees the new next_to_clean. 768 */ 769 smp_mb(); 770 if (__netif_subqueue_stopped(tx_ring->netdev, 771 tx_ring->queue_index) && 772 !test_bit(__I40E_DOWN, &vsi->state)) { 773 netif_wake_subqueue(tx_ring->netdev, 774 tx_ring->queue_index); 775 ++tx_ring->tx_stats.restart_queue; 776 } 777 } 778 779 return !!budget; 780 } 781 782 /** 783 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 784 * @vsi: the VSI we care about 785 * @q_vector: the vector on which to enable writeback 786 * 787 **/ 788 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 789 struct i40e_q_vector *q_vector) 790 { 791 u16 flags = q_vector->tx.ring[0].flags; 792 u32 val; 793 794 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 795 return; 796 797 if (q_vector->arm_wb_state) 798 return; 799 800 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 801 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 802 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 803 804 wr32(&vsi->back->hw, 805 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 806 val); 807 } else { 808 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 809 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 810 811 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 812 } 813 q_vector->arm_wb_state = true; 814 } 815 816 /** 817 * i40e_force_wb - Issue SW Interrupt so HW does a wb 818 * @vsi: the VSI we care about 819 * @q_vector: the vector on which to force writeback 820 * 821 **/ 822 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 823 { 824 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 825 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 826 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 827 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 828 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 829 /* allow 00 to be written to the index */ 830 831 wr32(&vsi->back->hw, 832 I40E_PFINT_DYN_CTLN(q_vector->v_idx + 833 vsi->base_vector - 1), val); 834 } else { 835 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 836 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 837 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 838 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 839 /* allow 00 to be written to the index */ 840 841 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 842 } 843 } 844 845 /** 846 * i40e_set_new_dynamic_itr - Find new ITR level 847 * @rc: structure containing ring performance data 848 * 849 * Returns true if ITR changed, false if not 850 * 851 * Stores a new ITR value based on packets and byte counts during 852 * the last interrupt. The advantage of per interrupt computation 853 * is faster updates and more accurate ITR for the current traffic 854 * pattern. Constants in this function were computed based on 855 * theoretical maximum wire speed and thresholds were set based on 856 * testing data as well as attempting to minimize response time 857 * while increasing bulk throughput. 858 **/ 859 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 860 { 861 enum i40e_latency_range new_latency_range = rc->latency_range; 862 struct i40e_q_vector *qv = rc->ring->q_vector; 863 u32 new_itr = rc->itr; 864 int bytes_per_int; 865 int usecs; 866 867 if (rc->total_packets == 0 || !rc->itr) 868 return false; 869 870 /* simple throttlerate management 871 * 0-10MB/s lowest (50000 ints/s) 872 * 10-20MB/s low (20000 ints/s) 873 * 20-1249MB/s bulk (18000 ints/s) 874 * > 40000 Rx packets per second (8000 ints/s) 875 * 876 * The math works out because the divisor is in 10^(-6) which 877 * turns the bytes/us input value into MB/s values, but 878 * make sure to use usecs, as the register values written 879 * are in 2 usec increments in the ITR registers, and make sure 880 * to use the smoothed values that the countdown timer gives us. 881 */ 882 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; 883 bytes_per_int = rc->total_bytes / usecs; 884 885 switch (new_latency_range) { 886 case I40E_LOWEST_LATENCY: 887 if (bytes_per_int > 10) 888 new_latency_range = I40E_LOW_LATENCY; 889 break; 890 case I40E_LOW_LATENCY: 891 if (bytes_per_int > 20) 892 new_latency_range = I40E_BULK_LATENCY; 893 else if (bytes_per_int <= 10) 894 new_latency_range = I40E_LOWEST_LATENCY; 895 break; 896 case I40E_BULK_LATENCY: 897 case I40E_ULTRA_LATENCY: 898 default: 899 if (bytes_per_int <= 20) 900 new_latency_range = I40E_LOW_LATENCY; 901 break; 902 } 903 904 /* this is to adjust RX more aggressively when streaming small 905 * packets. The value of 40000 was picked as it is just beyond 906 * what the hardware can receive per second if in low latency 907 * mode. 908 */ 909 #define RX_ULTRA_PACKET_RATE 40000 910 911 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && 912 (&qv->rx == rc)) 913 new_latency_range = I40E_ULTRA_LATENCY; 914 915 rc->latency_range = new_latency_range; 916 917 switch (new_latency_range) { 918 case I40E_LOWEST_LATENCY: 919 new_itr = I40E_ITR_50K; 920 break; 921 case I40E_LOW_LATENCY: 922 new_itr = I40E_ITR_20K; 923 break; 924 case I40E_BULK_LATENCY: 925 new_itr = I40E_ITR_18K; 926 break; 927 case I40E_ULTRA_LATENCY: 928 new_itr = I40E_ITR_8K; 929 break; 930 default: 931 break; 932 } 933 934 rc->total_bytes = 0; 935 rc->total_packets = 0; 936 937 if (new_itr != rc->itr) { 938 rc->itr = new_itr; 939 return true; 940 } 941 942 return false; 943 } 944 945 /** 946 * i40e_clean_programming_status - clean the programming status descriptor 947 * @rx_ring: the rx ring that has this descriptor 948 * @rx_desc: the rx descriptor written back by HW 949 * 950 * Flow director should handle FD_FILTER_STATUS to check its filter programming 951 * status being successful or not and take actions accordingly. FCoE should 952 * handle its context/filter programming/invalidation status and take actions. 953 * 954 **/ 955 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 956 union i40e_rx_desc *rx_desc) 957 { 958 u64 qw; 959 u8 id; 960 961 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 962 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 963 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 964 965 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 966 i40e_fd_handle_status(rx_ring, rx_desc, id); 967 #ifdef I40E_FCOE 968 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || 969 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) 970 i40e_fcoe_handle_status(rx_ring, rx_desc, id); 971 #endif 972 } 973 974 /** 975 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 976 * @tx_ring: the tx ring to set up 977 * 978 * Return 0 on success, negative on error 979 **/ 980 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 981 { 982 struct device *dev = tx_ring->dev; 983 int bi_size; 984 985 if (!dev) 986 return -ENOMEM; 987 988 /* warn if we are about to overwrite the pointer */ 989 WARN_ON(tx_ring->tx_bi); 990 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 991 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 992 if (!tx_ring->tx_bi) 993 goto err; 994 995 /* round up to nearest 4K */ 996 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 997 /* add u32 for head writeback, align after this takes care of 998 * guaranteeing this is at least one cache line in size 999 */ 1000 tx_ring->size += sizeof(u32); 1001 tx_ring->size = ALIGN(tx_ring->size, 4096); 1002 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1003 &tx_ring->dma, GFP_KERNEL); 1004 if (!tx_ring->desc) { 1005 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1006 tx_ring->size); 1007 goto err; 1008 } 1009 1010 tx_ring->next_to_use = 0; 1011 tx_ring->next_to_clean = 0; 1012 return 0; 1013 1014 err: 1015 kfree(tx_ring->tx_bi); 1016 tx_ring->tx_bi = NULL; 1017 return -ENOMEM; 1018 } 1019 1020 /** 1021 * i40e_clean_rx_ring - Free Rx buffers 1022 * @rx_ring: ring to be cleaned 1023 **/ 1024 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1025 { 1026 struct device *dev = rx_ring->dev; 1027 unsigned long bi_size; 1028 u16 i; 1029 1030 /* ring already cleared, nothing to do */ 1031 if (!rx_ring->rx_bi) 1032 return; 1033 1034 /* Free all the Rx ring sk_buffs */ 1035 for (i = 0; i < rx_ring->count; i++) { 1036 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; 1037 1038 if (rx_bi->skb) { 1039 dev_kfree_skb(rx_bi->skb); 1040 rx_bi->skb = NULL; 1041 } 1042 if (!rx_bi->page) 1043 continue; 1044 1045 dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE); 1046 __free_pages(rx_bi->page, 0); 1047 1048 rx_bi->page = NULL; 1049 rx_bi->page_offset = 0; 1050 } 1051 1052 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1053 memset(rx_ring->rx_bi, 0, bi_size); 1054 1055 /* Zero out the descriptor ring */ 1056 memset(rx_ring->desc, 0, rx_ring->size); 1057 1058 rx_ring->next_to_alloc = 0; 1059 rx_ring->next_to_clean = 0; 1060 rx_ring->next_to_use = 0; 1061 } 1062 1063 /** 1064 * i40e_free_rx_resources - Free Rx resources 1065 * @rx_ring: ring to clean the resources from 1066 * 1067 * Free all receive software resources 1068 **/ 1069 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1070 { 1071 i40e_clean_rx_ring(rx_ring); 1072 kfree(rx_ring->rx_bi); 1073 rx_ring->rx_bi = NULL; 1074 1075 if (rx_ring->desc) { 1076 dma_free_coherent(rx_ring->dev, rx_ring->size, 1077 rx_ring->desc, rx_ring->dma); 1078 rx_ring->desc = NULL; 1079 } 1080 } 1081 1082 /** 1083 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1084 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1085 * 1086 * Returns 0 on success, negative on failure 1087 **/ 1088 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1089 { 1090 struct device *dev = rx_ring->dev; 1091 int bi_size; 1092 1093 /* warn if we are about to overwrite the pointer */ 1094 WARN_ON(rx_ring->rx_bi); 1095 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1096 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1097 if (!rx_ring->rx_bi) 1098 goto err; 1099 1100 u64_stats_init(&rx_ring->syncp); 1101 1102 /* Round up to nearest 4K */ 1103 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1104 rx_ring->size = ALIGN(rx_ring->size, 4096); 1105 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1106 &rx_ring->dma, GFP_KERNEL); 1107 1108 if (!rx_ring->desc) { 1109 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1110 rx_ring->size); 1111 goto err; 1112 } 1113 1114 rx_ring->next_to_alloc = 0; 1115 rx_ring->next_to_clean = 0; 1116 rx_ring->next_to_use = 0; 1117 1118 return 0; 1119 err: 1120 kfree(rx_ring->rx_bi); 1121 rx_ring->rx_bi = NULL; 1122 return -ENOMEM; 1123 } 1124 1125 /** 1126 * i40e_release_rx_desc - Store the new tail and head values 1127 * @rx_ring: ring to bump 1128 * @val: new head index 1129 **/ 1130 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1131 { 1132 rx_ring->next_to_use = val; 1133 1134 /* update next to alloc since we have filled the ring */ 1135 rx_ring->next_to_alloc = val; 1136 1137 /* Force memory writes to complete before letting h/w 1138 * know there are new descriptors to fetch. (Only 1139 * applicable for weak-ordered memory model archs, 1140 * such as IA-64). 1141 */ 1142 wmb(); 1143 writel(val, rx_ring->tail); 1144 } 1145 1146 /** 1147 * i40e_alloc_mapped_page - recycle or make a new page 1148 * @rx_ring: ring to use 1149 * @bi: rx_buffer struct to modify 1150 * 1151 * Returns true if the page was successfully allocated or 1152 * reused. 1153 **/ 1154 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1155 struct i40e_rx_buffer *bi) 1156 { 1157 struct page *page = bi->page; 1158 dma_addr_t dma; 1159 1160 /* since we are recycling buffers we should seldom need to alloc */ 1161 if (likely(page)) { 1162 rx_ring->rx_stats.page_reuse_count++; 1163 return true; 1164 } 1165 1166 /* alloc new page for storage */ 1167 page = dev_alloc_page(); 1168 if (unlikely(!page)) { 1169 rx_ring->rx_stats.alloc_page_failed++; 1170 return false; 1171 } 1172 1173 /* map page for use */ 1174 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 1175 1176 /* if mapping failed free memory back to system since 1177 * there isn't much point in holding memory we can't use 1178 */ 1179 if (dma_mapping_error(rx_ring->dev, dma)) { 1180 __free_pages(page, 0); 1181 rx_ring->rx_stats.alloc_page_failed++; 1182 return false; 1183 } 1184 1185 bi->dma = dma; 1186 bi->page = page; 1187 bi->page_offset = 0; 1188 1189 return true; 1190 } 1191 1192 /** 1193 * i40e_receive_skb - Send a completed packet up the stack 1194 * @rx_ring: rx ring in play 1195 * @skb: packet to send up 1196 * @vlan_tag: vlan tag for packet 1197 **/ 1198 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1199 struct sk_buff *skb, u16 vlan_tag) 1200 { 1201 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1202 1203 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1204 (vlan_tag & VLAN_VID_MASK)) 1205 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1206 1207 napi_gro_receive(&q_vector->napi, skb); 1208 } 1209 1210 /** 1211 * i40e_alloc_rx_buffers - Replace used receive buffers 1212 * @rx_ring: ring to place buffers on 1213 * @cleaned_count: number of buffers to replace 1214 * 1215 * Returns false if all allocations were successful, true if any fail 1216 **/ 1217 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1218 { 1219 u16 ntu = rx_ring->next_to_use; 1220 union i40e_rx_desc *rx_desc; 1221 struct i40e_rx_buffer *bi; 1222 1223 /* do nothing if no valid netdev defined */ 1224 if (!rx_ring->netdev || !cleaned_count) 1225 return false; 1226 1227 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1228 bi = &rx_ring->rx_bi[ntu]; 1229 1230 do { 1231 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1232 goto no_buffers; 1233 1234 /* Refresh the desc even if buffer_addrs didn't change 1235 * because each write-back erases this info. 1236 */ 1237 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1238 rx_desc->read.hdr_addr = 0; 1239 1240 rx_desc++; 1241 bi++; 1242 ntu++; 1243 if (unlikely(ntu == rx_ring->count)) { 1244 rx_desc = I40E_RX_DESC(rx_ring, 0); 1245 bi = rx_ring->rx_bi; 1246 ntu = 0; 1247 } 1248 1249 /* clear the status bits for the next_to_use descriptor */ 1250 rx_desc->wb.qword1.status_error_len = 0; 1251 1252 cleaned_count--; 1253 } while (cleaned_count); 1254 1255 if (rx_ring->next_to_use != ntu) 1256 i40e_release_rx_desc(rx_ring, ntu); 1257 1258 return false; 1259 1260 no_buffers: 1261 if (rx_ring->next_to_use != ntu) 1262 i40e_release_rx_desc(rx_ring, ntu); 1263 1264 /* make sure to come back via polling to try again after 1265 * allocation failure 1266 */ 1267 return true; 1268 } 1269 1270 /** 1271 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1272 * @vsi: the VSI we care about 1273 * @skb: skb currently being received and modified 1274 * @rx_desc: the receive descriptor 1275 * 1276 * skb->protocol must be set before this function is called 1277 **/ 1278 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1279 struct sk_buff *skb, 1280 union i40e_rx_desc *rx_desc) 1281 { 1282 struct i40e_rx_ptype_decoded decoded; 1283 u32 rx_error, rx_status; 1284 bool ipv4, ipv6; 1285 u8 ptype; 1286 u64 qword; 1287 1288 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1289 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1290 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1291 I40E_RXD_QW1_ERROR_SHIFT; 1292 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1293 I40E_RXD_QW1_STATUS_SHIFT; 1294 decoded = decode_rx_desc_ptype(ptype); 1295 1296 skb->ip_summed = CHECKSUM_NONE; 1297 1298 skb_checksum_none_assert(skb); 1299 1300 /* Rx csum enabled and ip headers found? */ 1301 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1302 return; 1303 1304 /* did the hardware decode the packet and checksum? */ 1305 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1306 return; 1307 1308 /* both known and outer_ip must be set for the below code to work */ 1309 if (!(decoded.known && decoded.outer_ip)) 1310 return; 1311 1312 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1313 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); 1314 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1315 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); 1316 1317 if (ipv4 && 1318 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1319 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1320 goto checksum_fail; 1321 1322 /* likely incorrect csum if alternate IP extension headers found */ 1323 if (ipv6 && 1324 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1325 /* don't increment checksum err here, non-fatal err */ 1326 return; 1327 1328 /* there was some L4 error, count error and punt packet to the stack */ 1329 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1330 goto checksum_fail; 1331 1332 /* handle packets that were not able to be checksummed due 1333 * to arrival speed, in this case the stack can compute 1334 * the csum. 1335 */ 1336 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1337 return; 1338 1339 /* If there is an outer header present that might contain a checksum 1340 * we need to bump the checksum level by 1 to reflect the fact that 1341 * we are indicating we validated the inner checksum. 1342 */ 1343 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) 1344 skb->csum_level = 1; 1345 1346 /* Only report checksum unnecessary for TCP, UDP, or SCTP */ 1347 switch (decoded.inner_prot) { 1348 case I40E_RX_PTYPE_INNER_PROT_TCP: 1349 case I40E_RX_PTYPE_INNER_PROT_UDP: 1350 case I40E_RX_PTYPE_INNER_PROT_SCTP: 1351 skb->ip_summed = CHECKSUM_UNNECESSARY; 1352 /* fall though */ 1353 default: 1354 break; 1355 } 1356 1357 return; 1358 1359 checksum_fail: 1360 vsi->back->hw_csum_rx_error++; 1361 } 1362 1363 /** 1364 * i40e_ptype_to_htype - get a hash type 1365 * @ptype: the ptype value from the descriptor 1366 * 1367 * Returns a hash type to be used by skb_set_hash 1368 **/ 1369 static inline int i40e_ptype_to_htype(u8 ptype) 1370 { 1371 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1372 1373 if (!decoded.known) 1374 return PKT_HASH_TYPE_NONE; 1375 1376 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1377 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1378 return PKT_HASH_TYPE_L4; 1379 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1380 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1381 return PKT_HASH_TYPE_L3; 1382 else 1383 return PKT_HASH_TYPE_L2; 1384 } 1385 1386 /** 1387 * i40e_rx_hash - set the hash value in the skb 1388 * @ring: descriptor ring 1389 * @rx_desc: specific descriptor 1390 **/ 1391 static inline void i40e_rx_hash(struct i40e_ring *ring, 1392 union i40e_rx_desc *rx_desc, 1393 struct sk_buff *skb, 1394 u8 rx_ptype) 1395 { 1396 u32 hash; 1397 const __le64 rss_mask = 1398 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1399 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1400 1401 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1402 return; 1403 1404 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1405 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1406 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); 1407 } 1408 } 1409 1410 /** 1411 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1412 * @rx_ring: rx descriptor ring packet is being transacted on 1413 * @rx_desc: pointer to the EOP Rx descriptor 1414 * @skb: pointer to current skb being populated 1415 * @rx_ptype: the packet type decoded by hardware 1416 * 1417 * This function checks the ring, descriptor, and packet information in 1418 * order to populate the hash, checksum, VLAN, protocol, and 1419 * other fields within the skb. 1420 **/ 1421 static inline 1422 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1423 union i40e_rx_desc *rx_desc, struct sk_buff *skb, 1424 u8 rx_ptype) 1425 { 1426 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1427 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1428 I40E_RXD_QW1_STATUS_SHIFT; 1429 u32 rsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1430 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1431 1432 if (unlikely(rsyn)) { 1433 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, rsyn); 1434 rx_ring->last_rx_timestamp = jiffies; 1435 } 1436 1437 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1438 1439 /* modifies the skb - consumes the enet header */ 1440 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1441 1442 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1443 1444 skb_record_rx_queue(skb, rx_ring->queue_index); 1445 } 1446 1447 /** 1448 * i40e_pull_tail - i40e specific version of skb_pull_tail 1449 * @rx_ring: rx descriptor ring packet is being transacted on 1450 * @skb: pointer to current skb being adjusted 1451 * 1452 * This function is an i40e specific version of __pskb_pull_tail. The 1453 * main difference between this version and the original function is that 1454 * this function can make several assumptions about the state of things 1455 * that allow for significant optimizations versus the standard function. 1456 * As a result we can do things like drop a frag and maintain an accurate 1457 * truesize for the skb. 1458 */ 1459 static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb) 1460 { 1461 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 1462 unsigned char *va; 1463 unsigned int pull_len; 1464 1465 /* it is valid to use page_address instead of kmap since we are 1466 * working with pages allocated out of the lomem pool per 1467 * alloc_page(GFP_ATOMIC) 1468 */ 1469 va = skb_frag_address(frag); 1470 1471 /* we need the header to contain the greater of either ETH_HLEN or 1472 * 60 bytes if the skb->len is less than 60 for skb_pad. 1473 */ 1474 pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE); 1475 1476 /* align pull length to size of long to optimize memcpy performance */ 1477 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1478 1479 /* update all of the pointers */ 1480 skb_frag_size_sub(frag, pull_len); 1481 frag->page_offset += pull_len; 1482 skb->data_len -= pull_len; 1483 skb->tail += pull_len; 1484 } 1485 1486 /** 1487 * i40e_cleanup_headers - Correct empty headers 1488 * @rx_ring: rx descriptor ring packet is being transacted on 1489 * @skb: pointer to current skb being fixed 1490 * 1491 * Also address the case where we are pulling data in on pages only 1492 * and as such no data is present in the skb header. 1493 * 1494 * In addition if skb is not at least 60 bytes we need to pad it so that 1495 * it is large enough to qualify as a valid Ethernet frame. 1496 * 1497 * Returns true if an error was encountered and skb was freed. 1498 **/ 1499 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) 1500 { 1501 /* place header in linear portion of buffer */ 1502 if (skb_is_nonlinear(skb)) 1503 i40e_pull_tail(rx_ring, skb); 1504 1505 /* if eth_skb_pad returns an error the skb was freed */ 1506 if (eth_skb_pad(skb)) 1507 return true; 1508 1509 return false; 1510 } 1511 1512 /** 1513 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1514 * @rx_ring: rx descriptor ring to store buffers on 1515 * @old_buff: donor buffer to have page reused 1516 * 1517 * Synchronizes page for reuse by the adapter 1518 **/ 1519 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1520 struct i40e_rx_buffer *old_buff) 1521 { 1522 struct i40e_rx_buffer *new_buff; 1523 u16 nta = rx_ring->next_to_alloc; 1524 1525 new_buff = &rx_ring->rx_bi[nta]; 1526 1527 /* update, and store next to alloc */ 1528 nta++; 1529 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1530 1531 /* transfer page from old buffer to new buffer */ 1532 *new_buff = *old_buff; 1533 } 1534 1535 /** 1536 * i40e_page_is_reserved - check if reuse is possible 1537 * @page: page struct to check 1538 */ 1539 static inline bool i40e_page_is_reserved(struct page *page) 1540 { 1541 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); 1542 } 1543 1544 /** 1545 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff 1546 * @rx_ring: rx descriptor ring to transact packets on 1547 * @rx_buffer: buffer containing page to add 1548 * @rx_desc: descriptor containing length of buffer written by hardware 1549 * @skb: sk_buff to place the data into 1550 * 1551 * This function will add the data contained in rx_buffer->page to the skb. 1552 * This is done either through a direct copy if the data in the buffer is 1553 * less than the skb header size, otherwise it will just attach the page as 1554 * a frag to the skb. 1555 * 1556 * The function will then update the page offset if necessary and return 1557 * true if the buffer can be reused by the adapter. 1558 **/ 1559 static bool i40e_add_rx_frag(struct i40e_ring *rx_ring, 1560 struct i40e_rx_buffer *rx_buffer, 1561 union i40e_rx_desc *rx_desc, 1562 struct sk_buff *skb) 1563 { 1564 struct page *page = rx_buffer->page; 1565 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1566 unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 1567 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 1568 #if (PAGE_SIZE < 8192) 1569 unsigned int truesize = I40E_RXBUFFER_2048; 1570 #else 1571 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 1572 unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; 1573 #endif 1574 1575 /* will the data fit in the skb we allocated? if so, just 1576 * copy it as it is pretty small anyway 1577 */ 1578 if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { 1579 unsigned char *va = page_address(page) + rx_buffer->page_offset; 1580 1581 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 1582 1583 /* page is not reserved, we can reuse buffer as-is */ 1584 if (likely(!i40e_page_is_reserved(page))) 1585 return true; 1586 1587 /* this page cannot be reused so discard it */ 1588 __free_pages(page, 0); 1589 return false; 1590 } 1591 1592 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 1593 rx_buffer->page_offset, size, truesize); 1594 1595 /* avoid re-using remote pages */ 1596 if (unlikely(i40e_page_is_reserved(page))) 1597 return false; 1598 1599 #if (PAGE_SIZE < 8192) 1600 /* if we are only owner of page we can reuse it */ 1601 if (unlikely(page_count(page) != 1)) 1602 return false; 1603 1604 /* flip page offset to other buffer */ 1605 rx_buffer->page_offset ^= truesize; 1606 #else 1607 /* move offset up to the next cache line */ 1608 rx_buffer->page_offset += truesize; 1609 1610 if (rx_buffer->page_offset > last_offset) 1611 return false; 1612 #endif 1613 1614 /* Even if we own the page, we are not allowed to use atomic_set() 1615 * This would break get_page_unless_zero() users. 1616 */ 1617 get_page(rx_buffer->page); 1618 1619 return true; 1620 } 1621 1622 /** 1623 * i40e_fetch_rx_buffer - Allocate skb and populate it 1624 * @rx_ring: rx descriptor ring to transact packets on 1625 * @rx_desc: descriptor containing info written by hardware 1626 * 1627 * This function allocates an skb on the fly, and populates it with the page 1628 * data from the current receive descriptor, taking care to set up the skb 1629 * correctly, as well as handling calling the page recycle function if 1630 * necessary. 1631 */ 1632 static inline 1633 struct sk_buff *i40e_fetch_rx_buffer(struct i40e_ring *rx_ring, 1634 union i40e_rx_desc *rx_desc) 1635 { 1636 struct i40e_rx_buffer *rx_buffer; 1637 struct sk_buff *skb; 1638 struct page *page; 1639 1640 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; 1641 page = rx_buffer->page; 1642 prefetchw(page); 1643 1644 skb = rx_buffer->skb; 1645 1646 if (likely(!skb)) { 1647 void *page_addr = page_address(page) + rx_buffer->page_offset; 1648 1649 /* prefetch first cache line of first page */ 1650 prefetch(page_addr); 1651 #if L1_CACHE_BYTES < 128 1652 prefetch(page_addr + L1_CACHE_BYTES); 1653 #endif 1654 1655 /* allocate a skb to store the frags */ 1656 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 1657 I40E_RX_HDR_SIZE, 1658 GFP_ATOMIC | __GFP_NOWARN); 1659 if (unlikely(!skb)) { 1660 rx_ring->rx_stats.alloc_buff_failed++; 1661 return NULL; 1662 } 1663 1664 /* we will be copying header into skb->data in 1665 * pskb_may_pull so it is in our interest to prefetch 1666 * it now to avoid a possible cache miss 1667 */ 1668 prefetchw(skb->data); 1669 } else { 1670 rx_buffer->skb = NULL; 1671 } 1672 1673 /* we are reusing so sync this buffer for CPU use */ 1674 dma_sync_single_range_for_cpu(rx_ring->dev, 1675 rx_buffer->dma, 1676 rx_buffer->page_offset, 1677 I40E_RXBUFFER_2048, 1678 DMA_FROM_DEVICE); 1679 1680 /* pull page into skb */ 1681 if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 1682 /* hand second half of page back to the ring */ 1683 i40e_reuse_rx_page(rx_ring, rx_buffer); 1684 rx_ring->rx_stats.page_reuse_count++; 1685 } else { 1686 /* we are not reusing the buffer so unmap it */ 1687 dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, 1688 DMA_FROM_DEVICE); 1689 } 1690 1691 /* clear contents of buffer_info */ 1692 rx_buffer->page = NULL; 1693 1694 return skb; 1695 } 1696 1697 /** 1698 * i40e_is_non_eop - process handling of non-EOP buffers 1699 * @rx_ring: Rx ring being processed 1700 * @rx_desc: Rx descriptor for current buffer 1701 * @skb: Current socket buffer containing buffer in progress 1702 * 1703 * This function updates next to clean. If the buffer is an EOP buffer 1704 * this function exits returning false, otherwise it will place the 1705 * sk_buff in the next buffer to be chained and return true indicating 1706 * that this is in fact a non-EOP buffer. 1707 **/ 1708 static bool i40e_is_non_eop(struct i40e_ring *rx_ring, 1709 union i40e_rx_desc *rx_desc, 1710 struct sk_buff *skb) 1711 { 1712 u32 ntc = rx_ring->next_to_clean + 1; 1713 1714 /* fetch, update, and store next to clean */ 1715 ntc = (ntc < rx_ring->count) ? ntc : 0; 1716 rx_ring->next_to_clean = ntc; 1717 1718 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1719 1720 #define staterrlen rx_desc->wb.qword1.status_error_len 1721 if (unlikely(i40e_rx_is_programming_status(le64_to_cpu(staterrlen)))) { 1722 i40e_clean_programming_status(rx_ring, rx_desc); 1723 rx_ring->rx_bi[ntc].skb = skb; 1724 return true; 1725 } 1726 /* if we are the last buffer then there is nothing else to do */ 1727 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 1728 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 1729 return false; 1730 1731 /* place skb in next buffer to be received */ 1732 rx_ring->rx_bi[ntc].skb = skb; 1733 rx_ring->rx_stats.non_eop_descs++; 1734 1735 return true; 1736 } 1737 1738 /** 1739 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1740 * @rx_ring: rx descriptor ring to transact packets on 1741 * @budget: Total limit on number of packets to process 1742 * 1743 * This function provides a "bounce buffer" approach to Rx interrupt 1744 * processing. The advantage to this is that on systems that have 1745 * expensive overhead for IOMMU access this provides a means of avoiding 1746 * it by maintaining the mapping of the page to the system. 1747 * 1748 * Returns amount of work completed 1749 **/ 1750 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) 1751 { 1752 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1753 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1754 bool failure = false; 1755 1756 while (likely(total_rx_packets < budget)) { 1757 union i40e_rx_desc *rx_desc; 1758 struct sk_buff *skb; 1759 u32 rx_status; 1760 u16 vlan_tag; 1761 u8 rx_ptype; 1762 u64 qword; 1763 1764 /* return some buffers to hardware, one at a time is too slow */ 1765 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1766 failure = failure || 1767 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 1768 cleaned_count = 0; 1769 } 1770 1771 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); 1772 1773 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1774 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1775 I40E_RXD_QW1_PTYPE_SHIFT; 1776 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1777 I40E_RXD_QW1_STATUS_SHIFT; 1778 1779 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) 1780 break; 1781 1782 /* status_error_len will always be zero for unused descriptors 1783 * because it's cleared in cleanup, and overlaps with hdr_addr 1784 * which is always zero because packet split isn't used, if the 1785 * hardware wrote DD then it will be non-zero 1786 */ 1787 if (!rx_desc->wb.qword1.status_error_len) 1788 break; 1789 1790 /* This memory barrier is needed to keep us from reading 1791 * any other fields out of the rx_desc until we know the 1792 * DD bit is set. 1793 */ 1794 dma_rmb(); 1795 1796 skb = i40e_fetch_rx_buffer(rx_ring, rx_desc); 1797 if (!skb) 1798 break; 1799 1800 cleaned_count++; 1801 1802 if (i40e_is_non_eop(rx_ring, rx_desc, skb)) 1803 continue; 1804 1805 /* ERR_MASK will only have valid bits if EOP set, and 1806 * what we are doing here is actually checking 1807 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 1808 * the error field 1809 */ 1810 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 1811 dev_kfree_skb_any(skb); 1812 continue; 1813 } 1814 1815 if (i40e_cleanup_headers(rx_ring, skb)) 1816 continue; 1817 1818 /* probably a little skewed due to removing CRC */ 1819 total_rx_bytes += skb->len; 1820 1821 /* populate checksum, VLAN, and protocol */ 1822 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 1823 1824 #ifdef I40E_FCOE 1825 if (unlikely( 1826 i40e_rx_is_fcoe(rx_ptype) && 1827 !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) { 1828 dev_kfree_skb_any(skb); 1829 continue; 1830 } 1831 #endif 1832 1833 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? 1834 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; 1835 1836 i40e_receive_skb(rx_ring, skb, vlan_tag); 1837 1838 /* update budget accounting */ 1839 total_rx_packets++; 1840 } 1841 1842 u64_stats_update_begin(&rx_ring->syncp); 1843 rx_ring->stats.packets += total_rx_packets; 1844 rx_ring->stats.bytes += total_rx_bytes; 1845 u64_stats_update_end(&rx_ring->syncp); 1846 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1847 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1848 1849 /* guarantee a trip back through this routine if there was a failure */ 1850 return failure ? budget : total_rx_packets; 1851 } 1852 1853 static u32 i40e_buildreg_itr(const int type, const u16 itr) 1854 { 1855 u32 val; 1856 1857 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1858 /* Don't clear PBA because that can cause lost interrupts that 1859 * came in while we were cleaning/polling 1860 */ 1861 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 1862 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 1863 1864 return val; 1865 } 1866 1867 /* a small macro to shorten up some long lines */ 1868 #define INTREG I40E_PFINT_DYN_CTLN 1869 1870 /** 1871 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 1872 * @vsi: the VSI we care about 1873 * @q_vector: q_vector for which itr is being updated and interrupt enabled 1874 * 1875 **/ 1876 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 1877 struct i40e_q_vector *q_vector) 1878 { 1879 struct i40e_hw *hw = &vsi->back->hw; 1880 bool rx = false, tx = false; 1881 u32 rxval, txval; 1882 int vector; 1883 int idx = q_vector->v_idx; 1884 1885 vector = (q_vector->v_idx + vsi->base_vector); 1886 1887 /* avoid dynamic calculation if in countdown mode OR if 1888 * all dynamic is disabled 1889 */ 1890 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); 1891 1892 if (q_vector->itr_countdown > 0 || 1893 (!ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting) && 1894 !ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting))) { 1895 goto enable_int; 1896 } 1897 1898 if (ITR_IS_DYNAMIC(vsi->rx_rings[idx]->rx_itr_setting)) { 1899 rx = i40e_set_new_dynamic_itr(&q_vector->rx); 1900 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); 1901 } 1902 1903 if (ITR_IS_DYNAMIC(vsi->tx_rings[idx]->tx_itr_setting)) { 1904 tx = i40e_set_new_dynamic_itr(&q_vector->tx); 1905 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); 1906 } 1907 1908 if (rx || tx) { 1909 /* get the higher of the two ITR adjustments and 1910 * use the same value for both ITR registers 1911 * when in adaptive mode (Rx and/or Tx) 1912 */ 1913 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); 1914 1915 q_vector->tx.itr = q_vector->rx.itr = itr; 1916 txval = i40e_buildreg_itr(I40E_TX_ITR, itr); 1917 tx = true; 1918 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); 1919 rx = true; 1920 } 1921 1922 /* only need to enable the interrupt once, but need 1923 * to possibly update both ITR values 1924 */ 1925 if (rx) { 1926 /* set the INTENA_MSK_MASK so that this first write 1927 * won't actually enable the interrupt, instead just 1928 * updating the ITR (it's bit 31 PF and VF) 1929 */ 1930 rxval |= BIT(31); 1931 /* don't check _DOWN because interrupt isn't being enabled */ 1932 wr32(hw, INTREG(vector - 1), rxval); 1933 } 1934 1935 enable_int: 1936 if (!test_bit(__I40E_DOWN, &vsi->state)) 1937 wr32(hw, INTREG(vector - 1), txval); 1938 1939 if (q_vector->itr_countdown) 1940 q_vector->itr_countdown--; 1941 else 1942 q_vector->itr_countdown = ITR_COUNTDOWN_START; 1943 } 1944 1945 /** 1946 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 1947 * @napi: napi struct with our devices info in it 1948 * @budget: amount of work driver is allowed to do this pass, in packets 1949 * 1950 * This function will clean all queues associated with a q_vector. 1951 * 1952 * Returns the amount of work done 1953 **/ 1954 int i40e_napi_poll(struct napi_struct *napi, int budget) 1955 { 1956 struct i40e_q_vector *q_vector = 1957 container_of(napi, struct i40e_q_vector, napi); 1958 struct i40e_vsi *vsi = q_vector->vsi; 1959 struct i40e_ring *ring; 1960 bool clean_complete = true; 1961 bool arm_wb = false; 1962 int budget_per_ring; 1963 int work_done = 0; 1964 1965 if (test_bit(__I40E_DOWN, &vsi->state)) { 1966 napi_complete(napi); 1967 return 0; 1968 } 1969 1970 /* Clear hung_detected bit */ 1971 clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected); 1972 /* Since the actual Tx work is minimal, we can give the Tx a larger 1973 * budget and be more aggressive about cleaning up the Tx descriptors. 1974 */ 1975 i40e_for_each_ring(ring, q_vector->tx) { 1976 if (!i40e_clean_tx_irq(vsi, ring, budget)) { 1977 clean_complete = false; 1978 continue; 1979 } 1980 arm_wb |= ring->arm_wb; 1981 ring->arm_wb = false; 1982 } 1983 1984 /* Handle case where we are called by netpoll with a budget of 0 */ 1985 if (budget <= 0) 1986 goto tx_only; 1987 1988 /* We attempt to distribute budget to each Rx queue fairly, but don't 1989 * allow the budget to go below 1 because that would exit polling early. 1990 */ 1991 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 1992 1993 i40e_for_each_ring(ring, q_vector->rx) { 1994 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); 1995 1996 work_done += cleaned; 1997 /* if we clean as many as budgeted, we must not be done */ 1998 if (cleaned >= budget_per_ring) 1999 clean_complete = false; 2000 } 2001 2002 /* If work not completed, return budget and polling will return */ 2003 if (!clean_complete) { 2004 tx_only: 2005 if (arm_wb) { 2006 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2007 i40e_enable_wb_on_itr(vsi, q_vector); 2008 } 2009 return budget; 2010 } 2011 2012 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) 2013 q_vector->arm_wb_state = false; 2014 2015 /* Work is done so exit the polling mode and re-enable the interrupt */ 2016 napi_complete_done(napi, work_done); 2017 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 2018 i40e_update_enable_itr(vsi, q_vector); 2019 } else { /* Legacy mode */ 2020 i40e_irq_dynamic_enable_icr0(vsi->back, false); 2021 } 2022 return 0; 2023 } 2024 2025 /** 2026 * i40e_atr - Add a Flow Director ATR filter 2027 * @tx_ring: ring to add programming descriptor to 2028 * @skb: send buffer 2029 * @tx_flags: send tx flags 2030 **/ 2031 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2032 u32 tx_flags) 2033 { 2034 struct i40e_filter_program_desc *fdir_desc; 2035 struct i40e_pf *pf = tx_ring->vsi->back; 2036 union { 2037 unsigned char *network; 2038 struct iphdr *ipv4; 2039 struct ipv6hdr *ipv6; 2040 } hdr; 2041 struct tcphdr *th; 2042 unsigned int hlen; 2043 u32 flex_ptype, dtype_cmd; 2044 int l4_proto; 2045 u16 i; 2046 2047 /* make sure ATR is enabled */ 2048 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 2049 return; 2050 2051 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 2052 return; 2053 2054 /* if sampling is disabled do nothing */ 2055 if (!tx_ring->atr_sample_rate) 2056 return; 2057 2058 /* Currently only IPv4/IPv6 with TCP is supported */ 2059 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2060 return; 2061 2062 /* snag network header to get L4 type and address */ 2063 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2064 skb_inner_network_header(skb) : skb_network_header(skb); 2065 2066 /* Note: tx_flags gets modified to reflect inner protocols in 2067 * tx_enable_csum function if encap is enabled. 2068 */ 2069 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2070 /* access ihl as u8 to avoid unaligned access on ia64 */ 2071 hlen = (hdr.network[0] & 0x0F) << 2; 2072 l4_proto = hdr.ipv4->protocol; 2073 } else { 2074 hlen = hdr.network - skb->data; 2075 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 2076 hlen -= hdr.network - skb->data; 2077 } 2078 2079 if (l4_proto != IPPROTO_TCP) 2080 return; 2081 2082 th = (struct tcphdr *)(hdr.network + hlen); 2083 2084 /* Due to lack of space, no more new filters can be programmed */ 2085 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 2086 return; 2087 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && 2088 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) { 2089 /* HW ATR eviction will take care of removing filters on FIN 2090 * and RST packets. 2091 */ 2092 if (th->fin || th->rst) 2093 return; 2094 } 2095 2096 tx_ring->atr_count++; 2097 2098 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2099 if (!th->fin && 2100 !th->syn && 2101 !th->rst && 2102 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2103 return; 2104 2105 tx_ring->atr_count = 0; 2106 2107 /* grab the next descriptor */ 2108 i = tx_ring->next_to_use; 2109 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2110 2111 i++; 2112 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2113 2114 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2115 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2116 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2117 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2118 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2119 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2120 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2121 2122 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2123 2124 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2125 2126 dtype_cmd |= (th->fin || th->rst) ? 2127 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2128 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2129 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2130 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2131 2132 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2133 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2134 2135 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2136 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2137 2138 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2139 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2140 dtype_cmd |= 2141 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2142 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2143 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2144 else 2145 dtype_cmd |= 2146 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2147 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2148 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2149 2150 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) && 2151 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) 2152 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2153 2154 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2155 fdir_desc->rsvd = cpu_to_le32(0); 2156 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2157 fdir_desc->fd_id = cpu_to_le32(0); 2158 } 2159 2160 /** 2161 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2162 * @skb: send buffer 2163 * @tx_ring: ring to send buffer on 2164 * @flags: the tx flags to be set 2165 * 2166 * Checks the skb and set up correspondingly several generic transmit flags 2167 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2168 * 2169 * Returns error code indicate the frame should be dropped upon error and the 2170 * otherwise returns 0 to indicate the flags has been set properly. 2171 **/ 2172 #ifdef I40E_FCOE 2173 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2174 struct i40e_ring *tx_ring, 2175 u32 *flags) 2176 #else 2177 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2178 struct i40e_ring *tx_ring, 2179 u32 *flags) 2180 #endif 2181 { 2182 __be16 protocol = skb->protocol; 2183 u32 tx_flags = 0; 2184 2185 if (protocol == htons(ETH_P_8021Q) && 2186 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 2187 /* When HW VLAN acceleration is turned off by the user the 2188 * stack sets the protocol to 8021q so that the driver 2189 * can take any steps required to support the SW only 2190 * VLAN handling. In our case the driver doesn't need 2191 * to take any further steps so just set the protocol 2192 * to the encapsulated ethertype. 2193 */ 2194 skb->protocol = vlan_get_protocol(skb); 2195 goto out; 2196 } 2197 2198 /* if we have a HW VLAN tag being added, default to the HW one */ 2199 if (skb_vlan_tag_present(skb)) { 2200 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 2201 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2202 /* else if it is a SW VLAN, check the next protocol and store the tag */ 2203 } else if (protocol == htons(ETH_P_8021Q)) { 2204 struct vlan_hdr *vhdr, _vhdr; 2205 2206 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 2207 if (!vhdr) 2208 return -EINVAL; 2209 2210 protocol = vhdr->h_vlan_encapsulated_proto; 2211 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 2212 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 2213 } 2214 2215 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 2216 goto out; 2217 2218 /* Insert 802.1p priority into VLAN header */ 2219 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 2220 (skb->priority != TC_PRIO_CONTROL)) { 2221 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 2222 tx_flags |= (skb->priority & 0x7) << 2223 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 2224 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 2225 struct vlan_ethhdr *vhdr; 2226 int rc; 2227 2228 rc = skb_cow_head(skb, 0); 2229 if (rc < 0) 2230 return rc; 2231 vhdr = (struct vlan_ethhdr *)skb->data; 2232 vhdr->h_vlan_TCI = htons(tx_flags >> 2233 I40E_TX_FLAGS_VLAN_SHIFT); 2234 } else { 2235 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2236 } 2237 } 2238 2239 out: 2240 *flags = tx_flags; 2241 return 0; 2242 } 2243 2244 /** 2245 * i40e_tso - set up the tso context descriptor 2246 * @skb: ptr to the skb we're sending 2247 * @hdr_len: ptr to the size of the packet header 2248 * @cd_type_cmd_tso_mss: Quad Word 1 2249 * 2250 * Returns 0 if no TSO can happen, 1 if tso is going, or error 2251 **/ 2252 static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss) 2253 { 2254 u64 cd_cmd, cd_tso_len, cd_mss; 2255 union { 2256 struct iphdr *v4; 2257 struct ipv6hdr *v6; 2258 unsigned char *hdr; 2259 } ip; 2260 union { 2261 struct tcphdr *tcp; 2262 struct udphdr *udp; 2263 unsigned char *hdr; 2264 } l4; 2265 u32 paylen, l4_offset; 2266 int err; 2267 2268 if (skb->ip_summed != CHECKSUM_PARTIAL) 2269 return 0; 2270 2271 if (!skb_is_gso(skb)) 2272 return 0; 2273 2274 err = skb_cow_head(skb, 0); 2275 if (err < 0) 2276 return err; 2277 2278 ip.hdr = skb_network_header(skb); 2279 l4.hdr = skb_transport_header(skb); 2280 2281 /* initialize outer IP header fields */ 2282 if (ip.v4->version == 4) { 2283 ip.v4->tot_len = 0; 2284 ip.v4->check = 0; 2285 } else { 2286 ip.v6->payload_len = 0; 2287 } 2288 2289 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 2290 SKB_GSO_GRE_CSUM | 2291 SKB_GSO_IPXIP4 | 2292 SKB_GSO_IPXIP6 | 2293 SKB_GSO_UDP_TUNNEL | 2294 SKB_GSO_UDP_TUNNEL_CSUM)) { 2295 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2296 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 2297 l4.udp->len = 0; 2298 2299 /* determine offset of outer transport header */ 2300 l4_offset = l4.hdr - skb->data; 2301 2302 /* remove payload length from outer checksum */ 2303 paylen = skb->len - l4_offset; 2304 csum_replace_by_diff(&l4.udp->check, htonl(paylen)); 2305 } 2306 2307 /* reset pointers to inner headers */ 2308 ip.hdr = skb_inner_network_header(skb); 2309 l4.hdr = skb_inner_transport_header(skb); 2310 2311 /* initialize inner IP header fields */ 2312 if (ip.v4->version == 4) { 2313 ip.v4->tot_len = 0; 2314 ip.v4->check = 0; 2315 } else { 2316 ip.v6->payload_len = 0; 2317 } 2318 } 2319 2320 /* determine offset of inner transport header */ 2321 l4_offset = l4.hdr - skb->data; 2322 2323 /* remove payload length from inner checksum */ 2324 paylen = skb->len - l4_offset; 2325 csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); 2326 2327 /* compute length of segmentation header */ 2328 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 2329 2330 /* find the field values */ 2331 cd_cmd = I40E_TX_CTX_DESC_TSO; 2332 cd_tso_len = skb->len - *hdr_len; 2333 cd_mss = skb_shinfo(skb)->gso_size; 2334 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 2335 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 2336 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 2337 return 1; 2338 } 2339 2340 /** 2341 * i40e_tsyn - set up the tsyn context descriptor 2342 * @tx_ring: ptr to the ring to send 2343 * @skb: ptr to the skb we're sending 2344 * @tx_flags: the collected send information 2345 * @cd_type_cmd_tso_mss: Quad Word 1 2346 * 2347 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 2348 **/ 2349 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 2350 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 2351 { 2352 struct i40e_pf *pf; 2353 2354 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2355 return 0; 2356 2357 /* Tx timestamps cannot be sampled when doing TSO */ 2358 if (tx_flags & I40E_TX_FLAGS_TSO) 2359 return 0; 2360 2361 /* only timestamp the outbound packet if the user has requested it and 2362 * we are not already transmitting a packet to be timestamped 2363 */ 2364 pf = i40e_netdev_to_pf(tx_ring->netdev); 2365 if (!(pf->flags & I40E_FLAG_PTP)) 2366 return 0; 2367 2368 if (pf->ptp_tx && 2369 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { 2370 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2371 pf->ptp_tx_skb = skb_get(skb); 2372 } else { 2373 return 0; 2374 } 2375 2376 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 2377 I40E_TXD_CTX_QW1_CMD_SHIFT; 2378 2379 return 1; 2380 } 2381 2382 /** 2383 * i40e_tx_enable_csum - Enable Tx checksum offloads 2384 * @skb: send buffer 2385 * @tx_flags: pointer to Tx flags currently set 2386 * @td_cmd: Tx descriptor command bits to set 2387 * @td_offset: Tx descriptor header offsets to set 2388 * @tx_ring: Tx descriptor ring 2389 * @cd_tunneling: ptr to context desc bits 2390 **/ 2391 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 2392 u32 *td_cmd, u32 *td_offset, 2393 struct i40e_ring *tx_ring, 2394 u32 *cd_tunneling) 2395 { 2396 union { 2397 struct iphdr *v4; 2398 struct ipv6hdr *v6; 2399 unsigned char *hdr; 2400 } ip; 2401 union { 2402 struct tcphdr *tcp; 2403 struct udphdr *udp; 2404 unsigned char *hdr; 2405 } l4; 2406 unsigned char *exthdr; 2407 u32 offset, cmd = 0; 2408 __be16 frag_off; 2409 u8 l4_proto = 0; 2410 2411 if (skb->ip_summed != CHECKSUM_PARTIAL) 2412 return 0; 2413 2414 ip.hdr = skb_network_header(skb); 2415 l4.hdr = skb_transport_header(skb); 2416 2417 /* compute outer L2 header size */ 2418 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2419 2420 if (skb->encapsulation) { 2421 u32 tunnel = 0; 2422 /* define outer network header type */ 2423 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2424 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2425 I40E_TX_CTX_EXT_IP_IPV4 : 2426 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 2427 2428 l4_proto = ip.v4->protocol; 2429 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2430 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 2431 2432 exthdr = ip.hdr + sizeof(*ip.v6); 2433 l4_proto = ip.v6->nexthdr; 2434 if (l4.hdr != exthdr) 2435 ipv6_skip_exthdr(skb, exthdr - skb->data, 2436 &l4_proto, &frag_off); 2437 } 2438 2439 /* define outer transport */ 2440 switch (l4_proto) { 2441 case IPPROTO_UDP: 2442 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 2443 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2444 break; 2445 case IPPROTO_GRE: 2446 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 2447 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2448 break; 2449 case IPPROTO_IPIP: 2450 case IPPROTO_IPV6: 2451 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2452 l4.hdr = skb_inner_network_header(skb); 2453 break; 2454 default: 2455 if (*tx_flags & I40E_TX_FLAGS_TSO) 2456 return -1; 2457 2458 skb_checksum_help(skb); 2459 return 0; 2460 } 2461 2462 /* compute outer L3 header size */ 2463 tunnel |= ((l4.hdr - ip.hdr) / 4) << 2464 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 2465 2466 /* switch IP header pointer from outer to inner header */ 2467 ip.hdr = skb_inner_network_header(skb); 2468 2469 /* compute tunnel header size */ 2470 tunnel |= ((ip.hdr - l4.hdr) / 2) << 2471 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2472 2473 /* indicate if we need to offload outer UDP header */ 2474 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 2475 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2476 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 2477 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 2478 2479 /* record tunnel offload values */ 2480 *cd_tunneling |= tunnel; 2481 2482 /* switch L4 header pointer from outer to inner */ 2483 l4.hdr = skb_inner_transport_header(skb); 2484 l4_proto = 0; 2485 2486 /* reset type as we transition from outer to inner headers */ 2487 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 2488 if (ip.v4->version == 4) 2489 *tx_flags |= I40E_TX_FLAGS_IPV4; 2490 if (ip.v6->version == 6) 2491 *tx_flags |= I40E_TX_FLAGS_IPV6; 2492 } 2493 2494 /* Enable IP checksum offloads */ 2495 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2496 l4_proto = ip.v4->protocol; 2497 /* the stack computes the IP header already, the only time we 2498 * need the hardware to recompute it is in the case of TSO. 2499 */ 2500 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2501 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 2502 I40E_TX_DESC_CMD_IIPT_IPV4; 2503 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2504 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2505 2506 exthdr = ip.hdr + sizeof(*ip.v6); 2507 l4_proto = ip.v6->nexthdr; 2508 if (l4.hdr != exthdr) 2509 ipv6_skip_exthdr(skb, exthdr - skb->data, 2510 &l4_proto, &frag_off); 2511 } 2512 2513 /* compute inner L3 header size */ 2514 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2515 2516 /* Enable L4 checksum offloads */ 2517 switch (l4_proto) { 2518 case IPPROTO_TCP: 2519 /* enable checksum offloads */ 2520 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2521 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2522 break; 2523 case IPPROTO_SCTP: 2524 /* enable SCTP checksum offload */ 2525 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2526 offset |= (sizeof(struct sctphdr) >> 2) << 2527 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2528 break; 2529 case IPPROTO_UDP: 2530 /* enable UDP checksum offload */ 2531 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2532 offset |= (sizeof(struct udphdr) >> 2) << 2533 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2534 break; 2535 default: 2536 if (*tx_flags & I40E_TX_FLAGS_TSO) 2537 return -1; 2538 skb_checksum_help(skb); 2539 return 0; 2540 } 2541 2542 *td_cmd |= cmd; 2543 *td_offset |= offset; 2544 2545 return 1; 2546 } 2547 2548 /** 2549 * i40e_create_tx_ctx Build the Tx context descriptor 2550 * @tx_ring: ring to create the descriptor on 2551 * @cd_type_cmd_tso_mss: Quad Word 1 2552 * @cd_tunneling: Quad Word 0 - bits 0-31 2553 * @cd_l2tag2: Quad Word 0 - bits 32-63 2554 **/ 2555 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2556 const u64 cd_type_cmd_tso_mss, 2557 const u32 cd_tunneling, const u32 cd_l2tag2) 2558 { 2559 struct i40e_tx_context_desc *context_desc; 2560 int i = tx_ring->next_to_use; 2561 2562 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2563 !cd_tunneling && !cd_l2tag2) 2564 return; 2565 2566 /* grab the next descriptor */ 2567 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2568 2569 i++; 2570 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2571 2572 /* cpu_to_le32 and assign to struct fields */ 2573 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2574 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2575 context_desc->rsvd = cpu_to_le16(0); 2576 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2577 } 2578 2579 /** 2580 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2581 * @tx_ring: the ring to be checked 2582 * @size: the size buffer we want to assure is available 2583 * 2584 * Returns -EBUSY if a stop is needed, else 0 2585 **/ 2586 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2587 { 2588 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2589 /* Memory barrier before checking head and tail */ 2590 smp_mb(); 2591 2592 /* Check again in a case another CPU has just made room available. */ 2593 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 2594 return -EBUSY; 2595 2596 /* A reprieve! - use start_queue because it doesn't call schedule */ 2597 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2598 ++tx_ring->tx_stats.restart_queue; 2599 return 0; 2600 } 2601 2602 /** 2603 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 2604 * @skb: send buffer 2605 * 2606 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 2607 * and so we need to figure out the cases where we need to linearize the skb. 2608 * 2609 * For TSO we need to count the TSO header and segment payload separately. 2610 * As such we need to check cases where we have 7 fragments or more as we 2611 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 2612 * the segment payload in the first descriptor, and another 7 for the 2613 * fragments. 2614 **/ 2615 bool __i40e_chk_linearize(struct sk_buff *skb) 2616 { 2617 const struct skb_frag_struct *frag, *stale; 2618 int nr_frags, sum; 2619 2620 /* no need to check if number of frags is less than 7 */ 2621 nr_frags = skb_shinfo(skb)->nr_frags; 2622 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 2623 return false; 2624 2625 /* We need to walk through the list and validate that each group 2626 * of 6 fragments totals at least gso_size. However we don't need 2627 * to perform such validation on the last 6 since the last 6 cannot 2628 * inherit any data from a descriptor after them. 2629 */ 2630 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 2631 frag = &skb_shinfo(skb)->frags[0]; 2632 2633 /* Initialize size to the negative value of gso_size minus 1. We 2634 * use this as the worst case scenerio in which the frag ahead 2635 * of us only provides one byte which is why we are limited to 6 2636 * descriptors for a single transmit as the header and previous 2637 * fragment are already consuming 2 descriptors. 2638 */ 2639 sum = 1 - skb_shinfo(skb)->gso_size; 2640 2641 /* Add size of frags 0 through 4 to create our initial sum */ 2642 sum += skb_frag_size(frag++); 2643 sum += skb_frag_size(frag++); 2644 sum += skb_frag_size(frag++); 2645 sum += skb_frag_size(frag++); 2646 sum += skb_frag_size(frag++); 2647 2648 /* Walk through fragments adding latest fragment, testing it, and 2649 * then removing stale fragments from the sum. 2650 */ 2651 stale = &skb_shinfo(skb)->frags[0]; 2652 for (;;) { 2653 sum += skb_frag_size(frag++); 2654 2655 /* if sum is negative we failed to make sufficient progress */ 2656 if (sum < 0) 2657 return true; 2658 2659 /* use pre-decrement to avoid processing last fragment */ 2660 if (!--nr_frags) 2661 break; 2662 2663 sum -= skb_frag_size(stale++); 2664 } 2665 2666 return false; 2667 } 2668 2669 /** 2670 * i40e_tx_map - Build the Tx descriptor 2671 * @tx_ring: ring to send buffer on 2672 * @skb: send buffer 2673 * @first: first buffer info buffer to use 2674 * @tx_flags: collected send information 2675 * @hdr_len: size of the packet header 2676 * @td_cmd: the command field in the descriptor 2677 * @td_offset: offset for checksum or crc 2678 **/ 2679 #ifdef I40E_FCOE 2680 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2681 struct i40e_tx_buffer *first, u32 tx_flags, 2682 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2683 #else 2684 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2685 struct i40e_tx_buffer *first, u32 tx_flags, 2686 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2687 #endif 2688 { 2689 unsigned int data_len = skb->data_len; 2690 unsigned int size = skb_headlen(skb); 2691 struct skb_frag_struct *frag; 2692 struct i40e_tx_buffer *tx_bi; 2693 struct i40e_tx_desc *tx_desc; 2694 u16 i = tx_ring->next_to_use; 2695 u32 td_tag = 0; 2696 dma_addr_t dma; 2697 u16 gso_segs; 2698 u16 desc_count = 0; 2699 bool tail_bump = true; 2700 bool do_rs = false; 2701 2702 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 2703 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 2704 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 2705 I40E_TX_FLAGS_VLAN_SHIFT; 2706 } 2707 2708 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) 2709 gso_segs = skb_shinfo(skb)->gso_segs; 2710 else 2711 gso_segs = 1; 2712 2713 /* multiply data chunks by size of headers */ 2714 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); 2715 first->gso_segs = gso_segs; 2716 first->skb = skb; 2717 first->tx_flags = tx_flags; 2718 2719 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2720 2721 tx_desc = I40E_TX_DESC(tx_ring, i); 2722 tx_bi = first; 2723 2724 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2725 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2726 2727 if (dma_mapping_error(tx_ring->dev, dma)) 2728 goto dma_error; 2729 2730 /* record length, and DMA address */ 2731 dma_unmap_len_set(tx_bi, len, size); 2732 dma_unmap_addr_set(tx_bi, dma, dma); 2733 2734 /* align size to end of page */ 2735 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 2736 tx_desc->buffer_addr = cpu_to_le64(dma); 2737 2738 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 2739 tx_desc->cmd_type_offset_bsz = 2740 build_ctob(td_cmd, td_offset, 2741 max_data, td_tag); 2742 2743 tx_desc++; 2744 i++; 2745 desc_count++; 2746 2747 if (i == tx_ring->count) { 2748 tx_desc = I40E_TX_DESC(tx_ring, 0); 2749 i = 0; 2750 } 2751 2752 dma += max_data; 2753 size -= max_data; 2754 2755 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2756 tx_desc->buffer_addr = cpu_to_le64(dma); 2757 } 2758 2759 if (likely(!data_len)) 2760 break; 2761 2762 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 2763 size, td_tag); 2764 2765 tx_desc++; 2766 i++; 2767 desc_count++; 2768 2769 if (i == tx_ring->count) { 2770 tx_desc = I40E_TX_DESC(tx_ring, 0); 2771 i = 0; 2772 } 2773 2774 size = skb_frag_size(frag); 2775 data_len -= size; 2776 2777 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 2778 DMA_TO_DEVICE); 2779 2780 tx_bi = &tx_ring->tx_bi[i]; 2781 } 2782 2783 /* set next_to_watch value indicating a packet is present */ 2784 first->next_to_watch = tx_desc; 2785 2786 i++; 2787 if (i == tx_ring->count) 2788 i = 0; 2789 2790 tx_ring->next_to_use = i; 2791 2792 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, 2793 tx_ring->queue_index), 2794 first->bytecount); 2795 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 2796 2797 /* Algorithm to optimize tail and RS bit setting: 2798 * if xmit_more is supported 2799 * if xmit_more is true 2800 * do not update tail and do not mark RS bit. 2801 * if xmit_more is false and last xmit_more was false 2802 * if every packet spanned less than 4 desc 2803 * then set RS bit on 4th packet and update tail 2804 * on every packet 2805 * else 2806 * update tail and set RS bit on every packet. 2807 * if xmit_more is false and last_xmit_more was true 2808 * update tail and set RS bit. 2809 * 2810 * Optimization: wmb to be issued only in case of tail update. 2811 * Also optimize the Descriptor WB path for RS bit with the same 2812 * algorithm. 2813 * 2814 * Note: If there are less than 4 packets 2815 * pending and interrupts were disabled the service task will 2816 * trigger a force WB. 2817 */ 2818 if (skb->xmit_more && 2819 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2820 tx_ring->queue_index))) { 2821 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; 2822 tail_bump = false; 2823 } else if (!skb->xmit_more && 2824 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2825 tx_ring->queue_index)) && 2826 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) && 2827 (tx_ring->packet_stride < WB_STRIDE) && 2828 (desc_count < WB_STRIDE)) { 2829 tx_ring->packet_stride++; 2830 } else { 2831 tx_ring->packet_stride = 0; 2832 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET; 2833 do_rs = true; 2834 } 2835 if (do_rs) 2836 tx_ring->packet_stride = 0; 2837 2838 tx_desc->cmd_type_offset_bsz = 2839 build_ctob(td_cmd, td_offset, size, td_tag) | 2840 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD : 2841 I40E_TX_DESC_CMD_EOP) << 2842 I40E_TXD_QW1_CMD_SHIFT); 2843 2844 /* notify HW of packet */ 2845 if (!tail_bump) 2846 prefetchw(tx_desc + 1); 2847 2848 if (tail_bump) { 2849 /* Force memory writes to complete before letting h/w 2850 * know there are new descriptors to fetch. (Only 2851 * applicable for weak-ordered memory model archs, 2852 * such as IA-64). 2853 */ 2854 wmb(); 2855 writel(i, tx_ring->tail); 2856 } 2857 2858 return; 2859 2860 dma_error: 2861 dev_info(tx_ring->dev, "TX DMA map failed\n"); 2862 2863 /* clear dma mappings for failed tx_bi map */ 2864 for (;;) { 2865 tx_bi = &tx_ring->tx_bi[i]; 2866 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 2867 if (tx_bi == first) 2868 break; 2869 if (i == 0) 2870 i = tx_ring->count; 2871 i--; 2872 } 2873 2874 tx_ring->next_to_use = i; 2875 } 2876 2877 /** 2878 * i40e_xmit_frame_ring - Sends buffer on Tx ring 2879 * @skb: send buffer 2880 * @tx_ring: ring to send buffer on 2881 * 2882 * Returns NETDEV_TX_OK if sent, else an error code 2883 **/ 2884 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 2885 struct i40e_ring *tx_ring) 2886 { 2887 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 2888 u32 cd_tunneling = 0, cd_l2tag2 = 0; 2889 struct i40e_tx_buffer *first; 2890 u32 td_offset = 0; 2891 u32 tx_flags = 0; 2892 __be16 protocol; 2893 u32 td_cmd = 0; 2894 u8 hdr_len = 0; 2895 int tso, count; 2896 int tsyn; 2897 2898 /* prefetch the data, we'll need it later */ 2899 prefetch(skb->data); 2900 2901 count = i40e_xmit_descriptor_count(skb); 2902 if (i40e_chk_linearize(skb, count)) { 2903 if (__skb_linearize(skb)) 2904 goto out_drop; 2905 count = i40e_txd_use_count(skb->len); 2906 tx_ring->tx_stats.tx_linearize++; 2907 } 2908 2909 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 2910 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 2911 * + 4 desc gap to avoid the cache line where head is, 2912 * + 1 desc for context descriptor, 2913 * otherwise try next time 2914 */ 2915 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 2916 tx_ring->tx_stats.tx_busy++; 2917 return NETDEV_TX_BUSY; 2918 } 2919 2920 /* prepare the xmit flags */ 2921 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 2922 goto out_drop; 2923 2924 /* obtain protocol of skb */ 2925 protocol = vlan_get_protocol(skb); 2926 2927 /* record the location of the first descriptor for this packet */ 2928 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 2929 2930 /* setup IPv4/IPv6 offloads */ 2931 if (protocol == htons(ETH_P_IP)) 2932 tx_flags |= I40E_TX_FLAGS_IPV4; 2933 else if (protocol == htons(ETH_P_IPV6)) 2934 tx_flags |= I40E_TX_FLAGS_IPV6; 2935 2936 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss); 2937 2938 if (tso < 0) 2939 goto out_drop; 2940 else if (tso) 2941 tx_flags |= I40E_TX_FLAGS_TSO; 2942 2943 /* Always offload the checksum, since it's in the data descriptor */ 2944 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 2945 tx_ring, &cd_tunneling); 2946 if (tso < 0) 2947 goto out_drop; 2948 2949 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 2950 2951 if (tsyn) 2952 tx_flags |= I40E_TX_FLAGS_TSYN; 2953 2954 skb_tx_timestamp(skb); 2955 2956 /* always enable CRC insertion offload */ 2957 td_cmd |= I40E_TX_DESC_CMD_ICRC; 2958 2959 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 2960 cd_tunneling, cd_l2tag2); 2961 2962 /* Add Flow Director ATR if it's enabled. 2963 * 2964 * NOTE: this must always be directly before the data descriptor. 2965 */ 2966 i40e_atr(tx_ring, skb, tx_flags); 2967 2968 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 2969 td_cmd, td_offset); 2970 2971 return NETDEV_TX_OK; 2972 2973 out_drop: 2974 dev_kfree_skb_any(skb); 2975 return NETDEV_TX_OK; 2976 } 2977 2978 /** 2979 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 2980 * @skb: send buffer 2981 * @netdev: network interface device structure 2982 * 2983 * Returns NETDEV_TX_OK if sent, else an error code 2984 **/ 2985 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2986 { 2987 struct i40e_netdev_priv *np = netdev_priv(netdev); 2988 struct i40e_vsi *vsi = np->vsi; 2989 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 2990 2991 /* hardware can't handle really short frames, hardware padding works 2992 * beyond this point 2993 */ 2994 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 2995 return NETDEV_TX_OK; 2996 2997 return i40e_xmit_frame_ring(skb, tx_ring); 2998 } 2999