1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 251dce24bSJeff Kirsher /* Copyright(c) 2013 - 2018 Intel Corporation. */ 356a62fc8SJesse Brandeburg 456a62fc8SJesse Brandeburg #ifndef _I40E_REGISTER_H_ 556a62fc8SJesse Brandeburg #define _I40E_REGISTER_H_ 656a62fc8SJesse Brandeburg 74c33f83aSAnjali Singhai Jain #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 84c33f83aSAnjali Singhai Jain #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 94c33f83aSAnjali Singhai Jain #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 104c33f83aSAnjali Singhai Jain #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 114c33f83aSAnjali Singhai Jain #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 1256a62fc8SJesse Brandeburg #define I40E_PF_ARQH_ARQH_SHIFT 0 134c33f83aSAnjali Singhai Jain #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 144c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 1556a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 164c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 1756a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 184c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 1956a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 204c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 2156a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 22fb598262SBeilei Xing #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 234c33f83aSAnjali Singhai Jain #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 244c33f83aSAnjali Singhai Jain #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 254c33f83aSAnjali Singhai Jain #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 264c33f83aSAnjali Singhai Jain #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 274c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 2856a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 294c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 3056a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 314c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 3256a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 334c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 3456a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 35fb598262SBeilei Xing #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 364c33f83aSAnjali Singhai Jain #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 374c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 3856a62fc8SJesse Brandeburg #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 394c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 404c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 4156a62fc8SJesse Brandeburg #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 424c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 434c33f83aSAnjali Singhai Jain #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 4456a62fc8SJesse Brandeburg #define I40E_GL_FWSTS_FWS1B_SHIFT 16 454c33f83aSAnjali Singhai Jain #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 46fffeeddfSPiotr Kwapulinski #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 47fffeeddfSPiotr Kwapulinski #define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 48d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 49d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 50d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 51d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 52d4256c8eSAdrian Podlawski #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 53d4256c8eSAdrian Podlawski #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) 544c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 5556a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 5656a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 574c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 5856a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 594c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 6056a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 614c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 6256a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 6356a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 644c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 654c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 664c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 6756a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 6856a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 6956a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 7056a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 7156a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 7256a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 734c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 7456a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 75fb598262SBeilei Xing #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 764c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 7756a62fc8SJesse Brandeburg #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 7856a62fc8SJesse Brandeburg #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 794c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 804c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 8156a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 824c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 8356a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 844c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 854c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 8656a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 874c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 884c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 8956a62fc8SJesse Brandeburg #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 904c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 9156a62fc8SJesse Brandeburg #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 924c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 934c33f83aSAnjali Singhai Jain #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 944c33f83aSAnjali Singhai Jain #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 954c33f83aSAnjali Singhai Jain #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 964c33f83aSAnjali Singhai Jain #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 9756a62fc8SJesse Brandeburg #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 984c33f83aSAnjali Singhai Jain #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 994c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 10056a62fc8SJesse Brandeburg #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 1014c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 1024c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 10356a62fc8SJesse Brandeburg #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 1044c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 1054c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 1064c33f83aSAnjali Singhai Jain #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1074c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 10856a62fc8SJesse Brandeburg #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 1094c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 1104c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 11156a62fc8SJesse Brandeburg #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 1124c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 1134c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 11456a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 1154c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 1164c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1174c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 1184c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 11956a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 1204c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 1214c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1224c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 12356a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 1244c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 1254c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 1264c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 1274c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 1284c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 12956a62fc8SJesse Brandeburg #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 1304c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 1314c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1324c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 1334c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 13456a62fc8SJesse Brandeburg #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 1354c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 1364c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 1374c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 1384c33f83aSAnjali Singhai Jain #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 1394c33f83aSAnjali Singhai Jain #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 1404c33f83aSAnjali Singhai Jain #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 14156a62fc8SJesse Brandeburg #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 14256a62fc8SJesse Brandeburg #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 1434c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 14456a62fc8SJesse Brandeburg #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 1454c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 1464c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 14756a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 14856a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 14956a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 1504c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 15156a62fc8SJesse Brandeburg #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 1524c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 1534c33f83aSAnjali Singhai Jain #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 15456a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 15556a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 15656a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 1574c33f83aSAnjali Singhai Jain #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 1584c33f83aSAnjali Singhai Jain #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 15956a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 16056a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 16156a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 16256a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 1634c33f83aSAnjali Singhai Jain #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 164b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 165b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 166b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 1674c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 16856a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 1694c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 17056a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 1714c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 17256a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 1734c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 17456a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 1754c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 17656a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 1774c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 17856a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 1794c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 18056a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 1814c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 1824c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 18356a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 1844c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 18556a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 1864c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 18756a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 1884c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 18956a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 1904c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 19156a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 19256a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 1934c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 1944c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 19556a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 1964c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 19756a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 1984c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 19956a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 2004c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 20156a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 2024c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 20356a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_GRST_SHIFT 20 2044c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 20556a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 2064c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 20756a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 2084c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 20956a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 2104c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 21156a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 2124c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 21356a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_VFLR_SHIFT 29 2144c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT) 21556a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 2164c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT) 21756a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_SWINT_SHIFT 31 2184c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT) 2194c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 22056a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 2214c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 22256a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 2234c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 22456a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 2254c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT) 22656a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 2274c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 22856a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 2294c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 23056a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 2314c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 23256a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 2334c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 23456a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 2354c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 23656a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 2374c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 23856a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 2394c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 2404c33f83aSAnjali Singhai Jain #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 2414c33f83aSAnjali Singhai Jain #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 2424c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 24356a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 2444c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 24556a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 2464c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 24756a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 2484c33f83aSAnjali Singhai Jain #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 2495098850cSAnjali Singhai Jain #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 2504c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 25156a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 2524c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 25356a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 2544c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) 25556a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 2564c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 25756a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 2584c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 25956a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 26056a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 2614c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 26256a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 2634c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 2644c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 26556a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 2664c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 26756a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 2684c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT) 26956a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 2704c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 27156a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 2724c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 27356a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 27456a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 2754c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 27656a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 2774c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 2784c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2794c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 28056a62fc8SJesse Brandeburg #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 2814c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 2824c33f83aSAnjali Singhai Jain #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 28356a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 28456a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 28556a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 2864c33f83aSAnjali Singhai Jain #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 2874c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 28856a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 28956a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 29056a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 2914c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 29256a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 2934c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 29456a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 2954c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 2964c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 29756a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 2984c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 2994c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 30056a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 3014c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 30256a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 3034c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 3044c33f83aSAnjali Singhai Jain #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 30556a62fc8SJesse Brandeburg #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 3064c33f83aSAnjali Singhai Jain #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 3074c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 3084c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 3094c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 3104c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 311351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 3124c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 313351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 3144c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 315351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 316fb598262SBeilei Xing #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 3174c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 31856a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 3194c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 32056a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 3214c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 32256a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 323fb598262SBeilei Xing #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) 3244c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 32556a62fc8SJesse Brandeburg #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 3264c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 32756a62fc8SJesse Brandeburg #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 3284c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 3294c33f83aSAnjali Singhai Jain #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 3304c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 33156a62fc8SJesse Brandeburg #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 3324c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 33356a62fc8SJesse Brandeburg #define I40E_QTX_CTL_PF_INDX_SHIFT 2 3344c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT) 33556a62fc8SJesse Brandeburg #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 3364c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 3374c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 33856a62fc8SJesse Brandeburg #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 3394c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 34056a62fc8SJesse Brandeburg #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 3414c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 3424c33f83aSAnjali Singhai Jain #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 3434c33f83aSAnjali Singhai Jain #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 3444c33f83aSAnjali Singhai Jain #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 34556a62fc8SJesse Brandeburg #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 3464c33f83aSAnjali Singhai Jain #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 3474c33f83aSAnjali Singhai Jain #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 34856a62fc8SJesse Brandeburg #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 3494c33f83aSAnjali Singhai Jain #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 3504c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 35156a62fc8SJesse Brandeburg #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 3524c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 3534c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 3544c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 35556a62fc8SJesse Brandeburg #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 3564c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) 35756a62fc8SJesse Brandeburg #define I40E_PRTGL_SAH_MFS_SHIFT 16 3584c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT) 3594c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 36056a62fc8SJesse Brandeburg #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 3614c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 3624c33f83aSAnjali Singhai Jain #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 36356a62fc8SJesse Brandeburg #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 3644c33f83aSAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 3654c33f83aSAnjali Singhai Jain #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 36656a62fc8SJesse Brandeburg #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 3674c33f83aSAnjali Singhai Jain #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 3684c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 36956a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 37056a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_START_SHIFT 30 37156a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 372fb598262SBeilei Xing #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) 3734c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 37456a62fc8SJesse Brandeburg #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 3754c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 3764c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 37742794bd8SShannon Nelson #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 3784c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 37942794bd8SShannon Nelson #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 3804c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 3814c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 38256a62fc8SJesse Brandeburg #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 3834c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 3844c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 38556a62fc8SJesse Brandeburg #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 3864c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 38756a62fc8SJesse Brandeburg #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 3884c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 3894c33f83aSAnjali Singhai Jain #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 39056a62fc8SJesse Brandeburg #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 3914c33f83aSAnjali Singhai Jain #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 3924c33f83aSAnjali Singhai Jain #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 3934c33f83aSAnjali Singhai Jain #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 39456a62fc8SJesse Brandeburg #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 3954c33f83aSAnjali Singhai Jain #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 3964c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 39756a62fc8SJesse Brandeburg #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 3984c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 39956a62fc8SJesse Brandeburg #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 4004c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 4014c33f83aSAnjali Singhai Jain #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 4024c33f83aSAnjali Singhai Jain #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 4034c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 40456a62fc8SJesse Brandeburg #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 4054c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 40656a62fc8SJesse Brandeburg #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 4074c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 4084c33f83aSAnjali Singhai Jain #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 4094c33f83aSAnjali Singhai Jain #define I40E_GLQF_HKEY_MAX_INDEX 12 4104c33f83aSAnjali Singhai Jain #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 4114c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 41256a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 4134c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 41456a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 4154c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 41656a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 4174c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 41856a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 4194c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 42056a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 4214c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 42256a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 4234c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT) 42456a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 4254c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 42656a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 4274c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 4284c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 42956a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 4304c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 4314c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 43256a62fc8SJesse Brandeburg #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 4334c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 43456a62fc8SJesse Brandeburg #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 4354c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 4364c33f83aSAnjali Singhai Jain #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 4374c33f83aSAnjali Singhai Jain #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 43856a62fc8SJesse Brandeburg #define I40E_PFQF_HKEY_MAX_INDEX 12 4394c33f83aSAnjali Singhai Jain #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 44056a62fc8SJesse Brandeburg #define I40E_PFQF_HLUT_MAX_INDEX 127 441fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 442fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 443fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 444fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 445fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 446fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 447fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 448fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 4494c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 45056a62fc8SJesse Brandeburg #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 4514c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 4525807822fSAnjali Singhai jain #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 4534c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 45456a62fc8SJesse Brandeburg #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 4554c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 4564c33f83aSAnjali Singhai Jain #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 4574c33f83aSAnjali Singhai Jain #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 45856a62fc8SJesse Brandeburg #define I40E_VFQF_HKEY1_MAX_INDEX 12 4594c33f83aSAnjali Singhai Jain #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 46056a62fc8SJesse Brandeburg #define I40E_VFQF_HLUT1_MAX_INDEX 15 4614c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4624c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4634c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4644c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4654c33f83aSAnjali Singhai Jain #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4664c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4674c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4684c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4694c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4704c33f83aSAnjali Singhai Jain #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4714c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4724c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4734c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4744c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4754c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4764c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4774c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4784c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4794c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4804c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4814c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4824c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4834c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4844c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4854c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4864c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4874c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4884c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4894c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4904c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4914c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4924c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4934c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4944c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4954c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4964c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4974c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4984c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 4994c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5004c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5014c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5024c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5034c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5044c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5054c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5064c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5074c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5084c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5094c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 5104c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 5114c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 5124c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 5134c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5144c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5154c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5164c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5174c33f83aSAnjali Singhai Jain #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5184c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5194c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 5204c33f83aSAnjali Singhai Jain #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5214c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5224c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5234c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5244c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 5254c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5264c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5274c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5284c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5294c33f83aSAnjali Singhai Jain #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5304c33f83aSAnjali Singhai Jain #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5314c33f83aSAnjali Singhai Jain #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5324c33f83aSAnjali Singhai Jain #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5334c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5344c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5354c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5364c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5374c33f83aSAnjali Singhai Jain #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5384c33f83aSAnjali Singhai Jain #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5394c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5404c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5414c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5424c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 5434c33f83aSAnjali Singhai Jain #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5444c33f83aSAnjali Singhai Jain #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5454c33f83aSAnjali Singhai Jain #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5464c33f83aSAnjali Singhai Jain #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5474c33f83aSAnjali Singhai Jain #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5484c33f83aSAnjali Singhai Jain #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5494c33f83aSAnjali Singhai Jain #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5504c33f83aSAnjali Singhai Jain #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5514c33f83aSAnjali Singhai Jain #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5524c33f83aSAnjali Singhai Jain #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5534c33f83aSAnjali Singhai Jain #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5544c33f83aSAnjali Singhai Jain #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5554c33f83aSAnjali Singhai Jain #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5564c33f83aSAnjali Singhai Jain #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5570a0d9af5SMitch Williams #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5584c33f83aSAnjali Singhai Jain #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5594c33f83aSAnjali Singhai Jain #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5604c33f83aSAnjali Singhai Jain #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5614c33f83aSAnjali Singhai Jain #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 5624c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5634c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5644c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5654c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5664c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5674c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5684c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5694c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 5704c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 57156a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 5724c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 57356a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 5744c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 57556a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 5764c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 5774c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 57856a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 5794c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 58056a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 5814c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 58256a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 58356a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 5844c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 58556a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 5864c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 5874c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 5884c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 5894c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 5904c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 5914c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 59256a62fc8SJesse Brandeburg #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 5934c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 5944c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 5954c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 5964c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 5974c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 5984c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 5994c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 60056a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 6014c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 60256a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_EVENT_SHIFT 8 6034c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 60456a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_QUEUE_SHIFT 17 6054c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 60656a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_VALID_SHIFT 31 6074c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT) 6084c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 6094c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_QUEUE_SHIFT 0 6104c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT) 6114c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VF_NUM_SHIFT 12 6124c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT) 6134c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_PF_NUM_SHIFT 21 6144c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT) 6154c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_EVENT_SHIFT 25 6164c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT) 61756a62fc8SJesse Brandeburg #define I40E_GL_MDET_TX_VALID_SHIFT 31 6184c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT) 6194c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 62056a62fc8SJesse Brandeburg #define I40E_PF_MDET_RX_VALID_SHIFT 0 6214c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT) 6224c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 62356a62fc8SJesse Brandeburg #define I40E_PF_MDET_TX_VALID_SHIFT 0 6244c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 6254c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 62656a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 6274c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 62856a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 6294c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 63056a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 631fb598262SBeilei Xing #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) 6324c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 63356a62fc8SJesse Brandeburg #define I40E_VP_MDET_RX_VALID_SHIFT 0 6344c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 6354c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 63656a62fc8SJesse Brandeburg #define I40E_VP_MDET_TX_VALID_SHIFT 0 6374c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 6384c33f83aSAnjali Singhai Jain #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 63956a62fc8SJesse Brandeburg #define I40E_PFPM_APM_APME_SHIFT 0 6404c33f83aSAnjali Singhai Jain #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 6414c33f83aSAnjali Singhai Jain #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 64256a62fc8SJesse Brandeburg #define I40E_PFPM_WUFC_MAG_SHIFT 1 6434c33f83aSAnjali Singhai Jain #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 6444c33f83aSAnjali Singhai Jain #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 6454c33f83aSAnjali Singhai Jain #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 6464c33f83aSAnjali Singhai Jain #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 6474c33f83aSAnjali Singhai Jain #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 6484c33f83aSAnjali Singhai Jain #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 6494c33f83aSAnjali Singhai Jain #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 6504c33f83aSAnjali Singhai Jain #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 6514c33f83aSAnjali Singhai Jain #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 6524c33f83aSAnjali Singhai Jain #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 6534c33f83aSAnjali Singhai Jain #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 65456a62fc8SJesse Brandeburg #define I40E_VFQF_HLUT_MAX_INDEX 15 655da48c9a2SAnjali Singhai Jain 656da48c9a2SAnjali Singhai Jain 657da48c9a2SAnjali Singhai Jain 658da48c9a2SAnjali Singhai Jain 659da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 660da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 661da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 662da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 663da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 664da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 665da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 666da48c9a2SAnjali Singhai Jain 667da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 668da48c9a2SAnjali Singhai Jain 669da48c9a2SAnjali Singhai Jain 670da48c9a2SAnjali Singhai Jain 671fe726082SAnjali Singhai Jain #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 672fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 673fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 674fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 675fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 676fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 677fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 678fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 679da48c9a2SAnjali Singhai Jain #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 680da48c9a2SAnjali Singhai Jain /* Redefined for X722 family */ 681da48c9a2SAnjali Singhai Jain #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 682da48c9a2SAnjali Singhai Jain #endif /* _I40E_REGISTER_H_ */ 683