1ae06c70bSJeff Kirsher /* SPDX-License-Identifier: GPL-2.0 */ 290bc8e00SArkadiusz Kubalewski /* Copyright(c) 2013 - 2021 Intel Corporation. */ 356a62fc8SJesse Brandeburg 456a62fc8SJesse Brandeburg #ifndef _I40E_REGISTER_H_ 556a62fc8SJesse Brandeburg #define _I40E_REGISTER_H_ 656a62fc8SJesse Brandeburg 74c33f83aSAnjali Singhai Jain #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 84c33f83aSAnjali Singhai Jain #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 94c33f83aSAnjali Singhai Jain #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 104c33f83aSAnjali Singhai Jain #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 114c33f83aSAnjali Singhai Jain #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 1256a62fc8SJesse Brandeburg #define I40E_PF_ARQH_ARQH_SHIFT 0 134c33f83aSAnjali Singhai Jain #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 144c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 1556a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 164c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 1756a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 184c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 1956a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 204c33f83aSAnjali Singhai Jain #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 2156a62fc8SJesse Brandeburg #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 22fb598262SBeilei Xing #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 234c33f83aSAnjali Singhai Jain #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 244c33f83aSAnjali Singhai Jain #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 254c33f83aSAnjali Singhai Jain #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 264c33f83aSAnjali Singhai Jain #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 274c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 2856a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 294c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 3056a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 314c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 3256a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 334c33f83aSAnjali Singhai Jain #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 3456a62fc8SJesse Brandeburg #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 35fb598262SBeilei Xing #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 364c33f83aSAnjali Singhai Jain #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 3790bc8e00SArkadiusz Kubalewski #define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */ 3890bc8e00SArkadiusz Kubalewski #define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0 3990bc8e00SArkadiusz Kubalewski #define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) 4090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 4190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 4290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT) 434c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 4490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 4590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT) 4656a62fc8SJesse Brandeburg #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 474c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 484c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 4956a62fc8SJesse Brandeburg #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 504c33f83aSAnjali Singhai Jain #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 5190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */ 5290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 5390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT) 5490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 5590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT) 5690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 5790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 5890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 5990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT) 6090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 6190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 6290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */ 6390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 6490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 6590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 6690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 6790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 6890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 6990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 7090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 7190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 7290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 7390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 7490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 7590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 7690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 7790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 7890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 7990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 8090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 8190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 8290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 8390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 8490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 8590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 8690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ 8790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 8890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 8990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */ 9090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 9190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 9290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 9390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 9490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 9590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 9690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 9790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 9890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 9990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 10090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 10190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 10290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 10390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 10490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 10590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 10690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 10790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 10890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 10990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) 11090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 11190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 11290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 11390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 11490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 11590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 11690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 11790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ 11890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 11990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT) 12090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 12190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT) 12290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 12390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 12490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 12590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 12690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 12790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 12890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */ 12990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 13090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT) 13190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 13290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 13390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */ 13490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 13590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \ 13690bc8e00SArkadiusz Kubalewski I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 13790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 13890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 13990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */ 14090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 14190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, \ 14290bc8e00SArkadiusz Kubalewski I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 14390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 14490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 14590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */ 14690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 14790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT) 14890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 14990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 15090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 15190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 15290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 15390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 15490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 15590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 15690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 15790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 15890bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 15990bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 16090bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 16190bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 16290bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 16390bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 16490bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ 16590bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 16690bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 16790bc8e00SArkadiusz Kubalewski #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 1684c33f83aSAnjali Singhai Jain #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 16956a62fc8SJesse Brandeburg #define I40E_GL_FWSTS_FWS1B_SHIFT 16 1704c33f83aSAnjali Singhai Jain #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 171fffeeddfSPiotr Kwapulinski #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 172fffeeddfSPiotr Kwapulinski #define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 173d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 174d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 175d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 176d4256c8eSAdrian Podlawski #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 177d4256c8eSAdrian Podlawski #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 178d4256c8eSAdrian Podlawski #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) 1794c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 18056a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 18156a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 1824c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 18356a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 1844c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 18510507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 18610507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 18710507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 18856a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 1894c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 19056a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 19156a62fc8SJesse Brandeburg #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 1924c33f83aSAnjali Singhai Jain #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 19310507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 19410507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 19510507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 19610507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 19710507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 19810507130SPiotr Kwapulinski #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 1994c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 2004c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 20156a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 20256a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 20356a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 20456a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 205*45116a7cSIvan Vecera #define I40E_GLGEN_MSCA_OPCODE_MASK(_i) I40E_MASK(_i, I40E_GLGEN_MSCA_OPCODE_SHIFT) 20656a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 207*45116a7cSIvan Vecera #define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_STCODE_SHIFT) 20856a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 2094c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 21056a62fc8SJesse Brandeburg #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 211fb598262SBeilei Xing #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 2124c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 21356a62fc8SJesse Brandeburg #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 21456a62fc8SJesse Brandeburg #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 2154c33f83aSAnjali Singhai Jain #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 2161adb1563SLukasz Cieplicki #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 2171adb1563SLukasz Cieplicki #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 2181adb1563SLukasz Cieplicki #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 2191adb1563SLukasz Cieplicki #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 2201adb1563SLukasz Cieplicki #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 2214c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 22256a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 2234c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 22456a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 2254c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 2264c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 22756a62fc8SJesse Brandeburg #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 2284c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 2294c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 23056a62fc8SJesse Brandeburg #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 2314c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 23256a62fc8SJesse Brandeburg #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 2334c33f83aSAnjali Singhai Jain #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 2344c33f83aSAnjali Singhai Jain #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 2354c33f83aSAnjali Singhai Jain #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 2364c33f83aSAnjali Singhai Jain #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 2374c33f83aSAnjali Singhai Jain #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 23856a62fc8SJesse Brandeburg #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 2394c33f83aSAnjali Singhai Jain #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 2404c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 24156a62fc8SJesse Brandeburg #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 2424c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 2434c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 24456a62fc8SJesse Brandeburg #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 2454c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 2464c33f83aSAnjali Singhai Jain #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 2474c33f83aSAnjali Singhai Jain #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2484c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 24956a62fc8SJesse Brandeburg #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 2504c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 2514c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 25256a62fc8SJesse Brandeburg #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 2534c33f83aSAnjali Singhai Jain #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 2544c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 25556a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 2564c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 2574c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 2584c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 2594c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 26056a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 2614c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 2624c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 2634c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 26456a62fc8SJesse Brandeburg #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 2654c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 2664c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 2674c33f83aSAnjali Singhai Jain #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 2684c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 2694c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 27056a62fc8SJesse Brandeburg #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 2714c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 2724c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 2734c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 2744c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 27556a62fc8SJesse Brandeburg #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 2764c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 2774c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 2784c33f83aSAnjali Singhai Jain #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 2794c33f83aSAnjali Singhai Jain #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 2804c33f83aSAnjali Singhai Jain #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 2814c33f83aSAnjali Singhai Jain #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 28256a62fc8SJesse Brandeburg #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 28356a62fc8SJesse Brandeburg #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 2844c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 28556a62fc8SJesse Brandeburg #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 2864c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 2874c33f83aSAnjali Singhai Jain #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 28856a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 28956a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 29056a62fc8SJesse Brandeburg #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 2914c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 29256a62fc8SJesse Brandeburg #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 2934c33f83aSAnjali Singhai Jain #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 2944c33f83aSAnjali Singhai Jain #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 29556a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 29656a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 29756a62fc8SJesse Brandeburg #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 2984c33f83aSAnjali Singhai Jain #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 2994c33f83aSAnjali Singhai Jain #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 30056a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 30156a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 30256a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 30356a62fc8SJesse Brandeburg #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 3044c33f83aSAnjali Singhai Jain #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 305b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 306b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 307b8262a6dSAnjali Singhai Jain #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 3084c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 30956a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 3104c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 31156a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 3124c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 31356a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 3144c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 31556a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 3164c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 31756a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 3184c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 31956a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 3204c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 32156a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 3224c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 3234c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 32456a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 3254c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 32656a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 3274c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 32856a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 3294c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 33056a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 3314c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 33256a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 33366ca011aSIvan Vecera #define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 33456a62fc8SJesse Brandeburg #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 3354c33f83aSAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 33666ca011aSIvan Vecera #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 33766ca011aSIvan Vecera #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 3384c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 33956a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 3404c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 34156a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 3424c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 34356a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 3444c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 34556a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 3464c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 34756a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_GRST_SHIFT 20 3484c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 34956a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 3504c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 35156a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 3524c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 35356a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 3544c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 35556a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 3564c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 35756a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_VFLR_SHIFT 29 3584c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT) 35956a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 3604c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT) 36156a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_SWINT_SHIFT 31 3624c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT) 3634c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 36456a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 3654c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 36656a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 3674c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 36856a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 3694c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT) 37056a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 3714c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 37256a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 3734c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 37456a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 3754c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 37656a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 3774c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 37856a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 3794c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 38056a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 3814c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 38256a62fc8SJesse Brandeburg #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 3834c33f83aSAnjali Singhai Jain #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 3844c33f83aSAnjali Singhai Jain #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 3854c33f83aSAnjali Singhai Jain #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 3864c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 38756a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 3884c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 38956a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 3904c33f83aSAnjali Singhai Jain #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 39156a62fc8SJesse Brandeburg #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 3924c33f83aSAnjali Singhai Jain #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 3935098850cSAnjali Singhai Jain #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 3944c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 39556a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 3964c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 39756a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 3984c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) 39956a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 4004c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 40156a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 4024c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 40356a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 40456a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 4054c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 40656a62fc8SJesse Brandeburg #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 4074c33f83aSAnjali Singhai Jain #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 4084c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 40956a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 4104c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 41156a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 4124c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT) 41356a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 4144c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 41556a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 4164c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 41756a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 41856a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 4194c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 42056a62fc8SJesse Brandeburg #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 4214c33f83aSAnjali Singhai Jain #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 4224c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4234c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 42456a62fc8SJesse Brandeburg #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 4254c33f83aSAnjali Singhai Jain #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 4260f344c81SKaren Sornek #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 4270f344c81SKaren Sornek #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT) 4280f344c81SKaren Sornek #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 4294c33f83aSAnjali Singhai Jain #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 43056a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 43156a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 43256a62fc8SJesse Brandeburg #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 4334c33f83aSAnjali Singhai Jain #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 4344c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 43556a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 43656a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 43756a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 4384c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 43956a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 4404c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 44156a62fc8SJesse Brandeburg #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 4424c33f83aSAnjali Singhai Jain #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 4434c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 44456a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 4454c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 4464c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 44756a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 4484c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 44956a62fc8SJesse Brandeburg #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 4504c33f83aSAnjali Singhai Jain #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 4514c33f83aSAnjali Singhai Jain #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 45256a62fc8SJesse Brandeburg #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 4534c33f83aSAnjali Singhai Jain #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 4544c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 4554c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 4564c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 4574c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 458351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 4594c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 460351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 4614c33f83aSAnjali Singhai Jain #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 462351499abSMatt Jared #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 463fb598262SBeilei Xing #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 4644c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 46556a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 4664c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 46756a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 4684c33f83aSAnjali Singhai Jain #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 46956a62fc8SJesse Brandeburg #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 470fb598262SBeilei Xing #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) 4714c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 47256a62fc8SJesse Brandeburg #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 4734c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 47456a62fc8SJesse Brandeburg #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 4754c33f83aSAnjali Singhai Jain #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 4764c33f83aSAnjali Singhai Jain #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 4774c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 47856a62fc8SJesse Brandeburg #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 4794c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 48056a62fc8SJesse Brandeburg #define I40E_QTX_CTL_PF_INDX_SHIFT 2 4814c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT) 48256a62fc8SJesse Brandeburg #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 4834c33f83aSAnjali Singhai Jain #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 4844c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 48556a62fc8SJesse Brandeburg #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 4864c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 48756a62fc8SJesse Brandeburg #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 4884c33f83aSAnjali Singhai Jain #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 4894c33f83aSAnjali Singhai Jain #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 4904c33f83aSAnjali Singhai Jain #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 4914c33f83aSAnjali Singhai Jain #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 49256a62fc8SJesse Brandeburg #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 4934c33f83aSAnjali Singhai Jain #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 4944c33f83aSAnjali Singhai Jain #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 49556a62fc8SJesse Brandeburg #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 4964c33f83aSAnjali Singhai Jain #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 4974c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 49856a62fc8SJesse Brandeburg #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 4994c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 5004c33f83aSAnjali Singhai Jain #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 5014c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 50256a62fc8SJesse Brandeburg #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 5034c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) 50456a62fc8SJesse Brandeburg #define I40E_PRTGL_SAH_MFS_SHIFT 16 5054c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT) 5064c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 50756a62fc8SJesse Brandeburg #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 5084c33f83aSAnjali Singhai Jain #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 50990bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */ 51090bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 51190bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, \ 51290bc8e00SArkadiusz Kubalewski I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 51390bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */ 51490bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 51590bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, \ 51690bc8e00SArkadiusz Kubalewski I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 51790bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */ 51890bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 51990bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \ 52090bc8e00SArkadiusz Kubalewski I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 52190bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */ 52290bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 52390bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, \ 52490bc8e00SArkadiusz Kubalewski I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 52590bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ 52690bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 52790bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 52890bc8e00SArkadiusz Kubalewski #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, \ 52990bc8e00SArkadiusz Kubalewski I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 5304c33f83aSAnjali Singhai Jain #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 53156a62fc8SJesse Brandeburg #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 5324c33f83aSAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 5334c33f83aSAnjali Singhai Jain #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 53456a62fc8SJesse Brandeburg #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 5354c33f83aSAnjali Singhai Jain #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 5364c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 53756a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 53856a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_START_SHIFT 30 53956a62fc8SJesse Brandeburg #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 540fb598262SBeilei Xing #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) 5414c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 54256a62fc8SJesse Brandeburg #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 5434c33f83aSAnjali Singhai Jain #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 5444c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 54542794bd8SShannon Nelson #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 5464c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 54742794bd8SShannon Nelson #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 5484c33f83aSAnjali Singhai Jain #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 5494c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 55056a62fc8SJesse Brandeburg #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 5514c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 5524c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 55356a62fc8SJesse Brandeburg #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 5544c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 55556a62fc8SJesse Brandeburg #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 5564c33f83aSAnjali Singhai Jain #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 5574c33f83aSAnjali Singhai Jain #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 55856a62fc8SJesse Brandeburg #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 5594c33f83aSAnjali Singhai Jain #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 5604c33f83aSAnjali Singhai Jain #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 5614c33f83aSAnjali Singhai Jain #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 56256a62fc8SJesse Brandeburg #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 5634c33f83aSAnjali Singhai Jain #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 5644c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 56510507130SPiotr Kwapulinski #define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */ 56656a62fc8SJesse Brandeburg #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 5674c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 56856a62fc8SJesse Brandeburg #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 5694c33f83aSAnjali Singhai Jain #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 57095f352dcSAleksandr Loktionov #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 57195f352dcSAleksandr Loktionov #define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 5724c33f83aSAnjali Singhai Jain #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 5734c33f83aSAnjali Singhai Jain #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 57490bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 57590bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 57690bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 57790bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 57890bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 57990bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 58090bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 58190bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 58290bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 58390bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 58490bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 58590bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 58690bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */ 58790bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHW_SHW_SHIFT 0 58890bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT) 58990bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 59090bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 59190bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 59290bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */ 59390bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLW_SLW_SHIFT 0 59490bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT) 59590bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */ 59690bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SPS_SPS_SHIFT 0 59790bc8e00SArkadiusz Kubalewski #define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT) 5984c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 59956a62fc8SJesse Brandeburg #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 6004c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 60156a62fc8SJesse Brandeburg #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 6024c33f83aSAnjali Singhai Jain #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 6034c33f83aSAnjali Singhai Jain #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 6044c33f83aSAnjali Singhai Jain #define I40E_GLQF_HKEY_MAX_INDEX 12 6054c33f83aSAnjali Singhai Jain #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 6064c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 60756a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 6084c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 60956a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 6104c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 61156a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 6124c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 61356a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 6144c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 61556a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 6164c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 61756a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 6184c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT) 61956a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 6204c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 62156a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 6224c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 6234c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 62456a62fc8SJesse Brandeburg #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 6254c33f83aSAnjali Singhai Jain #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 6264c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 62756a62fc8SJesse Brandeburg #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 6284c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 62956a62fc8SJesse Brandeburg #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 6304c33f83aSAnjali Singhai Jain #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 6314c33f83aSAnjali Singhai Jain #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 6324c33f83aSAnjali Singhai Jain #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 63356a62fc8SJesse Brandeburg #define I40E_PFQF_HKEY_MAX_INDEX 12 6344c33f83aSAnjali Singhai Jain #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 63556a62fc8SJesse Brandeburg #define I40E_PFQF_HLUT_MAX_INDEX 127 636fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 637fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 638fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 639fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 640fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 641fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 642fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 643fe726082SAnjali Singhai Jain #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 6444c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 64556a62fc8SJesse Brandeburg #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 6464c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 6475807822fSAnjali Singhai jain #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 6484c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 64956a62fc8SJesse Brandeburg #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 6504c33f83aSAnjali Singhai Jain #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 6514c33f83aSAnjali Singhai Jain #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 6524c33f83aSAnjali Singhai Jain #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 65356a62fc8SJesse Brandeburg #define I40E_VFQF_HKEY1_MAX_INDEX 12 6544c33f83aSAnjali Singhai Jain #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 65556a62fc8SJesse Brandeburg #define I40E_VFQF_HLUT1_MAX_INDEX 15 6561adb1563SLukasz Cieplicki #define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 6571adb1563SLukasz Cieplicki #define I40E_GL_RXERR1H_MAX_INDEX 143 6581adb1563SLukasz Cieplicki #define I40E_GL_RXERR1H_RXERR1H_SHIFT 0 6591adb1563SLukasz Cieplicki #define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT) 6601adb1563SLukasz Cieplicki #define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 6611adb1563SLukasz Cieplicki #define I40E_GL_RXERR1L_MAX_INDEX 143 6621adb1563SLukasz Cieplicki #define I40E_GL_RXERR1L_RXERR1L_SHIFT 0 6631adb1563SLukasz Cieplicki #define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT) 6644c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6654c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6664c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6674c33f83aSAnjali Singhai Jain #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6684c33f83aSAnjali Singhai Jain #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6694c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6704c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6714c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6724c33f83aSAnjali Singhai Jain #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6734c33f83aSAnjali Singhai Jain #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6744c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6754c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6764c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6774c33f83aSAnjali Singhai Jain #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6784c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6794c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6804c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6814c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6824c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6834c33f83aSAnjali Singhai Jain #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6844c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6854c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6864c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6874c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6884c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6894c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6904c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6914c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6924c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6934c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6944c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6954c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6964c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6974c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6984c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 6994c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7004c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7014c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7024c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7034c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7044c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7054c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7064c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7074c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7084c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7094c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7104c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7114c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7124c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 7134c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 7144c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 7154c33f83aSAnjali Singhai Jain #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 7164c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7174c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7184c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7194c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7204c33f83aSAnjali Singhai Jain #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7214c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7224c33f83aSAnjali Singhai Jain #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 7234c33f83aSAnjali Singhai Jain #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7244c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7254c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7264c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7274c33f83aSAnjali Singhai Jain #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 7284c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7294c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7304c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7314c33f83aSAnjali Singhai Jain #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7324c33f83aSAnjali Singhai Jain #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7334c33f83aSAnjali Singhai Jain #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7344c33f83aSAnjali Singhai Jain #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7354c33f83aSAnjali Singhai Jain #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7364c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7374c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7384c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7394c33f83aSAnjali Singhai Jain #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7404c33f83aSAnjali Singhai Jain #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7414c33f83aSAnjali Singhai Jain #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7424c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7434c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7444c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7454c33f83aSAnjali Singhai Jain #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 7464c33f83aSAnjali Singhai Jain #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7474c33f83aSAnjali Singhai Jain #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7484c33f83aSAnjali Singhai Jain #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7494c33f83aSAnjali Singhai Jain #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7504c33f83aSAnjali Singhai Jain #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7514c33f83aSAnjali Singhai Jain #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7524c33f83aSAnjali Singhai Jain #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7534c33f83aSAnjali Singhai Jain #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7544c33f83aSAnjali Singhai Jain #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7554c33f83aSAnjali Singhai Jain #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7564c33f83aSAnjali Singhai Jain #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7574c33f83aSAnjali Singhai Jain #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7584c33f83aSAnjali Singhai Jain #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7594c33f83aSAnjali Singhai Jain #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7600a0d9af5SMitch Williams #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7614c33f83aSAnjali Singhai Jain #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7624c33f83aSAnjali Singhai Jain #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7634c33f83aSAnjali Singhai Jain #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7644c33f83aSAnjali Singhai Jain #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 7654c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7664c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7674c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7684c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7694c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7704c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7714c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7724c33f83aSAnjali Singhai Jain #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 7734c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 77456a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 7754c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 77610507130SPiotr Kwapulinski #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 77710507130SPiotr Kwapulinski #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 77856a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 7794c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 78056a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 7814c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 7824c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 78356a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 7844c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 78556a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 7864c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 78756a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 78856a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 7894c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 79056a62fc8SJesse Brandeburg #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 7914c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 7924c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 7934c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 7944c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 7954c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 79610507130SPiotr Kwapulinski #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 7974c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 79810507130SPiotr Kwapulinski #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 79910507130SPiotr Kwapulinski #define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 80056a62fc8SJesse Brandeburg #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 8014c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 8024c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 8034c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 8044c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 8054c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 8064c33f83aSAnjali Singhai Jain #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 80710507130SPiotr Kwapulinski #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 80810507130SPiotr Kwapulinski #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 80910507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 81010507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 81110507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 81210507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 81310507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT 17 81410507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_0_PTPFLAG_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_PTPFLAG_SHIFT) 81510507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 81610507130SPiotr Kwapulinski #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 81710507130SPiotr Kwapulinski #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 81810507130SPiotr Kwapulinski #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 81910507130SPiotr Kwapulinski #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 82010507130SPiotr Kwapulinski #define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */ 8214c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 82256a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 8234c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 82456a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_EVENT_SHIFT 8 8254c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 82656a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_QUEUE_SHIFT 17 8274c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 82856a62fc8SJesse Brandeburg #define I40E_GL_MDET_RX_VALID_SHIFT 31 8294c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT) 8304c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 8314c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_QUEUE_SHIFT 0 8324c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT) 8334c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VF_NUM_SHIFT 12 8344c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT) 8354c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_PF_NUM_SHIFT 21 8364c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT) 8374c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_EVENT_SHIFT 25 8384c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT) 83956a62fc8SJesse Brandeburg #define I40E_GL_MDET_TX_VALID_SHIFT 31 8404c33f83aSAnjali Singhai Jain #define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT) 8414c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 84256a62fc8SJesse Brandeburg #define I40E_PF_MDET_RX_VALID_SHIFT 0 8434c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT) 8444c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 84556a62fc8SJesse Brandeburg #define I40E_PF_MDET_TX_VALID_SHIFT 0 8464c33f83aSAnjali Singhai Jain #define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 8474c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 84856a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 8494c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 85056a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 8514c33f83aSAnjali Singhai Jain #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 85256a62fc8SJesse Brandeburg #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 853fb598262SBeilei Xing #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) 8544c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 85556a62fc8SJesse Brandeburg #define I40E_VP_MDET_RX_VALID_SHIFT 0 8564c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 8574c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 85856a62fc8SJesse Brandeburg #define I40E_VP_MDET_TX_VALID_SHIFT 0 8594c33f83aSAnjali Singhai Jain #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 8604c33f83aSAnjali Singhai Jain #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 86156a62fc8SJesse Brandeburg #define I40E_PFPM_APM_APME_SHIFT 0 8624c33f83aSAnjali Singhai Jain #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 8634c33f83aSAnjali Singhai Jain #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 86456a62fc8SJesse Brandeburg #define I40E_PFPM_WUFC_MAG_SHIFT 1 8654c33f83aSAnjali Singhai Jain #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 8664c33f83aSAnjali Singhai Jain #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 8674c33f83aSAnjali Singhai Jain #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 8684c33f83aSAnjali Singhai Jain #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 8694c33f83aSAnjali Singhai Jain #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 8704c33f83aSAnjali Singhai Jain #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 8714c33f83aSAnjali Singhai Jain #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 8724c33f83aSAnjali Singhai Jain #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 8734c33f83aSAnjali Singhai Jain #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 8744c33f83aSAnjali Singhai Jain #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 8754c33f83aSAnjali Singhai Jain #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 87656a62fc8SJesse Brandeburg #define I40E_VFQF_HLUT_MAX_INDEX 15 877da48c9a2SAnjali Singhai Jain 878da48c9a2SAnjali Singhai Jain 879da48c9a2SAnjali Singhai Jain 880da48c9a2SAnjali Singhai Jain 881da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 882da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 883da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 884da48c9a2SAnjali Singhai Jain #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 885da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 886da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 887da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 888da48c9a2SAnjali Singhai Jain 889da48c9a2SAnjali Singhai Jain #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 890da48c9a2SAnjali Singhai Jain 891da48c9a2SAnjali Singhai Jain 892da48c9a2SAnjali Singhai Jain 893fe726082SAnjali Singhai Jain #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 894fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 895fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 896fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 897fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 898fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 899fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 900fe726082SAnjali Singhai Jain #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 901da48c9a2SAnjali Singhai Jain #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 902da48c9a2SAnjali Singhai Jain /* Redefined for X722 family */ 903da48c9a2SAnjali Singhai Jain #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 904da48c9a2SAnjali Singhai Jain #endif /* _I40E_REGISTER_H_ */ 905