1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e.h" 28 #include <linux/ptp_classify.h> 29 30 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 31 * the fundamental clock design. However, the clock operations are much simpler 32 * in the XL710 because the device supports a full 64 bits of nanoseconds. 33 * Because the field is so wide, we can forgo the cycle counter and just 34 * operate with the nanosecond field directly without fear of overflow. 35 * 36 * Much like the 82599, the update period is dependent upon the link speed: 37 * At 40Gb link or no link, the period is 1.6ns. 38 * At 10Gb link, the period is multiplied by 2. (3.2ns) 39 * At 1Gb link, the period is multiplied by 20. (32ns) 40 * 1588 functionality is not supported at 100Mbps. 41 */ 42 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 43 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 44 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 45 46 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \ 47 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 48 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \ 49 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 50 51 /** 52 * i40e_ptp_read - Read the PHC time from the device 53 * @pf: Board private structure 54 * @ts: timespec structure to hold the current time value 55 * 56 * This function reads the PRTTSYN_TIME registers and stores them in a 57 * timespec. However, since the registers are 64 bits of nanoseconds, we must 58 * convert the result to a timespec before we can return. 59 **/ 60 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts) 61 { 62 struct i40e_hw *hw = &pf->hw; 63 u32 hi, lo; 64 u64 ns; 65 66 /* The timer latches on the lowest register read. */ 67 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 68 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 69 70 ns = (((u64)hi) << 32) | lo; 71 72 *ts = ns_to_timespec(ns); 73 } 74 75 /** 76 * i40e_ptp_write - Write the PHC time to the device 77 * @pf: Board private structure 78 * @ts: timespec structure that holds the new time value 79 * 80 * This function writes the PRTTSYN_TIME registers with the user value. Since 81 * we receive a timespec from the stack, we must convert that timespec into 82 * nanoseconds before programming the registers. 83 **/ 84 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts) 85 { 86 struct i40e_hw *hw = &pf->hw; 87 u64 ns = timespec_to_ns(ts); 88 89 /* The timer will not update until the high register is written, so 90 * write the low register first. 91 */ 92 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 93 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 94 } 95 96 /** 97 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 98 * @hwtstamps: Timestamp structure to update 99 * @timestamp: Timestamp from the hardware 100 * 101 * We need to convert the NIC clock value into a hwtstamp which can be used by 102 * the upper level timestamping functions. Since the timestamp is simply a 64- 103 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 104 **/ 105 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 106 u64 timestamp) 107 { 108 memset(hwtstamps, 0, sizeof(*hwtstamps)); 109 110 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 111 } 112 113 /** 114 * i40e_ptp_adjfreq - Adjust the PHC frequency 115 * @ptp: The PTP clock structure 116 * @ppb: Parts per billion adjustment from the base 117 * 118 * Adjust the frequency of the PHC by the indicated parts per billion from the 119 * base frequency. 120 **/ 121 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 122 { 123 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 124 struct i40e_hw *hw = &pf->hw; 125 u64 adj, freq, diff; 126 int neg_adj = 0; 127 128 if (ppb < 0) { 129 neg_adj = 1; 130 ppb = -ppb; 131 } 132 133 smp_mb(); /* Force any pending update before accessing. */ 134 adj = ACCESS_ONCE(pf->ptp_base_adj); 135 136 freq = adj; 137 freq *= ppb; 138 diff = div_u64(freq, 1000000000ULL); 139 140 if (neg_adj) 141 adj -= diff; 142 else 143 adj += diff; 144 145 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 146 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 147 148 return 0; 149 } 150 151 /** 152 * i40e_ptp_adjtime - Adjust the PHC time 153 * @ptp: The PTP clock structure 154 * @delta: Offset in nanoseconds to adjust the PHC time by 155 * 156 * Adjust the frequency of the PHC by the indicated parts per billion from the 157 * base frequency. 158 **/ 159 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 160 { 161 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 162 struct timespec now, then = ns_to_timespec(delta); 163 unsigned long flags; 164 165 spin_lock_irqsave(&pf->tmreg_lock, flags); 166 167 i40e_ptp_read(pf, &now); 168 now = timespec_add(now, then); 169 i40e_ptp_write(pf, (const struct timespec *)&now); 170 171 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 172 173 return 0; 174 } 175 176 /** 177 * i40e_ptp_gettime - Get the time of the PHC 178 * @ptp: The PTP clock structure 179 * @ts: timespec structure to hold the current time value 180 * 181 * Read the device clock and return the correct value on ns, after converting it 182 * into a timespec struct. 183 **/ 184 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 185 { 186 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 187 unsigned long flags; 188 189 spin_lock_irqsave(&pf->tmreg_lock, flags); 190 i40e_ptp_read(pf, ts); 191 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 192 193 return 0; 194 } 195 196 /** 197 * i40e_ptp_settime - Set the time of the PHC 198 * @ptp: The PTP clock structure 199 * @ts: timespec structure that holds the new time value 200 * 201 * Set the device clock to the user input value. The conversion from timespec 202 * to ns happens in the write function. 203 **/ 204 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 205 const struct timespec *ts) 206 { 207 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 208 unsigned long flags; 209 210 spin_lock_irqsave(&pf->tmreg_lock, flags); 211 i40e_ptp_write(pf, ts); 212 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 213 214 return 0; 215 } 216 217 /** 218 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 219 * @ptp: The PTP clock structure 220 * @rq: The requested feature to change 221 * @on: Enable/disable flag 222 * 223 * The XL710 does not support any of the ancillary features of the PHC 224 * subsystem, so this function may just return. 225 **/ 226 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 227 struct ptp_clock_request *rq, int on) 228 { 229 return -EOPNOTSUPP; 230 } 231 232 /** 233 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 234 * @vsi: The VSI with the rings relevant to 1588 235 * 236 * This watchdog task is scheduled to detect error case where hardware has 237 * dropped an Rx packet that was timestamped when the ring is full. The 238 * particular error is rare but leaves the device in a state unable to timestamp 239 * any future packets. 240 **/ 241 void i40e_ptp_rx_hang(struct i40e_vsi *vsi) 242 { 243 struct i40e_pf *pf = vsi->back; 244 struct i40e_hw *hw = &pf->hw; 245 struct i40e_ring *rx_ring; 246 unsigned long rx_event; 247 u32 prttsyn_stat; 248 int n; 249 250 if (!(pf->flags & I40E_FLAG_PTP)) 251 return; 252 253 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 254 255 /* Unless all four receive timestamp registers are latched, we are not 256 * concerned about a possible PTP Rx hang, so just update the timeout 257 * counter and exit. 258 */ 259 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK << 260 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) | 261 (I40E_PRTTSYN_STAT_1_RXT1_MASK << 262 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) | 263 (I40E_PRTTSYN_STAT_1_RXT2_MASK << 264 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) | 265 (I40E_PRTTSYN_STAT_1_RXT3_MASK << 266 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) { 267 pf->last_rx_ptp_check = jiffies; 268 return; 269 } 270 271 /* Determine the most recent watchdog or rx_timestamp event. */ 272 rx_event = pf->last_rx_ptp_check; 273 for (n = 0; n < vsi->num_queue_pairs; n++) { 274 rx_ring = vsi->rx_rings[n]; 275 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 276 rx_event = rx_ring->last_rx_timestamp; 277 } 278 279 /* Only need to read the high RXSTMP register to clear the lock */ 280 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 281 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 282 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 283 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 284 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 285 pf->last_rx_ptp_check = jiffies; 286 pf->rx_hwtstamp_cleared++; 287 dev_warn(&vsi->back->pdev->dev, 288 "%s: clearing Rx timestamp hang\n", 289 __func__); 290 } 291 } 292 293 /** 294 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 295 * @pf: Board private structure 296 * 297 * Read the value of the Tx timestamp from the registers, convert it into a 298 * value consumable by the stack, and store that result into the shhwtstamps 299 * struct before returning it up the stack. 300 **/ 301 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 302 { 303 struct skb_shared_hwtstamps shhwtstamps; 304 struct i40e_hw *hw = &pf->hw; 305 u32 hi, lo; 306 u64 ns; 307 308 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 309 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 310 311 ns = (((u64)hi) << 32) | lo; 312 313 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 314 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps); 315 dev_kfree_skb_any(pf->ptp_tx_skb); 316 pf->ptp_tx_skb = NULL; 317 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 318 } 319 320 /** 321 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 322 * @pf: Board private structure 323 * @skb: Particular skb to send timestamp with 324 * @index: Index into the receive timestamp registers for the timestamp 325 * 326 * The XL710 receives a notification in the receive descriptor with an offset 327 * into the set of RXTIME registers where the timestamp is for that skb. This 328 * function goes and fetches the receive timestamp from that offset, if a valid 329 * one exists. The RXTIME registers are in ns, so we must convert the result 330 * first. 331 **/ 332 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 333 { 334 u32 prttsyn_stat, hi, lo; 335 struct i40e_hw *hw; 336 u64 ns; 337 338 /* Since we cannot turn off the Rx timestamp logic if the device is 339 * doing Tx timestamping, check if Rx timestamping is configured. 340 */ 341 if (!pf->ptp_rx) 342 return; 343 344 hw = &pf->hw; 345 346 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 347 348 if (!(prttsyn_stat & (1 << index))) 349 return; 350 351 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 352 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 353 354 ns = (((u64)hi) << 32) | lo; 355 356 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 357 } 358 359 /** 360 * i40e_ptp_set_increment - Utility function to update clock increment rate 361 * @pf: Board private structure 362 * 363 * During a link change, the DMA frequency that drives the 1588 logic will 364 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 365 * we must update the increment value per clock tick. 366 **/ 367 void i40e_ptp_set_increment(struct i40e_pf *pf) 368 { 369 struct i40e_link_status *hw_link_info; 370 struct i40e_hw *hw = &pf->hw; 371 u64 incval; 372 373 hw_link_info = &hw->phy.link_info; 374 375 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 376 377 switch (hw_link_info->link_speed) { 378 case I40E_LINK_SPEED_10GB: 379 incval = I40E_PTP_10GB_INCVAL; 380 break; 381 case I40E_LINK_SPEED_1GB: 382 incval = I40E_PTP_1GB_INCVAL; 383 break; 384 case I40E_LINK_SPEED_100MB: 385 { 386 static int warn_once; 387 388 if (!warn_once) { 389 dev_warn(&pf->pdev->dev, 390 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 391 warn_once++; 392 } 393 incval = 0; 394 break; 395 } 396 case I40E_LINK_SPEED_40GB: 397 default: 398 incval = I40E_PTP_40GB_INCVAL; 399 break; 400 } 401 402 /* Write the new increment value into the increment register. The 403 * hardware will not update the clock until both registers have been 404 * written. 405 */ 406 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 407 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 408 409 /* Update the base adjustement value. */ 410 ACCESS_ONCE(pf->ptp_base_adj) = incval; 411 smp_mb(); /* Force the above update. */ 412 } 413 414 /** 415 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 416 * @pf: Board private structure 417 * @ifreq: ioctl data 418 * 419 * Obtain the current hardware timestamping settigs as requested. To do this, 420 * keep a shadow copy of the timestamp settings rather than attempting to 421 * deconstruct it from the registers. 422 **/ 423 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 424 { 425 struct hwtstamp_config *config = &pf->tstamp_config; 426 427 if (!(pf->flags & I40E_FLAG_PTP)) 428 return -EOPNOTSUPP; 429 430 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 431 -EFAULT : 0; 432 } 433 434 /** 435 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 436 * @pf: Board private structure 437 * @config: hwtstamp settings requested or saved 438 * 439 * Control hardware registers to enter the specific mode requested by the 440 * user. Also used during reset path to ensure that timestamp settings are 441 * maintained. 442 * 443 * Note: modifies config in place, and may update the requested mode to be 444 * more broad if the specific filter is not directly supported. 445 **/ 446 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 447 struct hwtstamp_config *config) 448 { 449 struct i40e_hw *hw = &pf->hw; 450 u32 tsyntype, regval; 451 452 /* Reserved for future extensions. */ 453 if (config->flags) 454 return -EINVAL; 455 456 switch (config->tx_type) { 457 case HWTSTAMP_TX_OFF: 458 pf->ptp_tx = false; 459 break; 460 case HWTSTAMP_TX_ON: 461 pf->ptp_tx = true; 462 break; 463 default: 464 return -ERANGE; 465 } 466 467 switch (config->rx_filter) { 468 case HWTSTAMP_FILTER_NONE: 469 pf->ptp_rx = false; 470 tsyntype = 0; 471 break; 472 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 473 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 474 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 475 pf->ptp_rx = true; 476 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 477 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 478 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 479 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 480 break; 481 case HWTSTAMP_FILTER_PTP_V2_EVENT: 482 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 483 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 484 case HWTSTAMP_FILTER_PTP_V2_SYNC: 485 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 486 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 487 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 488 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 489 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 490 pf->ptp_rx = true; 491 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 492 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 | 493 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 494 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 495 break; 496 case HWTSTAMP_FILTER_ALL: 497 default: 498 return -ERANGE; 499 } 500 501 /* Clear out all 1588-related registers to clear and unlatch them. */ 502 rd32(hw, I40E_PRTTSYN_STAT_0); 503 rd32(hw, I40E_PRTTSYN_TXTIME_H); 504 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 505 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 506 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 507 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 508 509 /* Enable/disable the Tx timestamp interrupt based on user input. */ 510 regval = rd32(hw, I40E_PRTTSYN_CTL0); 511 if (pf->ptp_tx) 512 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 513 else 514 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 515 wr32(hw, I40E_PRTTSYN_CTL0, regval); 516 517 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 518 if (pf->ptp_tx) 519 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 520 else 521 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 522 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 523 524 /* There is no simple on/off switch for Rx. To "disable" Rx support, 525 * ignore any received timestamps, rather than turn off the clock. 526 */ 527 if (pf->ptp_rx) { 528 regval = rd32(hw, I40E_PRTTSYN_CTL1); 529 /* clear everything but the enable bit */ 530 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 531 /* now enable bits for desired Rx timestamps */ 532 regval |= tsyntype; 533 wr32(hw, I40E_PRTTSYN_CTL1, regval); 534 } 535 536 return 0; 537 } 538 539 /** 540 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 541 * @pf: Board private structure 542 * @ifreq: ioctl data 543 * 544 * Respond to the user filter requests and make the appropriate hardware 545 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 546 * logic, so keep track in software of whether to indicate these timestamps 547 * or not. 548 * 549 * It is permissible to "upgrade" the user request to a broader filter, as long 550 * as the user receives the timestamps they care about and the user is notified 551 * the filter has been broadened. 552 **/ 553 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 554 { 555 struct hwtstamp_config config; 556 int err; 557 558 if (!(pf->flags & I40E_FLAG_PTP)) 559 return -EOPNOTSUPP; 560 561 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 562 return -EFAULT; 563 564 err = i40e_ptp_set_timestamp_mode(pf, &config); 565 if (err) 566 return err; 567 568 /* save these settings for future reference */ 569 pf->tstamp_config = config; 570 571 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 572 -EFAULT : 0; 573 } 574 575 /** 576 * i40e_ptp_create_clock - Create PTP clock device for userspace 577 * @pf: Board private structure 578 * 579 * This function creates a new PTP clock device. It only creates one if we 580 * don't already have one, so it is safe to call. Will return error if it 581 * can't create one, but success if we already have a device. Should be used 582 * by i40e_ptp_init to create clock initially, and prevent global resets from 583 * creating new clock devices. 584 **/ 585 static long i40e_ptp_create_clock(struct i40e_pf *pf) 586 { 587 /* no need to create a clock device if we already have one */ 588 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 589 return 0; 590 591 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name)); 592 pf->ptp_caps.owner = THIS_MODULE; 593 pf->ptp_caps.max_adj = 999999999; 594 pf->ptp_caps.n_ext_ts = 0; 595 pf->ptp_caps.pps = 0; 596 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 597 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 598 pf->ptp_caps.gettime = i40e_ptp_gettime; 599 pf->ptp_caps.settime = i40e_ptp_settime; 600 pf->ptp_caps.enable = i40e_ptp_feature_enable; 601 602 /* Attempt to register the clock before enabling the hardware. */ 603 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 604 if (IS_ERR(pf->ptp_clock)) { 605 return PTR_ERR(pf->ptp_clock); 606 } 607 608 /* clear the hwtstamp settings here during clock create, instead of 609 * during regular init, so that we can maintain settings across a 610 * reset or suspend. 611 */ 612 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 613 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 614 615 return 0; 616 } 617 618 /** 619 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 620 * @pf: Board private structure 621 * 622 * This function sets device up for 1588 support. The first time it is run, it 623 * will create a PHC clock device. It does not create a clock device if one 624 * already exists. It also reconfigures the device after a reset. 625 **/ 626 void i40e_ptp_init(struct i40e_pf *pf) 627 { 628 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 629 struct i40e_hw *hw = &pf->hw; 630 u32 pf_id; 631 long err; 632 633 /* Only one PF is assigned to control 1588 logic per port. Do not 634 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 635 */ 636 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 637 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 638 if (hw->pf_id != pf_id) { 639 pf->flags &= ~I40E_FLAG_PTP; 640 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 641 __func__, 642 netdev->name); 643 return; 644 } 645 646 /* we have to initialize the lock first, since we can't control 647 * when the user will enter the PHC device entry points 648 */ 649 spin_lock_init(&pf->tmreg_lock); 650 651 /* ensure we have a clock device */ 652 err = i40e_ptp_create_clock(pf); 653 if (err) { 654 pf->ptp_clock = NULL; 655 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 656 __func__); 657 } else { 658 struct timespec ts; 659 u32 regval; 660 661 dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__, 662 netdev->name); 663 pf->flags |= I40E_FLAG_PTP; 664 665 /* Ensure the clocks are running. */ 666 regval = rd32(hw, I40E_PRTTSYN_CTL0); 667 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 668 wr32(hw, I40E_PRTTSYN_CTL0, regval); 669 regval = rd32(hw, I40E_PRTTSYN_CTL1); 670 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 671 wr32(hw, I40E_PRTTSYN_CTL1, regval); 672 673 /* Set the increment value per clock tick. */ 674 i40e_ptp_set_increment(pf); 675 676 /* reset timestamping mode */ 677 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 678 679 /* Set the clock value. */ 680 ts = ktime_to_timespec(ktime_get_real()); 681 i40e_ptp_settime(&pf->ptp_caps, &ts); 682 } 683 } 684 685 /** 686 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 687 * @pf: Board private structure 688 * 689 * This function handles the cleanup work required from the initialization by 690 * clearing out the important information and unregistering the PHC. 691 **/ 692 void i40e_ptp_stop(struct i40e_pf *pf) 693 { 694 pf->flags &= ~I40E_FLAG_PTP; 695 pf->ptp_tx = false; 696 pf->ptp_rx = false; 697 698 if (pf->ptp_tx_skb) { 699 dev_kfree_skb_any(pf->ptp_tx_skb); 700 pf->ptp_tx_skb = NULL; 701 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 702 } 703 704 if (pf->ptp_clock) { 705 ptp_clock_unregister(pf->ptp_clock); 706 pf->ptp_clock = NULL; 707 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 708 pf->vsi[pf->lan_vsi]->netdev->name); 709 } 710 } 711