1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include <linux/ptp_classify.h> 6 #include <linux/posix-clock.h> 7 8 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 9 * the fundamental clock design. However, the clock operations are much simpler 10 * in the XL710 because the device supports a full 64 bits of nanoseconds. 11 * Because the field is so wide, we can forgo the cycle counter and just 12 * operate with the nanosecond field directly without fear of overflow. 13 * 14 * Much like the 82599, the update period is dependent upon the link speed: 15 * At 40Gb, 25Gb, or no link, the period is 1.6ns. 16 * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns) 17 * At 1Gb link, the period is multiplied by 20. (32ns) 18 * 1588 functionality is not supported at 100Mbps. 19 */ 20 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 21 #define I40E_PTP_10GB_INCVAL_MULT 2 22 #define I40E_PTP_5GB_INCVAL_MULT 2 23 #define I40E_PTP_1GB_INCVAL_MULT 20 24 #define I40E_ISGN 0x80000000 25 26 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 27 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 28 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 29 #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB 30 31 enum i40e_ptp_pin { 32 SDP3_2 = 0, 33 SDP3_3, 34 GPIO_4 35 }; 36 37 enum i40e_can_set_pins_t { 38 CANT_DO_PINS = -1, 39 CAN_SET_PINS, 40 CAN_DO_PINS 41 }; 42 43 static struct ptp_pin_desc sdp_desc[] = { 44 /* name idx func chan */ 45 {"SDP3_2", SDP3_2, PTP_PF_NONE, 0}, 46 {"SDP3_3", SDP3_3, PTP_PF_NONE, 1}, 47 {"GPIO_4", GPIO_4, PTP_PF_NONE, 1}, 48 }; 49 50 enum i40e_ptp_gpio_pin_state { 51 end = -2, 52 invalid, 53 off, 54 in_A, 55 in_B, 56 out_A, 57 out_B, 58 }; 59 60 static const char * const i40e_ptp_gpio_pin_state2str[] = { 61 "off", "in_A", "in_B", "out_A", "out_B" 62 }; 63 64 enum i40e_ptp_led_pin_state { 65 led_end = -2, 66 low = 0, 67 high, 68 }; 69 70 struct i40e_ptp_pins_settings { 71 enum i40e_ptp_gpio_pin_state sdp3_2; 72 enum i40e_ptp_gpio_pin_state sdp3_3; 73 enum i40e_ptp_gpio_pin_state gpio_4; 74 enum i40e_ptp_led_pin_state led2_0; 75 enum i40e_ptp_led_pin_state led2_1; 76 enum i40e_ptp_led_pin_state led3_0; 77 enum i40e_ptp_led_pin_state led3_1; 78 }; 79 80 static const struct i40e_ptp_pins_settings 81 i40e_ptp_pin_led_allowed_states[] = { 82 {off, off, off, high, high, high, high}, 83 {off, in_A, off, high, high, high, low}, 84 {off, out_A, off, high, low, high, high}, 85 {off, in_B, off, high, high, high, low}, 86 {off, out_B, off, high, low, high, high}, 87 {in_A, off, off, high, high, high, low}, 88 {in_A, in_B, off, high, high, high, low}, 89 {in_A, out_B, off, high, low, high, high}, 90 {out_A, off, off, high, low, high, high}, 91 {out_A, in_B, off, high, low, high, high}, 92 {in_B, off, off, high, high, high, low}, 93 {in_B, in_A, off, high, high, high, low}, 94 {in_B, out_A, off, high, low, high, high}, 95 {out_B, off, off, high, low, high, high}, 96 {out_B, in_A, off, high, low, high, high}, 97 {off, off, in_A, high, high, low, high}, 98 {off, out_A, in_A, high, low, low, high}, 99 {off, in_B, in_A, high, high, low, low}, 100 {off, out_B, in_A, high, low, low, high}, 101 {out_A, off, in_A, high, low, low, high}, 102 {out_A, in_B, in_A, high, low, low, high}, 103 {in_B, off, in_A, high, high, low, low}, 104 {in_B, out_A, in_A, high, low, low, high}, 105 {out_B, off, in_A, high, low, low, high}, 106 {off, off, out_A, low, high, high, high}, 107 {off, in_A, out_A, low, high, high, low}, 108 {off, in_B, out_A, low, high, high, low}, 109 {off, out_B, out_A, low, low, high, high}, 110 {in_A, off, out_A, low, high, high, low}, 111 {in_A, in_B, out_A, low, high, high, low}, 112 {in_A, out_B, out_A, low, low, high, high}, 113 {in_B, off, out_A, low, high, high, low}, 114 {in_B, in_A, out_A, low, high, high, low}, 115 {out_B, off, out_A, low, low, high, high}, 116 {out_B, in_A, out_A, low, low, high, high}, 117 {off, off, in_B, high, high, low, high}, 118 {off, in_A, in_B, high, high, low, low}, 119 {off, out_A, in_B, high, low, low, high}, 120 {off, out_B, in_B, high, low, low, high}, 121 {in_A, off, in_B, high, high, low, low}, 122 {in_A, out_B, in_B, high, low, low, high}, 123 {out_A, off, in_B, high, low, low, high}, 124 {out_B, off, in_B, high, low, low, high}, 125 {out_B, in_A, in_B, high, low, low, high}, 126 {off, off, out_B, low, high, high, high}, 127 {off, in_A, out_B, low, high, high, low}, 128 {off, out_A, out_B, low, low, high, high}, 129 {off, in_B, out_B, low, high, high, low}, 130 {in_A, off, out_B, low, high, high, low}, 131 {in_A, in_B, out_B, low, high, high, low}, 132 {out_A, off, out_B, low, low, high, high}, 133 {out_A, in_B, out_B, low, low, high, high}, 134 {in_B, off, out_B, low, high, high, low}, 135 {in_B, in_A, out_B, low, high, high, low}, 136 {in_B, out_A, out_B, low, low, high, high}, 137 {end, end, end, led_end, led_end, led_end, led_end} 138 }; 139 140 static int i40e_ptp_set_pins(struct i40e_pf *pf, 141 struct i40e_ptp_pins_settings *pins); 142 143 /** 144 * i40e_ptp_extts0_work - workqueue task function 145 * @work: workqueue task structure 146 * 147 * Service for PTP external clock event 148 **/ 149 static void i40e_ptp_extts0_work(struct work_struct *work) 150 { 151 struct i40e_pf *pf = container_of(work, struct i40e_pf, 152 ptp_extts0_work); 153 struct i40e_hw *hw = &pf->hw; 154 struct ptp_clock_event event; 155 u32 hi, lo; 156 157 /* Event time is captured by one of the two matched registers 158 * PRTTSYN_EVNT_L: 32 LSB of sampled time event 159 * PRTTSYN_EVNT_H: 32 MSB of sampled time event 160 * Event is defined in PRTTSYN_EVNT_0 register 161 */ 162 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0)); 163 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0)); 164 165 event.timestamp = (((u64)hi) << 32) | lo; 166 167 event.type = PTP_CLOCK_EXTTS; 168 event.index = hw->pf_id; 169 170 /* fire event */ 171 ptp_clock_event(pf->ptp_clock, &event); 172 } 173 174 /** 175 * i40e_is_ptp_pin_dev - check if device supports PTP pins 176 * @hw: pointer to the hardware structure 177 * 178 * Return true if device supports PTP pins, false otherwise. 179 **/ 180 static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw) 181 { 182 return hw->device_id == I40E_DEV_ID_25G_SFP28 && 183 hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN; 184 } 185 186 /** 187 * i40e_can_set_pins - check possibility of manipulating the pins 188 * @pf: board private structure 189 * 190 * Check if all conditions are satisfied to manipulate PTP pins. 191 * Return CAN_SET_PINS if pins can be set on a specific PF or 192 * return CAN_DO_PINS if pins can be manipulated within a NIC or 193 * return CANT_DO_PINS otherwise. 194 **/ 195 static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf) 196 { 197 if (!i40e_is_ptp_pin_dev(&pf->hw)) { 198 dev_warn(&pf->pdev->dev, 199 "PTP external clock not supported.\n"); 200 return CANT_DO_PINS; 201 } 202 203 if (!pf->ptp_pins) { 204 dev_warn(&pf->pdev->dev, 205 "PTP PIN manipulation not allowed.\n"); 206 return CANT_DO_PINS; 207 } 208 209 if (pf->hw.pf_id) { 210 dev_warn(&pf->pdev->dev, 211 "PTP PINs should be accessed via PF0.\n"); 212 return CAN_DO_PINS; 213 } 214 215 return CAN_SET_PINS; 216 } 217 218 /** 219 * i40_ptp_reset_timing_events - Reset PTP timing events 220 * @pf: Board private structure 221 * 222 * This function resets timing events for pf. 223 **/ 224 static void i40_ptp_reset_timing_events(struct i40e_pf *pf) 225 { 226 u32 i; 227 228 spin_lock_bh(&pf->ptp_rx_lock); 229 for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) { 230 /* reading and automatically clearing timing events registers */ 231 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i)); 232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i)); 233 pf->latch_events[i] = 0; 234 } 235 /* reading and automatically clearing timing events registers */ 236 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L); 237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H); 238 239 pf->tx_hwtstamp_timeouts = 0; 240 pf->tx_hwtstamp_skipped = 0; 241 pf->rx_hwtstamp_cleared = 0; 242 pf->latch_event_flags = 0; 243 spin_unlock_bh(&pf->ptp_rx_lock); 244 } 245 246 /** 247 * i40e_ptp_verify - check pins 248 * @ptp: ptp clock 249 * @pin: pin index 250 * @func: assigned function 251 * @chan: channel 252 * 253 * Check pins consistency. 254 * Return 0 on success or error on failure. 255 **/ 256 static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 257 enum ptp_pin_function func, unsigned int chan) 258 { 259 switch (func) { 260 case PTP_PF_NONE: 261 case PTP_PF_EXTTS: 262 case PTP_PF_PEROUT: 263 break; 264 case PTP_PF_PHYSYNC: 265 return -EOPNOTSUPP; 266 } 267 return 0; 268 } 269 270 /** 271 * i40e_ptp_read - Read the PHC time from the device 272 * @pf: Board private structure 273 * @ts: timespec structure to hold the current time value 274 * @sts: structure to hold the system time before and after reading the PHC 275 * 276 * This function reads the PRTTSYN_TIME registers and stores them in a 277 * timespec. However, since the registers are 64 bits of nanoseconds, we must 278 * convert the result to a timespec before we can return. 279 **/ 280 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, 281 struct ptp_system_timestamp *sts) 282 { 283 struct i40e_hw *hw = &pf->hw; 284 u32 hi, lo; 285 u64 ns; 286 287 /* The timer latches on the lowest register read. */ 288 ptp_read_system_prets(sts); 289 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 290 ptp_read_system_postts(sts); 291 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 292 293 ns = (((u64)hi) << 32) | lo; 294 295 *ts = ns_to_timespec64(ns); 296 } 297 298 /** 299 * i40e_ptp_write - Write the PHC time to the device 300 * @pf: Board private structure 301 * @ts: timespec structure that holds the new time value 302 * 303 * This function writes the PRTTSYN_TIME registers with the user value. Since 304 * we receive a timespec from the stack, we must convert that timespec into 305 * nanoseconds before programming the registers. 306 **/ 307 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 308 { 309 struct i40e_hw *hw = &pf->hw; 310 u64 ns = timespec64_to_ns(ts); 311 312 /* The timer will not update until the high register is written, so 313 * write the low register first. 314 */ 315 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 316 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 317 } 318 319 /** 320 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 321 * @hwtstamps: Timestamp structure to update 322 * @timestamp: Timestamp from the hardware 323 * 324 * We need to convert the NIC clock value into a hwtstamp which can be used by 325 * the upper level timestamping functions. Since the timestamp is simply a 64- 326 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 327 **/ 328 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 329 u64 timestamp) 330 { 331 memset(hwtstamps, 0, sizeof(*hwtstamps)); 332 333 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 334 } 335 336 /** 337 * i40e_ptp_adjfreq - Adjust the PHC frequency 338 * @ptp: The PTP clock structure 339 * @ppb: Parts per billion adjustment from the base 340 * 341 * Adjust the frequency of the PHC by the indicated parts per billion from the 342 * base frequency. 343 **/ 344 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 345 { 346 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 347 struct i40e_hw *hw = &pf->hw; 348 u64 adj, freq, diff; 349 int neg_adj = 0; 350 351 if (ppb < 0) { 352 neg_adj = 1; 353 ppb = -ppb; 354 } 355 356 freq = I40E_PTP_40GB_INCVAL; 357 freq *= ppb; 358 diff = div_u64(freq, 1000000000ULL); 359 360 if (neg_adj) 361 adj = I40E_PTP_40GB_INCVAL - diff; 362 else 363 adj = I40E_PTP_40GB_INCVAL + diff; 364 365 /* At some link speeds, the base incval is so large that directly 366 * multiplying by ppb would result in arithmetic overflow even when 367 * using a u64. Avoid this by instead calculating the new incval 368 * always in terms of the 40GbE clock rate and then multiplying by the 369 * link speed factor afterwards. This does result in slightly lower 370 * precision at lower link speeds, but it is fairly minor. 371 */ 372 smp_mb(); /* Force any pending update before accessing. */ 373 adj *= READ_ONCE(pf->ptp_adj_mult); 374 375 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 376 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 377 378 return 0; 379 } 380 381 /** 382 * i40e_ptp_set_1pps_signal_hw - configure 1PPS PTP signal for pins 383 * @pf: the PF private data structure 384 * 385 * Configure 1PPS signal used for PTP pins 386 **/ 387 static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf) 388 { 389 struct i40e_hw *hw = &pf->hw; 390 struct timespec64 now; 391 u64 ns; 392 393 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0); 394 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 395 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE); 396 397 i40e_ptp_read(pf, &now, NULL); 398 now.tv_sec += I40E_PTP_2_SEC_DELAY; 399 now.tv_nsec = 0; 400 ns = timespec64_to_ns(&now); 401 402 /* I40E_PRTTSYN_TGT_L(1) */ 403 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF); 404 /* I40E_PRTTSYN_TGT_H(1) */ 405 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32); 406 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND); 407 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 408 wr32(hw, I40E_PRTTSYN_AUX_0(1), 409 I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD); 410 } 411 412 /** 413 * i40e_ptp_adjtime - Adjust the PHC time 414 * @ptp: The PTP clock structure 415 * @delta: Offset in nanoseconds to adjust the PHC time by 416 * 417 * Adjust the current clock time by a delta specified in nanoseconds. 418 **/ 419 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 420 { 421 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 422 struct i40e_hw *hw = &pf->hw; 423 424 mutex_lock(&pf->tmreg_lock); 425 426 if (delta > -999999900LL && delta < 999999900LL) { 427 int neg_adj = 0; 428 u32 timadj; 429 u64 tohw; 430 431 if (delta < 0) { 432 neg_adj = 1; 433 tohw = -delta; 434 } else { 435 tohw = delta; 436 } 437 438 timadj = tohw & 0x3FFFFFFF; 439 if (neg_adj) 440 timadj |= I40E_ISGN; 441 wr32(hw, I40E_PRTTSYN_ADJ, timadj); 442 } else { 443 struct timespec64 then, now; 444 445 then = ns_to_timespec64(delta); 446 i40e_ptp_read(pf, &now, NULL); 447 now = timespec64_add(now, then); 448 i40e_ptp_write(pf, (const struct timespec64 *)&now); 449 i40e_ptp_set_1pps_signal_hw(pf); 450 } 451 452 mutex_unlock(&pf->tmreg_lock); 453 454 return 0; 455 } 456 457 /** 458 * i40e_ptp_gettimex - Get the time of the PHC 459 * @ptp: The PTP clock structure 460 * @ts: timespec structure to hold the current time value 461 * @sts: structure to hold the system time before and after reading the PHC 462 * 463 * Read the device clock and return the correct value on ns, after converting it 464 * into a timespec struct. 465 **/ 466 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 467 struct ptp_system_timestamp *sts) 468 { 469 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 470 471 mutex_lock(&pf->tmreg_lock); 472 i40e_ptp_read(pf, ts, sts); 473 mutex_unlock(&pf->tmreg_lock); 474 475 return 0; 476 } 477 478 /** 479 * i40e_ptp_settime - Set the time of the PHC 480 * @ptp: The PTP clock structure 481 * @ts: timespec64 structure that holds the new time value 482 * 483 * Set the device clock to the user input value. The conversion from timespec 484 * to ns happens in the write function. 485 **/ 486 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 487 const struct timespec64 *ts) 488 { 489 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 490 491 mutex_lock(&pf->tmreg_lock); 492 i40e_ptp_write(pf, ts); 493 mutex_unlock(&pf->tmreg_lock); 494 495 return 0; 496 } 497 498 /** 499 * i40e_pps_configure - configure PPS events 500 * @ptp: ptp clock 501 * @rq: clock request 502 * @on: status 503 * 504 * Configure PPS events for external clock source. 505 * Return 0 on success or error on failure. 506 **/ 507 static int i40e_pps_configure(struct ptp_clock_info *ptp, 508 struct ptp_clock_request *rq, 509 int on) 510 { 511 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 512 513 if (!!on) 514 i40e_ptp_set_1pps_signal_hw(pf); 515 516 return 0; 517 } 518 519 /** 520 * i40e_pin_state - determine PIN state 521 * @index: PIN index 522 * @func: function assigned to PIN 523 * 524 * Determine PIN state based on PIN index and function assigned. 525 * Return PIN state. 526 **/ 527 static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func) 528 { 529 enum i40e_ptp_gpio_pin_state state = off; 530 531 if (index == 0 && func == PTP_PF_EXTTS) 532 state = in_A; 533 if (index == 1 && func == PTP_PF_EXTTS) 534 state = in_B; 535 if (index == 0 && func == PTP_PF_PEROUT) 536 state = out_A; 537 if (index == 1 && func == PTP_PF_PEROUT) 538 state = out_B; 539 540 return state; 541 } 542 543 /** 544 * i40e_ptp_enable_pin - enable PINs. 545 * @pf: private board structure 546 * @chan: channel 547 * @func: PIN function 548 * @on: state 549 * 550 * Enable PTP pins for external clock source. 551 * Return 0 on success or error code on failure. 552 **/ 553 static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan, 554 enum ptp_pin_function func, int on) 555 { 556 enum i40e_ptp_gpio_pin_state *pin = NULL; 557 struct i40e_ptp_pins_settings pins; 558 int pin_index; 559 560 /* Use PF0 to set pins. Return success for user space tools */ 561 if (pf->hw.pf_id) 562 return 0; 563 564 /* Preserve previous state of pins that we don't touch */ 565 pins.sdp3_2 = pf->ptp_pins->sdp3_2; 566 pins.sdp3_3 = pf->ptp_pins->sdp3_3; 567 pins.gpio_4 = pf->ptp_pins->gpio_4; 568 569 /* To turn on the pin - find the corresponding one based on 570 * the given index. To to turn the function off - find 571 * which pin had it assigned. Don't use ptp_find_pin here 572 * because it tries to lock the pincfg_mux which is locked by 573 * ptp_pin_store() that calls here. 574 */ 575 if (on) { 576 pin_index = ptp_find_pin(pf->ptp_clock, func, chan); 577 if (pin_index < 0) 578 return -EBUSY; 579 580 switch (pin_index) { 581 case SDP3_2: 582 pin = &pins.sdp3_2; 583 break; 584 case SDP3_3: 585 pin = &pins.sdp3_3; 586 break; 587 case GPIO_4: 588 pin = &pins.gpio_4; 589 break; 590 default: 591 return -EINVAL; 592 } 593 594 *pin = i40e_pin_state(chan, func); 595 } else { 596 pins.sdp3_2 = off; 597 pins.sdp3_3 = off; 598 pins.gpio_4 = off; 599 } 600 601 return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0; 602 } 603 604 /** 605 * i40e_ptp_feature_enable - Enable external clock pins 606 * @ptp: The PTP clock structure 607 * @rq: The PTP clock request structure 608 * @on: To turn feature on/off 609 * 610 * Setting on/off PTP PPS feature for pin. 611 **/ 612 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 613 struct ptp_clock_request *rq, 614 int on) 615 { 616 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 617 618 enum ptp_pin_function func; 619 unsigned int chan; 620 621 /* TODO: Implement flags handling for EXTTS and PEROUT */ 622 switch (rq->type) { 623 case PTP_CLK_REQ_EXTTS: 624 func = PTP_PF_EXTTS; 625 chan = rq->extts.index; 626 break; 627 case PTP_CLK_REQ_PEROUT: 628 func = PTP_PF_PEROUT; 629 chan = rq->perout.index; 630 break; 631 case PTP_CLK_REQ_PPS: 632 return i40e_pps_configure(ptp, rq, on); 633 default: 634 return -EOPNOTSUPP; 635 } 636 637 return i40e_ptp_enable_pin(pf, chan, func, on); 638 } 639 640 /** 641 * i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events 642 * @pf: the PF data structure 643 * 644 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 645 * for noticed latch events. This allows the driver to keep track of the first 646 * time a latch event was noticed which will be used to help clear out Rx 647 * timestamps for packets that got dropped or lost. 648 * 649 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 650 * expected to be called only while under the ptp_rx_lock. 651 **/ 652 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 653 { 654 struct i40e_hw *hw = &pf->hw; 655 u32 prttsyn_stat, new_latch_events; 656 int i; 657 658 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 659 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 660 661 /* Update the jiffies time for any newly latched timestamp. This 662 * ensures that we store the time that we first discovered a timestamp 663 * was latched by the hardware. The service task will later determine 664 * if we should free the latch and drop that timestamp should too much 665 * time pass. This flow ensures that we only update jiffies for new 666 * events latched since the last time we checked, and not all events 667 * currently latched, so that the service task accounting remains 668 * accurate. 669 */ 670 for (i = 0; i < 4; i++) { 671 if (new_latch_events & BIT(i)) 672 pf->latch_events[i] = jiffies; 673 } 674 675 /* Finally, we store the current status of the Rx timestamp latches */ 676 pf->latch_event_flags = prttsyn_stat; 677 678 return prttsyn_stat; 679 } 680 681 /** 682 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 683 * @pf: The PF private data structure 684 * 685 * This watchdog task is scheduled to detect error case where hardware has 686 * dropped an Rx packet that was timestamped when the ring is full. The 687 * particular error is rare but leaves the device in a state unable to timestamp 688 * any future packets. 689 **/ 690 void i40e_ptp_rx_hang(struct i40e_pf *pf) 691 { 692 struct i40e_hw *hw = &pf->hw; 693 unsigned int i, cleared = 0; 694 695 /* Since we cannot turn off the Rx timestamp logic if the device is 696 * configured for Tx timestamping, we check if Rx timestamping is 697 * configured. We don't want to spuriously warn about Rx timestamp 698 * hangs if we don't care about the timestamps. 699 */ 700 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 701 return; 702 703 spin_lock_bh(&pf->ptp_rx_lock); 704 705 /* Update current latch times for Rx events */ 706 i40e_ptp_get_rx_events(pf); 707 708 /* Check all the currently latched Rx events and see whether they have 709 * been latched for over a second. It is assumed that any timestamp 710 * should have been cleared within this time, or else it was captured 711 * for a dropped frame that the driver never received. Thus, we will 712 * clear any timestamp that has been latched for over 1 second. 713 */ 714 for (i = 0; i < 4; i++) { 715 if ((pf->latch_event_flags & BIT(i)) && 716 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 717 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 718 pf->latch_event_flags &= ~BIT(i); 719 cleared++; 720 } 721 } 722 723 spin_unlock_bh(&pf->ptp_rx_lock); 724 725 /* Log a warning if more than 2 timestamps got dropped in the same 726 * check. We don't want to warn about all drops because it can occur 727 * in normal scenarios such as PTP frames on multicast addresses we 728 * aren't listening to. However, administrator should know if this is 729 * the reason packets aren't receiving timestamps. 730 */ 731 if (cleared > 2) 732 dev_dbg(&pf->pdev->dev, 733 "Dropped %d missed RXTIME timestamp events\n", 734 cleared); 735 736 /* Finally, update the rx_hwtstamp_cleared counter */ 737 pf->rx_hwtstamp_cleared += cleared; 738 } 739 740 /** 741 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 742 * @pf: The PF private data structure 743 * 744 * This watchdog task is run periodically to make sure that we clear the Tx 745 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 746 * time. It is unexpected in the normal case but if it occurs it results in 747 * permanently preventing timestamps of future packets. 748 **/ 749 void i40e_ptp_tx_hang(struct i40e_pf *pf) 750 { 751 struct sk_buff *skb; 752 753 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 754 return; 755 756 /* Nothing to do if we're not already waiting for a timestamp */ 757 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 758 return; 759 760 /* We already have a handler routine which is run when we are notified 761 * of a Tx timestamp in the hardware. If we don't get an interrupt 762 * within a second it is reasonable to assume that we never will. 763 */ 764 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 765 skb = pf->ptp_tx_skb; 766 pf->ptp_tx_skb = NULL; 767 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 768 769 /* Free the skb after we clear the bitlock */ 770 dev_kfree_skb_any(skb); 771 pf->tx_hwtstamp_timeouts++; 772 } 773 } 774 775 /** 776 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 777 * @pf: Board private structure 778 * 779 * Read the value of the Tx timestamp from the registers, convert it into a 780 * value consumable by the stack, and store that result into the shhwtstamps 781 * struct before returning it up the stack. 782 **/ 783 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 784 { 785 struct skb_shared_hwtstamps shhwtstamps; 786 struct sk_buff *skb = pf->ptp_tx_skb; 787 struct i40e_hw *hw = &pf->hw; 788 u32 hi, lo; 789 u64 ns; 790 791 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 792 return; 793 794 /* don't attempt to timestamp if we don't have an skb */ 795 if (!pf->ptp_tx_skb) 796 return; 797 798 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 799 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 800 801 ns = (((u64)hi) << 32) | lo; 802 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 803 804 /* Clear the bit lock as soon as possible after reading the register, 805 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 806 * applications might wake up and attempt to request another transmit 807 * timestamp prior to the bit lock being cleared. 808 */ 809 pf->ptp_tx_skb = NULL; 810 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 811 812 /* Notify the stack and free the skb after we've unlocked */ 813 skb_tstamp_tx(skb, &shhwtstamps); 814 dev_kfree_skb_any(skb); 815 } 816 817 /** 818 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 819 * @pf: Board private structure 820 * @skb: Particular skb to send timestamp with 821 * @index: Index into the receive timestamp registers for the timestamp 822 * 823 * The XL710 receives a notification in the receive descriptor with an offset 824 * into the set of RXTIME registers where the timestamp is for that skb. This 825 * function goes and fetches the receive timestamp from that offset, if a valid 826 * one exists. The RXTIME registers are in ns, so we must convert the result 827 * first. 828 **/ 829 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 830 { 831 u32 prttsyn_stat, hi, lo; 832 struct i40e_hw *hw; 833 u64 ns; 834 835 /* Since we cannot turn off the Rx timestamp logic if the device is 836 * doing Tx timestamping, check if Rx timestamping is configured. 837 */ 838 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 839 return; 840 841 hw = &pf->hw; 842 843 spin_lock_bh(&pf->ptp_rx_lock); 844 845 /* Get current Rx events and update latch times */ 846 prttsyn_stat = i40e_ptp_get_rx_events(pf); 847 848 /* TODO: Should we warn about missing Rx timestamp event? */ 849 if (!(prttsyn_stat & BIT(index))) { 850 spin_unlock_bh(&pf->ptp_rx_lock); 851 return; 852 } 853 854 /* Clear the latched event since we're about to read its register */ 855 pf->latch_event_flags &= ~BIT(index); 856 857 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 858 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 859 860 spin_unlock_bh(&pf->ptp_rx_lock); 861 862 ns = (((u64)hi) << 32) | lo; 863 864 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 865 } 866 867 /** 868 * i40e_ptp_set_increment - Utility function to update clock increment rate 869 * @pf: Board private structure 870 * 871 * During a link change, the DMA frequency that drives the 1588 logic will 872 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 873 * we must update the increment value per clock tick. 874 **/ 875 void i40e_ptp_set_increment(struct i40e_pf *pf) 876 { 877 struct i40e_link_status *hw_link_info; 878 struct i40e_hw *hw = &pf->hw; 879 u64 incval; 880 u32 mult; 881 882 hw_link_info = &hw->phy.link_info; 883 884 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 885 886 switch (hw_link_info->link_speed) { 887 case I40E_LINK_SPEED_10GB: 888 mult = I40E_PTP_10GB_INCVAL_MULT; 889 break; 890 case I40E_LINK_SPEED_5GB: 891 mult = I40E_PTP_5GB_INCVAL_MULT; 892 break; 893 case I40E_LINK_SPEED_1GB: 894 mult = I40E_PTP_1GB_INCVAL_MULT; 895 break; 896 case I40E_LINK_SPEED_100MB: 897 { 898 static int warn_once; 899 900 if (!warn_once) { 901 dev_warn(&pf->pdev->dev, 902 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 903 warn_once++; 904 } 905 mult = 0; 906 break; 907 } 908 case I40E_LINK_SPEED_40GB: 909 default: 910 mult = 1; 911 break; 912 } 913 914 /* The increment value is calculated by taking the base 40GbE incvalue 915 * and multiplying it by a factor based on the link speed. 916 */ 917 incval = I40E_PTP_40GB_INCVAL * mult; 918 919 /* Write the new increment value into the increment register. The 920 * hardware will not update the clock until both registers have been 921 * written. 922 */ 923 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 924 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 925 926 /* Update the base adjustement value. */ 927 WRITE_ONCE(pf->ptp_adj_mult, mult); 928 smp_mb(); /* Force the above update. */ 929 } 930 931 /** 932 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 933 * @pf: Board private structure 934 * @ifr: ioctl data 935 * 936 * Obtain the current hardware timestamping settigs as requested. To do this, 937 * keep a shadow copy of the timestamp settings rather than attempting to 938 * deconstruct it from the registers. 939 **/ 940 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 941 { 942 struct hwtstamp_config *config = &pf->tstamp_config; 943 944 if (!(pf->flags & I40E_FLAG_PTP)) 945 return -EOPNOTSUPP; 946 947 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 948 -EFAULT : 0; 949 } 950 951 /** 952 * i40e_ptp_free_pins - free memory used by PTP pins 953 * @pf: Board private structure 954 * 955 * Release memory allocated for PTP pins. 956 **/ 957 static void i40e_ptp_free_pins(struct i40e_pf *pf) 958 { 959 if (i40e_is_ptp_pin_dev(&pf->hw)) { 960 kfree(pf->ptp_pins); 961 kfree(pf->ptp_caps.pin_config); 962 pf->ptp_pins = NULL; 963 } 964 } 965 966 /** 967 * i40e_ptp_set_pin_hw - Set HW GPIO pin 968 * @hw: pointer to the hardware structure 969 * @pin: pin index 970 * @state: pin state 971 * 972 * Set status of GPIO pin for external clock handling. 973 **/ 974 static void i40e_ptp_set_pin_hw(struct i40e_hw *hw, 975 unsigned int pin, 976 enum i40e_ptp_gpio_pin_state state) 977 { 978 switch (state) { 979 case off: 980 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0); 981 break; 982 case in_A: 983 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 984 I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0); 985 break; 986 case in_B: 987 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 988 I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0); 989 break; 990 case out_A: 991 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 992 I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1); 993 break; 994 case out_B: 995 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 996 I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1); 997 break; 998 default: 999 break; 1000 } 1001 } 1002 1003 /** 1004 * i40e_ptp_set_led_hw - Set HW GPIO led 1005 * @hw: pointer to the hardware structure 1006 * @led: led index 1007 * @state: led state 1008 * 1009 * Set status of GPIO led for external clock handling. 1010 **/ 1011 static void i40e_ptp_set_led_hw(struct i40e_hw *hw, 1012 unsigned int led, 1013 enum i40e_ptp_led_pin_state state) 1014 { 1015 switch (state) { 1016 case low: 1017 wr32(hw, I40E_GLGEN_GPIO_SET, 1018 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led); 1019 break; 1020 case high: 1021 wr32(hw, I40E_GLGEN_GPIO_SET, 1022 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | 1023 I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led); 1024 break; 1025 default: 1026 break; 1027 } 1028 } 1029 1030 /** 1031 * i40e_ptp_init_leds_hw - init LEDs 1032 * @hw: pointer to a hardware structure 1033 * 1034 * Set initial state of LEDs 1035 **/ 1036 static void i40e_ptp_init_leds_hw(struct i40e_hw *hw) 1037 { 1038 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0), 1039 I40E_GLGEN_GPIO_CTL_LED_INIT); 1040 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1), 1041 I40E_GLGEN_GPIO_CTL_LED_INIT); 1042 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0), 1043 I40E_GLGEN_GPIO_CTL_LED_INIT); 1044 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1), 1045 I40E_GLGEN_GPIO_CTL_LED_INIT); 1046 } 1047 1048 /** 1049 * i40e_ptp_set_pins_hw - Set HW GPIO pins 1050 * @pf: Board private structure 1051 * 1052 * This function sets GPIO pins for PTP 1053 **/ 1054 static void i40e_ptp_set_pins_hw(struct i40e_pf *pf) 1055 { 1056 const struct i40e_ptp_pins_settings *pins = pf->ptp_pins; 1057 struct i40e_hw *hw = &pf->hw; 1058 1059 /* pin must be disabled before it may be used */ 1060 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1061 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1062 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1063 1064 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2); 1065 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3); 1066 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4); 1067 1068 i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0); 1069 i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1); 1070 i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0); 1071 i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1); 1072 1073 dev_info(&pf->pdev->dev, 1074 "PTP configuration set to: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1075 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1076 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1077 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1078 } 1079 1080 /** 1081 * i40e_ptp_set_pins - set PTP pins in HW 1082 * @pf: Board private structure 1083 * @pins: PTP pins to be applied 1084 * 1085 * Validate and set PTP pins in HW for specific PF. 1086 * Return 0 on success or negative value on error. 1087 **/ 1088 static int i40e_ptp_set_pins(struct i40e_pf *pf, 1089 struct i40e_ptp_pins_settings *pins) 1090 { 1091 enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf); 1092 int i = 0; 1093 1094 if (pin_caps == CANT_DO_PINS) 1095 return -EOPNOTSUPP; 1096 else if (pin_caps == CAN_DO_PINS) 1097 return 0; 1098 1099 if (pins->sdp3_2 == invalid) 1100 pins->sdp3_2 = pf->ptp_pins->sdp3_2; 1101 if (pins->sdp3_3 == invalid) 1102 pins->sdp3_3 = pf->ptp_pins->sdp3_3; 1103 if (pins->gpio_4 == invalid) 1104 pins->gpio_4 = pf->ptp_pins->gpio_4; 1105 while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) { 1106 if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 && 1107 pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 && 1108 pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) { 1109 pins->led2_0 = 1110 i40e_ptp_pin_led_allowed_states[i].led2_0; 1111 pins->led2_1 = 1112 i40e_ptp_pin_led_allowed_states[i].led2_1; 1113 pins->led3_0 = 1114 i40e_ptp_pin_led_allowed_states[i].led3_0; 1115 pins->led3_1 = 1116 i40e_ptp_pin_led_allowed_states[i].led3_1; 1117 break; 1118 } 1119 i++; 1120 } 1121 if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) { 1122 dev_warn(&pf->pdev->dev, 1123 "Unsupported PTP pin configuration: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1124 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1125 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1126 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1127 1128 return -EPERM; 1129 } 1130 memcpy(pf->ptp_pins, pins, sizeof(*pins)); 1131 i40e_ptp_set_pins_hw(pf); 1132 i40_ptp_reset_timing_events(pf); 1133 1134 return 0; 1135 } 1136 1137 /** 1138 * i40e_ptp_alloc_pins - allocate PTP pins structure 1139 * @pf: Board private structure 1140 * 1141 * allocate PTP pins structure 1142 **/ 1143 int i40e_ptp_alloc_pins(struct i40e_pf *pf) 1144 { 1145 if (!i40e_is_ptp_pin_dev(&pf->hw)) 1146 return 0; 1147 1148 pf->ptp_pins = 1149 kzalloc(sizeof(struct i40e_ptp_pins_settings), GFP_KERNEL); 1150 1151 if (!pf->ptp_pins) { 1152 dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n"); 1153 return -I40E_ERR_NO_MEMORY; 1154 } 1155 1156 pf->ptp_pins->sdp3_2 = off; 1157 pf->ptp_pins->sdp3_3 = off; 1158 pf->ptp_pins->gpio_4 = off; 1159 pf->ptp_pins->led2_0 = high; 1160 pf->ptp_pins->led2_1 = high; 1161 pf->ptp_pins->led3_0 = high; 1162 pf->ptp_pins->led3_1 = high; 1163 1164 /* Use PF0 to set pins in HW. Return success for user space tools */ 1165 if (pf->hw.pf_id) 1166 return 0; 1167 1168 i40e_ptp_init_leds_hw(&pf->hw); 1169 i40e_ptp_set_pins_hw(pf); 1170 1171 return 0; 1172 } 1173 1174 /** 1175 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 1176 * @pf: Board private structure 1177 * @config: hwtstamp settings requested or saved 1178 * 1179 * Control hardware registers to enter the specific mode requested by the 1180 * user. Also used during reset path to ensure that timestamp settings are 1181 * maintained. 1182 * 1183 * Note: modifies config in place, and may update the requested mode to be 1184 * more broad if the specific filter is not directly supported. 1185 **/ 1186 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 1187 struct hwtstamp_config *config) 1188 { 1189 struct i40e_hw *hw = &pf->hw; 1190 u32 tsyntype, regval; 1191 1192 /* Selects external trigger to cause event */ 1193 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1194 /* Bit 17:16 is EVNTLVL, 01B rising edge */ 1195 regval &= 0; 1196 regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT); 1197 /* regval: 0001 0000 0000 0000 0000 */ 1198 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1199 1200 /* Enabel interrupts */ 1201 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1202 regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT; 1203 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1204 1205 INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work); 1206 1207 switch (config->tx_type) { 1208 case HWTSTAMP_TX_OFF: 1209 pf->ptp_tx = false; 1210 break; 1211 case HWTSTAMP_TX_ON: 1212 pf->ptp_tx = true; 1213 break; 1214 default: 1215 return -ERANGE; 1216 } 1217 1218 switch (config->rx_filter) { 1219 case HWTSTAMP_FILTER_NONE: 1220 pf->ptp_rx = false; 1221 /* We set the type to V1, but do not enable UDP packet 1222 * recognition. In this way, we should be as close to 1223 * disabling PTP Rx timestamps as possible since V1 packets 1224 * are always UDP, since L2 packets are a V2 feature. 1225 */ 1226 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 1227 break; 1228 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1229 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1230 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1231 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 1232 return -ERANGE; 1233 pf->ptp_rx = true; 1234 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 1235 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 1236 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 1237 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1238 break; 1239 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1240 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1241 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1242 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1243 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1244 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1245 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 1246 return -ERANGE; 1247 fallthrough; 1248 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1249 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1250 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1251 pf->ptp_rx = true; 1252 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 1253 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 1254 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 1255 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 1256 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1257 } else { 1258 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1259 } 1260 break; 1261 case HWTSTAMP_FILTER_NTP_ALL: 1262 case HWTSTAMP_FILTER_ALL: 1263 default: 1264 return -ERANGE; 1265 } 1266 1267 /* Clear out all 1588-related registers to clear and unlatch them. */ 1268 spin_lock_bh(&pf->ptp_rx_lock); 1269 rd32(hw, I40E_PRTTSYN_STAT_0); 1270 rd32(hw, I40E_PRTTSYN_TXTIME_H); 1271 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 1272 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 1273 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 1274 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 1275 pf->latch_event_flags = 0; 1276 spin_unlock_bh(&pf->ptp_rx_lock); 1277 1278 /* Enable/disable the Tx timestamp interrupt based on user input. */ 1279 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1280 if (pf->ptp_tx) 1281 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1282 else 1283 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1284 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1285 1286 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 1287 if (pf->ptp_tx) 1288 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1289 else 1290 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1291 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 1292 1293 /* Although there is no simple on/off switch for Rx, we "disable" Rx 1294 * timestamps by setting to V1 only mode and clear the UDP 1295 * recognition. This ought to disable all PTP Rx timestamps as V1 1296 * packets are always over UDP. Note that software is configured to 1297 * ignore Rx timestamps via the pf->ptp_rx flag. 1298 */ 1299 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1300 /* clear everything but the enable bit */ 1301 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1302 /* now enable bits for desired Rx timestamps */ 1303 regval |= tsyntype; 1304 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1305 1306 return 0; 1307 } 1308 1309 /** 1310 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 1311 * @pf: Board private structure 1312 * @ifr: ioctl data 1313 * 1314 * Respond to the user filter requests and make the appropriate hardware 1315 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 1316 * logic, so keep track in software of whether to indicate these timestamps 1317 * or not. 1318 * 1319 * It is permissible to "upgrade" the user request to a broader filter, as long 1320 * as the user receives the timestamps they care about and the user is notified 1321 * the filter has been broadened. 1322 **/ 1323 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 1324 { 1325 struct hwtstamp_config config; 1326 int err; 1327 1328 if (!(pf->flags & I40E_FLAG_PTP)) 1329 return -EOPNOTSUPP; 1330 1331 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1332 return -EFAULT; 1333 1334 err = i40e_ptp_set_timestamp_mode(pf, &config); 1335 if (err) 1336 return err; 1337 1338 /* save these settings for future reference */ 1339 pf->tstamp_config = config; 1340 1341 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1342 -EFAULT : 0; 1343 } 1344 1345 /** 1346 * i40e_init_pin_config - initialize pins. 1347 * @pf: private board structure 1348 * 1349 * Initialize pins for external clock source. 1350 * Return 0 on success or error code on failure. 1351 **/ 1352 static int i40e_init_pin_config(struct i40e_pf *pf) 1353 { 1354 int i; 1355 1356 pf->ptp_caps.n_pins = 3; 1357 pf->ptp_caps.n_ext_ts = 2; 1358 pf->ptp_caps.pps = 1; 1359 pf->ptp_caps.n_per_out = 2; 1360 1361 pf->ptp_caps.pin_config = kcalloc(pf->ptp_caps.n_pins, 1362 sizeof(*pf->ptp_caps.pin_config), 1363 GFP_KERNEL); 1364 if (!pf->ptp_caps.pin_config) 1365 return -ENOMEM; 1366 1367 for (i = 0; i < pf->ptp_caps.n_pins; i++) { 1368 snprintf(pf->ptp_caps.pin_config[i].name, 1369 sizeof(pf->ptp_caps.pin_config[i].name), 1370 "%s", sdp_desc[i].name); 1371 pf->ptp_caps.pin_config[i].index = sdp_desc[i].index; 1372 pf->ptp_caps.pin_config[i].func = PTP_PF_NONE; 1373 pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan; 1374 } 1375 1376 pf->ptp_caps.verify = i40e_ptp_verify; 1377 pf->ptp_caps.enable = i40e_ptp_feature_enable; 1378 1379 pf->ptp_caps.pps = 1; 1380 1381 return 0; 1382 } 1383 1384 /** 1385 * i40e_ptp_create_clock - Create PTP clock device for userspace 1386 * @pf: Board private structure 1387 * 1388 * This function creates a new PTP clock device. It only creates one if we 1389 * don't already have one, so it is safe to call. Will return error if it 1390 * can't create one, but success if we already have a device. Should be used 1391 * by i40e_ptp_init to create clock initially, and prevent global resets from 1392 * creating new clock devices. 1393 **/ 1394 static long i40e_ptp_create_clock(struct i40e_pf *pf) 1395 { 1396 /* no need to create a clock device if we already have one */ 1397 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 1398 return 0; 1399 1400 strlcpy(pf->ptp_caps.name, i40e_driver_name, 1401 sizeof(pf->ptp_caps.name) - 1); 1402 pf->ptp_caps.owner = THIS_MODULE; 1403 pf->ptp_caps.max_adj = 999999999; 1404 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 1405 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 1406 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; 1407 pf->ptp_caps.settime64 = i40e_ptp_settime; 1408 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1409 int err = i40e_init_pin_config(pf); 1410 1411 if (err) 1412 return err; 1413 } 1414 1415 /* Attempt to register the clock before enabling the hardware. */ 1416 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 1417 if (IS_ERR(pf->ptp_clock)) 1418 return PTR_ERR(pf->ptp_clock); 1419 1420 /* clear the hwtstamp settings here during clock create, instead of 1421 * during regular init, so that we can maintain settings across a 1422 * reset or suspend. 1423 */ 1424 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1425 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1426 1427 /* Set the previous "reset" time to the current Kernel clock time */ 1428 ktime_get_real_ts64(&pf->ptp_prev_hw_time); 1429 pf->ptp_reset_start = ktime_get(); 1430 1431 return 0; 1432 } 1433 1434 /** 1435 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time 1436 * @pf: Board private structure 1437 * 1438 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should 1439 * be called at the end of preparing to reset, just before hardware reset 1440 * occurs, in order to preserve the PTP time as close as possible across 1441 * resets. 1442 */ 1443 void i40e_ptp_save_hw_time(struct i40e_pf *pf) 1444 { 1445 /* don't try to access the PTP clock if it's not enabled */ 1446 if (!(pf->flags & I40E_FLAG_PTP)) 1447 return; 1448 1449 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); 1450 /* Get a monotonic starting time for this reset */ 1451 pf->ptp_reset_start = ktime_get(); 1452 } 1453 1454 /** 1455 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs 1456 * @pf: Board private structure 1457 * 1458 * Restore the PTP hardware clock registers. We previously cached the PTP 1459 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, 1460 * update this value based on the time delta since the time was saved, using 1461 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. 1462 * 1463 * This ensures that the hardware clock is restored to nearly what it should 1464 * have been if a reset had not occurred. 1465 */ 1466 void i40e_ptp_restore_hw_time(struct i40e_pf *pf) 1467 { 1468 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); 1469 1470 /* Update the previous HW time with the ktime delta */ 1471 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); 1472 1473 /* Restore the hardware clock registers */ 1474 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); 1475 } 1476 1477 /** 1478 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 1479 * @pf: Board private structure 1480 * 1481 * This function sets device up for 1588 support. The first time it is run, it 1482 * will create a PHC clock device. It does not create a clock device if one 1483 * already exists. It also reconfigures the device after a reset. 1484 * 1485 * The first time a clock is created, i40e_ptp_create_clock will set 1486 * pf->ptp_prev_hw_time to the current system time. During resets, it is 1487 * expected that this timespec will be set to the last known PTP clock time, 1488 * in order to preserve the clock time as close as possible across a reset. 1489 **/ 1490 void i40e_ptp_init(struct i40e_pf *pf) 1491 { 1492 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 1493 struct i40e_hw *hw = &pf->hw; 1494 u32 pf_id; 1495 long err; 1496 1497 /* Only one PF is assigned to control 1588 logic per port. Do not 1498 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 1499 */ 1500 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 1501 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 1502 if (hw->pf_id != pf_id) { 1503 pf->flags &= ~I40E_FLAG_PTP; 1504 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 1505 __func__, 1506 netdev->name); 1507 return; 1508 } 1509 1510 mutex_init(&pf->tmreg_lock); 1511 spin_lock_init(&pf->ptp_rx_lock); 1512 1513 /* ensure we have a clock device */ 1514 err = i40e_ptp_create_clock(pf); 1515 if (err) { 1516 pf->ptp_clock = NULL; 1517 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 1518 __func__); 1519 } else if (pf->ptp_clock) { 1520 u32 regval; 1521 1522 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 1523 dev_info(&pf->pdev->dev, "PHC enabled\n"); 1524 pf->flags |= I40E_FLAG_PTP; 1525 1526 /* Ensure the clocks are running. */ 1527 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1528 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 1529 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1530 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1531 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1532 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1533 1534 /* Set the increment value per clock tick. */ 1535 i40e_ptp_set_increment(pf); 1536 1537 /* reset timestamping mode */ 1538 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 1539 1540 /* Restore the clock time based on last known value */ 1541 i40e_ptp_restore_hw_time(pf); 1542 } 1543 1544 i40e_ptp_set_1pps_signal_hw(pf); 1545 } 1546 1547 /** 1548 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 1549 * @pf: Board private structure 1550 * 1551 * This function handles the cleanup work required from the initialization by 1552 * clearing out the important information and unregistering the PHC. 1553 **/ 1554 void i40e_ptp_stop(struct i40e_pf *pf) 1555 { 1556 struct i40e_hw *hw = &pf->hw; 1557 u32 regval; 1558 1559 pf->flags &= ~I40E_FLAG_PTP; 1560 pf->ptp_tx = false; 1561 pf->ptp_rx = false; 1562 1563 if (pf->ptp_tx_skb) { 1564 struct sk_buff *skb = pf->ptp_tx_skb; 1565 1566 pf->ptp_tx_skb = NULL; 1567 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 1568 dev_kfree_skb_any(skb); 1569 } 1570 1571 if (pf->ptp_clock) { 1572 ptp_clock_unregister(pf->ptp_clock); 1573 pf->ptp_clock = NULL; 1574 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 1575 pf->vsi[pf->lan_vsi]->netdev->name); 1576 } 1577 1578 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1579 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1580 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1581 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1582 } 1583 1584 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1585 regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK; 1586 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1587 1588 /* Disable interrupts */ 1589 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1590 regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK; 1591 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1592 1593 i40e_ptp_free_pins(pf); 1594 } 1595