1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e.h" 28 #include <linux/ptp_classify.h> 29 30 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 31 * the fundamental clock design. However, the clock operations are much simpler 32 * in the XL710 because the device supports a full 64 bits of nanoseconds. 33 * Because the field is so wide, we can forgo the cycle counter and just 34 * operate with the nanosecond field directly without fear of overflow. 35 * 36 * Much like the 82599, the update period is dependent upon the link speed: 37 * At 40Gb link or no link, the period is 1.6ns. 38 * At 10Gb link, the period is multiplied by 2. (3.2ns) 39 * At 1Gb link, the period is multiplied by 20. (32ns) 40 * 1588 functionality is not supported at 100Mbps. 41 */ 42 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 43 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 44 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 45 46 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \ 47 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 48 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \ 49 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 50 51 /** 52 * i40e_ptp_read - Read the PHC time from the device 53 * @pf: Board private structure 54 * @ts: timespec structure to hold the current time value 55 * 56 * This function reads the PRTTSYN_TIME registers and stores them in a 57 * timespec. However, since the registers are 64 bits of nanoseconds, we must 58 * convert the result to a timespec before we can return. 59 **/ 60 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts) 61 { 62 struct i40e_hw *hw = &pf->hw; 63 u32 hi, lo; 64 u64 ns; 65 66 /* The timer latches on the lowest register read. */ 67 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 68 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 69 70 ns = (((u64)hi) << 32) | lo; 71 72 *ts = ns_to_timespec64(ns); 73 } 74 75 /** 76 * i40e_ptp_write - Write the PHC time to the device 77 * @pf: Board private structure 78 * @ts: timespec structure that holds the new time value 79 * 80 * This function writes the PRTTSYN_TIME registers with the user value. Since 81 * we receive a timespec from the stack, we must convert that timespec into 82 * nanoseconds before programming the registers. 83 **/ 84 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 85 { 86 struct i40e_hw *hw = &pf->hw; 87 u64 ns = timespec64_to_ns(ts); 88 89 /* The timer will not update until the high register is written, so 90 * write the low register first. 91 */ 92 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 93 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 94 } 95 96 /** 97 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 98 * @hwtstamps: Timestamp structure to update 99 * @timestamp: Timestamp from the hardware 100 * 101 * We need to convert the NIC clock value into a hwtstamp which can be used by 102 * the upper level timestamping functions. Since the timestamp is simply a 64- 103 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 104 **/ 105 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 106 u64 timestamp) 107 { 108 memset(hwtstamps, 0, sizeof(*hwtstamps)); 109 110 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 111 } 112 113 /** 114 * i40e_ptp_adjfreq - Adjust the PHC frequency 115 * @ptp: The PTP clock structure 116 * @ppb: Parts per billion adjustment from the base 117 * 118 * Adjust the frequency of the PHC by the indicated parts per billion from the 119 * base frequency. 120 **/ 121 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 122 { 123 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 124 struct i40e_hw *hw = &pf->hw; 125 u64 adj, freq, diff; 126 int neg_adj = 0; 127 128 if (ppb < 0) { 129 neg_adj = 1; 130 ppb = -ppb; 131 } 132 133 smp_mb(); /* Force any pending update before accessing. */ 134 adj = ACCESS_ONCE(pf->ptp_base_adj); 135 136 freq = adj; 137 freq *= ppb; 138 diff = div_u64(freq, 1000000000ULL); 139 140 if (neg_adj) 141 adj -= diff; 142 else 143 adj += diff; 144 145 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 146 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 147 148 return 0; 149 } 150 151 /** 152 * i40e_ptp_adjtime - Adjust the PHC time 153 * @ptp: The PTP clock structure 154 * @delta: Offset in nanoseconds to adjust the PHC time by 155 * 156 * Adjust the frequency of the PHC by the indicated parts per billion from the 157 * base frequency. 158 **/ 159 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 160 { 161 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 162 struct timespec64 now, then = ns_to_timespec64(delta); 163 unsigned long flags; 164 165 spin_lock_irqsave(&pf->tmreg_lock, flags); 166 167 i40e_ptp_read(pf, &now); 168 now = timespec64_add(now, then); 169 i40e_ptp_write(pf, (const struct timespec64 *)&now); 170 171 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 172 173 return 0; 174 } 175 176 /** 177 * i40e_ptp_gettime - Get the time of the PHC 178 * @ptp: The PTP clock structure 179 * @ts: timespec structure to hold the current time value 180 * 181 * Read the device clock and return the correct value on ns, after converting it 182 * into a timespec struct. 183 **/ 184 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 185 { 186 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 187 unsigned long flags; 188 189 spin_lock_irqsave(&pf->tmreg_lock, flags); 190 i40e_ptp_read(pf, ts); 191 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 192 193 return 0; 194 } 195 196 /** 197 * i40e_ptp_settime - Set the time of the PHC 198 * @ptp: The PTP clock structure 199 * @ts: timespec structure that holds the new time value 200 * 201 * Set the device clock to the user input value. The conversion from timespec 202 * to ns happens in the write function. 203 **/ 204 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 205 const struct timespec64 *ts) 206 { 207 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 208 unsigned long flags; 209 210 spin_lock_irqsave(&pf->tmreg_lock, flags); 211 i40e_ptp_write(pf, ts); 212 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 213 214 return 0; 215 } 216 217 /** 218 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 219 * @ptp: The PTP clock structure 220 * @rq: The requested feature to change 221 * @on: Enable/disable flag 222 * 223 * The XL710 does not support any of the ancillary features of the PHC 224 * subsystem, so this function may just return. 225 **/ 226 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 227 struct ptp_clock_request *rq, int on) 228 { 229 return -EOPNOTSUPP; 230 } 231 232 /** 233 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 234 * @vsi: The VSI with the rings relevant to 1588 235 * 236 * This watchdog task is scheduled to detect error case where hardware has 237 * dropped an Rx packet that was timestamped when the ring is full. The 238 * particular error is rare but leaves the device in a state unable to timestamp 239 * any future packets. 240 **/ 241 void i40e_ptp_rx_hang(struct i40e_vsi *vsi) 242 { 243 struct i40e_pf *pf = vsi->back; 244 struct i40e_hw *hw = &pf->hw; 245 struct i40e_ring *rx_ring; 246 unsigned long rx_event; 247 u32 prttsyn_stat; 248 int n; 249 250 /* Since we cannot turn off the Rx timestamp logic if the device is 251 * configured for Tx timestamping, we check if Rx timestamping is 252 * configured. We don't want to spuriously warn about Rx timestamp 253 * hangs if we don't care about the timestamps. 254 */ 255 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 256 return; 257 258 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 259 260 /* Unless all four receive timestamp registers are latched, we are not 261 * concerned about a possible PTP Rx hang, so just update the timeout 262 * counter and exit. 263 */ 264 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK << 265 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) | 266 (I40E_PRTTSYN_STAT_1_RXT1_MASK << 267 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) | 268 (I40E_PRTTSYN_STAT_1_RXT2_MASK << 269 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) | 270 (I40E_PRTTSYN_STAT_1_RXT3_MASK << 271 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) { 272 pf->last_rx_ptp_check = jiffies; 273 return; 274 } 275 276 /* Determine the most recent watchdog or rx_timestamp event. */ 277 rx_event = pf->last_rx_ptp_check; 278 for (n = 0; n < vsi->num_queue_pairs; n++) { 279 rx_ring = vsi->rx_rings[n]; 280 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 281 rx_event = rx_ring->last_rx_timestamp; 282 } 283 284 /* Only need to read the high RXSTMP register to clear the lock */ 285 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 286 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 287 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 288 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 289 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 290 pf->last_rx_ptp_check = jiffies; 291 pf->rx_hwtstamp_cleared++; 292 dev_warn(&vsi->back->pdev->dev, 293 "%s: clearing Rx timestamp hang\n", 294 __func__); 295 } 296 } 297 298 /** 299 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 300 * @pf: Board private structure 301 * 302 * Read the value of the Tx timestamp from the registers, convert it into a 303 * value consumable by the stack, and store that result into the shhwtstamps 304 * struct before returning it up the stack. 305 **/ 306 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 307 { 308 struct skb_shared_hwtstamps shhwtstamps; 309 struct i40e_hw *hw = &pf->hw; 310 u32 hi, lo; 311 u64 ns; 312 313 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 314 return; 315 316 /* don't attempt to timestamp if we don't have an skb */ 317 if (!pf->ptp_tx_skb) 318 return; 319 320 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 321 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 322 323 ns = (((u64)hi) << 32) | lo; 324 325 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 326 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps); 327 dev_kfree_skb_any(pf->ptp_tx_skb); 328 pf->ptp_tx_skb = NULL; 329 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 330 } 331 332 /** 333 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 334 * @pf: Board private structure 335 * @skb: Particular skb to send timestamp with 336 * @index: Index into the receive timestamp registers for the timestamp 337 * 338 * The XL710 receives a notification in the receive descriptor with an offset 339 * into the set of RXTIME registers where the timestamp is for that skb. This 340 * function goes and fetches the receive timestamp from that offset, if a valid 341 * one exists. The RXTIME registers are in ns, so we must convert the result 342 * first. 343 **/ 344 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 345 { 346 u32 prttsyn_stat, hi, lo; 347 struct i40e_hw *hw; 348 u64 ns; 349 350 /* Since we cannot turn off the Rx timestamp logic if the device is 351 * doing Tx timestamping, check if Rx timestamping is configured. 352 */ 353 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 354 return; 355 356 hw = &pf->hw; 357 358 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 359 360 if (!(prttsyn_stat & (1 << index))) 361 return; 362 363 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 364 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 365 366 ns = (((u64)hi) << 32) | lo; 367 368 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 369 } 370 371 /** 372 * i40e_ptp_set_increment - Utility function to update clock increment rate 373 * @pf: Board private structure 374 * 375 * During a link change, the DMA frequency that drives the 1588 logic will 376 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 377 * we must update the increment value per clock tick. 378 **/ 379 void i40e_ptp_set_increment(struct i40e_pf *pf) 380 { 381 struct i40e_link_status *hw_link_info; 382 struct i40e_hw *hw = &pf->hw; 383 u64 incval; 384 385 hw_link_info = &hw->phy.link_info; 386 387 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 388 389 switch (hw_link_info->link_speed) { 390 case I40E_LINK_SPEED_10GB: 391 incval = I40E_PTP_10GB_INCVAL; 392 break; 393 case I40E_LINK_SPEED_1GB: 394 incval = I40E_PTP_1GB_INCVAL; 395 break; 396 case I40E_LINK_SPEED_100MB: 397 { 398 static int warn_once; 399 400 if (!warn_once) { 401 dev_warn(&pf->pdev->dev, 402 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 403 warn_once++; 404 } 405 incval = 0; 406 break; 407 } 408 case I40E_LINK_SPEED_40GB: 409 default: 410 incval = I40E_PTP_40GB_INCVAL; 411 break; 412 } 413 414 /* Write the new increment value into the increment register. The 415 * hardware will not update the clock until both registers have been 416 * written. 417 */ 418 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 419 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 420 421 /* Update the base adjustement value. */ 422 ACCESS_ONCE(pf->ptp_base_adj) = incval; 423 smp_mb(); /* Force the above update. */ 424 } 425 426 /** 427 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 428 * @pf: Board private structure 429 * @ifreq: ioctl data 430 * 431 * Obtain the current hardware timestamping settigs as requested. To do this, 432 * keep a shadow copy of the timestamp settings rather than attempting to 433 * deconstruct it from the registers. 434 **/ 435 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 436 { 437 struct hwtstamp_config *config = &pf->tstamp_config; 438 439 if (!(pf->flags & I40E_FLAG_PTP)) 440 return -EOPNOTSUPP; 441 442 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 443 -EFAULT : 0; 444 } 445 446 /** 447 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 448 * @pf: Board private structure 449 * @config: hwtstamp settings requested or saved 450 * 451 * Control hardware registers to enter the specific mode requested by the 452 * user. Also used during reset path to ensure that timestamp settings are 453 * maintained. 454 * 455 * Note: modifies config in place, and may update the requested mode to be 456 * more broad if the specific filter is not directly supported. 457 **/ 458 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 459 struct hwtstamp_config *config) 460 { 461 struct i40e_hw *hw = &pf->hw; 462 u32 tsyntype, regval; 463 464 /* Reserved for future extensions. */ 465 if (config->flags) 466 return -EINVAL; 467 468 switch (config->tx_type) { 469 case HWTSTAMP_TX_OFF: 470 pf->ptp_tx = false; 471 break; 472 case HWTSTAMP_TX_ON: 473 pf->ptp_tx = true; 474 break; 475 default: 476 return -ERANGE; 477 } 478 479 switch (config->rx_filter) { 480 case HWTSTAMP_FILTER_NONE: 481 pf->ptp_rx = false; 482 /* We set the type to V1, but do not enable UDP packet 483 * recognition. In this way, we should be as close to 484 * disabling PTP Rx timestamps as possible since V1 packets 485 * are always UDP, since L2 packets are a V2 feature. 486 */ 487 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 488 break; 489 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 490 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 491 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 492 pf->ptp_rx = true; 493 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 494 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 495 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 496 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 497 break; 498 case HWTSTAMP_FILTER_PTP_V2_EVENT: 499 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 500 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 501 case HWTSTAMP_FILTER_PTP_V2_SYNC: 502 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 503 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 504 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 505 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 506 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 507 pf->ptp_rx = true; 508 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 509 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 | 510 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 511 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 512 break; 513 case HWTSTAMP_FILTER_ALL: 514 default: 515 return -ERANGE; 516 } 517 518 /* Clear out all 1588-related registers to clear and unlatch them. */ 519 rd32(hw, I40E_PRTTSYN_STAT_0); 520 rd32(hw, I40E_PRTTSYN_TXTIME_H); 521 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 522 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 523 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 524 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 525 526 /* Enable/disable the Tx timestamp interrupt based on user input. */ 527 regval = rd32(hw, I40E_PRTTSYN_CTL0); 528 if (pf->ptp_tx) 529 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 530 else 531 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 532 wr32(hw, I40E_PRTTSYN_CTL0, regval); 533 534 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 535 if (pf->ptp_tx) 536 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 537 else 538 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 539 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 540 541 /* Although there is no simple on/off switch for Rx, we "disable" Rx 542 * timestamps by setting to V1 only mode and clear the UDP 543 * recognition. This ought to disable all PTP Rx timestamps as V1 544 * packets are always over UDP. Note that software is configured to 545 * ignore Rx timestamps via the pf->ptp_rx flag. 546 */ 547 regval = rd32(hw, I40E_PRTTSYN_CTL1); 548 /* clear everything but the enable bit */ 549 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 550 /* now enable bits for desired Rx timestamps */ 551 regval |= tsyntype; 552 wr32(hw, I40E_PRTTSYN_CTL1, regval); 553 554 return 0; 555 } 556 557 /** 558 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 559 * @pf: Board private structure 560 * @ifreq: ioctl data 561 * 562 * Respond to the user filter requests and make the appropriate hardware 563 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 564 * logic, so keep track in software of whether to indicate these timestamps 565 * or not. 566 * 567 * It is permissible to "upgrade" the user request to a broader filter, as long 568 * as the user receives the timestamps they care about and the user is notified 569 * the filter has been broadened. 570 **/ 571 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 572 { 573 struct hwtstamp_config config; 574 int err; 575 576 if (!(pf->flags & I40E_FLAG_PTP)) 577 return -EOPNOTSUPP; 578 579 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 580 return -EFAULT; 581 582 err = i40e_ptp_set_timestamp_mode(pf, &config); 583 if (err) 584 return err; 585 586 /* save these settings for future reference */ 587 pf->tstamp_config = config; 588 589 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 590 -EFAULT : 0; 591 } 592 593 /** 594 * i40e_ptp_create_clock - Create PTP clock device for userspace 595 * @pf: Board private structure 596 * 597 * This function creates a new PTP clock device. It only creates one if we 598 * don't already have one, so it is safe to call. Will return error if it 599 * can't create one, but success if we already have a device. Should be used 600 * by i40e_ptp_init to create clock initially, and prevent global resets from 601 * creating new clock devices. 602 **/ 603 static long i40e_ptp_create_clock(struct i40e_pf *pf) 604 { 605 /* no need to create a clock device if we already have one */ 606 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 607 return 0; 608 609 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name)); 610 pf->ptp_caps.owner = THIS_MODULE; 611 pf->ptp_caps.max_adj = 999999999; 612 pf->ptp_caps.n_ext_ts = 0; 613 pf->ptp_caps.pps = 0; 614 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 615 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 616 pf->ptp_caps.gettime64 = i40e_ptp_gettime; 617 pf->ptp_caps.settime64 = i40e_ptp_settime; 618 pf->ptp_caps.enable = i40e_ptp_feature_enable; 619 620 /* Attempt to register the clock before enabling the hardware. */ 621 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 622 if (IS_ERR(pf->ptp_clock)) { 623 return PTR_ERR(pf->ptp_clock); 624 } 625 626 /* clear the hwtstamp settings here during clock create, instead of 627 * during regular init, so that we can maintain settings across a 628 * reset or suspend. 629 */ 630 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 631 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 632 633 return 0; 634 } 635 636 /** 637 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 638 * @pf: Board private structure 639 * 640 * This function sets device up for 1588 support. The first time it is run, it 641 * will create a PHC clock device. It does not create a clock device if one 642 * already exists. It also reconfigures the device after a reset. 643 **/ 644 void i40e_ptp_init(struct i40e_pf *pf) 645 { 646 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 647 struct i40e_hw *hw = &pf->hw; 648 u32 pf_id; 649 long err; 650 651 /* Only one PF is assigned to control 1588 logic per port. Do not 652 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 653 */ 654 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 655 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 656 if (hw->pf_id != pf_id) { 657 pf->flags &= ~I40E_FLAG_PTP; 658 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 659 __func__, 660 netdev->name); 661 return; 662 } 663 664 /* we have to initialize the lock first, since we can't control 665 * when the user will enter the PHC device entry points 666 */ 667 spin_lock_init(&pf->tmreg_lock); 668 669 /* ensure we have a clock device */ 670 err = i40e_ptp_create_clock(pf); 671 if (err) { 672 pf->ptp_clock = NULL; 673 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 674 __func__); 675 } else { 676 struct timespec64 ts; 677 u32 regval; 678 679 dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__, 680 netdev->name); 681 pf->flags |= I40E_FLAG_PTP; 682 683 /* Ensure the clocks are running. */ 684 regval = rd32(hw, I40E_PRTTSYN_CTL0); 685 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 686 wr32(hw, I40E_PRTTSYN_CTL0, regval); 687 regval = rd32(hw, I40E_PRTTSYN_CTL1); 688 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 689 wr32(hw, I40E_PRTTSYN_CTL1, regval); 690 691 /* Set the increment value per clock tick. */ 692 i40e_ptp_set_increment(pf); 693 694 /* reset timestamping mode */ 695 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 696 697 /* Set the clock value. */ 698 ts = ktime_to_timespec64(ktime_get_real()); 699 i40e_ptp_settime(&pf->ptp_caps, &ts); 700 } 701 } 702 703 /** 704 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 705 * @pf: Board private structure 706 * 707 * This function handles the cleanup work required from the initialization by 708 * clearing out the important information and unregistering the PHC. 709 **/ 710 void i40e_ptp_stop(struct i40e_pf *pf) 711 { 712 pf->flags &= ~I40E_FLAG_PTP; 713 pf->ptp_tx = false; 714 pf->ptp_rx = false; 715 716 if (pf->ptp_tx_skb) { 717 dev_kfree_skb_any(pf->ptp_tx_skb); 718 pf->ptp_tx_skb = NULL; 719 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 720 } 721 722 if (pf->ptp_clock) { 723 ptp_clock_unregister(pf->ptp_clock); 724 pf->ptp_clock = NULL; 725 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 726 pf->vsi[pf->lan_vsi]->netdev->name); 727 } 728 } 729