1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Driver
4  * Copyright(c) 2013 - 2014 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26 
27 #include "i40e.h"
28 #include <linux/export.h>
29 #include <linux/ptp_classify.h>
30 
31 /* The XL710 timesync is very much like Intel's 82599 design when it comes to
32  * the fundamental clock design. However, the clock operations are much simpler
33  * in the XL710 because the device supports a full 64 bits of nanoseconds.
34  * Because the field is so wide, we can forgo the cycle counter and just
35  * operate with the nanosecond field directly without fear of overflow.
36  *
37  * Much like the 82599, the update period is dependent upon the link speed:
38  * At 40Gb link or no link, the period is 1.6ns.
39  * At 10Gb link, the period is multiplied by 2. (3.2ns)
40  * At 1Gb link, the period is multiplied by 20. (32ns)
41  * 1588 functionality is not supported at 100Mbps.
42  */
43 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
44 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
45 #define I40E_PTP_1GB_INCVAL  0x2000000000ULL
46 
47 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1  (0x1 << \
48 					I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
49 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2  (0x2 << \
50 					I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
51 
52 /**
53  * i40e_ptp_read - Read the PHC time from the device
54  * @pf: Board private structure
55  * @ts: timespec structure to hold the current time value
56  *
57  * This function reads the PRTTSYN_TIME registers and stores them in a
58  * timespec. However, since the registers are 64 bits of nanoseconds, we must
59  * convert the result to a timespec before we can return.
60  **/
61 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts)
62 {
63 	struct i40e_hw *hw = &pf->hw;
64 	u32 hi, lo;
65 	u64 ns;
66 
67 	/* The timer latches on the lowest register read. */
68 	lo = rd32(hw, I40E_PRTTSYN_TIME_L);
69 	hi = rd32(hw, I40E_PRTTSYN_TIME_H);
70 
71 	ns = (((u64)hi) << 32) | lo;
72 
73 	*ts = ns_to_timespec(ns);
74 }
75 
76 /**
77  * i40e_ptp_write - Write the PHC time to the device
78  * @pf: Board private structure
79  * @ts: timespec structure that holds the new time value
80  *
81  * This function writes the PRTTSYN_TIME registers with the user value. Since
82  * we receive a timespec from the stack, we must convert that timespec into
83  * nanoseconds before programming the registers.
84  **/
85 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts)
86 {
87 	struct i40e_hw *hw = &pf->hw;
88 	u64 ns = timespec_to_ns(ts);
89 
90 	/* The timer will not update until the high register is written, so
91 	 * write the low register first.
92 	 */
93 	wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
94 	wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
95 }
96 
97 /**
98  * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
99  * @hwtstamps: Timestamp structure to update
100  * @timestamp: Timestamp from the hardware
101  *
102  * We need to convert the NIC clock value into a hwtstamp which can be used by
103  * the upper level timestamping functions. Since the timestamp is simply a 64-
104  * bit nanosecond value, we can call ns_to_ktime directly to handle this.
105  **/
106 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
107 					 u64 timestamp)
108 {
109 	memset(hwtstamps, 0, sizeof(*hwtstamps));
110 
111 	hwtstamps->hwtstamp = ns_to_ktime(timestamp);
112 }
113 
114 /**
115  * i40e_ptp_adjfreq - Adjust the PHC frequency
116  * @ptp: The PTP clock structure
117  * @ppb: Parts per billion adjustment from the base
118  *
119  * Adjust the frequency of the PHC by the indicated parts per billion from the
120  * base frequency.
121  **/
122 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
123 {
124 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
125 	struct i40e_hw *hw = &pf->hw;
126 	u64 adj, freq, diff;
127 	int neg_adj = 0;
128 
129 	if (ppb < 0) {
130 		neg_adj = 1;
131 		ppb = -ppb;
132 	}
133 
134 	smp_mb(); /* Force any pending update before accessing. */
135 	adj = ACCESS_ONCE(pf->ptp_base_adj);
136 
137 	freq = adj;
138 	freq *= ppb;
139 	diff = div_u64(freq, 1000000000ULL);
140 
141 	if (neg_adj)
142 		adj -= diff;
143 	else
144 		adj += diff;
145 
146 	wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
147 	wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
148 
149 	return 0;
150 }
151 
152 /**
153  * i40e_ptp_adjtime - Adjust the PHC time
154  * @ptp: The PTP clock structure
155  * @delta: Offset in nanoseconds to adjust the PHC time by
156  *
157  * Adjust the frequency of the PHC by the indicated parts per billion from the
158  * base frequency.
159  **/
160 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
161 {
162 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
163 	struct timespec now, then = ns_to_timespec(delta);
164 	unsigned long flags;
165 
166 	spin_lock_irqsave(&pf->tmreg_lock, flags);
167 
168 	i40e_ptp_read(pf, &now);
169 	now = timespec_add(now, then);
170 	i40e_ptp_write(pf, (const struct timespec *)&now);
171 
172 	spin_unlock_irqrestore(&pf->tmreg_lock, flags);
173 
174 	return 0;
175 }
176 
177 /**
178  * i40e_ptp_gettime - Get the time of the PHC
179  * @ptp: The PTP clock structure
180  * @ts: timespec structure to hold the current time value
181  *
182  * Read the device clock and return the correct value on ns, after converting it
183  * into a timespec struct.
184  **/
185 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
186 {
187 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
188 	unsigned long flags;
189 
190 	spin_lock_irqsave(&pf->tmreg_lock, flags);
191 	i40e_ptp_read(pf, ts);
192 	spin_unlock_irqrestore(&pf->tmreg_lock, flags);
193 
194 	return 0;
195 }
196 
197 /**
198  * i40e_ptp_settime - Set the time of the PHC
199  * @ptp: The PTP clock structure
200  * @ts: timespec structure that holds the new time value
201  *
202  * Set the device clock to the user input value. The conversion from timespec
203  * to ns happens in the write function.
204  **/
205 static int i40e_ptp_settime(struct ptp_clock_info *ptp,
206 			    const struct timespec *ts)
207 {
208 	struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
209 	unsigned long flags;
210 
211 	spin_lock_irqsave(&pf->tmreg_lock, flags);
212 	i40e_ptp_write(pf, ts);
213 	spin_unlock_irqrestore(&pf->tmreg_lock, flags);
214 
215 	return 0;
216 }
217 
218 /**
219  * i40e_ptp_enable - Enable/disable ancillary features of the PHC subsystem
220  * @ptp: The PTP clock structure
221  * @rq: The requested feature to change
222  * @on: Enable/disable flag
223  *
224  * The XL710 does not support any of the ancillary features of the PHC
225  * subsystem, so this function may just return.
226  **/
227 static int i40e_ptp_enable(struct ptp_clock_info *ptp,
228 			   struct ptp_clock_request *rq, int on)
229 {
230 	return -EOPNOTSUPP;
231 }
232 
233 /**
234  * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
235  * @vsi: The VSI with the rings relevant to 1588
236  *
237  * This watchdog task is scheduled to detect error case where hardware has
238  * dropped an Rx packet that was timestamped when the ring is full. The
239  * particular error is rare but leaves the device in a state unable to timestamp
240  * any future packets.
241  **/
242 void i40e_ptp_rx_hang(struct i40e_vsi *vsi)
243 {
244 	struct i40e_pf *pf = vsi->back;
245 	struct i40e_hw *hw = &pf->hw;
246 	struct i40e_ring *rx_ring;
247 	unsigned long rx_event;
248 	u32 prttsyn_stat;
249 	int n;
250 
251 	if (pf->flags & I40E_FLAG_PTP)
252 		return;
253 
254 	prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
255 
256 	/* Unless all four receive timestamp registers are latched, we are not
257 	 * concerned about a possible PTP Rx hang, so just update the timeout
258 	 * counter and exit.
259 	 */
260 	if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK <<
261 			       I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
262 			      (I40E_PRTTSYN_STAT_1_RXT1_MASK <<
263 			       I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
264 			      (I40E_PRTTSYN_STAT_1_RXT2_MASK <<
265 			       I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
266 			      (I40E_PRTTSYN_STAT_1_RXT3_MASK <<
267 			       I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) {
268 		pf->last_rx_ptp_check = jiffies;
269 		return;
270 	}
271 
272 	/* Determine the most recent watchdog or rx_timestamp event. */
273 	rx_event = pf->last_rx_ptp_check;
274 	for (n = 0; n < vsi->num_queue_pairs; n++) {
275 		rx_ring = vsi->rx_rings[n];
276 		if (time_after(rx_ring->last_rx_timestamp, rx_event))
277 			rx_event = rx_ring->last_rx_timestamp;
278 	}
279 
280 	/* Only need to read the high RXSTMP register to clear the lock */
281 	if (time_is_before_jiffies(rx_event + 5 * HZ)) {
282 		rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
283 		rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
284 		rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
285 		rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
286 		pf->last_rx_ptp_check = jiffies;
287 		pf->rx_hwtstamp_cleared++;
288 		dev_warn(&vsi->back->pdev->dev,
289 			 "%s: clearing Rx timestamp hang\n",
290 			 __func__);
291 	}
292 }
293 
294 /**
295  * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
296  * @pf: Board private structure
297  *
298  * Read the value of the Tx timestamp from the registers, convert it into a
299  * value consumable by the stack, and store that result into the shhwtstamps
300  * struct before returning it up the stack.
301  **/
302 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
303 {
304 	struct skb_shared_hwtstamps shhwtstamps;
305 	struct i40e_hw *hw = &pf->hw;
306 	u32 hi, lo;
307 	u64 ns;
308 
309 	lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
310 	hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
311 
312 	ns = (((u64)hi) << 32) | lo;
313 
314 	i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
315 	skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps);
316 	dev_kfree_skb_any(pf->ptp_tx_skb);
317 	pf->ptp_tx_skb = NULL;
318 }
319 
320 /**
321  * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
322  * @pf: Board private structure
323  * @skb: Particular skb to send timestamp with
324  * @index: Index into the receive timestamp registers for the timestamp
325  *
326  * The XL710 receives a notification in the receive descriptor with an offset
327  * into the set of RXTIME registers where the timestamp is for that skb. This
328  * function goes and fetches the receive timestamp from that offset, if a valid
329  * one exists. The RXTIME registers are in ns, so we must convert the result
330  * first.
331  **/
332 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
333 {
334 	u32 prttsyn_stat, hi, lo;
335 	struct i40e_hw *hw;
336 	u64 ns;
337 
338 	/* Since we cannot turn off the Rx timestamp logic if the device is
339 	 * doing Tx timestamping, check if Rx timestamping is configured.
340 	 */
341 	if (!pf->ptp_rx)
342 		return;
343 
344 	hw = &pf->hw;
345 
346 	prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
347 
348 	if (!(prttsyn_stat & (1 << index)))
349 		return;
350 
351 	lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
352 	hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
353 
354 	ns = (((u64)hi) << 32) | lo;
355 
356 	i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
357 }
358 
359 /**
360  * i40e_ptp_set_increment - Utility function to update clock increment rate
361  * @pf: Board private structure
362  *
363  * During a link change, the DMA frequency that drives the 1588 logic will
364  * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
365  * we must update the increment value per clock tick.
366  **/
367 void i40e_ptp_set_increment(struct i40e_pf *pf)
368 {
369 	struct i40e_link_status *hw_link_info;
370 	struct i40e_hw *hw = &pf->hw;
371 	u64 incval;
372 
373 	hw_link_info = &hw->phy.link_info;
374 
375 	i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
376 
377 	switch (hw_link_info->link_speed) {
378 	case I40E_LINK_SPEED_10GB:
379 		incval = I40E_PTP_10GB_INCVAL;
380 		break;
381 	case I40E_LINK_SPEED_1GB:
382 		incval = I40E_PTP_1GB_INCVAL;
383 		break;
384 	case I40E_LINK_SPEED_100MB:
385 		dev_warn(&pf->pdev->dev,
386 			 "%s: 1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n",
387 			 __func__);
388 		incval = 0;
389 		break;
390 	case I40E_LINK_SPEED_40GB:
391 	default:
392 		incval = I40E_PTP_40GB_INCVAL;
393 		break;
394 	}
395 
396 	/* Write the new increment value into the increment register. The
397 	 * hardware will not update the clock until both registers have been
398 	 * written.
399 	 */
400 	wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
401 	wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
402 
403 	/* Update the base adjustement value. */
404 	ACCESS_ONCE(pf->ptp_base_adj) = incval;
405 	smp_mb(); /* Force the above update. */
406 }
407 
408 /**
409  * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
410  * @pf: Board private structure
411  * @ifreq: ioctl data
412  *
413  * Obtain the current hardware timestamping settigs as requested. To do this,
414  * keep a shadow copy of the timestamp settings rather than attempting to
415  * deconstruct it from the registers.
416  **/
417 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
418 {
419 	struct hwtstamp_config *config = &pf->tstamp_config;
420 
421 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
422 		-EFAULT : 0;
423 }
424 
425 /**
426  * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
427  * @pf: Board private structure
428  * @ifreq: ioctl data
429  *
430  * Respond to the user filter requests and make the appropriate hardware
431  * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
432  * logic, so keep track in software of whether to indicate these timestamps
433  * or not.
434  *
435  * It is permissible to "upgrade" the user request to a broader filter, as long
436  * as the user receives the timestamps they care about and the user is notified
437  * the filter has been broadened.
438  **/
439 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
440 {
441 	struct i40e_hw *hw = &pf->hw;
442 	struct hwtstamp_config *config = &pf->tstamp_config;
443 	u32 pf_id, tsyntype, regval;
444 
445 	if (copy_from_user(config, ifr->ifr_data, sizeof(*config)))
446 		return -EFAULT;
447 
448 	/* Reserved for future extensions. */
449 	if (config->flags)
450 		return -EINVAL;
451 
452 	/* Confirm that 1588 is supported on this PF. */
453 	pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
454 		I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
455 	if (hw->pf_id != pf_id)
456 		return -EINVAL;
457 
458 	switch (config->tx_type) {
459 	case HWTSTAMP_TX_OFF:
460 		pf->ptp_tx = false;
461 		break;
462 	case HWTSTAMP_TX_ON:
463 		pf->ptp_tx = true;
464 		break;
465 	default:
466 		return -ERANGE;
467 	}
468 
469 	switch (config->rx_filter) {
470 	case HWTSTAMP_FILTER_NONE:
471 		pf->ptp_rx = false;
472 		tsyntype = 0;
473 		break;
474 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
475 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
476 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
477 		pf->ptp_rx = true;
478 		tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
479 			   I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
480 			   I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
481 		config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
482 		break;
483 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
484 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
485 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
486 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
487 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
488 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
489 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
490 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
491 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
492 		pf->ptp_rx = true;
493 		tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
494 			   I40E_PRTTSYN_CTL1_TSYNTYPE_V2 |
495 			   I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
496 		config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
497 		break;
498 	case HWTSTAMP_FILTER_ALL:
499 	default:
500 		return -ERANGE;
501 	}
502 
503 	/* Clear out all 1588-related registers to clear and unlatch them. */
504 	rd32(hw, I40E_PRTTSYN_STAT_0);
505 	rd32(hw, I40E_PRTTSYN_TXTIME_H);
506 	rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
507 	rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
508 	rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
509 	rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
510 
511 	/* Enable/disable the Tx timestamp interrupt based on user input. */
512 	regval = rd32(hw, I40E_PRTTSYN_CTL0);
513 	if (pf->ptp_tx)
514 		regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
515 	else
516 		regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
517 	wr32(hw, I40E_PRTTSYN_CTL0, regval);
518 
519 	regval = rd32(hw, I40E_PFINT_ICR0_ENA);
520 	if (pf->ptp_tx)
521 		regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
522 	else
523 		regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
524 	wr32(hw, I40E_PFINT_ICR0_ENA, regval);
525 
526 	/* There is no simple on/off switch for Rx. To "disable" Rx support,
527 	 * ignore any received timestamps, rather than turn off the clock.
528 	 */
529 	if (pf->ptp_rx) {
530 		regval = rd32(hw, I40E_PRTTSYN_CTL1);
531 		/* clear everything but the enable bit */
532 		regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
533 		/* now enable bits for desired Rx timestamps */
534 		regval |= tsyntype;
535 		wr32(hw, I40E_PRTTSYN_CTL1, regval);
536 	}
537 
538 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
539 		-EFAULT : 0;
540 }
541 
542 /**
543  * i40e_ptp_init - Initialize the 1588 support and register the PHC
544  * @pf: Board private structure
545  *
546  * This function registers the device clock as a PHC. If it is successful, it
547  * starts the clock in the hardware.
548  **/
549 void i40e_ptp_init(struct i40e_pf *pf)
550 {
551 	struct i40e_hw *hw = &pf->hw;
552 	struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
553 
554 	strncpy(pf->ptp_caps.name, "i40e", sizeof(pf->ptp_caps.name));
555 	pf->ptp_caps.owner = THIS_MODULE;
556 	pf->ptp_caps.max_adj = 999999999;
557 	pf->ptp_caps.n_ext_ts = 0;
558 	pf->ptp_caps.pps = 0;
559 	pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
560 	pf->ptp_caps.adjtime = i40e_ptp_adjtime;
561 	pf->ptp_caps.gettime = i40e_ptp_gettime;
562 	pf->ptp_caps.settime = i40e_ptp_settime;
563 	pf->ptp_caps.enable = i40e_ptp_enable;
564 
565 	/* Attempt to register the clock before enabling the hardware. */
566 	pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
567 	if (IS_ERR(pf->ptp_clock)) {
568 		pf->ptp_clock = NULL;
569 		dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
570 			__func__);
571 	} else {
572 		struct timespec ts;
573 		u32 regval;
574 
575 		spin_lock_init(&pf->tmreg_lock);
576 
577 		dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__,
578 			 netdev->name);
579 		pf->flags |= I40E_FLAG_PTP;
580 
581 		/* Ensure the clocks are running. */
582 		regval = rd32(hw, I40E_PRTTSYN_CTL0);
583 		regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
584 		wr32(hw, I40E_PRTTSYN_CTL0, regval);
585 		regval = rd32(hw, I40E_PRTTSYN_CTL1);
586 		regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
587 		wr32(hw, I40E_PRTTSYN_CTL1, regval);
588 
589 		/* Set the increment value per clock tick. */
590 		i40e_ptp_set_increment(pf);
591 
592 		/* reset the tstamp_config */
593 		memset(&pf->tstamp_config, 0, sizeof(pf->tstamp_config));
594 
595 		/* Set the clock value. */
596 		ts = ktime_to_timespec(ktime_get_real());
597 		i40e_ptp_settime(&pf->ptp_caps, &ts);
598 	}
599 }
600 
601 /**
602  * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
603  * @pf: Board private structure
604  *
605  * This function handles the cleanup work required from the initialization by
606  * clearing out the important information and unregistering the PHC.
607  **/
608 void i40e_ptp_stop(struct i40e_pf *pf)
609 {
610 	pf->flags &= ~I40E_FLAG_PTP;
611 	pf->ptp_tx = false;
612 	pf->ptp_rx = false;
613 
614 	if (pf->ptp_tx_skb) {
615 		dev_kfree_skb_any(pf->ptp_tx_skb);
616 		pf->ptp_tx_skb = NULL;
617 	}
618 
619 	if (pf->ptp_clock) {
620 		ptp_clock_unregister(pf->ptp_clock);
621 		pf->ptp_clock = NULL;
622 		dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
623 			 pf->vsi[pf->lan_vsi]->netdev->name);
624 	}
625 }
626