1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include <linux/ptp_classify.h> 6 7 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 8 * the fundamental clock design. However, the clock operations are much simpler 9 * in the XL710 because the device supports a full 64 bits of nanoseconds. 10 * Because the field is so wide, we can forgo the cycle counter and just 11 * operate with the nanosecond field directly without fear of overflow. 12 * 13 * Much like the 82599, the update period is dependent upon the link speed: 14 * At 40Gb link or no link, the period is 1.6ns. 15 * At 10Gb link, the period is multiplied by 2. (3.2ns) 16 * At 1Gb link, the period is multiplied by 20. (32ns) 17 * 1588 functionality is not supported at 100Mbps. 18 */ 19 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 20 #define I40E_PTP_10GB_INCVAL_MULT 2 21 #define I40E_PTP_1GB_INCVAL_MULT 20 22 23 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 24 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 25 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 26 27 /** 28 * i40e_ptp_read - Read the PHC time from the device 29 * @pf: Board private structure 30 * @ts: timespec structure to hold the current time value 31 * 32 * This function reads the PRTTSYN_TIME registers and stores them in a 33 * timespec. However, since the registers are 64 bits of nanoseconds, we must 34 * convert the result to a timespec before we can return. 35 **/ 36 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts) 37 { 38 struct i40e_hw *hw = &pf->hw; 39 u32 hi, lo; 40 u64 ns; 41 42 /* The timer latches on the lowest register read. */ 43 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 44 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 45 46 ns = (((u64)hi) << 32) | lo; 47 48 *ts = ns_to_timespec64(ns); 49 } 50 51 /** 52 * i40e_ptp_write - Write the PHC time to the device 53 * @pf: Board private structure 54 * @ts: timespec structure that holds the new time value 55 * 56 * This function writes the PRTTSYN_TIME registers with the user value. Since 57 * we receive a timespec from the stack, we must convert that timespec into 58 * nanoseconds before programming the registers. 59 **/ 60 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 61 { 62 struct i40e_hw *hw = &pf->hw; 63 u64 ns = timespec64_to_ns(ts); 64 65 /* The timer will not update until the high register is written, so 66 * write the low register first. 67 */ 68 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 69 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 70 } 71 72 /** 73 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 74 * @hwtstamps: Timestamp structure to update 75 * @timestamp: Timestamp from the hardware 76 * 77 * We need to convert the NIC clock value into a hwtstamp which can be used by 78 * the upper level timestamping functions. Since the timestamp is simply a 64- 79 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 80 **/ 81 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 82 u64 timestamp) 83 { 84 memset(hwtstamps, 0, sizeof(*hwtstamps)); 85 86 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 87 } 88 89 /** 90 * i40e_ptp_adjfreq - Adjust the PHC frequency 91 * @ptp: The PTP clock structure 92 * @ppb: Parts per billion adjustment from the base 93 * 94 * Adjust the frequency of the PHC by the indicated parts per billion from the 95 * base frequency. 96 **/ 97 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 98 { 99 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 100 struct i40e_hw *hw = &pf->hw; 101 u64 adj, freq, diff; 102 int neg_adj = 0; 103 104 if (ppb < 0) { 105 neg_adj = 1; 106 ppb = -ppb; 107 } 108 109 freq = I40E_PTP_40GB_INCVAL; 110 freq *= ppb; 111 diff = div_u64(freq, 1000000000ULL); 112 113 if (neg_adj) 114 adj = I40E_PTP_40GB_INCVAL - diff; 115 else 116 adj = I40E_PTP_40GB_INCVAL + diff; 117 118 /* At some link speeds, the base incval is so large that directly 119 * multiplying by ppb would result in arithmetic overflow even when 120 * using a u64. Avoid this by instead calculating the new incval 121 * always in terms of the 40GbE clock rate and then multiplying by the 122 * link speed factor afterwards. This does result in slightly lower 123 * precision at lower link speeds, but it is fairly minor. 124 */ 125 smp_mb(); /* Force any pending update before accessing. */ 126 adj *= READ_ONCE(pf->ptp_adj_mult); 127 128 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 129 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 130 131 return 0; 132 } 133 134 /** 135 * i40e_ptp_adjtime - Adjust the PHC time 136 * @ptp: The PTP clock structure 137 * @delta: Offset in nanoseconds to adjust the PHC time by 138 * 139 * Adjust the frequency of the PHC by the indicated parts per billion from the 140 * base frequency. 141 **/ 142 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 143 { 144 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 145 struct timespec64 now; 146 147 mutex_lock(&pf->tmreg_lock); 148 149 i40e_ptp_read(pf, &now); 150 timespec64_add_ns(&now, delta); 151 i40e_ptp_write(pf, (const struct timespec64 *)&now); 152 153 mutex_unlock(&pf->tmreg_lock); 154 155 return 0; 156 } 157 158 /** 159 * i40e_ptp_gettime - Get the time of the PHC 160 * @ptp: The PTP clock structure 161 * @ts: timespec structure to hold the current time value 162 * 163 * Read the device clock and return the correct value on ns, after converting it 164 * into a timespec struct. 165 **/ 166 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 167 { 168 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 169 170 mutex_lock(&pf->tmreg_lock); 171 i40e_ptp_read(pf, ts); 172 mutex_unlock(&pf->tmreg_lock); 173 174 return 0; 175 } 176 177 /** 178 * i40e_ptp_settime - Set the time of the PHC 179 * @ptp: The PTP clock structure 180 * @ts: timespec structure that holds the new time value 181 * 182 * Set the device clock to the user input value. The conversion from timespec 183 * to ns happens in the write function. 184 **/ 185 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 186 const struct timespec64 *ts) 187 { 188 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 189 190 mutex_lock(&pf->tmreg_lock); 191 i40e_ptp_write(pf, ts); 192 mutex_unlock(&pf->tmreg_lock); 193 194 return 0; 195 } 196 197 /** 198 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 199 * @ptp: The PTP clock structure 200 * @rq: The requested feature to change 201 * @on: Enable/disable flag 202 * 203 * The XL710 does not support any of the ancillary features of the PHC 204 * subsystem, so this function may just return. 205 **/ 206 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 207 struct ptp_clock_request *rq, int on) 208 { 209 return -EOPNOTSUPP; 210 } 211 212 /** 213 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events 214 * @pf: the PF data structure 215 * 216 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 217 * for noticed latch events. This allows the driver to keep track of the first 218 * time a latch event was noticed which will be used to help clear out Rx 219 * timestamps for packets that got dropped or lost. 220 * 221 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 222 * expected to be called only while under the ptp_rx_lock. 223 **/ 224 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 225 { 226 struct i40e_hw *hw = &pf->hw; 227 u32 prttsyn_stat, new_latch_events; 228 int i; 229 230 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 231 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 232 233 /* Update the jiffies time for any newly latched timestamp. This 234 * ensures that we store the time that we first discovered a timestamp 235 * was latched by the hardware. The service task will later determine 236 * if we should free the latch and drop that timestamp should too much 237 * time pass. This flow ensures that we only update jiffies for new 238 * events latched since the last time we checked, and not all events 239 * currently latched, so that the service task accounting remains 240 * accurate. 241 */ 242 for (i = 0; i < 4; i++) { 243 if (new_latch_events & BIT(i)) 244 pf->latch_events[i] = jiffies; 245 } 246 247 /* Finally, we store the current status of the Rx timestamp latches */ 248 pf->latch_event_flags = prttsyn_stat; 249 250 return prttsyn_stat; 251 } 252 253 /** 254 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 255 * @pf: The PF private data structure 256 * @vsi: The VSI with the rings relevant to 1588 257 * 258 * This watchdog task is scheduled to detect error case where hardware has 259 * dropped an Rx packet that was timestamped when the ring is full. The 260 * particular error is rare but leaves the device in a state unable to timestamp 261 * any future packets. 262 **/ 263 void i40e_ptp_rx_hang(struct i40e_pf *pf) 264 { 265 struct i40e_hw *hw = &pf->hw; 266 unsigned int i, cleared = 0; 267 268 /* Since we cannot turn off the Rx timestamp logic if the device is 269 * configured for Tx timestamping, we check if Rx timestamping is 270 * configured. We don't want to spuriously warn about Rx timestamp 271 * hangs if we don't care about the timestamps. 272 */ 273 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 274 return; 275 276 spin_lock_bh(&pf->ptp_rx_lock); 277 278 /* Update current latch times for Rx events */ 279 i40e_ptp_get_rx_events(pf); 280 281 /* Check all the currently latched Rx events and see whether they have 282 * been latched for over a second. It is assumed that any timestamp 283 * should have been cleared within this time, or else it was captured 284 * for a dropped frame that the driver never received. Thus, we will 285 * clear any timestamp that has been latched for over 1 second. 286 */ 287 for (i = 0; i < 4; i++) { 288 if ((pf->latch_event_flags & BIT(i)) && 289 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 290 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 291 pf->latch_event_flags &= ~BIT(i); 292 cleared++; 293 } 294 } 295 296 spin_unlock_bh(&pf->ptp_rx_lock); 297 298 /* Log a warning if more than 2 timestamps got dropped in the same 299 * check. We don't want to warn about all drops because it can occur 300 * in normal scenarios such as PTP frames on multicast addresses we 301 * aren't listening to. However, administrator should know if this is 302 * the reason packets aren't receiving timestamps. 303 */ 304 if (cleared > 2) 305 dev_dbg(&pf->pdev->dev, 306 "Dropped %d missed RXTIME timestamp events\n", 307 cleared); 308 309 /* Finally, update the rx_hwtstamp_cleared counter */ 310 pf->rx_hwtstamp_cleared += cleared; 311 } 312 313 /** 314 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 315 * @pf: The PF private data structure 316 * 317 * This watchdog task is run periodically to make sure that we clear the Tx 318 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 319 * time. It is unexpected in the normal case but if it occurs it results in 320 * permanently preventing timestamps of future packets. 321 **/ 322 void i40e_ptp_tx_hang(struct i40e_pf *pf) 323 { 324 struct sk_buff *skb; 325 326 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 327 return; 328 329 /* Nothing to do if we're not already waiting for a timestamp */ 330 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 331 return; 332 333 /* We already have a handler routine which is run when we are notified 334 * of a Tx timestamp in the hardware. If we don't get an interrupt 335 * within a second it is reasonable to assume that we never will. 336 */ 337 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 338 skb = pf->ptp_tx_skb; 339 pf->ptp_tx_skb = NULL; 340 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 341 342 /* Free the skb after we clear the bitlock */ 343 dev_kfree_skb_any(skb); 344 pf->tx_hwtstamp_timeouts++; 345 } 346 } 347 348 /** 349 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 350 * @pf: Board private structure 351 * 352 * Read the value of the Tx timestamp from the registers, convert it into a 353 * value consumable by the stack, and store that result into the shhwtstamps 354 * struct before returning it up the stack. 355 **/ 356 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 357 { 358 struct skb_shared_hwtstamps shhwtstamps; 359 struct sk_buff *skb = pf->ptp_tx_skb; 360 struct i40e_hw *hw = &pf->hw; 361 u32 hi, lo; 362 u64 ns; 363 364 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 365 return; 366 367 /* don't attempt to timestamp if we don't have an skb */ 368 if (!pf->ptp_tx_skb) 369 return; 370 371 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 372 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 373 374 ns = (((u64)hi) << 32) | lo; 375 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 376 377 /* Clear the bit lock as soon as possible after reading the register, 378 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 379 * applications might wake up and attempt to request another transmit 380 * timestamp prior to the bit lock being cleared. 381 */ 382 pf->ptp_tx_skb = NULL; 383 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 384 385 /* Notify the stack and free the skb after we've unlocked */ 386 skb_tstamp_tx(skb, &shhwtstamps); 387 dev_kfree_skb_any(skb); 388 } 389 390 /** 391 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 392 * @pf: Board private structure 393 * @skb: Particular skb to send timestamp with 394 * @index: Index into the receive timestamp registers for the timestamp 395 * 396 * The XL710 receives a notification in the receive descriptor with an offset 397 * into the set of RXTIME registers where the timestamp is for that skb. This 398 * function goes and fetches the receive timestamp from that offset, if a valid 399 * one exists. The RXTIME registers are in ns, so we must convert the result 400 * first. 401 **/ 402 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 403 { 404 u32 prttsyn_stat, hi, lo; 405 struct i40e_hw *hw; 406 u64 ns; 407 408 /* Since we cannot turn off the Rx timestamp logic if the device is 409 * doing Tx timestamping, check if Rx timestamping is configured. 410 */ 411 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 412 return; 413 414 hw = &pf->hw; 415 416 spin_lock_bh(&pf->ptp_rx_lock); 417 418 /* Get current Rx events and update latch times */ 419 prttsyn_stat = i40e_ptp_get_rx_events(pf); 420 421 /* TODO: Should we warn about missing Rx timestamp event? */ 422 if (!(prttsyn_stat & BIT(index))) { 423 spin_unlock_bh(&pf->ptp_rx_lock); 424 return; 425 } 426 427 /* Clear the latched event since we're about to read its register */ 428 pf->latch_event_flags &= ~BIT(index); 429 430 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 431 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 432 433 spin_unlock_bh(&pf->ptp_rx_lock); 434 435 ns = (((u64)hi) << 32) | lo; 436 437 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 438 } 439 440 /** 441 * i40e_ptp_set_increment - Utility function to update clock increment rate 442 * @pf: Board private structure 443 * 444 * During a link change, the DMA frequency that drives the 1588 logic will 445 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 446 * we must update the increment value per clock tick. 447 **/ 448 void i40e_ptp_set_increment(struct i40e_pf *pf) 449 { 450 struct i40e_link_status *hw_link_info; 451 struct i40e_hw *hw = &pf->hw; 452 u64 incval; 453 u32 mult; 454 455 hw_link_info = &hw->phy.link_info; 456 457 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 458 459 switch (hw_link_info->link_speed) { 460 case I40E_LINK_SPEED_10GB: 461 mult = I40E_PTP_10GB_INCVAL_MULT; 462 break; 463 case I40E_LINK_SPEED_1GB: 464 mult = I40E_PTP_1GB_INCVAL_MULT; 465 break; 466 case I40E_LINK_SPEED_100MB: 467 { 468 static int warn_once; 469 470 if (!warn_once) { 471 dev_warn(&pf->pdev->dev, 472 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 473 warn_once++; 474 } 475 mult = 0; 476 break; 477 } 478 case I40E_LINK_SPEED_40GB: 479 default: 480 mult = 1; 481 break; 482 } 483 484 /* The increment value is calculated by taking the base 40GbE incvalue 485 * and multiplying it by a factor based on the link speed. 486 */ 487 incval = I40E_PTP_40GB_INCVAL * mult; 488 489 /* Write the new increment value into the increment register. The 490 * hardware will not update the clock until both registers have been 491 * written. 492 */ 493 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 494 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 495 496 /* Update the base adjustement value. */ 497 WRITE_ONCE(pf->ptp_adj_mult, mult); 498 smp_mb(); /* Force the above update. */ 499 } 500 501 /** 502 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 503 * @pf: Board private structure 504 * @ifr: ioctl data 505 * 506 * Obtain the current hardware timestamping settigs as requested. To do this, 507 * keep a shadow copy of the timestamp settings rather than attempting to 508 * deconstruct it from the registers. 509 **/ 510 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 511 { 512 struct hwtstamp_config *config = &pf->tstamp_config; 513 514 if (!(pf->flags & I40E_FLAG_PTP)) 515 return -EOPNOTSUPP; 516 517 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 518 -EFAULT : 0; 519 } 520 521 /** 522 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 523 * @pf: Board private structure 524 * @config: hwtstamp settings requested or saved 525 * 526 * Control hardware registers to enter the specific mode requested by the 527 * user. Also used during reset path to ensure that timestamp settings are 528 * maintained. 529 * 530 * Note: modifies config in place, and may update the requested mode to be 531 * more broad if the specific filter is not directly supported. 532 **/ 533 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 534 struct hwtstamp_config *config) 535 { 536 struct i40e_hw *hw = &pf->hw; 537 u32 tsyntype, regval; 538 539 /* Reserved for future extensions. */ 540 if (config->flags) 541 return -EINVAL; 542 543 switch (config->tx_type) { 544 case HWTSTAMP_TX_OFF: 545 pf->ptp_tx = false; 546 break; 547 case HWTSTAMP_TX_ON: 548 pf->ptp_tx = true; 549 break; 550 default: 551 return -ERANGE; 552 } 553 554 switch (config->rx_filter) { 555 case HWTSTAMP_FILTER_NONE: 556 pf->ptp_rx = false; 557 /* We set the type to V1, but do not enable UDP packet 558 * recognition. In this way, we should be as close to 559 * disabling PTP Rx timestamps as possible since V1 packets 560 * are always UDP, since L2 packets are a V2 feature. 561 */ 562 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 563 break; 564 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 565 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 566 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 567 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 568 return -ERANGE; 569 pf->ptp_rx = true; 570 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 571 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 572 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 573 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 574 break; 575 case HWTSTAMP_FILTER_PTP_V2_EVENT: 576 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 577 case HWTSTAMP_FILTER_PTP_V2_SYNC: 578 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 579 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 580 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 581 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 582 return -ERANGE; 583 /* fall through */ 584 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 585 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 586 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 587 pf->ptp_rx = true; 588 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 589 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 590 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 591 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 592 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 593 } else { 594 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 595 } 596 break; 597 case HWTSTAMP_FILTER_NTP_ALL: 598 case HWTSTAMP_FILTER_ALL: 599 default: 600 return -ERANGE; 601 } 602 603 /* Clear out all 1588-related registers to clear and unlatch them. */ 604 spin_lock_bh(&pf->ptp_rx_lock); 605 rd32(hw, I40E_PRTTSYN_STAT_0); 606 rd32(hw, I40E_PRTTSYN_TXTIME_H); 607 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 608 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 609 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 610 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 611 pf->latch_event_flags = 0; 612 spin_unlock_bh(&pf->ptp_rx_lock); 613 614 /* Enable/disable the Tx timestamp interrupt based on user input. */ 615 regval = rd32(hw, I40E_PRTTSYN_CTL0); 616 if (pf->ptp_tx) 617 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 618 else 619 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 620 wr32(hw, I40E_PRTTSYN_CTL0, regval); 621 622 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 623 if (pf->ptp_tx) 624 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 625 else 626 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 627 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 628 629 /* Although there is no simple on/off switch for Rx, we "disable" Rx 630 * timestamps by setting to V1 only mode and clear the UDP 631 * recognition. This ought to disable all PTP Rx timestamps as V1 632 * packets are always over UDP. Note that software is configured to 633 * ignore Rx timestamps via the pf->ptp_rx flag. 634 */ 635 regval = rd32(hw, I40E_PRTTSYN_CTL1); 636 /* clear everything but the enable bit */ 637 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 638 /* now enable bits for desired Rx timestamps */ 639 regval |= tsyntype; 640 wr32(hw, I40E_PRTTSYN_CTL1, regval); 641 642 return 0; 643 } 644 645 /** 646 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 647 * @pf: Board private structure 648 * @ifr: ioctl data 649 * 650 * Respond to the user filter requests and make the appropriate hardware 651 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 652 * logic, so keep track in software of whether to indicate these timestamps 653 * or not. 654 * 655 * It is permissible to "upgrade" the user request to a broader filter, as long 656 * as the user receives the timestamps they care about and the user is notified 657 * the filter has been broadened. 658 **/ 659 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 660 { 661 struct hwtstamp_config config; 662 int err; 663 664 if (!(pf->flags & I40E_FLAG_PTP)) 665 return -EOPNOTSUPP; 666 667 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 668 return -EFAULT; 669 670 err = i40e_ptp_set_timestamp_mode(pf, &config); 671 if (err) 672 return err; 673 674 /* save these settings for future reference */ 675 pf->tstamp_config = config; 676 677 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 678 -EFAULT : 0; 679 } 680 681 /** 682 * i40e_ptp_create_clock - Create PTP clock device for userspace 683 * @pf: Board private structure 684 * 685 * This function creates a new PTP clock device. It only creates one if we 686 * don't already have one, so it is safe to call. Will return error if it 687 * can't create one, but success if we already have a device. Should be used 688 * by i40e_ptp_init to create clock initially, and prevent global resets from 689 * creating new clock devices. 690 **/ 691 static long i40e_ptp_create_clock(struct i40e_pf *pf) 692 { 693 /* no need to create a clock device if we already have one */ 694 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 695 return 0; 696 697 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name)); 698 pf->ptp_caps.owner = THIS_MODULE; 699 pf->ptp_caps.max_adj = 999999999; 700 pf->ptp_caps.n_ext_ts = 0; 701 pf->ptp_caps.pps = 0; 702 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 703 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 704 pf->ptp_caps.gettime64 = i40e_ptp_gettime; 705 pf->ptp_caps.settime64 = i40e_ptp_settime; 706 pf->ptp_caps.enable = i40e_ptp_feature_enable; 707 708 /* Attempt to register the clock before enabling the hardware. */ 709 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 710 if (IS_ERR(pf->ptp_clock)) 711 return PTR_ERR(pf->ptp_clock); 712 713 /* clear the hwtstamp settings here during clock create, instead of 714 * during regular init, so that we can maintain settings across a 715 * reset or suspend. 716 */ 717 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 718 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 719 720 return 0; 721 } 722 723 /** 724 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 725 * @pf: Board private structure 726 * 727 * This function sets device up for 1588 support. The first time it is run, it 728 * will create a PHC clock device. It does not create a clock device if one 729 * already exists. It also reconfigures the device after a reset. 730 **/ 731 void i40e_ptp_init(struct i40e_pf *pf) 732 { 733 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 734 struct i40e_hw *hw = &pf->hw; 735 u32 pf_id; 736 long err; 737 738 /* Only one PF is assigned to control 1588 logic per port. Do not 739 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 740 */ 741 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 742 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 743 if (hw->pf_id != pf_id) { 744 pf->flags &= ~I40E_FLAG_PTP; 745 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 746 __func__, 747 netdev->name); 748 return; 749 } 750 751 mutex_init(&pf->tmreg_lock); 752 spin_lock_init(&pf->ptp_rx_lock); 753 754 /* ensure we have a clock device */ 755 err = i40e_ptp_create_clock(pf); 756 if (err) { 757 pf->ptp_clock = NULL; 758 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 759 __func__); 760 } else if (pf->ptp_clock) { 761 struct timespec64 ts; 762 u32 regval; 763 764 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 765 dev_info(&pf->pdev->dev, "PHC enabled\n"); 766 pf->flags |= I40E_FLAG_PTP; 767 768 /* Ensure the clocks are running. */ 769 regval = rd32(hw, I40E_PRTTSYN_CTL0); 770 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 771 wr32(hw, I40E_PRTTSYN_CTL0, regval); 772 regval = rd32(hw, I40E_PRTTSYN_CTL1); 773 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 774 wr32(hw, I40E_PRTTSYN_CTL1, regval); 775 776 /* Set the increment value per clock tick. */ 777 i40e_ptp_set_increment(pf); 778 779 /* reset timestamping mode */ 780 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 781 782 /* Set the clock value. */ 783 ts = ktime_to_timespec64(ktime_get_real()); 784 i40e_ptp_settime(&pf->ptp_caps, &ts); 785 } 786 } 787 788 /** 789 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 790 * @pf: Board private structure 791 * 792 * This function handles the cleanup work required from the initialization by 793 * clearing out the important information and unregistering the PHC. 794 **/ 795 void i40e_ptp_stop(struct i40e_pf *pf) 796 { 797 pf->flags &= ~I40E_FLAG_PTP; 798 pf->ptp_tx = false; 799 pf->ptp_rx = false; 800 801 if (pf->ptp_tx_skb) { 802 struct sk_buff *skb = pf->ptp_tx_skb; 803 804 pf->ptp_tx_skb = NULL; 805 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 806 dev_kfree_skb_any(skb); 807 } 808 809 if (pf->ptp_clock) { 810 ptp_clock_unregister(pf->ptp_clock); 811 pf->ptp_clock = NULL; 812 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 813 pf->vsi[pf->lan_vsi]->netdev->name); 814 } 815 } 816