1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e.h" 28 #include <linux/ptp_classify.h> 29 30 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 31 * the fundamental clock design. However, the clock operations are much simpler 32 * in the XL710 because the device supports a full 64 bits of nanoseconds. 33 * Because the field is so wide, we can forgo the cycle counter and just 34 * operate with the nanosecond field directly without fear of overflow. 35 * 36 * Much like the 82599, the update period is dependent upon the link speed: 37 * At 40Gb link or no link, the period is 1.6ns. 38 * At 10Gb link, the period is multiplied by 2. (3.2ns) 39 * At 1Gb link, the period is multiplied by 20. (32ns) 40 * 1588 functionality is not supported at 100Mbps. 41 */ 42 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 43 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 44 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 45 46 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 47 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 48 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 49 50 /** 51 * i40e_ptp_read - Read the PHC time from the device 52 * @pf: Board private structure 53 * @ts: timespec structure to hold the current time value 54 * 55 * This function reads the PRTTSYN_TIME registers and stores them in a 56 * timespec. However, since the registers are 64 bits of nanoseconds, we must 57 * convert the result to a timespec before we can return. 58 **/ 59 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts) 60 { 61 struct i40e_hw *hw = &pf->hw; 62 u32 hi, lo; 63 u64 ns; 64 65 /* The timer latches on the lowest register read. */ 66 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 67 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 68 69 ns = (((u64)hi) << 32) | lo; 70 71 *ts = ns_to_timespec64(ns); 72 } 73 74 /** 75 * i40e_ptp_write - Write the PHC time to the device 76 * @pf: Board private structure 77 * @ts: timespec structure that holds the new time value 78 * 79 * This function writes the PRTTSYN_TIME registers with the user value. Since 80 * we receive a timespec from the stack, we must convert that timespec into 81 * nanoseconds before programming the registers. 82 **/ 83 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 84 { 85 struct i40e_hw *hw = &pf->hw; 86 u64 ns = timespec64_to_ns(ts); 87 88 /* The timer will not update until the high register is written, so 89 * write the low register first. 90 */ 91 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 92 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 93 } 94 95 /** 96 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 97 * @hwtstamps: Timestamp structure to update 98 * @timestamp: Timestamp from the hardware 99 * 100 * We need to convert the NIC clock value into a hwtstamp which can be used by 101 * the upper level timestamping functions. Since the timestamp is simply a 64- 102 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 103 **/ 104 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 105 u64 timestamp) 106 { 107 memset(hwtstamps, 0, sizeof(*hwtstamps)); 108 109 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 110 } 111 112 /** 113 * i40e_ptp_adjfreq - Adjust the PHC frequency 114 * @ptp: The PTP clock structure 115 * @ppb: Parts per billion adjustment from the base 116 * 117 * Adjust the frequency of the PHC by the indicated parts per billion from the 118 * base frequency. 119 **/ 120 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 121 { 122 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 123 struct i40e_hw *hw = &pf->hw; 124 u64 adj, freq, diff; 125 int neg_adj = 0; 126 127 if (ppb < 0) { 128 neg_adj = 1; 129 ppb = -ppb; 130 } 131 132 smp_mb(); /* Force any pending update before accessing. */ 133 adj = ACCESS_ONCE(pf->ptp_base_adj); 134 135 freq = adj; 136 freq *= ppb; 137 diff = div_u64(freq, 1000000000ULL); 138 139 if (neg_adj) 140 adj -= diff; 141 else 142 adj += diff; 143 144 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 145 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 146 147 return 0; 148 } 149 150 /** 151 * i40e_ptp_adjtime - Adjust the PHC time 152 * @ptp: The PTP clock structure 153 * @delta: Offset in nanoseconds to adjust the PHC time by 154 * 155 * Adjust the frequency of the PHC by the indicated parts per billion from the 156 * base frequency. 157 **/ 158 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 159 { 160 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 161 struct timespec64 now, then = ns_to_timespec64(delta); 162 unsigned long flags; 163 164 spin_lock_irqsave(&pf->tmreg_lock, flags); 165 166 i40e_ptp_read(pf, &now); 167 now = timespec64_add(now, then); 168 i40e_ptp_write(pf, (const struct timespec64 *)&now); 169 170 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 171 172 return 0; 173 } 174 175 /** 176 * i40e_ptp_gettime - Get the time of the PHC 177 * @ptp: The PTP clock structure 178 * @ts: timespec structure to hold the current time value 179 * 180 * Read the device clock and return the correct value on ns, after converting it 181 * into a timespec struct. 182 **/ 183 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 184 { 185 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 186 unsigned long flags; 187 188 spin_lock_irqsave(&pf->tmreg_lock, flags); 189 i40e_ptp_read(pf, ts); 190 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 191 192 return 0; 193 } 194 195 /** 196 * i40e_ptp_settime - Set the time of the PHC 197 * @ptp: The PTP clock structure 198 * @ts: timespec structure that holds the new time value 199 * 200 * Set the device clock to the user input value. The conversion from timespec 201 * to ns happens in the write function. 202 **/ 203 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 204 const struct timespec64 *ts) 205 { 206 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 207 unsigned long flags; 208 209 spin_lock_irqsave(&pf->tmreg_lock, flags); 210 i40e_ptp_write(pf, ts); 211 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 212 213 return 0; 214 } 215 216 /** 217 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 218 * @ptp: The PTP clock structure 219 * @rq: The requested feature to change 220 * @on: Enable/disable flag 221 * 222 * The XL710 does not support any of the ancillary features of the PHC 223 * subsystem, so this function may just return. 224 **/ 225 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 226 struct ptp_clock_request *rq, int on) 227 { 228 return -EOPNOTSUPP; 229 } 230 231 /** 232 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 233 * @vsi: The VSI with the rings relevant to 1588 234 * 235 * This watchdog task is scheduled to detect error case where hardware has 236 * dropped an Rx packet that was timestamped when the ring is full. The 237 * particular error is rare but leaves the device in a state unable to timestamp 238 * any future packets. 239 **/ 240 void i40e_ptp_rx_hang(struct i40e_vsi *vsi) 241 { 242 struct i40e_pf *pf = vsi->back; 243 struct i40e_hw *hw = &pf->hw; 244 struct i40e_ring *rx_ring; 245 unsigned long rx_event; 246 u32 prttsyn_stat; 247 int n; 248 249 /* Since we cannot turn off the Rx timestamp logic if the device is 250 * configured for Tx timestamping, we check if Rx timestamping is 251 * configured. We don't want to spuriously warn about Rx timestamp 252 * hangs if we don't care about the timestamps. 253 */ 254 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 255 return; 256 257 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 258 259 /* Unless all four receive timestamp registers are latched, we are not 260 * concerned about a possible PTP Rx hang, so just update the timeout 261 * counter and exit. 262 */ 263 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK << 264 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) | 265 (I40E_PRTTSYN_STAT_1_RXT1_MASK << 266 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) | 267 (I40E_PRTTSYN_STAT_1_RXT2_MASK << 268 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) | 269 (I40E_PRTTSYN_STAT_1_RXT3_MASK << 270 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) { 271 pf->last_rx_ptp_check = jiffies; 272 return; 273 } 274 275 /* Determine the most recent watchdog or rx_timestamp event. */ 276 rx_event = pf->last_rx_ptp_check; 277 for (n = 0; n < vsi->num_queue_pairs; n++) { 278 rx_ring = vsi->rx_rings[n]; 279 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 280 rx_event = rx_ring->last_rx_timestamp; 281 } 282 283 /* Only need to read the high RXSTMP register to clear the lock */ 284 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 285 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 286 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 287 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 288 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 289 pf->last_rx_ptp_check = jiffies; 290 pf->rx_hwtstamp_cleared++; 291 dev_warn(&vsi->back->pdev->dev, 292 "%s: clearing Rx timestamp hang\n", 293 __func__); 294 } 295 } 296 297 /** 298 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 299 * @pf: Board private structure 300 * 301 * Read the value of the Tx timestamp from the registers, convert it into a 302 * value consumable by the stack, and store that result into the shhwtstamps 303 * struct before returning it up the stack. 304 **/ 305 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 306 { 307 struct skb_shared_hwtstamps shhwtstamps; 308 struct i40e_hw *hw = &pf->hw; 309 u32 hi, lo; 310 u64 ns; 311 312 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 313 return; 314 315 /* don't attempt to timestamp if we don't have an skb */ 316 if (!pf->ptp_tx_skb) 317 return; 318 319 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 320 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 321 322 ns = (((u64)hi) << 32) | lo; 323 324 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 325 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps); 326 dev_kfree_skb_any(pf->ptp_tx_skb); 327 pf->ptp_tx_skb = NULL; 328 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 329 } 330 331 /** 332 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 333 * @pf: Board private structure 334 * @skb: Particular skb to send timestamp with 335 * @index: Index into the receive timestamp registers for the timestamp 336 * 337 * The XL710 receives a notification in the receive descriptor with an offset 338 * into the set of RXTIME registers where the timestamp is for that skb. This 339 * function goes and fetches the receive timestamp from that offset, if a valid 340 * one exists. The RXTIME registers are in ns, so we must convert the result 341 * first. 342 **/ 343 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 344 { 345 u32 prttsyn_stat, hi, lo; 346 struct i40e_hw *hw; 347 u64 ns; 348 349 /* Since we cannot turn off the Rx timestamp logic if the device is 350 * doing Tx timestamping, check if Rx timestamping is configured. 351 */ 352 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 353 return; 354 355 hw = &pf->hw; 356 357 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 358 359 if (!(prttsyn_stat & BIT(index))) 360 return; 361 362 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 363 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 364 365 ns = (((u64)hi) << 32) | lo; 366 367 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 368 } 369 370 /** 371 * i40e_ptp_set_increment - Utility function to update clock increment rate 372 * @pf: Board private structure 373 * 374 * During a link change, the DMA frequency that drives the 1588 logic will 375 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 376 * we must update the increment value per clock tick. 377 **/ 378 void i40e_ptp_set_increment(struct i40e_pf *pf) 379 { 380 struct i40e_link_status *hw_link_info; 381 struct i40e_hw *hw = &pf->hw; 382 u64 incval; 383 384 hw_link_info = &hw->phy.link_info; 385 386 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 387 388 switch (hw_link_info->link_speed) { 389 case I40E_LINK_SPEED_10GB: 390 incval = I40E_PTP_10GB_INCVAL; 391 break; 392 case I40E_LINK_SPEED_1GB: 393 incval = I40E_PTP_1GB_INCVAL; 394 break; 395 case I40E_LINK_SPEED_100MB: 396 { 397 static int warn_once; 398 399 if (!warn_once) { 400 dev_warn(&pf->pdev->dev, 401 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 402 warn_once++; 403 } 404 incval = 0; 405 break; 406 } 407 case I40E_LINK_SPEED_40GB: 408 default: 409 incval = I40E_PTP_40GB_INCVAL; 410 break; 411 } 412 413 /* Write the new increment value into the increment register. The 414 * hardware will not update the clock until both registers have been 415 * written. 416 */ 417 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 418 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 419 420 /* Update the base adjustement value. */ 421 ACCESS_ONCE(pf->ptp_base_adj) = incval; 422 smp_mb(); /* Force the above update. */ 423 } 424 425 /** 426 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 427 * @pf: Board private structure 428 * @ifreq: ioctl data 429 * 430 * Obtain the current hardware timestamping settigs as requested. To do this, 431 * keep a shadow copy of the timestamp settings rather than attempting to 432 * deconstruct it from the registers. 433 **/ 434 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 435 { 436 struct hwtstamp_config *config = &pf->tstamp_config; 437 438 if (!(pf->flags & I40E_FLAG_PTP)) 439 return -EOPNOTSUPP; 440 441 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 442 -EFAULT : 0; 443 } 444 445 /** 446 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 447 * @pf: Board private structure 448 * @config: hwtstamp settings requested or saved 449 * 450 * Control hardware registers to enter the specific mode requested by the 451 * user. Also used during reset path to ensure that timestamp settings are 452 * maintained. 453 * 454 * Note: modifies config in place, and may update the requested mode to be 455 * more broad if the specific filter is not directly supported. 456 **/ 457 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 458 struct hwtstamp_config *config) 459 { 460 struct i40e_hw *hw = &pf->hw; 461 u32 tsyntype, regval; 462 463 /* Reserved for future extensions. */ 464 if (config->flags) 465 return -EINVAL; 466 467 switch (config->tx_type) { 468 case HWTSTAMP_TX_OFF: 469 pf->ptp_tx = false; 470 break; 471 case HWTSTAMP_TX_ON: 472 pf->ptp_tx = true; 473 break; 474 default: 475 return -ERANGE; 476 } 477 478 switch (config->rx_filter) { 479 case HWTSTAMP_FILTER_NONE: 480 pf->ptp_rx = false; 481 /* We set the type to V1, but do not enable UDP packet 482 * recognition. In this way, we should be as close to 483 * disabling PTP Rx timestamps as possible since V1 packets 484 * are always UDP, since L2 packets are a V2 feature. 485 */ 486 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 487 break; 488 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 489 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 490 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 491 pf->ptp_rx = true; 492 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 493 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 494 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 495 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 496 break; 497 case HWTSTAMP_FILTER_PTP_V2_EVENT: 498 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 500 case HWTSTAMP_FILTER_PTP_V2_SYNC: 501 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 502 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 503 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 504 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 505 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 506 pf->ptp_rx = true; 507 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 508 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 | 509 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 510 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 511 break; 512 case HWTSTAMP_FILTER_ALL: 513 default: 514 return -ERANGE; 515 } 516 517 /* Clear out all 1588-related registers to clear and unlatch them. */ 518 rd32(hw, I40E_PRTTSYN_STAT_0); 519 rd32(hw, I40E_PRTTSYN_TXTIME_H); 520 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 521 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 522 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 523 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 524 525 /* Enable/disable the Tx timestamp interrupt based on user input. */ 526 regval = rd32(hw, I40E_PRTTSYN_CTL0); 527 if (pf->ptp_tx) 528 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 529 else 530 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 531 wr32(hw, I40E_PRTTSYN_CTL0, regval); 532 533 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 534 if (pf->ptp_tx) 535 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 536 else 537 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 538 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 539 540 /* Although there is no simple on/off switch for Rx, we "disable" Rx 541 * timestamps by setting to V1 only mode and clear the UDP 542 * recognition. This ought to disable all PTP Rx timestamps as V1 543 * packets are always over UDP. Note that software is configured to 544 * ignore Rx timestamps via the pf->ptp_rx flag. 545 */ 546 regval = rd32(hw, I40E_PRTTSYN_CTL1); 547 /* clear everything but the enable bit */ 548 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 549 /* now enable bits for desired Rx timestamps */ 550 regval |= tsyntype; 551 wr32(hw, I40E_PRTTSYN_CTL1, regval); 552 553 return 0; 554 } 555 556 /** 557 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 558 * @pf: Board private structure 559 * @ifreq: ioctl data 560 * 561 * Respond to the user filter requests and make the appropriate hardware 562 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 563 * logic, so keep track in software of whether to indicate these timestamps 564 * or not. 565 * 566 * It is permissible to "upgrade" the user request to a broader filter, as long 567 * as the user receives the timestamps they care about and the user is notified 568 * the filter has been broadened. 569 **/ 570 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 571 { 572 struct hwtstamp_config config; 573 int err; 574 575 if (!(pf->flags & I40E_FLAG_PTP)) 576 return -EOPNOTSUPP; 577 578 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 579 return -EFAULT; 580 581 err = i40e_ptp_set_timestamp_mode(pf, &config); 582 if (err) 583 return err; 584 585 /* save these settings for future reference */ 586 pf->tstamp_config = config; 587 588 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 589 -EFAULT : 0; 590 } 591 592 /** 593 * i40e_ptp_create_clock - Create PTP clock device for userspace 594 * @pf: Board private structure 595 * 596 * This function creates a new PTP clock device. It only creates one if we 597 * don't already have one, so it is safe to call. Will return error if it 598 * can't create one, but success if we already have a device. Should be used 599 * by i40e_ptp_init to create clock initially, and prevent global resets from 600 * creating new clock devices. 601 **/ 602 static long i40e_ptp_create_clock(struct i40e_pf *pf) 603 { 604 /* no need to create a clock device if we already have one */ 605 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 606 return 0; 607 608 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name)); 609 pf->ptp_caps.owner = THIS_MODULE; 610 pf->ptp_caps.max_adj = 999999999; 611 pf->ptp_caps.n_ext_ts = 0; 612 pf->ptp_caps.pps = 0; 613 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 614 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 615 pf->ptp_caps.gettime64 = i40e_ptp_gettime; 616 pf->ptp_caps.settime64 = i40e_ptp_settime; 617 pf->ptp_caps.enable = i40e_ptp_feature_enable; 618 619 /* Attempt to register the clock before enabling the hardware. */ 620 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 621 if (IS_ERR(pf->ptp_clock)) 622 return PTR_ERR(pf->ptp_clock); 623 624 /* clear the hwtstamp settings here during clock create, instead of 625 * during regular init, so that we can maintain settings across a 626 * reset or suspend. 627 */ 628 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 629 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 630 631 return 0; 632 } 633 634 /** 635 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 636 * @pf: Board private structure 637 * 638 * This function sets device up for 1588 support. The first time it is run, it 639 * will create a PHC clock device. It does not create a clock device if one 640 * already exists. It also reconfigures the device after a reset. 641 **/ 642 void i40e_ptp_init(struct i40e_pf *pf) 643 { 644 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 645 struct i40e_hw *hw = &pf->hw; 646 u32 pf_id; 647 long err; 648 649 /* Only one PF is assigned to control 1588 logic per port. Do not 650 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 651 */ 652 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 653 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 654 if (hw->pf_id != pf_id) { 655 pf->flags &= ~I40E_FLAG_PTP; 656 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 657 __func__, 658 netdev->name); 659 return; 660 } 661 662 /* we have to initialize the lock first, since we can't control 663 * when the user will enter the PHC device entry points 664 */ 665 spin_lock_init(&pf->tmreg_lock); 666 667 /* ensure we have a clock device */ 668 err = i40e_ptp_create_clock(pf); 669 if (err) { 670 pf->ptp_clock = NULL; 671 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 672 __func__); 673 } else { 674 struct timespec64 ts; 675 u32 regval; 676 677 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 678 dev_info(&pf->pdev->dev, "PHC enabled\n"); 679 pf->flags |= I40E_FLAG_PTP; 680 681 /* Ensure the clocks are running. */ 682 regval = rd32(hw, I40E_PRTTSYN_CTL0); 683 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 684 wr32(hw, I40E_PRTTSYN_CTL0, regval); 685 regval = rd32(hw, I40E_PRTTSYN_CTL1); 686 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 687 wr32(hw, I40E_PRTTSYN_CTL1, regval); 688 689 /* Set the increment value per clock tick. */ 690 i40e_ptp_set_increment(pf); 691 692 /* reset timestamping mode */ 693 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 694 695 /* Set the clock value. */ 696 ts = ktime_to_timespec64(ktime_get_real()); 697 i40e_ptp_settime(&pf->ptp_caps, &ts); 698 } 699 } 700 701 /** 702 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 703 * @pf: Board private structure 704 * 705 * This function handles the cleanup work required from the initialization by 706 * clearing out the important information and unregistering the PHC. 707 **/ 708 void i40e_ptp_stop(struct i40e_pf *pf) 709 { 710 pf->flags &= ~I40E_FLAG_PTP; 711 pf->ptp_tx = false; 712 pf->ptp_rx = false; 713 714 if (pf->ptp_tx_skb) { 715 dev_kfree_skb_any(pf->ptp_tx_skb); 716 pf->ptp_tx_skb = NULL; 717 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, &pf->state); 718 } 719 720 if (pf->ptp_clock) { 721 ptp_clock_unregister(pf->ptp_clock); 722 pf->ptp_clock = NULL; 723 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 724 pf->vsi[pf->lan_vsi]->netdev->name); 725 } 726 } 727