1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include <linux/ptp_classify.h> 6 7 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 8 * the fundamental clock design. However, the clock operations are much simpler 9 * in the XL710 because the device supports a full 64 bits of nanoseconds. 10 * Because the field is so wide, we can forgo the cycle counter and just 11 * operate with the nanosecond field directly without fear of overflow. 12 * 13 * Much like the 82599, the update period is dependent upon the link speed: 14 * At 40Gb link or no link, the period is 1.6ns. 15 * At 10Gb link, the period is multiplied by 2. (3.2ns) 16 * At 1Gb link, the period is multiplied by 20. (32ns) 17 * 1588 functionality is not supported at 100Mbps. 18 */ 19 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 20 #define I40E_PTP_10GB_INCVAL_MULT 2 21 #define I40E_PTP_1GB_INCVAL_MULT 20 22 23 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 24 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 25 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 26 27 /** 28 * i40e_ptp_read - Read the PHC time from the device 29 * @pf: Board private structure 30 * @ts: timespec structure to hold the current time value 31 * @sts: structure to hold the system time before and after reading the PHC 32 * 33 * This function reads the PRTTSYN_TIME registers and stores them in a 34 * timespec. However, since the registers are 64 bits of nanoseconds, we must 35 * convert the result to a timespec before we can return. 36 **/ 37 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, 38 struct ptp_system_timestamp *sts) 39 { 40 struct i40e_hw *hw = &pf->hw; 41 u32 hi, lo; 42 u64 ns; 43 44 /* The timer latches on the lowest register read. */ 45 ptp_read_system_prets(sts); 46 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 47 ptp_read_system_postts(sts); 48 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 49 50 ns = (((u64)hi) << 32) | lo; 51 52 *ts = ns_to_timespec64(ns); 53 } 54 55 /** 56 * i40e_ptp_write - Write the PHC time to the device 57 * @pf: Board private structure 58 * @ts: timespec structure that holds the new time value 59 * 60 * This function writes the PRTTSYN_TIME registers with the user value. Since 61 * we receive a timespec from the stack, we must convert that timespec into 62 * nanoseconds before programming the registers. 63 **/ 64 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 65 { 66 struct i40e_hw *hw = &pf->hw; 67 u64 ns = timespec64_to_ns(ts); 68 69 /* The timer will not update until the high register is written, so 70 * write the low register first. 71 */ 72 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 73 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 74 } 75 76 /** 77 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 78 * @hwtstamps: Timestamp structure to update 79 * @timestamp: Timestamp from the hardware 80 * 81 * We need to convert the NIC clock value into a hwtstamp which can be used by 82 * the upper level timestamping functions. Since the timestamp is simply a 64- 83 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 84 **/ 85 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 86 u64 timestamp) 87 { 88 memset(hwtstamps, 0, sizeof(*hwtstamps)); 89 90 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 91 } 92 93 /** 94 * i40e_ptp_adjfreq - Adjust the PHC frequency 95 * @ptp: The PTP clock structure 96 * @ppb: Parts per billion adjustment from the base 97 * 98 * Adjust the frequency of the PHC by the indicated parts per billion from the 99 * base frequency. 100 **/ 101 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 102 { 103 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 104 struct i40e_hw *hw = &pf->hw; 105 u64 adj, freq, diff; 106 int neg_adj = 0; 107 108 if (ppb < 0) { 109 neg_adj = 1; 110 ppb = -ppb; 111 } 112 113 freq = I40E_PTP_40GB_INCVAL; 114 freq *= ppb; 115 diff = div_u64(freq, 1000000000ULL); 116 117 if (neg_adj) 118 adj = I40E_PTP_40GB_INCVAL - diff; 119 else 120 adj = I40E_PTP_40GB_INCVAL + diff; 121 122 /* At some link speeds, the base incval is so large that directly 123 * multiplying by ppb would result in arithmetic overflow even when 124 * using a u64. Avoid this by instead calculating the new incval 125 * always in terms of the 40GbE clock rate and then multiplying by the 126 * link speed factor afterwards. This does result in slightly lower 127 * precision at lower link speeds, but it is fairly minor. 128 */ 129 smp_mb(); /* Force any pending update before accessing. */ 130 adj *= READ_ONCE(pf->ptp_adj_mult); 131 132 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 133 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 134 135 return 0; 136 } 137 138 /** 139 * i40e_ptp_adjtime - Adjust the PHC time 140 * @ptp: The PTP clock structure 141 * @delta: Offset in nanoseconds to adjust the PHC time by 142 * 143 * Adjust the frequency of the PHC by the indicated parts per billion from the 144 * base frequency. 145 **/ 146 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 147 { 148 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 149 struct timespec64 now, then; 150 151 then = ns_to_timespec64(delta); 152 mutex_lock(&pf->tmreg_lock); 153 154 i40e_ptp_read(pf, &now, NULL); 155 now = timespec64_add(now, then); 156 i40e_ptp_write(pf, (const struct timespec64 *)&now); 157 158 mutex_unlock(&pf->tmreg_lock); 159 160 return 0; 161 } 162 163 /** 164 * i40e_ptp_gettimex - Get the time of the PHC 165 * @ptp: The PTP clock structure 166 * @ts: timespec structure to hold the current time value 167 * @sts: structure to hold the system time before and after reading the PHC 168 * 169 * Read the device clock and return the correct value on ns, after converting it 170 * into a timespec struct. 171 **/ 172 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 173 struct ptp_system_timestamp *sts) 174 { 175 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 176 177 mutex_lock(&pf->tmreg_lock); 178 i40e_ptp_read(pf, ts, sts); 179 mutex_unlock(&pf->tmreg_lock); 180 181 return 0; 182 } 183 184 /** 185 * i40e_ptp_settime - Set the time of the PHC 186 * @ptp: The PTP clock structure 187 * @ts: timespec structure that holds the new time value 188 * 189 * Set the device clock to the user input value. The conversion from timespec 190 * to ns happens in the write function. 191 **/ 192 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 193 const struct timespec64 *ts) 194 { 195 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 196 197 mutex_lock(&pf->tmreg_lock); 198 i40e_ptp_write(pf, ts); 199 mutex_unlock(&pf->tmreg_lock); 200 201 return 0; 202 } 203 204 /** 205 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 206 * @ptp: The PTP clock structure 207 * @rq: The requested feature to change 208 * @on: Enable/disable flag 209 * 210 * The XL710 does not support any of the ancillary features of the PHC 211 * subsystem, so this function may just return. 212 **/ 213 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 214 struct ptp_clock_request *rq, int on) 215 { 216 return -EOPNOTSUPP; 217 } 218 219 /** 220 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events 221 * @pf: the PF data structure 222 * 223 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 224 * for noticed latch events. This allows the driver to keep track of the first 225 * time a latch event was noticed which will be used to help clear out Rx 226 * timestamps for packets that got dropped or lost. 227 * 228 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 229 * expected to be called only while under the ptp_rx_lock. 230 **/ 231 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 232 { 233 struct i40e_hw *hw = &pf->hw; 234 u32 prttsyn_stat, new_latch_events; 235 int i; 236 237 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 238 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 239 240 /* Update the jiffies time for any newly latched timestamp. This 241 * ensures that we store the time that we first discovered a timestamp 242 * was latched by the hardware. The service task will later determine 243 * if we should free the latch and drop that timestamp should too much 244 * time pass. This flow ensures that we only update jiffies for new 245 * events latched since the last time we checked, and not all events 246 * currently latched, so that the service task accounting remains 247 * accurate. 248 */ 249 for (i = 0; i < 4; i++) { 250 if (new_latch_events & BIT(i)) 251 pf->latch_events[i] = jiffies; 252 } 253 254 /* Finally, we store the current status of the Rx timestamp latches */ 255 pf->latch_event_flags = prttsyn_stat; 256 257 return prttsyn_stat; 258 } 259 260 /** 261 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 262 * @pf: The PF private data structure 263 * @vsi: The VSI with the rings relevant to 1588 264 * 265 * This watchdog task is scheduled to detect error case where hardware has 266 * dropped an Rx packet that was timestamped when the ring is full. The 267 * particular error is rare but leaves the device in a state unable to timestamp 268 * any future packets. 269 **/ 270 void i40e_ptp_rx_hang(struct i40e_pf *pf) 271 { 272 struct i40e_hw *hw = &pf->hw; 273 unsigned int i, cleared = 0; 274 275 /* Since we cannot turn off the Rx timestamp logic if the device is 276 * configured for Tx timestamping, we check if Rx timestamping is 277 * configured. We don't want to spuriously warn about Rx timestamp 278 * hangs if we don't care about the timestamps. 279 */ 280 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 281 return; 282 283 spin_lock_bh(&pf->ptp_rx_lock); 284 285 /* Update current latch times for Rx events */ 286 i40e_ptp_get_rx_events(pf); 287 288 /* Check all the currently latched Rx events and see whether they have 289 * been latched for over a second. It is assumed that any timestamp 290 * should have been cleared within this time, or else it was captured 291 * for a dropped frame that the driver never received. Thus, we will 292 * clear any timestamp that has been latched for over 1 second. 293 */ 294 for (i = 0; i < 4; i++) { 295 if ((pf->latch_event_flags & BIT(i)) && 296 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 297 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 298 pf->latch_event_flags &= ~BIT(i); 299 cleared++; 300 } 301 } 302 303 spin_unlock_bh(&pf->ptp_rx_lock); 304 305 /* Log a warning if more than 2 timestamps got dropped in the same 306 * check. We don't want to warn about all drops because it can occur 307 * in normal scenarios such as PTP frames on multicast addresses we 308 * aren't listening to. However, administrator should know if this is 309 * the reason packets aren't receiving timestamps. 310 */ 311 if (cleared > 2) 312 dev_dbg(&pf->pdev->dev, 313 "Dropped %d missed RXTIME timestamp events\n", 314 cleared); 315 316 /* Finally, update the rx_hwtstamp_cleared counter */ 317 pf->rx_hwtstamp_cleared += cleared; 318 } 319 320 /** 321 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 322 * @pf: The PF private data structure 323 * 324 * This watchdog task is run periodically to make sure that we clear the Tx 325 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 326 * time. It is unexpected in the normal case but if it occurs it results in 327 * permanently preventing timestamps of future packets. 328 **/ 329 void i40e_ptp_tx_hang(struct i40e_pf *pf) 330 { 331 struct sk_buff *skb; 332 333 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 334 return; 335 336 /* Nothing to do if we're not already waiting for a timestamp */ 337 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 338 return; 339 340 /* We already have a handler routine which is run when we are notified 341 * of a Tx timestamp in the hardware. If we don't get an interrupt 342 * within a second it is reasonable to assume that we never will. 343 */ 344 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 345 skb = pf->ptp_tx_skb; 346 pf->ptp_tx_skb = NULL; 347 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 348 349 /* Free the skb after we clear the bitlock */ 350 dev_kfree_skb_any(skb); 351 pf->tx_hwtstamp_timeouts++; 352 } 353 } 354 355 /** 356 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 357 * @pf: Board private structure 358 * 359 * Read the value of the Tx timestamp from the registers, convert it into a 360 * value consumable by the stack, and store that result into the shhwtstamps 361 * struct before returning it up the stack. 362 **/ 363 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 364 { 365 struct skb_shared_hwtstamps shhwtstamps; 366 struct sk_buff *skb = pf->ptp_tx_skb; 367 struct i40e_hw *hw = &pf->hw; 368 u32 hi, lo; 369 u64 ns; 370 371 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 372 return; 373 374 /* don't attempt to timestamp if we don't have an skb */ 375 if (!pf->ptp_tx_skb) 376 return; 377 378 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 379 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 380 381 ns = (((u64)hi) << 32) | lo; 382 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 383 384 /* Clear the bit lock as soon as possible after reading the register, 385 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 386 * applications might wake up and attempt to request another transmit 387 * timestamp prior to the bit lock being cleared. 388 */ 389 pf->ptp_tx_skb = NULL; 390 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 391 392 /* Notify the stack and free the skb after we've unlocked */ 393 skb_tstamp_tx(skb, &shhwtstamps); 394 dev_kfree_skb_any(skb); 395 } 396 397 /** 398 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 399 * @pf: Board private structure 400 * @skb: Particular skb to send timestamp with 401 * @index: Index into the receive timestamp registers for the timestamp 402 * 403 * The XL710 receives a notification in the receive descriptor with an offset 404 * into the set of RXTIME registers where the timestamp is for that skb. This 405 * function goes and fetches the receive timestamp from that offset, if a valid 406 * one exists. The RXTIME registers are in ns, so we must convert the result 407 * first. 408 **/ 409 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 410 { 411 u32 prttsyn_stat, hi, lo; 412 struct i40e_hw *hw; 413 u64 ns; 414 415 /* Since we cannot turn off the Rx timestamp logic if the device is 416 * doing Tx timestamping, check if Rx timestamping is configured. 417 */ 418 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 419 return; 420 421 hw = &pf->hw; 422 423 spin_lock_bh(&pf->ptp_rx_lock); 424 425 /* Get current Rx events and update latch times */ 426 prttsyn_stat = i40e_ptp_get_rx_events(pf); 427 428 /* TODO: Should we warn about missing Rx timestamp event? */ 429 if (!(prttsyn_stat & BIT(index))) { 430 spin_unlock_bh(&pf->ptp_rx_lock); 431 return; 432 } 433 434 /* Clear the latched event since we're about to read its register */ 435 pf->latch_event_flags &= ~BIT(index); 436 437 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 438 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 439 440 spin_unlock_bh(&pf->ptp_rx_lock); 441 442 ns = (((u64)hi) << 32) | lo; 443 444 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 445 } 446 447 /** 448 * i40e_ptp_set_increment - Utility function to update clock increment rate 449 * @pf: Board private structure 450 * 451 * During a link change, the DMA frequency that drives the 1588 logic will 452 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 453 * we must update the increment value per clock tick. 454 **/ 455 void i40e_ptp_set_increment(struct i40e_pf *pf) 456 { 457 struct i40e_link_status *hw_link_info; 458 struct i40e_hw *hw = &pf->hw; 459 u64 incval; 460 u32 mult; 461 462 hw_link_info = &hw->phy.link_info; 463 464 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 465 466 switch (hw_link_info->link_speed) { 467 case I40E_LINK_SPEED_10GB: 468 mult = I40E_PTP_10GB_INCVAL_MULT; 469 break; 470 case I40E_LINK_SPEED_1GB: 471 mult = I40E_PTP_1GB_INCVAL_MULT; 472 break; 473 case I40E_LINK_SPEED_100MB: 474 { 475 static int warn_once; 476 477 if (!warn_once) { 478 dev_warn(&pf->pdev->dev, 479 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 480 warn_once++; 481 } 482 mult = 0; 483 break; 484 } 485 case I40E_LINK_SPEED_40GB: 486 default: 487 mult = 1; 488 break; 489 } 490 491 /* The increment value is calculated by taking the base 40GbE incvalue 492 * and multiplying it by a factor based on the link speed. 493 */ 494 incval = I40E_PTP_40GB_INCVAL * mult; 495 496 /* Write the new increment value into the increment register. The 497 * hardware will not update the clock until both registers have been 498 * written. 499 */ 500 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 501 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 502 503 /* Update the base adjustement value. */ 504 WRITE_ONCE(pf->ptp_adj_mult, mult); 505 smp_mb(); /* Force the above update. */ 506 } 507 508 /** 509 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 510 * @pf: Board private structure 511 * @ifr: ioctl data 512 * 513 * Obtain the current hardware timestamping settigs as requested. To do this, 514 * keep a shadow copy of the timestamp settings rather than attempting to 515 * deconstruct it from the registers. 516 **/ 517 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 518 { 519 struct hwtstamp_config *config = &pf->tstamp_config; 520 521 if (!(pf->flags & I40E_FLAG_PTP)) 522 return -EOPNOTSUPP; 523 524 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 525 -EFAULT : 0; 526 } 527 528 /** 529 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 530 * @pf: Board private structure 531 * @config: hwtstamp settings requested or saved 532 * 533 * Control hardware registers to enter the specific mode requested by the 534 * user. Also used during reset path to ensure that timestamp settings are 535 * maintained. 536 * 537 * Note: modifies config in place, and may update the requested mode to be 538 * more broad if the specific filter is not directly supported. 539 **/ 540 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 541 struct hwtstamp_config *config) 542 { 543 struct i40e_hw *hw = &pf->hw; 544 u32 tsyntype, regval; 545 546 /* Reserved for future extensions. */ 547 if (config->flags) 548 return -EINVAL; 549 550 switch (config->tx_type) { 551 case HWTSTAMP_TX_OFF: 552 pf->ptp_tx = false; 553 break; 554 case HWTSTAMP_TX_ON: 555 pf->ptp_tx = true; 556 break; 557 default: 558 return -ERANGE; 559 } 560 561 switch (config->rx_filter) { 562 case HWTSTAMP_FILTER_NONE: 563 pf->ptp_rx = false; 564 /* We set the type to V1, but do not enable UDP packet 565 * recognition. In this way, we should be as close to 566 * disabling PTP Rx timestamps as possible since V1 packets 567 * are always UDP, since L2 packets are a V2 feature. 568 */ 569 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 570 break; 571 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 572 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 573 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 574 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 575 return -ERANGE; 576 pf->ptp_rx = true; 577 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 578 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 579 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 580 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 581 break; 582 case HWTSTAMP_FILTER_PTP_V2_EVENT: 583 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 584 case HWTSTAMP_FILTER_PTP_V2_SYNC: 585 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 586 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 587 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 588 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 589 return -ERANGE; 590 /* fall through */ 591 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 592 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 593 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 594 pf->ptp_rx = true; 595 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 596 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 597 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 598 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 599 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 600 } else { 601 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 602 } 603 break; 604 case HWTSTAMP_FILTER_NTP_ALL: 605 case HWTSTAMP_FILTER_ALL: 606 default: 607 return -ERANGE; 608 } 609 610 /* Clear out all 1588-related registers to clear and unlatch them. */ 611 spin_lock_bh(&pf->ptp_rx_lock); 612 rd32(hw, I40E_PRTTSYN_STAT_0); 613 rd32(hw, I40E_PRTTSYN_TXTIME_H); 614 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 615 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 616 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 617 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 618 pf->latch_event_flags = 0; 619 spin_unlock_bh(&pf->ptp_rx_lock); 620 621 /* Enable/disable the Tx timestamp interrupt based on user input. */ 622 regval = rd32(hw, I40E_PRTTSYN_CTL0); 623 if (pf->ptp_tx) 624 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 625 else 626 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 627 wr32(hw, I40E_PRTTSYN_CTL0, regval); 628 629 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 630 if (pf->ptp_tx) 631 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 632 else 633 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 634 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 635 636 /* Although there is no simple on/off switch for Rx, we "disable" Rx 637 * timestamps by setting to V1 only mode and clear the UDP 638 * recognition. This ought to disable all PTP Rx timestamps as V1 639 * packets are always over UDP. Note that software is configured to 640 * ignore Rx timestamps via the pf->ptp_rx flag. 641 */ 642 regval = rd32(hw, I40E_PRTTSYN_CTL1); 643 /* clear everything but the enable bit */ 644 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 645 /* now enable bits for desired Rx timestamps */ 646 regval |= tsyntype; 647 wr32(hw, I40E_PRTTSYN_CTL1, regval); 648 649 return 0; 650 } 651 652 /** 653 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 654 * @pf: Board private structure 655 * @ifr: ioctl data 656 * 657 * Respond to the user filter requests and make the appropriate hardware 658 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 659 * logic, so keep track in software of whether to indicate these timestamps 660 * or not. 661 * 662 * It is permissible to "upgrade" the user request to a broader filter, as long 663 * as the user receives the timestamps they care about and the user is notified 664 * the filter has been broadened. 665 **/ 666 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 667 { 668 struct hwtstamp_config config; 669 int err; 670 671 if (!(pf->flags & I40E_FLAG_PTP)) 672 return -EOPNOTSUPP; 673 674 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 675 return -EFAULT; 676 677 err = i40e_ptp_set_timestamp_mode(pf, &config); 678 if (err) 679 return err; 680 681 /* save these settings for future reference */ 682 pf->tstamp_config = config; 683 684 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 685 -EFAULT : 0; 686 } 687 688 /** 689 * i40e_ptp_create_clock - Create PTP clock device for userspace 690 * @pf: Board private structure 691 * 692 * This function creates a new PTP clock device. It only creates one if we 693 * don't already have one, so it is safe to call. Will return error if it 694 * can't create one, but success if we already have a device. Should be used 695 * by i40e_ptp_init to create clock initially, and prevent global resets from 696 * creating new clock devices. 697 **/ 698 static long i40e_ptp_create_clock(struct i40e_pf *pf) 699 { 700 /* no need to create a clock device if we already have one */ 701 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 702 return 0; 703 704 strlcpy(pf->ptp_caps.name, i40e_driver_name, 705 sizeof(pf->ptp_caps.name) - 1); 706 pf->ptp_caps.owner = THIS_MODULE; 707 pf->ptp_caps.max_adj = 999999999; 708 pf->ptp_caps.n_ext_ts = 0; 709 pf->ptp_caps.pps = 0; 710 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 711 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 712 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; 713 pf->ptp_caps.settime64 = i40e_ptp_settime; 714 pf->ptp_caps.enable = i40e_ptp_feature_enable; 715 716 /* Attempt to register the clock before enabling the hardware. */ 717 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 718 if (IS_ERR(pf->ptp_clock)) 719 return PTR_ERR(pf->ptp_clock); 720 721 /* clear the hwtstamp settings here during clock create, instead of 722 * during regular init, so that we can maintain settings across a 723 * reset or suspend. 724 */ 725 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 726 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 727 728 /* Set the previous "reset" time to the current Kernel clock time */ 729 pf->ptp_prev_hw_time = ktime_to_timespec64(ktime_get_real()); 730 pf->ptp_reset_start = ktime_get(); 731 732 return 0; 733 } 734 735 /** 736 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time 737 * @pf: Board private structure 738 * 739 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should 740 * be called at the end of preparing to reset, just before hardware reset 741 * occurs, in order to preserve the PTP time as close as possible across 742 * resets. 743 */ 744 void i40e_ptp_save_hw_time(struct i40e_pf *pf) 745 { 746 /* don't try to access the PTP clock if it's not enabled */ 747 if (!(pf->flags & I40E_FLAG_PTP)) 748 return; 749 750 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); 751 /* Get a monotonic starting time for this reset */ 752 pf->ptp_reset_start = ktime_get(); 753 } 754 755 /** 756 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs 757 * @pf: Board private structure 758 * 759 * Restore the PTP hardware clock registers. We previously cached the PTP 760 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, 761 * update this value based on the time delta since the time was saved, using 762 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. 763 * 764 * This ensures that the hardware clock is restored to nearly what it should 765 * have been if a reset had not occurred. 766 */ 767 void i40e_ptp_restore_hw_time(struct i40e_pf *pf) 768 { 769 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); 770 771 /* Update the previous HW time with the ktime delta */ 772 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); 773 774 /* Restore the hardware clock registers */ 775 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); 776 } 777 778 /** 779 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 780 * @pf: Board private structure 781 * 782 * This function sets device up for 1588 support. The first time it is run, it 783 * will create a PHC clock device. It does not create a clock device if one 784 * already exists. It also reconfigures the device after a reset. 785 * 786 * The first time a clock is created, i40e_ptp_create_clock will set 787 * pf->ptp_prev_hw_time to the current system time. During resets, it is 788 * expected that this timespec will be set to the last known PTP clock time, 789 * in order to preserve the clock time as close as possible across a reset. 790 **/ 791 void i40e_ptp_init(struct i40e_pf *pf) 792 { 793 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 794 struct i40e_hw *hw = &pf->hw; 795 u32 pf_id; 796 long err; 797 798 /* Only one PF is assigned to control 1588 logic per port. Do not 799 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 800 */ 801 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 802 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 803 if (hw->pf_id != pf_id) { 804 pf->flags &= ~I40E_FLAG_PTP; 805 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 806 __func__, 807 netdev->name); 808 return; 809 } 810 811 mutex_init(&pf->tmreg_lock); 812 spin_lock_init(&pf->ptp_rx_lock); 813 814 /* ensure we have a clock device */ 815 err = i40e_ptp_create_clock(pf); 816 if (err) { 817 pf->ptp_clock = NULL; 818 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 819 __func__); 820 } else if (pf->ptp_clock) { 821 u32 regval; 822 823 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 824 dev_info(&pf->pdev->dev, "PHC enabled\n"); 825 pf->flags |= I40E_FLAG_PTP; 826 827 /* Ensure the clocks are running. */ 828 regval = rd32(hw, I40E_PRTTSYN_CTL0); 829 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 830 wr32(hw, I40E_PRTTSYN_CTL0, regval); 831 regval = rd32(hw, I40E_PRTTSYN_CTL1); 832 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 833 wr32(hw, I40E_PRTTSYN_CTL1, regval); 834 835 /* Set the increment value per clock tick. */ 836 i40e_ptp_set_increment(pf); 837 838 /* reset timestamping mode */ 839 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 840 841 /* Restore the clock time based on last known value */ 842 i40e_ptp_restore_hw_time(pf); 843 } 844 } 845 846 /** 847 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 848 * @pf: Board private structure 849 * 850 * This function handles the cleanup work required from the initialization by 851 * clearing out the important information and unregistering the PHC. 852 **/ 853 void i40e_ptp_stop(struct i40e_pf *pf) 854 { 855 pf->flags &= ~I40E_FLAG_PTP; 856 pf->ptp_tx = false; 857 pf->ptp_rx = false; 858 859 if (pf->ptp_tx_skb) { 860 struct sk_buff *skb = pf->ptp_tx_skb; 861 862 pf->ptp_tx_skb = NULL; 863 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 864 dev_kfree_skb_any(skb); 865 } 866 867 if (pf->ptp_clock) { 868 ptp_clock_unregister(pf->ptp_clock); 869 pf->ptp_clock = NULL; 870 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 871 pf->vsi[pf->lan_vsi]->netdev->name); 872 } 873 } 874