1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e.h" 28 #include <linux/export.h> 29 #include <linux/ptp_classify.h> 30 31 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 32 * the fundamental clock design. However, the clock operations are much simpler 33 * in the XL710 because the device supports a full 64 bits of nanoseconds. 34 * Because the field is so wide, we can forgo the cycle counter and just 35 * operate with the nanosecond field directly without fear of overflow. 36 * 37 * Much like the 82599, the update period is dependent upon the link speed: 38 * At 40Gb link or no link, the period is 1.6ns. 39 * At 10Gb link, the period is multiplied by 2. (3.2ns) 40 * At 1Gb link, the period is multiplied by 20. (32ns) 41 * 1588 functionality is not supported at 100Mbps. 42 */ 43 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 44 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 45 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 46 47 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \ 48 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 49 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \ 50 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 51 #define I40E_PTP_TX_TIMEOUT (HZ * 15) 52 53 /** 54 * i40e_ptp_read - Read the PHC time from the device 55 * @pf: Board private structure 56 * @ts: timespec structure to hold the current time value 57 * 58 * This function reads the PRTTSYN_TIME registers and stores them in a 59 * timespec. However, since the registers are 64 bits of nanoseconds, we must 60 * convert the result to a timespec before we can return. 61 **/ 62 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts) 63 { 64 struct i40e_hw *hw = &pf->hw; 65 u32 hi, lo; 66 u64 ns; 67 68 /* The timer latches on the lowest register read. */ 69 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 70 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 71 72 ns = (((u64)hi) << 32) | lo; 73 74 *ts = ns_to_timespec(ns); 75 } 76 77 /** 78 * i40e_ptp_write - Write the PHC time to the device 79 * @pf: Board private structure 80 * @ts: timespec structure that holds the new time value 81 * 82 * This function writes the PRTTSYN_TIME registers with the user value. Since 83 * we receive a timespec from the stack, we must convert that timespec into 84 * nanoseconds before programming the registers. 85 **/ 86 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts) 87 { 88 struct i40e_hw *hw = &pf->hw; 89 u64 ns = timespec_to_ns(ts); 90 91 /* The timer will not update until the high register is written, so 92 * write the low register first. 93 */ 94 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 95 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 96 } 97 98 /** 99 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 100 * @hwtstamps: Timestamp structure to update 101 * @timestamp: Timestamp from the hardware 102 * 103 * We need to convert the NIC clock value into a hwtstamp which can be used by 104 * the upper level timestamping functions. Since the timestamp is simply a 64- 105 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 106 **/ 107 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 108 u64 timestamp) 109 { 110 memset(hwtstamps, 0, sizeof(*hwtstamps)); 111 112 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 113 } 114 115 /** 116 * i40e_ptp_adjfreq - Adjust the PHC frequency 117 * @ptp: The PTP clock structure 118 * @ppb: Parts per billion adjustment from the base 119 * 120 * Adjust the frequency of the PHC by the indicated parts per billion from the 121 * base frequency. 122 **/ 123 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 124 { 125 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 126 struct i40e_hw *hw = &pf->hw; 127 u64 adj, freq, diff; 128 int neg_adj = 0; 129 130 if (ppb < 0) { 131 neg_adj = 1; 132 ppb = -ppb; 133 } 134 135 smp_mb(); /* Force any pending update before accessing. */ 136 adj = ACCESS_ONCE(pf->ptp_base_adj); 137 138 freq = adj; 139 freq *= ppb; 140 diff = div_u64(freq, 1000000000ULL); 141 142 if (neg_adj) 143 adj -= diff; 144 else 145 adj += diff; 146 147 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 148 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 149 150 return 0; 151 } 152 153 /** 154 * i40e_ptp_adjtime - Adjust the PHC time 155 * @ptp: The PTP clock structure 156 * @delta: Offset in nanoseconds to adjust the PHC time by 157 * 158 * Adjust the frequency of the PHC by the indicated parts per billion from the 159 * base frequency. 160 **/ 161 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 162 { 163 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 164 struct timespec now, then = ns_to_timespec(delta); 165 unsigned long flags; 166 167 spin_lock_irqsave(&pf->tmreg_lock, flags); 168 169 i40e_ptp_read(pf, &now); 170 now = timespec_add(now, then); 171 i40e_ptp_write(pf, (const struct timespec *)&now); 172 173 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 174 175 return 0; 176 } 177 178 /** 179 * i40e_ptp_gettime - Get the time of the PHC 180 * @ptp: The PTP clock structure 181 * @ts: timespec structure to hold the current time value 182 * 183 * Read the device clock and return the correct value on ns, after converting it 184 * into a timespec struct. 185 **/ 186 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) 187 { 188 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 189 unsigned long flags; 190 191 spin_lock_irqsave(&pf->tmreg_lock, flags); 192 i40e_ptp_read(pf, ts); 193 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 194 195 return 0; 196 } 197 198 /** 199 * i40e_ptp_settime - Set the time of the PHC 200 * @ptp: The PTP clock structure 201 * @ts: timespec structure that holds the new time value 202 * 203 * Set the device clock to the user input value. The conversion from timespec 204 * to ns happens in the write function. 205 **/ 206 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 207 const struct timespec *ts) 208 { 209 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 210 unsigned long flags; 211 212 spin_lock_irqsave(&pf->tmreg_lock, flags); 213 i40e_ptp_write(pf, ts); 214 spin_unlock_irqrestore(&pf->tmreg_lock, flags); 215 216 return 0; 217 } 218 219 /** 220 * i40e_ptp_tx_work 221 * @work: pointer to work struct 222 * 223 * This work function polls the PRTTSYN_STAT_0.TXTIME bit to determine when a 224 * Tx timestamp event has occurred, in order to pass the Tx timestamp value up 225 * the stack in the skb. 226 */ 227 static void i40e_ptp_tx_work(struct work_struct *work) 228 { 229 struct i40e_pf *pf = container_of(work, struct i40e_pf, 230 ptp_tx_work); 231 struct i40e_hw *hw = &pf->hw; 232 u32 prttsyn_stat_0; 233 234 if (!pf->ptp_tx_skb) 235 return; 236 237 if (time_is_before_jiffies(pf->ptp_tx_start + 238 I40E_PTP_TX_TIMEOUT)) { 239 dev_kfree_skb_any(pf->ptp_tx_skb); 240 pf->ptp_tx_skb = NULL; 241 pf->tx_hwtstamp_timeouts++; 242 dev_warn(&pf->pdev->dev, "clearing Tx timestamp hang"); 243 return; 244 } 245 246 prttsyn_stat_0 = rd32(hw, I40E_PRTTSYN_STAT_0); 247 if (prttsyn_stat_0 & I40E_PRTTSYN_STAT_0_TXTIME_MASK) 248 i40e_ptp_tx_hwtstamp(pf); 249 else 250 schedule_work(&pf->ptp_tx_work); 251 } 252 253 /** 254 * i40e_ptp_enable - Enable/disable ancillary features of the PHC subsystem 255 * @ptp: The PTP clock structure 256 * @rq: The requested feature to change 257 * @on: Enable/disable flag 258 * 259 * The XL710 does not support any of the ancillary features of the PHC 260 * subsystem, so this function may just return. 261 **/ 262 static int i40e_ptp_enable(struct ptp_clock_info *ptp, 263 struct ptp_clock_request *rq, int on) 264 { 265 return -EOPNOTSUPP; 266 } 267 268 /** 269 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 270 * @vsi: The VSI with the rings relevant to 1588 271 * 272 * This watchdog task is scheduled to detect error case where hardware has 273 * dropped an Rx packet that was timestamped when the ring is full. The 274 * particular error is rare but leaves the device in a state unable to timestamp 275 * any future packets. 276 **/ 277 void i40e_ptp_rx_hang(struct i40e_vsi *vsi) 278 { 279 struct i40e_pf *pf = vsi->back; 280 struct i40e_hw *hw = &pf->hw; 281 struct i40e_ring *rx_ring; 282 unsigned long rx_event; 283 u32 prttsyn_stat; 284 int n; 285 286 if (pf->flags & I40E_FLAG_PTP) 287 return; 288 289 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 290 291 /* Unless all four receive timestamp registers are latched, we are not 292 * concerned about a possible PTP Rx hang, so just update the timeout 293 * counter and exit. 294 */ 295 if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK << 296 I40E_PRTTSYN_STAT_1_RXT0_SHIFT) | 297 (I40E_PRTTSYN_STAT_1_RXT1_MASK << 298 I40E_PRTTSYN_STAT_1_RXT1_SHIFT) | 299 (I40E_PRTTSYN_STAT_1_RXT2_MASK << 300 I40E_PRTTSYN_STAT_1_RXT2_SHIFT) | 301 (I40E_PRTTSYN_STAT_1_RXT3_MASK << 302 I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) { 303 pf->last_rx_ptp_check = jiffies; 304 return; 305 } 306 307 /* Determine the most recent watchdog or rx_timestamp event. */ 308 rx_event = pf->last_rx_ptp_check; 309 for (n = 0; n < vsi->num_queue_pairs; n++) { 310 rx_ring = vsi->rx_rings[n]; 311 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 312 rx_event = rx_ring->last_rx_timestamp; 313 } 314 315 /* Only need to read the high RXSTMP register to clear the lock */ 316 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 317 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 318 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 319 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 320 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 321 pf->last_rx_ptp_check = jiffies; 322 pf->rx_hwtstamp_cleared++; 323 dev_warn(&vsi->back->pdev->dev, 324 "%s: clearing Rx timestamp hang", 325 __func__); 326 } 327 } 328 329 /** 330 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 331 * @pf: Board private structure 332 * 333 * Read the value of the Tx timestamp from the registers, convert it into a 334 * value consumable by the stack, and store that result into the shhwtstamps 335 * struct before returning it up the stack. 336 **/ 337 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 338 { 339 struct skb_shared_hwtstamps shhwtstamps; 340 struct i40e_hw *hw = &pf->hw; 341 u32 hi, lo; 342 u64 ns; 343 344 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 345 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 346 347 ns = (((u64)hi) << 32) | lo; 348 349 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 350 skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps); 351 dev_kfree_skb_any(pf->ptp_tx_skb); 352 pf->ptp_tx_skb = NULL; 353 } 354 355 /** 356 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 357 * @pf: Board private structure 358 * @skb: Particular skb to send timestamp with 359 * @index: Index into the receive timestamp registers for the timestamp 360 * 361 * The XL710 receives a notification in the receive descriptor with an offset 362 * into the set of RXTIME registers where the timestamp is for that skb. This 363 * function goes and fetches the receive timestamp from that offset, if a valid 364 * one exists. The RXTIME registers are in ns, so we must convert the result 365 * first. 366 **/ 367 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 368 { 369 u32 prttsyn_stat, hi, lo; 370 struct i40e_hw *hw; 371 u64 ns; 372 373 /* Since we cannot turn off the Rx timestamp logic if the device is 374 * doing Tx timestamping, check if Rx timestamping is configured. 375 */ 376 if (!pf->ptp_rx) 377 return; 378 379 hw = &pf->hw; 380 381 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 382 383 if (!(prttsyn_stat & (1 << index))) 384 return; 385 386 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 387 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 388 389 ns = (((u64)hi) << 32) | lo; 390 391 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 392 } 393 394 /** 395 * i40e_ptp_set_increment - Utility function to update clock increment rate 396 * @pf: Board private structure 397 * 398 * During a link change, the DMA frequency that drives the 1588 logic will 399 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 400 * we must update the increment value per clock tick. 401 **/ 402 void i40e_ptp_set_increment(struct i40e_pf *pf) 403 { 404 struct i40e_link_status *hw_link_info; 405 struct i40e_hw *hw = &pf->hw; 406 u64 incval; 407 408 hw_link_info = &hw->phy.link_info; 409 410 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 411 412 switch (hw_link_info->link_speed) { 413 case I40E_LINK_SPEED_10GB: 414 incval = I40E_PTP_10GB_INCVAL; 415 break; 416 case I40E_LINK_SPEED_1GB: 417 incval = I40E_PTP_1GB_INCVAL; 418 break; 419 case I40E_LINK_SPEED_100MB: 420 dev_warn(&pf->pdev->dev, 421 "%s: 1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n", 422 __func__); 423 incval = 0; 424 break; 425 case I40E_LINK_SPEED_40GB: 426 default: 427 incval = I40E_PTP_40GB_INCVAL; 428 break; 429 } 430 431 /* Write the new increment value into the increment register. The 432 * hardware will not update the clock until both registers have been 433 * written. 434 */ 435 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 436 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 437 438 /* Update the base adjustement value. */ 439 ACCESS_ONCE(pf->ptp_base_adj) = incval; 440 smp_mb(); /* Force the above update. */ 441 } 442 443 /** 444 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 445 * @pf: Board private structure 446 * @ifreq: ioctl data 447 * 448 * Obtain the current hardware timestamping settigs as requested. To do this, 449 * keep a shadow copy of the timestamp settings rather than attempting to 450 * deconstruct it from the registers. 451 **/ 452 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 453 { 454 struct hwtstamp_config *config = &pf->tstamp_config; 455 456 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 457 -EFAULT : 0; 458 } 459 460 /** 461 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 462 * @pf: Board private structure 463 * @ifreq: ioctl data 464 * 465 * Respond to the user filter requests and make the appropriate hardware 466 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 467 * logic, so keep track in software of whether to indicate these timestamps 468 * or not. 469 * 470 * It is permissible to "upgrade" the user request to a broader filter, as long 471 * as the user receives the timestamps they care about and the user is notified 472 * the filter has been broadened. 473 **/ 474 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 475 { 476 struct i40e_hw *hw = &pf->hw; 477 struct hwtstamp_config *config = &pf->tstamp_config; 478 u32 pf_id, tsyntype, regval; 479 480 if (copy_from_user(config, ifr->ifr_data, sizeof(*config))) 481 return -EFAULT; 482 483 /* Reserved for future extensions. */ 484 if (config->flags) 485 return -EINVAL; 486 487 /* Confirm that 1588 is supported on this PF. */ 488 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 489 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 490 if (hw->pf_id != pf_id) 491 return -EINVAL; 492 493 switch (config->tx_type) { 494 case HWTSTAMP_TX_OFF: 495 pf->ptp_tx = false; 496 break; 497 case HWTSTAMP_TX_ON: 498 pf->ptp_tx = true; 499 break; 500 default: 501 return -ERANGE; 502 } 503 504 switch (config->rx_filter) { 505 case HWTSTAMP_FILTER_NONE: 506 pf->ptp_rx = false; 507 tsyntype = 0; 508 break; 509 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 510 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 511 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 512 pf->ptp_rx = true; 513 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 514 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 515 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 516 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 517 break; 518 case HWTSTAMP_FILTER_PTP_V2_EVENT: 519 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 521 case HWTSTAMP_FILTER_PTP_V2_SYNC: 522 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 523 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 524 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 527 pf->ptp_rx = true; 528 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 529 I40E_PRTTSYN_CTL1_TSYNTYPE_V2 | 530 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 531 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 532 break; 533 case HWTSTAMP_FILTER_ALL: 534 default: 535 return -ERANGE; 536 } 537 538 /* Clear out all 1588-related registers to clear and unlatch them. */ 539 rd32(hw, I40E_PRTTSYN_STAT_0); 540 rd32(hw, I40E_PRTTSYN_TXTIME_H); 541 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 542 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 543 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 544 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 545 546 /* Enable/disable the Tx timestamp interrupt based on user input. */ 547 regval = rd32(hw, I40E_PRTTSYN_CTL0); 548 if (pf->ptp_tx) 549 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 550 else 551 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 552 wr32(hw, I40E_PRTTSYN_CTL0, regval); 553 554 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 555 if (pf->ptp_tx) 556 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 557 else 558 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 559 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 560 561 /* There is no simple on/off switch for Rx. To "disable" Rx support, 562 * ignore any received timestamps, rather than turn off the clock. 563 */ 564 if (pf->ptp_rx) { 565 regval = rd32(hw, I40E_PRTTSYN_CTL1); 566 /* clear everything but the enable bit */ 567 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 568 /* now enable bits for desired Rx timestamps */ 569 regval |= tsyntype; 570 wr32(hw, I40E_PRTTSYN_CTL1, regval); 571 } 572 573 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 574 -EFAULT : 0; 575 } 576 577 /** 578 * i40e_ptp_init - Initialize the 1588 support and register the PHC 579 * @pf: Board private structure 580 * 581 * This function registers the device clock as a PHC. If it is successful, it 582 * starts the clock in the hardware. 583 **/ 584 void i40e_ptp_init(struct i40e_pf *pf) 585 { 586 struct i40e_hw *hw = &pf->hw; 587 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 588 589 strncpy(pf->ptp_caps.name, "i40e", sizeof(pf->ptp_caps.name)); 590 pf->ptp_caps.owner = THIS_MODULE; 591 pf->ptp_caps.max_adj = 999999999; 592 pf->ptp_caps.n_ext_ts = 0; 593 pf->ptp_caps.pps = 0; 594 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 595 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 596 pf->ptp_caps.gettime = i40e_ptp_gettime; 597 pf->ptp_caps.settime = i40e_ptp_settime; 598 pf->ptp_caps.enable = i40e_ptp_enable; 599 600 /* Attempt to register the clock before enabling the hardware. */ 601 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 602 if (IS_ERR(pf->ptp_clock)) { 603 pf->ptp_clock = NULL; 604 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 605 __func__); 606 } else { 607 struct timespec ts; 608 u32 regval; 609 610 spin_lock_init(&pf->tmreg_lock); 611 INIT_WORK(&pf->ptp_tx_work, i40e_ptp_tx_work); 612 613 dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__, 614 netdev->name); 615 pf->flags |= I40E_FLAG_PTP; 616 617 /* Ensure the clocks are running. */ 618 regval = rd32(hw, I40E_PRTTSYN_CTL0); 619 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 620 wr32(hw, I40E_PRTTSYN_CTL0, regval); 621 regval = rd32(hw, I40E_PRTTSYN_CTL1); 622 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 623 wr32(hw, I40E_PRTTSYN_CTL1, regval); 624 625 /* Set the increment value per clock tick. */ 626 i40e_ptp_set_increment(pf); 627 628 /* reset the tstamp_config */ 629 memset(&pf->tstamp_config, 0, sizeof(pf->tstamp_config)); 630 631 /* Set the clock value. */ 632 ts = ktime_to_timespec(ktime_get_real()); 633 i40e_ptp_settime(&pf->ptp_caps, &ts); 634 } 635 } 636 637 /** 638 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 639 * @pf: Board private structure 640 * 641 * This function handles the cleanup work required from the initialization by 642 * clearing out the important information and unregistering the PHC. 643 **/ 644 void i40e_ptp_stop(struct i40e_pf *pf) 645 { 646 pf->flags &= ~I40E_FLAG_PTP; 647 pf->ptp_tx = false; 648 pf->ptp_rx = false; 649 650 cancel_work_sync(&pf->ptp_tx_work); 651 if (pf->ptp_tx_skb) { 652 dev_kfree_skb_any(pf->ptp_tx_skb); 653 pf->ptp_tx_skb = NULL; 654 } 655 656 if (pf->ptp_clock) { 657 ptp_clock_unregister(pf->ptp_clock); 658 pf->ptp_clock = NULL; 659 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 660 pf->vsi[pf->lan_vsi]->netdev->name); 661 } 662 } 663