1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e.h" 28 #include <linux/ptp_classify.h> 29 30 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 31 * the fundamental clock design. However, the clock operations are much simpler 32 * in the XL710 because the device supports a full 64 bits of nanoseconds. 33 * Because the field is so wide, we can forgo the cycle counter and just 34 * operate with the nanosecond field directly without fear of overflow. 35 * 36 * Much like the 82599, the update period is dependent upon the link speed: 37 * At 40Gb link or no link, the period is 1.6ns. 38 * At 10Gb link, the period is multiplied by 2. (3.2ns) 39 * At 1Gb link, the period is multiplied by 20. (32ns) 40 * 1588 functionality is not supported at 100Mbps. 41 */ 42 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 43 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL 44 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL 45 46 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 47 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 48 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 49 50 /** 51 * i40e_ptp_read - Read the PHC time from the device 52 * @pf: Board private structure 53 * @ts: timespec structure to hold the current time value 54 * 55 * This function reads the PRTTSYN_TIME registers and stores them in a 56 * timespec. However, since the registers are 64 bits of nanoseconds, we must 57 * convert the result to a timespec before we can return. 58 **/ 59 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts) 60 { 61 struct i40e_hw *hw = &pf->hw; 62 u32 hi, lo; 63 u64 ns; 64 65 /* The timer latches on the lowest register read. */ 66 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 67 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 68 69 ns = (((u64)hi) << 32) | lo; 70 71 *ts = ns_to_timespec64(ns); 72 } 73 74 /** 75 * i40e_ptp_write - Write the PHC time to the device 76 * @pf: Board private structure 77 * @ts: timespec structure that holds the new time value 78 * 79 * This function writes the PRTTSYN_TIME registers with the user value. Since 80 * we receive a timespec from the stack, we must convert that timespec into 81 * nanoseconds before programming the registers. 82 **/ 83 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 84 { 85 struct i40e_hw *hw = &pf->hw; 86 u64 ns = timespec64_to_ns(ts); 87 88 /* The timer will not update until the high register is written, so 89 * write the low register first. 90 */ 91 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 92 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 93 } 94 95 /** 96 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 97 * @hwtstamps: Timestamp structure to update 98 * @timestamp: Timestamp from the hardware 99 * 100 * We need to convert the NIC clock value into a hwtstamp which can be used by 101 * the upper level timestamping functions. Since the timestamp is simply a 64- 102 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 103 **/ 104 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 105 u64 timestamp) 106 { 107 memset(hwtstamps, 0, sizeof(*hwtstamps)); 108 109 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 110 } 111 112 /** 113 * i40e_ptp_adjfreq - Adjust the PHC frequency 114 * @ptp: The PTP clock structure 115 * @ppb: Parts per billion adjustment from the base 116 * 117 * Adjust the frequency of the PHC by the indicated parts per billion from the 118 * base frequency. 119 **/ 120 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 121 { 122 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 123 struct i40e_hw *hw = &pf->hw; 124 u64 adj, freq, diff; 125 int neg_adj = 0; 126 127 if (ppb < 0) { 128 neg_adj = 1; 129 ppb = -ppb; 130 } 131 132 smp_mb(); /* Force any pending update before accessing. */ 133 adj = READ_ONCE(pf->ptp_base_adj); 134 135 freq = adj; 136 freq *= ppb; 137 diff = div_u64(freq, 1000000000ULL); 138 139 if (neg_adj) 140 adj -= diff; 141 else 142 adj += diff; 143 144 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 145 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 146 147 return 0; 148 } 149 150 /** 151 * i40e_ptp_adjtime - Adjust the PHC time 152 * @ptp: The PTP clock structure 153 * @delta: Offset in nanoseconds to adjust the PHC time by 154 * 155 * Adjust the frequency of the PHC by the indicated parts per billion from the 156 * base frequency. 157 **/ 158 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 159 { 160 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 161 struct timespec64 now; 162 163 mutex_lock(&pf->tmreg_lock); 164 165 i40e_ptp_read(pf, &now); 166 timespec64_add_ns(&now, delta); 167 i40e_ptp_write(pf, (const struct timespec64 *)&now); 168 169 mutex_unlock(&pf->tmreg_lock); 170 171 return 0; 172 } 173 174 /** 175 * i40e_ptp_gettime - Get the time of the PHC 176 * @ptp: The PTP clock structure 177 * @ts: timespec structure to hold the current time value 178 * 179 * Read the device clock and return the correct value on ns, after converting it 180 * into a timespec struct. 181 **/ 182 static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 183 { 184 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 185 186 mutex_lock(&pf->tmreg_lock); 187 i40e_ptp_read(pf, ts); 188 mutex_unlock(&pf->tmreg_lock); 189 190 return 0; 191 } 192 193 /** 194 * i40e_ptp_settime - Set the time of the PHC 195 * @ptp: The PTP clock structure 196 * @ts: timespec structure that holds the new time value 197 * 198 * Set the device clock to the user input value. The conversion from timespec 199 * to ns happens in the write function. 200 **/ 201 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 202 const struct timespec64 *ts) 203 { 204 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 205 206 mutex_lock(&pf->tmreg_lock); 207 i40e_ptp_write(pf, ts); 208 mutex_unlock(&pf->tmreg_lock); 209 210 return 0; 211 } 212 213 /** 214 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 215 * @ptp: The PTP clock structure 216 * @rq: The requested feature to change 217 * @on: Enable/disable flag 218 * 219 * The XL710 does not support any of the ancillary features of the PHC 220 * subsystem, so this function may just return. 221 **/ 222 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 223 struct ptp_clock_request *rq, int on) 224 { 225 return -EOPNOTSUPP; 226 } 227 228 /** 229 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events 230 * @pf: the PF data structure 231 * 232 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 233 * for noticed latch events. This allows the driver to keep track of the first 234 * time a latch event was noticed which will be used to help clear out Rx 235 * timestamps for packets that got dropped or lost. 236 * 237 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 238 * expected to be called only while under the ptp_rx_lock. 239 **/ 240 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 241 { 242 struct i40e_hw *hw = &pf->hw; 243 u32 prttsyn_stat, new_latch_events; 244 int i; 245 246 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 247 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 248 249 /* Update the jiffies time for any newly latched timestamp. This 250 * ensures that we store the time that we first discovered a timestamp 251 * was latched by the hardware. The service task will later determine 252 * if we should free the latch and drop that timestamp should too much 253 * time pass. This flow ensures that we only update jiffies for new 254 * events latched since the last time we checked, and not all events 255 * currently latched, so that the service task accounting remains 256 * accurate. 257 */ 258 for (i = 0; i < 4; i++) { 259 if (new_latch_events & BIT(i)) 260 pf->latch_events[i] = jiffies; 261 } 262 263 /* Finally, we store the current status of the Rx timestamp latches */ 264 pf->latch_event_flags = prttsyn_stat; 265 266 return prttsyn_stat; 267 } 268 269 /** 270 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 271 * @pf: The PF private data structure 272 * @vsi: The VSI with the rings relevant to 1588 273 * 274 * This watchdog task is scheduled to detect error case where hardware has 275 * dropped an Rx packet that was timestamped when the ring is full. The 276 * particular error is rare but leaves the device in a state unable to timestamp 277 * any future packets. 278 **/ 279 void i40e_ptp_rx_hang(struct i40e_pf *pf) 280 { 281 struct i40e_hw *hw = &pf->hw; 282 unsigned int i, cleared = 0; 283 284 /* Since we cannot turn off the Rx timestamp logic if the device is 285 * configured for Tx timestamping, we check if Rx timestamping is 286 * configured. We don't want to spuriously warn about Rx timestamp 287 * hangs if we don't care about the timestamps. 288 */ 289 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 290 return; 291 292 spin_lock_bh(&pf->ptp_rx_lock); 293 294 /* Update current latch times for Rx events */ 295 i40e_ptp_get_rx_events(pf); 296 297 /* Check all the currently latched Rx events and see whether they have 298 * been latched for over a second. It is assumed that any timestamp 299 * should have been cleared within this time, or else it was captured 300 * for a dropped frame that the driver never received. Thus, we will 301 * clear any timestamp that has been latched for over 1 second. 302 */ 303 for (i = 0; i < 4; i++) { 304 if ((pf->latch_event_flags & BIT(i)) && 305 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 306 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 307 pf->latch_event_flags &= ~BIT(i); 308 cleared++; 309 } 310 } 311 312 spin_unlock_bh(&pf->ptp_rx_lock); 313 314 /* Log a warning if more than 2 timestamps got dropped in the same 315 * check. We don't want to warn about all drops because it can occur 316 * in normal scenarios such as PTP frames on multicast addresses we 317 * aren't listening to. However, administrator should know if this is 318 * the reason packets aren't receiving timestamps. 319 */ 320 if (cleared > 2) 321 dev_dbg(&pf->pdev->dev, 322 "Dropped %d missed RXTIME timestamp events\n", 323 cleared); 324 325 /* Finally, update the rx_hwtstamp_cleared counter */ 326 pf->rx_hwtstamp_cleared += cleared; 327 } 328 329 /** 330 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 331 * @pf: The PF private data structure 332 * 333 * This watchdog task is run periodically to make sure that we clear the Tx 334 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 335 * time. It is unexpected in the normal case but if it occurs it results in 336 * permanently prevent timestamps of future packets 337 **/ 338 void i40e_ptp_tx_hang(struct i40e_pf *pf) 339 { 340 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 341 return; 342 343 /* Nothing to do if we're not already waiting for a timestamp */ 344 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 345 return; 346 347 /* We already have a handler routine which is run when we are notified 348 * of a Tx timestamp in the hardware. If we don't get an interrupt 349 * within a second it is reasonable to assume that we never will. 350 */ 351 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 352 dev_kfree_skb_any(pf->ptp_tx_skb); 353 pf->ptp_tx_skb = NULL; 354 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 355 pf->tx_hwtstamp_timeouts++; 356 } 357 } 358 359 /** 360 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 361 * @pf: Board private structure 362 * 363 * Read the value of the Tx timestamp from the registers, convert it into a 364 * value consumable by the stack, and store that result into the shhwtstamps 365 * struct before returning it up the stack. 366 **/ 367 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 368 { 369 struct skb_shared_hwtstamps shhwtstamps; 370 struct sk_buff *skb = pf->ptp_tx_skb; 371 struct i40e_hw *hw = &pf->hw; 372 u32 hi, lo; 373 u64 ns; 374 375 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 376 return; 377 378 /* don't attempt to timestamp if we don't have an skb */ 379 if (!pf->ptp_tx_skb) 380 return; 381 382 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 383 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 384 385 ns = (((u64)hi) << 32) | lo; 386 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 387 388 /* Clear the bit lock as soon as possible after reading the register, 389 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 390 * applications might wake up and attempt to request another transmit 391 * timestamp prior to the bit lock being cleared. 392 */ 393 pf->ptp_tx_skb = NULL; 394 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 395 396 /* Notify the stack and free the skb after we've unlocked */ 397 skb_tstamp_tx(skb, &shhwtstamps); 398 dev_kfree_skb_any(skb); 399 } 400 401 /** 402 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 403 * @pf: Board private structure 404 * @skb: Particular skb to send timestamp with 405 * @index: Index into the receive timestamp registers for the timestamp 406 * 407 * The XL710 receives a notification in the receive descriptor with an offset 408 * into the set of RXTIME registers where the timestamp is for that skb. This 409 * function goes and fetches the receive timestamp from that offset, if a valid 410 * one exists. The RXTIME registers are in ns, so we must convert the result 411 * first. 412 **/ 413 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 414 { 415 u32 prttsyn_stat, hi, lo; 416 struct i40e_hw *hw; 417 u64 ns; 418 419 /* Since we cannot turn off the Rx timestamp logic if the device is 420 * doing Tx timestamping, check if Rx timestamping is configured. 421 */ 422 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 423 return; 424 425 hw = &pf->hw; 426 427 spin_lock_bh(&pf->ptp_rx_lock); 428 429 /* Get current Rx events and update latch times */ 430 prttsyn_stat = i40e_ptp_get_rx_events(pf); 431 432 /* TODO: Should we warn about missing Rx timestamp event? */ 433 if (!(prttsyn_stat & BIT(index))) { 434 spin_unlock_bh(&pf->ptp_rx_lock); 435 return; 436 } 437 438 /* Clear the latched event since we're about to read its register */ 439 pf->latch_event_flags &= ~BIT(index); 440 441 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 442 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 443 444 spin_unlock_bh(&pf->ptp_rx_lock); 445 446 ns = (((u64)hi) << 32) | lo; 447 448 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 449 } 450 451 /** 452 * i40e_ptp_set_increment - Utility function to update clock increment rate 453 * @pf: Board private structure 454 * 455 * During a link change, the DMA frequency that drives the 1588 logic will 456 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 457 * we must update the increment value per clock tick. 458 **/ 459 void i40e_ptp_set_increment(struct i40e_pf *pf) 460 { 461 struct i40e_link_status *hw_link_info; 462 struct i40e_hw *hw = &pf->hw; 463 u64 incval; 464 465 hw_link_info = &hw->phy.link_info; 466 467 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 468 469 switch (hw_link_info->link_speed) { 470 case I40E_LINK_SPEED_10GB: 471 incval = I40E_PTP_10GB_INCVAL; 472 break; 473 case I40E_LINK_SPEED_1GB: 474 incval = I40E_PTP_1GB_INCVAL; 475 break; 476 case I40E_LINK_SPEED_100MB: 477 { 478 static int warn_once; 479 480 if (!warn_once) { 481 dev_warn(&pf->pdev->dev, 482 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 483 warn_once++; 484 } 485 incval = 0; 486 break; 487 } 488 case I40E_LINK_SPEED_40GB: 489 default: 490 incval = I40E_PTP_40GB_INCVAL; 491 break; 492 } 493 494 /* Write the new increment value into the increment register. The 495 * hardware will not update the clock until both registers have been 496 * written. 497 */ 498 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 499 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 500 501 /* Update the base adjustement value. */ 502 WRITE_ONCE(pf->ptp_base_adj, incval); 503 smp_mb(); /* Force the above update. */ 504 } 505 506 /** 507 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 508 * @pf: Board private structure 509 * @ifreq: ioctl data 510 * 511 * Obtain the current hardware timestamping settigs as requested. To do this, 512 * keep a shadow copy of the timestamp settings rather than attempting to 513 * deconstruct it from the registers. 514 **/ 515 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 516 { 517 struct hwtstamp_config *config = &pf->tstamp_config; 518 519 if (!(pf->flags & I40E_FLAG_PTP)) 520 return -EOPNOTSUPP; 521 522 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 523 -EFAULT : 0; 524 } 525 526 /** 527 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 528 * @pf: Board private structure 529 * @config: hwtstamp settings requested or saved 530 * 531 * Control hardware registers to enter the specific mode requested by the 532 * user. Also used during reset path to ensure that timestamp settings are 533 * maintained. 534 * 535 * Note: modifies config in place, and may update the requested mode to be 536 * more broad if the specific filter is not directly supported. 537 **/ 538 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 539 struct hwtstamp_config *config) 540 { 541 struct i40e_hw *hw = &pf->hw; 542 u32 tsyntype, regval; 543 544 /* Reserved for future extensions. */ 545 if (config->flags) 546 return -EINVAL; 547 548 switch (config->tx_type) { 549 case HWTSTAMP_TX_OFF: 550 pf->ptp_tx = false; 551 break; 552 case HWTSTAMP_TX_ON: 553 pf->ptp_tx = true; 554 break; 555 default: 556 return -ERANGE; 557 } 558 559 switch (config->rx_filter) { 560 case HWTSTAMP_FILTER_NONE: 561 pf->ptp_rx = false; 562 /* We set the type to V1, but do not enable UDP packet 563 * recognition. In this way, we should be as close to 564 * disabling PTP Rx timestamps as possible since V1 packets 565 * are always UDP, since L2 packets are a V2 feature. 566 */ 567 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 568 break; 569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 570 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 571 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 572 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 573 return -ERANGE; 574 pf->ptp_rx = true; 575 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 576 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 577 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 578 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 579 break; 580 case HWTSTAMP_FILTER_PTP_V2_EVENT: 581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 582 case HWTSTAMP_FILTER_PTP_V2_SYNC: 583 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 584 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 585 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 586 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 587 return -ERANGE; 588 /* fall through */ 589 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 590 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 591 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 592 pf->ptp_rx = true; 593 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 594 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 595 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 596 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 597 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 598 } else { 599 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 600 } 601 break; 602 case HWTSTAMP_FILTER_NTP_ALL: 603 case HWTSTAMP_FILTER_ALL: 604 default: 605 return -ERANGE; 606 } 607 608 /* Clear out all 1588-related registers to clear and unlatch them. */ 609 spin_lock_bh(&pf->ptp_rx_lock); 610 rd32(hw, I40E_PRTTSYN_STAT_0); 611 rd32(hw, I40E_PRTTSYN_TXTIME_H); 612 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 613 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 614 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 615 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 616 pf->latch_event_flags = 0; 617 spin_unlock_bh(&pf->ptp_rx_lock); 618 619 /* Enable/disable the Tx timestamp interrupt based on user input. */ 620 regval = rd32(hw, I40E_PRTTSYN_CTL0); 621 if (pf->ptp_tx) 622 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 623 else 624 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 625 wr32(hw, I40E_PRTTSYN_CTL0, regval); 626 627 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 628 if (pf->ptp_tx) 629 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 630 else 631 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 632 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 633 634 /* Although there is no simple on/off switch for Rx, we "disable" Rx 635 * timestamps by setting to V1 only mode and clear the UDP 636 * recognition. This ought to disable all PTP Rx timestamps as V1 637 * packets are always over UDP. Note that software is configured to 638 * ignore Rx timestamps via the pf->ptp_rx flag. 639 */ 640 regval = rd32(hw, I40E_PRTTSYN_CTL1); 641 /* clear everything but the enable bit */ 642 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 643 /* now enable bits for desired Rx timestamps */ 644 regval |= tsyntype; 645 wr32(hw, I40E_PRTTSYN_CTL1, regval); 646 647 return 0; 648 } 649 650 /** 651 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 652 * @pf: Board private structure 653 * @ifreq: ioctl data 654 * 655 * Respond to the user filter requests and make the appropriate hardware 656 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 657 * logic, so keep track in software of whether to indicate these timestamps 658 * or not. 659 * 660 * It is permissible to "upgrade" the user request to a broader filter, as long 661 * as the user receives the timestamps they care about and the user is notified 662 * the filter has been broadened. 663 **/ 664 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 665 { 666 struct hwtstamp_config config; 667 int err; 668 669 if (!(pf->flags & I40E_FLAG_PTP)) 670 return -EOPNOTSUPP; 671 672 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 673 return -EFAULT; 674 675 err = i40e_ptp_set_timestamp_mode(pf, &config); 676 if (err) 677 return err; 678 679 /* save these settings for future reference */ 680 pf->tstamp_config = config; 681 682 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 683 -EFAULT : 0; 684 } 685 686 /** 687 * i40e_ptp_create_clock - Create PTP clock device for userspace 688 * @pf: Board private structure 689 * 690 * This function creates a new PTP clock device. It only creates one if we 691 * don't already have one, so it is safe to call. Will return error if it 692 * can't create one, but success if we already have a device. Should be used 693 * by i40e_ptp_init to create clock initially, and prevent global resets from 694 * creating new clock devices. 695 **/ 696 static long i40e_ptp_create_clock(struct i40e_pf *pf) 697 { 698 /* no need to create a clock device if we already have one */ 699 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 700 return 0; 701 702 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name)); 703 pf->ptp_caps.owner = THIS_MODULE; 704 pf->ptp_caps.max_adj = 999999999; 705 pf->ptp_caps.n_ext_ts = 0; 706 pf->ptp_caps.pps = 0; 707 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 708 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 709 pf->ptp_caps.gettime64 = i40e_ptp_gettime; 710 pf->ptp_caps.settime64 = i40e_ptp_settime; 711 pf->ptp_caps.enable = i40e_ptp_feature_enable; 712 713 /* Attempt to register the clock before enabling the hardware. */ 714 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 715 if (IS_ERR(pf->ptp_clock)) 716 return PTR_ERR(pf->ptp_clock); 717 718 /* clear the hwtstamp settings here during clock create, instead of 719 * during regular init, so that we can maintain settings across a 720 * reset or suspend. 721 */ 722 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 723 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 724 725 return 0; 726 } 727 728 /** 729 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 730 * @pf: Board private structure 731 * 732 * This function sets device up for 1588 support. The first time it is run, it 733 * will create a PHC clock device. It does not create a clock device if one 734 * already exists. It also reconfigures the device after a reset. 735 **/ 736 void i40e_ptp_init(struct i40e_pf *pf) 737 { 738 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 739 struct i40e_hw *hw = &pf->hw; 740 u32 pf_id; 741 long err; 742 743 /* Only one PF is assigned to control 1588 logic per port. Do not 744 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 745 */ 746 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 747 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 748 if (hw->pf_id != pf_id) { 749 pf->flags &= ~I40E_FLAG_PTP; 750 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 751 __func__, 752 netdev->name); 753 return; 754 } 755 756 mutex_init(&pf->tmreg_lock); 757 spin_lock_init(&pf->ptp_rx_lock); 758 759 /* ensure we have a clock device */ 760 err = i40e_ptp_create_clock(pf); 761 if (err) { 762 pf->ptp_clock = NULL; 763 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 764 __func__); 765 } else if (pf->ptp_clock) { 766 struct timespec64 ts; 767 u32 regval; 768 769 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 770 dev_info(&pf->pdev->dev, "PHC enabled\n"); 771 pf->flags |= I40E_FLAG_PTP; 772 773 /* Ensure the clocks are running. */ 774 regval = rd32(hw, I40E_PRTTSYN_CTL0); 775 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 776 wr32(hw, I40E_PRTTSYN_CTL0, regval); 777 regval = rd32(hw, I40E_PRTTSYN_CTL1); 778 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 779 wr32(hw, I40E_PRTTSYN_CTL1, regval); 780 781 /* Set the increment value per clock tick. */ 782 i40e_ptp_set_increment(pf); 783 784 /* reset timestamping mode */ 785 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 786 787 /* Set the clock value. */ 788 ts = ktime_to_timespec64(ktime_get_real()); 789 i40e_ptp_settime(&pf->ptp_caps, &ts); 790 } 791 } 792 793 /** 794 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 795 * @pf: Board private structure 796 * 797 * This function handles the cleanup work required from the initialization by 798 * clearing out the important information and unregistering the PHC. 799 **/ 800 void i40e_ptp_stop(struct i40e_pf *pf) 801 { 802 pf->flags &= ~I40E_FLAG_PTP; 803 pf->ptp_tx = false; 804 pf->ptp_rx = false; 805 806 if (pf->ptp_tx_skb) { 807 dev_kfree_skb_any(pf->ptp_tx_skb); 808 pf->ptp_tx_skb = NULL; 809 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 810 } 811 812 if (pf->ptp_clock) { 813 ptp_clock_unregister(pf->ptp_clock); 814 pf->ptp_clock = NULL; 815 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 816 pf->vsi[pf->lan_vsi]->netdev->name); 817 } 818 } 819