1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include <linux/ptp_classify.h> 6 #include <linux/posix-clock.h> 7 8 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 9 * the fundamental clock design. However, the clock operations are much simpler 10 * in the XL710 because the device supports a full 64 bits of nanoseconds. 11 * Because the field is so wide, we can forgo the cycle counter and just 12 * operate with the nanosecond field directly without fear of overflow. 13 * 14 * Much like the 82599, the update period is dependent upon the link speed: 15 * At 40Gb, 25Gb, or no link, the period is 1.6ns. 16 * At 10Gb or 5Gb link, the period is multiplied by 2. (3.2ns) 17 * At 1Gb link, the period is multiplied by 20. (32ns) 18 * 1588 functionality is not supported at 100Mbps. 19 */ 20 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 21 #define I40E_PTP_10GB_INCVAL_MULT 2 22 #define I40E_PTP_5GB_INCVAL_MULT 2 23 #define I40E_PTP_1GB_INCVAL_MULT 20 24 #define I40E_ISGN 0x80000000 25 26 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 27 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 28 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 29 #define I40E_SUBDEV_ID_25G_PTP_PIN 0xB 30 31 enum i40e_ptp_pin { 32 SDP3_2 = 0, 33 SDP3_3, 34 GPIO_4 35 }; 36 37 enum i40e_can_set_pins_t { 38 CANT_DO_PINS = -1, 39 CAN_SET_PINS, 40 CAN_DO_PINS 41 }; 42 43 static struct ptp_pin_desc sdp_desc[] = { 44 /* name idx func chan */ 45 {"SDP3_2", SDP3_2, PTP_PF_NONE, 0}, 46 {"SDP3_3", SDP3_3, PTP_PF_NONE, 1}, 47 {"GPIO_4", GPIO_4, PTP_PF_NONE, 1}, 48 }; 49 50 enum i40e_ptp_gpio_pin_state { 51 end = -2, 52 invalid, 53 off, 54 in_A, 55 in_B, 56 out_A, 57 out_B, 58 }; 59 60 static const char * const i40e_ptp_gpio_pin_state2str[] = { 61 "off", "in_A", "in_B", "out_A", "out_B" 62 }; 63 64 enum i40e_ptp_led_pin_state { 65 led_end = -2, 66 low = 0, 67 high, 68 }; 69 70 struct i40e_ptp_pins_settings { 71 enum i40e_ptp_gpio_pin_state sdp3_2; 72 enum i40e_ptp_gpio_pin_state sdp3_3; 73 enum i40e_ptp_gpio_pin_state gpio_4; 74 enum i40e_ptp_led_pin_state led2_0; 75 enum i40e_ptp_led_pin_state led2_1; 76 enum i40e_ptp_led_pin_state led3_0; 77 enum i40e_ptp_led_pin_state led3_1; 78 }; 79 80 static const struct i40e_ptp_pins_settings 81 i40e_ptp_pin_led_allowed_states[] = { 82 {off, off, off, high, high, high, high}, 83 {off, in_A, off, high, high, high, low}, 84 {off, out_A, off, high, low, high, high}, 85 {off, in_B, off, high, high, high, low}, 86 {off, out_B, off, high, low, high, high}, 87 {in_A, off, off, high, high, high, low}, 88 {in_A, in_B, off, high, high, high, low}, 89 {in_A, out_B, off, high, low, high, high}, 90 {out_A, off, off, high, low, high, high}, 91 {out_A, in_B, off, high, low, high, high}, 92 {in_B, off, off, high, high, high, low}, 93 {in_B, in_A, off, high, high, high, low}, 94 {in_B, out_A, off, high, low, high, high}, 95 {out_B, off, off, high, low, high, high}, 96 {out_B, in_A, off, high, low, high, high}, 97 {off, off, in_A, high, high, low, high}, 98 {off, out_A, in_A, high, low, low, high}, 99 {off, in_B, in_A, high, high, low, low}, 100 {off, out_B, in_A, high, low, low, high}, 101 {out_A, off, in_A, high, low, low, high}, 102 {out_A, in_B, in_A, high, low, low, high}, 103 {in_B, off, in_A, high, high, low, low}, 104 {in_B, out_A, in_A, high, low, low, high}, 105 {out_B, off, in_A, high, low, low, high}, 106 {off, off, out_A, low, high, high, high}, 107 {off, in_A, out_A, low, high, high, low}, 108 {off, in_B, out_A, low, high, high, low}, 109 {off, out_B, out_A, low, low, high, high}, 110 {in_A, off, out_A, low, high, high, low}, 111 {in_A, in_B, out_A, low, high, high, low}, 112 {in_A, out_B, out_A, low, low, high, high}, 113 {in_B, off, out_A, low, high, high, low}, 114 {in_B, in_A, out_A, low, high, high, low}, 115 {out_B, off, out_A, low, low, high, high}, 116 {out_B, in_A, out_A, low, low, high, high}, 117 {off, off, in_B, high, high, low, high}, 118 {off, in_A, in_B, high, high, low, low}, 119 {off, out_A, in_B, high, low, low, high}, 120 {off, out_B, in_B, high, low, low, high}, 121 {in_A, off, in_B, high, high, low, low}, 122 {in_A, out_B, in_B, high, low, low, high}, 123 {out_A, off, in_B, high, low, low, high}, 124 {out_B, off, in_B, high, low, low, high}, 125 {out_B, in_A, in_B, high, low, low, high}, 126 {off, off, out_B, low, high, high, high}, 127 {off, in_A, out_B, low, high, high, low}, 128 {off, out_A, out_B, low, low, high, high}, 129 {off, in_B, out_B, low, high, high, low}, 130 {in_A, off, out_B, low, high, high, low}, 131 {in_A, in_B, out_B, low, high, high, low}, 132 {out_A, off, out_B, low, low, high, high}, 133 {out_A, in_B, out_B, low, low, high, high}, 134 {in_B, off, out_B, low, high, high, low}, 135 {in_B, in_A, out_B, low, high, high, low}, 136 {in_B, out_A, out_B, low, low, high, high}, 137 {end, end, end, led_end, led_end, led_end, led_end} 138 }; 139 140 static int i40e_ptp_set_pins(struct i40e_pf *pf, 141 struct i40e_ptp_pins_settings *pins); 142 143 /** 144 * i40e_ptp_extts0_work - workqueue task function 145 * @work: workqueue task structure 146 * 147 * Service for PTP external clock event 148 **/ 149 static void i40e_ptp_extts0_work(struct work_struct *work) 150 { 151 struct i40e_pf *pf = container_of(work, struct i40e_pf, 152 ptp_extts0_work); 153 struct i40e_hw *hw = &pf->hw; 154 struct ptp_clock_event event; 155 u32 hi, lo; 156 157 /* Event time is captured by one of the two matched registers 158 * PRTTSYN_EVNT_L: 32 LSB of sampled time event 159 * PRTTSYN_EVNT_H: 32 MSB of sampled time event 160 * Event is defined in PRTTSYN_EVNT_0 register 161 */ 162 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0)); 163 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0)); 164 165 event.timestamp = (((u64)hi) << 32) | lo; 166 167 event.type = PTP_CLOCK_EXTTS; 168 event.index = hw->pf_id; 169 170 /* fire event */ 171 ptp_clock_event(pf->ptp_clock, &event); 172 } 173 174 /** 175 * i40e_is_ptp_pin_dev - check if device supports PTP pins 176 * @hw: pointer to the hardware structure 177 * 178 * Return true if device supports PTP pins, false otherwise. 179 **/ 180 static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw) 181 { 182 return hw->device_id == I40E_DEV_ID_25G_SFP28 && 183 hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN; 184 } 185 186 /** 187 * i40e_can_set_pins - check possibility of manipulating the pins 188 * @pf: board private structure 189 * 190 * Check if all conditions are satisfied to manipulate PTP pins. 191 * Return CAN_SET_PINS if pins can be set on a specific PF or 192 * return CAN_DO_PINS if pins can be manipulated within a NIC or 193 * return CANT_DO_PINS otherwise. 194 **/ 195 static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf) 196 { 197 if (!i40e_is_ptp_pin_dev(&pf->hw)) { 198 dev_warn(&pf->pdev->dev, 199 "PTP external clock not supported.\n"); 200 return CANT_DO_PINS; 201 } 202 203 if (!pf->ptp_pins) { 204 dev_warn(&pf->pdev->dev, 205 "PTP PIN manipulation not allowed.\n"); 206 return CANT_DO_PINS; 207 } 208 209 if (pf->hw.pf_id) { 210 dev_warn(&pf->pdev->dev, 211 "PTP PINs should be accessed via PF0.\n"); 212 return CAN_DO_PINS; 213 } 214 215 return CAN_SET_PINS; 216 } 217 218 /** 219 * i40_ptp_reset_timing_events - Reset PTP timing events 220 * @pf: Board private structure 221 * 222 * This function resets timing events for pf. 223 **/ 224 static void i40_ptp_reset_timing_events(struct i40e_pf *pf) 225 { 226 u32 i; 227 228 spin_lock_bh(&pf->ptp_rx_lock); 229 for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) { 230 /* reading and automatically clearing timing events registers */ 231 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i)); 232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i)); 233 pf->latch_events[i] = 0; 234 } 235 /* reading and automatically clearing timing events registers */ 236 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L); 237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H); 238 239 pf->tx_hwtstamp_timeouts = 0; 240 pf->tx_hwtstamp_skipped = 0; 241 pf->rx_hwtstamp_cleared = 0; 242 pf->latch_event_flags = 0; 243 spin_unlock_bh(&pf->ptp_rx_lock); 244 } 245 246 /** 247 * i40e_ptp_verify - check pins 248 * @ptp: ptp clock 249 * @pin: pin index 250 * @func: assigned function 251 * @chan: channel 252 * 253 * Check pins consistency. 254 * Return 0 on success or error on failure. 255 **/ 256 static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin, 257 enum ptp_pin_function func, unsigned int chan) 258 { 259 switch (func) { 260 case PTP_PF_NONE: 261 case PTP_PF_EXTTS: 262 case PTP_PF_PEROUT: 263 break; 264 case PTP_PF_PHYSYNC: 265 return -EOPNOTSUPP; 266 } 267 return 0; 268 } 269 270 /** 271 * i40e_ptp_read - Read the PHC time from the device 272 * @pf: Board private structure 273 * @ts: timespec structure to hold the current time value 274 * @sts: structure to hold the system time before and after reading the PHC 275 * 276 * This function reads the PRTTSYN_TIME registers and stores them in a 277 * timespec. However, since the registers are 64 bits of nanoseconds, we must 278 * convert the result to a timespec before we can return. 279 **/ 280 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, 281 struct ptp_system_timestamp *sts) 282 { 283 struct i40e_hw *hw = &pf->hw; 284 u32 hi, lo; 285 u64 ns; 286 287 /* The timer latches on the lowest register read. */ 288 ptp_read_system_prets(sts); 289 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 290 ptp_read_system_postts(sts); 291 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 292 293 ns = (((u64)hi) << 32) | lo; 294 295 *ts = ns_to_timespec64(ns); 296 } 297 298 /** 299 * i40e_ptp_write - Write the PHC time to the device 300 * @pf: Board private structure 301 * @ts: timespec structure that holds the new time value 302 * 303 * This function writes the PRTTSYN_TIME registers with the user value. Since 304 * we receive a timespec from the stack, we must convert that timespec into 305 * nanoseconds before programming the registers. 306 **/ 307 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 308 { 309 struct i40e_hw *hw = &pf->hw; 310 u64 ns = timespec64_to_ns(ts); 311 312 /* The timer will not update until the high register is written, so 313 * write the low register first. 314 */ 315 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 316 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 317 } 318 319 /** 320 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 321 * @hwtstamps: Timestamp structure to update 322 * @timestamp: Timestamp from the hardware 323 * 324 * We need to convert the NIC clock value into a hwtstamp which can be used by 325 * the upper level timestamping functions. Since the timestamp is simply a 64- 326 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 327 **/ 328 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 329 u64 timestamp) 330 { 331 memset(hwtstamps, 0, sizeof(*hwtstamps)); 332 333 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 334 } 335 336 /** 337 * i40e_ptp_adjfine - Adjust the PHC frequency 338 * @ptp: The PTP clock structure 339 * @scaled_ppm: Scaled parts per million adjustment from base 340 * 341 * Adjust the frequency of the PHC by the indicated delta from the base 342 * frequency. 343 * 344 * Scaled parts per million is ppm with a 16 bit binary fractional field. 345 **/ 346 static int i40e_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 347 { 348 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 349 struct i40e_hw *hw = &pf->hw; 350 u64 adj, base_adj; 351 352 smp_mb(); /* Force any pending update before accessing. */ 353 base_adj = I40E_PTP_40GB_INCVAL * READ_ONCE(pf->ptp_adj_mult); 354 355 adj = adjust_by_scaled_ppm(base_adj, scaled_ppm); 356 357 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 358 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 359 360 return 0; 361 } 362 363 /** 364 * i40e_ptp_set_1pps_signal_hw - configure 1PPS PTP signal for pins 365 * @pf: the PF private data structure 366 * 367 * Configure 1PPS signal used for PTP pins 368 **/ 369 static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf) 370 { 371 struct i40e_hw *hw = &pf->hw; 372 struct timespec64 now; 373 u64 ns; 374 375 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0); 376 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 377 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE); 378 379 i40e_ptp_read(pf, &now, NULL); 380 now.tv_sec += I40E_PTP_2_SEC_DELAY; 381 now.tv_nsec = 0; 382 ns = timespec64_to_ns(&now); 383 384 /* I40E_PRTTSYN_TGT_L(1) */ 385 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF); 386 /* I40E_PRTTSYN_TGT_H(1) */ 387 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32); 388 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND); 389 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT); 390 wr32(hw, I40E_PRTTSYN_AUX_0(1), 391 I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD); 392 } 393 394 /** 395 * i40e_ptp_adjtime - Adjust the PHC time 396 * @ptp: The PTP clock structure 397 * @delta: Offset in nanoseconds to adjust the PHC time by 398 * 399 * Adjust the current clock time by a delta specified in nanoseconds. 400 **/ 401 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 402 { 403 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 404 struct i40e_hw *hw = &pf->hw; 405 406 mutex_lock(&pf->tmreg_lock); 407 408 if (delta > -999999900LL && delta < 999999900LL) { 409 int neg_adj = 0; 410 u32 timadj; 411 u64 tohw; 412 413 if (delta < 0) { 414 neg_adj = 1; 415 tohw = -delta; 416 } else { 417 tohw = delta; 418 } 419 420 timadj = tohw & 0x3FFFFFFF; 421 if (neg_adj) 422 timadj |= I40E_ISGN; 423 wr32(hw, I40E_PRTTSYN_ADJ, timadj); 424 } else { 425 struct timespec64 then, now; 426 427 then = ns_to_timespec64(delta); 428 i40e_ptp_read(pf, &now, NULL); 429 now = timespec64_add(now, then); 430 i40e_ptp_write(pf, (const struct timespec64 *)&now); 431 i40e_ptp_set_1pps_signal_hw(pf); 432 } 433 434 mutex_unlock(&pf->tmreg_lock); 435 436 return 0; 437 } 438 439 /** 440 * i40e_ptp_gettimex - Get the time of the PHC 441 * @ptp: The PTP clock structure 442 * @ts: timespec structure to hold the current time value 443 * @sts: structure to hold the system time before and after reading the PHC 444 * 445 * Read the device clock and return the correct value on ns, after converting it 446 * into a timespec struct. 447 **/ 448 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 449 struct ptp_system_timestamp *sts) 450 { 451 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 452 453 mutex_lock(&pf->tmreg_lock); 454 i40e_ptp_read(pf, ts, sts); 455 mutex_unlock(&pf->tmreg_lock); 456 457 return 0; 458 } 459 460 /** 461 * i40e_ptp_settime - Set the time of the PHC 462 * @ptp: The PTP clock structure 463 * @ts: timespec64 structure that holds the new time value 464 * 465 * Set the device clock to the user input value. The conversion from timespec 466 * to ns happens in the write function. 467 **/ 468 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 469 const struct timespec64 *ts) 470 { 471 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 472 473 mutex_lock(&pf->tmreg_lock); 474 i40e_ptp_write(pf, ts); 475 mutex_unlock(&pf->tmreg_lock); 476 477 return 0; 478 } 479 480 /** 481 * i40e_pps_configure - configure PPS events 482 * @ptp: ptp clock 483 * @rq: clock request 484 * @on: status 485 * 486 * Configure PPS events for external clock source. 487 * Return 0 on success or error on failure. 488 **/ 489 static int i40e_pps_configure(struct ptp_clock_info *ptp, 490 struct ptp_clock_request *rq, 491 int on) 492 { 493 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 494 495 if (!!on) 496 i40e_ptp_set_1pps_signal_hw(pf); 497 498 return 0; 499 } 500 501 /** 502 * i40e_pin_state - determine PIN state 503 * @index: PIN index 504 * @func: function assigned to PIN 505 * 506 * Determine PIN state based on PIN index and function assigned. 507 * Return PIN state. 508 **/ 509 static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func) 510 { 511 enum i40e_ptp_gpio_pin_state state = off; 512 513 if (index == 0 && func == PTP_PF_EXTTS) 514 state = in_A; 515 if (index == 1 && func == PTP_PF_EXTTS) 516 state = in_B; 517 if (index == 0 && func == PTP_PF_PEROUT) 518 state = out_A; 519 if (index == 1 && func == PTP_PF_PEROUT) 520 state = out_B; 521 522 return state; 523 } 524 525 /** 526 * i40e_ptp_enable_pin - enable PINs. 527 * @pf: private board structure 528 * @chan: channel 529 * @func: PIN function 530 * @on: state 531 * 532 * Enable PTP pins for external clock source. 533 * Return 0 on success or error code on failure. 534 **/ 535 static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan, 536 enum ptp_pin_function func, int on) 537 { 538 enum i40e_ptp_gpio_pin_state *pin = NULL; 539 struct i40e_ptp_pins_settings pins; 540 int pin_index; 541 542 /* Use PF0 to set pins. Return success for user space tools */ 543 if (pf->hw.pf_id) 544 return 0; 545 546 /* Preserve previous state of pins that we don't touch */ 547 pins.sdp3_2 = pf->ptp_pins->sdp3_2; 548 pins.sdp3_3 = pf->ptp_pins->sdp3_3; 549 pins.gpio_4 = pf->ptp_pins->gpio_4; 550 551 /* To turn on the pin - find the corresponding one based on 552 * the given index. To to turn the function off - find 553 * which pin had it assigned. Don't use ptp_find_pin here 554 * because it tries to lock the pincfg_mux which is locked by 555 * ptp_pin_store() that calls here. 556 */ 557 if (on) { 558 pin_index = ptp_find_pin(pf->ptp_clock, func, chan); 559 if (pin_index < 0) 560 return -EBUSY; 561 562 switch (pin_index) { 563 case SDP3_2: 564 pin = &pins.sdp3_2; 565 break; 566 case SDP3_3: 567 pin = &pins.sdp3_3; 568 break; 569 case GPIO_4: 570 pin = &pins.gpio_4; 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 *pin = i40e_pin_state(chan, func); 577 } else { 578 pins.sdp3_2 = off; 579 pins.sdp3_3 = off; 580 pins.gpio_4 = off; 581 } 582 583 return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0; 584 } 585 586 /** 587 * i40e_ptp_feature_enable - Enable external clock pins 588 * @ptp: The PTP clock structure 589 * @rq: The PTP clock request structure 590 * @on: To turn feature on/off 591 * 592 * Setting on/off PTP PPS feature for pin. 593 **/ 594 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 595 struct ptp_clock_request *rq, 596 int on) 597 { 598 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 599 600 enum ptp_pin_function func; 601 unsigned int chan; 602 603 /* TODO: Implement flags handling for EXTTS and PEROUT */ 604 switch (rq->type) { 605 case PTP_CLK_REQ_EXTTS: 606 func = PTP_PF_EXTTS; 607 chan = rq->extts.index; 608 break; 609 case PTP_CLK_REQ_PEROUT: 610 func = PTP_PF_PEROUT; 611 chan = rq->perout.index; 612 break; 613 case PTP_CLK_REQ_PPS: 614 return i40e_pps_configure(ptp, rq, on); 615 default: 616 return -EOPNOTSUPP; 617 } 618 619 return i40e_ptp_enable_pin(pf, chan, func, on); 620 } 621 622 /** 623 * i40e_ptp_get_rx_events - Read I40E_PRTTSYN_STAT_1 and latch events 624 * @pf: the PF data structure 625 * 626 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 627 * for noticed latch events. This allows the driver to keep track of the first 628 * time a latch event was noticed which will be used to help clear out Rx 629 * timestamps for packets that got dropped or lost. 630 * 631 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 632 * expected to be called only while under the ptp_rx_lock. 633 **/ 634 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 635 { 636 struct i40e_hw *hw = &pf->hw; 637 u32 prttsyn_stat, new_latch_events; 638 int i; 639 640 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 641 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 642 643 /* Update the jiffies time for any newly latched timestamp. This 644 * ensures that we store the time that we first discovered a timestamp 645 * was latched by the hardware. The service task will later determine 646 * if we should free the latch and drop that timestamp should too much 647 * time pass. This flow ensures that we only update jiffies for new 648 * events latched since the last time we checked, and not all events 649 * currently latched, so that the service task accounting remains 650 * accurate. 651 */ 652 for (i = 0; i < 4; i++) { 653 if (new_latch_events & BIT(i)) 654 pf->latch_events[i] = jiffies; 655 } 656 657 /* Finally, we store the current status of the Rx timestamp latches */ 658 pf->latch_event_flags = prttsyn_stat; 659 660 return prttsyn_stat; 661 } 662 663 /** 664 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 665 * @pf: The PF private data structure 666 * 667 * This watchdog task is scheduled to detect error case where hardware has 668 * dropped an Rx packet that was timestamped when the ring is full. The 669 * particular error is rare but leaves the device in a state unable to timestamp 670 * any future packets. 671 **/ 672 void i40e_ptp_rx_hang(struct i40e_pf *pf) 673 { 674 struct i40e_hw *hw = &pf->hw; 675 unsigned int i, cleared = 0; 676 677 /* Since we cannot turn off the Rx timestamp logic if the device is 678 * configured for Tx timestamping, we check if Rx timestamping is 679 * configured. We don't want to spuriously warn about Rx timestamp 680 * hangs if we don't care about the timestamps. 681 */ 682 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 683 return; 684 685 spin_lock_bh(&pf->ptp_rx_lock); 686 687 /* Update current latch times for Rx events */ 688 i40e_ptp_get_rx_events(pf); 689 690 /* Check all the currently latched Rx events and see whether they have 691 * been latched for over a second. It is assumed that any timestamp 692 * should have been cleared within this time, or else it was captured 693 * for a dropped frame that the driver never received. Thus, we will 694 * clear any timestamp that has been latched for over 1 second. 695 */ 696 for (i = 0; i < 4; i++) { 697 if ((pf->latch_event_flags & BIT(i)) && 698 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 699 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 700 pf->latch_event_flags &= ~BIT(i); 701 cleared++; 702 } 703 } 704 705 spin_unlock_bh(&pf->ptp_rx_lock); 706 707 /* Log a warning if more than 2 timestamps got dropped in the same 708 * check. We don't want to warn about all drops because it can occur 709 * in normal scenarios such as PTP frames on multicast addresses we 710 * aren't listening to. However, administrator should know if this is 711 * the reason packets aren't receiving timestamps. 712 */ 713 if (cleared > 2) 714 dev_dbg(&pf->pdev->dev, 715 "Dropped %d missed RXTIME timestamp events\n", 716 cleared); 717 718 /* Finally, update the rx_hwtstamp_cleared counter */ 719 pf->rx_hwtstamp_cleared += cleared; 720 } 721 722 /** 723 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 724 * @pf: The PF private data structure 725 * 726 * This watchdog task is run periodically to make sure that we clear the Tx 727 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 728 * time. It is unexpected in the normal case but if it occurs it results in 729 * permanently preventing timestamps of future packets. 730 **/ 731 void i40e_ptp_tx_hang(struct i40e_pf *pf) 732 { 733 struct sk_buff *skb; 734 735 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 736 return; 737 738 /* Nothing to do if we're not already waiting for a timestamp */ 739 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 740 return; 741 742 /* We already have a handler routine which is run when we are notified 743 * of a Tx timestamp in the hardware. If we don't get an interrupt 744 * within a second it is reasonable to assume that we never will. 745 */ 746 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 747 skb = pf->ptp_tx_skb; 748 pf->ptp_tx_skb = NULL; 749 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 750 751 /* Free the skb after we clear the bitlock */ 752 dev_kfree_skb_any(skb); 753 pf->tx_hwtstamp_timeouts++; 754 } 755 } 756 757 /** 758 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 759 * @pf: Board private structure 760 * 761 * Read the value of the Tx timestamp from the registers, convert it into a 762 * value consumable by the stack, and store that result into the shhwtstamps 763 * struct before returning it up the stack. 764 **/ 765 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 766 { 767 struct skb_shared_hwtstamps shhwtstamps; 768 struct sk_buff *skb = pf->ptp_tx_skb; 769 struct i40e_hw *hw = &pf->hw; 770 u32 hi, lo; 771 u64 ns; 772 773 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 774 return; 775 776 /* don't attempt to timestamp if we don't have an skb */ 777 if (!pf->ptp_tx_skb) 778 return; 779 780 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 781 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 782 783 ns = (((u64)hi) << 32) | lo; 784 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 785 786 /* Clear the bit lock as soon as possible after reading the register, 787 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 788 * applications might wake up and attempt to request another transmit 789 * timestamp prior to the bit lock being cleared. 790 */ 791 pf->ptp_tx_skb = NULL; 792 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 793 794 /* Notify the stack and free the skb after we've unlocked */ 795 skb_tstamp_tx(skb, &shhwtstamps); 796 dev_kfree_skb_any(skb); 797 } 798 799 /** 800 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 801 * @pf: Board private structure 802 * @skb: Particular skb to send timestamp with 803 * @index: Index into the receive timestamp registers for the timestamp 804 * 805 * The XL710 receives a notification in the receive descriptor with an offset 806 * into the set of RXTIME registers where the timestamp is for that skb. This 807 * function goes and fetches the receive timestamp from that offset, if a valid 808 * one exists. The RXTIME registers are in ns, so we must convert the result 809 * first. 810 **/ 811 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 812 { 813 u32 prttsyn_stat, hi, lo; 814 struct i40e_hw *hw; 815 u64 ns; 816 817 /* Since we cannot turn off the Rx timestamp logic if the device is 818 * doing Tx timestamping, check if Rx timestamping is configured. 819 */ 820 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 821 return; 822 823 hw = &pf->hw; 824 825 spin_lock_bh(&pf->ptp_rx_lock); 826 827 /* Get current Rx events and update latch times */ 828 prttsyn_stat = i40e_ptp_get_rx_events(pf); 829 830 /* TODO: Should we warn about missing Rx timestamp event? */ 831 if (!(prttsyn_stat & BIT(index))) { 832 spin_unlock_bh(&pf->ptp_rx_lock); 833 return; 834 } 835 836 /* Clear the latched event since we're about to read its register */ 837 pf->latch_event_flags &= ~BIT(index); 838 839 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 840 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 841 842 spin_unlock_bh(&pf->ptp_rx_lock); 843 844 ns = (((u64)hi) << 32) | lo; 845 846 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 847 } 848 849 /** 850 * i40e_ptp_set_increment - Utility function to update clock increment rate 851 * @pf: Board private structure 852 * 853 * During a link change, the DMA frequency that drives the 1588 logic will 854 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 855 * we must update the increment value per clock tick. 856 **/ 857 void i40e_ptp_set_increment(struct i40e_pf *pf) 858 { 859 struct i40e_link_status *hw_link_info; 860 struct i40e_hw *hw = &pf->hw; 861 u64 incval; 862 u32 mult; 863 864 hw_link_info = &hw->phy.link_info; 865 866 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 867 868 switch (hw_link_info->link_speed) { 869 case I40E_LINK_SPEED_10GB: 870 mult = I40E_PTP_10GB_INCVAL_MULT; 871 break; 872 case I40E_LINK_SPEED_5GB: 873 mult = I40E_PTP_5GB_INCVAL_MULT; 874 break; 875 case I40E_LINK_SPEED_1GB: 876 mult = I40E_PTP_1GB_INCVAL_MULT; 877 break; 878 case I40E_LINK_SPEED_100MB: 879 { 880 static int warn_once; 881 882 if (!warn_once) { 883 dev_warn(&pf->pdev->dev, 884 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 885 warn_once++; 886 } 887 mult = 0; 888 break; 889 } 890 case I40E_LINK_SPEED_40GB: 891 default: 892 mult = 1; 893 break; 894 } 895 896 /* The increment value is calculated by taking the base 40GbE incvalue 897 * and multiplying it by a factor based on the link speed. 898 */ 899 incval = I40E_PTP_40GB_INCVAL * mult; 900 901 /* Write the new increment value into the increment register. The 902 * hardware will not update the clock until both registers have been 903 * written. 904 */ 905 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 906 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 907 908 /* Update the base adjustement value. */ 909 WRITE_ONCE(pf->ptp_adj_mult, mult); 910 smp_mb(); /* Force the above update. */ 911 } 912 913 /** 914 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 915 * @pf: Board private structure 916 * @ifr: ioctl data 917 * 918 * Obtain the current hardware timestamping settigs as requested. To do this, 919 * keep a shadow copy of the timestamp settings rather than attempting to 920 * deconstruct it from the registers. 921 **/ 922 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 923 { 924 struct hwtstamp_config *config = &pf->tstamp_config; 925 926 if (!(pf->flags & I40E_FLAG_PTP)) 927 return -EOPNOTSUPP; 928 929 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 930 -EFAULT : 0; 931 } 932 933 /** 934 * i40e_ptp_free_pins - free memory used by PTP pins 935 * @pf: Board private structure 936 * 937 * Release memory allocated for PTP pins. 938 **/ 939 static void i40e_ptp_free_pins(struct i40e_pf *pf) 940 { 941 if (i40e_is_ptp_pin_dev(&pf->hw)) { 942 kfree(pf->ptp_pins); 943 kfree(pf->ptp_caps.pin_config); 944 pf->ptp_pins = NULL; 945 } 946 } 947 948 /** 949 * i40e_ptp_set_pin_hw - Set HW GPIO pin 950 * @hw: pointer to the hardware structure 951 * @pin: pin index 952 * @state: pin state 953 * 954 * Set status of GPIO pin for external clock handling. 955 **/ 956 static void i40e_ptp_set_pin_hw(struct i40e_hw *hw, 957 unsigned int pin, 958 enum i40e_ptp_gpio_pin_state state) 959 { 960 switch (state) { 961 case off: 962 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0); 963 break; 964 case in_A: 965 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 966 I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0); 967 break; 968 case in_B: 969 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 970 I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0); 971 break; 972 case out_A: 973 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 974 I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1); 975 break; 976 case out_B: 977 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 978 I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1); 979 break; 980 default: 981 break; 982 } 983 } 984 985 /** 986 * i40e_ptp_set_led_hw - Set HW GPIO led 987 * @hw: pointer to the hardware structure 988 * @led: led index 989 * @state: led state 990 * 991 * Set status of GPIO led for external clock handling. 992 **/ 993 static void i40e_ptp_set_led_hw(struct i40e_hw *hw, 994 unsigned int led, 995 enum i40e_ptp_led_pin_state state) 996 { 997 switch (state) { 998 case low: 999 wr32(hw, I40E_GLGEN_GPIO_SET, 1000 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led); 1001 break; 1002 case high: 1003 wr32(hw, I40E_GLGEN_GPIO_SET, 1004 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | 1005 I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led); 1006 break; 1007 default: 1008 break; 1009 } 1010 } 1011 1012 /** 1013 * i40e_ptp_init_leds_hw - init LEDs 1014 * @hw: pointer to a hardware structure 1015 * 1016 * Set initial state of LEDs 1017 **/ 1018 static void i40e_ptp_init_leds_hw(struct i40e_hw *hw) 1019 { 1020 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0), 1021 I40E_GLGEN_GPIO_CTL_LED_INIT); 1022 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1), 1023 I40E_GLGEN_GPIO_CTL_LED_INIT); 1024 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0), 1025 I40E_GLGEN_GPIO_CTL_LED_INIT); 1026 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1), 1027 I40E_GLGEN_GPIO_CTL_LED_INIT); 1028 } 1029 1030 /** 1031 * i40e_ptp_set_pins_hw - Set HW GPIO pins 1032 * @pf: Board private structure 1033 * 1034 * This function sets GPIO pins for PTP 1035 **/ 1036 static void i40e_ptp_set_pins_hw(struct i40e_pf *pf) 1037 { 1038 const struct i40e_ptp_pins_settings *pins = pf->ptp_pins; 1039 struct i40e_hw *hw = &pf->hw; 1040 1041 /* pin must be disabled before it may be used */ 1042 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1043 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1044 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1045 1046 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2); 1047 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3); 1048 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4); 1049 1050 i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0); 1051 i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1); 1052 i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0); 1053 i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1); 1054 1055 dev_info(&pf->pdev->dev, 1056 "PTP configuration set to: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1057 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1058 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1059 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1060 } 1061 1062 /** 1063 * i40e_ptp_set_pins - set PTP pins in HW 1064 * @pf: Board private structure 1065 * @pins: PTP pins to be applied 1066 * 1067 * Validate and set PTP pins in HW for specific PF. 1068 * Return 0 on success or negative value on error. 1069 **/ 1070 static int i40e_ptp_set_pins(struct i40e_pf *pf, 1071 struct i40e_ptp_pins_settings *pins) 1072 { 1073 enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf); 1074 int i = 0; 1075 1076 if (pin_caps == CANT_DO_PINS) 1077 return -EOPNOTSUPP; 1078 else if (pin_caps == CAN_DO_PINS) 1079 return 0; 1080 1081 if (pins->sdp3_2 == invalid) 1082 pins->sdp3_2 = pf->ptp_pins->sdp3_2; 1083 if (pins->sdp3_3 == invalid) 1084 pins->sdp3_3 = pf->ptp_pins->sdp3_3; 1085 if (pins->gpio_4 == invalid) 1086 pins->gpio_4 = pf->ptp_pins->gpio_4; 1087 while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) { 1088 if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 && 1089 pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 && 1090 pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) { 1091 pins->led2_0 = 1092 i40e_ptp_pin_led_allowed_states[i].led2_0; 1093 pins->led2_1 = 1094 i40e_ptp_pin_led_allowed_states[i].led2_1; 1095 pins->led3_0 = 1096 i40e_ptp_pin_led_allowed_states[i].led3_0; 1097 pins->led3_1 = 1098 i40e_ptp_pin_led_allowed_states[i].led3_1; 1099 break; 1100 } 1101 i++; 1102 } 1103 if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) { 1104 dev_warn(&pf->pdev->dev, 1105 "Unsupported PTP pin configuration: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n", 1106 i40e_ptp_gpio_pin_state2str[pins->sdp3_2], 1107 i40e_ptp_gpio_pin_state2str[pins->sdp3_3], 1108 i40e_ptp_gpio_pin_state2str[pins->gpio_4]); 1109 1110 return -EPERM; 1111 } 1112 memcpy(pf->ptp_pins, pins, sizeof(*pins)); 1113 i40e_ptp_set_pins_hw(pf); 1114 i40_ptp_reset_timing_events(pf); 1115 1116 return 0; 1117 } 1118 1119 /** 1120 * i40e_ptp_alloc_pins - allocate PTP pins structure 1121 * @pf: Board private structure 1122 * 1123 * allocate PTP pins structure 1124 **/ 1125 int i40e_ptp_alloc_pins(struct i40e_pf *pf) 1126 { 1127 if (!i40e_is_ptp_pin_dev(&pf->hw)) 1128 return 0; 1129 1130 pf->ptp_pins = 1131 kzalloc(sizeof(struct i40e_ptp_pins_settings), GFP_KERNEL); 1132 1133 if (!pf->ptp_pins) { 1134 dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n"); 1135 return -I40E_ERR_NO_MEMORY; 1136 } 1137 1138 pf->ptp_pins->sdp3_2 = off; 1139 pf->ptp_pins->sdp3_3 = off; 1140 pf->ptp_pins->gpio_4 = off; 1141 pf->ptp_pins->led2_0 = high; 1142 pf->ptp_pins->led2_1 = high; 1143 pf->ptp_pins->led3_0 = high; 1144 pf->ptp_pins->led3_1 = high; 1145 1146 /* Use PF0 to set pins in HW. Return success for user space tools */ 1147 if (pf->hw.pf_id) 1148 return 0; 1149 1150 i40e_ptp_init_leds_hw(&pf->hw); 1151 i40e_ptp_set_pins_hw(pf); 1152 1153 return 0; 1154 } 1155 1156 /** 1157 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 1158 * @pf: Board private structure 1159 * @config: hwtstamp settings requested or saved 1160 * 1161 * Control hardware registers to enter the specific mode requested by the 1162 * user. Also used during reset path to ensure that timestamp settings are 1163 * maintained. 1164 * 1165 * Note: modifies config in place, and may update the requested mode to be 1166 * more broad if the specific filter is not directly supported. 1167 **/ 1168 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 1169 struct hwtstamp_config *config) 1170 { 1171 struct i40e_hw *hw = &pf->hw; 1172 u32 tsyntype, regval; 1173 1174 /* Selects external trigger to cause event */ 1175 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1176 /* Bit 17:16 is EVNTLVL, 01B rising edge */ 1177 regval &= 0; 1178 regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT); 1179 /* regval: 0001 0000 0000 0000 0000 */ 1180 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1181 1182 /* Enabel interrupts */ 1183 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1184 regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT; 1185 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1186 1187 INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work); 1188 1189 switch (config->tx_type) { 1190 case HWTSTAMP_TX_OFF: 1191 pf->ptp_tx = false; 1192 break; 1193 case HWTSTAMP_TX_ON: 1194 pf->ptp_tx = true; 1195 break; 1196 default: 1197 return -ERANGE; 1198 } 1199 1200 switch (config->rx_filter) { 1201 case HWTSTAMP_FILTER_NONE: 1202 pf->ptp_rx = false; 1203 /* We set the type to V1, but do not enable UDP packet 1204 * recognition. In this way, we should be as close to 1205 * disabling PTP Rx timestamps as possible since V1 packets 1206 * are always UDP, since L2 packets are a V2 feature. 1207 */ 1208 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 1209 break; 1210 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1211 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1212 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1213 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 1214 return -ERANGE; 1215 pf->ptp_rx = true; 1216 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 1217 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 1218 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 1219 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1220 break; 1221 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1222 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1223 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1224 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1225 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1226 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1227 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 1228 return -ERANGE; 1229 fallthrough; 1230 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1231 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1232 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1233 pf->ptp_rx = true; 1234 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 1235 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 1236 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 1237 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 1238 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1239 } else { 1240 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1241 } 1242 break; 1243 case HWTSTAMP_FILTER_NTP_ALL: 1244 case HWTSTAMP_FILTER_ALL: 1245 default: 1246 return -ERANGE; 1247 } 1248 1249 /* Clear out all 1588-related registers to clear and unlatch them. */ 1250 spin_lock_bh(&pf->ptp_rx_lock); 1251 rd32(hw, I40E_PRTTSYN_STAT_0); 1252 rd32(hw, I40E_PRTTSYN_TXTIME_H); 1253 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 1254 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 1255 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 1256 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 1257 pf->latch_event_flags = 0; 1258 spin_unlock_bh(&pf->ptp_rx_lock); 1259 1260 /* Enable/disable the Tx timestamp interrupt based on user input. */ 1261 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1262 if (pf->ptp_tx) 1263 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1264 else 1265 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 1266 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1267 1268 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 1269 if (pf->ptp_tx) 1270 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1271 else 1272 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 1273 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 1274 1275 /* Although there is no simple on/off switch for Rx, we "disable" Rx 1276 * timestamps by setting to V1 only mode and clear the UDP 1277 * recognition. This ought to disable all PTP Rx timestamps as V1 1278 * packets are always over UDP. Note that software is configured to 1279 * ignore Rx timestamps via the pf->ptp_rx flag. 1280 */ 1281 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1282 /* clear everything but the enable bit */ 1283 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1284 /* now enable bits for desired Rx timestamps */ 1285 regval |= tsyntype; 1286 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1287 1288 return 0; 1289 } 1290 1291 /** 1292 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 1293 * @pf: Board private structure 1294 * @ifr: ioctl data 1295 * 1296 * Respond to the user filter requests and make the appropriate hardware 1297 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 1298 * logic, so keep track in software of whether to indicate these timestamps 1299 * or not. 1300 * 1301 * It is permissible to "upgrade" the user request to a broader filter, as long 1302 * as the user receives the timestamps they care about and the user is notified 1303 * the filter has been broadened. 1304 **/ 1305 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 1306 { 1307 struct hwtstamp_config config; 1308 int err; 1309 1310 if (!(pf->flags & I40E_FLAG_PTP)) 1311 return -EOPNOTSUPP; 1312 1313 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1314 return -EFAULT; 1315 1316 err = i40e_ptp_set_timestamp_mode(pf, &config); 1317 if (err) 1318 return err; 1319 1320 /* save these settings for future reference */ 1321 pf->tstamp_config = config; 1322 1323 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1324 -EFAULT : 0; 1325 } 1326 1327 /** 1328 * i40e_init_pin_config - initialize pins. 1329 * @pf: private board structure 1330 * 1331 * Initialize pins for external clock source. 1332 * Return 0 on success or error code on failure. 1333 **/ 1334 static int i40e_init_pin_config(struct i40e_pf *pf) 1335 { 1336 int i; 1337 1338 pf->ptp_caps.n_pins = 3; 1339 pf->ptp_caps.n_ext_ts = 2; 1340 pf->ptp_caps.pps = 1; 1341 pf->ptp_caps.n_per_out = 2; 1342 1343 pf->ptp_caps.pin_config = kcalloc(pf->ptp_caps.n_pins, 1344 sizeof(*pf->ptp_caps.pin_config), 1345 GFP_KERNEL); 1346 if (!pf->ptp_caps.pin_config) 1347 return -ENOMEM; 1348 1349 for (i = 0; i < pf->ptp_caps.n_pins; i++) { 1350 snprintf(pf->ptp_caps.pin_config[i].name, 1351 sizeof(pf->ptp_caps.pin_config[i].name), 1352 "%s", sdp_desc[i].name); 1353 pf->ptp_caps.pin_config[i].index = sdp_desc[i].index; 1354 pf->ptp_caps.pin_config[i].func = PTP_PF_NONE; 1355 pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan; 1356 } 1357 1358 pf->ptp_caps.verify = i40e_ptp_verify; 1359 pf->ptp_caps.enable = i40e_ptp_feature_enable; 1360 1361 pf->ptp_caps.pps = 1; 1362 1363 return 0; 1364 } 1365 1366 /** 1367 * i40e_ptp_create_clock - Create PTP clock device for userspace 1368 * @pf: Board private structure 1369 * 1370 * This function creates a new PTP clock device. It only creates one if we 1371 * don't already have one, so it is safe to call. Will return error if it 1372 * can't create one, but success if we already have a device. Should be used 1373 * by i40e_ptp_init to create clock initially, and prevent global resets from 1374 * creating new clock devices. 1375 **/ 1376 static long i40e_ptp_create_clock(struct i40e_pf *pf) 1377 { 1378 /* no need to create a clock device if we already have one */ 1379 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 1380 return 0; 1381 1382 strscpy(pf->ptp_caps.name, i40e_driver_name, 1383 sizeof(pf->ptp_caps.name) - 1); 1384 pf->ptp_caps.owner = THIS_MODULE; 1385 pf->ptp_caps.max_adj = 999999999; 1386 pf->ptp_caps.adjfine = i40e_ptp_adjfine; 1387 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 1388 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; 1389 pf->ptp_caps.settime64 = i40e_ptp_settime; 1390 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1391 int err = i40e_init_pin_config(pf); 1392 1393 if (err) 1394 return err; 1395 } 1396 1397 /* Attempt to register the clock before enabling the hardware. */ 1398 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 1399 if (IS_ERR(pf->ptp_clock)) 1400 return PTR_ERR(pf->ptp_clock); 1401 1402 /* clear the hwtstamp settings here during clock create, instead of 1403 * during regular init, so that we can maintain settings across a 1404 * reset or suspend. 1405 */ 1406 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1407 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1408 1409 /* Set the previous "reset" time to the current Kernel clock time */ 1410 ktime_get_real_ts64(&pf->ptp_prev_hw_time); 1411 pf->ptp_reset_start = ktime_get(); 1412 1413 return 0; 1414 } 1415 1416 /** 1417 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time 1418 * @pf: Board private structure 1419 * 1420 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should 1421 * be called at the end of preparing to reset, just before hardware reset 1422 * occurs, in order to preserve the PTP time as close as possible across 1423 * resets. 1424 */ 1425 void i40e_ptp_save_hw_time(struct i40e_pf *pf) 1426 { 1427 /* don't try to access the PTP clock if it's not enabled */ 1428 if (!(pf->flags & I40E_FLAG_PTP)) 1429 return; 1430 1431 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); 1432 /* Get a monotonic starting time for this reset */ 1433 pf->ptp_reset_start = ktime_get(); 1434 } 1435 1436 /** 1437 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs 1438 * @pf: Board private structure 1439 * 1440 * Restore the PTP hardware clock registers. We previously cached the PTP 1441 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, 1442 * update this value based on the time delta since the time was saved, using 1443 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. 1444 * 1445 * This ensures that the hardware clock is restored to nearly what it should 1446 * have been if a reset had not occurred. 1447 */ 1448 void i40e_ptp_restore_hw_time(struct i40e_pf *pf) 1449 { 1450 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); 1451 1452 /* Update the previous HW time with the ktime delta */ 1453 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); 1454 1455 /* Restore the hardware clock registers */ 1456 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); 1457 } 1458 1459 /** 1460 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 1461 * @pf: Board private structure 1462 * 1463 * This function sets device up for 1588 support. The first time it is run, it 1464 * will create a PHC clock device. It does not create a clock device if one 1465 * already exists. It also reconfigures the device after a reset. 1466 * 1467 * The first time a clock is created, i40e_ptp_create_clock will set 1468 * pf->ptp_prev_hw_time to the current system time. During resets, it is 1469 * expected that this timespec will be set to the last known PTP clock time, 1470 * in order to preserve the clock time as close as possible across a reset. 1471 **/ 1472 void i40e_ptp_init(struct i40e_pf *pf) 1473 { 1474 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 1475 struct i40e_hw *hw = &pf->hw; 1476 u32 pf_id; 1477 long err; 1478 1479 /* Only one PF is assigned to control 1588 logic per port. Do not 1480 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 1481 */ 1482 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 1483 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 1484 if (hw->pf_id != pf_id) { 1485 pf->flags &= ~I40E_FLAG_PTP; 1486 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 1487 __func__, 1488 netdev->name); 1489 return; 1490 } 1491 1492 mutex_init(&pf->tmreg_lock); 1493 spin_lock_init(&pf->ptp_rx_lock); 1494 1495 /* ensure we have a clock device */ 1496 err = i40e_ptp_create_clock(pf); 1497 if (err) { 1498 pf->ptp_clock = NULL; 1499 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 1500 __func__); 1501 } else if (pf->ptp_clock) { 1502 u32 regval; 1503 1504 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 1505 dev_info(&pf->pdev->dev, "PHC enabled\n"); 1506 pf->flags |= I40E_FLAG_PTP; 1507 1508 /* Ensure the clocks are running. */ 1509 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1510 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 1511 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1512 regval = rd32(hw, I40E_PRTTSYN_CTL1); 1513 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 1514 wr32(hw, I40E_PRTTSYN_CTL1, regval); 1515 1516 /* Set the increment value per clock tick. */ 1517 i40e_ptp_set_increment(pf); 1518 1519 /* reset timestamping mode */ 1520 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 1521 1522 /* Restore the clock time based on last known value */ 1523 i40e_ptp_restore_hw_time(pf); 1524 } 1525 1526 i40e_ptp_set_1pps_signal_hw(pf); 1527 } 1528 1529 /** 1530 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 1531 * @pf: Board private structure 1532 * 1533 * This function handles the cleanup work required from the initialization by 1534 * clearing out the important information and unregistering the PHC. 1535 **/ 1536 void i40e_ptp_stop(struct i40e_pf *pf) 1537 { 1538 struct i40e_hw *hw = &pf->hw; 1539 u32 regval; 1540 1541 pf->flags &= ~I40E_FLAG_PTP; 1542 pf->ptp_tx = false; 1543 pf->ptp_rx = false; 1544 1545 if (pf->ptp_tx_skb) { 1546 struct sk_buff *skb = pf->ptp_tx_skb; 1547 1548 pf->ptp_tx_skb = NULL; 1549 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 1550 dev_kfree_skb_any(skb); 1551 } 1552 1553 if (pf->ptp_clock) { 1554 ptp_clock_unregister(pf->ptp_clock); 1555 pf->ptp_clock = NULL; 1556 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 1557 pf->vsi[pf->lan_vsi]->netdev->name); 1558 } 1559 1560 if (i40e_is_ptp_pin_dev(&pf->hw)) { 1561 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off); 1562 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off); 1563 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off); 1564 } 1565 1566 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0)); 1567 regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK; 1568 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval); 1569 1570 /* Disable interrupts */ 1571 regval = rd32(hw, I40E_PRTTSYN_CTL0); 1572 regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK; 1573 wr32(hw, I40E_PRTTSYN_CTL0, regval); 1574 1575 i40e_ptp_free_pins(pf); 1576 } 1577