1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include <linux/ptp_classify.h> 6 7 /* The XL710 timesync is very much like Intel's 82599 design when it comes to 8 * the fundamental clock design. However, the clock operations are much simpler 9 * in the XL710 because the device supports a full 64 bits of nanoseconds. 10 * Because the field is so wide, we can forgo the cycle counter and just 11 * operate with the nanosecond field directly without fear of overflow. 12 * 13 * Much like the 82599, the update period is dependent upon the link speed: 14 * At 40Gb link or no link, the period is 1.6ns. 15 * At 10Gb link, the period is multiplied by 2. (3.2ns) 16 * At 1Gb link, the period is multiplied by 20. (32ns) 17 * 1588 functionality is not supported at 100Mbps. 18 */ 19 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL 20 #define I40E_PTP_10GB_INCVAL_MULT 2 21 #define I40E_PTP_1GB_INCVAL_MULT 20 22 23 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 24 #define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \ 25 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 26 27 /** 28 * i40e_ptp_read - Read the PHC time from the device 29 * @pf: Board private structure 30 * @ts: timespec structure to hold the current time value 31 * @sts: structure to hold the system time before and after reading the PHC 32 * 33 * This function reads the PRTTSYN_TIME registers and stores them in a 34 * timespec. However, since the registers are 64 bits of nanoseconds, we must 35 * convert the result to a timespec before we can return. 36 **/ 37 static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts, 38 struct ptp_system_timestamp *sts) 39 { 40 struct i40e_hw *hw = &pf->hw; 41 u32 hi, lo; 42 u64 ns; 43 44 /* The timer latches on the lowest register read. */ 45 ptp_read_system_prets(sts); 46 lo = rd32(hw, I40E_PRTTSYN_TIME_L); 47 ptp_read_system_postts(sts); 48 hi = rd32(hw, I40E_PRTTSYN_TIME_H); 49 50 ns = (((u64)hi) << 32) | lo; 51 52 *ts = ns_to_timespec64(ns); 53 } 54 55 /** 56 * i40e_ptp_write - Write the PHC time to the device 57 * @pf: Board private structure 58 * @ts: timespec structure that holds the new time value 59 * 60 * This function writes the PRTTSYN_TIME registers with the user value. Since 61 * we receive a timespec from the stack, we must convert that timespec into 62 * nanoseconds before programming the registers. 63 **/ 64 static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) 65 { 66 struct i40e_hw *hw = &pf->hw; 67 u64 ns = timespec64_to_ns(ts); 68 69 /* The timer will not update until the high register is written, so 70 * write the low register first. 71 */ 72 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF); 73 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32); 74 } 75 76 /** 77 * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time 78 * @hwtstamps: Timestamp structure to update 79 * @timestamp: Timestamp from the hardware 80 * 81 * We need to convert the NIC clock value into a hwtstamp which can be used by 82 * the upper level timestamping functions. Since the timestamp is simply a 64- 83 * bit nanosecond value, we can call ns_to_ktime directly to handle this. 84 **/ 85 static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps, 86 u64 timestamp) 87 { 88 memset(hwtstamps, 0, sizeof(*hwtstamps)); 89 90 hwtstamps->hwtstamp = ns_to_ktime(timestamp); 91 } 92 93 /** 94 * i40e_ptp_adjfreq - Adjust the PHC frequency 95 * @ptp: The PTP clock structure 96 * @ppb: Parts per billion adjustment from the base 97 * 98 * Adjust the frequency of the PHC by the indicated parts per billion from the 99 * base frequency. 100 **/ 101 static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 102 { 103 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 104 struct i40e_hw *hw = &pf->hw; 105 u64 adj, freq, diff; 106 int neg_adj = 0; 107 108 if (ppb < 0) { 109 neg_adj = 1; 110 ppb = -ppb; 111 } 112 113 freq = I40E_PTP_40GB_INCVAL; 114 freq *= ppb; 115 diff = div_u64(freq, 1000000000ULL); 116 117 if (neg_adj) 118 adj = I40E_PTP_40GB_INCVAL - diff; 119 else 120 adj = I40E_PTP_40GB_INCVAL + diff; 121 122 /* At some link speeds, the base incval is so large that directly 123 * multiplying by ppb would result in arithmetic overflow even when 124 * using a u64. Avoid this by instead calculating the new incval 125 * always in terms of the 40GbE clock rate and then multiplying by the 126 * link speed factor afterwards. This does result in slightly lower 127 * precision at lower link speeds, but it is fairly minor. 128 */ 129 smp_mb(); /* Force any pending update before accessing. */ 130 adj *= READ_ONCE(pf->ptp_adj_mult); 131 132 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF); 133 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32); 134 135 return 0; 136 } 137 138 /** 139 * i40e_ptp_adjtime - Adjust the PHC time 140 * @ptp: The PTP clock structure 141 * @delta: Offset in nanoseconds to adjust the PHC time by 142 * 143 * Adjust the current clock time by a delta specified in nanoseconds. 144 **/ 145 static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 146 { 147 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 148 struct timespec64 now, then; 149 150 then = ns_to_timespec64(delta); 151 mutex_lock(&pf->tmreg_lock); 152 153 i40e_ptp_read(pf, &now, NULL); 154 now = timespec64_add(now, then); 155 i40e_ptp_write(pf, (const struct timespec64 *)&now); 156 157 mutex_unlock(&pf->tmreg_lock); 158 159 return 0; 160 } 161 162 /** 163 * i40e_ptp_gettimex - Get the time of the PHC 164 * @ptp: The PTP clock structure 165 * @ts: timespec structure to hold the current time value 166 * @sts: structure to hold the system time before and after reading the PHC 167 * 168 * Read the device clock and return the correct value on ns, after converting it 169 * into a timespec struct. 170 **/ 171 static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, 172 struct ptp_system_timestamp *sts) 173 { 174 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 175 176 mutex_lock(&pf->tmreg_lock); 177 i40e_ptp_read(pf, ts, sts); 178 mutex_unlock(&pf->tmreg_lock); 179 180 return 0; 181 } 182 183 /** 184 * i40e_ptp_settime - Set the time of the PHC 185 * @ptp: The PTP clock structure 186 * @ts: timespec structure that holds the new time value 187 * 188 * Set the device clock to the user input value. The conversion from timespec 189 * to ns happens in the write function. 190 **/ 191 static int i40e_ptp_settime(struct ptp_clock_info *ptp, 192 const struct timespec64 *ts) 193 { 194 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); 195 196 mutex_lock(&pf->tmreg_lock); 197 i40e_ptp_write(pf, ts); 198 mutex_unlock(&pf->tmreg_lock); 199 200 return 0; 201 } 202 203 /** 204 * i40e_ptp_feature_enable - Enable/disable ancillary features of the PHC subsystem 205 * @ptp: The PTP clock structure 206 * @rq: The requested feature to change 207 * @on: Enable/disable flag 208 * 209 * The XL710 does not support any of the ancillary features of the PHC 210 * subsystem, so this function may just return. 211 **/ 212 static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp, 213 struct ptp_clock_request *rq, int on) 214 { 215 return -EOPNOTSUPP; 216 } 217 218 /** 219 * i40e_ptp_update_latch_events - Read I40E_PRTTSYN_STAT_1 and latch events 220 * @pf: the PF data structure 221 * 222 * This function reads I40E_PRTTSYN_STAT_1 and updates the corresponding timers 223 * for noticed latch events. This allows the driver to keep track of the first 224 * time a latch event was noticed which will be used to help clear out Rx 225 * timestamps for packets that got dropped or lost. 226 * 227 * This function will return the current value of I40E_PRTTSYN_STAT_1 and is 228 * expected to be called only while under the ptp_rx_lock. 229 **/ 230 static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf) 231 { 232 struct i40e_hw *hw = &pf->hw; 233 u32 prttsyn_stat, new_latch_events; 234 int i; 235 236 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); 237 new_latch_events = prttsyn_stat & ~pf->latch_event_flags; 238 239 /* Update the jiffies time for any newly latched timestamp. This 240 * ensures that we store the time that we first discovered a timestamp 241 * was latched by the hardware. The service task will later determine 242 * if we should free the latch and drop that timestamp should too much 243 * time pass. This flow ensures that we only update jiffies for new 244 * events latched since the last time we checked, and not all events 245 * currently latched, so that the service task accounting remains 246 * accurate. 247 */ 248 for (i = 0; i < 4; i++) { 249 if (new_latch_events & BIT(i)) 250 pf->latch_events[i] = jiffies; 251 } 252 253 /* Finally, we store the current status of the Rx timestamp latches */ 254 pf->latch_event_flags = prttsyn_stat; 255 256 return prttsyn_stat; 257 } 258 259 /** 260 * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung 261 * @pf: The PF private data structure 262 * 263 * This watchdog task is scheduled to detect error case where hardware has 264 * dropped an Rx packet that was timestamped when the ring is full. The 265 * particular error is rare but leaves the device in a state unable to timestamp 266 * any future packets. 267 **/ 268 void i40e_ptp_rx_hang(struct i40e_pf *pf) 269 { 270 struct i40e_hw *hw = &pf->hw; 271 unsigned int i, cleared = 0; 272 273 /* Since we cannot turn off the Rx timestamp logic if the device is 274 * configured for Tx timestamping, we check if Rx timestamping is 275 * configured. We don't want to spuriously warn about Rx timestamp 276 * hangs if we don't care about the timestamps. 277 */ 278 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 279 return; 280 281 spin_lock_bh(&pf->ptp_rx_lock); 282 283 /* Update current latch times for Rx events */ 284 i40e_ptp_get_rx_events(pf); 285 286 /* Check all the currently latched Rx events and see whether they have 287 * been latched for over a second. It is assumed that any timestamp 288 * should have been cleared within this time, or else it was captured 289 * for a dropped frame that the driver never received. Thus, we will 290 * clear any timestamp that has been latched for over 1 second. 291 */ 292 for (i = 0; i < 4; i++) { 293 if ((pf->latch_event_flags & BIT(i)) && 294 time_is_before_jiffies(pf->latch_events[i] + HZ)) { 295 rd32(hw, I40E_PRTTSYN_RXTIME_H(i)); 296 pf->latch_event_flags &= ~BIT(i); 297 cleared++; 298 } 299 } 300 301 spin_unlock_bh(&pf->ptp_rx_lock); 302 303 /* Log a warning if more than 2 timestamps got dropped in the same 304 * check. We don't want to warn about all drops because it can occur 305 * in normal scenarios such as PTP frames on multicast addresses we 306 * aren't listening to. However, administrator should know if this is 307 * the reason packets aren't receiving timestamps. 308 */ 309 if (cleared > 2) 310 dev_dbg(&pf->pdev->dev, 311 "Dropped %d missed RXTIME timestamp events\n", 312 cleared); 313 314 /* Finally, update the rx_hwtstamp_cleared counter */ 315 pf->rx_hwtstamp_cleared += cleared; 316 } 317 318 /** 319 * i40e_ptp_tx_hang - Detect error case when Tx timestamp register is hung 320 * @pf: The PF private data structure 321 * 322 * This watchdog task is run periodically to make sure that we clear the Tx 323 * timestamp logic if we don't obtain a timestamp in a reasonable amount of 324 * time. It is unexpected in the normal case but if it occurs it results in 325 * permanently preventing timestamps of future packets. 326 **/ 327 void i40e_ptp_tx_hang(struct i40e_pf *pf) 328 { 329 struct sk_buff *skb; 330 331 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 332 return; 333 334 /* Nothing to do if we're not already waiting for a timestamp */ 335 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state)) 336 return; 337 338 /* We already have a handler routine which is run when we are notified 339 * of a Tx timestamp in the hardware. If we don't get an interrupt 340 * within a second it is reasonable to assume that we never will. 341 */ 342 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) { 343 skb = pf->ptp_tx_skb; 344 pf->ptp_tx_skb = NULL; 345 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 346 347 /* Free the skb after we clear the bitlock */ 348 dev_kfree_skb_any(skb); 349 pf->tx_hwtstamp_timeouts++; 350 } 351 } 352 353 /** 354 * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp 355 * @pf: Board private structure 356 * 357 * Read the value of the Tx timestamp from the registers, convert it into a 358 * value consumable by the stack, and store that result into the shhwtstamps 359 * struct before returning it up the stack. 360 **/ 361 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf) 362 { 363 struct skb_shared_hwtstamps shhwtstamps; 364 struct sk_buff *skb = pf->ptp_tx_skb; 365 struct i40e_hw *hw = &pf->hw; 366 u32 hi, lo; 367 u64 ns; 368 369 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx) 370 return; 371 372 /* don't attempt to timestamp if we don't have an skb */ 373 if (!pf->ptp_tx_skb) 374 return; 375 376 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); 377 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); 378 379 ns = (((u64)hi) << 32) | lo; 380 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns); 381 382 /* Clear the bit lock as soon as possible after reading the register, 383 * and prior to notifying the stack via skb_tstamp_tx(). Otherwise 384 * applications might wake up and attempt to request another transmit 385 * timestamp prior to the bit lock being cleared. 386 */ 387 pf->ptp_tx_skb = NULL; 388 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 389 390 /* Notify the stack and free the skb after we've unlocked */ 391 skb_tstamp_tx(skb, &shhwtstamps); 392 dev_kfree_skb_any(skb); 393 } 394 395 /** 396 * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp 397 * @pf: Board private structure 398 * @skb: Particular skb to send timestamp with 399 * @index: Index into the receive timestamp registers for the timestamp 400 * 401 * The XL710 receives a notification in the receive descriptor with an offset 402 * into the set of RXTIME registers where the timestamp is for that skb. This 403 * function goes and fetches the receive timestamp from that offset, if a valid 404 * one exists. The RXTIME registers are in ns, so we must convert the result 405 * first. 406 **/ 407 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index) 408 { 409 u32 prttsyn_stat, hi, lo; 410 struct i40e_hw *hw; 411 u64 ns; 412 413 /* Since we cannot turn off the Rx timestamp logic if the device is 414 * doing Tx timestamping, check if Rx timestamping is configured. 415 */ 416 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx) 417 return; 418 419 hw = &pf->hw; 420 421 spin_lock_bh(&pf->ptp_rx_lock); 422 423 /* Get current Rx events and update latch times */ 424 prttsyn_stat = i40e_ptp_get_rx_events(pf); 425 426 /* TODO: Should we warn about missing Rx timestamp event? */ 427 if (!(prttsyn_stat & BIT(index))) { 428 spin_unlock_bh(&pf->ptp_rx_lock); 429 return; 430 } 431 432 /* Clear the latched event since we're about to read its register */ 433 pf->latch_event_flags &= ~BIT(index); 434 435 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index)); 436 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index)); 437 438 spin_unlock_bh(&pf->ptp_rx_lock); 439 440 ns = (((u64)hi) << 32) | lo; 441 442 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns); 443 } 444 445 /** 446 * i40e_ptp_set_increment - Utility function to update clock increment rate 447 * @pf: Board private structure 448 * 449 * During a link change, the DMA frequency that drives the 1588 logic will 450 * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds, 451 * we must update the increment value per clock tick. 452 **/ 453 void i40e_ptp_set_increment(struct i40e_pf *pf) 454 { 455 struct i40e_link_status *hw_link_info; 456 struct i40e_hw *hw = &pf->hw; 457 u64 incval; 458 u32 mult; 459 460 hw_link_info = &hw->phy.link_info; 461 462 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL); 463 464 switch (hw_link_info->link_speed) { 465 case I40E_LINK_SPEED_10GB: 466 mult = I40E_PTP_10GB_INCVAL_MULT; 467 break; 468 case I40E_LINK_SPEED_1GB: 469 mult = I40E_PTP_1GB_INCVAL_MULT; 470 break; 471 case I40E_LINK_SPEED_100MB: 472 { 473 static int warn_once; 474 475 if (!warn_once) { 476 dev_warn(&pf->pdev->dev, 477 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n"); 478 warn_once++; 479 } 480 mult = 0; 481 break; 482 } 483 case I40E_LINK_SPEED_40GB: 484 default: 485 mult = 1; 486 break; 487 } 488 489 /* The increment value is calculated by taking the base 40GbE incvalue 490 * and multiplying it by a factor based on the link speed. 491 */ 492 incval = I40E_PTP_40GB_INCVAL * mult; 493 494 /* Write the new increment value into the increment register. The 495 * hardware will not update the clock until both registers have been 496 * written. 497 */ 498 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF); 499 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32); 500 501 /* Update the base adjustement value. */ 502 WRITE_ONCE(pf->ptp_adj_mult, mult); 503 smp_mb(); /* Force the above update. */ 504 } 505 506 /** 507 * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping 508 * @pf: Board private structure 509 * @ifr: ioctl data 510 * 511 * Obtain the current hardware timestamping settigs as requested. To do this, 512 * keep a shadow copy of the timestamp settings rather than attempting to 513 * deconstruct it from the registers. 514 **/ 515 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 516 { 517 struct hwtstamp_config *config = &pf->tstamp_config; 518 519 if (!(pf->flags & I40E_FLAG_PTP)) 520 return -EOPNOTSUPP; 521 522 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 523 -EFAULT : 0; 524 } 525 526 /** 527 * i40e_ptp_set_timestamp_mode - setup hardware for requested timestamp mode 528 * @pf: Board private structure 529 * @config: hwtstamp settings requested or saved 530 * 531 * Control hardware registers to enter the specific mode requested by the 532 * user. Also used during reset path to ensure that timestamp settings are 533 * maintained. 534 * 535 * Note: modifies config in place, and may update the requested mode to be 536 * more broad if the specific filter is not directly supported. 537 **/ 538 static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf, 539 struct hwtstamp_config *config) 540 { 541 struct i40e_hw *hw = &pf->hw; 542 u32 tsyntype, regval; 543 544 /* Reserved for future extensions. */ 545 if (config->flags) 546 return -EINVAL; 547 548 switch (config->tx_type) { 549 case HWTSTAMP_TX_OFF: 550 pf->ptp_tx = false; 551 break; 552 case HWTSTAMP_TX_ON: 553 pf->ptp_tx = true; 554 break; 555 default: 556 return -ERANGE; 557 } 558 559 switch (config->rx_filter) { 560 case HWTSTAMP_FILTER_NONE: 561 pf->ptp_rx = false; 562 /* We set the type to V1, but do not enable UDP packet 563 * recognition. In this way, we should be as close to 564 * disabling PTP Rx timestamps as possible since V1 packets 565 * are always UDP, since L2 packets are a V2 feature. 566 */ 567 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1; 568 break; 569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 570 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 571 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 572 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 573 return -ERANGE; 574 pf->ptp_rx = true; 575 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK | 576 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 | 577 I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 578 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 579 break; 580 case HWTSTAMP_FILTER_PTP_V2_EVENT: 581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 582 case HWTSTAMP_FILTER_PTP_V2_SYNC: 583 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 584 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 585 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 586 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE)) 587 return -ERANGE; 588 fallthrough; 589 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 590 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 591 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 592 pf->ptp_rx = true; 593 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK | 594 I40E_PRTTSYN_CTL1_TSYNTYPE_V2; 595 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) { 596 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK; 597 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 598 } else { 599 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 600 } 601 break; 602 case HWTSTAMP_FILTER_NTP_ALL: 603 case HWTSTAMP_FILTER_ALL: 604 default: 605 return -ERANGE; 606 } 607 608 /* Clear out all 1588-related registers to clear and unlatch them. */ 609 spin_lock_bh(&pf->ptp_rx_lock); 610 rd32(hw, I40E_PRTTSYN_STAT_0); 611 rd32(hw, I40E_PRTTSYN_TXTIME_H); 612 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); 613 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); 614 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); 615 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); 616 pf->latch_event_flags = 0; 617 spin_unlock_bh(&pf->ptp_rx_lock); 618 619 /* Enable/disable the Tx timestamp interrupt based on user input. */ 620 regval = rd32(hw, I40E_PRTTSYN_CTL0); 621 if (pf->ptp_tx) 622 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 623 else 624 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; 625 wr32(hw, I40E_PRTTSYN_CTL0, regval); 626 627 regval = rd32(hw, I40E_PFINT_ICR0_ENA); 628 if (pf->ptp_tx) 629 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 630 else 631 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 632 wr32(hw, I40E_PFINT_ICR0_ENA, regval); 633 634 /* Although there is no simple on/off switch for Rx, we "disable" Rx 635 * timestamps by setting to V1 only mode and clear the UDP 636 * recognition. This ought to disable all PTP Rx timestamps as V1 637 * packets are always over UDP. Note that software is configured to 638 * ignore Rx timestamps via the pf->ptp_rx flag. 639 */ 640 regval = rd32(hw, I40E_PRTTSYN_CTL1); 641 /* clear everything but the enable bit */ 642 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 643 /* now enable bits for desired Rx timestamps */ 644 regval |= tsyntype; 645 wr32(hw, I40E_PRTTSYN_CTL1, regval); 646 647 return 0; 648 } 649 650 /** 651 * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping 652 * @pf: Board private structure 653 * @ifr: ioctl data 654 * 655 * Respond to the user filter requests and make the appropriate hardware 656 * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping 657 * logic, so keep track in software of whether to indicate these timestamps 658 * or not. 659 * 660 * It is permissible to "upgrade" the user request to a broader filter, as long 661 * as the user receives the timestamps they care about and the user is notified 662 * the filter has been broadened. 663 **/ 664 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr) 665 { 666 struct hwtstamp_config config; 667 int err; 668 669 if (!(pf->flags & I40E_FLAG_PTP)) 670 return -EOPNOTSUPP; 671 672 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 673 return -EFAULT; 674 675 err = i40e_ptp_set_timestamp_mode(pf, &config); 676 if (err) 677 return err; 678 679 /* save these settings for future reference */ 680 pf->tstamp_config = config; 681 682 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 683 -EFAULT : 0; 684 } 685 686 /** 687 * i40e_ptp_create_clock - Create PTP clock device for userspace 688 * @pf: Board private structure 689 * 690 * This function creates a new PTP clock device. It only creates one if we 691 * don't already have one, so it is safe to call. Will return error if it 692 * can't create one, but success if we already have a device. Should be used 693 * by i40e_ptp_init to create clock initially, and prevent global resets from 694 * creating new clock devices. 695 **/ 696 static long i40e_ptp_create_clock(struct i40e_pf *pf) 697 { 698 /* no need to create a clock device if we already have one */ 699 if (!IS_ERR_OR_NULL(pf->ptp_clock)) 700 return 0; 701 702 strlcpy(pf->ptp_caps.name, i40e_driver_name, 703 sizeof(pf->ptp_caps.name) - 1); 704 pf->ptp_caps.owner = THIS_MODULE; 705 pf->ptp_caps.max_adj = 999999999; 706 pf->ptp_caps.n_ext_ts = 0; 707 pf->ptp_caps.pps = 0; 708 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; 709 pf->ptp_caps.adjtime = i40e_ptp_adjtime; 710 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex; 711 pf->ptp_caps.settime64 = i40e_ptp_settime; 712 pf->ptp_caps.enable = i40e_ptp_feature_enable; 713 714 /* Attempt to register the clock before enabling the hardware. */ 715 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev); 716 if (IS_ERR(pf->ptp_clock)) 717 return PTR_ERR(pf->ptp_clock); 718 719 /* clear the hwtstamp settings here during clock create, instead of 720 * during regular init, so that we can maintain settings across a 721 * reset or suspend. 722 */ 723 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 724 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 725 726 /* Set the previous "reset" time to the current Kernel clock time */ 727 ktime_get_real_ts64(&pf->ptp_prev_hw_time); 728 pf->ptp_reset_start = ktime_get(); 729 730 return 0; 731 } 732 733 /** 734 * i40e_ptp_save_hw_time - Save the current PTP time as ptp_prev_hw_time 735 * @pf: Board private structure 736 * 737 * Read the current PTP time and save it into pf->ptp_prev_hw_time. This should 738 * be called at the end of preparing to reset, just before hardware reset 739 * occurs, in order to preserve the PTP time as close as possible across 740 * resets. 741 */ 742 void i40e_ptp_save_hw_time(struct i40e_pf *pf) 743 { 744 /* don't try to access the PTP clock if it's not enabled */ 745 if (!(pf->flags & I40E_FLAG_PTP)) 746 return; 747 748 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL); 749 /* Get a monotonic starting time for this reset */ 750 pf->ptp_reset_start = ktime_get(); 751 } 752 753 /** 754 * i40e_ptp_restore_hw_time - Restore the ptp_prev_hw_time + delta to PTP regs 755 * @pf: Board private structure 756 * 757 * Restore the PTP hardware clock registers. We previously cached the PTP 758 * hardware time as pf->ptp_prev_hw_time. To be as accurate as possible, 759 * update this value based on the time delta since the time was saved, using 760 * CLOCK_MONOTONIC (via ktime_get()) to calculate the time difference. 761 * 762 * This ensures that the hardware clock is restored to nearly what it should 763 * have been if a reset had not occurred. 764 */ 765 void i40e_ptp_restore_hw_time(struct i40e_pf *pf) 766 { 767 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start); 768 769 /* Update the previous HW time with the ktime delta */ 770 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta)); 771 772 /* Restore the hardware clock registers */ 773 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time); 774 } 775 776 /** 777 * i40e_ptp_init - Initialize the 1588 support after device probe or reset 778 * @pf: Board private structure 779 * 780 * This function sets device up for 1588 support. The first time it is run, it 781 * will create a PHC clock device. It does not create a clock device if one 782 * already exists. It also reconfigures the device after a reset. 783 * 784 * The first time a clock is created, i40e_ptp_create_clock will set 785 * pf->ptp_prev_hw_time to the current system time. During resets, it is 786 * expected that this timespec will be set to the last known PTP clock time, 787 * in order to preserve the clock time as close as possible across a reset. 788 **/ 789 void i40e_ptp_init(struct i40e_pf *pf) 790 { 791 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev; 792 struct i40e_hw *hw = &pf->hw; 793 u32 pf_id; 794 long err; 795 796 /* Only one PF is assigned to control 1588 logic per port. Do not 797 * enable any support for PFs not assigned via PRTTSYN_CTL0.PF_ID 798 */ 799 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >> 800 I40E_PRTTSYN_CTL0_PF_ID_SHIFT; 801 if (hw->pf_id != pf_id) { 802 pf->flags &= ~I40E_FLAG_PTP; 803 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n", 804 __func__, 805 netdev->name); 806 return; 807 } 808 809 mutex_init(&pf->tmreg_lock); 810 spin_lock_init(&pf->ptp_rx_lock); 811 812 /* ensure we have a clock device */ 813 err = i40e_ptp_create_clock(pf); 814 if (err) { 815 pf->ptp_clock = NULL; 816 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", 817 __func__); 818 } else if (pf->ptp_clock) { 819 u32 regval; 820 821 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 822 dev_info(&pf->pdev->dev, "PHC enabled\n"); 823 pf->flags |= I40E_FLAG_PTP; 824 825 /* Ensure the clocks are running. */ 826 regval = rd32(hw, I40E_PRTTSYN_CTL0); 827 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; 828 wr32(hw, I40E_PRTTSYN_CTL0, regval); 829 regval = rd32(hw, I40E_PRTTSYN_CTL1); 830 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; 831 wr32(hw, I40E_PRTTSYN_CTL1, regval); 832 833 /* Set the increment value per clock tick. */ 834 i40e_ptp_set_increment(pf); 835 836 /* reset timestamping mode */ 837 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); 838 839 /* Restore the clock time based on last known value */ 840 i40e_ptp_restore_hw_time(pf); 841 } 842 } 843 844 /** 845 * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC 846 * @pf: Board private structure 847 * 848 * This function handles the cleanup work required from the initialization by 849 * clearing out the important information and unregistering the PHC. 850 **/ 851 void i40e_ptp_stop(struct i40e_pf *pf) 852 { 853 pf->flags &= ~I40E_FLAG_PTP; 854 pf->ptp_tx = false; 855 pf->ptp_rx = false; 856 857 if (pf->ptp_tx_skb) { 858 struct sk_buff *skb = pf->ptp_tx_skb; 859 860 pf->ptp_tx_skb = NULL; 861 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state); 862 dev_kfree_skb_any(skb); 863 } 864 865 if (pf->ptp_clock) { 866 ptp_clock_unregister(pf->ptp_clock); 867 pf->ptp_clock = NULL; 868 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__, 869 pf->vsi[pf->lan_vsi]->netdev->name); 870 } 871 } 872