1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e_prototype.h" 5 6 /** 7 * i40e_init_nvm_ops - Initialize NVM function pointers 8 * @hw: pointer to the HW structure 9 * 10 * Setup the function pointers and the NVM info structure. Should be called 11 * once per NVM initialization, e.g. inside the i40e_init_shared_code(). 12 * Please notice that the NVM term is used here (& in all methods covered 13 * in this file) as an equivalent of the FLASH part mapped into the SR. 14 * We are accessing FLASH always thru the Shadow RAM. 15 **/ 16 i40e_status i40e_init_nvm(struct i40e_hw *hw) 17 { 18 struct i40e_nvm_info *nvm = &hw->nvm; 19 i40e_status ret_code = 0; 20 u32 fla, gens; 21 u8 sr_size; 22 23 /* The SR size is stored regardless of the nvm programming mode 24 * as the blank mode may be used in the factory line. 25 */ 26 gens = rd32(hw, I40E_GLNVM_GENS); 27 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 28 I40E_GLNVM_GENS_SR_SIZE_SHIFT); 29 /* Switching to words (sr_size contains power of 2KB) */ 30 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 31 32 /* Check if we are in the normal or blank NVM programming mode */ 33 fla = rd32(hw, I40E_GLNVM_FLA); 34 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */ 35 /* Max NVM timeout */ 36 nvm->timeout = I40E_MAX_NVM_TIMEOUT; 37 nvm->blank_nvm_mode = false; 38 } else { /* Blank programming mode */ 39 nvm->blank_nvm_mode = true; 40 ret_code = I40E_ERR_NVM_BLANK_MODE; 41 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); 42 } 43 44 return ret_code; 45 } 46 47 /** 48 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership 49 * @hw: pointer to the HW structure 50 * @access: NVM access type (read or write) 51 * 52 * This function will request NVM ownership for reading 53 * via the proper Admin Command. 54 **/ 55 i40e_status i40e_acquire_nvm(struct i40e_hw *hw, 56 enum i40e_aq_resource_access_type access) 57 { 58 i40e_status ret_code = 0; 59 u64 gtime, timeout; 60 u64 time_left = 0; 61 62 if (hw->nvm.blank_nvm_mode) 63 goto i40e_i40e_acquire_nvm_exit; 64 65 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, 66 0, &time_left, NULL); 67 /* Reading the Global Device Timer */ 68 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 69 70 /* Store the timeout */ 71 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; 72 73 if (ret_code) 74 i40e_debug(hw, I40E_DEBUG_NVM, 75 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n", 76 access, time_left, ret_code, hw->aq.asq_last_status); 77 78 if (ret_code && time_left) { 79 /* Poll until the current NVM owner timeouts */ 80 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime; 81 while ((gtime < timeout) && time_left) { 82 usleep_range(10000, 20000); 83 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 84 ret_code = i40e_aq_request_resource(hw, 85 I40E_NVM_RESOURCE_ID, 86 access, 0, &time_left, 87 NULL); 88 if (!ret_code) { 89 hw->nvm.hw_semaphore_timeout = 90 I40E_MS_TO_GTIME(time_left) + gtime; 91 break; 92 } 93 } 94 if (ret_code) { 95 hw->nvm.hw_semaphore_timeout = 0; 96 i40e_debug(hw, I40E_DEBUG_NVM, 97 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n", 98 time_left, ret_code, hw->aq.asq_last_status); 99 } 100 } 101 102 i40e_i40e_acquire_nvm_exit: 103 return ret_code; 104 } 105 106 /** 107 * i40e_release_nvm - Generic request for releasing the NVM ownership 108 * @hw: pointer to the HW structure 109 * 110 * This function will release NVM resource via the proper Admin Command. 111 **/ 112 void i40e_release_nvm(struct i40e_hw *hw) 113 { 114 i40e_status ret_code = I40E_SUCCESS; 115 u32 total_delay = 0; 116 117 if (hw->nvm.blank_nvm_mode) 118 return; 119 120 ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 121 122 /* there are some rare cases when trying to release the resource 123 * results in an admin Q timeout, so handle them correctly 124 */ 125 while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) && 126 (total_delay < hw->aq.asq_cmd_timeout)) { 127 usleep_range(1000, 2000); 128 ret_code = i40e_aq_release_resource(hw, 129 I40E_NVM_RESOURCE_ID, 130 0, NULL); 131 total_delay++; 132 } 133 } 134 135 /** 136 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit 137 * @hw: pointer to the HW structure 138 * 139 * Polls the SRCTL Shadow RAM register done bit. 140 **/ 141 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) 142 { 143 i40e_status ret_code = I40E_ERR_TIMEOUT; 144 u32 srctl, wait_cnt; 145 146 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */ 147 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { 148 srctl = rd32(hw, I40E_GLNVM_SRCTL); 149 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { 150 ret_code = 0; 151 break; 152 } 153 udelay(5); 154 } 155 if (ret_code == I40E_ERR_TIMEOUT) 156 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); 157 return ret_code; 158 } 159 160 /** 161 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register 162 * @hw: pointer to the HW structure 163 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 164 * @data: word read from the Shadow RAM 165 * 166 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 167 **/ 168 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, 169 u16 *data) 170 { 171 i40e_status ret_code = I40E_ERR_TIMEOUT; 172 u32 sr_reg; 173 174 if (offset >= hw->nvm.sr_size) { 175 i40e_debug(hw, I40E_DEBUG_NVM, 176 "NVM read error: offset %d beyond Shadow RAM limit %d\n", 177 offset, hw->nvm.sr_size); 178 ret_code = I40E_ERR_PARAM; 179 goto read_nvm_exit; 180 } 181 182 /* Poll the done bit first */ 183 ret_code = i40e_poll_sr_srctl_done_bit(hw); 184 if (!ret_code) { 185 /* Write the address and start reading */ 186 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 187 BIT(I40E_GLNVM_SRCTL_START_SHIFT); 188 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); 189 190 /* Poll I40E_GLNVM_SRCTL until the done bit is set */ 191 ret_code = i40e_poll_sr_srctl_done_bit(hw); 192 if (!ret_code) { 193 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 194 *data = (u16)((sr_reg & 195 I40E_GLNVM_SRDATA_RDDATA_MASK) 196 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 197 } 198 } 199 if (ret_code) 200 i40e_debug(hw, I40E_DEBUG_NVM, 201 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", 202 offset); 203 204 read_nvm_exit: 205 return ret_code; 206 } 207 208 /** 209 * i40e_read_nvm_aq - Read Shadow RAM. 210 * @hw: pointer to the HW structure. 211 * @module_pointer: module pointer location in words from the NVM beginning 212 * @offset: offset in words from module start 213 * @words: number of words to write 214 * @data: buffer with words to write to the Shadow RAM 215 * @last_command: tells the AdminQ that this is the last command 216 * 217 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 218 **/ 219 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, 220 u8 module_pointer, u32 offset, 221 u16 words, void *data, 222 bool last_command) 223 { 224 i40e_status ret_code = I40E_ERR_NVM; 225 struct i40e_asq_cmd_details cmd_details; 226 227 memset(&cmd_details, 0, sizeof(cmd_details)); 228 cmd_details.wb_desc = &hw->nvm_wb_desc; 229 230 /* Here we are checking the SR limit only for the flat memory model. 231 * We cannot do it for the module-based model, as we did not acquire 232 * the NVM resource yet (we cannot get the module pointer value). 233 * Firmware will check the module-based model. 234 */ 235 if ((offset + words) > hw->nvm.sr_size) 236 i40e_debug(hw, I40E_DEBUG_NVM, 237 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 238 (offset + words), hw->nvm.sr_size); 239 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 240 /* We can write only up to 4KB (one sector), in one AQ write */ 241 i40e_debug(hw, I40E_DEBUG_NVM, 242 "NVM write fail error: tried to write %d words, limit is %d.\n", 243 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 244 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 245 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 246 /* A single write cannot spread over two sectors */ 247 i40e_debug(hw, I40E_DEBUG_NVM, 248 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 249 offset, words); 250 else 251 ret_code = i40e_aq_read_nvm(hw, module_pointer, 252 2 * offset, /*bytes*/ 253 2 * words, /*bytes*/ 254 data, last_command, &cmd_details); 255 256 return ret_code; 257 } 258 259 /** 260 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ 261 * @hw: pointer to the HW structure 262 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 263 * @data: word read from the Shadow RAM 264 * 265 * Reads one 16 bit word from the Shadow RAM using the AdminQ 266 **/ 267 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 268 u16 *data) 269 { 270 i40e_status ret_code = I40E_ERR_TIMEOUT; 271 272 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); 273 *data = le16_to_cpu(*(__le16 *)data); 274 275 return ret_code; 276 } 277 278 /** 279 * __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking 280 * @hw: pointer to the HW structure 281 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 282 * @data: word read from the Shadow RAM 283 * 284 * Reads one 16 bit word from the Shadow RAM. 285 * 286 * Do not use this function except in cases where the nvm lock is already 287 * taken via i40e_acquire_nvm(). 288 **/ 289 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw, 290 u16 offset, u16 *data) 291 { 292 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) 293 return i40e_read_nvm_word_aq(hw, offset, data); 294 295 return i40e_read_nvm_word_srctl(hw, offset, data); 296 } 297 298 /** 299 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary 300 * @hw: pointer to the HW structure 301 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 302 * @data: word read from the Shadow RAM 303 * 304 * Reads one 16 bit word from the Shadow RAM. 305 **/ 306 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, 307 u16 *data) 308 { 309 i40e_status ret_code = 0; 310 311 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) 312 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 313 if (ret_code) 314 return ret_code; 315 316 ret_code = __i40e_read_nvm_word(hw, offset, data); 317 318 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) 319 i40e_release_nvm(hw); 320 321 return ret_code; 322 } 323 324 /** 325 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register 326 * @hw: pointer to the HW structure 327 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 328 * @words: (in) number of words to read; (out) number of words actually read 329 * @data: words read from the Shadow RAM 330 * 331 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 332 * method. The buffer read is preceded by the NVM ownership take 333 * and followed by the release. 334 **/ 335 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, 336 u16 *words, u16 *data) 337 { 338 i40e_status ret_code = 0; 339 u16 index, word; 340 341 /* Loop thru the selected region */ 342 for (word = 0; word < *words; word++) { 343 index = offset + word; 344 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); 345 if (ret_code) 346 break; 347 } 348 349 /* Update the number of words read from the Shadow RAM */ 350 *words = word; 351 352 return ret_code; 353 } 354 355 /** 356 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ 357 * @hw: pointer to the HW structure 358 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 359 * @words: (in) number of words to read; (out) number of words actually read 360 * @data: words read from the Shadow RAM 361 * 362 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 363 * method. The buffer read is preceded by the NVM ownership take 364 * and followed by the release. 365 **/ 366 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, 367 u16 *words, u16 *data) 368 { 369 i40e_status ret_code; 370 u16 read_size; 371 bool last_cmd = false; 372 u16 words_read = 0; 373 u16 i = 0; 374 375 do { 376 /* Calculate number of bytes we should read in this step. 377 * FVL AQ do not allow to read more than one page at a time or 378 * to cross page boundaries. 379 */ 380 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS) 381 read_size = min(*words, 382 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - 383 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS))); 384 else 385 read_size = min((*words - words_read), 386 I40E_SR_SECTOR_SIZE_IN_WORDS); 387 388 /* Check if this is last command, if so set proper flag */ 389 if ((words_read + read_size) >= *words) 390 last_cmd = true; 391 392 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, 393 data + words_read, last_cmd); 394 if (ret_code) 395 goto read_nvm_buffer_aq_exit; 396 397 /* Increment counter for words already read and move offset to 398 * new read location 399 */ 400 words_read += read_size; 401 offset += read_size; 402 } while (words_read < *words); 403 404 for (i = 0; i < *words; i++) 405 data[i] = le16_to_cpu(((__le16 *)data)[i]); 406 407 read_nvm_buffer_aq_exit: 408 *words = words_read; 409 return ret_code; 410 } 411 412 /** 413 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock 414 * @hw: pointer to the HW structure 415 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 416 * @words: (in) number of words to read; (out) number of words actually read 417 * @data: words read from the Shadow RAM 418 * 419 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 420 * method. 421 **/ 422 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw, 423 u16 offset, u16 *words, 424 u16 *data) 425 { 426 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) 427 return i40e_read_nvm_buffer_aq(hw, offset, words, data); 428 429 return i40e_read_nvm_buffer_srctl(hw, offset, words, data); 430 } 431 432 /** 433 * i40e_write_nvm_aq - Writes Shadow RAM. 434 * @hw: pointer to the HW structure. 435 * @module_pointer: module pointer location in words from the NVM beginning 436 * @offset: offset in words from module start 437 * @words: number of words to write 438 * @data: buffer with words to write to the Shadow RAM 439 * @last_command: tells the AdminQ that this is the last command 440 * 441 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 442 **/ 443 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 444 u32 offset, u16 words, void *data, 445 bool last_command) 446 { 447 i40e_status ret_code = I40E_ERR_NVM; 448 struct i40e_asq_cmd_details cmd_details; 449 450 memset(&cmd_details, 0, sizeof(cmd_details)); 451 cmd_details.wb_desc = &hw->nvm_wb_desc; 452 453 /* Here we are checking the SR limit only for the flat memory model. 454 * We cannot do it for the module-based model, as we did not acquire 455 * the NVM resource yet (we cannot get the module pointer value). 456 * Firmware will check the module-based model. 457 */ 458 if ((offset + words) > hw->nvm.sr_size) 459 i40e_debug(hw, I40E_DEBUG_NVM, 460 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 461 (offset + words), hw->nvm.sr_size); 462 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 463 /* We can write only up to 4KB (one sector), in one AQ write */ 464 i40e_debug(hw, I40E_DEBUG_NVM, 465 "NVM write fail error: tried to write %d words, limit is %d.\n", 466 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 467 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 468 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 469 /* A single write cannot spread over two sectors */ 470 i40e_debug(hw, I40E_DEBUG_NVM, 471 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 472 offset, words); 473 else 474 ret_code = i40e_aq_update_nvm(hw, module_pointer, 475 2 * offset, /*bytes*/ 476 2 * words, /*bytes*/ 477 data, last_command, 0, 478 &cmd_details); 479 480 return ret_code; 481 } 482 483 /** 484 * i40e_calc_nvm_checksum - Calculates and returns the checksum 485 * @hw: pointer to hardware structure 486 * @checksum: pointer to the checksum 487 * 488 * This function calculates SW Checksum that covers the whole 64kB shadow RAM 489 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD 490 * is customer specific and unknown. Therefore, this function skips all maximum 491 * possible size of VPD (1kB). 492 **/ 493 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, 494 u16 *checksum) 495 { 496 i40e_status ret_code; 497 struct i40e_virt_mem vmem; 498 u16 pcie_alt_module = 0; 499 u16 checksum_local = 0; 500 u16 vpd_module = 0; 501 u16 *data; 502 u16 i = 0; 503 504 ret_code = i40e_allocate_virt_mem(hw, &vmem, 505 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); 506 if (ret_code) 507 goto i40e_calc_nvm_checksum_exit; 508 data = (u16 *)vmem.va; 509 510 /* read pointer to VPD area */ 511 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); 512 if (ret_code) { 513 ret_code = I40E_ERR_NVM_CHECKSUM; 514 goto i40e_calc_nvm_checksum_exit; 515 } 516 517 /* read pointer to PCIe Alt Auto-load module */ 518 ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, 519 &pcie_alt_module); 520 if (ret_code) { 521 ret_code = I40E_ERR_NVM_CHECKSUM; 522 goto i40e_calc_nvm_checksum_exit; 523 } 524 525 /* Calculate SW checksum that covers the whole 64kB shadow RAM 526 * except the VPD and PCIe ALT Auto-load modules 527 */ 528 for (i = 0; i < hw->nvm.sr_size; i++) { 529 /* Read SR page */ 530 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) { 531 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS; 532 533 ret_code = __i40e_read_nvm_buffer(hw, i, &words, data); 534 if (ret_code) { 535 ret_code = I40E_ERR_NVM_CHECKSUM; 536 goto i40e_calc_nvm_checksum_exit; 537 } 538 } 539 540 /* Skip Checksum word */ 541 if (i == I40E_SR_SW_CHECKSUM_WORD) 542 continue; 543 /* Skip VPD module (convert byte size to word count) */ 544 if ((i >= (u32)vpd_module) && 545 (i < ((u32)vpd_module + 546 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) { 547 continue; 548 } 549 /* Skip PCIe ALT module (convert byte size to word count) */ 550 if ((i >= (u32)pcie_alt_module) && 551 (i < ((u32)pcie_alt_module + 552 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) { 553 continue; 554 } 555 556 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS]; 557 } 558 559 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; 560 561 i40e_calc_nvm_checksum_exit: 562 i40e_free_virt_mem(hw, &vmem); 563 return ret_code; 564 } 565 566 /** 567 * i40e_update_nvm_checksum - Updates the NVM checksum 568 * @hw: pointer to hardware structure 569 * 570 * NVM ownership must be acquired before calling this function and released 571 * on ARQ completion event reception by caller. 572 * This function will commit SR to NVM. 573 **/ 574 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) 575 { 576 i40e_status ret_code; 577 u16 checksum; 578 __le16 le_sum; 579 580 ret_code = i40e_calc_nvm_checksum(hw, &checksum); 581 le_sum = cpu_to_le16(checksum); 582 if (!ret_code) 583 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, 584 1, &le_sum, true); 585 586 return ret_code; 587 } 588 589 /** 590 * i40e_validate_nvm_checksum - Validate EEPROM checksum 591 * @hw: pointer to hardware structure 592 * @checksum: calculated checksum 593 * 594 * Performs checksum calculation and validates the NVM SW checksum. If the 595 * caller does not need checksum, the value can be NULL. 596 **/ 597 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, 598 u16 *checksum) 599 { 600 i40e_status ret_code = 0; 601 u16 checksum_sr = 0; 602 u16 checksum_local = 0; 603 604 /* We must acquire the NVM lock in order to correctly synchronize the 605 * NVM accesses across multiple PFs. Without doing so it is possible 606 * for one of the PFs to read invalid data potentially indicating that 607 * the checksum is invalid. 608 */ 609 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 610 if (ret_code) 611 return ret_code; 612 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); 613 __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); 614 i40e_release_nvm(hw); 615 if (ret_code) 616 return ret_code; 617 618 /* Verify read checksum from EEPROM is the same as 619 * calculated checksum 620 */ 621 if (checksum_local != checksum_sr) 622 ret_code = I40E_ERR_NVM_CHECKSUM; 623 624 /* If the user cares, return the calculated checksum */ 625 if (checksum) 626 *checksum = checksum_local; 627 628 return ret_code; 629 } 630 631 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 632 struct i40e_nvm_access *cmd, 633 u8 *bytes, int *perrno); 634 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 635 struct i40e_nvm_access *cmd, 636 u8 *bytes, int *perrno); 637 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 638 struct i40e_nvm_access *cmd, 639 u8 *bytes, int *errno); 640 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 641 struct i40e_nvm_access *cmd, 642 int *perrno); 643 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 644 struct i40e_nvm_access *cmd, 645 int *perrno); 646 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 647 struct i40e_nvm_access *cmd, 648 u8 *bytes, int *perrno); 649 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 650 struct i40e_nvm_access *cmd, 651 u8 *bytes, int *perrno); 652 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 653 struct i40e_nvm_access *cmd, 654 u8 *bytes, int *perrno); 655 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 656 struct i40e_nvm_access *cmd, 657 u8 *bytes, int *perrno); 658 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw, 659 struct i40e_nvm_access *cmd, 660 u8 *bytes, int *perrno); 661 static inline u8 i40e_nvmupd_get_module(u32 val) 662 { 663 return (u8)(val & I40E_NVM_MOD_PNT_MASK); 664 } 665 static inline u8 i40e_nvmupd_get_transaction(u32 val) 666 { 667 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 668 } 669 670 static inline u8 i40e_nvmupd_get_preservation_flags(u32 val) 671 { 672 return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >> 673 I40E_NVM_PRESERVATION_FLAGS_SHIFT); 674 } 675 676 static const char * const i40e_nvm_update_state_str[] = { 677 "I40E_NVMUPD_INVALID", 678 "I40E_NVMUPD_READ_CON", 679 "I40E_NVMUPD_READ_SNT", 680 "I40E_NVMUPD_READ_LCB", 681 "I40E_NVMUPD_READ_SA", 682 "I40E_NVMUPD_WRITE_ERA", 683 "I40E_NVMUPD_WRITE_CON", 684 "I40E_NVMUPD_WRITE_SNT", 685 "I40E_NVMUPD_WRITE_LCB", 686 "I40E_NVMUPD_WRITE_SA", 687 "I40E_NVMUPD_CSUM_CON", 688 "I40E_NVMUPD_CSUM_SA", 689 "I40E_NVMUPD_CSUM_LCB", 690 "I40E_NVMUPD_STATUS", 691 "I40E_NVMUPD_EXEC_AQ", 692 "I40E_NVMUPD_GET_AQ_RESULT", 693 "I40E_NVMUPD_GET_AQ_EVENT", 694 }; 695 696 /** 697 * i40e_nvmupd_command - Process an NVM update command 698 * @hw: pointer to hardware structure 699 * @cmd: pointer to nvm update command 700 * @bytes: pointer to the data buffer 701 * @perrno: pointer to return error code 702 * 703 * Dispatches command depending on what update state is current 704 **/ 705 i40e_status i40e_nvmupd_command(struct i40e_hw *hw, 706 struct i40e_nvm_access *cmd, 707 u8 *bytes, int *perrno) 708 { 709 i40e_status status; 710 enum i40e_nvmupd_cmd upd_cmd; 711 712 /* assume success */ 713 *perrno = 0; 714 715 /* early check for status command and debug msgs */ 716 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 717 718 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", 719 i40e_nvm_update_state_str[upd_cmd], 720 hw->nvmupd_state, 721 hw->nvm_release_on_done, hw->nvm_wait_opcode, 722 cmd->command, cmd->config, cmd->offset, cmd->data_size); 723 724 if (upd_cmd == I40E_NVMUPD_INVALID) { 725 *perrno = -EFAULT; 726 i40e_debug(hw, I40E_DEBUG_NVM, 727 "i40e_nvmupd_validate_command returns %d errno %d\n", 728 upd_cmd, *perrno); 729 } 730 731 /* a status request returns immediately rather than 732 * going into the state machine 733 */ 734 if (upd_cmd == I40E_NVMUPD_STATUS) { 735 if (!cmd->data_size) { 736 *perrno = -EFAULT; 737 return I40E_ERR_BUF_TOO_SHORT; 738 } 739 740 bytes[0] = hw->nvmupd_state; 741 742 if (cmd->data_size >= 4) { 743 bytes[1] = 0; 744 *((u16 *)&bytes[2]) = hw->nvm_wait_opcode; 745 } 746 747 /* Clear error status on read */ 748 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) 749 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 750 751 return 0; 752 } 753 754 /* Clear status even it is not read and log */ 755 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { 756 i40e_debug(hw, I40E_DEBUG_NVM, 757 "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); 758 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 759 } 760 761 /* Acquire lock to prevent race condition where adminq_task 762 * can execute after i40e_nvmupd_nvm_read/write but before state 763 * variables (nvm_wait_opcode, nvm_release_on_done) are updated. 764 * 765 * During NVMUpdate, it is observed that lock could be held for 766 * ~5ms for most commands. However lock is held for ~60ms for 767 * NVMUPD_CSUM_LCB command. 768 */ 769 mutex_lock(&hw->aq.arq_mutex); 770 switch (hw->nvmupd_state) { 771 case I40E_NVMUPD_STATE_INIT: 772 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 773 break; 774 775 case I40E_NVMUPD_STATE_READING: 776 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 777 break; 778 779 case I40E_NVMUPD_STATE_WRITING: 780 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 781 break; 782 783 case I40E_NVMUPD_STATE_INIT_WAIT: 784 case I40E_NVMUPD_STATE_WRITE_WAIT: 785 /* if we need to stop waiting for an event, clear 786 * the wait info and return before doing anything else 787 */ 788 if (cmd->offset == 0xffff) { 789 i40e_nvmupd_clear_wait_state(hw); 790 status = 0; 791 break; 792 } 793 794 status = I40E_ERR_NOT_READY; 795 *perrno = -EBUSY; 796 break; 797 798 default: 799 /* invalid state, should never happen */ 800 i40e_debug(hw, I40E_DEBUG_NVM, 801 "NVMUPD: no such state %d\n", hw->nvmupd_state); 802 status = I40E_NOT_SUPPORTED; 803 *perrno = -ESRCH; 804 break; 805 } 806 807 mutex_unlock(&hw->aq.arq_mutex); 808 return status; 809 } 810 811 /** 812 * i40e_nvmupd_state_init - Handle NVM update state Init 813 * @hw: pointer to hardware structure 814 * @cmd: pointer to nvm update command buffer 815 * @bytes: pointer to the data buffer 816 * @perrno: pointer to return error code 817 * 818 * Process legitimate commands of the Init state and conditionally set next 819 * state. Reject all other commands. 820 **/ 821 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 822 struct i40e_nvm_access *cmd, 823 u8 *bytes, int *perrno) 824 { 825 i40e_status status = 0; 826 enum i40e_nvmupd_cmd upd_cmd; 827 828 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 829 830 switch (upd_cmd) { 831 case I40E_NVMUPD_READ_SA: 832 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 833 if (status) { 834 *perrno = i40e_aq_rc_to_posix(status, 835 hw->aq.asq_last_status); 836 } else { 837 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 838 i40e_release_nvm(hw); 839 } 840 break; 841 842 case I40E_NVMUPD_READ_SNT: 843 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 844 if (status) { 845 *perrno = i40e_aq_rc_to_posix(status, 846 hw->aq.asq_last_status); 847 } else { 848 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 849 if (status) 850 i40e_release_nvm(hw); 851 else 852 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 853 } 854 break; 855 856 case I40E_NVMUPD_WRITE_ERA: 857 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 858 if (status) { 859 *perrno = i40e_aq_rc_to_posix(status, 860 hw->aq.asq_last_status); 861 } else { 862 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 863 if (status) { 864 i40e_release_nvm(hw); 865 } else { 866 hw->nvm_release_on_done = true; 867 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; 868 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 869 } 870 } 871 break; 872 873 case I40E_NVMUPD_WRITE_SA: 874 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 875 if (status) { 876 *perrno = i40e_aq_rc_to_posix(status, 877 hw->aq.asq_last_status); 878 } else { 879 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 880 if (status) { 881 i40e_release_nvm(hw); 882 } else { 883 hw->nvm_release_on_done = true; 884 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 885 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 886 } 887 } 888 break; 889 890 case I40E_NVMUPD_WRITE_SNT: 891 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 892 if (status) { 893 *perrno = i40e_aq_rc_to_posix(status, 894 hw->aq.asq_last_status); 895 } else { 896 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 897 if (status) { 898 i40e_release_nvm(hw); 899 } else { 900 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 901 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 902 } 903 } 904 break; 905 906 case I40E_NVMUPD_CSUM_SA: 907 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 908 if (status) { 909 *perrno = i40e_aq_rc_to_posix(status, 910 hw->aq.asq_last_status); 911 } else { 912 status = i40e_update_nvm_checksum(hw); 913 if (status) { 914 *perrno = hw->aq.asq_last_status ? 915 i40e_aq_rc_to_posix(status, 916 hw->aq.asq_last_status) : 917 -EIO; 918 i40e_release_nvm(hw); 919 } else { 920 hw->nvm_release_on_done = true; 921 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 922 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 923 } 924 } 925 break; 926 927 case I40E_NVMUPD_EXEC_AQ: 928 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 929 break; 930 931 case I40E_NVMUPD_GET_AQ_RESULT: 932 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 933 break; 934 935 case I40E_NVMUPD_GET_AQ_EVENT: 936 status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno); 937 break; 938 939 default: 940 i40e_debug(hw, I40E_DEBUG_NVM, 941 "NVMUPD: bad cmd %s in init state\n", 942 i40e_nvm_update_state_str[upd_cmd]); 943 status = I40E_ERR_NVM; 944 *perrno = -ESRCH; 945 break; 946 } 947 return status; 948 } 949 950 /** 951 * i40e_nvmupd_state_reading - Handle NVM update state Reading 952 * @hw: pointer to hardware structure 953 * @cmd: pointer to nvm update command buffer 954 * @bytes: pointer to the data buffer 955 * @perrno: pointer to return error code 956 * 957 * NVM ownership is already held. Process legitimate commands and set any 958 * change in state; reject all other commands. 959 **/ 960 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 961 struct i40e_nvm_access *cmd, 962 u8 *bytes, int *perrno) 963 { 964 i40e_status status = 0; 965 enum i40e_nvmupd_cmd upd_cmd; 966 967 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 968 969 switch (upd_cmd) { 970 case I40E_NVMUPD_READ_SA: 971 case I40E_NVMUPD_READ_CON: 972 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 973 break; 974 975 case I40E_NVMUPD_READ_LCB: 976 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 977 i40e_release_nvm(hw); 978 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 979 break; 980 981 default: 982 i40e_debug(hw, I40E_DEBUG_NVM, 983 "NVMUPD: bad cmd %s in reading state.\n", 984 i40e_nvm_update_state_str[upd_cmd]); 985 status = I40E_NOT_SUPPORTED; 986 *perrno = -ESRCH; 987 break; 988 } 989 return status; 990 } 991 992 /** 993 * i40e_nvmupd_state_writing - Handle NVM update state Writing 994 * @hw: pointer to hardware structure 995 * @cmd: pointer to nvm update command buffer 996 * @bytes: pointer to the data buffer 997 * @perrno: pointer to return error code 998 * 999 * NVM ownership is already held. Process legitimate commands and set any 1000 * change in state; reject all other commands 1001 **/ 1002 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 1003 struct i40e_nvm_access *cmd, 1004 u8 *bytes, int *perrno) 1005 { 1006 i40e_status status = 0; 1007 enum i40e_nvmupd_cmd upd_cmd; 1008 bool retry_attempt = false; 1009 1010 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 1011 1012 retry: 1013 switch (upd_cmd) { 1014 case I40E_NVMUPD_WRITE_CON: 1015 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1016 if (!status) { 1017 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1018 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1019 } 1020 break; 1021 1022 case I40E_NVMUPD_WRITE_LCB: 1023 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 1024 if (status) { 1025 *perrno = hw->aq.asq_last_status ? 1026 i40e_aq_rc_to_posix(status, 1027 hw->aq.asq_last_status) : 1028 -EIO; 1029 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1030 } else { 1031 hw->nvm_release_on_done = true; 1032 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1033 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1034 } 1035 break; 1036 1037 case I40E_NVMUPD_CSUM_CON: 1038 /* Assumes the caller has acquired the nvm */ 1039 status = i40e_update_nvm_checksum(hw); 1040 if (status) { 1041 *perrno = hw->aq.asq_last_status ? 1042 i40e_aq_rc_to_posix(status, 1043 hw->aq.asq_last_status) : 1044 -EIO; 1045 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1046 } else { 1047 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1048 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 1049 } 1050 break; 1051 1052 case I40E_NVMUPD_CSUM_LCB: 1053 /* Assumes the caller has acquired the nvm */ 1054 status = i40e_update_nvm_checksum(hw); 1055 if (status) { 1056 *perrno = hw->aq.asq_last_status ? 1057 i40e_aq_rc_to_posix(status, 1058 hw->aq.asq_last_status) : 1059 -EIO; 1060 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1061 } else { 1062 hw->nvm_release_on_done = true; 1063 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; 1064 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1065 } 1066 break; 1067 1068 default: 1069 i40e_debug(hw, I40E_DEBUG_NVM, 1070 "NVMUPD: bad cmd %s in writing state.\n", 1071 i40e_nvm_update_state_str[upd_cmd]); 1072 status = I40E_NOT_SUPPORTED; 1073 *perrno = -ESRCH; 1074 break; 1075 } 1076 1077 /* In some circumstances, a multi-write transaction takes longer 1078 * than the default 3 minute timeout on the write semaphore. If 1079 * the write failed with an EBUSY status, this is likely the problem, 1080 * so here we try to reacquire the semaphore then retry the write. 1081 * We only do one retry, then give up. 1082 */ 1083 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 1084 !retry_attempt) { 1085 i40e_status old_status = status; 1086 u32 old_asq_status = hw->aq.asq_last_status; 1087 u32 gtime; 1088 1089 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 1090 if (gtime >= hw->nvm.hw_semaphore_timeout) { 1091 i40e_debug(hw, I40E_DEBUG_ALL, 1092 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 1093 gtime, hw->nvm.hw_semaphore_timeout); 1094 i40e_release_nvm(hw); 1095 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 1096 if (status) { 1097 i40e_debug(hw, I40E_DEBUG_ALL, 1098 "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 1099 hw->aq.asq_last_status); 1100 status = old_status; 1101 hw->aq.asq_last_status = old_asq_status; 1102 } else { 1103 retry_attempt = true; 1104 goto retry; 1105 } 1106 } 1107 } 1108 1109 return status; 1110 } 1111 1112 /** 1113 * i40e_nvmupd_clear_wait_state - clear wait state on hw 1114 * @hw: pointer to the hardware structure 1115 **/ 1116 void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw) 1117 { 1118 i40e_debug(hw, I40E_DEBUG_NVM, 1119 "NVMUPD: clearing wait on opcode 0x%04x\n", 1120 hw->nvm_wait_opcode); 1121 1122 if (hw->nvm_release_on_done) { 1123 i40e_release_nvm(hw); 1124 hw->nvm_release_on_done = false; 1125 } 1126 hw->nvm_wait_opcode = 0; 1127 1128 if (hw->aq.arq_last_status) { 1129 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; 1130 return; 1131 } 1132 1133 switch (hw->nvmupd_state) { 1134 case I40E_NVMUPD_STATE_INIT_WAIT: 1135 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1136 break; 1137 1138 case I40E_NVMUPD_STATE_WRITE_WAIT: 1139 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 1140 break; 1141 1142 default: 1143 break; 1144 } 1145 } 1146 1147 /** 1148 * i40e_nvmupd_check_wait_event - handle NVM update operation events 1149 * @hw: pointer to the hardware structure 1150 * @opcode: the event that just happened 1151 * @desc: AdminQ descriptor 1152 **/ 1153 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, 1154 struct i40e_aq_desc *desc) 1155 { 1156 u32 aq_desc_len = sizeof(struct i40e_aq_desc); 1157 1158 if (opcode == hw->nvm_wait_opcode) { 1159 memcpy(&hw->nvm_aq_event_desc, desc, aq_desc_len); 1160 i40e_nvmupd_clear_wait_state(hw); 1161 } 1162 } 1163 1164 /** 1165 * i40e_nvmupd_validate_command - Validate given command 1166 * @hw: pointer to hardware structure 1167 * @cmd: pointer to nvm update command buffer 1168 * @perrno: pointer to return error code 1169 * 1170 * Return one of the valid command types or I40E_NVMUPD_INVALID 1171 **/ 1172 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 1173 struct i40e_nvm_access *cmd, 1174 int *perrno) 1175 { 1176 enum i40e_nvmupd_cmd upd_cmd; 1177 u8 module, transaction; 1178 1179 /* anything that doesn't match a recognized case is an error */ 1180 upd_cmd = I40E_NVMUPD_INVALID; 1181 1182 transaction = i40e_nvmupd_get_transaction(cmd->config); 1183 module = i40e_nvmupd_get_module(cmd->config); 1184 1185 /* limits on data size */ 1186 if ((cmd->data_size < 1) || 1187 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 1188 i40e_debug(hw, I40E_DEBUG_NVM, 1189 "i40e_nvmupd_validate_command data_size %d\n", 1190 cmd->data_size); 1191 *perrno = -EFAULT; 1192 return I40E_NVMUPD_INVALID; 1193 } 1194 1195 switch (cmd->command) { 1196 case I40E_NVM_READ: 1197 switch (transaction) { 1198 case I40E_NVM_CON: 1199 upd_cmd = I40E_NVMUPD_READ_CON; 1200 break; 1201 case I40E_NVM_SNT: 1202 upd_cmd = I40E_NVMUPD_READ_SNT; 1203 break; 1204 case I40E_NVM_LCB: 1205 upd_cmd = I40E_NVMUPD_READ_LCB; 1206 break; 1207 case I40E_NVM_SA: 1208 upd_cmd = I40E_NVMUPD_READ_SA; 1209 break; 1210 case I40E_NVM_EXEC: 1211 if (module == 0xf) 1212 upd_cmd = I40E_NVMUPD_STATUS; 1213 else if (module == 0) 1214 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; 1215 break; 1216 case I40E_NVM_AQE: 1217 upd_cmd = I40E_NVMUPD_GET_AQ_EVENT; 1218 break; 1219 } 1220 break; 1221 1222 case I40E_NVM_WRITE: 1223 switch (transaction) { 1224 case I40E_NVM_CON: 1225 upd_cmd = I40E_NVMUPD_WRITE_CON; 1226 break; 1227 case I40E_NVM_SNT: 1228 upd_cmd = I40E_NVMUPD_WRITE_SNT; 1229 break; 1230 case I40E_NVM_LCB: 1231 upd_cmd = I40E_NVMUPD_WRITE_LCB; 1232 break; 1233 case I40E_NVM_SA: 1234 upd_cmd = I40E_NVMUPD_WRITE_SA; 1235 break; 1236 case I40E_NVM_ERA: 1237 upd_cmd = I40E_NVMUPD_WRITE_ERA; 1238 break; 1239 case I40E_NVM_CSUM: 1240 upd_cmd = I40E_NVMUPD_CSUM_CON; 1241 break; 1242 case (I40E_NVM_CSUM|I40E_NVM_SA): 1243 upd_cmd = I40E_NVMUPD_CSUM_SA; 1244 break; 1245 case (I40E_NVM_CSUM|I40E_NVM_LCB): 1246 upd_cmd = I40E_NVMUPD_CSUM_LCB; 1247 break; 1248 case I40E_NVM_EXEC: 1249 if (module == 0) 1250 upd_cmd = I40E_NVMUPD_EXEC_AQ; 1251 break; 1252 } 1253 break; 1254 } 1255 1256 return upd_cmd; 1257 } 1258 1259 /** 1260 * i40e_nvmupd_exec_aq - Run an AQ command 1261 * @hw: pointer to hardware structure 1262 * @cmd: pointer to nvm update command buffer 1263 * @bytes: pointer to the data buffer 1264 * @perrno: pointer to return error code 1265 * 1266 * cmd structure contains identifiers and data buffer 1267 **/ 1268 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 1269 struct i40e_nvm_access *cmd, 1270 u8 *bytes, int *perrno) 1271 { 1272 struct i40e_asq_cmd_details cmd_details; 1273 i40e_status status; 1274 struct i40e_aq_desc *aq_desc; 1275 u32 buff_size = 0; 1276 u8 *buff = NULL; 1277 u32 aq_desc_len; 1278 u32 aq_data_len; 1279 1280 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1281 if (cmd->offset == 0xffff) 1282 return 0; 1283 1284 memset(&cmd_details, 0, sizeof(cmd_details)); 1285 cmd_details.wb_desc = &hw->nvm_wb_desc; 1286 1287 aq_desc_len = sizeof(struct i40e_aq_desc); 1288 memset(&hw->nvm_wb_desc, 0, aq_desc_len); 1289 1290 /* get the aq descriptor */ 1291 if (cmd->data_size < aq_desc_len) { 1292 i40e_debug(hw, I40E_DEBUG_NVM, 1293 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n", 1294 cmd->data_size, aq_desc_len); 1295 *perrno = -EINVAL; 1296 return I40E_ERR_PARAM; 1297 } 1298 aq_desc = (struct i40e_aq_desc *)bytes; 1299 1300 /* if data buffer needed, make sure it's ready */ 1301 aq_data_len = cmd->data_size - aq_desc_len; 1302 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen)); 1303 if (buff_size) { 1304 if (!hw->nvm_buff.va) { 1305 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, 1306 hw->aq.asq_buf_size); 1307 if (status) 1308 i40e_debug(hw, I40E_DEBUG_NVM, 1309 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n", 1310 status); 1311 } 1312 1313 if (hw->nvm_buff.va) { 1314 buff = hw->nvm_buff.va; 1315 memcpy(buff, &bytes[aq_desc_len], aq_data_len); 1316 } 1317 } 1318 1319 if (cmd->offset) 1320 memset(&hw->nvm_aq_event_desc, 0, aq_desc_len); 1321 1322 /* and away we go! */ 1323 status = i40e_asq_send_command(hw, aq_desc, buff, 1324 buff_size, &cmd_details); 1325 if (status) { 1326 i40e_debug(hw, I40E_DEBUG_NVM, 1327 "i40e_nvmupd_exec_aq err %s aq_err %s\n", 1328 i40e_stat_str(hw, status), 1329 i40e_aq_str(hw, hw->aq.asq_last_status)); 1330 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1331 return status; 1332 } 1333 1334 /* should we wait for a followup event? */ 1335 if (cmd->offset) { 1336 hw->nvm_wait_opcode = cmd->offset; 1337 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 1338 } 1339 1340 return status; 1341 } 1342 1343 /** 1344 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq 1345 * @hw: pointer to hardware structure 1346 * @cmd: pointer to nvm update command buffer 1347 * @bytes: pointer to the data buffer 1348 * @perrno: pointer to return error code 1349 * 1350 * cmd structure contains identifiers and data buffer 1351 **/ 1352 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 1353 struct i40e_nvm_access *cmd, 1354 u8 *bytes, int *perrno) 1355 { 1356 u32 aq_total_len; 1357 u32 aq_desc_len; 1358 int remainder; 1359 u8 *buff; 1360 1361 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1362 1363 aq_desc_len = sizeof(struct i40e_aq_desc); 1364 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); 1365 1366 /* check offset range */ 1367 if (cmd->offset > aq_total_len) { 1368 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n", 1369 __func__, cmd->offset, aq_total_len); 1370 *perrno = -EINVAL; 1371 return I40E_ERR_PARAM; 1372 } 1373 1374 /* check copylength range */ 1375 if (cmd->data_size > (aq_total_len - cmd->offset)) { 1376 int new_len = aq_total_len - cmd->offset; 1377 1378 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n", 1379 __func__, cmd->data_size, new_len); 1380 cmd->data_size = new_len; 1381 } 1382 1383 remainder = cmd->data_size; 1384 if (cmd->offset < aq_desc_len) { 1385 u32 len = aq_desc_len - cmd->offset; 1386 1387 len = min(len, cmd->data_size); 1388 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n", 1389 __func__, cmd->offset, cmd->offset + len); 1390 1391 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; 1392 memcpy(bytes, buff, len); 1393 1394 bytes += len; 1395 remainder -= len; 1396 buff = hw->nvm_buff.va; 1397 } else { 1398 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len); 1399 } 1400 1401 if (remainder > 0) { 1402 int start_byte = buff - (u8 *)hw->nvm_buff.va; 1403 1404 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", 1405 __func__, start_byte, start_byte + remainder); 1406 memcpy(bytes, buff, remainder); 1407 } 1408 1409 return 0; 1410 } 1411 1412 /** 1413 * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq 1414 * @hw: pointer to hardware structure 1415 * @cmd: pointer to nvm update command buffer 1416 * @bytes: pointer to the data buffer 1417 * @perrno: pointer to return error code 1418 * 1419 * cmd structure contains identifiers and data buffer 1420 **/ 1421 static i40e_status i40e_nvmupd_get_aq_event(struct i40e_hw *hw, 1422 struct i40e_nvm_access *cmd, 1423 u8 *bytes, int *perrno) 1424 { 1425 u32 aq_total_len; 1426 u32 aq_desc_len; 1427 1428 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1429 1430 aq_desc_len = sizeof(struct i40e_aq_desc); 1431 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_aq_event_desc.datalen); 1432 1433 /* check copylength range */ 1434 if (cmd->data_size > aq_total_len) { 1435 i40e_debug(hw, I40E_DEBUG_NVM, 1436 "%s: copy length %d too big, trimming to %d\n", 1437 __func__, cmd->data_size, aq_total_len); 1438 cmd->data_size = aq_total_len; 1439 } 1440 1441 memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size); 1442 1443 return 0; 1444 } 1445 1446 /** 1447 * i40e_nvmupd_nvm_read - Read NVM 1448 * @hw: pointer to hardware structure 1449 * @cmd: pointer to nvm update command buffer 1450 * @bytes: pointer to the data buffer 1451 * @perrno: pointer to return error code 1452 * 1453 * cmd structure contains identifiers and data buffer 1454 **/ 1455 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1456 struct i40e_nvm_access *cmd, 1457 u8 *bytes, int *perrno) 1458 { 1459 struct i40e_asq_cmd_details cmd_details; 1460 i40e_status status; 1461 u8 module, transaction; 1462 bool last; 1463 1464 transaction = i40e_nvmupd_get_transaction(cmd->config); 1465 module = i40e_nvmupd_get_module(cmd->config); 1466 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1467 1468 memset(&cmd_details, 0, sizeof(cmd_details)); 1469 cmd_details.wb_desc = &hw->nvm_wb_desc; 1470 1471 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1472 bytes, last, &cmd_details); 1473 if (status) { 1474 i40e_debug(hw, I40E_DEBUG_NVM, 1475 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 1476 module, cmd->offset, cmd->data_size); 1477 i40e_debug(hw, I40E_DEBUG_NVM, 1478 "i40e_nvmupd_nvm_read status %d aq %d\n", 1479 status, hw->aq.asq_last_status); 1480 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1481 } 1482 1483 return status; 1484 } 1485 1486 /** 1487 * i40e_nvmupd_nvm_erase - Erase an NVM module 1488 * @hw: pointer to hardware structure 1489 * @cmd: pointer to nvm update command buffer 1490 * @perrno: pointer to return error code 1491 * 1492 * module, offset, data_size and data are in cmd structure 1493 **/ 1494 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1495 struct i40e_nvm_access *cmd, 1496 int *perrno) 1497 { 1498 i40e_status status = 0; 1499 struct i40e_asq_cmd_details cmd_details; 1500 u8 module, transaction; 1501 bool last; 1502 1503 transaction = i40e_nvmupd_get_transaction(cmd->config); 1504 module = i40e_nvmupd_get_module(cmd->config); 1505 last = (transaction & I40E_NVM_LCB); 1506 1507 memset(&cmd_details, 0, sizeof(cmd_details)); 1508 cmd_details.wb_desc = &hw->nvm_wb_desc; 1509 1510 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1511 last, &cmd_details); 1512 if (status) { 1513 i40e_debug(hw, I40E_DEBUG_NVM, 1514 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 1515 module, cmd->offset, cmd->data_size); 1516 i40e_debug(hw, I40E_DEBUG_NVM, 1517 "i40e_nvmupd_nvm_erase status %d aq %d\n", 1518 status, hw->aq.asq_last_status); 1519 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1520 } 1521 1522 return status; 1523 } 1524 1525 /** 1526 * i40e_nvmupd_nvm_write - Write NVM 1527 * @hw: pointer to hardware structure 1528 * @cmd: pointer to nvm update command buffer 1529 * @bytes: pointer to the data buffer 1530 * @perrno: pointer to return error code 1531 * 1532 * module, offset, data_size and data are in cmd structure 1533 **/ 1534 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1535 struct i40e_nvm_access *cmd, 1536 u8 *bytes, int *perrno) 1537 { 1538 i40e_status status = 0; 1539 struct i40e_asq_cmd_details cmd_details; 1540 u8 module, transaction; 1541 u8 preservation_flags; 1542 bool last; 1543 1544 transaction = i40e_nvmupd_get_transaction(cmd->config); 1545 module = i40e_nvmupd_get_module(cmd->config); 1546 last = (transaction & I40E_NVM_LCB); 1547 preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); 1548 1549 memset(&cmd_details, 0, sizeof(cmd_details)); 1550 cmd_details.wb_desc = &hw->nvm_wb_desc; 1551 1552 status = i40e_aq_update_nvm(hw, module, cmd->offset, 1553 (u16)cmd->data_size, bytes, last, 1554 preservation_flags, &cmd_details); 1555 if (status) { 1556 i40e_debug(hw, I40E_DEBUG_NVM, 1557 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 1558 module, cmd->offset, cmd->data_size); 1559 i40e_debug(hw, I40E_DEBUG_NVM, 1560 "i40e_nvmupd_nvm_write status %d aq %d\n", 1561 status, hw->aq.asq_last_status); 1562 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1563 } 1564 1565 return status; 1566 } 1567