1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_prototype.h" 28 29 /** 30 * i40e_init_nvm_ops - Initialize NVM function pointers 31 * @hw: pointer to the HW structure 32 * 33 * Setup the function pointers and the NVM info structure. Should be called 34 * once per NVM initialization, e.g. inside the i40e_init_shared_code(). 35 * Please notice that the NVM term is used here (& in all methods covered 36 * in this file) as an equivalent of the FLASH part mapped into the SR. 37 * We are accessing FLASH always thru the Shadow RAM. 38 **/ 39 i40e_status i40e_init_nvm(struct i40e_hw *hw) 40 { 41 struct i40e_nvm_info *nvm = &hw->nvm; 42 i40e_status ret_code = 0; 43 u32 fla, gens; 44 u8 sr_size; 45 46 /* The SR size is stored regardless of the nvm programming mode 47 * as the blank mode may be used in the factory line. 48 */ 49 gens = rd32(hw, I40E_GLNVM_GENS); 50 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 51 I40E_GLNVM_GENS_SR_SIZE_SHIFT); 52 /* Switching to words (sr_size contains power of 2KB) */ 53 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 54 55 /* Check if we are in the normal or blank NVM programming mode */ 56 fla = rd32(hw, I40E_GLNVM_FLA); 57 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */ 58 /* Max NVM timeout */ 59 nvm->timeout = I40E_MAX_NVM_TIMEOUT; 60 nvm->blank_nvm_mode = false; 61 } else { /* Blank programming mode */ 62 nvm->blank_nvm_mode = true; 63 ret_code = I40E_ERR_NVM_BLANK_MODE; 64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); 65 } 66 67 return ret_code; 68 } 69 70 /** 71 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership 72 * @hw: pointer to the HW structure 73 * @access: NVM access type (read or write) 74 * 75 * This function will request NVM ownership for reading 76 * via the proper Admin Command. 77 **/ 78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw, 79 enum i40e_aq_resource_access_type access) 80 { 81 i40e_status ret_code = 0; 82 u64 gtime, timeout; 83 u64 time_left = 0; 84 85 if (hw->nvm.blank_nvm_mode) 86 goto i40e_i40e_acquire_nvm_exit; 87 88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, 89 0, &time_left, NULL); 90 /* Reading the Global Device Timer */ 91 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 92 93 /* Store the timeout */ 94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; 95 96 if (ret_code) 97 i40e_debug(hw, I40E_DEBUG_NVM, 98 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n", 99 access, time_left, ret_code, hw->aq.asq_last_status); 100 101 if (ret_code && time_left) { 102 /* Poll until the current NVM owner timeouts */ 103 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime; 104 while ((gtime < timeout) && time_left) { 105 usleep_range(10000, 20000); 106 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 107 ret_code = i40e_aq_request_resource(hw, 108 I40E_NVM_RESOURCE_ID, 109 access, 0, &time_left, 110 NULL); 111 if (!ret_code) { 112 hw->nvm.hw_semaphore_timeout = 113 I40E_MS_TO_GTIME(time_left) + gtime; 114 break; 115 } 116 } 117 if (ret_code) { 118 hw->nvm.hw_semaphore_timeout = 0; 119 i40e_debug(hw, I40E_DEBUG_NVM, 120 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n", 121 time_left, ret_code, hw->aq.asq_last_status); 122 } 123 } 124 125 i40e_i40e_acquire_nvm_exit: 126 return ret_code; 127 } 128 129 /** 130 * i40e_release_nvm - Generic request for releasing the NVM ownership 131 * @hw: pointer to the HW structure 132 * 133 * This function will release NVM resource via the proper Admin Command. 134 **/ 135 void i40e_release_nvm(struct i40e_hw *hw) 136 { 137 if (!hw->nvm.blank_nvm_mode) 138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 139 } 140 141 /** 142 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit 143 * @hw: pointer to the HW structure 144 * 145 * Polls the SRCTL Shadow RAM register done bit. 146 **/ 147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) 148 { 149 i40e_status ret_code = I40E_ERR_TIMEOUT; 150 u32 srctl, wait_cnt; 151 152 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */ 153 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { 154 srctl = rd32(hw, I40E_GLNVM_SRCTL); 155 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { 156 ret_code = 0; 157 break; 158 } 159 udelay(5); 160 } 161 if (ret_code == I40E_ERR_TIMEOUT) 162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); 163 return ret_code; 164 } 165 166 /** 167 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register 168 * @hw: pointer to the HW structure 169 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 170 * @data: word read from the Shadow RAM 171 * 172 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 173 **/ 174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, 175 u16 *data) 176 { 177 i40e_status ret_code = I40E_ERR_TIMEOUT; 178 u32 sr_reg; 179 180 if (offset >= hw->nvm.sr_size) { 181 i40e_debug(hw, I40E_DEBUG_NVM, 182 "NVM read error: offset %d beyond Shadow RAM limit %d\n", 183 offset, hw->nvm.sr_size); 184 ret_code = I40E_ERR_PARAM; 185 goto read_nvm_exit; 186 } 187 188 /* Poll the done bit first */ 189 ret_code = i40e_poll_sr_srctl_done_bit(hw); 190 if (!ret_code) { 191 /* Write the address and start reading */ 192 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 193 BIT(I40E_GLNVM_SRCTL_START_SHIFT); 194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg); 195 196 /* Poll I40E_GLNVM_SRCTL until the done bit is set */ 197 ret_code = i40e_poll_sr_srctl_done_bit(hw); 198 if (!ret_code) { 199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 200 *data = (u16)((sr_reg & 201 I40E_GLNVM_SRDATA_RDDATA_MASK) 202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 203 } 204 } 205 if (ret_code) 206 i40e_debug(hw, I40E_DEBUG_NVM, 207 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", 208 offset); 209 210 read_nvm_exit: 211 return ret_code; 212 } 213 214 /** 215 * i40e_read_nvm_aq - Read Shadow RAM. 216 * @hw: pointer to the HW structure. 217 * @module_pointer: module pointer location in words from the NVM beginning 218 * @offset: offset in words from module start 219 * @words: number of words to write 220 * @data: buffer with words to write to the Shadow RAM 221 * @last_command: tells the AdminQ that this is the last command 222 * 223 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 224 **/ 225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 226 u32 offset, u16 words, void *data, 227 bool last_command) 228 { 229 i40e_status ret_code = I40E_ERR_NVM; 230 struct i40e_asq_cmd_details cmd_details; 231 232 memset(&cmd_details, 0, sizeof(cmd_details)); 233 234 /* Here we are checking the SR limit only for the flat memory model. 235 * We cannot do it for the module-based model, as we did not acquire 236 * the NVM resource yet (we cannot get the module pointer value). 237 * Firmware will check the module-based model. 238 */ 239 if ((offset + words) > hw->nvm.sr_size) 240 i40e_debug(hw, I40E_DEBUG_NVM, 241 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 242 (offset + words), hw->nvm.sr_size); 243 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 244 /* We can write only up to 4KB (one sector), in one AQ write */ 245 i40e_debug(hw, I40E_DEBUG_NVM, 246 "NVM write fail error: tried to write %d words, limit is %d.\n", 247 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 248 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 249 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 250 /* A single write cannot spread over two sectors */ 251 i40e_debug(hw, I40E_DEBUG_NVM, 252 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 253 offset, words); 254 else 255 ret_code = i40e_aq_read_nvm(hw, module_pointer, 256 2 * offset, /*bytes*/ 257 2 * words, /*bytes*/ 258 data, last_command, &cmd_details); 259 260 return ret_code; 261 } 262 263 /** 264 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ 265 * @hw: pointer to the HW structure 266 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 267 * @data: word read from the Shadow RAM 268 * 269 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 270 **/ 271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 272 u16 *data) 273 { 274 i40e_status ret_code = I40E_ERR_TIMEOUT; 275 276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); 277 *data = le16_to_cpu(*(__le16 *)data); 278 279 return ret_code; 280 } 281 282 /** 283 * i40e_read_nvm_word - Reads Shadow RAM 284 * @hw: pointer to the HW structure 285 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 286 * @data: word read from the Shadow RAM 287 * 288 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 289 **/ 290 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, 291 u16 *data) 292 { 293 if (hw->mac.type == I40E_MAC_X722) 294 return i40e_read_nvm_word_aq(hw, offset, data); 295 return i40e_read_nvm_word_srctl(hw, offset, data); 296 } 297 298 /** 299 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register 300 * @hw: pointer to the HW structure 301 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 302 * @words: (in) number of words to read; (out) number of words actually read 303 * @data: words read from the Shadow RAM 304 * 305 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 306 * method. The buffer read is preceded by the NVM ownership take 307 * and followed by the release. 308 **/ 309 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, 310 u16 *words, u16 *data) 311 { 312 i40e_status ret_code = 0; 313 u16 index, word; 314 315 /* Loop thru the selected region */ 316 for (word = 0; word < *words; word++) { 317 index = offset + word; 318 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); 319 if (ret_code) 320 break; 321 } 322 323 /* Update the number of words read from the Shadow RAM */ 324 *words = word; 325 326 return ret_code; 327 } 328 329 /** 330 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ 331 * @hw: pointer to the HW structure 332 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 333 * @words: (in) number of words to read; (out) number of words actually read 334 * @data: words read from the Shadow RAM 335 * 336 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 337 * method. The buffer read is preceded by the NVM ownership take 338 * and followed by the release. 339 **/ 340 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, 341 u16 *words, u16 *data) 342 { 343 i40e_status ret_code; 344 u16 read_size = *words; 345 bool last_cmd = false; 346 u16 words_read = 0; 347 u16 i = 0; 348 349 do { 350 /* Calculate number of bytes we should read in this step. 351 * FVL AQ do not allow to read more than one page at a time or 352 * to cross page boundaries. 353 */ 354 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS) 355 read_size = min(*words, 356 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - 357 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS))); 358 else 359 read_size = min((*words - words_read), 360 I40E_SR_SECTOR_SIZE_IN_WORDS); 361 362 /* Check if this is last command, if so set proper flag */ 363 if ((words_read + read_size) >= *words) 364 last_cmd = true; 365 366 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, 367 data + words_read, last_cmd); 368 if (ret_code) 369 goto read_nvm_buffer_aq_exit; 370 371 /* Increment counter for words already read and move offset to 372 * new read location 373 */ 374 words_read += read_size; 375 offset += read_size; 376 } while (words_read < *words); 377 378 for (i = 0; i < *words; i++) 379 data[i] = le16_to_cpu(((__le16 *)data)[i]); 380 381 read_nvm_buffer_aq_exit: 382 *words = words_read; 383 return ret_code; 384 } 385 386 /** 387 * i40e_read_nvm_buffer - Reads Shadow RAM buffer 388 * @hw: pointer to the HW structure 389 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 390 * @words: (in) number of words to read; (out) number of words actually read 391 * @data: words read from the Shadow RAM 392 * 393 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 394 * method. The buffer read is preceded by the NVM ownership take 395 * and followed by the release. 396 **/ 397 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, 398 u16 *words, u16 *data) 399 { 400 if (hw->mac.type == I40E_MAC_X722) 401 return i40e_read_nvm_buffer_aq(hw, offset, words, data); 402 return i40e_read_nvm_buffer_srctl(hw, offset, words, data); 403 } 404 405 /** 406 * i40e_write_nvm_aq - Writes Shadow RAM. 407 * @hw: pointer to the HW structure. 408 * @module_pointer: module pointer location in words from the NVM beginning 409 * @offset: offset in words from module start 410 * @words: number of words to write 411 * @data: buffer with words to write to the Shadow RAM 412 * @last_command: tells the AdminQ that this is the last command 413 * 414 * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 415 **/ 416 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 417 u32 offset, u16 words, void *data, 418 bool last_command) 419 { 420 i40e_status ret_code = I40E_ERR_NVM; 421 struct i40e_asq_cmd_details cmd_details; 422 423 memset(&cmd_details, 0, sizeof(cmd_details)); 424 cmd_details.wb_desc = &hw->nvm_wb_desc; 425 426 /* Here we are checking the SR limit only for the flat memory model. 427 * We cannot do it for the module-based model, as we did not acquire 428 * the NVM resource yet (we cannot get the module pointer value). 429 * Firmware will check the module-based model. 430 */ 431 if ((offset + words) > hw->nvm.sr_size) 432 i40e_debug(hw, I40E_DEBUG_NVM, 433 "NVM write error: offset %d beyond Shadow RAM limit %d\n", 434 (offset + words), hw->nvm.sr_size); 435 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 436 /* We can write only up to 4KB (one sector), in one AQ write */ 437 i40e_debug(hw, I40E_DEBUG_NVM, 438 "NVM write fail error: tried to write %d words, limit is %d.\n", 439 words, I40E_SR_SECTOR_SIZE_IN_WORDS); 440 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 441 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 442 /* A single write cannot spread over two sectors */ 443 i40e_debug(hw, I40E_DEBUG_NVM, 444 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 445 offset, words); 446 else 447 ret_code = i40e_aq_update_nvm(hw, module_pointer, 448 2 * offset, /*bytes*/ 449 2 * words, /*bytes*/ 450 data, last_command, &cmd_details); 451 452 return ret_code; 453 } 454 455 /** 456 * i40e_calc_nvm_checksum - Calculates and returns the checksum 457 * @hw: pointer to hardware structure 458 * @checksum: pointer to the checksum 459 * 460 * This function calculates SW Checksum that covers the whole 64kB shadow RAM 461 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD 462 * is customer specific and unknown. Therefore, this function skips all maximum 463 * possible size of VPD (1kB). 464 **/ 465 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, 466 u16 *checksum) 467 { 468 i40e_status ret_code = 0; 469 struct i40e_virt_mem vmem; 470 u16 pcie_alt_module = 0; 471 u16 checksum_local = 0; 472 u16 vpd_module = 0; 473 u16 *data; 474 u16 i = 0; 475 476 ret_code = i40e_allocate_virt_mem(hw, &vmem, 477 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); 478 if (ret_code) 479 goto i40e_calc_nvm_checksum_exit; 480 data = (u16 *)vmem.va; 481 482 /* read pointer to VPD area */ 483 ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); 484 if (ret_code) { 485 ret_code = I40E_ERR_NVM_CHECKSUM; 486 goto i40e_calc_nvm_checksum_exit; 487 } 488 489 /* read pointer to PCIe Alt Auto-load module */ 490 ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, 491 &pcie_alt_module); 492 if (ret_code) { 493 ret_code = I40E_ERR_NVM_CHECKSUM; 494 goto i40e_calc_nvm_checksum_exit; 495 } 496 497 /* Calculate SW checksum that covers the whole 64kB shadow RAM 498 * except the VPD and PCIe ALT Auto-load modules 499 */ 500 for (i = 0; i < hw->nvm.sr_size; i++) { 501 /* Read SR page */ 502 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) { 503 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS; 504 505 ret_code = i40e_read_nvm_buffer(hw, i, &words, data); 506 if (ret_code) { 507 ret_code = I40E_ERR_NVM_CHECKSUM; 508 goto i40e_calc_nvm_checksum_exit; 509 } 510 } 511 512 /* Skip Checksum word */ 513 if (i == I40E_SR_SW_CHECKSUM_WORD) 514 continue; 515 /* Skip VPD module (convert byte size to word count) */ 516 if ((i >= (u32)vpd_module) && 517 (i < ((u32)vpd_module + 518 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) { 519 continue; 520 } 521 /* Skip PCIe ALT module (convert byte size to word count) */ 522 if ((i >= (u32)pcie_alt_module) && 523 (i < ((u32)pcie_alt_module + 524 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) { 525 continue; 526 } 527 528 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS]; 529 } 530 531 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; 532 533 i40e_calc_nvm_checksum_exit: 534 i40e_free_virt_mem(hw, &vmem); 535 return ret_code; 536 } 537 538 /** 539 * i40e_update_nvm_checksum - Updates the NVM checksum 540 * @hw: pointer to hardware structure 541 * 542 * NVM ownership must be acquired before calling this function and released 543 * on ARQ completion event reception by caller. 544 * This function will commit SR to NVM. 545 **/ 546 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) 547 { 548 i40e_status ret_code = 0; 549 u16 checksum; 550 551 ret_code = i40e_calc_nvm_checksum(hw, &checksum); 552 if (!ret_code) 553 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, 554 1, &checksum, true); 555 556 return ret_code; 557 } 558 559 /** 560 * i40e_validate_nvm_checksum - Validate EEPROM checksum 561 * @hw: pointer to hardware structure 562 * @checksum: calculated checksum 563 * 564 * Performs checksum calculation and validates the NVM SW checksum. If the 565 * caller does not need checksum, the value can be NULL. 566 **/ 567 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, 568 u16 *checksum) 569 { 570 i40e_status ret_code = 0; 571 u16 checksum_sr = 0; 572 u16 checksum_local = 0; 573 574 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); 575 if (ret_code) 576 goto i40e_validate_nvm_checksum_exit; 577 578 /* Do not use i40e_read_nvm_word() because we do not want to take 579 * the synchronization semaphores twice here. 580 */ 581 i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); 582 583 /* Verify read checksum from EEPROM is the same as 584 * calculated checksum 585 */ 586 if (checksum_local != checksum_sr) 587 ret_code = I40E_ERR_NVM_CHECKSUM; 588 589 /* If the user cares, return the calculated checksum */ 590 if (checksum) 591 *checksum = checksum_local; 592 593 i40e_validate_nvm_checksum_exit: 594 return ret_code; 595 } 596 597 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 598 struct i40e_nvm_access *cmd, 599 u8 *bytes, int *perrno); 600 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 601 struct i40e_nvm_access *cmd, 602 u8 *bytes, int *perrno); 603 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 604 struct i40e_nvm_access *cmd, 605 u8 *bytes, int *errno); 606 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 607 struct i40e_nvm_access *cmd, 608 int *perrno); 609 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 610 struct i40e_nvm_access *cmd, 611 int *perrno); 612 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 613 struct i40e_nvm_access *cmd, 614 u8 *bytes, int *perrno); 615 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 616 struct i40e_nvm_access *cmd, 617 u8 *bytes, int *perrno); 618 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 619 struct i40e_nvm_access *cmd, 620 u8 *bytes, int *perrno); 621 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 622 struct i40e_nvm_access *cmd, 623 u8 *bytes, int *perrno); 624 static inline u8 i40e_nvmupd_get_module(u32 val) 625 { 626 return (u8)(val & I40E_NVM_MOD_PNT_MASK); 627 } 628 static inline u8 i40e_nvmupd_get_transaction(u32 val) 629 { 630 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 631 } 632 633 static char *i40e_nvm_update_state_str[] = { 634 "I40E_NVMUPD_INVALID", 635 "I40E_NVMUPD_READ_CON", 636 "I40E_NVMUPD_READ_SNT", 637 "I40E_NVMUPD_READ_LCB", 638 "I40E_NVMUPD_READ_SA", 639 "I40E_NVMUPD_WRITE_ERA", 640 "I40E_NVMUPD_WRITE_CON", 641 "I40E_NVMUPD_WRITE_SNT", 642 "I40E_NVMUPD_WRITE_LCB", 643 "I40E_NVMUPD_WRITE_SA", 644 "I40E_NVMUPD_CSUM_CON", 645 "I40E_NVMUPD_CSUM_SA", 646 "I40E_NVMUPD_CSUM_LCB", 647 "I40E_NVMUPD_STATUS", 648 "I40E_NVMUPD_EXEC_AQ", 649 "I40E_NVMUPD_GET_AQ_RESULT", 650 }; 651 652 /** 653 * i40e_nvmupd_command - Process an NVM update command 654 * @hw: pointer to hardware structure 655 * @cmd: pointer to nvm update command 656 * @bytes: pointer to the data buffer 657 * @perrno: pointer to return error code 658 * 659 * Dispatches command depending on what update state is current 660 **/ 661 i40e_status i40e_nvmupd_command(struct i40e_hw *hw, 662 struct i40e_nvm_access *cmd, 663 u8 *bytes, int *perrno) 664 { 665 i40e_status status; 666 enum i40e_nvmupd_cmd upd_cmd; 667 668 /* assume success */ 669 *perrno = 0; 670 671 /* early check for status command and debug msgs */ 672 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 673 674 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d\n", 675 i40e_nvm_update_state_str[upd_cmd], 676 hw->nvmupd_state, 677 hw->aq.nvm_release_on_done); 678 679 if (upd_cmd == I40E_NVMUPD_INVALID) { 680 *perrno = -EFAULT; 681 i40e_debug(hw, I40E_DEBUG_NVM, 682 "i40e_nvmupd_validate_command returns %d errno %d\n", 683 upd_cmd, *perrno); 684 } 685 686 /* a status request returns immediately rather than 687 * going into the state machine 688 */ 689 if (upd_cmd == I40E_NVMUPD_STATUS) { 690 bytes[0] = hw->nvmupd_state; 691 return 0; 692 } 693 694 switch (hw->nvmupd_state) { 695 case I40E_NVMUPD_STATE_INIT: 696 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 697 break; 698 699 case I40E_NVMUPD_STATE_READING: 700 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 701 break; 702 703 case I40E_NVMUPD_STATE_WRITING: 704 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 705 break; 706 707 case I40E_NVMUPD_STATE_INIT_WAIT: 708 case I40E_NVMUPD_STATE_WRITE_WAIT: 709 status = I40E_ERR_NOT_READY; 710 *perrno = -EBUSY; 711 break; 712 713 default: 714 /* invalid state, should never happen */ 715 i40e_debug(hw, I40E_DEBUG_NVM, 716 "NVMUPD: no such state %d\n", hw->nvmupd_state); 717 status = I40E_NOT_SUPPORTED; 718 *perrno = -ESRCH; 719 break; 720 } 721 return status; 722 } 723 724 /** 725 * i40e_nvmupd_state_init - Handle NVM update state Init 726 * @hw: pointer to hardware structure 727 * @cmd: pointer to nvm update command buffer 728 * @bytes: pointer to the data buffer 729 * @perrno: pointer to return error code 730 * 731 * Process legitimate commands of the Init state and conditionally set next 732 * state. Reject all other commands. 733 **/ 734 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 735 struct i40e_nvm_access *cmd, 736 u8 *bytes, int *perrno) 737 { 738 i40e_status status = 0; 739 enum i40e_nvmupd_cmd upd_cmd; 740 741 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 742 743 switch (upd_cmd) { 744 case I40E_NVMUPD_READ_SA: 745 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 746 if (status) { 747 *perrno = i40e_aq_rc_to_posix(status, 748 hw->aq.asq_last_status); 749 } else { 750 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 751 i40e_release_nvm(hw); 752 } 753 break; 754 755 case I40E_NVMUPD_READ_SNT: 756 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 757 if (status) { 758 *perrno = i40e_aq_rc_to_posix(status, 759 hw->aq.asq_last_status); 760 } else { 761 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 762 if (status) 763 i40e_release_nvm(hw); 764 else 765 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 766 } 767 break; 768 769 case I40E_NVMUPD_WRITE_ERA: 770 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 771 if (status) { 772 *perrno = i40e_aq_rc_to_posix(status, 773 hw->aq.asq_last_status); 774 } else { 775 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 776 if (status) { 777 i40e_release_nvm(hw); 778 } else { 779 hw->aq.nvm_release_on_done = true; 780 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 781 } 782 } 783 break; 784 785 case I40E_NVMUPD_WRITE_SA: 786 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 787 if (status) { 788 *perrno = i40e_aq_rc_to_posix(status, 789 hw->aq.asq_last_status); 790 } else { 791 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 792 if (status) { 793 i40e_release_nvm(hw); 794 } else { 795 hw->aq.nvm_release_on_done = true; 796 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 797 } 798 } 799 break; 800 801 case I40E_NVMUPD_WRITE_SNT: 802 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 803 if (status) { 804 *perrno = i40e_aq_rc_to_posix(status, 805 hw->aq.asq_last_status); 806 } else { 807 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 808 if (status) 809 i40e_release_nvm(hw); 810 else 811 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 812 } 813 break; 814 815 case I40E_NVMUPD_CSUM_SA: 816 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 817 if (status) { 818 *perrno = i40e_aq_rc_to_posix(status, 819 hw->aq.asq_last_status); 820 } else { 821 status = i40e_update_nvm_checksum(hw); 822 if (status) { 823 *perrno = hw->aq.asq_last_status ? 824 i40e_aq_rc_to_posix(status, 825 hw->aq.asq_last_status) : 826 -EIO; 827 i40e_release_nvm(hw); 828 } else { 829 hw->aq.nvm_release_on_done = true; 830 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 831 } 832 } 833 break; 834 835 case I40E_NVMUPD_EXEC_AQ: 836 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 837 break; 838 839 case I40E_NVMUPD_GET_AQ_RESULT: 840 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 841 break; 842 843 default: 844 i40e_debug(hw, I40E_DEBUG_NVM, 845 "NVMUPD: bad cmd %s in init state\n", 846 i40e_nvm_update_state_str[upd_cmd]); 847 status = I40E_ERR_NVM; 848 *perrno = -ESRCH; 849 break; 850 } 851 return status; 852 } 853 854 /** 855 * i40e_nvmupd_state_reading - Handle NVM update state Reading 856 * @hw: pointer to hardware structure 857 * @cmd: pointer to nvm update command buffer 858 * @bytes: pointer to the data buffer 859 * @perrno: pointer to return error code 860 * 861 * NVM ownership is already held. Process legitimate commands and set any 862 * change in state; reject all other commands. 863 **/ 864 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 865 struct i40e_nvm_access *cmd, 866 u8 *bytes, int *perrno) 867 { 868 i40e_status status = 0; 869 enum i40e_nvmupd_cmd upd_cmd; 870 871 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 872 873 switch (upd_cmd) { 874 case I40E_NVMUPD_READ_SA: 875 case I40E_NVMUPD_READ_CON: 876 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 877 break; 878 879 case I40E_NVMUPD_READ_LCB: 880 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 881 i40e_release_nvm(hw); 882 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 883 break; 884 885 default: 886 i40e_debug(hw, I40E_DEBUG_NVM, 887 "NVMUPD: bad cmd %s in reading state.\n", 888 i40e_nvm_update_state_str[upd_cmd]); 889 status = I40E_NOT_SUPPORTED; 890 *perrno = -ESRCH; 891 break; 892 } 893 return status; 894 } 895 896 /** 897 * i40e_nvmupd_state_writing - Handle NVM update state Writing 898 * @hw: pointer to hardware structure 899 * @cmd: pointer to nvm update command buffer 900 * @bytes: pointer to the data buffer 901 * @perrno: pointer to return error code 902 * 903 * NVM ownership is already held. Process legitimate commands and set any 904 * change in state; reject all other commands 905 **/ 906 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 907 struct i40e_nvm_access *cmd, 908 u8 *bytes, int *perrno) 909 { 910 i40e_status status = 0; 911 enum i40e_nvmupd_cmd upd_cmd; 912 bool retry_attempt = false; 913 914 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 915 916 retry: 917 switch (upd_cmd) { 918 case I40E_NVMUPD_WRITE_CON: 919 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 920 if (!status) 921 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 922 break; 923 924 case I40E_NVMUPD_WRITE_LCB: 925 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 926 if (status) { 927 *perrno = hw->aq.asq_last_status ? 928 i40e_aq_rc_to_posix(status, 929 hw->aq.asq_last_status) : 930 -EIO; 931 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 932 } else { 933 hw->aq.nvm_release_on_done = true; 934 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 935 } 936 break; 937 938 case I40E_NVMUPD_CSUM_CON: 939 status = i40e_update_nvm_checksum(hw); 940 if (status) { 941 *perrno = hw->aq.asq_last_status ? 942 i40e_aq_rc_to_posix(status, 943 hw->aq.asq_last_status) : 944 -EIO; 945 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 946 } else { 947 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 948 } 949 break; 950 951 case I40E_NVMUPD_CSUM_LCB: 952 status = i40e_update_nvm_checksum(hw); 953 if (status) { 954 *perrno = hw->aq.asq_last_status ? 955 i40e_aq_rc_to_posix(status, 956 hw->aq.asq_last_status) : 957 -EIO; 958 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 959 } else { 960 hw->aq.nvm_release_on_done = true; 961 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 962 } 963 break; 964 965 default: 966 i40e_debug(hw, I40E_DEBUG_NVM, 967 "NVMUPD: bad cmd %s in writing state.\n", 968 i40e_nvm_update_state_str[upd_cmd]); 969 status = I40E_NOT_SUPPORTED; 970 *perrno = -ESRCH; 971 break; 972 } 973 974 /* In some circumstances, a multi-write transaction takes longer 975 * than the default 3 minute timeout on the write semaphore. If 976 * the write failed with an EBUSY status, this is likely the problem, 977 * so here we try to reacquire the semaphore then retry the write. 978 * We only do one retry, then give up. 979 */ 980 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 981 !retry_attempt) { 982 i40e_status old_status = status; 983 u32 old_asq_status = hw->aq.asq_last_status; 984 u32 gtime; 985 986 gtime = rd32(hw, I40E_GLVFGEN_TIMER); 987 if (gtime >= hw->nvm.hw_semaphore_timeout) { 988 i40e_debug(hw, I40E_DEBUG_ALL, 989 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 990 gtime, hw->nvm.hw_semaphore_timeout); 991 i40e_release_nvm(hw); 992 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 993 if (status) { 994 i40e_debug(hw, I40E_DEBUG_ALL, 995 "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 996 hw->aq.asq_last_status); 997 status = old_status; 998 hw->aq.asq_last_status = old_asq_status; 999 } else { 1000 retry_attempt = true; 1001 goto retry; 1002 } 1003 } 1004 } 1005 1006 return status; 1007 } 1008 1009 /** 1010 * i40e_nvmupd_validate_command - Validate given command 1011 * @hw: pointer to hardware structure 1012 * @cmd: pointer to nvm update command buffer 1013 * @perrno: pointer to return error code 1014 * 1015 * Return one of the valid command types or I40E_NVMUPD_INVALID 1016 **/ 1017 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 1018 struct i40e_nvm_access *cmd, 1019 int *perrno) 1020 { 1021 enum i40e_nvmupd_cmd upd_cmd; 1022 u8 module, transaction; 1023 1024 /* anything that doesn't match a recognized case is an error */ 1025 upd_cmd = I40E_NVMUPD_INVALID; 1026 1027 transaction = i40e_nvmupd_get_transaction(cmd->config); 1028 module = i40e_nvmupd_get_module(cmd->config); 1029 1030 /* limits on data size */ 1031 if ((cmd->data_size < 1) || 1032 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 1033 i40e_debug(hw, I40E_DEBUG_NVM, 1034 "i40e_nvmupd_validate_command data_size %d\n", 1035 cmd->data_size); 1036 *perrno = -EFAULT; 1037 return I40E_NVMUPD_INVALID; 1038 } 1039 1040 switch (cmd->command) { 1041 case I40E_NVM_READ: 1042 switch (transaction) { 1043 case I40E_NVM_CON: 1044 upd_cmd = I40E_NVMUPD_READ_CON; 1045 break; 1046 case I40E_NVM_SNT: 1047 upd_cmd = I40E_NVMUPD_READ_SNT; 1048 break; 1049 case I40E_NVM_LCB: 1050 upd_cmd = I40E_NVMUPD_READ_LCB; 1051 break; 1052 case I40E_NVM_SA: 1053 upd_cmd = I40E_NVMUPD_READ_SA; 1054 break; 1055 case I40E_NVM_EXEC: 1056 if (module == 0xf) 1057 upd_cmd = I40E_NVMUPD_STATUS; 1058 else if (module == 0) 1059 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; 1060 break; 1061 } 1062 break; 1063 1064 case I40E_NVM_WRITE: 1065 switch (transaction) { 1066 case I40E_NVM_CON: 1067 upd_cmd = I40E_NVMUPD_WRITE_CON; 1068 break; 1069 case I40E_NVM_SNT: 1070 upd_cmd = I40E_NVMUPD_WRITE_SNT; 1071 break; 1072 case I40E_NVM_LCB: 1073 upd_cmd = I40E_NVMUPD_WRITE_LCB; 1074 break; 1075 case I40E_NVM_SA: 1076 upd_cmd = I40E_NVMUPD_WRITE_SA; 1077 break; 1078 case I40E_NVM_ERA: 1079 upd_cmd = I40E_NVMUPD_WRITE_ERA; 1080 break; 1081 case I40E_NVM_CSUM: 1082 upd_cmd = I40E_NVMUPD_CSUM_CON; 1083 break; 1084 case (I40E_NVM_CSUM|I40E_NVM_SA): 1085 upd_cmd = I40E_NVMUPD_CSUM_SA; 1086 break; 1087 case (I40E_NVM_CSUM|I40E_NVM_LCB): 1088 upd_cmd = I40E_NVMUPD_CSUM_LCB; 1089 break; 1090 case I40E_NVM_EXEC: 1091 if (module == 0) 1092 upd_cmd = I40E_NVMUPD_EXEC_AQ; 1093 break; 1094 } 1095 break; 1096 } 1097 1098 return upd_cmd; 1099 } 1100 1101 /** 1102 * i40e_nvmupd_exec_aq - Run an AQ command 1103 * @hw: pointer to hardware structure 1104 * @cmd: pointer to nvm update command buffer 1105 * @bytes: pointer to the data buffer 1106 * @perrno: pointer to return error code 1107 * 1108 * cmd structure contains identifiers and data buffer 1109 **/ 1110 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 1111 struct i40e_nvm_access *cmd, 1112 u8 *bytes, int *perrno) 1113 { 1114 struct i40e_asq_cmd_details cmd_details; 1115 i40e_status status; 1116 struct i40e_aq_desc *aq_desc; 1117 u32 buff_size = 0; 1118 u8 *buff = NULL; 1119 u32 aq_desc_len; 1120 u32 aq_data_len; 1121 1122 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1123 memset(&cmd_details, 0, sizeof(cmd_details)); 1124 cmd_details.wb_desc = &hw->nvm_wb_desc; 1125 1126 aq_desc_len = sizeof(struct i40e_aq_desc); 1127 memset(&hw->nvm_wb_desc, 0, aq_desc_len); 1128 1129 /* get the aq descriptor */ 1130 if (cmd->data_size < aq_desc_len) { 1131 i40e_debug(hw, I40E_DEBUG_NVM, 1132 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n", 1133 cmd->data_size, aq_desc_len); 1134 *perrno = -EINVAL; 1135 return I40E_ERR_PARAM; 1136 } 1137 aq_desc = (struct i40e_aq_desc *)bytes; 1138 1139 /* if data buffer needed, make sure it's ready */ 1140 aq_data_len = cmd->data_size - aq_desc_len; 1141 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen)); 1142 if (buff_size) { 1143 if (!hw->nvm_buff.va) { 1144 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, 1145 hw->aq.asq_buf_size); 1146 if (status) 1147 i40e_debug(hw, I40E_DEBUG_NVM, 1148 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n", 1149 status); 1150 } 1151 1152 if (hw->nvm_buff.va) { 1153 buff = hw->nvm_buff.va; 1154 memcpy(buff, &bytes[aq_desc_len], aq_data_len); 1155 } 1156 } 1157 1158 /* and away we go! */ 1159 status = i40e_asq_send_command(hw, aq_desc, buff, 1160 buff_size, &cmd_details); 1161 if (status) { 1162 i40e_debug(hw, I40E_DEBUG_NVM, 1163 "i40e_nvmupd_exec_aq err %s aq_err %s\n", 1164 i40e_stat_str(hw, status), 1165 i40e_aq_str(hw, hw->aq.asq_last_status)); 1166 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1167 } 1168 1169 return status; 1170 } 1171 1172 /** 1173 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq 1174 * @hw: pointer to hardware structure 1175 * @cmd: pointer to nvm update command buffer 1176 * @bytes: pointer to the data buffer 1177 * @perrno: pointer to return error code 1178 * 1179 * cmd structure contains identifiers and data buffer 1180 **/ 1181 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 1182 struct i40e_nvm_access *cmd, 1183 u8 *bytes, int *perrno) 1184 { 1185 u32 aq_total_len; 1186 u32 aq_desc_len; 1187 int remainder; 1188 u8 *buff; 1189 1190 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1191 1192 aq_desc_len = sizeof(struct i40e_aq_desc); 1193 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); 1194 1195 /* check offset range */ 1196 if (cmd->offset > aq_total_len) { 1197 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n", 1198 __func__, cmd->offset, aq_total_len); 1199 *perrno = -EINVAL; 1200 return I40E_ERR_PARAM; 1201 } 1202 1203 /* check copylength range */ 1204 if (cmd->data_size > (aq_total_len - cmd->offset)) { 1205 int new_len = aq_total_len - cmd->offset; 1206 1207 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n", 1208 __func__, cmd->data_size, new_len); 1209 cmd->data_size = new_len; 1210 } 1211 1212 remainder = cmd->data_size; 1213 if (cmd->offset < aq_desc_len) { 1214 u32 len = aq_desc_len - cmd->offset; 1215 1216 len = min(len, cmd->data_size); 1217 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n", 1218 __func__, cmd->offset, cmd->offset + len); 1219 1220 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; 1221 memcpy(bytes, buff, len); 1222 1223 bytes += len; 1224 remainder -= len; 1225 buff = hw->nvm_buff.va; 1226 } else { 1227 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len); 1228 } 1229 1230 if (remainder > 0) { 1231 int start_byte = buff - (u8 *)hw->nvm_buff.va; 1232 1233 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", 1234 __func__, start_byte, start_byte + remainder); 1235 memcpy(bytes, buff, remainder); 1236 } 1237 1238 return 0; 1239 } 1240 1241 /** 1242 * i40e_nvmupd_nvm_read - Read NVM 1243 * @hw: pointer to hardware structure 1244 * @cmd: pointer to nvm update command buffer 1245 * @bytes: pointer to the data buffer 1246 * @perrno: pointer to return error code 1247 * 1248 * cmd structure contains identifiers and data buffer 1249 **/ 1250 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1251 struct i40e_nvm_access *cmd, 1252 u8 *bytes, int *perrno) 1253 { 1254 struct i40e_asq_cmd_details cmd_details; 1255 i40e_status status; 1256 u8 module, transaction; 1257 bool last; 1258 1259 transaction = i40e_nvmupd_get_transaction(cmd->config); 1260 module = i40e_nvmupd_get_module(cmd->config); 1261 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1262 1263 memset(&cmd_details, 0, sizeof(cmd_details)); 1264 cmd_details.wb_desc = &hw->nvm_wb_desc; 1265 1266 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1267 bytes, last, &cmd_details); 1268 if (status) { 1269 i40e_debug(hw, I40E_DEBUG_NVM, 1270 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 1271 module, cmd->offset, cmd->data_size); 1272 i40e_debug(hw, I40E_DEBUG_NVM, 1273 "i40e_nvmupd_nvm_read status %d aq %d\n", 1274 status, hw->aq.asq_last_status); 1275 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1276 } 1277 1278 return status; 1279 } 1280 1281 /** 1282 * i40e_nvmupd_nvm_erase - Erase an NVM module 1283 * @hw: pointer to hardware structure 1284 * @cmd: pointer to nvm update command buffer 1285 * @perrno: pointer to return error code 1286 * 1287 * module, offset, data_size and data are in cmd structure 1288 **/ 1289 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1290 struct i40e_nvm_access *cmd, 1291 int *perrno) 1292 { 1293 i40e_status status = 0; 1294 struct i40e_asq_cmd_details cmd_details; 1295 u8 module, transaction; 1296 bool last; 1297 1298 transaction = i40e_nvmupd_get_transaction(cmd->config); 1299 module = i40e_nvmupd_get_module(cmd->config); 1300 last = (transaction & I40E_NVM_LCB); 1301 1302 memset(&cmd_details, 0, sizeof(cmd_details)); 1303 cmd_details.wb_desc = &hw->nvm_wb_desc; 1304 1305 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 1306 last, &cmd_details); 1307 if (status) { 1308 i40e_debug(hw, I40E_DEBUG_NVM, 1309 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 1310 module, cmd->offset, cmd->data_size); 1311 i40e_debug(hw, I40E_DEBUG_NVM, 1312 "i40e_nvmupd_nvm_erase status %d aq %d\n", 1313 status, hw->aq.asq_last_status); 1314 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1315 } 1316 1317 return status; 1318 } 1319 1320 /** 1321 * i40e_nvmupd_nvm_write - Write NVM 1322 * @hw: pointer to hardware structure 1323 * @cmd: pointer to nvm update command buffer 1324 * @bytes: pointer to the data buffer 1325 * @perrno: pointer to return error code 1326 * 1327 * module, offset, data_size and data are in cmd structure 1328 **/ 1329 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1330 struct i40e_nvm_access *cmd, 1331 u8 *bytes, int *perrno) 1332 { 1333 i40e_status status = 0; 1334 struct i40e_asq_cmd_details cmd_details; 1335 u8 module, transaction; 1336 bool last; 1337 1338 transaction = i40e_nvmupd_get_transaction(cmd->config); 1339 module = i40e_nvmupd_get_module(cmd->config); 1340 last = (transaction & I40E_NVM_LCB); 1341 1342 memset(&cmd_details, 0, sizeof(cmd_details)); 1343 cmd_details.wb_desc = &hw->nvm_wb_desc; 1344 1345 status = i40e_aq_update_nvm(hw, module, cmd->offset, 1346 (u16)cmd->data_size, bytes, last, 1347 &cmd_details); 1348 if (status) { 1349 i40e_debug(hw, I40E_DEBUG_NVM, 1350 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 1351 module, cmd->offset, cmd->data_size); 1352 i40e_debug(hw, I40E_DEBUG_NVM, 1353 "i40e_nvmupd_nvm_write status %d aq %d\n", 1354 status, hw->aq.asq_last_status); 1355 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1356 } 1357 1358 return status; 1359 } 1360