156a62fc8SJesse Brandeburg /******************************************************************************* 256a62fc8SJesse Brandeburg * 356a62fc8SJesse Brandeburg * Intel Ethernet Controller XL710 Family Linux Driver 4dc641b73SGreg Rose * Copyright(c) 2013 - 2014 Intel Corporation. 556a62fc8SJesse Brandeburg * 656a62fc8SJesse Brandeburg * This program is free software; you can redistribute it and/or modify it 756a62fc8SJesse Brandeburg * under the terms and conditions of the GNU General Public License, 856a62fc8SJesse Brandeburg * version 2, as published by the Free Software Foundation. 956a62fc8SJesse Brandeburg * 1056a62fc8SJesse Brandeburg * This program is distributed in the hope it will be useful, but WITHOUT 1156a62fc8SJesse Brandeburg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1256a62fc8SJesse Brandeburg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1356a62fc8SJesse Brandeburg * more details. 1456a62fc8SJesse Brandeburg * 15dc641b73SGreg Rose * You should have received a copy of the GNU General Public License along 16dc641b73SGreg Rose * with this program. If not, see <http://www.gnu.org/licenses/>. 1756a62fc8SJesse Brandeburg * 1856a62fc8SJesse Brandeburg * The full GNU General Public License is included in this distribution in 1956a62fc8SJesse Brandeburg * the file called "COPYING". 2056a62fc8SJesse Brandeburg * 2156a62fc8SJesse Brandeburg * Contact Information: 2256a62fc8SJesse Brandeburg * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 2356a62fc8SJesse Brandeburg * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 2456a62fc8SJesse Brandeburg * 2556a62fc8SJesse Brandeburg ******************************************************************************/ 2656a62fc8SJesse Brandeburg 2756a62fc8SJesse Brandeburg #include "i40e_prototype.h" 2856a62fc8SJesse Brandeburg 2956a62fc8SJesse Brandeburg /** 303e26186dSShannon Nelson * i40e_init_nvm_ops - Initialize NVM function pointers 313e26186dSShannon Nelson * @hw: pointer to the HW structure 3256a62fc8SJesse Brandeburg * 333e26186dSShannon Nelson * Setup the function pointers and the NVM info structure. Should be called 3456a62fc8SJesse Brandeburg * once per NVM initialization, e.g. inside the i40e_init_shared_code(). 3556a62fc8SJesse Brandeburg * Please notice that the NVM term is used here (& in all methods covered 3656a62fc8SJesse Brandeburg * in this file) as an equivalent of the FLASH part mapped into the SR. 3756a62fc8SJesse Brandeburg * We are accessing FLASH always thru the Shadow RAM. 3856a62fc8SJesse Brandeburg **/ 3956a62fc8SJesse Brandeburg i40e_status i40e_init_nvm(struct i40e_hw *hw) 4056a62fc8SJesse Brandeburg { 4156a62fc8SJesse Brandeburg struct i40e_nvm_info *nvm = &hw->nvm; 4256a62fc8SJesse Brandeburg i40e_status ret_code = 0; 4356a62fc8SJesse Brandeburg u32 fla, gens; 4456a62fc8SJesse Brandeburg u8 sr_size; 4556a62fc8SJesse Brandeburg 4656a62fc8SJesse Brandeburg /* The SR size is stored regardless of the nvm programming mode 4756a62fc8SJesse Brandeburg * as the blank mode may be used in the factory line. 4856a62fc8SJesse Brandeburg */ 4956a62fc8SJesse Brandeburg gens = rd32(hw, I40E_GLNVM_GENS); 5056a62fc8SJesse Brandeburg sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> 5156a62fc8SJesse Brandeburg I40E_GLNVM_GENS_SR_SIZE_SHIFT); 523e26186dSShannon Nelson /* Switching to words (sr_size contains power of 2KB) */ 5341a1d04bSJesse Brandeburg nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; 5456a62fc8SJesse Brandeburg 553e26186dSShannon Nelson /* Check if we are in the normal or blank NVM programming mode */ 5656a62fc8SJesse Brandeburg fla = rd32(hw, I40E_GLNVM_FLA); 573e26186dSShannon Nelson if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */ 583e26186dSShannon Nelson /* Max NVM timeout */ 5956a62fc8SJesse Brandeburg nvm->timeout = I40E_MAX_NVM_TIMEOUT; 6056a62fc8SJesse Brandeburg nvm->blank_nvm_mode = false; 613e26186dSShannon Nelson } else { /* Blank programming mode */ 6256a62fc8SJesse Brandeburg nvm->blank_nvm_mode = true; 6356a62fc8SJesse Brandeburg ret_code = I40E_ERR_NVM_BLANK_MODE; 6474d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n"); 6556a62fc8SJesse Brandeburg } 6656a62fc8SJesse Brandeburg 6756a62fc8SJesse Brandeburg return ret_code; 6856a62fc8SJesse Brandeburg } 6956a62fc8SJesse Brandeburg 7056a62fc8SJesse Brandeburg /** 713e26186dSShannon Nelson * i40e_acquire_nvm - Generic request for acquiring the NVM ownership 723e26186dSShannon Nelson * @hw: pointer to the HW structure 733e26186dSShannon Nelson * @access: NVM access type (read or write) 7456a62fc8SJesse Brandeburg * 7556a62fc8SJesse Brandeburg * This function will request NVM ownership for reading 7656a62fc8SJesse Brandeburg * via the proper Admin Command. 7756a62fc8SJesse Brandeburg **/ 7856a62fc8SJesse Brandeburg i40e_status i40e_acquire_nvm(struct i40e_hw *hw, 7956a62fc8SJesse Brandeburg enum i40e_aq_resource_access_type access) 8056a62fc8SJesse Brandeburg { 8156a62fc8SJesse Brandeburg i40e_status ret_code = 0; 8256a62fc8SJesse Brandeburg u64 gtime, timeout; 83c509c1deSShannon Nelson u64 time_left = 0; 8456a62fc8SJesse Brandeburg 8556a62fc8SJesse Brandeburg if (hw->nvm.blank_nvm_mode) 8656a62fc8SJesse Brandeburg goto i40e_i40e_acquire_nvm_exit; 8756a62fc8SJesse Brandeburg 8856a62fc8SJesse Brandeburg ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, 89c509c1deSShannon Nelson 0, &time_left, NULL); 903e26186dSShannon Nelson /* Reading the Global Device Timer */ 9156a62fc8SJesse Brandeburg gtime = rd32(hw, I40E_GLVFGEN_TIMER); 9256a62fc8SJesse Brandeburg 933e26186dSShannon Nelson /* Store the timeout */ 94c509c1deSShannon Nelson hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; 9556a62fc8SJesse Brandeburg 96a3f0b381SShannon Nelson if (ret_code) 97a3f0b381SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 98a3f0b381SShannon Nelson "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n", 99a3f0b381SShannon Nelson access, time_left, ret_code, hw->aq.asq_last_status); 100a3f0b381SShannon Nelson 101a3f0b381SShannon Nelson if (ret_code && time_left) { 1023e26186dSShannon Nelson /* Poll until the current NVM owner timeouts */ 103c509c1deSShannon Nelson timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime; 104a3f0b381SShannon Nelson while ((gtime < timeout) && time_left) { 10556a62fc8SJesse Brandeburg usleep_range(10000, 20000); 106c509c1deSShannon Nelson gtime = rd32(hw, I40E_GLVFGEN_TIMER); 10756a62fc8SJesse Brandeburg ret_code = i40e_aq_request_resource(hw, 10856a62fc8SJesse Brandeburg I40E_NVM_RESOURCE_ID, 109c509c1deSShannon Nelson access, 0, &time_left, 11056a62fc8SJesse Brandeburg NULL); 11156a62fc8SJesse Brandeburg if (!ret_code) { 11256a62fc8SJesse Brandeburg hw->nvm.hw_semaphore_timeout = 113c509c1deSShannon Nelson I40E_MS_TO_GTIME(time_left) + gtime; 11456a62fc8SJesse Brandeburg break; 11556a62fc8SJesse Brandeburg } 11656a62fc8SJesse Brandeburg } 11756a62fc8SJesse Brandeburg if (ret_code) { 11856a62fc8SJesse Brandeburg hw->nvm.hw_semaphore_timeout = 0; 11974d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 120a3f0b381SShannon Nelson "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n", 121a3f0b381SShannon Nelson time_left, ret_code, hw->aq.asq_last_status); 12256a62fc8SJesse Brandeburg } 12356a62fc8SJesse Brandeburg } 12456a62fc8SJesse Brandeburg 12556a62fc8SJesse Brandeburg i40e_i40e_acquire_nvm_exit: 12656a62fc8SJesse Brandeburg return ret_code; 12756a62fc8SJesse Brandeburg } 12856a62fc8SJesse Brandeburg 12956a62fc8SJesse Brandeburg /** 1303e26186dSShannon Nelson * i40e_release_nvm - Generic request for releasing the NVM ownership 1313e26186dSShannon Nelson * @hw: pointer to the HW structure 13256a62fc8SJesse Brandeburg * 13356a62fc8SJesse Brandeburg * This function will release NVM resource via the proper Admin Command. 13456a62fc8SJesse Brandeburg **/ 13556a62fc8SJesse Brandeburg void i40e_release_nvm(struct i40e_hw *hw) 13656a62fc8SJesse Brandeburg { 13756a62fc8SJesse Brandeburg if (!hw->nvm.blank_nvm_mode) 13856a62fc8SJesse Brandeburg i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 13956a62fc8SJesse Brandeburg } 14056a62fc8SJesse Brandeburg 14156a62fc8SJesse Brandeburg /** 1423e26186dSShannon Nelson * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit 1433e26186dSShannon Nelson * @hw: pointer to the HW structure 14456a62fc8SJesse Brandeburg * 14556a62fc8SJesse Brandeburg * Polls the SRCTL Shadow RAM register done bit. 14656a62fc8SJesse Brandeburg **/ 14756a62fc8SJesse Brandeburg static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) 14856a62fc8SJesse Brandeburg { 14956a62fc8SJesse Brandeburg i40e_status ret_code = I40E_ERR_TIMEOUT; 15056a62fc8SJesse Brandeburg u32 srctl, wait_cnt; 15156a62fc8SJesse Brandeburg 1523e26186dSShannon Nelson /* Poll the I40E_GLNVM_SRCTL until the done bit is set */ 15356a62fc8SJesse Brandeburg for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { 15456a62fc8SJesse Brandeburg srctl = rd32(hw, I40E_GLNVM_SRCTL); 15556a62fc8SJesse Brandeburg if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { 15656a62fc8SJesse Brandeburg ret_code = 0; 15756a62fc8SJesse Brandeburg break; 15856a62fc8SJesse Brandeburg } 15956a62fc8SJesse Brandeburg udelay(5); 16056a62fc8SJesse Brandeburg } 16156a62fc8SJesse Brandeburg if (ret_code == I40E_ERR_TIMEOUT) 16274d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); 16356a62fc8SJesse Brandeburg return ret_code; 16456a62fc8SJesse Brandeburg } 16556a62fc8SJesse Brandeburg 16656a62fc8SJesse Brandeburg /** 167d1bbe0eaSKamil Krawczyk * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register 1683e26186dSShannon Nelson * @hw: pointer to the HW structure 1693e26186dSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 1703e26186dSShannon Nelson * @data: word read from the Shadow RAM 17156a62fc8SJesse Brandeburg * 1723e26186dSShannon Nelson * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 17356a62fc8SJesse Brandeburg **/ 17437a2973aSShannon Nelson static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, 17556a62fc8SJesse Brandeburg u16 *data) 17656a62fc8SJesse Brandeburg { 17756a62fc8SJesse Brandeburg i40e_status ret_code = I40E_ERR_TIMEOUT; 17856a62fc8SJesse Brandeburg u32 sr_reg; 17956a62fc8SJesse Brandeburg 18056a62fc8SJesse Brandeburg if (offset >= hw->nvm.sr_size) { 18174d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 18274d0d0edSShannon Nelson "NVM read error: offset %d beyond Shadow RAM limit %d\n", 18374d0d0edSShannon Nelson offset, hw->nvm.sr_size); 18456a62fc8SJesse Brandeburg ret_code = I40E_ERR_PARAM; 18556a62fc8SJesse Brandeburg goto read_nvm_exit; 18656a62fc8SJesse Brandeburg } 18756a62fc8SJesse Brandeburg 1883e26186dSShannon Nelson /* Poll the done bit first */ 18956a62fc8SJesse Brandeburg ret_code = i40e_poll_sr_srctl_done_bit(hw); 19056a62fc8SJesse Brandeburg if (!ret_code) { 1913e26186dSShannon Nelson /* Write the address and start reading */ 19241a1d04bSJesse Brandeburg sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | 19341a1d04bSJesse Brandeburg BIT(I40E_GLNVM_SRCTL_START_SHIFT); 19456a62fc8SJesse Brandeburg wr32(hw, I40E_GLNVM_SRCTL, sr_reg); 19556a62fc8SJesse Brandeburg 1963e26186dSShannon Nelson /* Poll I40E_GLNVM_SRCTL until the done bit is set */ 19756a62fc8SJesse Brandeburg ret_code = i40e_poll_sr_srctl_done_bit(hw); 19856a62fc8SJesse Brandeburg if (!ret_code) { 19956a62fc8SJesse Brandeburg sr_reg = rd32(hw, I40E_GLNVM_SRDATA); 20056a62fc8SJesse Brandeburg *data = (u16)((sr_reg & 20156a62fc8SJesse Brandeburg I40E_GLNVM_SRDATA_RDDATA_MASK) 20256a62fc8SJesse Brandeburg >> I40E_GLNVM_SRDATA_RDDATA_SHIFT); 20356a62fc8SJesse Brandeburg } 20456a62fc8SJesse Brandeburg } 20556a62fc8SJesse Brandeburg if (ret_code) 20674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 20774d0d0edSShannon Nelson "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", 20856a62fc8SJesse Brandeburg offset); 20956a62fc8SJesse Brandeburg 21056a62fc8SJesse Brandeburg read_nvm_exit: 21156a62fc8SJesse Brandeburg return ret_code; 21256a62fc8SJesse Brandeburg } 21356a62fc8SJesse Brandeburg 21456a62fc8SJesse Brandeburg /** 2157073f46eSShannon Nelson * i40e_read_nvm_aq - Read Shadow RAM. 2167073f46eSShannon Nelson * @hw: pointer to the HW structure. 2177073f46eSShannon Nelson * @module_pointer: module pointer location in words from the NVM beginning 2187073f46eSShannon Nelson * @offset: offset in words from module start 2197073f46eSShannon Nelson * @words: number of words to write 2207073f46eSShannon Nelson * @data: buffer with words to write to the Shadow RAM 2217073f46eSShannon Nelson * @last_command: tells the AdminQ that this is the last command 2227073f46eSShannon Nelson * 2237073f46eSShannon Nelson * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 2247073f46eSShannon Nelson **/ 2257073f46eSShannon Nelson static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 2267073f46eSShannon Nelson u32 offset, u16 words, void *data, 2277073f46eSShannon Nelson bool last_command) 2287073f46eSShannon Nelson { 2297073f46eSShannon Nelson i40e_status ret_code = I40E_ERR_NVM; 2307073f46eSShannon Nelson struct i40e_asq_cmd_details cmd_details; 2317073f46eSShannon Nelson 2327073f46eSShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 2337073f46eSShannon Nelson 2347073f46eSShannon Nelson /* Here we are checking the SR limit only for the flat memory model. 2357073f46eSShannon Nelson * We cannot do it for the module-based model, as we did not acquire 2367073f46eSShannon Nelson * the NVM resource yet (we cannot get the module pointer value). 2377073f46eSShannon Nelson * Firmware will check the module-based model. 2387073f46eSShannon Nelson */ 2397073f46eSShannon Nelson if ((offset + words) > hw->nvm.sr_size) 2407073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 2417073f46eSShannon Nelson "NVM write error: offset %d beyond Shadow RAM limit %d\n", 2427073f46eSShannon Nelson (offset + words), hw->nvm.sr_size); 2437073f46eSShannon Nelson else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 2447073f46eSShannon Nelson /* We can write only up to 4KB (one sector), in one AQ write */ 2457073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 2467073f46eSShannon Nelson "NVM write fail error: tried to write %d words, limit is %d.\n", 2477073f46eSShannon Nelson words, I40E_SR_SECTOR_SIZE_IN_WORDS); 2487073f46eSShannon Nelson else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 2497073f46eSShannon Nelson != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 2507073f46eSShannon Nelson /* A single write cannot spread over two sectors */ 2517073f46eSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 2527073f46eSShannon Nelson "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 2537073f46eSShannon Nelson offset, words); 2547073f46eSShannon Nelson else 2557073f46eSShannon Nelson ret_code = i40e_aq_read_nvm(hw, module_pointer, 2567073f46eSShannon Nelson 2 * offset, /*bytes*/ 2577073f46eSShannon Nelson 2 * words, /*bytes*/ 2587073f46eSShannon Nelson data, last_command, &cmd_details); 2597073f46eSShannon Nelson 2607073f46eSShannon Nelson return ret_code; 2617073f46eSShannon Nelson } 2627073f46eSShannon Nelson 2637073f46eSShannon Nelson /** 2647073f46eSShannon Nelson * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ 2657073f46eSShannon Nelson * @hw: pointer to the HW structure 2667073f46eSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 2677073f46eSShannon Nelson * @data: word read from the Shadow RAM 2687073f46eSShannon Nelson * 2697073f46eSShannon Nelson * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 2707073f46eSShannon Nelson **/ 2717073f46eSShannon Nelson static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, 2727073f46eSShannon Nelson u16 *data) 2737073f46eSShannon Nelson { 2747073f46eSShannon Nelson i40e_status ret_code = I40E_ERR_TIMEOUT; 2757073f46eSShannon Nelson 2767073f46eSShannon Nelson ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true); 2777073f46eSShannon Nelson *data = le16_to_cpu(*(__le16 *)data); 2787073f46eSShannon Nelson 2797073f46eSShannon Nelson return ret_code; 2807073f46eSShannon Nelson } 2817073f46eSShannon Nelson 2827073f46eSShannon Nelson /** 283d1bbe0eaSKamil Krawczyk * i40e_read_nvm_word - Reads Shadow RAM 284d1bbe0eaSKamil Krawczyk * @hw: pointer to the HW structure 285d1bbe0eaSKamil Krawczyk * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 286d1bbe0eaSKamil Krawczyk * @data: word read from the Shadow RAM 287d1bbe0eaSKamil Krawczyk * 288d1bbe0eaSKamil Krawczyk * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. 289d1bbe0eaSKamil Krawczyk **/ 290d1bbe0eaSKamil Krawczyk i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, 291d1bbe0eaSKamil Krawczyk u16 *data) 292d1bbe0eaSKamil Krawczyk { 29307f89be8SAnjali Singhai enum i40e_status_code ret_code = 0; 29407f89be8SAnjali Singhai 29507f89be8SAnjali Singhai if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { 29607f89be8SAnjali Singhai ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 29707f89be8SAnjali Singhai if (!ret_code) { 29807f89be8SAnjali Singhai ret_code = i40e_read_nvm_word_aq(hw, offset, data); 29907f89be8SAnjali Singhai i40e_release_nvm(hw); 30007f89be8SAnjali Singhai } 30107f89be8SAnjali Singhai } else { 30207f89be8SAnjali Singhai ret_code = i40e_read_nvm_word_srctl(hw, offset, data); 30307f89be8SAnjali Singhai } 30407f89be8SAnjali Singhai return ret_code; 305d1bbe0eaSKamil Krawczyk } 306d1bbe0eaSKamil Krawczyk 307d1bbe0eaSKamil Krawczyk /** 308d1bbe0eaSKamil Krawczyk * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register 309d1bbe0eaSKamil Krawczyk * @hw: pointer to the HW structure 310d1bbe0eaSKamil Krawczyk * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 311d1bbe0eaSKamil Krawczyk * @words: (in) number of words to read; (out) number of words actually read 312d1bbe0eaSKamil Krawczyk * @data: words read from the Shadow RAM 313d1bbe0eaSKamil Krawczyk * 314d1bbe0eaSKamil Krawczyk * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 315d1bbe0eaSKamil Krawczyk * method. The buffer read is preceded by the NVM ownership take 316d1bbe0eaSKamil Krawczyk * and followed by the release. 317d1bbe0eaSKamil Krawczyk **/ 31837a2973aSShannon Nelson static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, 319d1bbe0eaSKamil Krawczyk u16 *words, u16 *data) 320d1bbe0eaSKamil Krawczyk { 321d1bbe0eaSKamil Krawczyk i40e_status ret_code = 0; 322d1bbe0eaSKamil Krawczyk u16 index, word; 323d1bbe0eaSKamil Krawczyk 324d1bbe0eaSKamil Krawczyk /* Loop thru the selected region */ 325d1bbe0eaSKamil Krawczyk for (word = 0; word < *words; word++) { 326d1bbe0eaSKamil Krawczyk index = offset + word; 327d1bbe0eaSKamil Krawczyk ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]); 328d1bbe0eaSKamil Krawczyk if (ret_code) 329d1bbe0eaSKamil Krawczyk break; 330d1bbe0eaSKamil Krawczyk } 331d1bbe0eaSKamil Krawczyk 332d1bbe0eaSKamil Krawczyk /* Update the number of words read from the Shadow RAM */ 333d1bbe0eaSKamil Krawczyk *words = word; 334d1bbe0eaSKamil Krawczyk 335d1bbe0eaSKamil Krawczyk return ret_code; 336d1bbe0eaSKamil Krawczyk } 337d1bbe0eaSKamil Krawczyk 338d1bbe0eaSKamil Krawczyk /** 3397073f46eSShannon Nelson * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ 3407073f46eSShannon Nelson * @hw: pointer to the HW structure 3417073f46eSShannon Nelson * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 3427073f46eSShannon Nelson * @words: (in) number of words to read; (out) number of words actually read 3437073f46eSShannon Nelson * @data: words read from the Shadow RAM 3447073f46eSShannon Nelson * 3457073f46eSShannon Nelson * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() 3467073f46eSShannon Nelson * method. The buffer read is preceded by the NVM ownership take 3477073f46eSShannon Nelson * and followed by the release. 3487073f46eSShannon Nelson **/ 3497073f46eSShannon Nelson static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, 3507073f46eSShannon Nelson u16 *words, u16 *data) 3517073f46eSShannon Nelson { 3527073f46eSShannon Nelson i40e_status ret_code; 3537073f46eSShannon Nelson u16 read_size = *words; 3547073f46eSShannon Nelson bool last_cmd = false; 3557073f46eSShannon Nelson u16 words_read = 0; 3567073f46eSShannon Nelson u16 i = 0; 3577073f46eSShannon Nelson 3587073f46eSShannon Nelson do { 3597073f46eSShannon Nelson /* Calculate number of bytes we should read in this step. 3607073f46eSShannon Nelson * FVL AQ do not allow to read more than one page at a time or 3617073f46eSShannon Nelson * to cross page boundaries. 3627073f46eSShannon Nelson */ 3637073f46eSShannon Nelson if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS) 3647073f46eSShannon Nelson read_size = min(*words, 3657073f46eSShannon Nelson (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - 3667073f46eSShannon Nelson (offset % I40E_SR_SECTOR_SIZE_IN_WORDS))); 3677073f46eSShannon Nelson else 3687073f46eSShannon Nelson read_size = min((*words - words_read), 3697073f46eSShannon Nelson I40E_SR_SECTOR_SIZE_IN_WORDS); 3707073f46eSShannon Nelson 3717073f46eSShannon Nelson /* Check if this is last command, if so set proper flag */ 3727073f46eSShannon Nelson if ((words_read + read_size) >= *words) 3737073f46eSShannon Nelson last_cmd = true; 3747073f46eSShannon Nelson 3757073f46eSShannon Nelson ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size, 3767073f46eSShannon Nelson data + words_read, last_cmd); 3777073f46eSShannon Nelson if (ret_code) 3787073f46eSShannon Nelson goto read_nvm_buffer_aq_exit; 3797073f46eSShannon Nelson 3807073f46eSShannon Nelson /* Increment counter for words already read and move offset to 3817073f46eSShannon Nelson * new read location 3827073f46eSShannon Nelson */ 3837073f46eSShannon Nelson words_read += read_size; 3847073f46eSShannon Nelson offset += read_size; 3857073f46eSShannon Nelson } while (words_read < *words); 3867073f46eSShannon Nelson 3877073f46eSShannon Nelson for (i = 0; i < *words; i++) 3887073f46eSShannon Nelson data[i] = le16_to_cpu(((__le16 *)data)[i]); 3897073f46eSShannon Nelson 3907073f46eSShannon Nelson read_nvm_buffer_aq_exit: 3917073f46eSShannon Nelson *words = words_read; 3927073f46eSShannon Nelson return ret_code; 3937073f46eSShannon Nelson } 3947073f46eSShannon Nelson 3957073f46eSShannon Nelson /** 3963e26186dSShannon Nelson * i40e_read_nvm_buffer - Reads Shadow RAM buffer 3973e26186dSShannon Nelson * @hw: pointer to the HW structure 39856a62fc8SJesse Brandeburg * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). 3993e26186dSShannon Nelson * @words: (in) number of words to read; (out) number of words actually read 4003e26186dSShannon Nelson * @data: words read from the Shadow RAM 40156a62fc8SJesse Brandeburg * 40256a62fc8SJesse Brandeburg * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() 40356a62fc8SJesse Brandeburg * method. The buffer read is preceded by the NVM ownership take 40456a62fc8SJesse Brandeburg * and followed by the release. 40556a62fc8SJesse Brandeburg **/ 40656a62fc8SJesse Brandeburg i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, 40756a62fc8SJesse Brandeburg u16 *words, u16 *data) 40856a62fc8SJesse Brandeburg { 40907f89be8SAnjali Singhai enum i40e_status_code ret_code = 0; 41007f89be8SAnjali Singhai 41107f89be8SAnjali Singhai if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { 41207f89be8SAnjali Singhai ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 41307f89be8SAnjali Singhai if (!ret_code) { 41407f89be8SAnjali Singhai ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, 41507f89be8SAnjali Singhai data); 41607f89be8SAnjali Singhai i40e_release_nvm(hw); 41707f89be8SAnjali Singhai } 41807f89be8SAnjali Singhai } else { 41907f89be8SAnjali Singhai ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); 42007f89be8SAnjali Singhai } 42107f89be8SAnjali Singhai return ret_code; 42256a62fc8SJesse Brandeburg } 42356a62fc8SJesse Brandeburg 42456a62fc8SJesse Brandeburg /** 425cd552cb4SShannon Nelson * i40e_write_nvm_aq - Writes Shadow RAM. 426cd552cb4SShannon Nelson * @hw: pointer to the HW structure. 427cd552cb4SShannon Nelson * @module_pointer: module pointer location in words from the NVM beginning 428cd552cb4SShannon Nelson * @offset: offset in words from module start 429cd552cb4SShannon Nelson * @words: number of words to write 430cd552cb4SShannon Nelson * @data: buffer with words to write to the Shadow RAM 431cd552cb4SShannon Nelson * @last_command: tells the AdminQ that this is the last command 432cd552cb4SShannon Nelson * 433cd552cb4SShannon Nelson * Writes a 16 bit words buffer to the Shadow RAM using the admin command. 434cd552cb4SShannon Nelson **/ 435952d9639SWei Yongjun static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, 436cd552cb4SShannon Nelson u32 offset, u16 words, void *data, 437cd552cb4SShannon Nelson bool last_command) 438cd552cb4SShannon Nelson { 439cd552cb4SShannon Nelson i40e_status ret_code = I40E_ERR_NVM; 4406b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details; 4416b5c1b89SShannon Nelson 4426b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 4436b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc; 444cd552cb4SShannon Nelson 445cd552cb4SShannon Nelson /* Here we are checking the SR limit only for the flat memory model. 446cd552cb4SShannon Nelson * We cannot do it for the module-based model, as we did not acquire 447cd552cb4SShannon Nelson * the NVM resource yet (we cannot get the module pointer value). 448cd552cb4SShannon Nelson * Firmware will check the module-based model. 449cd552cb4SShannon Nelson */ 450cd552cb4SShannon Nelson if ((offset + words) > hw->nvm.sr_size) 45174d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 45274d0d0edSShannon Nelson "NVM write error: offset %d beyond Shadow RAM limit %d\n", 45374d0d0edSShannon Nelson (offset + words), hw->nvm.sr_size); 454cd552cb4SShannon Nelson else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) 455cd552cb4SShannon Nelson /* We can write only up to 4KB (one sector), in one AQ write */ 45674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 45774d0d0edSShannon Nelson "NVM write fail error: tried to write %d words, limit is %d.\n", 45874d0d0edSShannon Nelson words, I40E_SR_SECTOR_SIZE_IN_WORDS); 459cd552cb4SShannon Nelson else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) 460cd552cb4SShannon Nelson != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) 461cd552cb4SShannon Nelson /* A single write cannot spread over two sectors */ 46274d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 46374d0d0edSShannon Nelson "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", 46474d0d0edSShannon Nelson offset, words); 465cd552cb4SShannon Nelson else 466cd552cb4SShannon Nelson ret_code = i40e_aq_update_nvm(hw, module_pointer, 467cd552cb4SShannon Nelson 2 * offset, /*bytes*/ 468cd552cb4SShannon Nelson 2 * words, /*bytes*/ 4696b5c1b89SShannon Nelson data, last_command, &cmd_details); 470cd552cb4SShannon Nelson 471cd552cb4SShannon Nelson return ret_code; 472cd552cb4SShannon Nelson } 473cd552cb4SShannon Nelson 474cd552cb4SShannon Nelson /** 47556a62fc8SJesse Brandeburg * i40e_calc_nvm_checksum - Calculates and returns the checksum 47656a62fc8SJesse Brandeburg * @hw: pointer to hardware structure 47798d44381SJeff Kirsher * @checksum: pointer to the checksum 47856a62fc8SJesse Brandeburg * 4793e26186dSShannon Nelson * This function calculates SW Checksum that covers the whole 64kB shadow RAM 48056a62fc8SJesse Brandeburg * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD 48156a62fc8SJesse Brandeburg * is customer specific and unknown. Therefore, this function skips all maximum 48256a62fc8SJesse Brandeburg * possible size of VPD (1kB). 48356a62fc8SJesse Brandeburg **/ 48456a62fc8SJesse Brandeburg static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, 48556a62fc8SJesse Brandeburg u16 *checksum) 48656a62fc8SJesse Brandeburg { 4870e5229c6SJean Sacren i40e_status ret_code; 488d1bbe0eaSKamil Krawczyk struct i40e_virt_mem vmem; 48956a62fc8SJesse Brandeburg u16 pcie_alt_module = 0; 49056a62fc8SJesse Brandeburg u16 checksum_local = 0; 49156a62fc8SJesse Brandeburg u16 vpd_module = 0; 492d1bbe0eaSKamil Krawczyk u16 *data; 493d1bbe0eaSKamil Krawczyk u16 i = 0; 494d1bbe0eaSKamil Krawczyk 495d1bbe0eaSKamil Krawczyk ret_code = i40e_allocate_virt_mem(hw, &vmem, 496d1bbe0eaSKamil Krawczyk I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); 497d1bbe0eaSKamil Krawczyk if (ret_code) 498d1bbe0eaSKamil Krawczyk goto i40e_calc_nvm_checksum_exit; 499d1bbe0eaSKamil Krawczyk data = (u16 *)vmem.va; 50056a62fc8SJesse Brandeburg 50156a62fc8SJesse Brandeburg /* read pointer to VPD area */ 502a4bcfbb7SShannon Nelson ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); 50356a62fc8SJesse Brandeburg if (ret_code) { 50456a62fc8SJesse Brandeburg ret_code = I40E_ERR_NVM_CHECKSUM; 50556a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit; 50656a62fc8SJesse Brandeburg } 50756a62fc8SJesse Brandeburg 50856a62fc8SJesse Brandeburg /* read pointer to PCIe Alt Auto-load module */ 509a4bcfbb7SShannon Nelson ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, 51056a62fc8SJesse Brandeburg &pcie_alt_module); 51156a62fc8SJesse Brandeburg if (ret_code) { 51256a62fc8SJesse Brandeburg ret_code = I40E_ERR_NVM_CHECKSUM; 51356a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit; 51456a62fc8SJesse Brandeburg } 51556a62fc8SJesse Brandeburg 51656a62fc8SJesse Brandeburg /* Calculate SW checksum that covers the whole 64kB shadow RAM 51756a62fc8SJesse Brandeburg * except the VPD and PCIe ALT Auto-load modules 51856a62fc8SJesse Brandeburg */ 51956a62fc8SJesse Brandeburg for (i = 0; i < hw->nvm.sr_size; i++) { 520d1bbe0eaSKamil Krawczyk /* Read SR page */ 521d1bbe0eaSKamil Krawczyk if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) { 522d1bbe0eaSKamil Krawczyk u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS; 52356a62fc8SJesse Brandeburg 524d1bbe0eaSKamil Krawczyk ret_code = i40e_read_nvm_buffer(hw, i, &words, data); 52556a62fc8SJesse Brandeburg if (ret_code) { 52656a62fc8SJesse Brandeburg ret_code = I40E_ERR_NVM_CHECKSUM; 52756a62fc8SJesse Brandeburg goto i40e_calc_nvm_checksum_exit; 52856a62fc8SJesse Brandeburg } 529d1bbe0eaSKamil Krawczyk } 530d1bbe0eaSKamil Krawczyk 531d1bbe0eaSKamil Krawczyk /* Skip Checksum word */ 532d1bbe0eaSKamil Krawczyk if (i == I40E_SR_SW_CHECKSUM_WORD) 533d1bbe0eaSKamil Krawczyk continue; 534d1bbe0eaSKamil Krawczyk /* Skip VPD module (convert byte size to word count) */ 535d1bbe0eaSKamil Krawczyk if ((i >= (u32)vpd_module) && 536d1bbe0eaSKamil Krawczyk (i < ((u32)vpd_module + 537d1bbe0eaSKamil Krawczyk (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) { 538d1bbe0eaSKamil Krawczyk continue; 539d1bbe0eaSKamil Krawczyk } 540d1bbe0eaSKamil Krawczyk /* Skip PCIe ALT module (convert byte size to word count) */ 541d1bbe0eaSKamil Krawczyk if ((i >= (u32)pcie_alt_module) && 542d1bbe0eaSKamil Krawczyk (i < ((u32)pcie_alt_module + 543d1bbe0eaSKamil Krawczyk (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) { 544d1bbe0eaSKamil Krawczyk continue; 545d1bbe0eaSKamil Krawczyk } 546d1bbe0eaSKamil Krawczyk 547d1bbe0eaSKamil Krawczyk checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS]; 54856a62fc8SJesse Brandeburg } 54956a62fc8SJesse Brandeburg 55056a62fc8SJesse Brandeburg *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; 55156a62fc8SJesse Brandeburg 55256a62fc8SJesse Brandeburg i40e_calc_nvm_checksum_exit: 553d1bbe0eaSKamil Krawczyk i40e_free_virt_mem(hw, &vmem); 55456a62fc8SJesse Brandeburg return ret_code; 55556a62fc8SJesse Brandeburg } 55656a62fc8SJesse Brandeburg 55756a62fc8SJesse Brandeburg /** 558cd552cb4SShannon Nelson * i40e_update_nvm_checksum - Updates the NVM checksum 559cd552cb4SShannon Nelson * @hw: pointer to hardware structure 560cd552cb4SShannon Nelson * 561cd552cb4SShannon Nelson * NVM ownership must be acquired before calling this function and released 562cd552cb4SShannon Nelson * on ARQ completion event reception by caller. 563cd552cb4SShannon Nelson * This function will commit SR to NVM. 564cd552cb4SShannon Nelson **/ 565cd552cb4SShannon Nelson i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw) 566cd552cb4SShannon Nelson { 5670e5229c6SJean Sacren i40e_status ret_code; 568cd552cb4SShannon Nelson u16 checksum; 569dd38c583SJesse Brandeburg __le16 le_sum; 570cd552cb4SShannon Nelson 571cd552cb4SShannon Nelson ret_code = i40e_calc_nvm_checksum(hw, &checksum); 5722fc4cd52SJean Sacren if (!ret_code) { 573dd38c583SJesse Brandeburg le_sum = cpu_to_le16(checksum); 574cd552cb4SShannon Nelson ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD, 575dd38c583SJesse Brandeburg 1, &le_sum, true); 5762fc4cd52SJean Sacren } 577cd552cb4SShannon Nelson 578cd552cb4SShannon Nelson return ret_code; 579cd552cb4SShannon Nelson } 580cd552cb4SShannon Nelson 581cd552cb4SShannon Nelson /** 58256a62fc8SJesse Brandeburg * i40e_validate_nvm_checksum - Validate EEPROM checksum 58356a62fc8SJesse Brandeburg * @hw: pointer to hardware structure 58456a62fc8SJesse Brandeburg * @checksum: calculated checksum 58556a62fc8SJesse Brandeburg * 58656a62fc8SJesse Brandeburg * Performs checksum calculation and validates the NVM SW checksum. If the 58756a62fc8SJesse Brandeburg * caller does not need checksum, the value can be NULL. 58856a62fc8SJesse Brandeburg **/ 58956a62fc8SJesse Brandeburg i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, 59056a62fc8SJesse Brandeburg u16 *checksum) 59156a62fc8SJesse Brandeburg { 59256a62fc8SJesse Brandeburg i40e_status ret_code = 0; 59356a62fc8SJesse Brandeburg u16 checksum_sr = 0; 594e15c9fa0SJesse Brandeburg u16 checksum_local = 0; 59556a62fc8SJesse Brandeburg 59656a62fc8SJesse Brandeburg ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); 59756a62fc8SJesse Brandeburg if (ret_code) 5987a208e83SKamil Krawczyk goto i40e_validate_nvm_checksum_exit; 59956a62fc8SJesse Brandeburg 60056a62fc8SJesse Brandeburg /* Do not use i40e_read_nvm_word() because we do not want to take 60156a62fc8SJesse Brandeburg * the synchronization semaphores twice here. 60256a62fc8SJesse Brandeburg */ 603a4bcfbb7SShannon Nelson i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); 60456a62fc8SJesse Brandeburg 60556a62fc8SJesse Brandeburg /* Verify read checksum from EEPROM is the same as 60656a62fc8SJesse Brandeburg * calculated checksum 60756a62fc8SJesse Brandeburg */ 60856a62fc8SJesse Brandeburg if (checksum_local != checksum_sr) 60956a62fc8SJesse Brandeburg ret_code = I40E_ERR_NVM_CHECKSUM; 61056a62fc8SJesse Brandeburg 61156a62fc8SJesse Brandeburg /* If the user cares, return the calculated checksum */ 61256a62fc8SJesse Brandeburg if (checksum) 61356a62fc8SJesse Brandeburg *checksum = checksum_local; 61456a62fc8SJesse Brandeburg 61556a62fc8SJesse Brandeburg i40e_validate_nvm_checksum_exit: 61656a62fc8SJesse Brandeburg return ret_code; 61756a62fc8SJesse Brandeburg } 618cd552cb4SShannon Nelson 619cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 620cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 62179afe839SShannon Nelson u8 *bytes, int *perrno); 622cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 623cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 62479afe839SShannon Nelson u8 *bytes, int *perrno); 625cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 626cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 627cd552cb4SShannon Nelson u8 *bytes, int *errno); 628cd552cb4SShannon Nelson static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 629cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 63079afe839SShannon Nelson int *perrno); 631cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 632cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 63379afe839SShannon Nelson int *perrno); 634cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 635cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 63679afe839SShannon Nelson u8 *bytes, int *perrno); 637cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 638cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 63979afe839SShannon Nelson u8 *bytes, int *perrno); 640e4c83c20SShannon Nelson static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 641e4c83c20SShannon Nelson struct i40e_nvm_access *cmd, 642e4c83c20SShannon Nelson u8 *bytes, int *perrno); 643b72dc7b1SShannon Nelson static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 644b72dc7b1SShannon Nelson struct i40e_nvm_access *cmd, 645b72dc7b1SShannon Nelson u8 *bytes, int *perrno); 646cd552cb4SShannon Nelson static inline u8 i40e_nvmupd_get_module(u32 val) 647cd552cb4SShannon Nelson { 648cd552cb4SShannon Nelson return (u8)(val & I40E_NVM_MOD_PNT_MASK); 649cd552cb4SShannon Nelson } 650cd552cb4SShannon Nelson static inline u8 i40e_nvmupd_get_transaction(u32 val) 651cd552cb4SShannon Nelson { 652cd552cb4SShannon Nelson return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); 653cd552cb4SShannon Nelson } 654cd552cb4SShannon Nelson 6554e68adfeSJingjing Wu static const char * const i40e_nvm_update_state_str[] = { 65674d0d0edSShannon Nelson "I40E_NVMUPD_INVALID", 65774d0d0edSShannon Nelson "I40E_NVMUPD_READ_CON", 65874d0d0edSShannon Nelson "I40E_NVMUPD_READ_SNT", 65974d0d0edSShannon Nelson "I40E_NVMUPD_READ_LCB", 66074d0d0edSShannon Nelson "I40E_NVMUPD_READ_SA", 66174d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_ERA", 66274d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_CON", 66374d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_SNT", 66474d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_LCB", 66574d0d0edSShannon Nelson "I40E_NVMUPD_WRITE_SA", 66674d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_CON", 66774d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_SA", 66874d0d0edSShannon Nelson "I40E_NVMUPD_CSUM_LCB", 6690af8e9dbSShannon Nelson "I40E_NVMUPD_STATUS", 670e4c83c20SShannon Nelson "I40E_NVMUPD_EXEC_AQ", 671b72dc7b1SShannon Nelson "I40E_NVMUPD_GET_AQ_RESULT", 67274d0d0edSShannon Nelson }; 67374d0d0edSShannon Nelson 674cd552cb4SShannon Nelson /** 675cd552cb4SShannon Nelson * i40e_nvmupd_command - Process an NVM update command 676cd552cb4SShannon Nelson * @hw: pointer to hardware structure 677cd552cb4SShannon Nelson * @cmd: pointer to nvm update command 678cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 67979afe839SShannon Nelson * @perrno: pointer to return error code 680cd552cb4SShannon Nelson * 681cd552cb4SShannon Nelson * Dispatches command depending on what update state is current 682cd552cb4SShannon Nelson **/ 683cd552cb4SShannon Nelson i40e_status i40e_nvmupd_command(struct i40e_hw *hw, 684cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 68579afe839SShannon Nelson u8 *bytes, int *perrno) 686cd552cb4SShannon Nelson { 687cd552cb4SShannon Nelson i40e_status status; 6880af8e9dbSShannon Nelson enum i40e_nvmupd_cmd upd_cmd; 689cd552cb4SShannon Nelson 690cd552cb4SShannon Nelson /* assume success */ 69179afe839SShannon Nelson *perrno = 0; 692cd552cb4SShannon Nelson 6930af8e9dbSShannon Nelson /* early check for status command and debug msgs */ 6940af8e9dbSShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 6950af8e9dbSShannon Nelson 6961d73b2dbSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n", 6970af8e9dbSShannon Nelson i40e_nvm_update_state_str[upd_cmd], 6980af8e9dbSShannon Nelson hw->nvmupd_state, 699437f82a2SShannon Nelson hw->nvm_release_on_done, 7001d73b2dbSShannon Nelson cmd->command, cmd->config, cmd->offset, cmd->data_size); 7010af8e9dbSShannon Nelson 7020af8e9dbSShannon Nelson if (upd_cmd == I40E_NVMUPD_INVALID) { 7030af8e9dbSShannon Nelson *perrno = -EFAULT; 7040af8e9dbSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 7050af8e9dbSShannon Nelson "i40e_nvmupd_validate_command returns %d errno %d\n", 7060af8e9dbSShannon Nelson upd_cmd, *perrno); 7070af8e9dbSShannon Nelson } 7080af8e9dbSShannon Nelson 7090af8e9dbSShannon Nelson /* a status request returns immediately rather than 7100af8e9dbSShannon Nelson * going into the state machine 7110af8e9dbSShannon Nelson */ 7120af8e9dbSShannon Nelson if (upd_cmd == I40E_NVMUPD_STATUS) { 7130af8e9dbSShannon Nelson bytes[0] = hw->nvmupd_state; 7140af8e9dbSShannon Nelson return 0; 7150af8e9dbSShannon Nelson } 7160af8e9dbSShannon Nelson 717cd552cb4SShannon Nelson switch (hw->nvmupd_state) { 718cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_INIT: 71979afe839SShannon Nelson status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); 720cd552cb4SShannon Nelson break; 721cd552cb4SShannon Nelson 722cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_READING: 72379afe839SShannon Nelson status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); 724cd552cb4SShannon Nelson break; 725cd552cb4SShannon Nelson 726cd552cb4SShannon Nelson case I40E_NVMUPD_STATE_WRITING: 72779afe839SShannon Nelson status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); 728cd552cb4SShannon Nelson break; 729cd552cb4SShannon Nelson 7302f1b5bc8SShannon Nelson case I40E_NVMUPD_STATE_INIT_WAIT: 7312f1b5bc8SShannon Nelson case I40E_NVMUPD_STATE_WRITE_WAIT: 7322f1b5bc8SShannon Nelson status = I40E_ERR_NOT_READY; 7332f1b5bc8SShannon Nelson *perrno = -EBUSY; 7342f1b5bc8SShannon Nelson break; 7352f1b5bc8SShannon Nelson 736cd552cb4SShannon Nelson default: 737cd552cb4SShannon Nelson /* invalid state, should never happen */ 73874d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 73974d0d0edSShannon Nelson "NVMUPD: no such state %d\n", hw->nvmupd_state); 740cd552cb4SShannon Nelson status = I40E_NOT_SUPPORTED; 74179afe839SShannon Nelson *perrno = -ESRCH; 742cd552cb4SShannon Nelson break; 743cd552cb4SShannon Nelson } 744cd552cb4SShannon Nelson return status; 745cd552cb4SShannon Nelson } 746cd552cb4SShannon Nelson 747cd552cb4SShannon Nelson /** 748cd552cb4SShannon Nelson * i40e_nvmupd_state_init - Handle NVM update state Init 749cd552cb4SShannon Nelson * @hw: pointer to hardware structure 750cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 751cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 75279afe839SShannon Nelson * @perrno: pointer to return error code 753cd552cb4SShannon Nelson * 754cd552cb4SShannon Nelson * Process legitimate commands of the Init state and conditionally set next 755cd552cb4SShannon Nelson * state. Reject all other commands. 756cd552cb4SShannon Nelson **/ 757cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw, 758cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 75979afe839SShannon Nelson u8 *bytes, int *perrno) 760cd552cb4SShannon Nelson { 761cd552cb4SShannon Nelson i40e_status status = 0; 762cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd; 763cd552cb4SShannon Nelson 76479afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 765cd552cb4SShannon Nelson 766cd552cb4SShannon Nelson switch (upd_cmd) { 767cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SA: 768cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 769cd552cb4SShannon Nelson if (status) { 77079afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 771bf848f32SShannon Nelson hw->aq.asq_last_status); 772cd552cb4SShannon Nelson } else { 77379afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 774cd552cb4SShannon Nelson i40e_release_nvm(hw); 775cd552cb4SShannon Nelson } 776cd552cb4SShannon Nelson break; 777cd552cb4SShannon Nelson 778cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SNT: 779cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 780cd552cb4SShannon Nelson if (status) { 78179afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 782bf848f32SShannon Nelson hw->aq.asq_last_status); 783cd552cb4SShannon Nelson } else { 78479afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 7850fdd052cSShannon Nelson if (status) 7860fdd052cSShannon Nelson i40e_release_nvm(hw); 7870fdd052cSShannon Nelson else 788cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_READING; 789cd552cb4SShannon Nelson } 790cd552cb4SShannon Nelson break; 791cd552cb4SShannon Nelson 792cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_ERA: 793cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 794cd552cb4SShannon Nelson if (status) { 79579afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 796bf848f32SShannon Nelson hw->aq.asq_last_status); 797cd552cb4SShannon Nelson } else { 79879afe839SShannon Nelson status = i40e_nvmupd_nvm_erase(hw, cmd, perrno); 7992f1b5bc8SShannon Nelson if (status) { 800cd552cb4SShannon Nelson i40e_release_nvm(hw); 8012f1b5bc8SShannon Nelson } else { 802437f82a2SShannon Nelson hw->nvm_release_on_done = true; 8032f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 8042f1b5bc8SShannon Nelson } 805cd552cb4SShannon Nelson } 806cd552cb4SShannon Nelson break; 807cd552cb4SShannon Nelson 808cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_SA: 809cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 810cd552cb4SShannon Nelson if (status) { 81179afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 812bf848f32SShannon Nelson hw->aq.asq_last_status); 813cd552cb4SShannon Nelson } else { 81479afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 8152f1b5bc8SShannon Nelson if (status) { 816cd552cb4SShannon Nelson i40e_release_nvm(hw); 8172f1b5bc8SShannon Nelson } else { 818437f82a2SShannon Nelson hw->nvm_release_on_done = true; 8192f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 8202f1b5bc8SShannon Nelson } 821cd552cb4SShannon Nelson } 822cd552cb4SShannon Nelson break; 823cd552cb4SShannon Nelson 824cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_SNT: 825cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 826cd552cb4SShannon Nelson if (status) { 82779afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 828bf848f32SShannon Nelson hw->aq.asq_last_status); 829cd552cb4SShannon Nelson } else { 83079afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 8310fdd052cSShannon Nelson if (status) 8320fdd052cSShannon Nelson i40e_release_nvm(hw); 8330fdd052cSShannon Nelson else 8342f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 835cd552cb4SShannon Nelson } 836cd552cb4SShannon Nelson break; 837cd552cb4SShannon Nelson 838cd552cb4SShannon Nelson case I40E_NVMUPD_CSUM_SA: 839cd552cb4SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 840cd552cb4SShannon Nelson if (status) { 84179afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, 842bf848f32SShannon Nelson hw->aq.asq_last_status); 843cd552cb4SShannon Nelson } else { 844cd552cb4SShannon Nelson status = i40e_update_nvm_checksum(hw); 845cd552cb4SShannon Nelson if (status) { 84679afe839SShannon Nelson *perrno = hw->aq.asq_last_status ? 847bf848f32SShannon Nelson i40e_aq_rc_to_posix(status, 848bf848f32SShannon Nelson hw->aq.asq_last_status) : 849cd552cb4SShannon Nelson -EIO; 850cd552cb4SShannon Nelson i40e_release_nvm(hw); 851cd552cb4SShannon Nelson } else { 852437f82a2SShannon Nelson hw->nvm_release_on_done = true; 8532f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 854cd552cb4SShannon Nelson } 855cd552cb4SShannon Nelson } 856cd552cb4SShannon Nelson break; 857cd552cb4SShannon Nelson 858e4c83c20SShannon Nelson case I40E_NVMUPD_EXEC_AQ: 859e4c83c20SShannon Nelson status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); 860e4c83c20SShannon Nelson break; 861e4c83c20SShannon Nelson 862b72dc7b1SShannon Nelson case I40E_NVMUPD_GET_AQ_RESULT: 863b72dc7b1SShannon Nelson status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); 864b72dc7b1SShannon Nelson break; 865b72dc7b1SShannon Nelson 866cd552cb4SShannon Nelson default: 86774d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 86874d0d0edSShannon Nelson "NVMUPD: bad cmd %s in init state\n", 86974d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]); 870cd552cb4SShannon Nelson status = I40E_ERR_NVM; 87179afe839SShannon Nelson *perrno = -ESRCH; 872cd552cb4SShannon Nelson break; 873cd552cb4SShannon Nelson } 874cd552cb4SShannon Nelson return status; 875cd552cb4SShannon Nelson } 876cd552cb4SShannon Nelson 877cd552cb4SShannon Nelson /** 878cd552cb4SShannon Nelson * i40e_nvmupd_state_reading - Handle NVM update state Reading 879cd552cb4SShannon Nelson * @hw: pointer to hardware structure 880cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 881cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 88279afe839SShannon Nelson * @perrno: pointer to return error code 883cd552cb4SShannon Nelson * 884cd552cb4SShannon Nelson * NVM ownership is already held. Process legitimate commands and set any 885cd552cb4SShannon Nelson * change in state; reject all other commands. 886cd552cb4SShannon Nelson **/ 887cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw, 888cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 88979afe839SShannon Nelson u8 *bytes, int *perrno) 890cd552cb4SShannon Nelson { 8912f1b5bc8SShannon Nelson i40e_status status = 0; 892cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd; 893cd552cb4SShannon Nelson 89479afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 895cd552cb4SShannon Nelson 896cd552cb4SShannon Nelson switch (upd_cmd) { 897cd552cb4SShannon Nelson case I40E_NVMUPD_READ_SA: 898cd552cb4SShannon Nelson case I40E_NVMUPD_READ_CON: 89979afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 900cd552cb4SShannon Nelson break; 901cd552cb4SShannon Nelson 902cd552cb4SShannon Nelson case I40E_NVMUPD_READ_LCB: 90379afe839SShannon Nelson status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno); 904cd552cb4SShannon Nelson i40e_release_nvm(hw); 905cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 906cd552cb4SShannon Nelson break; 907cd552cb4SShannon Nelson 908cd552cb4SShannon Nelson default: 90974d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 91074d0d0edSShannon Nelson "NVMUPD: bad cmd %s in reading state.\n", 91174d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]); 912cd552cb4SShannon Nelson status = I40E_NOT_SUPPORTED; 91379afe839SShannon Nelson *perrno = -ESRCH; 914cd552cb4SShannon Nelson break; 915cd552cb4SShannon Nelson } 916cd552cb4SShannon Nelson return status; 917cd552cb4SShannon Nelson } 918cd552cb4SShannon Nelson 919cd552cb4SShannon Nelson /** 920cd552cb4SShannon Nelson * i40e_nvmupd_state_writing - Handle NVM update state Writing 921cd552cb4SShannon Nelson * @hw: pointer to hardware structure 922cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 923cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 92479afe839SShannon Nelson * @perrno: pointer to return error code 925cd552cb4SShannon Nelson * 926cd552cb4SShannon Nelson * NVM ownership is already held. Process legitimate commands and set any 927cd552cb4SShannon Nelson * change in state; reject all other commands 928cd552cb4SShannon Nelson **/ 929cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw, 930cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 93179afe839SShannon Nelson u8 *bytes, int *perrno) 932cd552cb4SShannon Nelson { 9332f1b5bc8SShannon Nelson i40e_status status = 0; 934cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd; 9352c47e351SShannon Nelson bool retry_attempt = false; 936cd552cb4SShannon Nelson 93779afe839SShannon Nelson upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno); 938cd552cb4SShannon Nelson 9392c47e351SShannon Nelson retry: 940cd552cb4SShannon Nelson switch (upd_cmd) { 941cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_CON: 94279afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 9432f1b5bc8SShannon Nelson if (!status) 9442f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 945cd552cb4SShannon Nelson break; 946cd552cb4SShannon Nelson 947cd552cb4SShannon Nelson case I40E_NVMUPD_WRITE_LCB: 94879afe839SShannon Nelson status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno); 9492f1b5bc8SShannon Nelson if (status) { 9502f1b5bc8SShannon Nelson *perrno = hw->aq.asq_last_status ? 9512f1b5bc8SShannon Nelson i40e_aq_rc_to_posix(status, 9522f1b5bc8SShannon Nelson hw->aq.asq_last_status) : 9532f1b5bc8SShannon Nelson -EIO; 954cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 9552f1b5bc8SShannon Nelson } else { 956437f82a2SShannon Nelson hw->nvm_release_on_done = true; 9572f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 9582f1b5bc8SShannon Nelson } 959cd552cb4SShannon Nelson break; 960cd552cb4SShannon Nelson 961cd552cb4SShannon Nelson case I40E_NVMUPD_CSUM_CON: 962cd552cb4SShannon Nelson status = i40e_update_nvm_checksum(hw); 963cd552cb4SShannon Nelson if (status) { 96479afe839SShannon Nelson *perrno = hw->aq.asq_last_status ? 965bf848f32SShannon Nelson i40e_aq_rc_to_posix(status, 966bf848f32SShannon Nelson hw->aq.asq_last_status) : 967cd552cb4SShannon Nelson -EIO; 968cd552cb4SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 9692f1b5bc8SShannon Nelson } else { 9702f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; 971cd552cb4SShannon Nelson } 972cd552cb4SShannon Nelson break; 973cd552cb4SShannon Nelson 9740fdd052cSShannon Nelson case I40E_NVMUPD_CSUM_LCB: 9750fdd052cSShannon Nelson status = i40e_update_nvm_checksum(hw); 9762f1b5bc8SShannon Nelson if (status) { 97779afe839SShannon Nelson *perrno = hw->aq.asq_last_status ? 978bf848f32SShannon Nelson i40e_aq_rc_to_posix(status, 979bf848f32SShannon Nelson hw->aq.asq_last_status) : 9800fdd052cSShannon Nelson -EIO; 9810fdd052cSShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 9822f1b5bc8SShannon Nelson } else { 983437f82a2SShannon Nelson hw->nvm_release_on_done = true; 9842f1b5bc8SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; 9852f1b5bc8SShannon Nelson } 9860fdd052cSShannon Nelson break; 9870fdd052cSShannon Nelson 988cd552cb4SShannon Nelson default: 98974d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 99074d0d0edSShannon Nelson "NVMUPD: bad cmd %s in writing state.\n", 99174d0d0edSShannon Nelson i40e_nvm_update_state_str[upd_cmd]); 992cd552cb4SShannon Nelson status = I40E_NOT_SUPPORTED; 99379afe839SShannon Nelson *perrno = -ESRCH; 994cd552cb4SShannon Nelson break; 995cd552cb4SShannon Nelson } 9962c47e351SShannon Nelson 9972c47e351SShannon Nelson /* In some circumstances, a multi-write transaction takes longer 9982c47e351SShannon Nelson * than the default 3 minute timeout on the write semaphore. If 9992c47e351SShannon Nelson * the write failed with an EBUSY status, this is likely the problem, 10002c47e351SShannon Nelson * so here we try to reacquire the semaphore then retry the write. 10012c47e351SShannon Nelson * We only do one retry, then give up. 10022c47e351SShannon Nelson */ 10032c47e351SShannon Nelson if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && 10042c47e351SShannon Nelson !retry_attempt) { 10052c47e351SShannon Nelson i40e_status old_status = status; 10062c47e351SShannon Nelson u32 old_asq_status = hw->aq.asq_last_status; 10072c47e351SShannon Nelson u32 gtime; 10082c47e351SShannon Nelson 10092c47e351SShannon Nelson gtime = rd32(hw, I40E_GLVFGEN_TIMER); 10102c47e351SShannon Nelson if (gtime >= hw->nvm.hw_semaphore_timeout) { 10112c47e351SShannon Nelson i40e_debug(hw, I40E_DEBUG_ALL, 10122c47e351SShannon Nelson "NVMUPD: write semaphore expired (%d >= %lld), retrying\n", 10132c47e351SShannon Nelson gtime, hw->nvm.hw_semaphore_timeout); 10142c47e351SShannon Nelson i40e_release_nvm(hw); 10152c47e351SShannon Nelson status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE); 10162c47e351SShannon Nelson if (status) { 10172c47e351SShannon Nelson i40e_debug(hw, I40E_DEBUG_ALL, 10182c47e351SShannon Nelson "NVMUPD: write semaphore reacquire failed aq_err = %d\n", 10192c47e351SShannon Nelson hw->aq.asq_last_status); 10202c47e351SShannon Nelson status = old_status; 10212c47e351SShannon Nelson hw->aq.asq_last_status = old_asq_status; 10222c47e351SShannon Nelson } else { 10232c47e351SShannon Nelson retry_attempt = true; 10242c47e351SShannon Nelson goto retry; 10252c47e351SShannon Nelson } 10262c47e351SShannon Nelson } 10272c47e351SShannon Nelson } 10282c47e351SShannon Nelson 1029cd552cb4SShannon Nelson return status; 1030cd552cb4SShannon Nelson } 1031cd552cb4SShannon Nelson 1032cd552cb4SShannon Nelson /** 1033bab2fb60SShannon Nelson * i40e_nvmupd_check_wait_event - handle NVM update operation events 1034bab2fb60SShannon Nelson * @hw: pointer to the hardware structure 1035bab2fb60SShannon Nelson * @opcode: the event that just happened 1036bab2fb60SShannon Nelson **/ 1037bab2fb60SShannon Nelson void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode) 1038bab2fb60SShannon Nelson { 1039bab2fb60SShannon Nelson if (opcode == i40e_aqc_opc_nvm_erase || 1040bab2fb60SShannon Nelson opcode == i40e_aqc_opc_nvm_update) { 1041bab2fb60SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 1042bab2fb60SShannon Nelson "NVMUPD: clearing wait on opcode 0x%04x\n", opcode); 1043bab2fb60SShannon Nelson if (hw->nvm_release_on_done) { 1044bab2fb60SShannon Nelson i40e_release_nvm(hw); 1045bab2fb60SShannon Nelson hw->nvm_release_on_done = false; 1046bab2fb60SShannon Nelson } 1047bab2fb60SShannon Nelson 1048bab2fb60SShannon Nelson switch (hw->nvmupd_state) { 1049bab2fb60SShannon Nelson case I40E_NVMUPD_STATE_INIT_WAIT: 1050bab2fb60SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 1051bab2fb60SShannon Nelson break; 1052bab2fb60SShannon Nelson 1053bab2fb60SShannon Nelson case I40E_NVMUPD_STATE_WRITE_WAIT: 1054bab2fb60SShannon Nelson hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; 1055bab2fb60SShannon Nelson break; 1056bab2fb60SShannon Nelson 1057bab2fb60SShannon Nelson default: 1058bab2fb60SShannon Nelson break; 1059bab2fb60SShannon Nelson } 1060bab2fb60SShannon Nelson } 1061bab2fb60SShannon Nelson } 1062bab2fb60SShannon Nelson 1063bab2fb60SShannon Nelson /** 1064cd552cb4SShannon Nelson * i40e_nvmupd_validate_command - Validate given command 1065cd552cb4SShannon Nelson * @hw: pointer to hardware structure 1066cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 106779afe839SShannon Nelson * @perrno: pointer to return error code 1068cd552cb4SShannon Nelson * 1069cd552cb4SShannon Nelson * Return one of the valid command types or I40E_NVMUPD_INVALID 1070cd552cb4SShannon Nelson **/ 1071cd552cb4SShannon Nelson static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw, 1072cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 107379afe839SShannon Nelson int *perrno) 1074cd552cb4SShannon Nelson { 1075cd552cb4SShannon Nelson enum i40e_nvmupd_cmd upd_cmd; 10760af8e9dbSShannon Nelson u8 module, transaction; 1077cd552cb4SShannon Nelson 1078cd552cb4SShannon Nelson /* anything that doesn't match a recognized case is an error */ 1079cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_INVALID; 1080cd552cb4SShannon Nelson 1081cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config); 10820af8e9dbSShannon Nelson module = i40e_nvmupd_get_module(cmd->config); 1083cd552cb4SShannon Nelson 1084cd552cb4SShannon Nelson /* limits on data size */ 1085cd552cb4SShannon Nelson if ((cmd->data_size < 1) || 1086cd552cb4SShannon Nelson (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { 108774d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 108874d0d0edSShannon Nelson "i40e_nvmupd_validate_command data_size %d\n", 1089cd552cb4SShannon Nelson cmd->data_size); 109079afe839SShannon Nelson *perrno = -EFAULT; 1091cd552cb4SShannon Nelson return I40E_NVMUPD_INVALID; 1092cd552cb4SShannon Nelson } 1093cd552cb4SShannon Nelson 1094cd552cb4SShannon Nelson switch (cmd->command) { 1095cd552cb4SShannon Nelson case I40E_NVM_READ: 1096cd552cb4SShannon Nelson switch (transaction) { 1097cd552cb4SShannon Nelson case I40E_NVM_CON: 1098cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_CON; 1099cd552cb4SShannon Nelson break; 1100cd552cb4SShannon Nelson case I40E_NVM_SNT: 1101cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_SNT; 1102cd552cb4SShannon Nelson break; 1103cd552cb4SShannon Nelson case I40E_NVM_LCB: 1104cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_LCB; 1105cd552cb4SShannon Nelson break; 1106cd552cb4SShannon Nelson case I40E_NVM_SA: 1107cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_READ_SA; 1108cd552cb4SShannon Nelson break; 11090af8e9dbSShannon Nelson case I40E_NVM_EXEC: 11100af8e9dbSShannon Nelson if (module == 0xf) 11110af8e9dbSShannon Nelson upd_cmd = I40E_NVMUPD_STATUS; 1112b72dc7b1SShannon Nelson else if (module == 0) 1113b72dc7b1SShannon Nelson upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; 11140af8e9dbSShannon Nelson break; 1115cd552cb4SShannon Nelson } 1116cd552cb4SShannon Nelson break; 1117cd552cb4SShannon Nelson 1118cd552cb4SShannon Nelson case I40E_NVM_WRITE: 1119cd552cb4SShannon Nelson switch (transaction) { 1120cd552cb4SShannon Nelson case I40E_NVM_CON: 1121cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_CON; 1122cd552cb4SShannon Nelson break; 1123cd552cb4SShannon Nelson case I40E_NVM_SNT: 1124cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_SNT; 1125cd552cb4SShannon Nelson break; 1126cd552cb4SShannon Nelson case I40E_NVM_LCB: 1127cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_LCB; 1128cd552cb4SShannon Nelson break; 1129cd552cb4SShannon Nelson case I40E_NVM_SA: 1130cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_SA; 1131cd552cb4SShannon Nelson break; 1132cd552cb4SShannon Nelson case I40E_NVM_ERA: 1133cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_WRITE_ERA; 1134cd552cb4SShannon Nelson break; 1135cd552cb4SShannon Nelson case I40E_NVM_CSUM: 1136cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_CON; 1137cd552cb4SShannon Nelson break; 1138cd552cb4SShannon Nelson case (I40E_NVM_CSUM|I40E_NVM_SA): 1139cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_SA; 1140cd552cb4SShannon Nelson break; 1141cd552cb4SShannon Nelson case (I40E_NVM_CSUM|I40E_NVM_LCB): 1142cd552cb4SShannon Nelson upd_cmd = I40E_NVMUPD_CSUM_LCB; 1143cd552cb4SShannon Nelson break; 1144e4c83c20SShannon Nelson case I40E_NVM_EXEC: 1145e4c83c20SShannon Nelson if (module == 0) 1146e4c83c20SShannon Nelson upd_cmd = I40E_NVMUPD_EXEC_AQ; 1147e4c83c20SShannon Nelson break; 1148cd552cb4SShannon Nelson } 1149cd552cb4SShannon Nelson break; 1150cd552cb4SShannon Nelson } 1151cd552cb4SShannon Nelson 1152cd552cb4SShannon Nelson return upd_cmd; 1153cd552cb4SShannon Nelson } 1154cd552cb4SShannon Nelson 1155cd552cb4SShannon Nelson /** 1156e4c83c20SShannon Nelson * i40e_nvmupd_exec_aq - Run an AQ command 1157e4c83c20SShannon Nelson * @hw: pointer to hardware structure 1158e4c83c20SShannon Nelson * @cmd: pointer to nvm update command buffer 1159e4c83c20SShannon Nelson * @bytes: pointer to the data buffer 1160e4c83c20SShannon Nelson * @perrno: pointer to return error code 1161e4c83c20SShannon Nelson * 1162e4c83c20SShannon Nelson * cmd structure contains identifiers and data buffer 1163e4c83c20SShannon Nelson **/ 1164e4c83c20SShannon Nelson static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw, 1165e4c83c20SShannon Nelson struct i40e_nvm_access *cmd, 1166e4c83c20SShannon Nelson u8 *bytes, int *perrno) 1167e4c83c20SShannon Nelson { 1168e4c83c20SShannon Nelson struct i40e_asq_cmd_details cmd_details; 1169e4c83c20SShannon Nelson i40e_status status; 1170e4c83c20SShannon Nelson struct i40e_aq_desc *aq_desc; 1171e4c83c20SShannon Nelson u32 buff_size = 0; 1172e4c83c20SShannon Nelson u8 *buff = NULL; 1173e4c83c20SShannon Nelson u32 aq_desc_len; 1174e4c83c20SShannon Nelson u32 aq_data_len; 1175e4c83c20SShannon Nelson 1176e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1177e4c83c20SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 1178e4c83c20SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc; 1179e4c83c20SShannon Nelson 1180e4c83c20SShannon Nelson aq_desc_len = sizeof(struct i40e_aq_desc); 1181e4c83c20SShannon Nelson memset(&hw->nvm_wb_desc, 0, aq_desc_len); 1182e4c83c20SShannon Nelson 1183e4c83c20SShannon Nelson /* get the aq descriptor */ 1184e4c83c20SShannon Nelson if (cmd->data_size < aq_desc_len) { 1185e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 1186e4c83c20SShannon Nelson "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n", 1187e4c83c20SShannon Nelson cmd->data_size, aq_desc_len); 1188e4c83c20SShannon Nelson *perrno = -EINVAL; 1189e4c83c20SShannon Nelson return I40E_ERR_PARAM; 1190e4c83c20SShannon Nelson } 1191e4c83c20SShannon Nelson aq_desc = (struct i40e_aq_desc *)bytes; 1192e4c83c20SShannon Nelson 1193e4c83c20SShannon Nelson /* if data buffer needed, make sure it's ready */ 1194e4c83c20SShannon Nelson aq_data_len = cmd->data_size - aq_desc_len; 1195e4c83c20SShannon Nelson buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen)); 1196e4c83c20SShannon Nelson if (buff_size) { 1197e4c83c20SShannon Nelson if (!hw->nvm_buff.va) { 1198e4c83c20SShannon Nelson status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, 1199e4c83c20SShannon Nelson hw->aq.asq_buf_size); 1200e4c83c20SShannon Nelson if (status) 1201e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 1202e4c83c20SShannon Nelson "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n", 1203e4c83c20SShannon Nelson status); 1204e4c83c20SShannon Nelson } 1205e4c83c20SShannon Nelson 1206e4c83c20SShannon Nelson if (hw->nvm_buff.va) { 1207e4c83c20SShannon Nelson buff = hw->nvm_buff.va; 1208e4c83c20SShannon Nelson memcpy(buff, &bytes[aq_desc_len], aq_data_len); 1209e4c83c20SShannon Nelson } 1210e4c83c20SShannon Nelson } 1211e4c83c20SShannon Nelson 1212e4c83c20SShannon Nelson /* and away we go! */ 1213e4c83c20SShannon Nelson status = i40e_asq_send_command(hw, aq_desc, buff, 1214e4c83c20SShannon Nelson buff_size, &cmd_details); 1215e4c83c20SShannon Nelson if (status) { 1216e4c83c20SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 1217e4c83c20SShannon Nelson "i40e_nvmupd_exec_aq err %s aq_err %s\n", 1218e4c83c20SShannon Nelson i40e_stat_str(hw, status), 1219e4c83c20SShannon Nelson i40e_aq_str(hw, hw->aq.asq_last_status)); 1220e4c83c20SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 1221e4c83c20SShannon Nelson } 1222e4c83c20SShannon Nelson 1223e4c83c20SShannon Nelson return status; 1224e4c83c20SShannon Nelson } 1225e4c83c20SShannon Nelson 1226e4c83c20SShannon Nelson /** 1227b72dc7b1SShannon Nelson * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq 1228b72dc7b1SShannon Nelson * @hw: pointer to hardware structure 1229b72dc7b1SShannon Nelson * @cmd: pointer to nvm update command buffer 1230b72dc7b1SShannon Nelson * @bytes: pointer to the data buffer 1231b72dc7b1SShannon Nelson * @perrno: pointer to return error code 1232b72dc7b1SShannon Nelson * 1233b72dc7b1SShannon Nelson * cmd structure contains identifiers and data buffer 1234b72dc7b1SShannon Nelson **/ 1235b72dc7b1SShannon Nelson static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw, 1236b72dc7b1SShannon Nelson struct i40e_nvm_access *cmd, 1237b72dc7b1SShannon Nelson u8 *bytes, int *perrno) 1238b72dc7b1SShannon Nelson { 1239b72dc7b1SShannon Nelson u32 aq_total_len; 1240b72dc7b1SShannon Nelson u32 aq_desc_len; 1241b72dc7b1SShannon Nelson int remainder; 1242b72dc7b1SShannon Nelson u8 *buff; 1243b72dc7b1SShannon Nelson 1244b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); 1245b72dc7b1SShannon Nelson 1246b72dc7b1SShannon Nelson aq_desc_len = sizeof(struct i40e_aq_desc); 1247b72dc7b1SShannon Nelson aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen); 1248b72dc7b1SShannon Nelson 1249b72dc7b1SShannon Nelson /* check offset range */ 1250b72dc7b1SShannon Nelson if (cmd->offset > aq_total_len) { 1251b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n", 1252b72dc7b1SShannon Nelson __func__, cmd->offset, aq_total_len); 1253b72dc7b1SShannon Nelson *perrno = -EINVAL; 1254b72dc7b1SShannon Nelson return I40E_ERR_PARAM; 1255b72dc7b1SShannon Nelson } 1256b72dc7b1SShannon Nelson 1257b72dc7b1SShannon Nelson /* check copylength range */ 1258b72dc7b1SShannon Nelson if (cmd->data_size > (aq_total_len - cmd->offset)) { 1259b72dc7b1SShannon Nelson int new_len = aq_total_len - cmd->offset; 1260b72dc7b1SShannon Nelson 1261b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n", 1262b72dc7b1SShannon Nelson __func__, cmd->data_size, new_len); 1263b72dc7b1SShannon Nelson cmd->data_size = new_len; 1264b72dc7b1SShannon Nelson } 1265b72dc7b1SShannon Nelson 1266b72dc7b1SShannon Nelson remainder = cmd->data_size; 1267b72dc7b1SShannon Nelson if (cmd->offset < aq_desc_len) { 1268b72dc7b1SShannon Nelson u32 len = aq_desc_len - cmd->offset; 1269b72dc7b1SShannon Nelson 1270b72dc7b1SShannon Nelson len = min(len, cmd->data_size); 1271b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n", 1272b72dc7b1SShannon Nelson __func__, cmd->offset, cmd->offset + len); 1273b72dc7b1SShannon Nelson 1274b72dc7b1SShannon Nelson buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; 1275b72dc7b1SShannon Nelson memcpy(bytes, buff, len); 1276b72dc7b1SShannon Nelson 1277b72dc7b1SShannon Nelson bytes += len; 1278b72dc7b1SShannon Nelson remainder -= len; 1279b72dc7b1SShannon Nelson buff = hw->nvm_buff.va; 1280b72dc7b1SShannon Nelson } else { 1281b72dc7b1SShannon Nelson buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len); 1282b72dc7b1SShannon Nelson } 1283b72dc7b1SShannon Nelson 1284b72dc7b1SShannon Nelson if (remainder > 0) { 1285b72dc7b1SShannon Nelson int start_byte = buff - (u8 *)hw->nvm_buff.va; 1286b72dc7b1SShannon Nelson 1287b72dc7b1SShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", 1288b72dc7b1SShannon Nelson __func__, start_byte, start_byte + remainder); 1289b72dc7b1SShannon Nelson memcpy(bytes, buff, remainder); 1290b72dc7b1SShannon Nelson } 1291b72dc7b1SShannon Nelson 1292b72dc7b1SShannon Nelson return 0; 1293b72dc7b1SShannon Nelson } 1294b72dc7b1SShannon Nelson 1295b72dc7b1SShannon Nelson /** 1296cd552cb4SShannon Nelson * i40e_nvmupd_nvm_read - Read NVM 1297cd552cb4SShannon Nelson * @hw: pointer to hardware structure 1298cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 1299cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 130079afe839SShannon Nelson * @perrno: pointer to return error code 1301cd552cb4SShannon Nelson * 1302cd552cb4SShannon Nelson * cmd structure contains identifiers and data buffer 1303cd552cb4SShannon Nelson **/ 1304cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw, 1305cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 130679afe839SShannon Nelson u8 *bytes, int *perrno) 1307cd552cb4SShannon Nelson { 13086b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details; 1309cd552cb4SShannon Nelson i40e_status status; 1310cd552cb4SShannon Nelson u8 module, transaction; 1311cd552cb4SShannon Nelson bool last; 1312cd552cb4SShannon Nelson 1313cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config); 1314cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config); 1315cd552cb4SShannon Nelson last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA); 1316cd552cb4SShannon Nelson 13176b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 13186b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc; 13196b5c1b89SShannon Nelson 1320cd552cb4SShannon Nelson status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 13216b5c1b89SShannon Nelson bytes, last, &cmd_details); 132274d0d0edSShannon Nelson if (status) { 132374d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 132474d0d0edSShannon Nelson "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n", 132574d0d0edSShannon Nelson module, cmd->offset, cmd->data_size); 132674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 132774d0d0edSShannon Nelson "i40e_nvmupd_nvm_read status %d aq %d\n", 132874d0d0edSShannon Nelson status, hw->aq.asq_last_status); 132979afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 133074d0d0edSShannon Nelson } 1331cd552cb4SShannon Nelson 1332cd552cb4SShannon Nelson return status; 1333cd552cb4SShannon Nelson } 1334cd552cb4SShannon Nelson 1335cd552cb4SShannon Nelson /** 1336cd552cb4SShannon Nelson * i40e_nvmupd_nvm_erase - Erase an NVM module 1337cd552cb4SShannon Nelson * @hw: pointer to hardware structure 1338cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 133979afe839SShannon Nelson * @perrno: pointer to return error code 1340cd552cb4SShannon Nelson * 1341cd552cb4SShannon Nelson * module, offset, data_size and data are in cmd structure 1342cd552cb4SShannon Nelson **/ 1343cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw, 1344cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 134579afe839SShannon Nelson int *perrno) 1346cd552cb4SShannon Nelson { 1347cd552cb4SShannon Nelson i40e_status status = 0; 13486b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details; 1349cd552cb4SShannon Nelson u8 module, transaction; 1350cd552cb4SShannon Nelson bool last; 1351cd552cb4SShannon Nelson 1352cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config); 1353cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config); 1354cd552cb4SShannon Nelson last = (transaction & I40E_NVM_LCB); 13556b5c1b89SShannon Nelson 13566b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 13576b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc; 13586b5c1b89SShannon Nelson 1359cd552cb4SShannon Nelson status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, 13606b5c1b89SShannon Nelson last, &cmd_details); 136174d0d0edSShannon Nelson if (status) { 136274d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 136374d0d0edSShannon Nelson "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n", 136474d0d0edSShannon Nelson module, cmd->offset, cmd->data_size); 136574d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 136674d0d0edSShannon Nelson "i40e_nvmupd_nvm_erase status %d aq %d\n", 136774d0d0edSShannon Nelson status, hw->aq.asq_last_status); 136879afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 136974d0d0edSShannon Nelson } 1370cd552cb4SShannon Nelson 1371cd552cb4SShannon Nelson return status; 1372cd552cb4SShannon Nelson } 1373cd552cb4SShannon Nelson 1374cd552cb4SShannon Nelson /** 1375cd552cb4SShannon Nelson * i40e_nvmupd_nvm_write - Write NVM 1376cd552cb4SShannon Nelson * @hw: pointer to hardware structure 1377cd552cb4SShannon Nelson * @cmd: pointer to nvm update command buffer 1378cd552cb4SShannon Nelson * @bytes: pointer to the data buffer 137979afe839SShannon Nelson * @perrno: pointer to return error code 1380cd552cb4SShannon Nelson * 1381cd552cb4SShannon Nelson * module, offset, data_size and data are in cmd structure 1382cd552cb4SShannon Nelson **/ 1383cd552cb4SShannon Nelson static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw, 1384cd552cb4SShannon Nelson struct i40e_nvm_access *cmd, 138579afe839SShannon Nelson u8 *bytes, int *perrno) 1386cd552cb4SShannon Nelson { 1387cd552cb4SShannon Nelson i40e_status status = 0; 13886b5c1b89SShannon Nelson struct i40e_asq_cmd_details cmd_details; 1389cd552cb4SShannon Nelson u8 module, transaction; 1390cd552cb4SShannon Nelson bool last; 1391cd552cb4SShannon Nelson 1392cd552cb4SShannon Nelson transaction = i40e_nvmupd_get_transaction(cmd->config); 1393cd552cb4SShannon Nelson module = i40e_nvmupd_get_module(cmd->config); 1394cd552cb4SShannon Nelson last = (transaction & I40E_NVM_LCB); 139574d0d0edSShannon Nelson 13966b5c1b89SShannon Nelson memset(&cmd_details, 0, sizeof(cmd_details)); 13976b5c1b89SShannon Nelson cmd_details.wb_desc = &hw->nvm_wb_desc; 13986b5c1b89SShannon Nelson 1399cd552cb4SShannon Nelson status = i40e_aq_update_nvm(hw, module, cmd->offset, 14006b5c1b89SShannon Nelson (u16)cmd->data_size, bytes, last, 14016b5c1b89SShannon Nelson &cmd_details); 140274d0d0edSShannon Nelson if (status) { 140374d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 140474d0d0edSShannon Nelson "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", 140574d0d0edSShannon Nelson module, cmd->offset, cmd->data_size); 140674d0d0edSShannon Nelson i40e_debug(hw, I40E_DEBUG_NVM, 140774d0d0edSShannon Nelson "i40e_nvmupd_nvm_write status %d aq %d\n", 140874d0d0edSShannon Nelson status, hw->aq.asq_last_status); 140979afe839SShannon Nelson *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); 141074d0d0edSShannon Nelson } 1411cd552cb4SShannon Nelson 1412cd552cb4SShannon Nelson return status; 1413cd552cb4SShannon Nelson } 1414