1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/etherdevice.h> 28 #include <linux/of_net.h> 29 #include <linux/pci.h> 30 31 /* Local includes */ 32 #include "i40e.h" 33 #include "i40e_diag.h" 34 #include <net/udp_tunnel.h> 35 36 const char i40e_driver_name[] = "i40e"; 37 static const char i40e_driver_string[] = 38 "Intel(R) Ethernet Connection XL710 Network Driver"; 39 40 #define DRV_KERN "-k" 41 42 #define DRV_VERSION_MAJOR 1 43 #define DRV_VERSION_MINOR 6 44 #define DRV_VERSION_BUILD 11 45 #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ 46 __stringify(DRV_VERSION_MINOR) "." \ 47 __stringify(DRV_VERSION_BUILD) DRV_KERN 48 const char i40e_driver_version_str[] = DRV_VERSION; 49 static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; 50 51 /* a bit of forward declarations */ 52 static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); 53 static void i40e_handle_reset_warning(struct i40e_pf *pf); 54 static int i40e_add_vsi(struct i40e_vsi *vsi); 55 static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); 56 static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); 57 static int i40e_setup_misc_vector(struct i40e_pf *pf); 58 static void i40e_determine_queue_usage(struct i40e_pf *pf); 59 static int i40e_setup_pf_filter_control(struct i40e_pf *pf); 60 static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 61 u16 rss_table_size, u16 rss_size); 62 static void i40e_fdir_sb_setup(struct i40e_pf *pf); 63 static int i40e_veb_get_bw_info(struct i40e_veb *veb); 64 65 /* i40e_pci_tbl - PCI Device ID Table 66 * 67 * Last entry must be all 0s 68 * 69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 70 * Class, Class Mask, private data (not used) } 71 */ 72 static const struct pci_device_id i40e_pci_tbl[] = { 73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, 76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, 78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, 84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, 86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, 87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, 89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, 91 /* required last entry */ 92 {0, } 93 }; 94 MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); 95 96 #define I40E_MAX_VF_COUNT 128 97 static int debug = -1; 98 module_param(debug, int, 0); 99 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 100 101 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 102 MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); 103 MODULE_LICENSE("GPL"); 104 MODULE_VERSION(DRV_VERSION); 105 106 static struct workqueue_struct *i40e_wq; 107 108 /** 109 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code 110 * @hw: pointer to the HW structure 111 * @mem: ptr to mem struct to fill out 112 * @size: size of memory requested 113 * @alignment: what to align the allocation to 114 **/ 115 int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, 116 u64 size, u32 alignment) 117 { 118 struct i40e_pf *pf = (struct i40e_pf *)hw->back; 119 120 mem->size = ALIGN(size, alignment); 121 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size, 122 &mem->pa, GFP_KERNEL); 123 if (!mem->va) 124 return -ENOMEM; 125 126 return 0; 127 } 128 129 /** 130 * i40e_free_dma_mem_d - OS specific memory free for shared code 131 * @hw: pointer to the HW structure 132 * @mem: ptr to mem struct to free 133 **/ 134 int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) 135 { 136 struct i40e_pf *pf = (struct i40e_pf *)hw->back; 137 138 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); 139 mem->va = NULL; 140 mem->pa = 0; 141 mem->size = 0; 142 143 return 0; 144 } 145 146 /** 147 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code 148 * @hw: pointer to the HW structure 149 * @mem: ptr to mem struct to fill out 150 * @size: size of memory requested 151 **/ 152 int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, 153 u32 size) 154 { 155 mem->size = size; 156 mem->va = kzalloc(size, GFP_KERNEL); 157 158 if (!mem->va) 159 return -ENOMEM; 160 161 return 0; 162 } 163 164 /** 165 * i40e_free_virt_mem_d - OS specific memory free for shared code 166 * @hw: pointer to the HW structure 167 * @mem: ptr to mem struct to free 168 **/ 169 int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) 170 { 171 /* it's ok to kfree a NULL pointer */ 172 kfree(mem->va); 173 mem->va = NULL; 174 mem->size = 0; 175 176 return 0; 177 } 178 179 /** 180 * i40e_get_lump - find a lump of free generic resource 181 * @pf: board private structure 182 * @pile: the pile of resource to search 183 * @needed: the number of items needed 184 * @id: an owner id to stick on the items assigned 185 * 186 * Returns the base item index of the lump, or negative for error 187 * 188 * The search_hint trick and lack of advanced fit-finding only work 189 * because we're highly likely to have all the same size lump requests. 190 * Linear search time and any fragmentation should be minimal. 191 **/ 192 static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, 193 u16 needed, u16 id) 194 { 195 int ret = -ENOMEM; 196 int i, j; 197 198 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { 199 dev_info(&pf->pdev->dev, 200 "param err: pile=%p needed=%d id=0x%04x\n", 201 pile, needed, id); 202 return -EINVAL; 203 } 204 205 /* start the linear search with an imperfect hint */ 206 i = pile->search_hint; 207 while (i < pile->num_entries) { 208 /* skip already allocated entries */ 209 if (pile->list[i] & I40E_PILE_VALID_BIT) { 210 i++; 211 continue; 212 } 213 214 /* do we have enough in this lump? */ 215 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { 216 if (pile->list[i+j] & I40E_PILE_VALID_BIT) 217 break; 218 } 219 220 if (j == needed) { 221 /* there was enough, so assign it to the requestor */ 222 for (j = 0; j < needed; j++) 223 pile->list[i+j] = id | I40E_PILE_VALID_BIT; 224 ret = i; 225 pile->search_hint = i + j; 226 break; 227 } 228 229 /* not enough, so skip over it and continue looking */ 230 i += j; 231 } 232 233 return ret; 234 } 235 236 /** 237 * i40e_put_lump - return a lump of generic resource 238 * @pile: the pile of resource to search 239 * @index: the base item index 240 * @id: the owner id of the items assigned 241 * 242 * Returns the count of items in the lump 243 **/ 244 static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) 245 { 246 int valid_id = (id | I40E_PILE_VALID_BIT); 247 int count = 0; 248 int i; 249 250 if (!pile || index >= pile->num_entries) 251 return -EINVAL; 252 253 for (i = index; 254 i < pile->num_entries && pile->list[i] == valid_id; 255 i++) { 256 pile->list[i] = 0; 257 count++; 258 } 259 260 if (count && index < pile->search_hint) 261 pile->search_hint = index; 262 263 return count; 264 } 265 266 /** 267 * i40e_find_vsi_from_id - searches for the vsi with the given id 268 * @pf - the pf structure to search for the vsi 269 * @id - id of the vsi it is searching for 270 **/ 271 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) 272 { 273 int i; 274 275 for (i = 0; i < pf->num_alloc_vsi; i++) 276 if (pf->vsi[i] && (pf->vsi[i]->id == id)) 277 return pf->vsi[i]; 278 279 return NULL; 280 } 281 282 /** 283 * i40e_service_event_schedule - Schedule the service task to wake up 284 * @pf: board private structure 285 * 286 * If not already scheduled, this puts the task into the work queue 287 **/ 288 void i40e_service_event_schedule(struct i40e_pf *pf) 289 { 290 if (!test_bit(__I40E_DOWN, &pf->state) && 291 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) && 292 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state)) 293 queue_work(i40e_wq, &pf->service_task); 294 } 295 296 /** 297 * i40e_tx_timeout - Respond to a Tx Hang 298 * @netdev: network interface device structure 299 * 300 * If any port has noticed a Tx timeout, it is likely that the whole 301 * device is munged, not just the one netdev port, so go for the full 302 * reset. 303 **/ 304 #ifdef I40E_FCOE 305 void i40e_tx_timeout(struct net_device *netdev) 306 #else 307 static void i40e_tx_timeout(struct net_device *netdev) 308 #endif 309 { 310 struct i40e_netdev_priv *np = netdev_priv(netdev); 311 struct i40e_vsi *vsi = np->vsi; 312 struct i40e_pf *pf = vsi->back; 313 struct i40e_ring *tx_ring = NULL; 314 unsigned int i, hung_queue = 0; 315 u32 head, val; 316 317 pf->tx_timeout_count++; 318 319 /* find the stopped queue the same way the stack does */ 320 for (i = 0; i < netdev->num_tx_queues; i++) { 321 struct netdev_queue *q; 322 unsigned long trans_start; 323 324 q = netdev_get_tx_queue(netdev, i); 325 trans_start = q->trans_start; 326 if (netif_xmit_stopped(q) && 327 time_after(jiffies, 328 (trans_start + netdev->watchdog_timeo))) { 329 hung_queue = i; 330 break; 331 } 332 } 333 334 if (i == netdev->num_tx_queues) { 335 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); 336 } else { 337 /* now that we have an index, find the tx_ring struct */ 338 for (i = 0; i < vsi->num_queue_pairs; i++) { 339 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { 340 if (hung_queue == 341 vsi->tx_rings[i]->queue_index) { 342 tx_ring = vsi->tx_rings[i]; 343 break; 344 } 345 } 346 } 347 } 348 349 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) 350 pf->tx_timeout_recovery_level = 1; /* reset after some time */ 351 else if (time_before(jiffies, 352 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) 353 return; /* don't do any new action before the next timeout */ 354 355 if (tx_ring) { 356 head = i40e_get_head(tx_ring); 357 /* Read interrupt register */ 358 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 359 val = rd32(&pf->hw, 360 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + 361 tx_ring->vsi->base_vector - 1)); 362 else 363 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); 364 365 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", 366 vsi->seid, hung_queue, tx_ring->next_to_clean, 367 head, tx_ring->next_to_use, 368 readl(tx_ring->tail), val); 369 } 370 371 pf->tx_timeout_last_recovery = jiffies; 372 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", 373 pf->tx_timeout_recovery_level, hung_queue); 374 375 switch (pf->tx_timeout_recovery_level) { 376 case 1: 377 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 378 break; 379 case 2: 380 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); 381 break; 382 case 3: 383 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); 384 break; 385 default: 386 netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); 387 break; 388 } 389 390 i40e_service_event_schedule(pf); 391 pf->tx_timeout_recovery_level++; 392 } 393 394 /** 395 * i40e_get_vsi_stats_struct - Get System Network Statistics 396 * @vsi: the VSI we care about 397 * 398 * Returns the address of the device statistics structure. 399 * The statistics are actually updated from the service task. 400 **/ 401 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) 402 { 403 return &vsi->net_stats; 404 } 405 406 /** 407 * i40e_get_netdev_stats_struct - Get statistics for netdev interface 408 * @netdev: network interface device structure 409 * 410 * Returns the address of the device statistics structure. 411 * The statistics are actually updated from the service task. 412 **/ 413 #ifdef I40E_FCOE 414 struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( 415 struct net_device *netdev, 416 struct rtnl_link_stats64 *stats) 417 #else 418 static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct( 419 struct net_device *netdev, 420 struct rtnl_link_stats64 *stats) 421 #endif 422 { 423 struct i40e_netdev_priv *np = netdev_priv(netdev); 424 struct i40e_ring *tx_ring, *rx_ring; 425 struct i40e_vsi *vsi = np->vsi; 426 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); 427 int i; 428 429 if (test_bit(__I40E_DOWN, &vsi->state)) 430 return stats; 431 432 if (!vsi->tx_rings) 433 return stats; 434 435 rcu_read_lock(); 436 for (i = 0; i < vsi->num_queue_pairs; i++) { 437 u64 bytes, packets; 438 unsigned int start; 439 440 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]); 441 if (!tx_ring) 442 continue; 443 444 do { 445 start = u64_stats_fetch_begin_irq(&tx_ring->syncp); 446 packets = tx_ring->stats.packets; 447 bytes = tx_ring->stats.bytes; 448 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start)); 449 450 stats->tx_packets += packets; 451 stats->tx_bytes += bytes; 452 rx_ring = &tx_ring[1]; 453 454 do { 455 start = u64_stats_fetch_begin_irq(&rx_ring->syncp); 456 packets = rx_ring->stats.packets; 457 bytes = rx_ring->stats.bytes; 458 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); 459 460 stats->rx_packets += packets; 461 stats->rx_bytes += bytes; 462 } 463 rcu_read_unlock(); 464 465 /* following stats updated by i40e_watchdog_subtask() */ 466 stats->multicast = vsi_stats->multicast; 467 stats->tx_errors = vsi_stats->tx_errors; 468 stats->tx_dropped = vsi_stats->tx_dropped; 469 stats->rx_errors = vsi_stats->rx_errors; 470 stats->rx_dropped = vsi_stats->rx_dropped; 471 stats->rx_crc_errors = vsi_stats->rx_crc_errors; 472 stats->rx_length_errors = vsi_stats->rx_length_errors; 473 474 return stats; 475 } 476 477 /** 478 * i40e_vsi_reset_stats - Resets all stats of the given vsi 479 * @vsi: the VSI to have its stats reset 480 **/ 481 void i40e_vsi_reset_stats(struct i40e_vsi *vsi) 482 { 483 struct rtnl_link_stats64 *ns; 484 int i; 485 486 if (!vsi) 487 return; 488 489 ns = i40e_get_vsi_stats_struct(vsi); 490 memset(ns, 0, sizeof(*ns)); 491 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); 492 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); 493 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); 494 if (vsi->rx_rings && vsi->rx_rings[0]) { 495 for (i = 0; i < vsi->num_queue_pairs; i++) { 496 memset(&vsi->rx_rings[i]->stats, 0, 497 sizeof(vsi->rx_rings[i]->stats)); 498 memset(&vsi->rx_rings[i]->rx_stats, 0, 499 sizeof(vsi->rx_rings[i]->rx_stats)); 500 memset(&vsi->tx_rings[i]->stats, 0, 501 sizeof(vsi->tx_rings[i]->stats)); 502 memset(&vsi->tx_rings[i]->tx_stats, 0, 503 sizeof(vsi->tx_rings[i]->tx_stats)); 504 } 505 } 506 vsi->stat_offsets_loaded = false; 507 } 508 509 /** 510 * i40e_pf_reset_stats - Reset all of the stats for the given PF 511 * @pf: the PF to be reset 512 **/ 513 void i40e_pf_reset_stats(struct i40e_pf *pf) 514 { 515 int i; 516 517 memset(&pf->stats, 0, sizeof(pf->stats)); 518 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); 519 pf->stat_offsets_loaded = false; 520 521 for (i = 0; i < I40E_MAX_VEB; i++) { 522 if (pf->veb[i]) { 523 memset(&pf->veb[i]->stats, 0, 524 sizeof(pf->veb[i]->stats)); 525 memset(&pf->veb[i]->stats_offsets, 0, 526 sizeof(pf->veb[i]->stats_offsets)); 527 pf->veb[i]->stat_offsets_loaded = false; 528 } 529 } 530 } 531 532 /** 533 * i40e_stat_update48 - read and update a 48 bit stat from the chip 534 * @hw: ptr to the hardware info 535 * @hireg: the high 32 bit reg to read 536 * @loreg: the low 32 bit reg to read 537 * @offset_loaded: has the initial offset been loaded yet 538 * @offset: ptr to current offset value 539 * @stat: ptr to the stat 540 * 541 * Since the device stats are not reset at PFReset, they likely will not 542 * be zeroed when the driver starts. We'll save the first values read 543 * and use them as offsets to be subtracted from the raw values in order 544 * to report stats that count from zero. In the process, we also manage 545 * the potential roll-over. 546 **/ 547 static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 548 bool offset_loaded, u64 *offset, u64 *stat) 549 { 550 u64 new_data; 551 552 if (hw->device_id == I40E_DEV_ID_QEMU) { 553 new_data = rd32(hw, loreg); 554 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 555 } else { 556 new_data = rd64(hw, loreg); 557 } 558 if (!offset_loaded) 559 *offset = new_data; 560 if (likely(new_data >= *offset)) 561 *stat = new_data - *offset; 562 else 563 *stat = (new_data + BIT_ULL(48)) - *offset; 564 *stat &= 0xFFFFFFFFFFFFULL; 565 } 566 567 /** 568 * i40e_stat_update32 - read and update a 32 bit stat from the chip 569 * @hw: ptr to the hardware info 570 * @reg: the hw reg to read 571 * @offset_loaded: has the initial offset been loaded yet 572 * @offset: ptr to current offset value 573 * @stat: ptr to the stat 574 **/ 575 static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, 576 bool offset_loaded, u64 *offset, u64 *stat) 577 { 578 u32 new_data; 579 580 new_data = rd32(hw, reg); 581 if (!offset_loaded) 582 *offset = new_data; 583 if (likely(new_data >= *offset)) 584 *stat = (u32)(new_data - *offset); 585 else 586 *stat = (u32)((new_data + BIT_ULL(32)) - *offset); 587 } 588 589 /** 590 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. 591 * @vsi: the VSI to be updated 592 **/ 593 void i40e_update_eth_stats(struct i40e_vsi *vsi) 594 { 595 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); 596 struct i40e_pf *pf = vsi->back; 597 struct i40e_hw *hw = &pf->hw; 598 struct i40e_eth_stats *oes; 599 struct i40e_eth_stats *es; /* device's eth stats */ 600 601 es = &vsi->eth_stats; 602 oes = &vsi->eth_stats_offsets; 603 604 /* Gather up the stats that the hw collects */ 605 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 606 vsi->stat_offsets_loaded, 607 &oes->tx_errors, &es->tx_errors); 608 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 609 vsi->stat_offsets_loaded, 610 &oes->rx_discards, &es->rx_discards); 611 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), 612 vsi->stat_offsets_loaded, 613 &oes->rx_unknown_protocol, &es->rx_unknown_protocol); 614 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 615 vsi->stat_offsets_loaded, 616 &oes->tx_errors, &es->tx_errors); 617 618 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 619 I40E_GLV_GORCL(stat_idx), 620 vsi->stat_offsets_loaded, 621 &oes->rx_bytes, &es->rx_bytes); 622 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 623 I40E_GLV_UPRCL(stat_idx), 624 vsi->stat_offsets_loaded, 625 &oes->rx_unicast, &es->rx_unicast); 626 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 627 I40E_GLV_MPRCL(stat_idx), 628 vsi->stat_offsets_loaded, 629 &oes->rx_multicast, &es->rx_multicast); 630 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 631 I40E_GLV_BPRCL(stat_idx), 632 vsi->stat_offsets_loaded, 633 &oes->rx_broadcast, &es->rx_broadcast); 634 635 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 636 I40E_GLV_GOTCL(stat_idx), 637 vsi->stat_offsets_loaded, 638 &oes->tx_bytes, &es->tx_bytes); 639 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 640 I40E_GLV_UPTCL(stat_idx), 641 vsi->stat_offsets_loaded, 642 &oes->tx_unicast, &es->tx_unicast); 643 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 644 I40E_GLV_MPTCL(stat_idx), 645 vsi->stat_offsets_loaded, 646 &oes->tx_multicast, &es->tx_multicast); 647 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 648 I40E_GLV_BPTCL(stat_idx), 649 vsi->stat_offsets_loaded, 650 &oes->tx_broadcast, &es->tx_broadcast); 651 vsi->stat_offsets_loaded = true; 652 } 653 654 /** 655 * i40e_update_veb_stats - Update Switch component statistics 656 * @veb: the VEB being updated 657 **/ 658 static void i40e_update_veb_stats(struct i40e_veb *veb) 659 { 660 struct i40e_pf *pf = veb->pf; 661 struct i40e_hw *hw = &pf->hw; 662 struct i40e_eth_stats *oes; 663 struct i40e_eth_stats *es; /* device's eth stats */ 664 struct i40e_veb_tc_stats *veb_oes; 665 struct i40e_veb_tc_stats *veb_es; 666 int i, idx = 0; 667 668 idx = veb->stats_idx; 669 es = &veb->stats; 670 oes = &veb->stats_offsets; 671 veb_es = &veb->tc_stats; 672 veb_oes = &veb->tc_stats_offsets; 673 674 /* Gather up the stats that the hw collects */ 675 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), 676 veb->stat_offsets_loaded, 677 &oes->tx_discards, &es->tx_discards); 678 if (hw->revision_id > 0) 679 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), 680 veb->stat_offsets_loaded, 681 &oes->rx_unknown_protocol, 682 &es->rx_unknown_protocol); 683 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), 684 veb->stat_offsets_loaded, 685 &oes->rx_bytes, &es->rx_bytes); 686 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), 687 veb->stat_offsets_loaded, 688 &oes->rx_unicast, &es->rx_unicast); 689 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), 690 veb->stat_offsets_loaded, 691 &oes->rx_multicast, &es->rx_multicast); 692 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), 693 veb->stat_offsets_loaded, 694 &oes->rx_broadcast, &es->rx_broadcast); 695 696 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), 697 veb->stat_offsets_loaded, 698 &oes->tx_bytes, &es->tx_bytes); 699 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), 700 veb->stat_offsets_loaded, 701 &oes->tx_unicast, &es->tx_unicast); 702 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), 703 veb->stat_offsets_loaded, 704 &oes->tx_multicast, &es->tx_multicast); 705 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), 706 veb->stat_offsets_loaded, 707 &oes->tx_broadcast, &es->tx_broadcast); 708 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 709 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), 710 I40E_GLVEBTC_RPCL(i, idx), 711 veb->stat_offsets_loaded, 712 &veb_oes->tc_rx_packets[i], 713 &veb_es->tc_rx_packets[i]); 714 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), 715 I40E_GLVEBTC_RBCL(i, idx), 716 veb->stat_offsets_loaded, 717 &veb_oes->tc_rx_bytes[i], 718 &veb_es->tc_rx_bytes[i]); 719 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), 720 I40E_GLVEBTC_TPCL(i, idx), 721 veb->stat_offsets_loaded, 722 &veb_oes->tc_tx_packets[i], 723 &veb_es->tc_tx_packets[i]); 724 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), 725 I40E_GLVEBTC_TBCL(i, idx), 726 veb->stat_offsets_loaded, 727 &veb_oes->tc_tx_bytes[i], 728 &veb_es->tc_tx_bytes[i]); 729 } 730 veb->stat_offsets_loaded = true; 731 } 732 733 #ifdef I40E_FCOE 734 /** 735 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters. 736 * @vsi: the VSI that is capable of doing FCoE 737 **/ 738 static void i40e_update_fcoe_stats(struct i40e_vsi *vsi) 739 { 740 struct i40e_pf *pf = vsi->back; 741 struct i40e_hw *hw = &pf->hw; 742 struct i40e_fcoe_stats *ofs; 743 struct i40e_fcoe_stats *fs; /* device's eth stats */ 744 int idx; 745 746 if (vsi->type != I40E_VSI_FCOE) 747 return; 748 749 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET; 750 fs = &vsi->fcoe_stats; 751 ofs = &vsi->fcoe_stats_offsets; 752 753 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx), 754 vsi->fcoe_stat_offsets_loaded, 755 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets); 756 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx), 757 vsi->fcoe_stat_offsets_loaded, 758 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords); 759 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx), 760 vsi->fcoe_stat_offsets_loaded, 761 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped); 762 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx), 763 vsi->fcoe_stat_offsets_loaded, 764 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets); 765 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx), 766 vsi->fcoe_stat_offsets_loaded, 767 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords); 768 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx), 769 vsi->fcoe_stat_offsets_loaded, 770 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc); 771 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx), 772 vsi->fcoe_stat_offsets_loaded, 773 &ofs->fcoe_last_error, &fs->fcoe_last_error); 774 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx), 775 vsi->fcoe_stat_offsets_loaded, 776 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count); 777 778 vsi->fcoe_stat_offsets_loaded = true; 779 } 780 781 #endif 782 /** 783 * i40e_update_vsi_stats - Update the vsi statistics counters. 784 * @vsi: the VSI to be updated 785 * 786 * There are a few instances where we store the same stat in a 787 * couple of different structs. This is partly because we have 788 * the netdev stats that need to be filled out, which is slightly 789 * different from the "eth_stats" defined by the chip and used in 790 * VF communications. We sort it out here. 791 **/ 792 static void i40e_update_vsi_stats(struct i40e_vsi *vsi) 793 { 794 struct i40e_pf *pf = vsi->back; 795 struct rtnl_link_stats64 *ons; 796 struct rtnl_link_stats64 *ns; /* netdev stats */ 797 struct i40e_eth_stats *oes; 798 struct i40e_eth_stats *es; /* device's eth stats */ 799 u32 tx_restart, tx_busy; 800 u64 tx_lost_interrupt; 801 struct i40e_ring *p; 802 u32 rx_page, rx_buf; 803 u64 bytes, packets; 804 unsigned int start; 805 u64 tx_linearize; 806 u64 tx_force_wb; 807 u64 rx_p, rx_b; 808 u64 tx_p, tx_b; 809 u16 q; 810 811 if (test_bit(__I40E_DOWN, &vsi->state) || 812 test_bit(__I40E_CONFIG_BUSY, &pf->state)) 813 return; 814 815 ns = i40e_get_vsi_stats_struct(vsi); 816 ons = &vsi->net_stats_offsets; 817 es = &vsi->eth_stats; 818 oes = &vsi->eth_stats_offsets; 819 820 /* Gather up the netdev and vsi stats that the driver collects 821 * on the fly during packet processing 822 */ 823 rx_b = rx_p = 0; 824 tx_b = tx_p = 0; 825 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; 826 tx_lost_interrupt = 0; 827 rx_page = 0; 828 rx_buf = 0; 829 rcu_read_lock(); 830 for (q = 0; q < vsi->num_queue_pairs; q++) { 831 /* locate Tx ring */ 832 p = ACCESS_ONCE(vsi->tx_rings[q]); 833 834 do { 835 start = u64_stats_fetch_begin_irq(&p->syncp); 836 packets = p->stats.packets; 837 bytes = p->stats.bytes; 838 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 839 tx_b += bytes; 840 tx_p += packets; 841 tx_restart += p->tx_stats.restart_queue; 842 tx_busy += p->tx_stats.tx_busy; 843 tx_linearize += p->tx_stats.tx_linearize; 844 tx_force_wb += p->tx_stats.tx_force_wb; 845 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt; 846 847 /* Rx queue is part of the same block as Tx queue */ 848 p = &p[1]; 849 do { 850 start = u64_stats_fetch_begin_irq(&p->syncp); 851 packets = p->stats.packets; 852 bytes = p->stats.bytes; 853 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 854 rx_b += bytes; 855 rx_p += packets; 856 rx_buf += p->rx_stats.alloc_buff_failed; 857 rx_page += p->rx_stats.alloc_page_failed; 858 } 859 rcu_read_unlock(); 860 vsi->tx_restart = tx_restart; 861 vsi->tx_busy = tx_busy; 862 vsi->tx_linearize = tx_linearize; 863 vsi->tx_force_wb = tx_force_wb; 864 vsi->tx_lost_interrupt = tx_lost_interrupt; 865 vsi->rx_page_failed = rx_page; 866 vsi->rx_buf_failed = rx_buf; 867 868 ns->rx_packets = rx_p; 869 ns->rx_bytes = rx_b; 870 ns->tx_packets = tx_p; 871 ns->tx_bytes = tx_b; 872 873 /* update netdev stats from eth stats */ 874 i40e_update_eth_stats(vsi); 875 ons->tx_errors = oes->tx_errors; 876 ns->tx_errors = es->tx_errors; 877 ons->multicast = oes->rx_multicast; 878 ns->multicast = es->rx_multicast; 879 ons->rx_dropped = oes->rx_discards; 880 ns->rx_dropped = es->rx_discards; 881 ons->tx_dropped = oes->tx_discards; 882 ns->tx_dropped = es->tx_discards; 883 884 /* pull in a couple PF stats if this is the main vsi */ 885 if (vsi == pf->vsi[pf->lan_vsi]) { 886 ns->rx_crc_errors = pf->stats.crc_errors; 887 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; 888 ns->rx_length_errors = pf->stats.rx_length_errors; 889 } 890 } 891 892 /** 893 * i40e_update_pf_stats - Update the PF statistics counters. 894 * @pf: the PF to be updated 895 **/ 896 static void i40e_update_pf_stats(struct i40e_pf *pf) 897 { 898 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 899 struct i40e_hw_port_stats *nsd = &pf->stats; 900 struct i40e_hw *hw = &pf->hw; 901 u32 val; 902 int i; 903 904 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 905 I40E_GLPRT_GORCL(hw->port), 906 pf->stat_offsets_loaded, 907 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 908 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 909 I40E_GLPRT_GOTCL(hw->port), 910 pf->stat_offsets_loaded, 911 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 912 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 913 pf->stat_offsets_loaded, 914 &osd->eth.rx_discards, 915 &nsd->eth.rx_discards); 916 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 917 I40E_GLPRT_UPRCL(hw->port), 918 pf->stat_offsets_loaded, 919 &osd->eth.rx_unicast, 920 &nsd->eth.rx_unicast); 921 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 922 I40E_GLPRT_MPRCL(hw->port), 923 pf->stat_offsets_loaded, 924 &osd->eth.rx_multicast, 925 &nsd->eth.rx_multicast); 926 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 927 I40E_GLPRT_BPRCL(hw->port), 928 pf->stat_offsets_loaded, 929 &osd->eth.rx_broadcast, 930 &nsd->eth.rx_broadcast); 931 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 932 I40E_GLPRT_UPTCL(hw->port), 933 pf->stat_offsets_loaded, 934 &osd->eth.tx_unicast, 935 &nsd->eth.tx_unicast); 936 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 937 I40E_GLPRT_MPTCL(hw->port), 938 pf->stat_offsets_loaded, 939 &osd->eth.tx_multicast, 940 &nsd->eth.tx_multicast); 941 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 942 I40E_GLPRT_BPTCL(hw->port), 943 pf->stat_offsets_loaded, 944 &osd->eth.tx_broadcast, 945 &nsd->eth.tx_broadcast); 946 947 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 948 pf->stat_offsets_loaded, 949 &osd->tx_dropped_link_down, 950 &nsd->tx_dropped_link_down); 951 952 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 953 pf->stat_offsets_loaded, 954 &osd->crc_errors, &nsd->crc_errors); 955 956 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 957 pf->stat_offsets_loaded, 958 &osd->illegal_bytes, &nsd->illegal_bytes); 959 960 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 961 pf->stat_offsets_loaded, 962 &osd->mac_local_faults, 963 &nsd->mac_local_faults); 964 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 965 pf->stat_offsets_loaded, 966 &osd->mac_remote_faults, 967 &nsd->mac_remote_faults); 968 969 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 970 pf->stat_offsets_loaded, 971 &osd->rx_length_errors, 972 &nsd->rx_length_errors); 973 974 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 975 pf->stat_offsets_loaded, 976 &osd->link_xon_rx, &nsd->link_xon_rx); 977 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 978 pf->stat_offsets_loaded, 979 &osd->link_xon_tx, &nsd->link_xon_tx); 980 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 981 pf->stat_offsets_loaded, 982 &osd->link_xoff_rx, &nsd->link_xoff_rx); 983 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 984 pf->stat_offsets_loaded, 985 &osd->link_xoff_tx, &nsd->link_xoff_tx); 986 987 for (i = 0; i < 8; i++) { 988 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), 989 pf->stat_offsets_loaded, 990 &osd->priority_xoff_rx[i], 991 &nsd->priority_xoff_rx[i]); 992 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), 993 pf->stat_offsets_loaded, 994 &osd->priority_xon_rx[i], 995 &nsd->priority_xon_rx[i]); 996 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), 997 pf->stat_offsets_loaded, 998 &osd->priority_xon_tx[i], 999 &nsd->priority_xon_tx[i]); 1000 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), 1001 pf->stat_offsets_loaded, 1002 &osd->priority_xoff_tx[i], 1003 &nsd->priority_xoff_tx[i]); 1004 i40e_stat_update32(hw, 1005 I40E_GLPRT_RXON2OFFCNT(hw->port, i), 1006 pf->stat_offsets_loaded, 1007 &osd->priority_xon_2_xoff[i], 1008 &nsd->priority_xon_2_xoff[i]); 1009 } 1010 1011 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 1012 I40E_GLPRT_PRC64L(hw->port), 1013 pf->stat_offsets_loaded, 1014 &osd->rx_size_64, &nsd->rx_size_64); 1015 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 1016 I40E_GLPRT_PRC127L(hw->port), 1017 pf->stat_offsets_loaded, 1018 &osd->rx_size_127, &nsd->rx_size_127); 1019 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 1020 I40E_GLPRT_PRC255L(hw->port), 1021 pf->stat_offsets_loaded, 1022 &osd->rx_size_255, &nsd->rx_size_255); 1023 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 1024 I40E_GLPRT_PRC511L(hw->port), 1025 pf->stat_offsets_loaded, 1026 &osd->rx_size_511, &nsd->rx_size_511); 1027 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 1028 I40E_GLPRT_PRC1023L(hw->port), 1029 pf->stat_offsets_loaded, 1030 &osd->rx_size_1023, &nsd->rx_size_1023); 1031 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 1032 I40E_GLPRT_PRC1522L(hw->port), 1033 pf->stat_offsets_loaded, 1034 &osd->rx_size_1522, &nsd->rx_size_1522); 1035 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 1036 I40E_GLPRT_PRC9522L(hw->port), 1037 pf->stat_offsets_loaded, 1038 &osd->rx_size_big, &nsd->rx_size_big); 1039 1040 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 1041 I40E_GLPRT_PTC64L(hw->port), 1042 pf->stat_offsets_loaded, 1043 &osd->tx_size_64, &nsd->tx_size_64); 1044 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 1045 I40E_GLPRT_PTC127L(hw->port), 1046 pf->stat_offsets_loaded, 1047 &osd->tx_size_127, &nsd->tx_size_127); 1048 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 1049 I40E_GLPRT_PTC255L(hw->port), 1050 pf->stat_offsets_loaded, 1051 &osd->tx_size_255, &nsd->tx_size_255); 1052 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 1053 I40E_GLPRT_PTC511L(hw->port), 1054 pf->stat_offsets_loaded, 1055 &osd->tx_size_511, &nsd->tx_size_511); 1056 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 1057 I40E_GLPRT_PTC1023L(hw->port), 1058 pf->stat_offsets_loaded, 1059 &osd->tx_size_1023, &nsd->tx_size_1023); 1060 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 1061 I40E_GLPRT_PTC1522L(hw->port), 1062 pf->stat_offsets_loaded, 1063 &osd->tx_size_1522, &nsd->tx_size_1522); 1064 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 1065 I40E_GLPRT_PTC9522L(hw->port), 1066 pf->stat_offsets_loaded, 1067 &osd->tx_size_big, &nsd->tx_size_big); 1068 1069 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 1070 pf->stat_offsets_loaded, 1071 &osd->rx_undersize, &nsd->rx_undersize); 1072 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 1073 pf->stat_offsets_loaded, 1074 &osd->rx_fragments, &nsd->rx_fragments); 1075 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 1076 pf->stat_offsets_loaded, 1077 &osd->rx_oversize, &nsd->rx_oversize); 1078 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 1079 pf->stat_offsets_loaded, 1080 &osd->rx_jabber, &nsd->rx_jabber); 1081 1082 /* FDIR stats */ 1083 i40e_stat_update32(hw, 1084 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)), 1085 pf->stat_offsets_loaded, 1086 &osd->fd_atr_match, &nsd->fd_atr_match); 1087 i40e_stat_update32(hw, 1088 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)), 1089 pf->stat_offsets_loaded, 1090 &osd->fd_sb_match, &nsd->fd_sb_match); 1091 i40e_stat_update32(hw, 1092 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)), 1093 pf->stat_offsets_loaded, 1094 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match); 1095 1096 val = rd32(hw, I40E_PRTPM_EEE_STAT); 1097 nsd->tx_lpi_status = 1098 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> 1099 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; 1100 nsd->rx_lpi_status = 1101 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> 1102 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; 1103 i40e_stat_update32(hw, I40E_PRTPM_TLPIC, 1104 pf->stat_offsets_loaded, 1105 &osd->tx_lpi_count, &nsd->tx_lpi_count); 1106 i40e_stat_update32(hw, I40E_PRTPM_RLPIC, 1107 pf->stat_offsets_loaded, 1108 &osd->rx_lpi_count, &nsd->rx_lpi_count); 1109 1110 if (pf->flags & I40E_FLAG_FD_SB_ENABLED && 1111 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) 1112 nsd->fd_sb_status = true; 1113 else 1114 nsd->fd_sb_status = false; 1115 1116 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && 1117 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 1118 nsd->fd_atr_status = true; 1119 else 1120 nsd->fd_atr_status = false; 1121 1122 pf->stat_offsets_loaded = true; 1123 } 1124 1125 /** 1126 * i40e_update_stats - Update the various statistics counters. 1127 * @vsi: the VSI to be updated 1128 * 1129 * Update the various stats for this VSI and its related entities. 1130 **/ 1131 void i40e_update_stats(struct i40e_vsi *vsi) 1132 { 1133 struct i40e_pf *pf = vsi->back; 1134 1135 if (vsi == pf->vsi[pf->lan_vsi]) 1136 i40e_update_pf_stats(pf); 1137 1138 i40e_update_vsi_stats(vsi); 1139 #ifdef I40E_FCOE 1140 i40e_update_fcoe_stats(vsi); 1141 #endif 1142 } 1143 1144 /** 1145 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter 1146 * @vsi: the VSI to be searched 1147 * @macaddr: the MAC address 1148 * @vlan: the vlan 1149 * @is_vf: make sure its a VF filter, else doesn't matter 1150 * @is_netdev: make sure its a netdev filter, else doesn't matter 1151 * 1152 * Returns ptr to the filter object or NULL 1153 **/ 1154 static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, 1155 u8 *macaddr, s16 vlan, 1156 bool is_vf, bool is_netdev) 1157 { 1158 struct i40e_mac_filter *f; 1159 1160 if (!vsi || !macaddr) 1161 return NULL; 1162 1163 list_for_each_entry(f, &vsi->mac_filter_list, list) { 1164 if ((ether_addr_equal(macaddr, f->macaddr)) && 1165 (vlan == f->vlan) && 1166 (!is_vf || f->is_vf) && 1167 (!is_netdev || f->is_netdev)) 1168 return f; 1169 } 1170 return NULL; 1171 } 1172 1173 /** 1174 * i40e_find_mac - Find a mac addr in the macvlan filters list 1175 * @vsi: the VSI to be searched 1176 * @macaddr: the MAC address we are searching for 1177 * @is_vf: make sure its a VF filter, else doesn't matter 1178 * @is_netdev: make sure its a netdev filter, else doesn't matter 1179 * 1180 * Returns the first filter with the provided MAC address or NULL if 1181 * MAC address was not found 1182 **/ 1183 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr, 1184 bool is_vf, bool is_netdev) 1185 { 1186 struct i40e_mac_filter *f; 1187 1188 if (!vsi || !macaddr) 1189 return NULL; 1190 1191 list_for_each_entry(f, &vsi->mac_filter_list, list) { 1192 if ((ether_addr_equal(macaddr, f->macaddr)) && 1193 (!is_vf || f->is_vf) && 1194 (!is_netdev || f->is_netdev)) 1195 return f; 1196 } 1197 return NULL; 1198 } 1199 1200 /** 1201 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode 1202 * @vsi: the VSI to be searched 1203 * 1204 * Returns true if VSI is in vlan mode or false otherwise 1205 **/ 1206 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) 1207 { 1208 struct i40e_mac_filter *f; 1209 1210 /* Only -1 for all the filters denotes not in vlan mode 1211 * so we have to go through all the list in order to make sure 1212 */ 1213 list_for_each_entry(f, &vsi->mac_filter_list, list) { 1214 if (f->vlan >= 0 || vsi->info.pvid) 1215 return true; 1216 } 1217 1218 return false; 1219 } 1220 1221 /** 1222 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans 1223 * @vsi: the VSI to be searched 1224 * @macaddr: the mac address to be filtered 1225 * @is_vf: true if it is a VF 1226 * @is_netdev: true if it is a netdev 1227 * 1228 * Goes through all the macvlan filters and adds a 1229 * macvlan filter for each unique vlan that already exists 1230 * 1231 * Returns first filter found on success, else NULL 1232 **/ 1233 struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr, 1234 bool is_vf, bool is_netdev) 1235 { 1236 struct i40e_mac_filter *f; 1237 1238 list_for_each_entry(f, &vsi->mac_filter_list, list) { 1239 if (vsi->info.pvid) 1240 f->vlan = le16_to_cpu(vsi->info.pvid); 1241 if (!i40e_find_filter(vsi, macaddr, f->vlan, 1242 is_vf, is_netdev)) { 1243 if (!i40e_add_filter(vsi, macaddr, f->vlan, 1244 is_vf, is_netdev)) 1245 return NULL; 1246 } 1247 } 1248 1249 return list_first_entry_or_null(&vsi->mac_filter_list, 1250 struct i40e_mac_filter, list); 1251 } 1252 1253 /** 1254 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS 1255 * @vsi: the VSI to be searched 1256 * @macaddr: the mac address to be removed 1257 * @is_vf: true if it is a VF 1258 * @is_netdev: true if it is a netdev 1259 * 1260 * Removes a given MAC address from a VSI, regardless of VLAN 1261 * 1262 * Returns 0 for success, or error 1263 **/ 1264 int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr, 1265 bool is_vf, bool is_netdev) 1266 { 1267 struct i40e_mac_filter *f = NULL; 1268 int changed = 0; 1269 1270 WARN(!spin_is_locked(&vsi->mac_filter_list_lock), 1271 "Missing mac_filter_list_lock\n"); 1272 list_for_each_entry(f, &vsi->mac_filter_list, list) { 1273 if ((ether_addr_equal(macaddr, f->macaddr)) && 1274 (is_vf == f->is_vf) && 1275 (is_netdev == f->is_netdev)) { 1276 f->counter--; 1277 changed = 1; 1278 if (f->counter == 0) 1279 f->state = I40E_FILTER_REMOVE; 1280 } 1281 } 1282 if (changed) { 1283 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 1284 vsi->back->flags |= I40E_FLAG_FILTER_SYNC; 1285 return 0; 1286 } 1287 return -ENOENT; 1288 } 1289 1290 /** 1291 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM 1292 * @vsi: the PF Main VSI - inappropriate for any other VSI 1293 * @macaddr: the MAC address 1294 * 1295 * Remove whatever filter the firmware set up so the driver can manage 1296 * its own filtering intelligently. 1297 **/ 1298 static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) 1299 { 1300 struct i40e_aqc_remove_macvlan_element_data element; 1301 struct i40e_pf *pf = vsi->back; 1302 1303 /* Only appropriate for the PF main VSI */ 1304 if (vsi->type != I40E_VSI_MAIN) 1305 return; 1306 1307 memset(&element, 0, sizeof(element)); 1308 ether_addr_copy(element.mac_addr, macaddr); 1309 element.vlan_tag = 0; 1310 /* Ignore error returns, some firmware does it this way... */ 1311 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 1312 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); 1313 1314 memset(&element, 0, sizeof(element)); 1315 ether_addr_copy(element.mac_addr, macaddr); 1316 element.vlan_tag = 0; 1317 /* ...and some firmware does it this way. */ 1318 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | 1319 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 1320 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); 1321 } 1322 1323 /** 1324 * i40e_add_filter - Add a mac/vlan filter to the VSI 1325 * @vsi: the VSI to be searched 1326 * @macaddr: the MAC address 1327 * @vlan: the vlan 1328 * @is_vf: make sure its a VF filter, else doesn't matter 1329 * @is_netdev: make sure its a netdev filter, else doesn't matter 1330 * 1331 * Returns ptr to the filter object or NULL when no memory available. 1332 * 1333 * NOTE: This function is expected to be called with mac_filter_list_lock 1334 * being held. 1335 **/ 1336 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1337 u8 *macaddr, s16 vlan, 1338 bool is_vf, bool is_netdev) 1339 { 1340 struct i40e_mac_filter *f; 1341 int changed = false; 1342 1343 if (!vsi || !macaddr) 1344 return NULL; 1345 1346 /* Do not allow broadcast filter to be added since broadcast filter 1347 * is added as part of add VSI for any newly created VSI except 1348 * FDIR VSI 1349 */ 1350 if (is_broadcast_ether_addr(macaddr)) 1351 return NULL; 1352 1353 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev); 1354 if (!f) { 1355 f = kzalloc(sizeof(*f), GFP_ATOMIC); 1356 if (!f) 1357 goto add_filter_out; 1358 1359 ether_addr_copy(f->macaddr, macaddr); 1360 f->vlan = vlan; 1361 /* If we're in overflow promisc mode, set the state directly 1362 * to failed, so we don't bother to try sending the filter 1363 * to the hardware. 1364 */ 1365 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state)) 1366 f->state = I40E_FILTER_FAILED; 1367 else 1368 f->state = I40E_FILTER_NEW; 1369 changed = true; 1370 INIT_LIST_HEAD(&f->list); 1371 list_add_tail(&f->list, &vsi->mac_filter_list); 1372 } 1373 1374 /* increment counter and add a new flag if needed */ 1375 if (is_vf) { 1376 if (!f->is_vf) { 1377 f->is_vf = true; 1378 f->counter++; 1379 } 1380 } else if (is_netdev) { 1381 if (!f->is_netdev) { 1382 f->is_netdev = true; 1383 f->counter++; 1384 } 1385 } else { 1386 f->counter++; 1387 } 1388 1389 if (changed) { 1390 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 1391 vsi->back->flags |= I40E_FLAG_FILTER_SYNC; 1392 } 1393 1394 add_filter_out: 1395 return f; 1396 } 1397 1398 /** 1399 * i40e_del_filter - Remove a mac/vlan filter from the VSI 1400 * @vsi: the VSI to be searched 1401 * @macaddr: the MAC address 1402 * @vlan: the vlan 1403 * @is_vf: make sure it's a VF filter, else doesn't matter 1404 * @is_netdev: make sure it's a netdev filter, else doesn't matter 1405 * 1406 * NOTE: This function is expected to be called with mac_filter_list_lock 1407 * being held. 1408 * ANOTHER NOTE: This function MUST be called from within the context of 1409 * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() 1410 * instead of list_for_each_entry(). 1411 **/ 1412 void i40e_del_filter(struct i40e_vsi *vsi, 1413 u8 *macaddr, s16 vlan, 1414 bool is_vf, bool is_netdev) 1415 { 1416 struct i40e_mac_filter *f; 1417 1418 if (!vsi || !macaddr) 1419 return; 1420 1421 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev); 1422 if (!f || f->counter == 0) 1423 return; 1424 1425 if (is_vf) { 1426 if (f->is_vf) { 1427 f->is_vf = false; 1428 f->counter--; 1429 } 1430 } else if (is_netdev) { 1431 if (f->is_netdev) { 1432 f->is_netdev = false; 1433 f->counter--; 1434 } 1435 } else { 1436 /* make sure we don't remove a filter in use by VF or netdev */ 1437 int min_f = 0; 1438 1439 min_f += (f->is_vf ? 1 : 0); 1440 min_f += (f->is_netdev ? 1 : 0); 1441 1442 if (f->counter > min_f) 1443 f->counter--; 1444 } 1445 1446 /* counter == 0 tells sync_filters_subtask to 1447 * remove the filter from the firmware's list 1448 */ 1449 if (f->counter == 0) { 1450 if ((f->state == I40E_FILTER_FAILED) || 1451 (f->state == I40E_FILTER_NEW)) { 1452 /* this one never got added by the FW. Just remove it, 1453 * no need to sync anything. 1454 */ 1455 list_del(&f->list); 1456 kfree(f); 1457 } else { 1458 f->state = I40E_FILTER_REMOVE; 1459 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 1460 vsi->back->flags |= I40E_FLAG_FILTER_SYNC; 1461 } 1462 } 1463 } 1464 1465 /** 1466 * i40e_set_mac - NDO callback to set mac address 1467 * @netdev: network interface device structure 1468 * @p: pointer to an address structure 1469 * 1470 * Returns 0 on success, negative on failure 1471 **/ 1472 #ifdef I40E_FCOE 1473 int i40e_set_mac(struct net_device *netdev, void *p) 1474 #else 1475 static int i40e_set_mac(struct net_device *netdev, void *p) 1476 #endif 1477 { 1478 struct i40e_netdev_priv *np = netdev_priv(netdev); 1479 struct i40e_vsi *vsi = np->vsi; 1480 struct i40e_pf *pf = vsi->back; 1481 struct i40e_hw *hw = &pf->hw; 1482 struct sockaddr *addr = p; 1483 1484 if (!is_valid_ether_addr(addr->sa_data)) 1485 return -EADDRNOTAVAIL; 1486 1487 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { 1488 netdev_info(netdev, "already using mac address %pM\n", 1489 addr->sa_data); 1490 return 0; 1491 } 1492 1493 if (test_bit(__I40E_DOWN, &vsi->back->state) || 1494 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) 1495 return -EADDRNOTAVAIL; 1496 1497 if (ether_addr_equal(hw->mac.addr, addr->sa_data)) 1498 netdev_info(netdev, "returning to hw mac address %pM\n", 1499 hw->mac.addr); 1500 else 1501 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); 1502 1503 spin_lock_bh(&vsi->mac_filter_list_lock); 1504 i40e_del_mac_all_vlan(vsi, netdev->dev_addr, false, true); 1505 i40e_put_mac_in_vlan(vsi, addr->sa_data, false, true); 1506 spin_unlock_bh(&vsi->mac_filter_list_lock); 1507 ether_addr_copy(netdev->dev_addr, addr->sa_data); 1508 if (vsi->type == I40E_VSI_MAIN) { 1509 i40e_status ret; 1510 1511 ret = i40e_aq_mac_address_write(&vsi->back->hw, 1512 I40E_AQC_WRITE_TYPE_LAA_WOL, 1513 addr->sa_data, NULL); 1514 if (ret) 1515 netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", 1516 i40e_stat_str(hw, ret), 1517 i40e_aq_str(hw, hw->aq.asq_last_status)); 1518 } 1519 1520 /* schedule our worker thread which will take care of 1521 * applying the new filter changes 1522 */ 1523 i40e_service_event_schedule(vsi->back); 1524 return 0; 1525 } 1526 1527 /** 1528 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc 1529 * @vsi: the VSI being setup 1530 * @ctxt: VSI context structure 1531 * @enabled_tc: Enabled TCs bitmap 1532 * @is_add: True if called before Add VSI 1533 * 1534 * Setup VSI queue mapping for enabled traffic classes. 1535 **/ 1536 #ifdef I40E_FCOE 1537 void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, 1538 struct i40e_vsi_context *ctxt, 1539 u8 enabled_tc, 1540 bool is_add) 1541 #else 1542 static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, 1543 struct i40e_vsi_context *ctxt, 1544 u8 enabled_tc, 1545 bool is_add) 1546 #endif 1547 { 1548 struct i40e_pf *pf = vsi->back; 1549 u16 sections = 0; 1550 u8 netdev_tc = 0; 1551 u16 numtc = 0; 1552 u16 qcount; 1553 u8 offset; 1554 u16 qmap; 1555 int i; 1556 u16 num_tc_qps = 0; 1557 1558 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 1559 offset = 0; 1560 1561 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { 1562 /* Find numtc from enabled TC bitmap */ 1563 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 1564 if (enabled_tc & BIT(i)) /* TC is enabled */ 1565 numtc++; 1566 } 1567 if (!numtc) { 1568 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); 1569 numtc = 1; 1570 } 1571 } else { 1572 /* At least TC0 is enabled in case of non-DCB case */ 1573 numtc = 1; 1574 } 1575 1576 vsi->tc_config.numtc = numtc; 1577 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; 1578 /* Number of queues per enabled TC */ 1579 qcount = vsi->alloc_queue_pairs; 1580 1581 num_tc_qps = qcount / numtc; 1582 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf)); 1583 1584 /* Setup queue offset/count for all TCs for given VSI */ 1585 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 1586 /* See if the given TC is enabled for the given VSI */ 1587 if (vsi->tc_config.enabled_tc & BIT(i)) { 1588 /* TC is enabled */ 1589 int pow, num_qps; 1590 1591 switch (vsi->type) { 1592 case I40E_VSI_MAIN: 1593 qcount = min_t(int, pf->alloc_rss_size, 1594 num_tc_qps); 1595 break; 1596 #ifdef I40E_FCOE 1597 case I40E_VSI_FCOE: 1598 qcount = num_tc_qps; 1599 break; 1600 #endif 1601 case I40E_VSI_FDIR: 1602 case I40E_VSI_SRIOV: 1603 case I40E_VSI_VMDQ2: 1604 default: 1605 qcount = num_tc_qps; 1606 WARN_ON(i != 0); 1607 break; 1608 } 1609 vsi->tc_config.tc_info[i].qoffset = offset; 1610 vsi->tc_config.tc_info[i].qcount = qcount; 1611 1612 /* find the next higher power-of-2 of num queue pairs */ 1613 num_qps = qcount; 1614 pow = 0; 1615 while (num_qps && (BIT_ULL(pow) < qcount)) { 1616 pow++; 1617 num_qps >>= 1; 1618 } 1619 1620 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; 1621 qmap = 1622 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 1623 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); 1624 1625 offset += qcount; 1626 } else { 1627 /* TC is not enabled so set the offset to 1628 * default queue and allocate one queue 1629 * for the given TC. 1630 */ 1631 vsi->tc_config.tc_info[i].qoffset = 0; 1632 vsi->tc_config.tc_info[i].qcount = 1; 1633 vsi->tc_config.tc_info[i].netdev_tc = 0; 1634 1635 qmap = 0; 1636 } 1637 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); 1638 } 1639 1640 /* Set actual Tx/Rx queue pairs */ 1641 vsi->num_queue_pairs = offset; 1642 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { 1643 if (vsi->req_queue_pairs > 0) 1644 vsi->num_queue_pairs = vsi->req_queue_pairs; 1645 else if (pf->flags & I40E_FLAG_MSIX_ENABLED) 1646 vsi->num_queue_pairs = pf->num_lan_msix; 1647 } 1648 1649 /* Scheduler section valid can only be set for ADD VSI */ 1650 if (is_add) { 1651 sections |= I40E_AQ_VSI_PROP_SCHED_VALID; 1652 1653 ctxt->info.up_enable_bits = enabled_tc; 1654 } 1655 if (vsi->type == I40E_VSI_SRIOV) { 1656 ctxt->info.mapping_flags |= 1657 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 1658 for (i = 0; i < vsi->num_queue_pairs; i++) 1659 ctxt->info.queue_mapping[i] = 1660 cpu_to_le16(vsi->base_queue + i); 1661 } else { 1662 ctxt->info.mapping_flags |= 1663 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); 1664 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); 1665 } 1666 ctxt->info.valid_sections |= cpu_to_le16(sections); 1667 } 1668 1669 /** 1670 * i40e_set_rx_mode - NDO callback to set the netdev filters 1671 * @netdev: network interface device structure 1672 **/ 1673 #ifdef I40E_FCOE 1674 void i40e_set_rx_mode(struct net_device *netdev) 1675 #else 1676 static void i40e_set_rx_mode(struct net_device *netdev) 1677 #endif 1678 { 1679 struct i40e_netdev_priv *np = netdev_priv(netdev); 1680 struct i40e_mac_filter *f, *ftmp; 1681 struct i40e_vsi *vsi = np->vsi; 1682 struct netdev_hw_addr *uca; 1683 struct netdev_hw_addr *mca; 1684 struct netdev_hw_addr *ha; 1685 1686 spin_lock_bh(&vsi->mac_filter_list_lock); 1687 1688 /* add addr if not already in the filter list */ 1689 netdev_for_each_uc_addr(uca, netdev) { 1690 if (!i40e_find_mac(vsi, uca->addr, false, true)) { 1691 if (i40e_is_vsi_in_vlan(vsi)) 1692 i40e_put_mac_in_vlan(vsi, uca->addr, 1693 false, true); 1694 else 1695 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY, 1696 false, true); 1697 } 1698 } 1699 1700 netdev_for_each_mc_addr(mca, netdev) { 1701 if (!i40e_find_mac(vsi, mca->addr, false, true)) { 1702 if (i40e_is_vsi_in_vlan(vsi)) 1703 i40e_put_mac_in_vlan(vsi, mca->addr, 1704 false, true); 1705 else 1706 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY, 1707 false, true); 1708 } 1709 } 1710 1711 /* remove filter if not in netdev list */ 1712 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 1713 1714 if (!f->is_netdev) 1715 continue; 1716 1717 netdev_for_each_mc_addr(mca, netdev) 1718 if (ether_addr_equal(mca->addr, f->macaddr)) 1719 goto bottom_of_search_loop; 1720 1721 netdev_for_each_uc_addr(uca, netdev) 1722 if (ether_addr_equal(uca->addr, f->macaddr)) 1723 goto bottom_of_search_loop; 1724 1725 for_each_dev_addr(netdev, ha) 1726 if (ether_addr_equal(ha->addr, f->macaddr)) 1727 goto bottom_of_search_loop; 1728 1729 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */ 1730 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true); 1731 1732 bottom_of_search_loop: 1733 continue; 1734 } 1735 spin_unlock_bh(&vsi->mac_filter_list_lock); 1736 1737 /* check for other flag changes */ 1738 if (vsi->current_netdev_flags != vsi->netdev->flags) { 1739 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 1740 vsi->back->flags |= I40E_FLAG_FILTER_SYNC; 1741 } 1742 1743 /* schedule our worker thread which will take care of 1744 * applying the new filter changes 1745 */ 1746 i40e_service_event_schedule(vsi->back); 1747 } 1748 1749 /** 1750 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries 1751 * @vsi: pointer to vsi struct 1752 * @from: Pointer to list which contains MAC filter entries - changes to 1753 * those entries needs to be undone. 1754 * 1755 * MAC filter entries from list were slated to be removed from device. 1756 **/ 1757 static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, 1758 struct list_head *from) 1759 { 1760 struct i40e_mac_filter *f, *ftmp; 1761 1762 list_for_each_entry_safe(f, ftmp, from, list) { 1763 /* Move the element back into MAC filter list*/ 1764 list_move_tail(&f->list, &vsi->mac_filter_list); 1765 } 1766 } 1767 1768 /** 1769 * i40e_update_filter_state - Update filter state based on return data 1770 * from firmware 1771 * @count: Number of filters added 1772 * @add_list: return data from fw 1773 * @head: pointer to first filter in current batch 1774 * @aq_err: status from fw 1775 * 1776 * MAC filter entries from list were slated to be added to device. Returns 1777 * number of successful filters. Note that 0 does NOT mean success! 1778 **/ 1779 static int 1780 i40e_update_filter_state(int count, 1781 struct i40e_aqc_add_macvlan_element_data *add_list, 1782 struct i40e_mac_filter *add_head, int aq_err) 1783 { 1784 int retval = 0; 1785 int i; 1786 1787 1788 if (!aq_err) { 1789 retval = count; 1790 /* Everything's good, mark all filters active. */ 1791 for (i = 0; i < count ; i++) { 1792 add_head->state = I40E_FILTER_ACTIVE; 1793 add_head = list_next_entry(add_head, list); 1794 } 1795 } else if (aq_err == I40E_AQ_RC_ENOSPC) { 1796 /* Device ran out of filter space. Check the return value 1797 * for each filter to see which ones are active. 1798 */ 1799 for (i = 0; i < count ; i++) { 1800 if (add_list[i].match_method == 1801 I40E_AQC_MM_ERR_NO_RES) { 1802 add_head->state = I40E_FILTER_FAILED; 1803 } else { 1804 add_head->state = I40E_FILTER_ACTIVE; 1805 retval++; 1806 } 1807 add_head = list_next_entry(add_head, list); 1808 } 1809 } else { 1810 /* Some other horrible thing happened, fail all filters */ 1811 retval = 0; 1812 for (i = 0; i < count ; i++) { 1813 add_head->state = I40E_FILTER_FAILED; 1814 add_head = list_next_entry(add_head, list); 1815 } 1816 } 1817 return retval; 1818 } 1819 1820 /** 1821 * i40e_sync_vsi_filters - Update the VSI filter list to the HW 1822 * @vsi: ptr to the VSI 1823 * 1824 * Push any outstanding VSI filter changes through the AdminQ. 1825 * 1826 * Returns 0 or error value 1827 **/ 1828 int i40e_sync_vsi_filters(struct i40e_vsi *vsi) 1829 { 1830 struct i40e_mac_filter *f, *ftmp, *add_head = NULL; 1831 struct list_head tmp_add_list, tmp_del_list; 1832 struct i40e_hw *hw = &vsi->back->hw; 1833 bool promisc_changed = false; 1834 char vsi_name[16] = "PF"; 1835 int filter_list_len = 0; 1836 u32 changed_flags = 0; 1837 i40e_status aq_ret = 0; 1838 int retval = 0; 1839 struct i40e_pf *pf; 1840 int num_add = 0; 1841 int num_del = 0; 1842 int aq_err = 0; 1843 u16 cmd_flags; 1844 int list_size; 1845 int fcnt; 1846 1847 /* empty array typed pointers, kcalloc later */ 1848 struct i40e_aqc_add_macvlan_element_data *add_list; 1849 struct i40e_aqc_remove_macvlan_element_data *del_list; 1850 1851 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state)) 1852 usleep_range(1000, 2000); 1853 pf = vsi->back; 1854 1855 if (vsi->netdev) { 1856 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; 1857 vsi->current_netdev_flags = vsi->netdev->flags; 1858 } 1859 1860 INIT_LIST_HEAD(&tmp_add_list); 1861 INIT_LIST_HEAD(&tmp_del_list); 1862 1863 if (vsi->type == I40E_VSI_SRIOV) 1864 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); 1865 else if (vsi->type != I40E_VSI_MAIN) 1866 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); 1867 1868 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { 1869 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; 1870 1871 spin_lock_bh(&vsi->mac_filter_list_lock); 1872 /* Create a list of filters to delete. */ 1873 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 1874 if (f->state == I40E_FILTER_REMOVE) { 1875 WARN_ON(f->counter != 0); 1876 /* Move the element into temporary del_list */ 1877 list_move_tail(&f->list, &tmp_del_list); 1878 vsi->active_filters--; 1879 } 1880 if (f->state == I40E_FILTER_NEW) { 1881 WARN_ON(f->counter == 0); 1882 /* Move the element into temporary add_list */ 1883 list_move_tail(&f->list, &tmp_add_list); 1884 } 1885 } 1886 spin_unlock_bh(&vsi->mac_filter_list_lock); 1887 } 1888 1889 /* Now process 'del_list' outside the lock */ 1890 if (!list_empty(&tmp_del_list)) { 1891 filter_list_len = hw->aq.asq_buf_size / 1892 sizeof(struct i40e_aqc_remove_macvlan_element_data); 1893 list_size = filter_list_len * 1894 sizeof(struct i40e_aqc_remove_macvlan_element_data); 1895 del_list = kzalloc(list_size, GFP_ATOMIC); 1896 if (!del_list) { 1897 /* Undo VSI's MAC filter entry element updates */ 1898 spin_lock_bh(&vsi->mac_filter_list_lock); 1899 i40e_undo_del_filter_entries(vsi, &tmp_del_list); 1900 spin_unlock_bh(&vsi->mac_filter_list_lock); 1901 retval = -ENOMEM; 1902 goto out; 1903 } 1904 1905 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) { 1906 cmd_flags = 0; 1907 1908 /* add to delete list */ 1909 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); 1910 if (f->vlan == I40E_VLAN_ANY) { 1911 del_list[num_del].vlan_tag = 0; 1912 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 1913 } else { 1914 del_list[num_del].vlan_tag = 1915 cpu_to_le16((u16)(f->vlan)); 1916 } 1917 1918 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 1919 del_list[num_del].flags = cmd_flags; 1920 num_del++; 1921 1922 /* flush a full buffer */ 1923 if (num_del == filter_list_len) { 1924 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, 1925 del_list, 1926 num_del, NULL); 1927 aq_err = hw->aq.asq_last_status; 1928 num_del = 0; 1929 memset(del_list, 0, list_size); 1930 1931 /* Explicitly ignore and do not report when 1932 * firmware returns ENOENT. 1933 */ 1934 if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { 1935 retval = -EIO; 1936 dev_info(&pf->pdev->dev, 1937 "ignoring delete macvlan error on %s, err %s, aq_err %s\n", 1938 vsi_name, 1939 i40e_stat_str(hw, aq_ret), 1940 i40e_aq_str(hw, aq_err)); 1941 } 1942 } 1943 /* Release memory for MAC filter entries which were 1944 * synced up with HW. 1945 */ 1946 list_del(&f->list); 1947 kfree(f); 1948 } 1949 1950 if (num_del) { 1951 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, del_list, 1952 num_del, NULL); 1953 aq_err = hw->aq.asq_last_status; 1954 num_del = 0; 1955 1956 /* Explicitly ignore and do not report when firmware 1957 * returns ENOENT. 1958 */ 1959 if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { 1960 retval = -EIO; 1961 dev_info(&pf->pdev->dev, 1962 "ignoring delete macvlan error on %s, err %s aq_err %s\n", 1963 vsi_name, 1964 i40e_stat_str(hw, aq_ret), 1965 i40e_aq_str(hw, aq_err)); 1966 } 1967 } 1968 1969 kfree(del_list); 1970 del_list = NULL; 1971 } 1972 1973 if (!list_empty(&tmp_add_list)) { 1974 /* Do all the adds now. */ 1975 filter_list_len = hw->aq.asq_buf_size / 1976 sizeof(struct i40e_aqc_add_macvlan_element_data); 1977 list_size = filter_list_len * 1978 sizeof(struct i40e_aqc_add_macvlan_element_data); 1979 add_list = kzalloc(list_size, GFP_ATOMIC); 1980 if (!add_list) { 1981 retval = -ENOMEM; 1982 goto out; 1983 } 1984 num_add = 0; 1985 list_for_each_entry(f, &tmp_add_list, list) { 1986 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, 1987 &vsi->state)) { 1988 f->state = I40E_FILTER_FAILED; 1989 continue; 1990 } 1991 /* add to add array */ 1992 if (num_add == 0) 1993 add_head = f; 1994 cmd_flags = 0; 1995 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr); 1996 if (f->vlan == I40E_VLAN_ANY) { 1997 add_list[num_add].vlan_tag = 0; 1998 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 1999 } else { 2000 add_list[num_add].vlan_tag = 2001 cpu_to_le16((u16)(f->vlan)); 2002 } 2003 add_list[num_add].queue_number = 0; 2004 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 2005 add_list[num_add].flags = cpu_to_le16(cmd_flags); 2006 num_add++; 2007 2008 /* flush a full buffer */ 2009 if (num_add == filter_list_len) { 2010 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid, 2011 add_list, num_add, 2012 NULL); 2013 aq_err = hw->aq.asq_last_status; 2014 fcnt = i40e_update_filter_state(num_add, 2015 add_list, 2016 add_head, 2017 aq_ret); 2018 vsi->active_filters += fcnt; 2019 2020 if (fcnt != num_add) { 2021 promisc_changed = true; 2022 set_bit(__I40E_FILTER_OVERFLOW_PROMISC, 2023 &vsi->state); 2024 vsi->promisc_threshold = 2025 (vsi->active_filters * 3) / 4; 2026 dev_warn(&pf->pdev->dev, 2027 "Error %s adding RX filters on %s, promiscuous mode forced on\n", 2028 i40e_aq_str(hw, aq_err), 2029 vsi_name); 2030 } 2031 memset(add_list, 0, list_size); 2032 num_add = 0; 2033 } 2034 } 2035 if (num_add) { 2036 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid, 2037 add_list, num_add, NULL); 2038 aq_err = hw->aq.asq_last_status; 2039 fcnt = i40e_update_filter_state(num_add, add_list, 2040 add_head, aq_ret); 2041 vsi->active_filters += fcnt; 2042 if (fcnt != num_add) { 2043 promisc_changed = true; 2044 set_bit(__I40E_FILTER_OVERFLOW_PROMISC, 2045 &vsi->state); 2046 vsi->promisc_threshold = 2047 (vsi->active_filters * 3) / 4; 2048 dev_warn(&pf->pdev->dev, 2049 "Error %s adding RX filters on %s, promiscuous mode forced on\n", 2050 i40e_aq_str(hw, aq_err), vsi_name); 2051 } 2052 } 2053 /* Now move all of the filters from the temp add list back to 2054 * the VSI's list. 2055 */ 2056 spin_lock_bh(&vsi->mac_filter_list_lock); 2057 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) { 2058 list_move_tail(&f->list, &vsi->mac_filter_list); 2059 } 2060 spin_unlock_bh(&vsi->mac_filter_list_lock); 2061 kfree(add_list); 2062 add_list = NULL; 2063 } 2064 2065 /* Check to see if we can drop out of overflow promiscuous mode. */ 2066 if (test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state) && 2067 (vsi->active_filters < vsi->promisc_threshold)) { 2068 int failed_count = 0; 2069 /* See if we have any failed filters. We can't drop out of 2070 * promiscuous until these have all been deleted. 2071 */ 2072 spin_lock_bh(&vsi->mac_filter_list_lock); 2073 list_for_each_entry(f, &vsi->mac_filter_list, list) { 2074 if (f->state == I40E_FILTER_FAILED) 2075 failed_count++; 2076 } 2077 spin_unlock_bh(&vsi->mac_filter_list_lock); 2078 if (!failed_count) { 2079 dev_info(&pf->pdev->dev, 2080 "filter logjam cleared on %s, leaving overflow promiscuous mode\n", 2081 vsi_name); 2082 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); 2083 promisc_changed = true; 2084 vsi->promisc_threshold = 0; 2085 } 2086 } 2087 2088 /* if the VF is not trusted do not do promisc */ 2089 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { 2090 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); 2091 goto out; 2092 } 2093 2094 /* check for changes in promiscuous modes */ 2095 if (changed_flags & IFF_ALLMULTI) { 2096 bool cur_multipromisc; 2097 2098 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); 2099 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, 2100 vsi->seid, 2101 cur_multipromisc, 2102 NULL); 2103 if (aq_ret) { 2104 retval = i40e_aq_rc_to_posix(aq_ret, 2105 hw->aq.asq_last_status); 2106 dev_info(&pf->pdev->dev, 2107 "set multi promisc failed on %s, err %s aq_err %s\n", 2108 vsi_name, 2109 i40e_stat_str(hw, aq_ret), 2110 i40e_aq_str(hw, hw->aq.asq_last_status)); 2111 } 2112 } 2113 if ((changed_flags & IFF_PROMISC) || 2114 (promisc_changed && 2115 test_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state))) { 2116 bool cur_promisc; 2117 2118 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || 2119 test_bit(__I40E_FILTER_OVERFLOW_PROMISC, 2120 &vsi->state)); 2121 if ((vsi->type == I40E_VSI_MAIN) && 2122 (pf->lan_veb != I40E_NO_VEB) && 2123 !(pf->flags & I40E_FLAG_MFP_ENABLED)) { 2124 /* set defport ON for Main VSI instead of true promisc 2125 * this way we will get all unicast/multicast and VLAN 2126 * promisc behavior but will not get VF or VMDq traffic 2127 * replicated on the Main VSI. 2128 */ 2129 if (pf->cur_promisc != cur_promisc) { 2130 pf->cur_promisc = cur_promisc; 2131 if (cur_promisc) 2132 aq_ret = 2133 i40e_aq_set_default_vsi(hw, 2134 vsi->seid, 2135 NULL); 2136 else 2137 aq_ret = 2138 i40e_aq_clear_default_vsi(hw, 2139 vsi->seid, 2140 NULL); 2141 if (aq_ret) { 2142 retval = i40e_aq_rc_to_posix(aq_ret, 2143 hw->aq.asq_last_status); 2144 dev_info(&pf->pdev->dev, 2145 "Set default VSI failed on %s, err %s, aq_err %s\n", 2146 vsi_name, 2147 i40e_stat_str(hw, aq_ret), 2148 i40e_aq_str(hw, 2149 hw->aq.asq_last_status)); 2150 } 2151 } 2152 } else { 2153 aq_ret = i40e_aq_set_vsi_unicast_promiscuous( 2154 hw, 2155 vsi->seid, 2156 cur_promisc, NULL, 2157 true); 2158 if (aq_ret) { 2159 retval = 2160 i40e_aq_rc_to_posix(aq_ret, 2161 hw->aq.asq_last_status); 2162 dev_info(&pf->pdev->dev, 2163 "set unicast promisc failed on %s, err %s, aq_err %s\n", 2164 vsi_name, 2165 i40e_stat_str(hw, aq_ret), 2166 i40e_aq_str(hw, 2167 hw->aq.asq_last_status)); 2168 } 2169 aq_ret = i40e_aq_set_vsi_multicast_promiscuous( 2170 hw, 2171 vsi->seid, 2172 cur_promisc, NULL); 2173 if (aq_ret) { 2174 retval = 2175 i40e_aq_rc_to_posix(aq_ret, 2176 hw->aq.asq_last_status); 2177 dev_info(&pf->pdev->dev, 2178 "set multicast promisc failed on %s, err %s, aq_err %s\n", 2179 vsi_name, 2180 i40e_stat_str(hw, aq_ret), 2181 i40e_aq_str(hw, 2182 hw->aq.asq_last_status)); 2183 } 2184 } 2185 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw, 2186 vsi->seid, 2187 cur_promisc, NULL); 2188 if (aq_ret) { 2189 retval = i40e_aq_rc_to_posix(aq_ret, 2190 pf->hw.aq.asq_last_status); 2191 dev_info(&pf->pdev->dev, 2192 "set brdcast promisc failed, err %s, aq_err %s\n", 2193 i40e_stat_str(hw, aq_ret), 2194 i40e_aq_str(hw, 2195 hw->aq.asq_last_status)); 2196 } 2197 } 2198 out: 2199 /* if something went wrong then set the changed flag so we try again */ 2200 if (retval) 2201 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 2202 2203 clear_bit(__I40E_CONFIG_BUSY, &vsi->state); 2204 return retval; 2205 } 2206 2207 /** 2208 * i40e_sync_filters_subtask - Sync the VSI filter list with HW 2209 * @pf: board private structure 2210 **/ 2211 static void i40e_sync_filters_subtask(struct i40e_pf *pf) 2212 { 2213 int v; 2214 2215 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC)) 2216 return; 2217 pf->flags &= ~I40E_FLAG_FILTER_SYNC; 2218 2219 for (v = 0; v < pf->num_alloc_vsi; v++) { 2220 if (pf->vsi[v] && 2221 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { 2222 int ret = i40e_sync_vsi_filters(pf->vsi[v]); 2223 2224 if (ret) { 2225 /* come back and try again later */ 2226 pf->flags |= I40E_FLAG_FILTER_SYNC; 2227 break; 2228 } 2229 } 2230 } 2231 } 2232 2233 /** 2234 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit 2235 * @netdev: network interface device structure 2236 * @new_mtu: new value for maximum frame size 2237 * 2238 * Returns 0 on success, negative on failure 2239 **/ 2240 static int i40e_change_mtu(struct net_device *netdev, int new_mtu) 2241 { 2242 struct i40e_netdev_priv *np = netdev_priv(netdev); 2243 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 2244 struct i40e_vsi *vsi = np->vsi; 2245 2246 /* MTU < 68 is an error and causes problems on some kernels */ 2247 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER)) 2248 return -EINVAL; 2249 2250 netdev_info(netdev, "changing MTU from %d to %d\n", 2251 netdev->mtu, new_mtu); 2252 netdev->mtu = new_mtu; 2253 if (netif_running(netdev)) 2254 i40e_vsi_reinit_locked(vsi); 2255 i40e_notify_client_of_l2_param_changes(vsi); 2256 return 0; 2257 } 2258 2259 /** 2260 * i40e_ioctl - Access the hwtstamp interface 2261 * @netdev: network interface device structure 2262 * @ifr: interface request data 2263 * @cmd: ioctl command 2264 **/ 2265 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2266 { 2267 struct i40e_netdev_priv *np = netdev_priv(netdev); 2268 struct i40e_pf *pf = np->vsi->back; 2269 2270 switch (cmd) { 2271 case SIOCGHWTSTAMP: 2272 return i40e_ptp_get_ts_config(pf, ifr); 2273 case SIOCSHWTSTAMP: 2274 return i40e_ptp_set_ts_config(pf, ifr); 2275 default: 2276 return -EOPNOTSUPP; 2277 } 2278 } 2279 2280 /** 2281 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI 2282 * @vsi: the vsi being adjusted 2283 **/ 2284 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) 2285 { 2286 struct i40e_vsi_context ctxt; 2287 i40e_status ret; 2288 2289 if ((vsi->info.valid_sections & 2290 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && 2291 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) 2292 return; /* already enabled */ 2293 2294 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); 2295 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 2296 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2297 2298 ctxt.seid = vsi->seid; 2299 ctxt.info = vsi->info; 2300 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 2301 if (ret) { 2302 dev_info(&vsi->back->pdev->dev, 2303 "update vlan stripping failed, err %s aq_err %s\n", 2304 i40e_stat_str(&vsi->back->hw, ret), 2305 i40e_aq_str(&vsi->back->hw, 2306 vsi->back->hw.aq.asq_last_status)); 2307 } 2308 } 2309 2310 /** 2311 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI 2312 * @vsi: the vsi being adjusted 2313 **/ 2314 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) 2315 { 2316 struct i40e_vsi_context ctxt; 2317 i40e_status ret; 2318 2319 if ((vsi->info.valid_sections & 2320 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && 2321 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == 2322 I40E_AQ_VSI_PVLAN_EMOD_MASK)) 2323 return; /* already disabled */ 2324 2325 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); 2326 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 2327 I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2328 2329 ctxt.seid = vsi->seid; 2330 ctxt.info = vsi->info; 2331 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 2332 if (ret) { 2333 dev_info(&vsi->back->pdev->dev, 2334 "update vlan stripping failed, err %s aq_err %s\n", 2335 i40e_stat_str(&vsi->back->hw, ret), 2336 i40e_aq_str(&vsi->back->hw, 2337 vsi->back->hw.aq.asq_last_status)); 2338 } 2339 } 2340 2341 /** 2342 * i40e_vlan_rx_register - Setup or shutdown vlan offload 2343 * @netdev: network interface to be adjusted 2344 * @features: netdev features to test if VLAN offload is enabled or not 2345 **/ 2346 static void i40e_vlan_rx_register(struct net_device *netdev, u32 features) 2347 { 2348 struct i40e_netdev_priv *np = netdev_priv(netdev); 2349 struct i40e_vsi *vsi = np->vsi; 2350 2351 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2352 i40e_vlan_stripping_enable(vsi); 2353 else 2354 i40e_vlan_stripping_disable(vsi); 2355 } 2356 2357 /** 2358 * i40e_vsi_add_vlan - Add vsi membership for given vlan 2359 * @vsi: the vsi being configured 2360 * @vid: vlan id to be added (0 = untagged only , -1 = any) 2361 **/ 2362 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid) 2363 { 2364 struct i40e_mac_filter *f, *ftmp, *add_f; 2365 bool is_netdev, is_vf; 2366 2367 is_vf = (vsi->type == I40E_VSI_SRIOV); 2368 is_netdev = !!(vsi->netdev); 2369 2370 /* Locked once because all functions invoked below iterates list*/ 2371 spin_lock_bh(&vsi->mac_filter_list_lock); 2372 2373 if (is_netdev) { 2374 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid, 2375 is_vf, is_netdev); 2376 if (!add_f) { 2377 dev_info(&vsi->back->pdev->dev, 2378 "Could not add vlan filter %d for %pM\n", 2379 vid, vsi->netdev->dev_addr); 2380 spin_unlock_bh(&vsi->mac_filter_list_lock); 2381 return -ENOMEM; 2382 } 2383 } 2384 2385 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 2386 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev); 2387 if (!add_f) { 2388 dev_info(&vsi->back->pdev->dev, 2389 "Could not add vlan filter %d for %pM\n", 2390 vid, f->macaddr); 2391 spin_unlock_bh(&vsi->mac_filter_list_lock); 2392 return -ENOMEM; 2393 } 2394 } 2395 2396 /* Now if we add a vlan tag, make sure to check if it is the first 2397 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag" 2398 * with 0, so we now accept untagged and specified tagged traffic 2399 * (and not all tags along with untagged) 2400 */ 2401 if (vid > 0) { 2402 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr, 2403 I40E_VLAN_ANY, 2404 is_vf, is_netdev)) { 2405 i40e_del_filter(vsi, vsi->netdev->dev_addr, 2406 I40E_VLAN_ANY, is_vf, is_netdev); 2407 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0, 2408 is_vf, is_netdev); 2409 if (!add_f) { 2410 dev_info(&vsi->back->pdev->dev, 2411 "Could not add filter 0 for %pM\n", 2412 vsi->netdev->dev_addr); 2413 spin_unlock_bh(&vsi->mac_filter_list_lock); 2414 return -ENOMEM; 2415 } 2416 } 2417 } 2418 2419 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */ 2420 if (vid > 0 && !vsi->info.pvid) { 2421 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 2422 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY, 2423 is_vf, is_netdev)) 2424 continue; 2425 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, 2426 is_vf, is_netdev); 2427 add_f = i40e_add_filter(vsi, f->macaddr, 2428 0, is_vf, is_netdev); 2429 if (!add_f) { 2430 dev_info(&vsi->back->pdev->dev, 2431 "Could not add filter 0 for %pM\n", 2432 f->macaddr); 2433 spin_unlock_bh(&vsi->mac_filter_list_lock); 2434 return -ENOMEM; 2435 } 2436 } 2437 } 2438 2439 spin_unlock_bh(&vsi->mac_filter_list_lock); 2440 2441 /* schedule our worker thread which will take care of 2442 * applying the new filter changes 2443 */ 2444 i40e_service_event_schedule(vsi->back); 2445 return 0; 2446 } 2447 2448 /** 2449 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan 2450 * @vsi: the vsi being configured 2451 * @vid: vlan id to be removed (0 = untagged only , -1 = any) 2452 * 2453 * Return: 0 on success or negative otherwise 2454 **/ 2455 int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid) 2456 { 2457 struct net_device *netdev = vsi->netdev; 2458 struct i40e_mac_filter *f, *ftmp, *add_f; 2459 bool is_vf, is_netdev; 2460 int filter_count = 0; 2461 2462 is_vf = (vsi->type == I40E_VSI_SRIOV); 2463 is_netdev = !!(netdev); 2464 2465 /* Locked once because all functions invoked below iterates list */ 2466 spin_lock_bh(&vsi->mac_filter_list_lock); 2467 2468 if (is_netdev) 2469 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev); 2470 2471 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) 2472 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev); 2473 2474 /* go through all the filters for this VSI and if there is only 2475 * vid == 0 it means there are no other filters, so vid 0 must 2476 * be replaced with -1. This signifies that we should from now 2477 * on accept any traffic (with any tag present, or untagged) 2478 */ 2479 list_for_each_entry(f, &vsi->mac_filter_list, list) { 2480 if (is_netdev) { 2481 if (f->vlan && 2482 ether_addr_equal(netdev->dev_addr, f->macaddr)) 2483 filter_count++; 2484 } 2485 2486 if (f->vlan) 2487 filter_count++; 2488 } 2489 2490 if (!filter_count && is_netdev) { 2491 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev); 2492 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, 2493 is_vf, is_netdev); 2494 if (!f) { 2495 dev_info(&vsi->back->pdev->dev, 2496 "Could not add filter %d for %pM\n", 2497 I40E_VLAN_ANY, netdev->dev_addr); 2498 spin_unlock_bh(&vsi->mac_filter_list_lock); 2499 return -ENOMEM; 2500 } 2501 } 2502 2503 if (!filter_count) { 2504 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 2505 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev); 2506 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY, 2507 is_vf, is_netdev); 2508 if (!add_f) { 2509 dev_info(&vsi->back->pdev->dev, 2510 "Could not add filter %d for %pM\n", 2511 I40E_VLAN_ANY, f->macaddr); 2512 spin_unlock_bh(&vsi->mac_filter_list_lock); 2513 return -ENOMEM; 2514 } 2515 } 2516 } 2517 2518 spin_unlock_bh(&vsi->mac_filter_list_lock); 2519 2520 /* schedule our worker thread which will take care of 2521 * applying the new filter changes 2522 */ 2523 i40e_service_event_schedule(vsi->back); 2524 return 0; 2525 } 2526 2527 /** 2528 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload 2529 * @netdev: network interface to be adjusted 2530 * @vid: vlan id to be added 2531 * 2532 * net_device_ops implementation for adding vlan ids 2533 **/ 2534 #ifdef I40E_FCOE 2535 int i40e_vlan_rx_add_vid(struct net_device *netdev, 2536 __always_unused __be16 proto, u16 vid) 2537 #else 2538 static int i40e_vlan_rx_add_vid(struct net_device *netdev, 2539 __always_unused __be16 proto, u16 vid) 2540 #endif 2541 { 2542 struct i40e_netdev_priv *np = netdev_priv(netdev); 2543 struct i40e_vsi *vsi = np->vsi; 2544 int ret = 0; 2545 2546 if (vid > 4095) 2547 return -EINVAL; 2548 2549 /* If the network stack called us with vid = 0 then 2550 * it is asking to receive priority tagged packets with 2551 * vlan id 0. Our HW receives them by default when configured 2552 * to receive untagged packets so there is no need to add an 2553 * extra filter for vlan 0 tagged packets. 2554 */ 2555 if (vid) 2556 ret = i40e_vsi_add_vlan(vsi, vid); 2557 2558 if (!ret && (vid < VLAN_N_VID)) 2559 set_bit(vid, vsi->active_vlans); 2560 2561 return ret; 2562 } 2563 2564 /** 2565 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload 2566 * @netdev: network interface to be adjusted 2567 * @vid: vlan id to be removed 2568 * 2569 * net_device_ops implementation for removing vlan ids 2570 **/ 2571 #ifdef I40E_FCOE 2572 int i40e_vlan_rx_kill_vid(struct net_device *netdev, 2573 __always_unused __be16 proto, u16 vid) 2574 #else 2575 static int i40e_vlan_rx_kill_vid(struct net_device *netdev, 2576 __always_unused __be16 proto, u16 vid) 2577 #endif 2578 { 2579 struct i40e_netdev_priv *np = netdev_priv(netdev); 2580 struct i40e_vsi *vsi = np->vsi; 2581 2582 /* return code is ignored as there is nothing a user 2583 * can do about failure to remove and a log message was 2584 * already printed from the other function 2585 */ 2586 i40e_vsi_kill_vlan(vsi, vid); 2587 2588 clear_bit(vid, vsi->active_vlans); 2589 2590 return 0; 2591 } 2592 2593 /** 2594 * i40e_macaddr_init - explicitly write the mac address filters 2595 * 2596 * @vsi: pointer to the vsi 2597 * @macaddr: the MAC address 2598 * 2599 * This is needed when the macaddr has been obtained by other 2600 * means than the default, e.g., from Open Firmware or IDPROM. 2601 * Returns 0 on success, negative on failure 2602 **/ 2603 static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr) 2604 { 2605 int ret; 2606 struct i40e_aqc_add_macvlan_element_data element; 2607 2608 ret = i40e_aq_mac_address_write(&vsi->back->hw, 2609 I40E_AQC_WRITE_TYPE_LAA_WOL, 2610 macaddr, NULL); 2611 if (ret) { 2612 dev_info(&vsi->back->pdev->dev, 2613 "Addr change for VSI failed: %d\n", ret); 2614 return -EADDRNOTAVAIL; 2615 } 2616 2617 memset(&element, 0, sizeof(element)); 2618 ether_addr_copy(element.mac_addr, macaddr); 2619 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH); 2620 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL); 2621 if (ret) { 2622 dev_info(&vsi->back->pdev->dev, 2623 "add filter failed err %s aq_err %s\n", 2624 i40e_stat_str(&vsi->back->hw, ret), 2625 i40e_aq_str(&vsi->back->hw, 2626 vsi->back->hw.aq.asq_last_status)); 2627 } 2628 return ret; 2629 } 2630 2631 /** 2632 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up 2633 * @vsi: the vsi being brought back up 2634 **/ 2635 static void i40e_restore_vlan(struct i40e_vsi *vsi) 2636 { 2637 u16 vid; 2638 2639 if (!vsi->netdev) 2640 return; 2641 2642 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features); 2643 2644 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) 2645 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q), 2646 vid); 2647 } 2648 2649 /** 2650 * i40e_vsi_add_pvid - Add pvid for the VSI 2651 * @vsi: the vsi being adjusted 2652 * @vid: the vlan id to set as a PVID 2653 **/ 2654 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) 2655 { 2656 struct i40e_vsi_context ctxt; 2657 i40e_status ret; 2658 2659 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); 2660 vsi->info.pvid = cpu_to_le16(vid); 2661 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | 2662 I40E_AQ_VSI_PVLAN_INSERT_PVID | 2663 I40E_AQ_VSI_PVLAN_EMOD_STR; 2664 2665 ctxt.seid = vsi->seid; 2666 ctxt.info = vsi->info; 2667 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 2668 if (ret) { 2669 dev_info(&vsi->back->pdev->dev, 2670 "add pvid failed, err %s aq_err %s\n", 2671 i40e_stat_str(&vsi->back->hw, ret), 2672 i40e_aq_str(&vsi->back->hw, 2673 vsi->back->hw.aq.asq_last_status)); 2674 return -ENOENT; 2675 } 2676 2677 return 0; 2678 } 2679 2680 /** 2681 * i40e_vsi_remove_pvid - Remove the pvid from the VSI 2682 * @vsi: the vsi being adjusted 2683 * 2684 * Just use the vlan_rx_register() service to put it back to normal 2685 **/ 2686 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) 2687 { 2688 i40e_vlan_stripping_disable(vsi); 2689 2690 vsi->info.pvid = 0; 2691 } 2692 2693 /** 2694 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources 2695 * @vsi: ptr to the VSI 2696 * 2697 * If this function returns with an error, then it's possible one or 2698 * more of the rings is populated (while the rest are not). It is the 2699 * callers duty to clean those orphaned rings. 2700 * 2701 * Return 0 on success, negative on failure 2702 **/ 2703 static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) 2704 { 2705 int i, err = 0; 2706 2707 for (i = 0; i < vsi->num_queue_pairs && !err; i++) 2708 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); 2709 2710 return err; 2711 } 2712 2713 /** 2714 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues 2715 * @vsi: ptr to the VSI 2716 * 2717 * Free VSI's transmit software resources 2718 **/ 2719 static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) 2720 { 2721 int i; 2722 2723 if (!vsi->tx_rings) 2724 return; 2725 2726 for (i = 0; i < vsi->num_queue_pairs; i++) 2727 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) 2728 i40e_free_tx_resources(vsi->tx_rings[i]); 2729 } 2730 2731 /** 2732 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources 2733 * @vsi: ptr to the VSI 2734 * 2735 * If this function returns with an error, then it's possible one or 2736 * more of the rings is populated (while the rest are not). It is the 2737 * callers duty to clean those orphaned rings. 2738 * 2739 * Return 0 on success, negative on failure 2740 **/ 2741 static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) 2742 { 2743 int i, err = 0; 2744 2745 for (i = 0; i < vsi->num_queue_pairs && !err; i++) 2746 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); 2747 #ifdef I40E_FCOE 2748 i40e_fcoe_setup_ddp_resources(vsi); 2749 #endif 2750 return err; 2751 } 2752 2753 /** 2754 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues 2755 * @vsi: ptr to the VSI 2756 * 2757 * Free all receive software resources 2758 **/ 2759 static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) 2760 { 2761 int i; 2762 2763 if (!vsi->rx_rings) 2764 return; 2765 2766 for (i = 0; i < vsi->num_queue_pairs; i++) 2767 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) 2768 i40e_free_rx_resources(vsi->rx_rings[i]); 2769 #ifdef I40E_FCOE 2770 i40e_fcoe_free_ddp_resources(vsi); 2771 #endif 2772 } 2773 2774 /** 2775 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring 2776 * @ring: The Tx ring to configure 2777 * 2778 * This enables/disables XPS for a given Tx descriptor ring 2779 * based on the TCs enabled for the VSI that ring belongs to. 2780 **/ 2781 static void i40e_config_xps_tx_ring(struct i40e_ring *ring) 2782 { 2783 struct i40e_vsi *vsi = ring->vsi; 2784 cpumask_var_t mask; 2785 2786 if (!ring->q_vector || !ring->netdev) 2787 return; 2788 2789 /* Single TC mode enable XPS */ 2790 if (vsi->tc_config.numtc <= 1) { 2791 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state)) 2792 netif_set_xps_queue(ring->netdev, 2793 &ring->q_vector->affinity_mask, 2794 ring->queue_index); 2795 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) { 2796 /* Disable XPS to allow selection based on TC */ 2797 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits); 2798 netif_set_xps_queue(ring->netdev, mask, ring->queue_index); 2799 free_cpumask_var(mask); 2800 } 2801 2802 /* schedule our worker thread which will take care of 2803 * applying the new filter changes 2804 */ 2805 i40e_service_event_schedule(vsi->back); 2806 } 2807 2808 /** 2809 * i40e_configure_tx_ring - Configure a transmit ring context and rest 2810 * @ring: The Tx ring to configure 2811 * 2812 * Configure the Tx descriptor ring in the HMC context. 2813 **/ 2814 static int i40e_configure_tx_ring(struct i40e_ring *ring) 2815 { 2816 struct i40e_vsi *vsi = ring->vsi; 2817 u16 pf_q = vsi->base_queue + ring->queue_index; 2818 struct i40e_hw *hw = &vsi->back->hw; 2819 struct i40e_hmc_obj_txq tx_ctx; 2820 i40e_status err = 0; 2821 u32 qtx_ctl = 0; 2822 2823 /* some ATR related tx ring init */ 2824 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { 2825 ring->atr_sample_rate = vsi->back->atr_sample_rate; 2826 ring->atr_count = 0; 2827 } else { 2828 ring->atr_sample_rate = 0; 2829 } 2830 2831 /* configure XPS */ 2832 i40e_config_xps_tx_ring(ring); 2833 2834 /* clear the context structure first */ 2835 memset(&tx_ctx, 0, sizeof(tx_ctx)); 2836 2837 tx_ctx.new_context = 1; 2838 tx_ctx.base = (ring->dma / 128); 2839 tx_ctx.qlen = ring->count; 2840 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | 2841 I40E_FLAG_FD_ATR_ENABLED)); 2842 #ifdef I40E_FCOE 2843 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); 2844 #endif 2845 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); 2846 /* FDIR VSI tx ring can still use RS bit and writebacks */ 2847 if (vsi->type != I40E_VSI_FDIR) 2848 tx_ctx.head_wb_ena = 1; 2849 tx_ctx.head_wb_addr = ring->dma + 2850 (ring->count * sizeof(struct i40e_tx_desc)); 2851 2852 /* As part of VSI creation/update, FW allocates certain 2853 * Tx arbitration queue sets for each TC enabled for 2854 * the VSI. The FW returns the handles to these queue 2855 * sets as part of the response buffer to Add VSI, 2856 * Update VSI, etc. AQ commands. It is expected that 2857 * these queue set handles be associated with the Tx 2858 * queues by the driver as part of the TX queue context 2859 * initialization. This has to be done regardless of 2860 * DCB as by default everything is mapped to TC0. 2861 */ 2862 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); 2863 tx_ctx.rdylist_act = 0; 2864 2865 /* clear the context in the HMC */ 2866 err = i40e_clear_lan_tx_queue_context(hw, pf_q); 2867 if (err) { 2868 dev_info(&vsi->back->pdev->dev, 2869 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", 2870 ring->queue_index, pf_q, err); 2871 return -ENOMEM; 2872 } 2873 2874 /* set the context in the HMC */ 2875 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); 2876 if (err) { 2877 dev_info(&vsi->back->pdev->dev, 2878 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", 2879 ring->queue_index, pf_q, err); 2880 return -ENOMEM; 2881 } 2882 2883 /* Now associate this queue with this PCI function */ 2884 if (vsi->type == I40E_VSI_VMDQ2) { 2885 qtx_ctl = I40E_QTX_CTL_VM_QUEUE; 2886 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & 2887 I40E_QTX_CTL_VFVM_INDX_MASK; 2888 } else { 2889 qtx_ctl = I40E_QTX_CTL_PF_QUEUE; 2890 } 2891 2892 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2893 I40E_QTX_CTL_PF_INDX_MASK); 2894 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); 2895 i40e_flush(hw); 2896 2897 /* cache tail off for easier writes later */ 2898 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); 2899 2900 return 0; 2901 } 2902 2903 /** 2904 * i40e_configure_rx_ring - Configure a receive ring context 2905 * @ring: The Rx ring to configure 2906 * 2907 * Configure the Rx descriptor ring in the HMC context. 2908 **/ 2909 static int i40e_configure_rx_ring(struct i40e_ring *ring) 2910 { 2911 struct i40e_vsi *vsi = ring->vsi; 2912 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; 2913 u16 pf_q = vsi->base_queue + ring->queue_index; 2914 struct i40e_hw *hw = &vsi->back->hw; 2915 struct i40e_hmc_obj_rxq rx_ctx; 2916 i40e_status err = 0; 2917 2918 ring->state = 0; 2919 2920 /* clear the context structure first */ 2921 memset(&rx_ctx, 0, sizeof(rx_ctx)); 2922 2923 ring->rx_buf_len = vsi->rx_buf_len; 2924 2925 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT; 2926 2927 rx_ctx.base = (ring->dma / 128); 2928 rx_ctx.qlen = ring->count; 2929 2930 /* use 32 byte descriptors */ 2931 rx_ctx.dsize = 1; 2932 2933 /* descriptor type is always zero 2934 * rx_ctx.dtype = 0; 2935 */ 2936 rx_ctx.hsplit_0 = 0; 2937 2938 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); 2939 if (hw->revision_id == 0) 2940 rx_ctx.lrxqthresh = 0; 2941 else 2942 rx_ctx.lrxqthresh = 2; 2943 rx_ctx.crcstrip = 1; 2944 rx_ctx.l2tsel = 1; 2945 /* this controls whether VLAN is stripped from inner headers */ 2946 rx_ctx.showiv = 0; 2947 #ifdef I40E_FCOE 2948 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE); 2949 #endif 2950 /* set the prefena field to 1 because the manual says to */ 2951 rx_ctx.prefena = 1; 2952 2953 /* clear the context in the HMC */ 2954 err = i40e_clear_lan_rx_queue_context(hw, pf_q); 2955 if (err) { 2956 dev_info(&vsi->back->pdev->dev, 2957 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", 2958 ring->queue_index, pf_q, err); 2959 return -ENOMEM; 2960 } 2961 2962 /* set the context in the HMC */ 2963 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); 2964 if (err) { 2965 dev_info(&vsi->back->pdev->dev, 2966 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", 2967 ring->queue_index, pf_q, err); 2968 return -ENOMEM; 2969 } 2970 2971 /* cache tail for quicker writes, and clear the reg before use */ 2972 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); 2973 writel(0, ring->tail); 2974 2975 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); 2976 2977 return 0; 2978 } 2979 2980 /** 2981 * i40e_vsi_configure_tx - Configure the VSI for Tx 2982 * @vsi: VSI structure describing this set of rings and resources 2983 * 2984 * Configure the Tx VSI for operation. 2985 **/ 2986 static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) 2987 { 2988 int err = 0; 2989 u16 i; 2990 2991 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) 2992 err = i40e_configure_tx_ring(vsi->tx_rings[i]); 2993 2994 return err; 2995 } 2996 2997 /** 2998 * i40e_vsi_configure_rx - Configure the VSI for Rx 2999 * @vsi: the VSI being configured 3000 * 3001 * Configure the Rx VSI for operation. 3002 **/ 3003 static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) 3004 { 3005 int err = 0; 3006 u16 i; 3007 3008 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN)) 3009 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN 3010 + ETH_FCS_LEN + VLAN_HLEN; 3011 else 3012 vsi->max_frame = I40E_RXBUFFER_2048; 3013 3014 vsi->rx_buf_len = I40E_RXBUFFER_2048; 3015 3016 #ifdef I40E_FCOE 3017 /* setup rx buffer for FCoE */ 3018 if ((vsi->type == I40E_VSI_FCOE) && 3019 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) { 3020 vsi->rx_buf_len = I40E_RXBUFFER_3072; 3021 vsi->max_frame = I40E_RXBUFFER_3072; 3022 } 3023 3024 #endif /* I40E_FCOE */ 3025 /* round up for the chip's needs */ 3026 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len, 3027 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); 3028 3029 /* set up individual rings */ 3030 for (i = 0; i < vsi->num_queue_pairs && !err; i++) 3031 err = i40e_configure_rx_ring(vsi->rx_rings[i]); 3032 3033 return err; 3034 } 3035 3036 /** 3037 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC 3038 * @vsi: ptr to the VSI 3039 **/ 3040 static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) 3041 { 3042 struct i40e_ring *tx_ring, *rx_ring; 3043 u16 qoffset, qcount; 3044 int i, n; 3045 3046 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { 3047 /* Reset the TC information */ 3048 for (i = 0; i < vsi->num_queue_pairs; i++) { 3049 rx_ring = vsi->rx_rings[i]; 3050 tx_ring = vsi->tx_rings[i]; 3051 rx_ring->dcb_tc = 0; 3052 tx_ring->dcb_tc = 0; 3053 } 3054 } 3055 3056 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { 3057 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) 3058 continue; 3059 3060 qoffset = vsi->tc_config.tc_info[n].qoffset; 3061 qcount = vsi->tc_config.tc_info[n].qcount; 3062 for (i = qoffset; i < (qoffset + qcount); i++) { 3063 rx_ring = vsi->rx_rings[i]; 3064 tx_ring = vsi->tx_rings[i]; 3065 rx_ring->dcb_tc = n; 3066 tx_ring->dcb_tc = n; 3067 } 3068 } 3069 } 3070 3071 /** 3072 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI 3073 * @vsi: ptr to the VSI 3074 **/ 3075 static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) 3076 { 3077 struct i40e_pf *pf = vsi->back; 3078 int err; 3079 3080 if (vsi->netdev) 3081 i40e_set_rx_mode(vsi->netdev); 3082 3083 if (!!(pf->flags & I40E_FLAG_PF_MAC)) { 3084 err = i40e_macaddr_init(vsi, pf->hw.mac.addr); 3085 if (err) { 3086 dev_warn(&pf->pdev->dev, 3087 "could not set up macaddr; err %d\n", err); 3088 } 3089 } 3090 } 3091 3092 /** 3093 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters 3094 * @vsi: Pointer to the targeted VSI 3095 * 3096 * This function replays the hlist on the hw where all the SB Flow Director 3097 * filters were saved. 3098 **/ 3099 static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) 3100 { 3101 struct i40e_fdir_filter *filter; 3102 struct i40e_pf *pf = vsi->back; 3103 struct hlist_node *node; 3104 3105 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) 3106 return; 3107 3108 hlist_for_each_entry_safe(filter, node, 3109 &pf->fdir_filter_list, fdir_node) { 3110 i40e_add_del_fdir(vsi, filter, true); 3111 } 3112 } 3113 3114 /** 3115 * i40e_vsi_configure - Set up the VSI for action 3116 * @vsi: the VSI being configured 3117 **/ 3118 static int i40e_vsi_configure(struct i40e_vsi *vsi) 3119 { 3120 int err; 3121 3122 i40e_set_vsi_rx_mode(vsi); 3123 i40e_restore_vlan(vsi); 3124 i40e_vsi_config_dcb_rings(vsi); 3125 err = i40e_vsi_configure_tx(vsi); 3126 if (!err) 3127 err = i40e_vsi_configure_rx(vsi); 3128 3129 return err; 3130 } 3131 3132 /** 3133 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW 3134 * @vsi: the VSI being configured 3135 **/ 3136 static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) 3137 { 3138 struct i40e_pf *pf = vsi->back; 3139 struct i40e_hw *hw = &pf->hw; 3140 u16 vector; 3141 int i, q; 3142 u32 qp; 3143 3144 /* The interrupt indexing is offset by 1 in the PFINT_ITRn 3145 * and PFINT_LNKLSTn registers, e.g.: 3146 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) 3147 */ 3148 qp = vsi->base_queue; 3149 vector = vsi->base_vector; 3150 for (i = 0; i < vsi->num_q_vectors; i++, vector++) { 3151 struct i40e_q_vector *q_vector = vsi->q_vectors[i]; 3152 3153 q_vector->itr_countdown = ITR_COUNTDOWN_START; 3154 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting); 3155 q_vector->rx.latency_range = I40E_LOW_LATENCY; 3156 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), 3157 q_vector->rx.itr); 3158 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting); 3159 q_vector->tx.latency_range = I40E_LOW_LATENCY; 3160 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), 3161 q_vector->tx.itr); 3162 wr32(hw, I40E_PFINT_RATEN(vector - 1), 3163 INTRL_USEC_TO_REG(vsi->int_rate_limit)); 3164 3165 /* Linked list for the queuepairs assigned to this vector */ 3166 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); 3167 for (q = 0; q < q_vector->num_ringpairs; q++) { 3168 u32 val; 3169 3170 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 3171 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 3172 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 3173 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| 3174 (I40E_QUEUE_TYPE_TX 3175 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 3176 3177 wr32(hw, I40E_QINT_RQCTL(qp), val); 3178 3179 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 3180 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 3181 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 3182 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)| 3183 (I40E_QUEUE_TYPE_RX 3184 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 3185 3186 /* Terminate the linked list */ 3187 if (q == (q_vector->num_ringpairs - 1)) 3188 val |= (I40E_QUEUE_END_OF_LIST 3189 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 3190 3191 wr32(hw, I40E_QINT_TQCTL(qp), val); 3192 qp++; 3193 } 3194 } 3195 3196 i40e_flush(hw); 3197 } 3198 3199 /** 3200 * i40e_enable_misc_int_causes - enable the non-queue interrupts 3201 * @hw: ptr to the hardware info 3202 **/ 3203 static void i40e_enable_misc_int_causes(struct i40e_pf *pf) 3204 { 3205 struct i40e_hw *hw = &pf->hw; 3206 u32 val; 3207 3208 /* clear things first */ 3209 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 3210 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 3211 3212 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 3213 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 3214 I40E_PFINT_ICR0_ENA_GRST_MASK | 3215 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | 3216 I40E_PFINT_ICR0_ENA_GPIO_MASK | 3217 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | 3218 I40E_PFINT_ICR0_ENA_VFLR_MASK | 3219 I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 3220 3221 if (pf->flags & I40E_FLAG_IWARP_ENABLED) 3222 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; 3223 3224 if (pf->flags & I40E_FLAG_PTP) 3225 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 3226 3227 wr32(hw, I40E_PFINT_ICR0_ENA, val); 3228 3229 /* SW_ITR_IDX = 0, but don't change INTENA */ 3230 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 3231 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 3232 3233 /* OTHER_ITR_IDX = 0 */ 3234 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 3235 } 3236 3237 /** 3238 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW 3239 * @vsi: the VSI being configured 3240 **/ 3241 static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) 3242 { 3243 struct i40e_q_vector *q_vector = vsi->q_vectors[0]; 3244 struct i40e_pf *pf = vsi->back; 3245 struct i40e_hw *hw = &pf->hw; 3246 u32 val; 3247 3248 /* set the ITR configuration */ 3249 q_vector->itr_countdown = ITR_COUNTDOWN_START; 3250 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting); 3251 q_vector->rx.latency_range = I40E_LOW_LATENCY; 3252 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr); 3253 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting); 3254 q_vector->tx.latency_range = I40E_LOW_LATENCY; 3255 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr); 3256 3257 i40e_enable_misc_int_causes(pf); 3258 3259 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 3260 wr32(hw, I40E_PFINT_LNKLST0, 0); 3261 3262 /* Associate the queue pair to the vector and enable the queue int */ 3263 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 3264 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 3265 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 3266 3267 wr32(hw, I40E_QINT_RQCTL(0), val); 3268 3269 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 3270 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 3271 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 3272 3273 wr32(hw, I40E_QINT_TQCTL(0), val); 3274 i40e_flush(hw); 3275 } 3276 3277 /** 3278 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 3279 * @pf: board private structure 3280 **/ 3281 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) 3282 { 3283 struct i40e_hw *hw = &pf->hw; 3284 3285 wr32(hw, I40E_PFINT_DYN_CTL0, 3286 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 3287 i40e_flush(hw); 3288 } 3289 3290 /** 3291 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 3292 * @pf: board private structure 3293 * @clearpba: true when all pending interrupt events should be cleared 3294 **/ 3295 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba) 3296 { 3297 struct i40e_hw *hw = &pf->hw; 3298 u32 val; 3299 3300 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 3301 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) | 3302 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 3303 3304 wr32(hw, I40E_PFINT_DYN_CTL0, val); 3305 i40e_flush(hw); 3306 } 3307 3308 /** 3309 * i40e_msix_clean_rings - MSIX mode Interrupt Handler 3310 * @irq: interrupt number 3311 * @data: pointer to a q_vector 3312 **/ 3313 static irqreturn_t i40e_msix_clean_rings(int irq, void *data) 3314 { 3315 struct i40e_q_vector *q_vector = data; 3316 3317 if (!q_vector->tx.ring && !q_vector->rx.ring) 3318 return IRQ_HANDLED; 3319 3320 napi_schedule_irqoff(&q_vector->napi); 3321 3322 return IRQ_HANDLED; 3323 } 3324 3325 /** 3326 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts 3327 * @vsi: the VSI being configured 3328 * @basename: name for the vector 3329 * 3330 * Allocates MSI-X vectors and requests interrupts from the kernel. 3331 **/ 3332 static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) 3333 { 3334 int q_vectors = vsi->num_q_vectors; 3335 struct i40e_pf *pf = vsi->back; 3336 int base = vsi->base_vector; 3337 int rx_int_idx = 0; 3338 int tx_int_idx = 0; 3339 int vector, err; 3340 3341 for (vector = 0; vector < q_vectors; vector++) { 3342 struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; 3343 3344 if (q_vector->tx.ring && q_vector->rx.ring) { 3345 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3346 "%s-%s-%d", basename, "TxRx", rx_int_idx++); 3347 tx_int_idx++; 3348 } else if (q_vector->rx.ring) { 3349 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3350 "%s-%s-%d", basename, "rx", rx_int_idx++); 3351 } else if (q_vector->tx.ring) { 3352 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 3353 "%s-%s-%d", basename, "tx", tx_int_idx++); 3354 } else { 3355 /* skip this unused q_vector */ 3356 continue; 3357 } 3358 err = request_irq(pf->msix_entries[base + vector].vector, 3359 vsi->irq_handler, 3360 0, 3361 q_vector->name, 3362 q_vector); 3363 if (err) { 3364 dev_info(&pf->pdev->dev, 3365 "MSIX request_irq failed, error: %d\n", err); 3366 goto free_queue_irqs; 3367 } 3368 /* assign the mask for this irq */ 3369 irq_set_affinity_hint(pf->msix_entries[base + vector].vector, 3370 &q_vector->affinity_mask); 3371 } 3372 3373 vsi->irqs_ready = true; 3374 return 0; 3375 3376 free_queue_irqs: 3377 while (vector) { 3378 vector--; 3379 irq_set_affinity_hint(pf->msix_entries[base + vector].vector, 3380 NULL); 3381 free_irq(pf->msix_entries[base + vector].vector, 3382 &(vsi->q_vectors[vector])); 3383 } 3384 return err; 3385 } 3386 3387 /** 3388 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI 3389 * @vsi: the VSI being un-configured 3390 **/ 3391 static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) 3392 { 3393 struct i40e_pf *pf = vsi->back; 3394 struct i40e_hw *hw = &pf->hw; 3395 int base = vsi->base_vector; 3396 int i; 3397 3398 for (i = 0; i < vsi->num_queue_pairs; i++) { 3399 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0); 3400 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0); 3401 } 3402 3403 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 3404 for (i = vsi->base_vector; 3405 i < (vsi->num_q_vectors + vsi->base_vector); i++) 3406 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); 3407 3408 i40e_flush(hw); 3409 for (i = 0; i < vsi->num_q_vectors; i++) 3410 synchronize_irq(pf->msix_entries[i + base].vector); 3411 } else { 3412 /* Legacy and MSI mode - this stops all interrupt handling */ 3413 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 3414 wr32(hw, I40E_PFINT_DYN_CTL0, 0); 3415 i40e_flush(hw); 3416 synchronize_irq(pf->pdev->irq); 3417 } 3418 } 3419 3420 /** 3421 * i40e_vsi_enable_irq - Enable IRQ for the given VSI 3422 * @vsi: the VSI being configured 3423 **/ 3424 static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) 3425 { 3426 struct i40e_pf *pf = vsi->back; 3427 int i; 3428 3429 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 3430 for (i = 0; i < vsi->num_q_vectors; i++) 3431 i40e_irq_dynamic_enable(vsi, i); 3432 } else { 3433 i40e_irq_dynamic_enable_icr0(pf, true); 3434 } 3435 3436 i40e_flush(&pf->hw); 3437 return 0; 3438 } 3439 3440 /** 3441 * i40e_stop_misc_vector - Stop the vector that handles non-queue events 3442 * @pf: board private structure 3443 **/ 3444 static void i40e_stop_misc_vector(struct i40e_pf *pf) 3445 { 3446 /* Disable ICR 0 */ 3447 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); 3448 i40e_flush(&pf->hw); 3449 } 3450 3451 /** 3452 * i40e_intr - MSI/Legacy and non-queue interrupt handler 3453 * @irq: interrupt number 3454 * @data: pointer to a q_vector 3455 * 3456 * This is the handler used for all MSI/Legacy interrupts, and deals 3457 * with both queue and non-queue interrupts. This is also used in 3458 * MSIX mode to handle the non-queue interrupts. 3459 **/ 3460 static irqreturn_t i40e_intr(int irq, void *data) 3461 { 3462 struct i40e_pf *pf = (struct i40e_pf *)data; 3463 struct i40e_hw *hw = &pf->hw; 3464 irqreturn_t ret = IRQ_NONE; 3465 u32 icr0, icr0_remaining; 3466 u32 val, ena_mask; 3467 3468 icr0 = rd32(hw, I40E_PFINT_ICR0); 3469 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); 3470 3471 /* if sharing a legacy IRQ, we might get called w/o an intr pending */ 3472 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) 3473 goto enable_intr; 3474 3475 /* if interrupt but no bits showing, must be SWINT */ 3476 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || 3477 (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) 3478 pf->sw_int_count++; 3479 3480 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && 3481 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { 3482 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; 3483 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; 3484 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n"); 3485 } 3486 3487 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ 3488 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { 3489 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 3490 struct i40e_q_vector *q_vector = vsi->q_vectors[0]; 3491 3492 /* We do not have a way to disarm Queue causes while leaving 3493 * interrupt enabled for all other causes, ideally 3494 * interrupt should be disabled while we are in NAPI but 3495 * this is not a performance path and napi_schedule() 3496 * can deal with rescheduling. 3497 */ 3498 if (!test_bit(__I40E_DOWN, &pf->state)) 3499 napi_schedule_irqoff(&q_vector->napi); 3500 } 3501 3502 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 3503 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 3504 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); 3505 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); 3506 } 3507 3508 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 3509 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 3510 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state); 3511 } 3512 3513 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { 3514 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 3515 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state); 3516 } 3517 3518 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { 3519 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) 3520 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); 3521 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; 3522 val = rd32(hw, I40E_GLGEN_RSTAT); 3523 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) 3524 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; 3525 if (val == I40E_RESET_CORER) { 3526 pf->corer_count++; 3527 } else if (val == I40E_RESET_GLOBR) { 3528 pf->globr_count++; 3529 } else if (val == I40E_RESET_EMPR) { 3530 pf->empr_count++; 3531 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state); 3532 } 3533 } 3534 3535 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { 3536 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; 3537 dev_info(&pf->pdev->dev, "HMC error interrupt\n"); 3538 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", 3539 rd32(hw, I40E_PFHMC_ERRORINFO), 3540 rd32(hw, I40E_PFHMC_ERRORDATA)); 3541 } 3542 3543 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { 3544 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); 3545 3546 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { 3547 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; 3548 i40e_ptp_tx_hwtstamp(pf); 3549 } 3550 } 3551 3552 /* If a critical error is pending we have no choice but to reset the 3553 * device. 3554 * Report and mask out any remaining unexpected interrupts. 3555 */ 3556 icr0_remaining = icr0 & ena_mask; 3557 if (icr0_remaining) { 3558 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", 3559 icr0_remaining); 3560 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || 3561 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || 3562 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { 3563 dev_info(&pf->pdev->dev, "device will be reset\n"); 3564 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 3565 i40e_service_event_schedule(pf); 3566 } 3567 ena_mask &= ~icr0_remaining; 3568 } 3569 ret = IRQ_HANDLED; 3570 3571 enable_intr: 3572 /* re-enable interrupt causes */ 3573 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); 3574 if (!test_bit(__I40E_DOWN, &pf->state)) { 3575 i40e_service_event_schedule(pf); 3576 i40e_irq_dynamic_enable_icr0(pf, false); 3577 } 3578 3579 return ret; 3580 } 3581 3582 /** 3583 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes 3584 * @tx_ring: tx ring to clean 3585 * @budget: how many cleans we're allowed 3586 * 3587 * Returns true if there's any budget left (e.g. the clean is finished) 3588 **/ 3589 static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) 3590 { 3591 struct i40e_vsi *vsi = tx_ring->vsi; 3592 u16 i = tx_ring->next_to_clean; 3593 struct i40e_tx_buffer *tx_buf; 3594 struct i40e_tx_desc *tx_desc; 3595 3596 tx_buf = &tx_ring->tx_bi[i]; 3597 tx_desc = I40E_TX_DESC(tx_ring, i); 3598 i -= tx_ring->count; 3599 3600 do { 3601 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 3602 3603 /* if next_to_watch is not set then there is no work pending */ 3604 if (!eop_desc) 3605 break; 3606 3607 /* prevent any other reads prior to eop_desc */ 3608 read_barrier_depends(); 3609 3610 /* if the descriptor isn't done, no work yet to do */ 3611 if (!(eop_desc->cmd_type_offset_bsz & 3612 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) 3613 break; 3614 3615 /* clear next_to_watch to prevent false hangs */ 3616 tx_buf->next_to_watch = NULL; 3617 3618 tx_desc->buffer_addr = 0; 3619 tx_desc->cmd_type_offset_bsz = 0; 3620 /* move past filter desc */ 3621 tx_buf++; 3622 tx_desc++; 3623 i++; 3624 if (unlikely(!i)) { 3625 i -= tx_ring->count; 3626 tx_buf = tx_ring->tx_bi; 3627 tx_desc = I40E_TX_DESC(tx_ring, 0); 3628 } 3629 /* unmap skb header data */ 3630 dma_unmap_single(tx_ring->dev, 3631 dma_unmap_addr(tx_buf, dma), 3632 dma_unmap_len(tx_buf, len), 3633 DMA_TO_DEVICE); 3634 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) 3635 kfree(tx_buf->raw_buf); 3636 3637 tx_buf->raw_buf = NULL; 3638 tx_buf->tx_flags = 0; 3639 tx_buf->next_to_watch = NULL; 3640 dma_unmap_len_set(tx_buf, len, 0); 3641 tx_desc->buffer_addr = 0; 3642 tx_desc->cmd_type_offset_bsz = 0; 3643 3644 /* move us past the eop_desc for start of next FD desc */ 3645 tx_buf++; 3646 tx_desc++; 3647 i++; 3648 if (unlikely(!i)) { 3649 i -= tx_ring->count; 3650 tx_buf = tx_ring->tx_bi; 3651 tx_desc = I40E_TX_DESC(tx_ring, 0); 3652 } 3653 3654 /* update budget accounting */ 3655 budget--; 3656 } while (likely(budget)); 3657 3658 i += tx_ring->count; 3659 tx_ring->next_to_clean = i; 3660 3661 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) 3662 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); 3663 3664 return budget > 0; 3665 } 3666 3667 /** 3668 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring 3669 * @irq: interrupt number 3670 * @data: pointer to a q_vector 3671 **/ 3672 static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) 3673 { 3674 struct i40e_q_vector *q_vector = data; 3675 struct i40e_vsi *vsi; 3676 3677 if (!q_vector->tx.ring) 3678 return IRQ_HANDLED; 3679 3680 vsi = q_vector->tx.ring->vsi; 3681 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); 3682 3683 return IRQ_HANDLED; 3684 } 3685 3686 /** 3687 * i40e_map_vector_to_qp - Assigns the queue pair to the vector 3688 * @vsi: the VSI being configured 3689 * @v_idx: vector index 3690 * @qp_idx: queue pair index 3691 **/ 3692 static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) 3693 { 3694 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; 3695 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; 3696 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; 3697 3698 tx_ring->q_vector = q_vector; 3699 tx_ring->next = q_vector->tx.ring; 3700 q_vector->tx.ring = tx_ring; 3701 q_vector->tx.count++; 3702 3703 rx_ring->q_vector = q_vector; 3704 rx_ring->next = q_vector->rx.ring; 3705 q_vector->rx.ring = rx_ring; 3706 q_vector->rx.count++; 3707 } 3708 3709 /** 3710 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors 3711 * @vsi: the VSI being configured 3712 * 3713 * This function maps descriptor rings to the queue-specific vectors 3714 * we were allotted through the MSI-X enabling code. Ideally, we'd have 3715 * one vector per queue pair, but on a constrained vector budget, we 3716 * group the queue pairs as "efficiently" as possible. 3717 **/ 3718 static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) 3719 { 3720 int qp_remaining = vsi->num_queue_pairs; 3721 int q_vectors = vsi->num_q_vectors; 3722 int num_ringpairs; 3723 int v_start = 0; 3724 int qp_idx = 0; 3725 3726 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to 3727 * group them so there are multiple queues per vector. 3728 * It is also important to go through all the vectors available to be 3729 * sure that if we don't use all the vectors, that the remaining vectors 3730 * are cleared. This is especially important when decreasing the 3731 * number of queues in use. 3732 */ 3733 for (; v_start < q_vectors; v_start++) { 3734 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; 3735 3736 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); 3737 3738 q_vector->num_ringpairs = num_ringpairs; 3739 3740 q_vector->rx.count = 0; 3741 q_vector->tx.count = 0; 3742 q_vector->rx.ring = NULL; 3743 q_vector->tx.ring = NULL; 3744 3745 while (num_ringpairs--) { 3746 i40e_map_vector_to_qp(vsi, v_start, qp_idx); 3747 qp_idx++; 3748 qp_remaining--; 3749 } 3750 } 3751 } 3752 3753 /** 3754 * i40e_vsi_request_irq - Request IRQ from the OS 3755 * @vsi: the VSI being configured 3756 * @basename: name for the vector 3757 **/ 3758 static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) 3759 { 3760 struct i40e_pf *pf = vsi->back; 3761 int err; 3762 3763 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 3764 err = i40e_vsi_request_irq_msix(vsi, basename); 3765 else if (pf->flags & I40E_FLAG_MSI_ENABLED) 3766 err = request_irq(pf->pdev->irq, i40e_intr, 0, 3767 pf->int_name, pf); 3768 else 3769 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, 3770 pf->int_name, pf); 3771 3772 if (err) 3773 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); 3774 3775 return err; 3776 } 3777 3778 #ifdef CONFIG_NET_POLL_CONTROLLER 3779 /** 3780 * i40e_netpoll - A Polling 'interrupt' handler 3781 * @netdev: network interface device structure 3782 * 3783 * This is used by netconsole to send skbs without having to re-enable 3784 * interrupts. It's not called while the normal interrupt routine is executing. 3785 **/ 3786 #ifdef I40E_FCOE 3787 void i40e_netpoll(struct net_device *netdev) 3788 #else 3789 static void i40e_netpoll(struct net_device *netdev) 3790 #endif 3791 { 3792 struct i40e_netdev_priv *np = netdev_priv(netdev); 3793 struct i40e_vsi *vsi = np->vsi; 3794 struct i40e_pf *pf = vsi->back; 3795 int i; 3796 3797 /* if interface is down do nothing */ 3798 if (test_bit(__I40E_DOWN, &vsi->state)) 3799 return; 3800 3801 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 3802 for (i = 0; i < vsi->num_q_vectors; i++) 3803 i40e_msix_clean_rings(0, vsi->q_vectors[i]); 3804 } else { 3805 i40e_intr(pf->pdev->irq, netdev); 3806 } 3807 } 3808 #endif 3809 3810 /** 3811 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled 3812 * @pf: the PF being configured 3813 * @pf_q: the PF queue 3814 * @enable: enable or disable state of the queue 3815 * 3816 * This routine will wait for the given Tx queue of the PF to reach the 3817 * enabled or disabled state. 3818 * Returns -ETIMEDOUT in case of failing to reach the requested state after 3819 * multiple retries; else will return 0 in case of success. 3820 **/ 3821 static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) 3822 { 3823 int i; 3824 u32 tx_reg; 3825 3826 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { 3827 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); 3828 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3829 break; 3830 3831 usleep_range(10, 20); 3832 } 3833 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) 3834 return -ETIMEDOUT; 3835 3836 return 0; 3837 } 3838 3839 /** 3840 * i40e_vsi_control_tx - Start or stop a VSI's rings 3841 * @vsi: the VSI being configured 3842 * @enable: start or stop the rings 3843 **/ 3844 static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) 3845 { 3846 struct i40e_pf *pf = vsi->back; 3847 struct i40e_hw *hw = &pf->hw; 3848 int i, j, pf_q, ret = 0; 3849 u32 tx_reg; 3850 3851 pf_q = vsi->base_queue; 3852 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { 3853 3854 /* warn the TX unit of coming changes */ 3855 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); 3856 if (!enable) 3857 usleep_range(10, 20); 3858 3859 for (j = 0; j < 50; j++) { 3860 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); 3861 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == 3862 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) 3863 break; 3864 usleep_range(1000, 2000); 3865 } 3866 /* Skip if the queue is already in the requested state */ 3867 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3868 continue; 3869 3870 /* turn on/off the queue */ 3871 if (enable) { 3872 wr32(hw, I40E_QTX_HEAD(pf_q), 0); 3873 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; 3874 } else { 3875 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3876 } 3877 3878 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); 3879 /* No waiting for the Tx queue to disable */ 3880 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) 3881 continue; 3882 3883 /* wait for the change to finish */ 3884 ret = i40e_pf_txq_wait(pf, pf_q, enable); 3885 if (ret) { 3886 dev_info(&pf->pdev->dev, 3887 "VSI seid %d Tx ring %d %sable timeout\n", 3888 vsi->seid, pf_q, (enable ? "en" : "dis")); 3889 break; 3890 } 3891 } 3892 3893 if (hw->revision_id == 0) 3894 mdelay(50); 3895 return ret; 3896 } 3897 3898 /** 3899 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 3900 * @pf: the PF being configured 3901 * @pf_q: the PF queue 3902 * @enable: enable or disable state of the queue 3903 * 3904 * This routine will wait for the given Rx queue of the PF to reach the 3905 * enabled or disabled state. 3906 * Returns -ETIMEDOUT in case of failing to reach the requested state after 3907 * multiple retries; else will return 0 in case of success. 3908 **/ 3909 static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) 3910 { 3911 int i; 3912 u32 rx_reg; 3913 3914 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { 3915 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); 3916 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3917 break; 3918 3919 usleep_range(10, 20); 3920 } 3921 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) 3922 return -ETIMEDOUT; 3923 3924 return 0; 3925 } 3926 3927 /** 3928 * i40e_vsi_control_rx - Start or stop a VSI's rings 3929 * @vsi: the VSI being configured 3930 * @enable: start or stop the rings 3931 **/ 3932 static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) 3933 { 3934 struct i40e_pf *pf = vsi->back; 3935 struct i40e_hw *hw = &pf->hw; 3936 int i, j, pf_q, ret = 0; 3937 u32 rx_reg; 3938 3939 pf_q = vsi->base_queue; 3940 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { 3941 for (j = 0; j < 50; j++) { 3942 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); 3943 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == 3944 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) 3945 break; 3946 usleep_range(1000, 2000); 3947 } 3948 3949 /* Skip if the queue is already in the requested state */ 3950 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3951 continue; 3952 3953 /* turn on/off the queue */ 3954 if (enable) 3955 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; 3956 else 3957 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3958 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); 3959 /* No waiting for the Tx queue to disable */ 3960 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state)) 3961 continue; 3962 3963 /* wait for the change to finish */ 3964 ret = i40e_pf_rxq_wait(pf, pf_q, enable); 3965 if (ret) { 3966 dev_info(&pf->pdev->dev, 3967 "VSI seid %d Rx ring %d %sable timeout\n", 3968 vsi->seid, pf_q, (enable ? "en" : "dis")); 3969 break; 3970 } 3971 } 3972 3973 return ret; 3974 } 3975 3976 /** 3977 * i40e_vsi_control_rings - Start or stop a VSI's rings 3978 * @vsi: the VSI being configured 3979 * @enable: start or stop the rings 3980 **/ 3981 int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request) 3982 { 3983 int ret = 0; 3984 3985 /* do rx first for enable and last for disable */ 3986 if (request) { 3987 ret = i40e_vsi_control_rx(vsi, request); 3988 if (ret) 3989 return ret; 3990 ret = i40e_vsi_control_tx(vsi, request); 3991 } else { 3992 /* Ignore return value, we need to shutdown whatever we can */ 3993 i40e_vsi_control_tx(vsi, request); 3994 i40e_vsi_control_rx(vsi, request); 3995 } 3996 3997 return ret; 3998 } 3999 4000 /** 4001 * i40e_vsi_free_irq - Free the irq association with the OS 4002 * @vsi: the VSI being configured 4003 **/ 4004 static void i40e_vsi_free_irq(struct i40e_vsi *vsi) 4005 { 4006 struct i40e_pf *pf = vsi->back; 4007 struct i40e_hw *hw = &pf->hw; 4008 int base = vsi->base_vector; 4009 u32 val, qp; 4010 int i; 4011 4012 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 4013 if (!vsi->q_vectors) 4014 return; 4015 4016 if (!vsi->irqs_ready) 4017 return; 4018 4019 vsi->irqs_ready = false; 4020 for (i = 0; i < vsi->num_q_vectors; i++) { 4021 u16 vector = i + base; 4022 4023 /* free only the irqs that were actually requested */ 4024 if (!vsi->q_vectors[i] || 4025 !vsi->q_vectors[i]->num_ringpairs) 4026 continue; 4027 4028 /* clear the affinity_mask in the IRQ descriptor */ 4029 irq_set_affinity_hint(pf->msix_entries[vector].vector, 4030 NULL); 4031 synchronize_irq(pf->msix_entries[vector].vector); 4032 free_irq(pf->msix_entries[vector].vector, 4033 vsi->q_vectors[i]); 4034 4035 /* Tear down the interrupt queue link list 4036 * 4037 * We know that they come in pairs and always 4038 * the Rx first, then the Tx. To clear the 4039 * link list, stick the EOL value into the 4040 * next_q field of the registers. 4041 */ 4042 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); 4043 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) 4044 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 4045 val |= I40E_QUEUE_END_OF_LIST 4046 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 4047 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); 4048 4049 while (qp != I40E_QUEUE_END_OF_LIST) { 4050 u32 next; 4051 4052 val = rd32(hw, I40E_QINT_RQCTL(qp)); 4053 4054 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | 4055 I40E_QINT_RQCTL_MSIX0_INDX_MASK | 4056 I40E_QINT_RQCTL_CAUSE_ENA_MASK | 4057 I40E_QINT_RQCTL_INTEVENT_MASK); 4058 4059 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | 4060 I40E_QINT_RQCTL_NEXTQ_INDX_MASK); 4061 4062 wr32(hw, I40E_QINT_RQCTL(qp), val); 4063 4064 val = rd32(hw, I40E_QINT_TQCTL(qp)); 4065 4066 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) 4067 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; 4068 4069 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | 4070 I40E_QINT_TQCTL_MSIX0_INDX_MASK | 4071 I40E_QINT_TQCTL_CAUSE_ENA_MASK | 4072 I40E_QINT_TQCTL_INTEVENT_MASK); 4073 4074 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | 4075 I40E_QINT_TQCTL_NEXTQ_INDX_MASK); 4076 4077 wr32(hw, I40E_QINT_TQCTL(qp), val); 4078 qp = next; 4079 } 4080 } 4081 } else { 4082 free_irq(pf->pdev->irq, pf); 4083 4084 val = rd32(hw, I40E_PFINT_LNKLST0); 4085 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) 4086 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; 4087 val |= I40E_QUEUE_END_OF_LIST 4088 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4089 wr32(hw, I40E_PFINT_LNKLST0, val); 4090 4091 val = rd32(hw, I40E_QINT_RQCTL(qp)); 4092 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | 4093 I40E_QINT_RQCTL_MSIX0_INDX_MASK | 4094 I40E_QINT_RQCTL_CAUSE_ENA_MASK | 4095 I40E_QINT_RQCTL_INTEVENT_MASK); 4096 4097 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | 4098 I40E_QINT_RQCTL_NEXTQ_INDX_MASK); 4099 4100 wr32(hw, I40E_QINT_RQCTL(qp), val); 4101 4102 val = rd32(hw, I40E_QINT_TQCTL(qp)); 4103 4104 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | 4105 I40E_QINT_TQCTL_MSIX0_INDX_MASK | 4106 I40E_QINT_TQCTL_CAUSE_ENA_MASK | 4107 I40E_QINT_TQCTL_INTEVENT_MASK); 4108 4109 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | 4110 I40E_QINT_TQCTL_NEXTQ_INDX_MASK); 4111 4112 wr32(hw, I40E_QINT_TQCTL(qp), val); 4113 } 4114 } 4115 4116 /** 4117 * i40e_free_q_vector - Free memory allocated for specific interrupt vector 4118 * @vsi: the VSI being configured 4119 * @v_idx: Index of vector to be freed 4120 * 4121 * This function frees the memory allocated to the q_vector. In addition if 4122 * NAPI is enabled it will delete any references to the NAPI struct prior 4123 * to freeing the q_vector. 4124 **/ 4125 static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) 4126 { 4127 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; 4128 struct i40e_ring *ring; 4129 4130 if (!q_vector) 4131 return; 4132 4133 /* disassociate q_vector from rings */ 4134 i40e_for_each_ring(ring, q_vector->tx) 4135 ring->q_vector = NULL; 4136 4137 i40e_for_each_ring(ring, q_vector->rx) 4138 ring->q_vector = NULL; 4139 4140 /* only VSI w/ an associated netdev is set up w/ NAPI */ 4141 if (vsi->netdev) 4142 netif_napi_del(&q_vector->napi); 4143 4144 vsi->q_vectors[v_idx] = NULL; 4145 4146 kfree_rcu(q_vector, rcu); 4147 } 4148 4149 /** 4150 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors 4151 * @vsi: the VSI being un-configured 4152 * 4153 * This frees the memory allocated to the q_vectors and 4154 * deletes references to the NAPI struct. 4155 **/ 4156 static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) 4157 { 4158 int v_idx; 4159 4160 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) 4161 i40e_free_q_vector(vsi, v_idx); 4162 } 4163 4164 /** 4165 * i40e_reset_interrupt_capability - Disable interrupt setup in OS 4166 * @pf: board private structure 4167 **/ 4168 static void i40e_reset_interrupt_capability(struct i40e_pf *pf) 4169 { 4170 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ 4171 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 4172 pci_disable_msix(pf->pdev); 4173 kfree(pf->msix_entries); 4174 pf->msix_entries = NULL; 4175 kfree(pf->irq_pile); 4176 pf->irq_pile = NULL; 4177 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { 4178 pci_disable_msi(pf->pdev); 4179 } 4180 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); 4181 } 4182 4183 /** 4184 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings 4185 * @pf: board private structure 4186 * 4187 * We go through and clear interrupt specific resources and reset the structure 4188 * to pre-load conditions 4189 **/ 4190 static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) 4191 { 4192 int i; 4193 4194 i40e_stop_misc_vector(pf); 4195 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { 4196 synchronize_irq(pf->msix_entries[0].vector); 4197 free_irq(pf->msix_entries[0].vector, pf); 4198 } 4199 4200 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, 4201 I40E_IWARP_IRQ_PILE_ID); 4202 4203 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); 4204 for (i = 0; i < pf->num_alloc_vsi; i++) 4205 if (pf->vsi[i]) 4206 i40e_vsi_free_q_vectors(pf->vsi[i]); 4207 i40e_reset_interrupt_capability(pf); 4208 } 4209 4210 /** 4211 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI 4212 * @vsi: the VSI being configured 4213 **/ 4214 static void i40e_napi_enable_all(struct i40e_vsi *vsi) 4215 { 4216 int q_idx; 4217 4218 if (!vsi->netdev) 4219 return; 4220 4221 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) 4222 napi_enable(&vsi->q_vectors[q_idx]->napi); 4223 } 4224 4225 /** 4226 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI 4227 * @vsi: the VSI being configured 4228 **/ 4229 static void i40e_napi_disable_all(struct i40e_vsi *vsi) 4230 { 4231 int q_idx; 4232 4233 if (!vsi->netdev) 4234 return; 4235 4236 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) 4237 napi_disable(&vsi->q_vectors[q_idx]->napi); 4238 } 4239 4240 /** 4241 * i40e_vsi_close - Shut down a VSI 4242 * @vsi: the vsi to be quelled 4243 **/ 4244 static void i40e_vsi_close(struct i40e_vsi *vsi) 4245 { 4246 bool reset = false; 4247 4248 if (!test_and_set_bit(__I40E_DOWN, &vsi->state)) 4249 i40e_down(vsi); 4250 i40e_vsi_free_irq(vsi); 4251 i40e_vsi_free_tx_resources(vsi); 4252 i40e_vsi_free_rx_resources(vsi); 4253 vsi->current_netdev_flags = 0; 4254 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) 4255 reset = true; 4256 i40e_notify_client_of_netdev_close(vsi, reset); 4257 } 4258 4259 /** 4260 * i40e_quiesce_vsi - Pause a given VSI 4261 * @vsi: the VSI being paused 4262 **/ 4263 static void i40e_quiesce_vsi(struct i40e_vsi *vsi) 4264 { 4265 if (test_bit(__I40E_DOWN, &vsi->state)) 4266 return; 4267 4268 /* No need to disable FCoE VSI when Tx suspended */ 4269 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) && 4270 vsi->type == I40E_VSI_FCOE) { 4271 dev_dbg(&vsi->back->pdev->dev, 4272 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid); 4273 return; 4274 } 4275 4276 set_bit(__I40E_NEEDS_RESTART, &vsi->state); 4277 if (vsi->netdev && netif_running(vsi->netdev)) 4278 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); 4279 else 4280 i40e_vsi_close(vsi); 4281 } 4282 4283 /** 4284 * i40e_unquiesce_vsi - Resume a given VSI 4285 * @vsi: the VSI being resumed 4286 **/ 4287 static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) 4288 { 4289 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state)) 4290 return; 4291 4292 clear_bit(__I40E_NEEDS_RESTART, &vsi->state); 4293 if (vsi->netdev && netif_running(vsi->netdev)) 4294 vsi->netdev->netdev_ops->ndo_open(vsi->netdev); 4295 else 4296 i40e_vsi_open(vsi); /* this clears the DOWN bit */ 4297 } 4298 4299 /** 4300 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF 4301 * @pf: the PF 4302 **/ 4303 static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) 4304 { 4305 int v; 4306 4307 for (v = 0; v < pf->num_alloc_vsi; v++) { 4308 if (pf->vsi[v]) 4309 i40e_quiesce_vsi(pf->vsi[v]); 4310 } 4311 } 4312 4313 /** 4314 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF 4315 * @pf: the PF 4316 **/ 4317 static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) 4318 { 4319 int v; 4320 4321 for (v = 0; v < pf->num_alloc_vsi; v++) { 4322 if (pf->vsi[v]) 4323 i40e_unquiesce_vsi(pf->vsi[v]); 4324 } 4325 } 4326 4327 #ifdef CONFIG_I40E_DCB 4328 /** 4329 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled 4330 * @vsi: the VSI being configured 4331 * 4332 * This function waits for the given VSI's queues to be disabled. 4333 **/ 4334 static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) 4335 { 4336 struct i40e_pf *pf = vsi->back; 4337 int i, pf_q, ret; 4338 4339 pf_q = vsi->base_queue; 4340 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { 4341 /* Check and wait for the disable status of the queue */ 4342 ret = i40e_pf_txq_wait(pf, pf_q, false); 4343 if (ret) { 4344 dev_info(&pf->pdev->dev, 4345 "VSI seid %d Tx ring %d disable timeout\n", 4346 vsi->seid, pf_q); 4347 return ret; 4348 } 4349 } 4350 4351 pf_q = vsi->base_queue; 4352 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { 4353 /* Check and wait for the disable status of the queue */ 4354 ret = i40e_pf_rxq_wait(pf, pf_q, false); 4355 if (ret) { 4356 dev_info(&pf->pdev->dev, 4357 "VSI seid %d Rx ring %d disable timeout\n", 4358 vsi->seid, pf_q); 4359 return ret; 4360 } 4361 } 4362 4363 return 0; 4364 } 4365 4366 /** 4367 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled 4368 * @pf: the PF 4369 * 4370 * This function waits for the queues to be in disabled state for all the 4371 * VSIs that are managed by this PF. 4372 **/ 4373 static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) 4374 { 4375 int v, ret = 0; 4376 4377 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { 4378 /* No need to wait for FCoE VSI queues */ 4379 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) { 4380 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); 4381 if (ret) 4382 break; 4383 } 4384 } 4385 4386 return ret; 4387 } 4388 4389 #endif 4390 4391 /** 4392 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue 4393 * @q_idx: TX queue number 4394 * @vsi: Pointer to VSI struct 4395 * 4396 * This function checks specified queue for given VSI. Detects hung condition. 4397 * Sets hung bit since it is two step process. Before next run of service task 4398 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not, 4399 * hung condition remain unchanged and during subsequent run, this function 4400 * issues SW interrupt to recover from hung condition. 4401 **/ 4402 static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi) 4403 { 4404 struct i40e_ring *tx_ring = NULL; 4405 struct i40e_pf *pf; 4406 u32 head, val, tx_pending_hw; 4407 int i; 4408 4409 pf = vsi->back; 4410 4411 /* now that we have an index, find the tx_ring struct */ 4412 for (i = 0; i < vsi->num_queue_pairs; i++) { 4413 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { 4414 if (q_idx == vsi->tx_rings[i]->queue_index) { 4415 tx_ring = vsi->tx_rings[i]; 4416 break; 4417 } 4418 } 4419 } 4420 4421 if (!tx_ring) 4422 return; 4423 4424 /* Read interrupt register */ 4425 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 4426 val = rd32(&pf->hw, 4427 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + 4428 tx_ring->vsi->base_vector - 1)); 4429 else 4430 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); 4431 4432 head = i40e_get_head(tx_ring); 4433 4434 tx_pending_hw = i40e_get_tx_pending(tx_ring, false); 4435 4436 /* HW is done executing descriptors, updated HEAD write back, 4437 * but SW hasn't processed those descriptors. If interrupt is 4438 * not generated from this point ON, it could result into 4439 * dev_watchdog detecting timeout on those netdev_queue, 4440 * hence proactively trigger SW interrupt. 4441 */ 4442 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { 4443 /* NAPI Poll didn't run and clear since it was set */ 4444 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT, 4445 &tx_ring->q_vector->hung_detected)) { 4446 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n", 4447 vsi->seid, q_idx, tx_pending_hw, 4448 tx_ring->next_to_clean, head, 4449 tx_ring->next_to_use, 4450 readl(tx_ring->tail)); 4451 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n", 4452 vsi->seid, q_idx, val); 4453 i40e_force_wb(vsi, tx_ring->q_vector); 4454 } else { 4455 /* First Chance - detected possible hung */ 4456 set_bit(I40E_Q_VECTOR_HUNG_DETECT, 4457 &tx_ring->q_vector->hung_detected); 4458 } 4459 } 4460 4461 /* This is the case where we have interrupts missing, 4462 * so the tx_pending in HW will most likely be 0, but we 4463 * will have tx_pending in SW since the WB happened but the 4464 * interrupt got lost. 4465 */ 4466 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) && 4467 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) { 4468 if (napi_reschedule(&tx_ring->q_vector->napi)) 4469 tx_ring->tx_stats.tx_lost_interrupt++; 4470 } 4471 } 4472 4473 /** 4474 * i40e_detect_recover_hung - Function to detect and recover hung_queues 4475 * @pf: pointer to PF struct 4476 * 4477 * LAN VSI has netdev and netdev has TX queues. This function is to check 4478 * each of those TX queues if they are hung, trigger recovery by issuing 4479 * SW interrupt. 4480 **/ 4481 static void i40e_detect_recover_hung(struct i40e_pf *pf) 4482 { 4483 struct net_device *netdev; 4484 struct i40e_vsi *vsi; 4485 int i; 4486 4487 /* Only for LAN VSI */ 4488 vsi = pf->vsi[pf->lan_vsi]; 4489 4490 if (!vsi) 4491 return; 4492 4493 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */ 4494 if (test_bit(__I40E_DOWN, &vsi->back->state) || 4495 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state)) 4496 return; 4497 4498 /* Make sure type is MAIN VSI */ 4499 if (vsi->type != I40E_VSI_MAIN) 4500 return; 4501 4502 netdev = vsi->netdev; 4503 if (!netdev) 4504 return; 4505 4506 /* Bail out if netif_carrier is not OK */ 4507 if (!netif_carrier_ok(netdev)) 4508 return; 4509 4510 /* Go thru' TX queues for netdev */ 4511 for (i = 0; i < netdev->num_tx_queues; i++) { 4512 struct netdev_queue *q; 4513 4514 q = netdev_get_tx_queue(netdev, i); 4515 if (q) 4516 i40e_detect_recover_hung_queue(i, vsi); 4517 } 4518 } 4519 4520 /** 4521 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP 4522 * @pf: pointer to PF 4523 * 4524 * Get TC map for ISCSI PF type that will include iSCSI TC 4525 * and LAN TC. 4526 **/ 4527 static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) 4528 { 4529 struct i40e_dcb_app_priority_table app; 4530 struct i40e_hw *hw = &pf->hw; 4531 u8 enabled_tc = 1; /* TC0 is always enabled */ 4532 u8 tc, i; 4533 /* Get the iSCSI APP TLV */ 4534 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; 4535 4536 for (i = 0; i < dcbcfg->numapps; i++) { 4537 app = dcbcfg->app[i]; 4538 if (app.selector == I40E_APP_SEL_TCPIP && 4539 app.protocolid == I40E_APP_PROTOID_ISCSI) { 4540 tc = dcbcfg->etscfg.prioritytable[app.priority]; 4541 enabled_tc |= BIT(tc); 4542 break; 4543 } 4544 } 4545 4546 return enabled_tc; 4547 } 4548 4549 /** 4550 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config 4551 * @dcbcfg: the corresponding DCBx configuration structure 4552 * 4553 * Return the number of TCs from given DCBx configuration 4554 **/ 4555 static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) 4556 { 4557 int i, tc_unused = 0; 4558 u8 num_tc = 0; 4559 u8 ret = 0; 4560 4561 /* Scan the ETS Config Priority Table to find 4562 * traffic class enabled for a given priority 4563 * and create a bitmask of enabled TCs 4564 */ 4565 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) 4566 num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); 4567 4568 /* Now scan the bitmask to check for 4569 * contiguous TCs starting with TC0 4570 */ 4571 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4572 if (num_tc & BIT(i)) { 4573 if (!tc_unused) { 4574 ret++; 4575 } else { 4576 pr_err("Non-contiguous TC - Disabling DCB\n"); 4577 return 1; 4578 } 4579 } else { 4580 tc_unused = 1; 4581 } 4582 } 4583 4584 /* There is always at least TC0 */ 4585 if (!ret) 4586 ret = 1; 4587 4588 return ret; 4589 } 4590 4591 /** 4592 * i40e_dcb_get_enabled_tc - Get enabled traffic classes 4593 * @dcbcfg: the corresponding DCBx configuration structure 4594 * 4595 * Query the current DCB configuration and return the number of 4596 * traffic classes enabled from the given DCBX config 4597 **/ 4598 static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) 4599 { 4600 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); 4601 u8 enabled_tc = 1; 4602 u8 i; 4603 4604 for (i = 0; i < num_tc; i++) 4605 enabled_tc |= BIT(i); 4606 4607 return enabled_tc; 4608 } 4609 4610 /** 4611 * i40e_pf_get_num_tc - Get enabled traffic classes for PF 4612 * @pf: PF being queried 4613 * 4614 * Return number of traffic classes enabled for the given PF 4615 **/ 4616 static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) 4617 { 4618 struct i40e_hw *hw = &pf->hw; 4619 u8 i, enabled_tc; 4620 u8 num_tc = 0; 4621 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; 4622 4623 /* If DCB is not enabled then always in single TC */ 4624 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) 4625 return 1; 4626 4627 /* SFP mode will be enabled for all TCs on port */ 4628 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) 4629 return i40e_dcb_get_num_tc(dcbcfg); 4630 4631 /* MFP mode return count of enabled TCs for this PF */ 4632 if (pf->hw.func_caps.iscsi) 4633 enabled_tc = i40e_get_iscsi_tc_map(pf); 4634 else 4635 return 1; /* Only TC0 */ 4636 4637 /* At least have TC0 */ 4638 enabled_tc = (enabled_tc ? enabled_tc : 0x1); 4639 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4640 if (enabled_tc & BIT(i)) 4641 num_tc++; 4642 } 4643 return num_tc; 4644 } 4645 4646 /** 4647 * i40e_pf_get_default_tc - Get bitmap for first enabled TC 4648 * @pf: PF being queried 4649 * 4650 * Return a bitmap for first enabled traffic class for this PF. 4651 **/ 4652 static u8 i40e_pf_get_default_tc(struct i40e_pf *pf) 4653 { 4654 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap; 4655 u8 i = 0; 4656 4657 if (!enabled_tc) 4658 return 0x1; /* TC0 */ 4659 4660 /* Find the first enabled TC */ 4661 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4662 if (enabled_tc & BIT(i)) 4663 break; 4664 } 4665 4666 return BIT(i); 4667 } 4668 4669 /** 4670 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes 4671 * @pf: PF being queried 4672 * 4673 * Return a bitmap for enabled traffic classes for this PF. 4674 **/ 4675 static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) 4676 { 4677 /* If DCB is not enabled for this PF then just return default TC */ 4678 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) 4679 return i40e_pf_get_default_tc(pf); 4680 4681 /* SFP mode we want PF to be enabled for all TCs */ 4682 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) 4683 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); 4684 4685 /* MFP enabled and iSCSI PF type */ 4686 if (pf->hw.func_caps.iscsi) 4687 return i40e_get_iscsi_tc_map(pf); 4688 else 4689 return i40e_pf_get_default_tc(pf); 4690 } 4691 4692 /** 4693 * i40e_vsi_get_bw_info - Query VSI BW Information 4694 * @vsi: the VSI being queried 4695 * 4696 * Returns 0 on success, negative value on failure 4697 **/ 4698 static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) 4699 { 4700 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; 4701 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; 4702 struct i40e_pf *pf = vsi->back; 4703 struct i40e_hw *hw = &pf->hw; 4704 i40e_status ret; 4705 u32 tc_bw_max; 4706 int i; 4707 4708 /* Get the VSI level BW configuration */ 4709 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); 4710 if (ret) { 4711 dev_info(&pf->pdev->dev, 4712 "couldn't get PF vsi bw config, err %s aq_err %s\n", 4713 i40e_stat_str(&pf->hw, ret), 4714 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 4715 return -EINVAL; 4716 } 4717 4718 /* Get the VSI level BW configuration per TC */ 4719 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, 4720 NULL); 4721 if (ret) { 4722 dev_info(&pf->pdev->dev, 4723 "couldn't get PF vsi ets bw config, err %s aq_err %s\n", 4724 i40e_stat_str(&pf->hw, ret), 4725 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 4726 return -EINVAL; 4727 } 4728 4729 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { 4730 dev_info(&pf->pdev->dev, 4731 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", 4732 bw_config.tc_valid_bits, 4733 bw_ets_config.tc_valid_bits); 4734 /* Still continuing */ 4735 } 4736 4737 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); 4738 vsi->bw_max_quanta = bw_config.max_bw; 4739 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | 4740 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); 4741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4742 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; 4743 vsi->bw_ets_limit_credits[i] = 4744 le16_to_cpu(bw_ets_config.credits[i]); 4745 /* 3 bits out of 4 for each TC */ 4746 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); 4747 } 4748 4749 return 0; 4750 } 4751 4752 /** 4753 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC 4754 * @vsi: the VSI being configured 4755 * @enabled_tc: TC bitmap 4756 * @bw_credits: BW shared credits per TC 4757 * 4758 * Returns 0 on success, negative value on failure 4759 **/ 4760 static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, 4761 u8 *bw_share) 4762 { 4763 struct i40e_aqc_configure_vsi_tc_bw_data bw_data; 4764 i40e_status ret; 4765 int i; 4766 4767 bw_data.tc_valid_bits = enabled_tc; 4768 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 4769 bw_data.tc_bw_credits[i] = bw_share[i]; 4770 4771 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data, 4772 NULL); 4773 if (ret) { 4774 dev_info(&vsi->back->pdev->dev, 4775 "AQ command Config VSI BW allocation per TC failed = %d\n", 4776 vsi->back->hw.aq.asq_last_status); 4777 return -EINVAL; 4778 } 4779 4780 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 4781 vsi->info.qs_handle[i] = bw_data.qs_handles[i]; 4782 4783 return 0; 4784 } 4785 4786 /** 4787 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration 4788 * @vsi: the VSI being configured 4789 * @enabled_tc: TC map to be enabled 4790 * 4791 **/ 4792 static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) 4793 { 4794 struct net_device *netdev = vsi->netdev; 4795 struct i40e_pf *pf = vsi->back; 4796 struct i40e_hw *hw = &pf->hw; 4797 u8 netdev_tc = 0; 4798 int i; 4799 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; 4800 4801 if (!netdev) 4802 return; 4803 4804 if (!enabled_tc) { 4805 netdev_reset_tc(netdev); 4806 return; 4807 } 4808 4809 /* Set up actual enabled TCs on the VSI */ 4810 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) 4811 return; 4812 4813 /* set per TC queues for the VSI */ 4814 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4815 /* Only set TC queues for enabled tcs 4816 * 4817 * e.g. For a VSI that has TC0 and TC3 enabled the 4818 * enabled_tc bitmap would be 0x00001001; the driver 4819 * will set the numtc for netdev as 2 that will be 4820 * referenced by the netdev layer as TC 0 and 1. 4821 */ 4822 if (vsi->tc_config.enabled_tc & BIT(i)) 4823 netdev_set_tc_queue(netdev, 4824 vsi->tc_config.tc_info[i].netdev_tc, 4825 vsi->tc_config.tc_info[i].qcount, 4826 vsi->tc_config.tc_info[i].qoffset); 4827 } 4828 4829 /* Assign UP2TC map for the VSI */ 4830 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { 4831 /* Get the actual TC# for the UP */ 4832 u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; 4833 /* Get the mapped netdev TC# for the UP */ 4834 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; 4835 netdev_set_prio_tc_map(netdev, i, netdev_tc); 4836 } 4837 } 4838 4839 /** 4840 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map 4841 * @vsi: the VSI being configured 4842 * @ctxt: the ctxt buffer returned from AQ VSI update param command 4843 **/ 4844 static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, 4845 struct i40e_vsi_context *ctxt) 4846 { 4847 /* copy just the sections touched not the entire info 4848 * since not all sections are valid as returned by 4849 * update vsi params 4850 */ 4851 vsi->info.mapping_flags = ctxt->info.mapping_flags; 4852 memcpy(&vsi->info.queue_mapping, 4853 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); 4854 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, 4855 sizeof(vsi->info.tc_mapping)); 4856 } 4857 4858 /** 4859 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map 4860 * @vsi: VSI to be configured 4861 * @enabled_tc: TC bitmap 4862 * 4863 * This configures a particular VSI for TCs that are mapped to the 4864 * given TC bitmap. It uses default bandwidth share for TCs across 4865 * VSIs to configure TC for a particular VSI. 4866 * 4867 * NOTE: 4868 * It is expected that the VSI queues have been quisced before calling 4869 * this function. 4870 **/ 4871 static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) 4872 { 4873 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; 4874 struct i40e_vsi_context ctxt; 4875 int ret = 0; 4876 int i; 4877 4878 /* Check if enabled_tc is same as existing or new TCs */ 4879 if (vsi->tc_config.enabled_tc == enabled_tc) 4880 return ret; 4881 4882 /* Enable ETS TCs with equal BW Share for now across all VSIs */ 4883 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4884 if (enabled_tc & BIT(i)) 4885 bw_share[i] = 1; 4886 } 4887 4888 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); 4889 if (ret) { 4890 dev_info(&vsi->back->pdev->dev, 4891 "Failed configuring TC map %d for VSI %d\n", 4892 enabled_tc, vsi->seid); 4893 goto out; 4894 } 4895 4896 /* Update Queue Pairs Mapping for currently enabled UPs */ 4897 ctxt.seid = vsi->seid; 4898 ctxt.pf_num = vsi->back->hw.pf_id; 4899 ctxt.vf_num = 0; 4900 ctxt.uplink_seid = vsi->uplink_seid; 4901 ctxt.info = vsi->info; 4902 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); 4903 4904 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { 4905 ctxt.info.valid_sections |= 4906 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); 4907 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; 4908 } 4909 4910 /* Update the VSI after updating the VSI queue-mapping information */ 4911 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 4912 if (ret) { 4913 dev_info(&vsi->back->pdev->dev, 4914 "Update vsi tc config failed, err %s aq_err %s\n", 4915 i40e_stat_str(&vsi->back->hw, ret), 4916 i40e_aq_str(&vsi->back->hw, 4917 vsi->back->hw.aq.asq_last_status)); 4918 goto out; 4919 } 4920 /* update the local VSI info with updated queue map */ 4921 i40e_vsi_update_queue_map(vsi, &ctxt); 4922 vsi->info.valid_sections = 0; 4923 4924 /* Update current VSI BW information */ 4925 ret = i40e_vsi_get_bw_info(vsi); 4926 if (ret) { 4927 dev_info(&vsi->back->pdev->dev, 4928 "Failed updating vsi bw info, err %s aq_err %s\n", 4929 i40e_stat_str(&vsi->back->hw, ret), 4930 i40e_aq_str(&vsi->back->hw, 4931 vsi->back->hw.aq.asq_last_status)); 4932 goto out; 4933 } 4934 4935 /* Update the netdev TC setup */ 4936 i40e_vsi_config_netdev_tc(vsi, enabled_tc); 4937 out: 4938 return ret; 4939 } 4940 4941 /** 4942 * i40e_veb_config_tc - Configure TCs for given VEB 4943 * @veb: given VEB 4944 * @enabled_tc: TC bitmap 4945 * 4946 * Configures given TC bitmap for VEB (switching) element 4947 **/ 4948 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) 4949 { 4950 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; 4951 struct i40e_pf *pf = veb->pf; 4952 int ret = 0; 4953 int i; 4954 4955 /* No TCs or already enabled TCs just return */ 4956 if (!enabled_tc || veb->enabled_tc == enabled_tc) 4957 return ret; 4958 4959 bw_data.tc_valid_bits = enabled_tc; 4960 /* bw_data.absolute_credits is not set (relative) */ 4961 4962 /* Enable ETS TCs with equal BW Share for now */ 4963 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 4964 if (enabled_tc & BIT(i)) 4965 bw_data.tc_bw_share_credits[i] = 1; 4966 } 4967 4968 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, 4969 &bw_data, NULL); 4970 if (ret) { 4971 dev_info(&pf->pdev->dev, 4972 "VEB bw config failed, err %s aq_err %s\n", 4973 i40e_stat_str(&pf->hw, ret), 4974 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 4975 goto out; 4976 } 4977 4978 /* Update the BW information */ 4979 ret = i40e_veb_get_bw_info(veb); 4980 if (ret) { 4981 dev_info(&pf->pdev->dev, 4982 "Failed getting veb bw config, err %s aq_err %s\n", 4983 i40e_stat_str(&pf->hw, ret), 4984 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 4985 } 4986 4987 out: 4988 return ret; 4989 } 4990 4991 #ifdef CONFIG_I40E_DCB 4992 /** 4993 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs 4994 * @pf: PF struct 4995 * 4996 * Reconfigure VEB/VSIs on a given PF; it is assumed that 4997 * the caller would've quiesce all the VSIs before calling 4998 * this function 4999 **/ 5000 static void i40e_dcb_reconfigure(struct i40e_pf *pf) 5001 { 5002 u8 tc_map = 0; 5003 int ret; 5004 u8 v; 5005 5006 /* Enable the TCs available on PF to all VEBs */ 5007 tc_map = i40e_pf_get_tc_map(pf); 5008 for (v = 0; v < I40E_MAX_VEB; v++) { 5009 if (!pf->veb[v]) 5010 continue; 5011 ret = i40e_veb_config_tc(pf->veb[v], tc_map); 5012 if (ret) { 5013 dev_info(&pf->pdev->dev, 5014 "Failed configuring TC for VEB seid=%d\n", 5015 pf->veb[v]->seid); 5016 /* Will try to configure as many components */ 5017 } 5018 } 5019 5020 /* Update each VSI */ 5021 for (v = 0; v < pf->num_alloc_vsi; v++) { 5022 if (!pf->vsi[v]) 5023 continue; 5024 5025 /* - Enable all TCs for the LAN VSI 5026 #ifdef I40E_FCOE 5027 * - For FCoE VSI only enable the TC configured 5028 * as per the APP TLV 5029 #endif 5030 * - For all others keep them at TC0 for now 5031 */ 5032 if (v == pf->lan_vsi) 5033 tc_map = i40e_pf_get_tc_map(pf); 5034 else 5035 tc_map = i40e_pf_get_default_tc(pf); 5036 #ifdef I40E_FCOE 5037 if (pf->vsi[v]->type == I40E_VSI_FCOE) 5038 tc_map = i40e_get_fcoe_tc_map(pf); 5039 #endif /* #ifdef I40E_FCOE */ 5040 5041 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); 5042 if (ret) { 5043 dev_info(&pf->pdev->dev, 5044 "Failed configuring TC for VSI seid=%d\n", 5045 pf->vsi[v]->seid); 5046 /* Will try to configure as many components */ 5047 } else { 5048 /* Re-configure VSI vectors based on updated TC map */ 5049 i40e_vsi_map_rings_to_vectors(pf->vsi[v]); 5050 if (pf->vsi[v]->netdev) 5051 i40e_dcbnl_set_all(pf->vsi[v]); 5052 } 5053 } 5054 } 5055 5056 /** 5057 * i40e_resume_port_tx - Resume port Tx 5058 * @pf: PF struct 5059 * 5060 * Resume a port's Tx and issue a PF reset in case of failure to 5061 * resume. 5062 **/ 5063 static int i40e_resume_port_tx(struct i40e_pf *pf) 5064 { 5065 struct i40e_hw *hw = &pf->hw; 5066 int ret; 5067 5068 ret = i40e_aq_resume_port_tx(hw, NULL); 5069 if (ret) { 5070 dev_info(&pf->pdev->dev, 5071 "Resume Port Tx failed, err %s aq_err %s\n", 5072 i40e_stat_str(&pf->hw, ret), 5073 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5074 /* Schedule PF reset to recover */ 5075 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 5076 i40e_service_event_schedule(pf); 5077 } 5078 5079 return ret; 5080 } 5081 5082 /** 5083 * i40e_init_pf_dcb - Initialize DCB configuration 5084 * @pf: PF being configured 5085 * 5086 * Query the current DCB configuration and cache it 5087 * in the hardware structure 5088 **/ 5089 static int i40e_init_pf_dcb(struct i40e_pf *pf) 5090 { 5091 struct i40e_hw *hw = &pf->hw; 5092 int err = 0; 5093 5094 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */ 5095 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT) 5096 goto out; 5097 5098 /* Get the initial DCB configuration */ 5099 err = i40e_init_dcb(hw); 5100 if (!err) { 5101 /* Device/Function is not DCBX capable */ 5102 if ((!hw->func_caps.dcb) || 5103 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { 5104 dev_info(&pf->pdev->dev, 5105 "DCBX offload is not supported or is disabled for this PF.\n"); 5106 5107 if (pf->flags & I40E_FLAG_MFP_ENABLED) 5108 goto out; 5109 5110 } else { 5111 /* When status is not DISABLED then DCBX in FW */ 5112 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | 5113 DCB_CAP_DCBX_VER_IEEE; 5114 5115 pf->flags |= I40E_FLAG_DCB_CAPABLE; 5116 /* Enable DCB tagging only when more than one TC */ 5117 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) 5118 pf->flags |= I40E_FLAG_DCB_ENABLED; 5119 dev_dbg(&pf->pdev->dev, 5120 "DCBX offload is supported for this PF.\n"); 5121 } 5122 } else { 5123 dev_info(&pf->pdev->dev, 5124 "Query for DCB configuration failed, err %s aq_err %s\n", 5125 i40e_stat_str(&pf->hw, err), 5126 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5127 } 5128 5129 out: 5130 return err; 5131 } 5132 #endif /* CONFIG_I40E_DCB */ 5133 #define SPEED_SIZE 14 5134 #define FC_SIZE 8 5135 /** 5136 * i40e_print_link_message - print link up or down 5137 * @vsi: the VSI for which link needs a message 5138 */ 5139 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) 5140 { 5141 char *speed = "Unknown"; 5142 char *fc = "Unknown"; 5143 5144 if (vsi->current_isup == isup) 5145 return; 5146 vsi->current_isup = isup; 5147 if (!isup) { 5148 netdev_info(vsi->netdev, "NIC Link is Down\n"); 5149 return; 5150 } 5151 5152 /* Warn user if link speed on NPAR enabled partition is not at 5153 * least 10GB 5154 */ 5155 if (vsi->back->hw.func_caps.npar_enable && 5156 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || 5157 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) 5158 netdev_warn(vsi->netdev, 5159 "The partition detected link speed that is less than 10Gbps\n"); 5160 5161 switch (vsi->back->hw.phy.link_info.link_speed) { 5162 case I40E_LINK_SPEED_40GB: 5163 speed = "40 G"; 5164 break; 5165 case I40E_LINK_SPEED_20GB: 5166 speed = "20 G"; 5167 break; 5168 case I40E_LINK_SPEED_10GB: 5169 speed = "10 G"; 5170 break; 5171 case I40E_LINK_SPEED_1GB: 5172 speed = "1000 M"; 5173 break; 5174 case I40E_LINK_SPEED_100MB: 5175 speed = "100 M"; 5176 break; 5177 default: 5178 break; 5179 } 5180 5181 switch (vsi->back->hw.fc.current_mode) { 5182 case I40E_FC_FULL: 5183 fc = "RX/TX"; 5184 break; 5185 case I40E_FC_TX_PAUSE: 5186 fc = "TX"; 5187 break; 5188 case I40E_FC_RX_PAUSE: 5189 fc = "RX"; 5190 break; 5191 default: 5192 fc = "None"; 5193 break; 5194 } 5195 5196 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n", 5197 speed, fc); 5198 } 5199 5200 /** 5201 * i40e_up_complete - Finish the last steps of bringing up a connection 5202 * @vsi: the VSI being configured 5203 **/ 5204 static int i40e_up_complete(struct i40e_vsi *vsi) 5205 { 5206 struct i40e_pf *pf = vsi->back; 5207 int err; 5208 5209 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 5210 i40e_vsi_configure_msix(vsi); 5211 else 5212 i40e_configure_msi_and_legacy(vsi); 5213 5214 /* start rings */ 5215 err = i40e_vsi_control_rings(vsi, true); 5216 if (err) 5217 return err; 5218 5219 clear_bit(__I40E_DOWN, &vsi->state); 5220 i40e_napi_enable_all(vsi); 5221 i40e_vsi_enable_irq(vsi); 5222 5223 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && 5224 (vsi->netdev)) { 5225 i40e_print_link_message(vsi, true); 5226 netif_tx_start_all_queues(vsi->netdev); 5227 netif_carrier_on(vsi->netdev); 5228 } else if (vsi->netdev) { 5229 i40e_print_link_message(vsi, false); 5230 /* need to check for qualified module here*/ 5231 if ((pf->hw.phy.link_info.link_info & 5232 I40E_AQ_MEDIA_AVAILABLE) && 5233 (!(pf->hw.phy.link_info.an_info & 5234 I40E_AQ_QUALIFIED_MODULE))) 5235 netdev_err(vsi->netdev, 5236 "the driver failed to link because an unqualified module was detected."); 5237 } 5238 5239 /* replay FDIR SB filters */ 5240 if (vsi->type == I40E_VSI_FDIR) { 5241 /* reset fd counters */ 5242 pf->fd_add_err = pf->fd_atr_cnt = 0; 5243 if (pf->fd_tcp_rule > 0) { 5244 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 5245 if (I40E_DEBUG_FD & pf->hw.debug_mask) 5246 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n"); 5247 pf->fd_tcp_rule = 0; 5248 } 5249 i40e_fdir_filter_restore(vsi); 5250 } 5251 5252 /* On the next run of the service_task, notify any clients of the new 5253 * opened netdev 5254 */ 5255 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; 5256 i40e_service_event_schedule(pf); 5257 5258 return 0; 5259 } 5260 5261 /** 5262 * i40e_vsi_reinit_locked - Reset the VSI 5263 * @vsi: the VSI being configured 5264 * 5265 * Rebuild the ring structs after some configuration 5266 * has changed, e.g. MTU size. 5267 **/ 5268 static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) 5269 { 5270 struct i40e_pf *pf = vsi->back; 5271 5272 WARN_ON(in_interrupt()); 5273 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state)) 5274 usleep_range(1000, 2000); 5275 i40e_down(vsi); 5276 5277 i40e_up(vsi); 5278 clear_bit(__I40E_CONFIG_BUSY, &pf->state); 5279 } 5280 5281 /** 5282 * i40e_up - Bring the connection back up after being down 5283 * @vsi: the VSI being configured 5284 **/ 5285 int i40e_up(struct i40e_vsi *vsi) 5286 { 5287 int err; 5288 5289 err = i40e_vsi_configure(vsi); 5290 if (!err) 5291 err = i40e_up_complete(vsi); 5292 5293 return err; 5294 } 5295 5296 /** 5297 * i40e_down - Shutdown the connection processing 5298 * @vsi: the VSI being stopped 5299 **/ 5300 void i40e_down(struct i40e_vsi *vsi) 5301 { 5302 int i; 5303 5304 /* It is assumed that the caller of this function 5305 * sets the vsi->state __I40E_DOWN bit. 5306 */ 5307 if (vsi->netdev) { 5308 netif_carrier_off(vsi->netdev); 5309 netif_tx_disable(vsi->netdev); 5310 } 5311 i40e_vsi_disable_irq(vsi); 5312 i40e_vsi_control_rings(vsi, false); 5313 i40e_napi_disable_all(vsi); 5314 5315 for (i = 0; i < vsi->num_queue_pairs; i++) { 5316 i40e_clean_tx_ring(vsi->tx_rings[i]); 5317 i40e_clean_rx_ring(vsi->rx_rings[i]); 5318 } 5319 5320 i40e_notify_client_of_netdev_close(vsi, false); 5321 5322 } 5323 5324 /** 5325 * i40e_setup_tc - configure multiple traffic classes 5326 * @netdev: net device to configure 5327 * @tc: number of traffic classes to enable 5328 **/ 5329 static int i40e_setup_tc(struct net_device *netdev, u8 tc) 5330 { 5331 struct i40e_netdev_priv *np = netdev_priv(netdev); 5332 struct i40e_vsi *vsi = np->vsi; 5333 struct i40e_pf *pf = vsi->back; 5334 u8 enabled_tc = 0; 5335 int ret = -EINVAL; 5336 int i; 5337 5338 /* Check if DCB enabled to continue */ 5339 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { 5340 netdev_info(netdev, "DCB is not enabled for adapter\n"); 5341 goto exit; 5342 } 5343 5344 /* Check if MFP enabled */ 5345 if (pf->flags & I40E_FLAG_MFP_ENABLED) { 5346 netdev_info(netdev, "Configuring TC not supported in MFP mode\n"); 5347 goto exit; 5348 } 5349 5350 /* Check whether tc count is within enabled limit */ 5351 if (tc > i40e_pf_get_num_tc(pf)) { 5352 netdev_info(netdev, "TC count greater than enabled on link for adapter\n"); 5353 goto exit; 5354 } 5355 5356 /* Generate TC map for number of tc requested */ 5357 for (i = 0; i < tc; i++) 5358 enabled_tc |= BIT(i); 5359 5360 /* Requesting same TC configuration as already enabled */ 5361 if (enabled_tc == vsi->tc_config.enabled_tc) 5362 return 0; 5363 5364 /* Quiesce VSI queues */ 5365 i40e_quiesce_vsi(vsi); 5366 5367 /* Configure VSI for enabled TCs */ 5368 ret = i40e_vsi_config_tc(vsi, enabled_tc); 5369 if (ret) { 5370 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", 5371 vsi->seid); 5372 goto exit; 5373 } 5374 5375 /* Unquiesce VSI */ 5376 i40e_unquiesce_vsi(vsi); 5377 5378 exit: 5379 return ret; 5380 } 5381 5382 #ifdef I40E_FCOE 5383 int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, 5384 struct tc_to_netdev *tc) 5385 #else 5386 static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto, 5387 struct tc_to_netdev *tc) 5388 #endif 5389 { 5390 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO) 5391 return -EINVAL; 5392 return i40e_setup_tc(netdev, tc->tc); 5393 } 5394 5395 /** 5396 * i40e_open - Called when a network interface is made active 5397 * @netdev: network interface device structure 5398 * 5399 * The open entry point is called when a network interface is made 5400 * active by the system (IFF_UP). At this point all resources needed 5401 * for transmit and receive operations are allocated, the interrupt 5402 * handler is registered with the OS, the netdev watchdog subtask is 5403 * enabled, and the stack is notified that the interface is ready. 5404 * 5405 * Returns 0 on success, negative value on failure 5406 **/ 5407 int i40e_open(struct net_device *netdev) 5408 { 5409 struct i40e_netdev_priv *np = netdev_priv(netdev); 5410 struct i40e_vsi *vsi = np->vsi; 5411 struct i40e_pf *pf = vsi->back; 5412 int err; 5413 5414 /* disallow open during test or if eeprom is broken */ 5415 if (test_bit(__I40E_TESTING, &pf->state) || 5416 test_bit(__I40E_BAD_EEPROM, &pf->state)) 5417 return -EBUSY; 5418 5419 netif_carrier_off(netdev); 5420 5421 err = i40e_vsi_open(vsi); 5422 if (err) 5423 return err; 5424 5425 /* configure global TSO hardware offload settings */ 5426 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | 5427 TCP_FLAG_FIN) >> 16); 5428 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | 5429 TCP_FLAG_FIN | 5430 TCP_FLAG_CWR) >> 16); 5431 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); 5432 5433 udp_tunnel_get_rx_info(netdev); 5434 i40e_notify_client_of_netdev_open(vsi); 5435 5436 return 0; 5437 } 5438 5439 /** 5440 * i40e_vsi_open - 5441 * @vsi: the VSI to open 5442 * 5443 * Finish initialization of the VSI. 5444 * 5445 * Returns 0 on success, negative value on failure 5446 **/ 5447 int i40e_vsi_open(struct i40e_vsi *vsi) 5448 { 5449 struct i40e_pf *pf = vsi->back; 5450 char int_name[I40E_INT_NAME_STR_LEN]; 5451 int err; 5452 5453 /* allocate descriptors */ 5454 err = i40e_vsi_setup_tx_resources(vsi); 5455 if (err) 5456 goto err_setup_tx; 5457 err = i40e_vsi_setup_rx_resources(vsi); 5458 if (err) 5459 goto err_setup_rx; 5460 5461 err = i40e_vsi_configure(vsi); 5462 if (err) 5463 goto err_setup_rx; 5464 5465 if (vsi->netdev) { 5466 snprintf(int_name, sizeof(int_name) - 1, "%s-%s", 5467 dev_driver_string(&pf->pdev->dev), vsi->netdev->name); 5468 err = i40e_vsi_request_irq(vsi, int_name); 5469 if (err) 5470 goto err_setup_rx; 5471 5472 /* Notify the stack of the actual queue counts. */ 5473 err = netif_set_real_num_tx_queues(vsi->netdev, 5474 vsi->num_queue_pairs); 5475 if (err) 5476 goto err_set_queues; 5477 5478 err = netif_set_real_num_rx_queues(vsi->netdev, 5479 vsi->num_queue_pairs); 5480 if (err) 5481 goto err_set_queues; 5482 5483 } else if (vsi->type == I40E_VSI_FDIR) { 5484 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", 5485 dev_driver_string(&pf->pdev->dev), 5486 dev_name(&pf->pdev->dev)); 5487 err = i40e_vsi_request_irq(vsi, int_name); 5488 5489 } else { 5490 err = -EINVAL; 5491 goto err_setup_rx; 5492 } 5493 5494 err = i40e_up_complete(vsi); 5495 if (err) 5496 goto err_up_complete; 5497 5498 return 0; 5499 5500 err_up_complete: 5501 i40e_down(vsi); 5502 err_set_queues: 5503 i40e_vsi_free_irq(vsi); 5504 err_setup_rx: 5505 i40e_vsi_free_rx_resources(vsi); 5506 err_setup_tx: 5507 i40e_vsi_free_tx_resources(vsi); 5508 if (vsi == pf->vsi[pf->lan_vsi]) 5509 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); 5510 5511 return err; 5512 } 5513 5514 /** 5515 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting 5516 * @pf: Pointer to PF 5517 * 5518 * This function destroys the hlist where all the Flow Director 5519 * filters were saved. 5520 **/ 5521 static void i40e_fdir_filter_exit(struct i40e_pf *pf) 5522 { 5523 struct i40e_fdir_filter *filter; 5524 struct hlist_node *node2; 5525 5526 hlist_for_each_entry_safe(filter, node2, 5527 &pf->fdir_filter_list, fdir_node) { 5528 hlist_del(&filter->fdir_node); 5529 kfree(filter); 5530 } 5531 pf->fdir_pf_active_filters = 0; 5532 } 5533 5534 /** 5535 * i40e_close - Disables a network interface 5536 * @netdev: network interface device structure 5537 * 5538 * The close entry point is called when an interface is de-activated 5539 * by the OS. The hardware is still under the driver's control, but 5540 * this netdev interface is disabled. 5541 * 5542 * Returns 0, this is not allowed to fail 5543 **/ 5544 int i40e_close(struct net_device *netdev) 5545 { 5546 struct i40e_netdev_priv *np = netdev_priv(netdev); 5547 struct i40e_vsi *vsi = np->vsi; 5548 5549 i40e_vsi_close(vsi); 5550 5551 return 0; 5552 } 5553 5554 /** 5555 * i40e_do_reset - Start a PF or Core Reset sequence 5556 * @pf: board private structure 5557 * @reset_flags: which reset is requested 5558 * 5559 * The essential difference in resets is that the PF Reset 5560 * doesn't clear the packet buffers, doesn't reset the PE 5561 * firmware, and doesn't bother the other PFs on the chip. 5562 **/ 5563 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags) 5564 { 5565 u32 val; 5566 5567 WARN_ON(in_interrupt()); 5568 5569 5570 /* do the biggest reset indicated */ 5571 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { 5572 5573 /* Request a Global Reset 5574 * 5575 * This will start the chip's countdown to the actual full 5576 * chip reset event, and a warning interrupt to be sent 5577 * to all PFs, including the requestor. Our handler 5578 * for the warning interrupt will deal with the shutdown 5579 * and recovery of the switch setup. 5580 */ 5581 dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); 5582 val = rd32(&pf->hw, I40E_GLGEN_RTRIG); 5583 val |= I40E_GLGEN_RTRIG_GLOBR_MASK; 5584 wr32(&pf->hw, I40E_GLGEN_RTRIG, val); 5585 5586 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { 5587 5588 /* Request a Core Reset 5589 * 5590 * Same as Global Reset, except does *not* include the MAC/PHY 5591 */ 5592 dev_dbg(&pf->pdev->dev, "CoreR requested\n"); 5593 val = rd32(&pf->hw, I40E_GLGEN_RTRIG); 5594 val |= I40E_GLGEN_RTRIG_CORER_MASK; 5595 wr32(&pf->hw, I40E_GLGEN_RTRIG, val); 5596 i40e_flush(&pf->hw); 5597 5598 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) { 5599 5600 /* Request a PF Reset 5601 * 5602 * Resets only the PF-specific registers 5603 * 5604 * This goes directly to the tear-down and rebuild of 5605 * the switch, since we need to do all the recovery as 5606 * for the Core Reset. 5607 */ 5608 dev_dbg(&pf->pdev->dev, "PFR requested\n"); 5609 i40e_handle_reset_warning(pf); 5610 5611 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { 5612 int v; 5613 5614 /* Find the VSI(s) that requested a re-init */ 5615 dev_info(&pf->pdev->dev, 5616 "VSI reinit requested\n"); 5617 for (v = 0; v < pf->num_alloc_vsi; v++) { 5618 struct i40e_vsi *vsi = pf->vsi[v]; 5619 5620 if (vsi != NULL && 5621 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) { 5622 i40e_vsi_reinit_locked(pf->vsi[v]); 5623 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state); 5624 } 5625 } 5626 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { 5627 int v; 5628 5629 /* Find the VSI(s) that needs to be brought down */ 5630 dev_info(&pf->pdev->dev, "VSI down requested\n"); 5631 for (v = 0; v < pf->num_alloc_vsi; v++) { 5632 struct i40e_vsi *vsi = pf->vsi[v]; 5633 5634 if (vsi != NULL && 5635 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) { 5636 set_bit(__I40E_DOWN, &vsi->state); 5637 i40e_down(vsi); 5638 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state); 5639 } 5640 } 5641 } else { 5642 dev_info(&pf->pdev->dev, 5643 "bad reset request 0x%08x\n", reset_flags); 5644 } 5645 } 5646 5647 #ifdef CONFIG_I40E_DCB 5648 /** 5649 * i40e_dcb_need_reconfig - Check if DCB needs reconfig 5650 * @pf: board private structure 5651 * @old_cfg: current DCB config 5652 * @new_cfg: new DCB config 5653 **/ 5654 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 5655 struct i40e_dcbx_config *old_cfg, 5656 struct i40e_dcbx_config *new_cfg) 5657 { 5658 bool need_reconfig = false; 5659 5660 /* Check if ETS configuration has changed */ 5661 if (memcmp(&new_cfg->etscfg, 5662 &old_cfg->etscfg, 5663 sizeof(new_cfg->etscfg))) { 5664 /* If Priority Table has changed reconfig is needed */ 5665 if (memcmp(&new_cfg->etscfg.prioritytable, 5666 &old_cfg->etscfg.prioritytable, 5667 sizeof(new_cfg->etscfg.prioritytable))) { 5668 need_reconfig = true; 5669 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); 5670 } 5671 5672 if (memcmp(&new_cfg->etscfg.tcbwtable, 5673 &old_cfg->etscfg.tcbwtable, 5674 sizeof(new_cfg->etscfg.tcbwtable))) 5675 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); 5676 5677 if (memcmp(&new_cfg->etscfg.tsatable, 5678 &old_cfg->etscfg.tsatable, 5679 sizeof(new_cfg->etscfg.tsatable))) 5680 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); 5681 } 5682 5683 /* Check if PFC configuration has changed */ 5684 if (memcmp(&new_cfg->pfc, 5685 &old_cfg->pfc, 5686 sizeof(new_cfg->pfc))) { 5687 need_reconfig = true; 5688 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); 5689 } 5690 5691 /* Check if APP Table has changed */ 5692 if (memcmp(&new_cfg->app, 5693 &old_cfg->app, 5694 sizeof(new_cfg->app))) { 5695 need_reconfig = true; 5696 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); 5697 } 5698 5699 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); 5700 return need_reconfig; 5701 } 5702 5703 /** 5704 * i40e_handle_lldp_event - Handle LLDP Change MIB event 5705 * @pf: board private structure 5706 * @e: event info posted on ARQ 5707 **/ 5708 static int i40e_handle_lldp_event(struct i40e_pf *pf, 5709 struct i40e_arq_event_info *e) 5710 { 5711 struct i40e_aqc_lldp_get_mib *mib = 5712 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; 5713 struct i40e_hw *hw = &pf->hw; 5714 struct i40e_dcbx_config tmp_dcbx_cfg; 5715 bool need_reconfig = false; 5716 int ret = 0; 5717 u8 type; 5718 5719 /* Not DCB capable or capability disabled */ 5720 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) 5721 return ret; 5722 5723 /* Ignore if event is not for Nearest Bridge */ 5724 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) 5725 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 5726 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); 5727 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) 5728 return ret; 5729 5730 /* Check MIB Type and return if event for Remote MIB update */ 5731 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; 5732 dev_dbg(&pf->pdev->dev, 5733 "LLDP event mib type %s\n", type ? "remote" : "local"); 5734 if (type == I40E_AQ_LLDP_MIB_REMOTE) { 5735 /* Update the remote cached instance and return */ 5736 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, 5737 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 5738 &hw->remote_dcbx_config); 5739 goto exit; 5740 } 5741 5742 /* Store the old configuration */ 5743 tmp_dcbx_cfg = hw->local_dcbx_config; 5744 5745 /* Reset the old DCBx configuration data */ 5746 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); 5747 /* Get updated DCBX data from firmware */ 5748 ret = i40e_get_dcb_config(&pf->hw); 5749 if (ret) { 5750 dev_info(&pf->pdev->dev, 5751 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", 5752 i40e_stat_str(&pf->hw, ret), 5753 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 5754 goto exit; 5755 } 5756 5757 /* No change detected in DCBX configs */ 5758 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, 5759 sizeof(tmp_dcbx_cfg))) { 5760 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); 5761 goto exit; 5762 } 5763 5764 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, 5765 &hw->local_dcbx_config); 5766 5767 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); 5768 5769 if (!need_reconfig) 5770 goto exit; 5771 5772 /* Enable DCB tagging only when more than one TC */ 5773 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) 5774 pf->flags |= I40E_FLAG_DCB_ENABLED; 5775 else 5776 pf->flags &= ~I40E_FLAG_DCB_ENABLED; 5777 5778 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); 5779 /* Reconfiguration needed quiesce all VSIs */ 5780 i40e_pf_quiesce_all_vsi(pf); 5781 5782 /* Changes in configuration update VEB/VSI */ 5783 i40e_dcb_reconfigure(pf); 5784 5785 ret = i40e_resume_port_tx(pf); 5786 5787 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state); 5788 /* In case of error no point in resuming VSIs */ 5789 if (ret) 5790 goto exit; 5791 5792 /* Wait for the PF's queues to be disabled */ 5793 ret = i40e_pf_wait_queues_disabled(pf); 5794 if (ret) { 5795 /* Schedule PF reset to recover */ 5796 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 5797 i40e_service_event_schedule(pf); 5798 } else { 5799 i40e_pf_unquiesce_all_vsi(pf); 5800 /* Notify the client for the DCB changes */ 5801 i40e_notify_client_of_l2_param_changes(pf->vsi[pf->lan_vsi]); 5802 } 5803 5804 exit: 5805 return ret; 5806 } 5807 #endif /* CONFIG_I40E_DCB */ 5808 5809 /** 5810 * i40e_do_reset_safe - Protected reset path for userland calls. 5811 * @pf: board private structure 5812 * @reset_flags: which reset is requested 5813 * 5814 **/ 5815 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) 5816 { 5817 rtnl_lock(); 5818 i40e_do_reset(pf, reset_flags); 5819 rtnl_unlock(); 5820 } 5821 5822 /** 5823 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event 5824 * @pf: board private structure 5825 * @e: event info posted on ARQ 5826 * 5827 * Handler for LAN Queue Overflow Event generated by the firmware for PF 5828 * and VF queues 5829 **/ 5830 static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, 5831 struct i40e_arq_event_info *e) 5832 { 5833 struct i40e_aqc_lan_overflow *data = 5834 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; 5835 u32 queue = le32_to_cpu(data->prtdcb_rupto); 5836 u32 qtx_ctl = le32_to_cpu(data->otx_ctl); 5837 struct i40e_hw *hw = &pf->hw; 5838 struct i40e_vf *vf; 5839 u16 vf_id; 5840 5841 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", 5842 queue, qtx_ctl); 5843 5844 /* Queue belongs to VF, find the VF and issue VF reset */ 5845 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) 5846 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { 5847 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) 5848 >> I40E_QTX_CTL_VFVM_INDX_SHIFT); 5849 vf_id -= hw->func_caps.vf_base_id; 5850 vf = &pf->vf[vf_id]; 5851 i40e_vc_notify_vf_reset(vf); 5852 /* Allow VF to process pending reset notification */ 5853 msleep(20); 5854 i40e_reset_vf(vf, false); 5855 } 5856 } 5857 5858 /** 5859 * i40e_service_event_complete - Finish up the service event 5860 * @pf: board private structure 5861 **/ 5862 static void i40e_service_event_complete(struct i40e_pf *pf) 5863 { 5864 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state)); 5865 5866 /* flush memory to make sure state is correct before next watchog */ 5867 smp_mb__before_atomic(); 5868 clear_bit(__I40E_SERVICE_SCHED, &pf->state); 5869 } 5870 5871 /** 5872 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters 5873 * @pf: board private structure 5874 **/ 5875 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) 5876 { 5877 u32 val, fcnt_prog; 5878 5879 val = rd32(&pf->hw, I40E_PFQF_FDSTAT); 5880 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); 5881 return fcnt_prog; 5882 } 5883 5884 /** 5885 * i40e_get_current_fd_count - Get total FD filters programmed for this PF 5886 * @pf: board private structure 5887 **/ 5888 u32 i40e_get_current_fd_count(struct i40e_pf *pf) 5889 { 5890 u32 val, fcnt_prog; 5891 5892 val = rd32(&pf->hw, I40E_PFQF_FDSTAT); 5893 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + 5894 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> 5895 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); 5896 return fcnt_prog; 5897 } 5898 5899 /** 5900 * i40e_get_global_fd_count - Get total FD filters programmed on device 5901 * @pf: board private structure 5902 **/ 5903 u32 i40e_get_global_fd_count(struct i40e_pf *pf) 5904 { 5905 u32 val, fcnt_prog; 5906 5907 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); 5908 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + 5909 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> 5910 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); 5911 return fcnt_prog; 5912 } 5913 5914 /** 5915 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled 5916 * @pf: board private structure 5917 **/ 5918 void i40e_fdir_check_and_reenable(struct i40e_pf *pf) 5919 { 5920 struct i40e_fdir_filter *filter; 5921 u32 fcnt_prog, fcnt_avail; 5922 struct hlist_node *node; 5923 5924 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) 5925 return; 5926 5927 /* Check if, FD SB or ATR was auto disabled and if there is enough room 5928 * to re-enable 5929 */ 5930 fcnt_prog = i40e_get_global_fd_count(pf); 5931 fcnt_avail = pf->fdir_pf_filter_count; 5932 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || 5933 (pf->fd_add_err == 0) || 5934 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) { 5935 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 5936 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { 5937 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; 5938 if (I40E_DEBUG_FD & pf->hw.debug_mask) 5939 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); 5940 } 5941 } 5942 /* Wait for some more space to be available to turn on ATR */ 5943 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) { 5944 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && 5945 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) { 5946 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; 5947 if (I40E_DEBUG_FD & pf->hw.debug_mask) 5948 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n"); 5949 } 5950 } 5951 5952 /* if hw had a problem adding a filter, delete it */ 5953 if (pf->fd_inv > 0) { 5954 hlist_for_each_entry_safe(filter, node, 5955 &pf->fdir_filter_list, fdir_node) { 5956 if (filter->fd_id == pf->fd_inv) { 5957 hlist_del(&filter->fdir_node); 5958 kfree(filter); 5959 pf->fdir_pf_active_filters--; 5960 } 5961 } 5962 } 5963 } 5964 5965 #define I40E_MIN_FD_FLUSH_INTERVAL 10 5966 #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 5967 /** 5968 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB 5969 * @pf: board private structure 5970 **/ 5971 static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) 5972 { 5973 unsigned long min_flush_time; 5974 int flush_wait_retry = 50; 5975 bool disable_atr = false; 5976 int fd_room; 5977 int reg; 5978 5979 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))) 5980 return; 5981 5982 if (!time_after(jiffies, pf->fd_flush_timestamp + 5983 (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) 5984 return; 5985 5986 /* If the flush is happening too quick and we have mostly SB rules we 5987 * should not re-enable ATR for some time. 5988 */ 5989 min_flush_time = pf->fd_flush_timestamp + 5990 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); 5991 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; 5992 5993 if (!(time_after(jiffies, min_flush_time)) && 5994 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { 5995 if (I40E_DEBUG_FD & pf->hw.debug_mask) 5996 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); 5997 disable_atr = true; 5998 } 5999 6000 pf->fd_flush_timestamp = jiffies; 6001 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 6002 /* flush all filters */ 6003 wr32(&pf->hw, I40E_PFQF_CTL_1, 6004 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); 6005 i40e_flush(&pf->hw); 6006 pf->fd_flush_cnt++; 6007 pf->fd_add_err = 0; 6008 do { 6009 /* Check FD flush status every 5-6msec */ 6010 usleep_range(5000, 6000); 6011 reg = rd32(&pf->hw, I40E_PFQF_CTL_1); 6012 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) 6013 break; 6014 } while (flush_wait_retry--); 6015 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { 6016 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); 6017 } else { 6018 /* replay sideband filters */ 6019 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); 6020 if (!disable_atr) 6021 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 6022 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); 6023 if (I40E_DEBUG_FD & pf->hw.debug_mask) 6024 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); 6025 } 6026 } 6027 6028 /** 6029 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed 6030 * @pf: board private structure 6031 **/ 6032 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) 6033 { 6034 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; 6035 } 6036 6037 /* We can see up to 256 filter programming desc in transit if the filters are 6038 * being applied really fast; before we see the first 6039 * filter miss error on Rx queue 0. Accumulating enough error messages before 6040 * reacting will make sure we don't cause flush too often. 6041 */ 6042 #define I40E_MAX_FD_PROGRAM_ERROR 256 6043 6044 /** 6045 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table 6046 * @pf: board private structure 6047 **/ 6048 static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) 6049 { 6050 6051 /* if interface is down do nothing */ 6052 if (test_bit(__I40E_DOWN, &pf->state)) 6053 return; 6054 6055 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))) 6056 return; 6057 6058 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) 6059 i40e_fdir_flush_and_replay(pf); 6060 6061 i40e_fdir_check_and_reenable(pf); 6062 6063 } 6064 6065 /** 6066 * i40e_vsi_link_event - notify VSI of a link event 6067 * @vsi: vsi to be notified 6068 * @link_up: link up or down 6069 **/ 6070 static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) 6071 { 6072 if (!vsi || test_bit(__I40E_DOWN, &vsi->state)) 6073 return; 6074 6075 switch (vsi->type) { 6076 case I40E_VSI_MAIN: 6077 #ifdef I40E_FCOE 6078 case I40E_VSI_FCOE: 6079 #endif 6080 if (!vsi->netdev || !vsi->netdev_registered) 6081 break; 6082 6083 if (link_up) { 6084 netif_carrier_on(vsi->netdev); 6085 netif_tx_wake_all_queues(vsi->netdev); 6086 } else { 6087 netif_carrier_off(vsi->netdev); 6088 netif_tx_stop_all_queues(vsi->netdev); 6089 } 6090 break; 6091 6092 case I40E_VSI_SRIOV: 6093 case I40E_VSI_VMDQ2: 6094 case I40E_VSI_CTRL: 6095 case I40E_VSI_IWARP: 6096 case I40E_VSI_MIRROR: 6097 default: 6098 /* there is no notification for other VSIs */ 6099 break; 6100 } 6101 } 6102 6103 /** 6104 * i40e_veb_link_event - notify elements on the veb of a link event 6105 * @veb: veb to be notified 6106 * @link_up: link up or down 6107 **/ 6108 static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) 6109 { 6110 struct i40e_pf *pf; 6111 int i; 6112 6113 if (!veb || !veb->pf) 6114 return; 6115 pf = veb->pf; 6116 6117 /* depth first... */ 6118 for (i = 0; i < I40E_MAX_VEB; i++) 6119 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) 6120 i40e_veb_link_event(pf->veb[i], link_up); 6121 6122 /* ... now the local VSIs */ 6123 for (i = 0; i < pf->num_alloc_vsi; i++) 6124 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) 6125 i40e_vsi_link_event(pf->vsi[i], link_up); 6126 } 6127 6128 /** 6129 * i40e_link_event - Update netif_carrier status 6130 * @pf: board private structure 6131 **/ 6132 static void i40e_link_event(struct i40e_pf *pf) 6133 { 6134 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 6135 u8 new_link_speed, old_link_speed; 6136 i40e_status status; 6137 bool new_link, old_link; 6138 6139 /* save off old link status information */ 6140 pf->hw.phy.link_info_old = pf->hw.phy.link_info; 6141 6142 /* set this to force the get_link_status call to refresh state */ 6143 pf->hw.phy.get_link_info = true; 6144 6145 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); 6146 6147 status = i40e_get_link_status(&pf->hw, &new_link); 6148 if (status) { 6149 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", 6150 status); 6151 return; 6152 } 6153 6154 old_link_speed = pf->hw.phy.link_info_old.link_speed; 6155 new_link_speed = pf->hw.phy.link_info.link_speed; 6156 6157 if (new_link == old_link && 6158 new_link_speed == old_link_speed && 6159 (test_bit(__I40E_DOWN, &vsi->state) || 6160 new_link == netif_carrier_ok(vsi->netdev))) 6161 return; 6162 6163 if (!test_bit(__I40E_DOWN, &vsi->state)) 6164 i40e_print_link_message(vsi, new_link); 6165 6166 /* Notify the base of the switch tree connected to 6167 * the link. Floating VEBs are not notified. 6168 */ 6169 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) 6170 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); 6171 else 6172 i40e_vsi_link_event(vsi, new_link); 6173 6174 if (pf->vf) 6175 i40e_vc_notify_link_state(pf); 6176 6177 if (pf->flags & I40E_FLAG_PTP) 6178 i40e_ptp_set_increment(pf); 6179 } 6180 6181 /** 6182 * i40e_watchdog_subtask - periodic checks not using event driven response 6183 * @pf: board private structure 6184 **/ 6185 static void i40e_watchdog_subtask(struct i40e_pf *pf) 6186 { 6187 int i; 6188 6189 /* if interface is down do nothing */ 6190 if (test_bit(__I40E_DOWN, &pf->state) || 6191 test_bit(__I40E_CONFIG_BUSY, &pf->state)) 6192 return; 6193 6194 /* make sure we don't do these things too often */ 6195 if (time_before(jiffies, (pf->service_timer_previous + 6196 pf->service_timer_period))) 6197 return; 6198 pf->service_timer_previous = jiffies; 6199 6200 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) 6201 i40e_link_event(pf); 6202 6203 /* Update the stats for active netdevs so the network stack 6204 * can look at updated numbers whenever it cares to 6205 */ 6206 for (i = 0; i < pf->num_alloc_vsi; i++) 6207 if (pf->vsi[i] && pf->vsi[i]->netdev) 6208 i40e_update_stats(pf->vsi[i]); 6209 6210 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { 6211 /* Update the stats for the active switching components */ 6212 for (i = 0; i < I40E_MAX_VEB; i++) 6213 if (pf->veb[i]) 6214 i40e_update_veb_stats(pf->veb[i]); 6215 } 6216 6217 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]); 6218 } 6219 6220 /** 6221 * i40e_reset_subtask - Set up for resetting the device and driver 6222 * @pf: board private structure 6223 **/ 6224 static void i40e_reset_subtask(struct i40e_pf *pf) 6225 { 6226 u32 reset_flags = 0; 6227 6228 rtnl_lock(); 6229 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) { 6230 reset_flags |= BIT(__I40E_REINIT_REQUESTED); 6231 clear_bit(__I40E_REINIT_REQUESTED, &pf->state); 6232 } 6233 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) { 6234 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); 6235 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 6236 } 6237 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) { 6238 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); 6239 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state); 6240 } 6241 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) { 6242 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); 6243 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state); 6244 } 6245 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) { 6246 reset_flags |= BIT(__I40E_DOWN_REQUESTED); 6247 clear_bit(__I40E_DOWN_REQUESTED, &pf->state); 6248 } 6249 6250 /* If there's a recovery already waiting, it takes 6251 * precedence before starting a new reset sequence. 6252 */ 6253 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) { 6254 i40e_handle_reset_warning(pf); 6255 goto unlock; 6256 } 6257 6258 /* If we're already down or resetting, just bail */ 6259 if (reset_flags && 6260 !test_bit(__I40E_DOWN, &pf->state) && 6261 !test_bit(__I40E_CONFIG_BUSY, &pf->state)) 6262 i40e_do_reset(pf, reset_flags); 6263 6264 unlock: 6265 rtnl_unlock(); 6266 } 6267 6268 /** 6269 * i40e_handle_link_event - Handle link event 6270 * @pf: board private structure 6271 * @e: event info posted on ARQ 6272 **/ 6273 static void i40e_handle_link_event(struct i40e_pf *pf, 6274 struct i40e_arq_event_info *e) 6275 { 6276 struct i40e_aqc_get_link_status *status = 6277 (struct i40e_aqc_get_link_status *)&e->desc.params.raw; 6278 6279 /* Do a new status request to re-enable LSE reporting 6280 * and load new status information into the hw struct 6281 * This completely ignores any state information 6282 * in the ARQ event info, instead choosing to always 6283 * issue the AQ update link status command. 6284 */ 6285 i40e_link_event(pf); 6286 6287 /* check for unqualified module, if link is down */ 6288 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && 6289 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && 6290 (!(status->link_info & I40E_AQ_LINK_UP))) 6291 dev_err(&pf->pdev->dev, 6292 "The driver failed to link because an unqualified module was detected.\n"); 6293 } 6294 6295 /** 6296 * i40e_clean_adminq_subtask - Clean the AdminQ rings 6297 * @pf: board private structure 6298 **/ 6299 static void i40e_clean_adminq_subtask(struct i40e_pf *pf) 6300 { 6301 struct i40e_arq_event_info event; 6302 struct i40e_hw *hw = &pf->hw; 6303 u16 pending, i = 0; 6304 i40e_status ret; 6305 u16 opcode; 6306 u32 oldval; 6307 u32 val; 6308 6309 /* Do not run clean AQ when PF reset fails */ 6310 if (test_bit(__I40E_RESET_FAILED, &pf->state)) 6311 return; 6312 6313 /* check for error indications */ 6314 val = rd32(&pf->hw, pf->hw.aq.arq.len); 6315 oldval = val; 6316 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { 6317 if (hw->debug_mask & I40E_DEBUG_AQ) 6318 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); 6319 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; 6320 } 6321 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { 6322 if (hw->debug_mask & I40E_DEBUG_AQ) 6323 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); 6324 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; 6325 pf->arq_overflows++; 6326 } 6327 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { 6328 if (hw->debug_mask & I40E_DEBUG_AQ) 6329 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); 6330 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; 6331 } 6332 if (oldval != val) 6333 wr32(&pf->hw, pf->hw.aq.arq.len, val); 6334 6335 val = rd32(&pf->hw, pf->hw.aq.asq.len); 6336 oldval = val; 6337 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { 6338 if (pf->hw.debug_mask & I40E_DEBUG_AQ) 6339 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); 6340 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; 6341 } 6342 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { 6343 if (pf->hw.debug_mask & I40E_DEBUG_AQ) 6344 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); 6345 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; 6346 } 6347 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { 6348 if (pf->hw.debug_mask & I40E_DEBUG_AQ) 6349 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); 6350 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; 6351 } 6352 if (oldval != val) 6353 wr32(&pf->hw, pf->hw.aq.asq.len, val); 6354 6355 event.buf_len = I40E_MAX_AQ_BUF_SIZE; 6356 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); 6357 if (!event.msg_buf) 6358 return; 6359 6360 do { 6361 ret = i40e_clean_arq_element(hw, &event, &pending); 6362 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) 6363 break; 6364 else if (ret) { 6365 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); 6366 break; 6367 } 6368 6369 opcode = le16_to_cpu(event.desc.opcode); 6370 switch (opcode) { 6371 6372 case i40e_aqc_opc_get_link_status: 6373 i40e_handle_link_event(pf, &event); 6374 break; 6375 case i40e_aqc_opc_send_msg_to_pf: 6376 ret = i40e_vc_process_vf_msg(pf, 6377 le16_to_cpu(event.desc.retval), 6378 le32_to_cpu(event.desc.cookie_high), 6379 le32_to_cpu(event.desc.cookie_low), 6380 event.msg_buf, 6381 event.msg_len); 6382 break; 6383 case i40e_aqc_opc_lldp_update_mib: 6384 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); 6385 #ifdef CONFIG_I40E_DCB 6386 rtnl_lock(); 6387 ret = i40e_handle_lldp_event(pf, &event); 6388 rtnl_unlock(); 6389 #endif /* CONFIG_I40E_DCB */ 6390 break; 6391 case i40e_aqc_opc_event_lan_overflow: 6392 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); 6393 i40e_handle_lan_overflow_event(pf, &event); 6394 break; 6395 case i40e_aqc_opc_send_msg_to_peer: 6396 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); 6397 break; 6398 case i40e_aqc_opc_nvm_erase: 6399 case i40e_aqc_opc_nvm_update: 6400 case i40e_aqc_opc_oem_post_update: 6401 i40e_debug(&pf->hw, I40E_DEBUG_NVM, 6402 "ARQ NVM operation 0x%04x completed\n", 6403 opcode); 6404 break; 6405 default: 6406 dev_info(&pf->pdev->dev, 6407 "ARQ: Unknown event 0x%04x ignored\n", 6408 opcode); 6409 break; 6410 } 6411 } while (pending && (i++ < pf->adminq_work_limit)); 6412 6413 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state); 6414 /* re-enable Admin queue interrupt cause */ 6415 val = rd32(hw, I40E_PFINT_ICR0_ENA); 6416 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 6417 wr32(hw, I40E_PFINT_ICR0_ENA, val); 6418 i40e_flush(hw); 6419 6420 kfree(event.msg_buf); 6421 } 6422 6423 /** 6424 * i40e_verify_eeprom - make sure eeprom is good to use 6425 * @pf: board private structure 6426 **/ 6427 static void i40e_verify_eeprom(struct i40e_pf *pf) 6428 { 6429 int err; 6430 6431 err = i40e_diag_eeprom_test(&pf->hw); 6432 if (err) { 6433 /* retry in case of garbage read */ 6434 err = i40e_diag_eeprom_test(&pf->hw); 6435 if (err) { 6436 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", 6437 err); 6438 set_bit(__I40E_BAD_EEPROM, &pf->state); 6439 } 6440 } 6441 6442 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) { 6443 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); 6444 clear_bit(__I40E_BAD_EEPROM, &pf->state); 6445 } 6446 } 6447 6448 /** 6449 * i40e_enable_pf_switch_lb 6450 * @pf: pointer to the PF structure 6451 * 6452 * enable switch loop back or die - no point in a return value 6453 **/ 6454 static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) 6455 { 6456 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 6457 struct i40e_vsi_context ctxt; 6458 int ret; 6459 6460 ctxt.seid = pf->main_vsi_seid; 6461 ctxt.pf_num = pf->hw.pf_id; 6462 ctxt.vf_num = 0; 6463 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); 6464 if (ret) { 6465 dev_info(&pf->pdev->dev, 6466 "couldn't get PF vsi config, err %s aq_err %s\n", 6467 i40e_stat_str(&pf->hw, ret), 6468 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6469 return; 6470 } 6471 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 6472 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); 6473 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 6474 6475 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 6476 if (ret) { 6477 dev_info(&pf->pdev->dev, 6478 "update vsi switch failed, err %s aq_err %s\n", 6479 i40e_stat_str(&pf->hw, ret), 6480 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6481 } 6482 } 6483 6484 /** 6485 * i40e_disable_pf_switch_lb 6486 * @pf: pointer to the PF structure 6487 * 6488 * disable switch loop back or die - no point in a return value 6489 **/ 6490 static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) 6491 { 6492 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 6493 struct i40e_vsi_context ctxt; 6494 int ret; 6495 6496 ctxt.seid = pf->main_vsi_seid; 6497 ctxt.pf_num = pf->hw.pf_id; 6498 ctxt.vf_num = 0; 6499 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); 6500 if (ret) { 6501 dev_info(&pf->pdev->dev, 6502 "couldn't get PF vsi config, err %s aq_err %s\n", 6503 i40e_stat_str(&pf->hw, ret), 6504 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6505 return; 6506 } 6507 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 6508 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); 6509 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 6510 6511 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); 6512 if (ret) { 6513 dev_info(&pf->pdev->dev, 6514 "update vsi switch failed, err %s aq_err %s\n", 6515 i40e_stat_str(&pf->hw, ret), 6516 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6517 } 6518 } 6519 6520 /** 6521 * i40e_config_bridge_mode - Configure the HW bridge mode 6522 * @veb: pointer to the bridge instance 6523 * 6524 * Configure the loop back mode for the LAN VSI that is downlink to the 6525 * specified HW bridge instance. It is expected this function is called 6526 * when a new HW bridge is instantiated. 6527 **/ 6528 static void i40e_config_bridge_mode(struct i40e_veb *veb) 6529 { 6530 struct i40e_pf *pf = veb->pf; 6531 6532 if (pf->hw.debug_mask & I40E_DEBUG_LAN) 6533 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", 6534 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 6535 if (veb->bridge_mode & BRIDGE_MODE_VEPA) 6536 i40e_disable_pf_switch_lb(pf); 6537 else 6538 i40e_enable_pf_switch_lb(pf); 6539 } 6540 6541 /** 6542 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it 6543 * @veb: pointer to the VEB instance 6544 * 6545 * This is a recursive function that first builds the attached VSIs then 6546 * recurses in to build the next layer of VEB. We track the connections 6547 * through our own index numbers because the seid's from the HW could 6548 * change across the reset. 6549 **/ 6550 static int i40e_reconstitute_veb(struct i40e_veb *veb) 6551 { 6552 struct i40e_vsi *ctl_vsi = NULL; 6553 struct i40e_pf *pf = veb->pf; 6554 int v, veb_idx; 6555 int ret; 6556 6557 /* build VSI that owns this VEB, temporarily attached to base VEB */ 6558 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { 6559 if (pf->vsi[v] && 6560 pf->vsi[v]->veb_idx == veb->idx && 6561 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { 6562 ctl_vsi = pf->vsi[v]; 6563 break; 6564 } 6565 } 6566 if (!ctl_vsi) { 6567 dev_info(&pf->pdev->dev, 6568 "missing owner VSI for veb_idx %d\n", veb->idx); 6569 ret = -ENOENT; 6570 goto end_reconstitute; 6571 } 6572 if (ctl_vsi != pf->vsi[pf->lan_vsi]) 6573 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; 6574 ret = i40e_add_vsi(ctl_vsi); 6575 if (ret) { 6576 dev_info(&pf->pdev->dev, 6577 "rebuild of veb_idx %d owner VSI failed: %d\n", 6578 veb->idx, ret); 6579 goto end_reconstitute; 6580 } 6581 i40e_vsi_reset_stats(ctl_vsi); 6582 6583 /* create the VEB in the switch and move the VSI onto the VEB */ 6584 ret = i40e_add_veb(veb, ctl_vsi); 6585 if (ret) 6586 goto end_reconstitute; 6587 6588 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) 6589 veb->bridge_mode = BRIDGE_MODE_VEB; 6590 else 6591 veb->bridge_mode = BRIDGE_MODE_VEPA; 6592 i40e_config_bridge_mode(veb); 6593 6594 /* create the remaining VSIs attached to this VEB */ 6595 for (v = 0; v < pf->num_alloc_vsi; v++) { 6596 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) 6597 continue; 6598 6599 if (pf->vsi[v]->veb_idx == veb->idx) { 6600 struct i40e_vsi *vsi = pf->vsi[v]; 6601 6602 vsi->uplink_seid = veb->seid; 6603 ret = i40e_add_vsi(vsi); 6604 if (ret) { 6605 dev_info(&pf->pdev->dev, 6606 "rebuild of vsi_idx %d failed: %d\n", 6607 v, ret); 6608 goto end_reconstitute; 6609 } 6610 i40e_vsi_reset_stats(vsi); 6611 } 6612 } 6613 6614 /* create any VEBs attached to this VEB - RECURSION */ 6615 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { 6616 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { 6617 pf->veb[veb_idx]->uplink_seid = veb->seid; 6618 ret = i40e_reconstitute_veb(pf->veb[veb_idx]); 6619 if (ret) 6620 break; 6621 } 6622 } 6623 6624 end_reconstitute: 6625 return ret; 6626 } 6627 6628 /** 6629 * i40e_get_capabilities - get info about the HW 6630 * @pf: the PF struct 6631 **/ 6632 static int i40e_get_capabilities(struct i40e_pf *pf) 6633 { 6634 struct i40e_aqc_list_capabilities_element_resp *cap_buf; 6635 u16 data_size; 6636 int buf_len; 6637 int err; 6638 6639 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 6640 do { 6641 cap_buf = kzalloc(buf_len, GFP_KERNEL); 6642 if (!cap_buf) 6643 return -ENOMEM; 6644 6645 /* this loads the data into the hw struct for us */ 6646 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, 6647 &data_size, 6648 i40e_aqc_opc_list_func_capabilities, 6649 NULL); 6650 /* data loaded, buffer no longer needed */ 6651 kfree(cap_buf); 6652 6653 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { 6654 /* retry with a larger buffer */ 6655 buf_len = data_size; 6656 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 6657 dev_info(&pf->pdev->dev, 6658 "capability discovery failed, err %s aq_err %s\n", 6659 i40e_stat_str(&pf->hw, err), 6660 i40e_aq_str(&pf->hw, 6661 pf->hw.aq.asq_last_status)); 6662 return -ENODEV; 6663 } 6664 } while (err); 6665 6666 if (pf->hw.debug_mask & I40E_DEBUG_USER) 6667 dev_info(&pf->pdev->dev, 6668 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", 6669 pf->hw.pf_id, pf->hw.func_caps.num_vfs, 6670 pf->hw.func_caps.num_msix_vectors, 6671 pf->hw.func_caps.num_msix_vectors_vf, 6672 pf->hw.func_caps.fd_filters_guaranteed, 6673 pf->hw.func_caps.fd_filters_best_effort, 6674 pf->hw.func_caps.num_tx_qp, 6675 pf->hw.func_caps.num_vsis); 6676 6677 #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ 6678 + pf->hw.func_caps.num_vfs) 6679 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) { 6680 dev_info(&pf->pdev->dev, 6681 "got num_vsis %d, setting num_vsis to %d\n", 6682 pf->hw.func_caps.num_vsis, DEF_NUM_VSI); 6683 pf->hw.func_caps.num_vsis = DEF_NUM_VSI; 6684 } 6685 6686 return 0; 6687 } 6688 6689 static int i40e_vsi_clear(struct i40e_vsi *vsi); 6690 6691 /** 6692 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband 6693 * @pf: board private structure 6694 **/ 6695 static void i40e_fdir_sb_setup(struct i40e_pf *pf) 6696 { 6697 struct i40e_vsi *vsi; 6698 int i; 6699 6700 /* quick workaround for an NVM issue that leaves a critical register 6701 * uninitialized 6702 */ 6703 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { 6704 static const u32 hkey[] = { 6705 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, 6706 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, 6707 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, 6708 0x95b3a76d}; 6709 6710 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) 6711 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); 6712 } 6713 6714 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) 6715 return; 6716 6717 /* find existing VSI and see if it needs configuring */ 6718 vsi = NULL; 6719 for (i = 0; i < pf->num_alloc_vsi; i++) { 6720 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { 6721 vsi = pf->vsi[i]; 6722 break; 6723 } 6724 } 6725 6726 /* create a new VSI if none exists */ 6727 if (!vsi) { 6728 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, 6729 pf->vsi[pf->lan_vsi]->seid, 0); 6730 if (!vsi) { 6731 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); 6732 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; 6733 return; 6734 } 6735 } 6736 6737 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); 6738 } 6739 6740 /** 6741 * i40e_fdir_teardown - release the Flow Director resources 6742 * @pf: board private structure 6743 **/ 6744 static void i40e_fdir_teardown(struct i40e_pf *pf) 6745 { 6746 int i; 6747 6748 i40e_fdir_filter_exit(pf); 6749 for (i = 0; i < pf->num_alloc_vsi; i++) { 6750 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { 6751 i40e_vsi_release(pf->vsi[i]); 6752 break; 6753 } 6754 } 6755 } 6756 6757 /** 6758 * i40e_prep_for_reset - prep for the core to reset 6759 * @pf: board private structure 6760 * 6761 * Close up the VFs and other things in prep for PF Reset. 6762 **/ 6763 static void i40e_prep_for_reset(struct i40e_pf *pf) 6764 { 6765 struct i40e_hw *hw = &pf->hw; 6766 i40e_status ret = 0; 6767 u32 v; 6768 6769 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state); 6770 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) 6771 return; 6772 if (i40e_check_asq_alive(&pf->hw)) 6773 i40e_vc_notify_reset(pf); 6774 6775 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); 6776 6777 /* quiesce the VSIs and their queues that are not already DOWN */ 6778 i40e_pf_quiesce_all_vsi(pf); 6779 6780 for (v = 0; v < pf->num_alloc_vsi; v++) { 6781 if (pf->vsi[v]) 6782 pf->vsi[v]->seid = 0; 6783 } 6784 6785 i40e_shutdown_adminq(&pf->hw); 6786 6787 /* call shutdown HMC */ 6788 if (hw->hmc.hmc_obj) { 6789 ret = i40e_shutdown_lan_hmc(hw); 6790 if (ret) 6791 dev_warn(&pf->pdev->dev, 6792 "shutdown_lan_hmc failed: %d\n", ret); 6793 } 6794 } 6795 6796 /** 6797 * i40e_send_version - update firmware with driver version 6798 * @pf: PF struct 6799 */ 6800 static void i40e_send_version(struct i40e_pf *pf) 6801 { 6802 struct i40e_driver_version dv; 6803 6804 dv.major_version = DRV_VERSION_MAJOR; 6805 dv.minor_version = DRV_VERSION_MINOR; 6806 dv.build_version = DRV_VERSION_BUILD; 6807 dv.subbuild_version = 0; 6808 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); 6809 i40e_aq_send_driver_version(&pf->hw, &dv, NULL); 6810 } 6811 6812 /** 6813 * i40e_reset_and_rebuild - reset and rebuild using a saved config 6814 * @pf: board private structure 6815 * @reinit: if the Main VSI needs to re-initialized. 6816 **/ 6817 static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit) 6818 { 6819 struct i40e_hw *hw = &pf->hw; 6820 u8 set_fc_aq_fail = 0; 6821 i40e_status ret; 6822 u32 val; 6823 u32 v; 6824 6825 /* Now we wait for GRST to settle out. 6826 * We don't have to delete the VEBs or VSIs from the hw switch 6827 * because the reset will make them disappear. 6828 */ 6829 ret = i40e_pf_reset(hw); 6830 if (ret) { 6831 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); 6832 set_bit(__I40E_RESET_FAILED, &pf->state); 6833 goto clear_recovery; 6834 } 6835 pf->pfr_count++; 6836 6837 if (test_bit(__I40E_DOWN, &pf->state)) 6838 goto clear_recovery; 6839 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); 6840 6841 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ 6842 ret = i40e_init_adminq(&pf->hw); 6843 if (ret) { 6844 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", 6845 i40e_stat_str(&pf->hw, ret), 6846 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6847 goto clear_recovery; 6848 } 6849 6850 /* re-verify the eeprom if we just had an EMP reset */ 6851 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state)) 6852 i40e_verify_eeprom(pf); 6853 6854 i40e_clear_pxe_mode(hw); 6855 ret = i40e_get_capabilities(pf); 6856 if (ret) 6857 goto end_core_reset; 6858 6859 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 6860 hw->func_caps.num_rx_qp, 6861 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); 6862 if (ret) { 6863 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); 6864 goto end_core_reset; 6865 } 6866 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 6867 if (ret) { 6868 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); 6869 goto end_core_reset; 6870 } 6871 6872 #ifdef CONFIG_I40E_DCB 6873 ret = i40e_init_pf_dcb(pf); 6874 if (ret) { 6875 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); 6876 pf->flags &= ~I40E_FLAG_DCB_CAPABLE; 6877 /* Continue without DCB enabled */ 6878 } 6879 #endif /* CONFIG_I40E_DCB */ 6880 #ifdef I40E_FCOE 6881 i40e_init_pf_fcoe(pf); 6882 6883 #endif 6884 /* do basic switch setup */ 6885 ret = i40e_setup_pf_switch(pf, reinit); 6886 if (ret) 6887 goto end_core_reset; 6888 6889 /* The driver only wants link up/down and module qualification 6890 * reports from firmware. Note the negative logic. 6891 */ 6892 ret = i40e_aq_set_phy_int_mask(&pf->hw, 6893 ~(I40E_AQ_EVENT_LINK_UPDOWN | 6894 I40E_AQ_EVENT_MEDIA_NA | 6895 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); 6896 if (ret) 6897 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", 6898 i40e_stat_str(&pf->hw, ret), 6899 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6900 6901 /* make sure our flow control settings are restored */ 6902 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); 6903 if (ret) 6904 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", 6905 i40e_stat_str(&pf->hw, ret), 6906 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 6907 6908 /* Rebuild the VSIs and VEBs that existed before reset. 6909 * They are still in our local switch element arrays, so only 6910 * need to rebuild the switch model in the HW. 6911 * 6912 * If there were VEBs but the reconstitution failed, we'll try 6913 * try to recover minimal use by getting the basic PF VSI working. 6914 */ 6915 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) { 6916 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); 6917 /* find the one VEB connected to the MAC, and find orphans */ 6918 for (v = 0; v < I40E_MAX_VEB; v++) { 6919 if (!pf->veb[v]) 6920 continue; 6921 6922 if (pf->veb[v]->uplink_seid == pf->mac_seid || 6923 pf->veb[v]->uplink_seid == 0) { 6924 ret = i40e_reconstitute_veb(pf->veb[v]); 6925 6926 if (!ret) 6927 continue; 6928 6929 /* If Main VEB failed, we're in deep doodoo, 6930 * so give up rebuilding the switch and set up 6931 * for minimal rebuild of PF VSI. 6932 * If orphan failed, we'll report the error 6933 * but try to keep going. 6934 */ 6935 if (pf->veb[v]->uplink_seid == pf->mac_seid) { 6936 dev_info(&pf->pdev->dev, 6937 "rebuild of switch failed: %d, will try to set up simple PF connection\n", 6938 ret); 6939 pf->vsi[pf->lan_vsi]->uplink_seid 6940 = pf->mac_seid; 6941 break; 6942 } else if (pf->veb[v]->uplink_seid == 0) { 6943 dev_info(&pf->pdev->dev, 6944 "rebuild of orphan VEB failed: %d\n", 6945 ret); 6946 } 6947 } 6948 } 6949 } 6950 6951 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) { 6952 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); 6953 /* no VEB, so rebuild only the Main VSI */ 6954 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]); 6955 if (ret) { 6956 dev_info(&pf->pdev->dev, 6957 "rebuild of Main VSI failed: %d\n", ret); 6958 goto end_core_reset; 6959 } 6960 } 6961 6962 /* Reconfigure hardware for allowing smaller MSS in the case 6963 * of TSO, so that we avoid the MDD being fired and causing 6964 * a reset in the case of small MSS+TSO. 6965 */ 6966 #define I40E_REG_MSS 0x000E64DC 6967 #define I40E_REG_MSS_MIN_MASK 0x3FF0000 6968 #define I40E_64BYTE_MSS 0x400000 6969 val = rd32(hw, I40E_REG_MSS); 6970 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { 6971 val &= ~I40E_REG_MSS_MIN_MASK; 6972 val |= I40E_64BYTE_MSS; 6973 wr32(hw, I40E_REG_MSS, val); 6974 } 6975 6976 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { 6977 msleep(75); 6978 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); 6979 if (ret) 6980 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", 6981 i40e_stat_str(&pf->hw, ret), 6982 i40e_aq_str(&pf->hw, 6983 pf->hw.aq.asq_last_status)); 6984 } 6985 /* reinit the misc interrupt */ 6986 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 6987 ret = i40e_setup_misc_vector(pf); 6988 6989 /* Add a filter to drop all Flow control frames from any VSI from being 6990 * transmitted. By doing so we stop a malicious VF from sending out 6991 * PAUSE or PFC frames and potentially controlling traffic for other 6992 * PF/VF VSIs. 6993 * The FW can still send Flow control frames if enabled. 6994 */ 6995 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, 6996 pf->main_vsi_seid); 6997 6998 /* restart the VSIs that were rebuilt and running before the reset */ 6999 i40e_pf_unquiesce_all_vsi(pf); 7000 7001 if (pf->num_alloc_vfs) { 7002 for (v = 0; v < pf->num_alloc_vfs; v++) 7003 i40e_reset_vf(&pf->vf[v], true); 7004 } 7005 7006 /* tell the firmware that we're starting */ 7007 i40e_send_version(pf); 7008 7009 end_core_reset: 7010 clear_bit(__I40E_RESET_FAILED, &pf->state); 7011 clear_recovery: 7012 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state); 7013 } 7014 7015 /** 7016 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild 7017 * @pf: board private structure 7018 * 7019 * Close up the VFs and other things in prep for a Core Reset, 7020 * then get ready to rebuild the world. 7021 **/ 7022 static void i40e_handle_reset_warning(struct i40e_pf *pf) 7023 { 7024 i40e_prep_for_reset(pf); 7025 i40e_reset_and_rebuild(pf, false); 7026 } 7027 7028 /** 7029 * i40e_handle_mdd_event 7030 * @pf: pointer to the PF structure 7031 * 7032 * Called from the MDD irq handler to identify possibly malicious vfs 7033 **/ 7034 static void i40e_handle_mdd_event(struct i40e_pf *pf) 7035 { 7036 struct i40e_hw *hw = &pf->hw; 7037 bool mdd_detected = false; 7038 bool pf_mdd_detected = false; 7039 struct i40e_vf *vf; 7040 u32 reg; 7041 int i; 7042 7043 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state)) 7044 return; 7045 7046 /* find what triggered the MDD event */ 7047 reg = rd32(hw, I40E_GL_MDET_TX); 7048 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 7049 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 7050 I40E_GL_MDET_TX_PF_NUM_SHIFT; 7051 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> 7052 I40E_GL_MDET_TX_VF_NUM_SHIFT; 7053 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 7054 I40E_GL_MDET_TX_EVENT_SHIFT; 7055 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 7056 I40E_GL_MDET_TX_QUEUE_SHIFT) - 7057 pf->hw.func_caps.base_queue; 7058 if (netif_msg_tx_err(pf)) 7059 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", 7060 event, queue, pf_num, vf_num); 7061 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 7062 mdd_detected = true; 7063 } 7064 reg = rd32(hw, I40E_GL_MDET_RX); 7065 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 7066 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 7067 I40E_GL_MDET_RX_FUNCTION_SHIFT; 7068 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 7069 I40E_GL_MDET_RX_EVENT_SHIFT; 7070 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 7071 I40E_GL_MDET_RX_QUEUE_SHIFT) - 7072 pf->hw.func_caps.base_queue; 7073 if (netif_msg_rx_err(pf)) 7074 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", 7075 event, queue, func); 7076 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 7077 mdd_detected = true; 7078 } 7079 7080 if (mdd_detected) { 7081 reg = rd32(hw, I40E_PF_MDET_TX); 7082 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 7083 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 7084 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n"); 7085 pf_mdd_detected = true; 7086 } 7087 reg = rd32(hw, I40E_PF_MDET_RX); 7088 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 7089 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 7090 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n"); 7091 pf_mdd_detected = true; 7092 } 7093 /* Queue belongs to the PF, initiate a reset */ 7094 if (pf_mdd_detected) { 7095 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state); 7096 i40e_service_event_schedule(pf); 7097 } 7098 } 7099 7100 /* see if one of the VFs needs its hand slapped */ 7101 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { 7102 vf = &(pf->vf[i]); 7103 reg = rd32(hw, I40E_VP_MDET_TX(i)); 7104 if (reg & I40E_VP_MDET_TX_VALID_MASK) { 7105 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); 7106 vf->num_mdd_events++; 7107 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", 7108 i); 7109 } 7110 7111 reg = rd32(hw, I40E_VP_MDET_RX(i)); 7112 if (reg & I40E_VP_MDET_RX_VALID_MASK) { 7113 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); 7114 vf->num_mdd_events++; 7115 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", 7116 i); 7117 } 7118 7119 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) { 7120 dev_info(&pf->pdev->dev, 7121 "Too many MDD events on VF %d, disabled\n", i); 7122 dev_info(&pf->pdev->dev, 7123 "Use PF Control I/F to re-enable the VF\n"); 7124 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states); 7125 } 7126 } 7127 7128 /* re-enable mdd interrupt cause */ 7129 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state); 7130 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 7131 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 7132 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 7133 i40e_flush(hw); 7134 } 7135 7136 /** 7137 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW 7138 * @pf: board private structure 7139 **/ 7140 static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) 7141 { 7142 struct i40e_hw *hw = &pf->hw; 7143 i40e_status ret; 7144 __be16 port; 7145 int i; 7146 7147 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC)) 7148 return; 7149 7150 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC; 7151 7152 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 7153 if (pf->pending_udp_bitmap & BIT_ULL(i)) { 7154 pf->pending_udp_bitmap &= ~BIT_ULL(i); 7155 port = pf->udp_ports[i].index; 7156 if (port) 7157 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port), 7158 pf->udp_ports[i].type, 7159 NULL, NULL); 7160 else 7161 ret = i40e_aq_del_udp_tunnel(hw, i, NULL); 7162 7163 if (ret) { 7164 dev_dbg(&pf->pdev->dev, 7165 "%s %s port %d, index %d failed, err %s aq_err %s\n", 7166 pf->udp_ports[i].type ? "vxlan" : "geneve", 7167 port ? "add" : "delete", 7168 ntohs(port), i, 7169 i40e_stat_str(&pf->hw, ret), 7170 i40e_aq_str(&pf->hw, 7171 pf->hw.aq.asq_last_status)); 7172 pf->udp_ports[i].index = 0; 7173 } 7174 } 7175 } 7176 } 7177 7178 /** 7179 * i40e_service_task - Run the driver's async subtasks 7180 * @work: pointer to work_struct containing our data 7181 **/ 7182 static void i40e_service_task(struct work_struct *work) 7183 { 7184 struct i40e_pf *pf = container_of(work, 7185 struct i40e_pf, 7186 service_task); 7187 unsigned long start_time = jiffies; 7188 7189 /* don't bother with service tasks if a reset is in progress */ 7190 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { 7191 i40e_service_event_complete(pf); 7192 return; 7193 } 7194 7195 i40e_detect_recover_hung(pf); 7196 i40e_sync_filters_subtask(pf); 7197 i40e_reset_subtask(pf); 7198 i40e_handle_mdd_event(pf); 7199 i40e_vc_process_vflr_event(pf); 7200 i40e_watchdog_subtask(pf); 7201 i40e_fdir_reinit_subtask(pf); 7202 i40e_client_subtask(pf); 7203 i40e_sync_filters_subtask(pf); 7204 i40e_sync_udp_filters_subtask(pf); 7205 i40e_clean_adminq_subtask(pf); 7206 7207 i40e_service_event_complete(pf); 7208 7209 /* If the tasks have taken longer than one timer cycle or there 7210 * is more work to be done, reschedule the service task now 7211 * rather than wait for the timer to tick again. 7212 */ 7213 if (time_after(jiffies, (start_time + pf->service_timer_period)) || 7214 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) || 7215 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) || 7216 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state)) 7217 i40e_service_event_schedule(pf); 7218 } 7219 7220 /** 7221 * i40e_service_timer - timer callback 7222 * @data: pointer to PF struct 7223 **/ 7224 static void i40e_service_timer(unsigned long data) 7225 { 7226 struct i40e_pf *pf = (struct i40e_pf *)data; 7227 7228 mod_timer(&pf->service_timer, 7229 round_jiffies(jiffies + pf->service_timer_period)); 7230 i40e_service_event_schedule(pf); 7231 } 7232 7233 /** 7234 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI 7235 * @vsi: the VSI being configured 7236 **/ 7237 static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) 7238 { 7239 struct i40e_pf *pf = vsi->back; 7240 7241 switch (vsi->type) { 7242 case I40E_VSI_MAIN: 7243 vsi->alloc_queue_pairs = pf->num_lan_qps; 7244 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, 7245 I40E_REQ_DESCRIPTOR_MULTIPLE); 7246 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 7247 vsi->num_q_vectors = pf->num_lan_msix; 7248 else 7249 vsi->num_q_vectors = 1; 7250 7251 break; 7252 7253 case I40E_VSI_FDIR: 7254 vsi->alloc_queue_pairs = 1; 7255 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, 7256 I40E_REQ_DESCRIPTOR_MULTIPLE); 7257 vsi->num_q_vectors = pf->num_fdsb_msix; 7258 break; 7259 7260 case I40E_VSI_VMDQ2: 7261 vsi->alloc_queue_pairs = pf->num_vmdq_qps; 7262 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, 7263 I40E_REQ_DESCRIPTOR_MULTIPLE); 7264 vsi->num_q_vectors = pf->num_vmdq_msix; 7265 break; 7266 7267 case I40E_VSI_SRIOV: 7268 vsi->alloc_queue_pairs = pf->num_vf_qps; 7269 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, 7270 I40E_REQ_DESCRIPTOR_MULTIPLE); 7271 break; 7272 7273 #ifdef I40E_FCOE 7274 case I40E_VSI_FCOE: 7275 vsi->alloc_queue_pairs = pf->num_fcoe_qps; 7276 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, 7277 I40E_REQ_DESCRIPTOR_MULTIPLE); 7278 vsi->num_q_vectors = pf->num_fcoe_msix; 7279 break; 7280 7281 #endif /* I40E_FCOE */ 7282 default: 7283 WARN_ON(1); 7284 return -ENODATA; 7285 } 7286 7287 return 0; 7288 } 7289 7290 /** 7291 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi 7292 * @type: VSI pointer 7293 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. 7294 * 7295 * On error: returns error code (negative) 7296 * On success: returns 0 7297 **/ 7298 static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) 7299 { 7300 int size; 7301 int ret = 0; 7302 7303 /* allocate memory for both Tx and Rx ring pointers */ 7304 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2; 7305 vsi->tx_rings = kzalloc(size, GFP_KERNEL); 7306 if (!vsi->tx_rings) 7307 return -ENOMEM; 7308 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs]; 7309 7310 if (alloc_qvectors) { 7311 /* allocate memory for q_vector pointers */ 7312 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; 7313 vsi->q_vectors = kzalloc(size, GFP_KERNEL); 7314 if (!vsi->q_vectors) { 7315 ret = -ENOMEM; 7316 goto err_vectors; 7317 } 7318 } 7319 return ret; 7320 7321 err_vectors: 7322 kfree(vsi->tx_rings); 7323 return ret; 7324 } 7325 7326 /** 7327 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF 7328 * @pf: board private structure 7329 * @type: type of VSI 7330 * 7331 * On error: returns error code (negative) 7332 * On success: returns vsi index in PF (positive) 7333 **/ 7334 static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) 7335 { 7336 int ret = -ENODEV; 7337 struct i40e_vsi *vsi; 7338 int vsi_idx; 7339 int i; 7340 7341 /* Need to protect the allocation of the VSIs at the PF level */ 7342 mutex_lock(&pf->switch_mutex); 7343 7344 /* VSI list may be fragmented if VSI creation/destruction has 7345 * been happening. We can afford to do a quick scan to look 7346 * for any free VSIs in the list. 7347 * 7348 * find next empty vsi slot, looping back around if necessary 7349 */ 7350 i = pf->next_vsi; 7351 while (i < pf->num_alloc_vsi && pf->vsi[i]) 7352 i++; 7353 if (i >= pf->num_alloc_vsi) { 7354 i = 0; 7355 while (i < pf->next_vsi && pf->vsi[i]) 7356 i++; 7357 } 7358 7359 if (i < pf->num_alloc_vsi && !pf->vsi[i]) { 7360 vsi_idx = i; /* Found one! */ 7361 } else { 7362 ret = -ENODEV; 7363 goto unlock_pf; /* out of VSI slots! */ 7364 } 7365 pf->next_vsi = ++i; 7366 7367 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); 7368 if (!vsi) { 7369 ret = -ENOMEM; 7370 goto unlock_pf; 7371 } 7372 vsi->type = type; 7373 vsi->back = pf; 7374 set_bit(__I40E_DOWN, &vsi->state); 7375 vsi->flags = 0; 7376 vsi->idx = vsi_idx; 7377 vsi->int_rate_limit = 0; 7378 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? 7379 pf->rss_table_size : 64; 7380 vsi->netdev_registered = false; 7381 vsi->work_limit = I40E_DEFAULT_IRQ_WORK; 7382 INIT_LIST_HEAD(&vsi->mac_filter_list); 7383 vsi->irqs_ready = false; 7384 7385 ret = i40e_set_num_rings_in_vsi(vsi); 7386 if (ret) 7387 goto err_rings; 7388 7389 ret = i40e_vsi_alloc_arrays(vsi, true); 7390 if (ret) 7391 goto err_rings; 7392 7393 /* Setup default MSIX irq handler for VSI */ 7394 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); 7395 7396 /* Initialize VSI lock */ 7397 spin_lock_init(&vsi->mac_filter_list_lock); 7398 pf->vsi[vsi_idx] = vsi; 7399 ret = vsi_idx; 7400 goto unlock_pf; 7401 7402 err_rings: 7403 pf->next_vsi = i - 1; 7404 kfree(vsi); 7405 unlock_pf: 7406 mutex_unlock(&pf->switch_mutex); 7407 return ret; 7408 } 7409 7410 /** 7411 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI 7412 * @type: VSI pointer 7413 * @free_qvectors: a bool to specify if q_vectors need to be freed. 7414 * 7415 * On error: returns error code (negative) 7416 * On success: returns 0 7417 **/ 7418 static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) 7419 { 7420 /* free the ring and vector containers */ 7421 if (free_qvectors) { 7422 kfree(vsi->q_vectors); 7423 vsi->q_vectors = NULL; 7424 } 7425 kfree(vsi->tx_rings); 7426 vsi->tx_rings = NULL; 7427 vsi->rx_rings = NULL; 7428 } 7429 7430 /** 7431 * i40e_clear_rss_config_user - clear the user configured RSS hash keys 7432 * and lookup table 7433 * @vsi: Pointer to VSI structure 7434 */ 7435 static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) 7436 { 7437 if (!vsi) 7438 return; 7439 7440 kfree(vsi->rss_hkey_user); 7441 vsi->rss_hkey_user = NULL; 7442 7443 kfree(vsi->rss_lut_user); 7444 vsi->rss_lut_user = NULL; 7445 } 7446 7447 /** 7448 * i40e_vsi_clear - Deallocate the VSI provided 7449 * @vsi: the VSI being un-configured 7450 **/ 7451 static int i40e_vsi_clear(struct i40e_vsi *vsi) 7452 { 7453 struct i40e_pf *pf; 7454 7455 if (!vsi) 7456 return 0; 7457 7458 if (!vsi->back) 7459 goto free_vsi; 7460 pf = vsi->back; 7461 7462 mutex_lock(&pf->switch_mutex); 7463 if (!pf->vsi[vsi->idx]) { 7464 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n", 7465 vsi->idx, vsi->idx, vsi, vsi->type); 7466 goto unlock_vsi; 7467 } 7468 7469 if (pf->vsi[vsi->idx] != vsi) { 7470 dev_err(&pf->pdev->dev, 7471 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n", 7472 pf->vsi[vsi->idx]->idx, 7473 pf->vsi[vsi->idx], 7474 pf->vsi[vsi->idx]->type, 7475 vsi->idx, vsi, vsi->type); 7476 goto unlock_vsi; 7477 } 7478 7479 /* updates the PF for this cleared vsi */ 7480 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); 7481 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); 7482 7483 i40e_vsi_free_arrays(vsi, true); 7484 i40e_clear_rss_config_user(vsi); 7485 7486 pf->vsi[vsi->idx] = NULL; 7487 if (vsi->idx < pf->next_vsi) 7488 pf->next_vsi = vsi->idx; 7489 7490 unlock_vsi: 7491 mutex_unlock(&pf->switch_mutex); 7492 free_vsi: 7493 kfree(vsi); 7494 7495 return 0; 7496 } 7497 7498 /** 7499 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI 7500 * @vsi: the VSI being cleaned 7501 **/ 7502 static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) 7503 { 7504 int i; 7505 7506 if (vsi->tx_rings && vsi->tx_rings[0]) { 7507 for (i = 0; i < vsi->alloc_queue_pairs; i++) { 7508 kfree_rcu(vsi->tx_rings[i], rcu); 7509 vsi->tx_rings[i] = NULL; 7510 vsi->rx_rings[i] = NULL; 7511 } 7512 } 7513 } 7514 7515 /** 7516 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI 7517 * @vsi: the VSI being configured 7518 **/ 7519 static int i40e_alloc_rings(struct i40e_vsi *vsi) 7520 { 7521 struct i40e_ring *tx_ring, *rx_ring; 7522 struct i40e_pf *pf = vsi->back; 7523 int i; 7524 7525 /* Set basic values in the rings to be used later during open() */ 7526 for (i = 0; i < vsi->alloc_queue_pairs; i++) { 7527 /* allocate space for both Tx and Rx in one shot */ 7528 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL); 7529 if (!tx_ring) 7530 goto err_out; 7531 7532 tx_ring->queue_index = i; 7533 tx_ring->reg_idx = vsi->base_queue + i; 7534 tx_ring->ring_active = false; 7535 tx_ring->vsi = vsi; 7536 tx_ring->netdev = vsi->netdev; 7537 tx_ring->dev = &pf->pdev->dev; 7538 tx_ring->count = vsi->num_desc; 7539 tx_ring->size = 0; 7540 tx_ring->dcb_tc = 0; 7541 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE) 7542 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; 7543 tx_ring->tx_itr_setting = pf->tx_itr_default; 7544 vsi->tx_rings[i] = tx_ring; 7545 7546 rx_ring = &tx_ring[1]; 7547 rx_ring->queue_index = i; 7548 rx_ring->reg_idx = vsi->base_queue + i; 7549 rx_ring->ring_active = false; 7550 rx_ring->vsi = vsi; 7551 rx_ring->netdev = vsi->netdev; 7552 rx_ring->dev = &pf->pdev->dev; 7553 rx_ring->count = vsi->num_desc; 7554 rx_ring->size = 0; 7555 rx_ring->dcb_tc = 0; 7556 rx_ring->rx_itr_setting = pf->rx_itr_default; 7557 vsi->rx_rings[i] = rx_ring; 7558 } 7559 7560 return 0; 7561 7562 err_out: 7563 i40e_vsi_clear_rings(vsi); 7564 return -ENOMEM; 7565 } 7566 7567 /** 7568 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel 7569 * @pf: board private structure 7570 * @vectors: the number of MSI-X vectors to request 7571 * 7572 * Returns the number of vectors reserved, or error 7573 **/ 7574 static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) 7575 { 7576 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, 7577 I40E_MIN_MSIX, vectors); 7578 if (vectors < 0) { 7579 dev_info(&pf->pdev->dev, 7580 "MSI-X vector reservation failed: %d\n", vectors); 7581 vectors = 0; 7582 } 7583 7584 return vectors; 7585 } 7586 7587 /** 7588 * i40e_init_msix - Setup the MSIX capability 7589 * @pf: board private structure 7590 * 7591 * Work with the OS to set up the MSIX vectors needed. 7592 * 7593 * Returns the number of vectors reserved or negative on failure 7594 **/ 7595 static int i40e_init_msix(struct i40e_pf *pf) 7596 { 7597 struct i40e_hw *hw = &pf->hw; 7598 int vectors_left; 7599 int v_budget, i; 7600 int v_actual; 7601 int iwarp_requested = 0; 7602 7603 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) 7604 return -ENODEV; 7605 7606 /* The number of vectors we'll request will be comprised of: 7607 * - Add 1 for "other" cause for Admin Queue events, etc. 7608 * - The number of LAN queue pairs 7609 * - Queues being used for RSS. 7610 * We don't need as many as max_rss_size vectors. 7611 * use rss_size instead in the calculation since that 7612 * is governed by number of cpus in the system. 7613 * - assumes symmetric Tx/Rx pairing 7614 * - The number of VMDq pairs 7615 * - The CPU count within the NUMA node if iWARP is enabled 7616 #ifdef I40E_FCOE 7617 * - The number of FCOE qps. 7618 #endif 7619 * Once we count this up, try the request. 7620 * 7621 * If we can't get what we want, we'll simplify to nearly nothing 7622 * and try again. If that still fails, we punt. 7623 */ 7624 vectors_left = hw->func_caps.num_msix_vectors; 7625 v_budget = 0; 7626 7627 /* reserve one vector for miscellaneous handler */ 7628 if (vectors_left) { 7629 v_budget++; 7630 vectors_left--; 7631 } 7632 7633 /* reserve vectors for the main PF traffic queues */ 7634 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left); 7635 vectors_left -= pf->num_lan_msix; 7636 v_budget += pf->num_lan_msix; 7637 7638 /* reserve one vector for sideband flow director */ 7639 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { 7640 if (vectors_left) { 7641 pf->num_fdsb_msix = 1; 7642 v_budget++; 7643 vectors_left--; 7644 } else { 7645 pf->num_fdsb_msix = 0; 7646 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; 7647 } 7648 } 7649 7650 #ifdef I40E_FCOE 7651 /* can we reserve enough for FCoE? */ 7652 if (pf->flags & I40E_FLAG_FCOE_ENABLED) { 7653 if (!vectors_left) 7654 pf->num_fcoe_msix = 0; 7655 else if (vectors_left >= pf->num_fcoe_qps) 7656 pf->num_fcoe_msix = pf->num_fcoe_qps; 7657 else 7658 pf->num_fcoe_msix = 1; 7659 v_budget += pf->num_fcoe_msix; 7660 vectors_left -= pf->num_fcoe_msix; 7661 } 7662 7663 #endif 7664 /* can we reserve enough for iWARP? */ 7665 if (pf->flags & I40E_FLAG_IWARP_ENABLED) { 7666 if (!vectors_left) 7667 pf->num_iwarp_msix = 0; 7668 else if (vectors_left < pf->num_iwarp_msix) 7669 pf->num_iwarp_msix = 1; 7670 v_budget += pf->num_iwarp_msix; 7671 vectors_left -= pf->num_iwarp_msix; 7672 } 7673 7674 /* any vectors left over go for VMDq support */ 7675 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { 7676 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps; 7677 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted); 7678 7679 /* if we're short on vectors for what's desired, we limit 7680 * the queues per vmdq. If this is still more than are 7681 * available, the user will need to change the number of 7682 * queues/vectors used by the PF later with the ethtool 7683 * channels command 7684 */ 7685 if (vmdq_vecs < vmdq_vecs_wanted) 7686 pf->num_vmdq_qps = 1; 7687 pf->num_vmdq_msix = pf->num_vmdq_qps; 7688 7689 v_budget += vmdq_vecs; 7690 vectors_left -= vmdq_vecs; 7691 } 7692 7693 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), 7694 GFP_KERNEL); 7695 if (!pf->msix_entries) 7696 return -ENOMEM; 7697 7698 for (i = 0; i < v_budget; i++) 7699 pf->msix_entries[i].entry = i; 7700 v_actual = i40e_reserve_msix_vectors(pf, v_budget); 7701 7702 if (v_actual != v_budget) { 7703 /* If we have limited resources, we will start with no vectors 7704 * for the special features and then allocate vectors to some 7705 * of these features based on the policy and at the end disable 7706 * the features that did not get any vectors. 7707 */ 7708 iwarp_requested = pf->num_iwarp_msix; 7709 pf->num_iwarp_msix = 0; 7710 #ifdef I40E_FCOE 7711 pf->num_fcoe_qps = 0; 7712 pf->num_fcoe_msix = 0; 7713 #endif 7714 pf->num_vmdq_msix = 0; 7715 } 7716 7717 if (v_actual < I40E_MIN_MSIX) { 7718 pf->flags &= ~I40E_FLAG_MSIX_ENABLED; 7719 kfree(pf->msix_entries); 7720 pf->msix_entries = NULL; 7721 return -ENODEV; 7722 7723 } else if (v_actual == I40E_MIN_MSIX) { 7724 /* Adjust for minimal MSIX use */ 7725 pf->num_vmdq_vsis = 0; 7726 pf->num_vmdq_qps = 0; 7727 pf->num_lan_qps = 1; 7728 pf->num_lan_msix = 1; 7729 7730 } else if (v_actual != v_budget) { 7731 int vec; 7732 7733 /* reserve the misc vector */ 7734 vec = v_actual - 1; 7735 7736 /* Scale vector usage down */ 7737 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ 7738 pf->num_vmdq_vsis = 1; 7739 pf->num_vmdq_qps = 1; 7740 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; 7741 7742 /* partition out the remaining vectors */ 7743 switch (vec) { 7744 case 2: 7745 pf->num_lan_msix = 1; 7746 break; 7747 case 3: 7748 if (pf->flags & I40E_FLAG_IWARP_ENABLED) { 7749 pf->num_lan_msix = 1; 7750 pf->num_iwarp_msix = 1; 7751 } else { 7752 pf->num_lan_msix = 2; 7753 } 7754 #ifdef I40E_FCOE 7755 /* give one vector to FCoE */ 7756 if (pf->flags & I40E_FLAG_FCOE_ENABLED) { 7757 pf->num_lan_msix = 1; 7758 pf->num_fcoe_msix = 1; 7759 } 7760 #endif 7761 break; 7762 default: 7763 if (pf->flags & I40E_FLAG_IWARP_ENABLED) { 7764 pf->num_iwarp_msix = min_t(int, (vec / 3), 7765 iwarp_requested); 7766 pf->num_vmdq_vsis = min_t(int, (vec / 3), 7767 I40E_DEFAULT_NUM_VMDQ_VSI); 7768 } else { 7769 pf->num_vmdq_vsis = min_t(int, (vec / 2), 7770 I40E_DEFAULT_NUM_VMDQ_VSI); 7771 } 7772 pf->num_lan_msix = min_t(int, 7773 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), 7774 pf->num_lan_msix); 7775 #ifdef I40E_FCOE 7776 /* give one vector to FCoE */ 7777 if (pf->flags & I40E_FLAG_FCOE_ENABLED) { 7778 pf->num_fcoe_msix = 1; 7779 vec--; 7780 } 7781 #endif 7782 break; 7783 } 7784 } 7785 7786 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && 7787 (pf->num_vmdq_msix == 0)) { 7788 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); 7789 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; 7790 } 7791 7792 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && 7793 (pf->num_iwarp_msix == 0)) { 7794 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); 7795 pf->flags &= ~I40E_FLAG_IWARP_ENABLED; 7796 } 7797 #ifdef I40E_FCOE 7798 7799 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) { 7800 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n"); 7801 pf->flags &= ~I40E_FLAG_FCOE_ENABLED; 7802 } 7803 #endif 7804 return v_actual; 7805 } 7806 7807 /** 7808 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 7809 * @vsi: the VSI being configured 7810 * @v_idx: index of the vector in the vsi struct 7811 * @cpu: cpu to be used on affinity_mask 7812 * 7813 * We allocate one q_vector. If allocation fails we return -ENOMEM. 7814 **/ 7815 static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu) 7816 { 7817 struct i40e_q_vector *q_vector; 7818 7819 /* allocate q_vector */ 7820 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); 7821 if (!q_vector) 7822 return -ENOMEM; 7823 7824 q_vector->vsi = vsi; 7825 q_vector->v_idx = v_idx; 7826 cpumask_set_cpu(cpu, &q_vector->affinity_mask); 7827 7828 if (vsi->netdev) 7829 netif_napi_add(vsi->netdev, &q_vector->napi, 7830 i40e_napi_poll, NAPI_POLL_WEIGHT); 7831 7832 q_vector->rx.latency_range = I40E_LOW_LATENCY; 7833 q_vector->tx.latency_range = I40E_LOW_LATENCY; 7834 7835 /* tie q_vector and vsi together */ 7836 vsi->q_vectors[v_idx] = q_vector; 7837 7838 return 0; 7839 } 7840 7841 /** 7842 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 7843 * @vsi: the VSI being configured 7844 * 7845 * We allocate one q_vector per queue interrupt. If allocation fails we 7846 * return -ENOMEM. 7847 **/ 7848 static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) 7849 { 7850 struct i40e_pf *pf = vsi->back; 7851 int err, v_idx, num_q_vectors, current_cpu; 7852 7853 /* if not MSIX, give the one vector only to the LAN VSI */ 7854 if (pf->flags & I40E_FLAG_MSIX_ENABLED) 7855 num_q_vectors = vsi->num_q_vectors; 7856 else if (vsi == pf->vsi[pf->lan_vsi]) 7857 num_q_vectors = 1; 7858 else 7859 return -EINVAL; 7860 7861 current_cpu = cpumask_first(cpu_online_mask); 7862 7863 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { 7864 err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu); 7865 if (err) 7866 goto err_out; 7867 current_cpu = cpumask_next(current_cpu, cpu_online_mask); 7868 if (unlikely(current_cpu >= nr_cpu_ids)) 7869 current_cpu = cpumask_first(cpu_online_mask); 7870 } 7871 7872 return 0; 7873 7874 err_out: 7875 while (v_idx--) 7876 i40e_free_q_vector(vsi, v_idx); 7877 7878 return err; 7879 } 7880 7881 /** 7882 * i40e_init_interrupt_scheme - Determine proper interrupt scheme 7883 * @pf: board private structure to initialize 7884 **/ 7885 static int i40e_init_interrupt_scheme(struct i40e_pf *pf) 7886 { 7887 int vectors = 0; 7888 ssize_t size; 7889 7890 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 7891 vectors = i40e_init_msix(pf); 7892 if (vectors < 0) { 7893 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | 7894 I40E_FLAG_IWARP_ENABLED | 7895 #ifdef I40E_FCOE 7896 I40E_FLAG_FCOE_ENABLED | 7897 #endif 7898 I40E_FLAG_RSS_ENABLED | 7899 I40E_FLAG_DCB_CAPABLE | 7900 I40E_FLAG_SRIOV_ENABLED | 7901 I40E_FLAG_FD_SB_ENABLED | 7902 I40E_FLAG_FD_ATR_ENABLED | 7903 I40E_FLAG_VMDQ_ENABLED); 7904 7905 /* rework the queue expectations without MSIX */ 7906 i40e_determine_queue_usage(pf); 7907 } 7908 } 7909 7910 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && 7911 (pf->flags & I40E_FLAG_MSI_ENABLED)) { 7912 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); 7913 vectors = pci_enable_msi(pf->pdev); 7914 if (vectors < 0) { 7915 dev_info(&pf->pdev->dev, "MSI init failed - %d\n", 7916 vectors); 7917 pf->flags &= ~I40E_FLAG_MSI_ENABLED; 7918 } 7919 vectors = 1; /* one MSI or Legacy vector */ 7920 } 7921 7922 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) 7923 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); 7924 7925 /* set up vector assignment tracking */ 7926 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); 7927 pf->irq_pile = kzalloc(size, GFP_KERNEL); 7928 if (!pf->irq_pile) { 7929 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n"); 7930 return -ENOMEM; 7931 } 7932 pf->irq_pile->num_entries = vectors; 7933 pf->irq_pile->search_hint = 0; 7934 7935 /* track first vector for misc interrupts, ignore return */ 7936 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); 7937 7938 return 0; 7939 } 7940 7941 /** 7942 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events 7943 * @pf: board private structure 7944 * 7945 * This sets up the handler for MSIX 0, which is used to manage the 7946 * non-queue interrupts, e.g. AdminQ and errors. This is not used 7947 * when in MSI or Legacy interrupt mode. 7948 **/ 7949 static int i40e_setup_misc_vector(struct i40e_pf *pf) 7950 { 7951 struct i40e_hw *hw = &pf->hw; 7952 int err = 0; 7953 7954 /* Only request the irq if this is the first time through, and 7955 * not when we're rebuilding after a Reset 7956 */ 7957 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) { 7958 err = request_irq(pf->msix_entries[0].vector, 7959 i40e_intr, 0, pf->int_name, pf); 7960 if (err) { 7961 dev_info(&pf->pdev->dev, 7962 "request_irq for %s failed: %d\n", 7963 pf->int_name, err); 7964 return -EFAULT; 7965 } 7966 } 7967 7968 i40e_enable_misc_int_causes(pf); 7969 7970 /* associate no queues to the misc vector */ 7971 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); 7972 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); 7973 7974 i40e_flush(hw); 7975 7976 i40e_irq_dynamic_enable_icr0(pf, true); 7977 7978 return err; 7979 } 7980 7981 /** 7982 * i40e_config_rss_aq - Prepare for RSS using AQ commands 7983 * @vsi: vsi structure 7984 * @seed: RSS hash seed 7985 **/ 7986 static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, 7987 u8 *lut, u16 lut_size) 7988 { 7989 struct i40e_aqc_get_set_rss_key_data rss_key; 7990 struct i40e_pf *pf = vsi->back; 7991 struct i40e_hw *hw = &pf->hw; 7992 bool pf_lut = false; 7993 u8 *rss_lut; 7994 int ret, i; 7995 7996 memcpy(&rss_key, seed, sizeof(rss_key)); 7997 7998 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL); 7999 if (!rss_lut) 8000 return -ENOMEM; 8001 8002 /* Populate the LUT with max no. of queues in round robin fashion */ 8003 for (i = 0; i < vsi->rss_table_size; i++) 8004 rss_lut[i] = i % vsi->rss_size; 8005 8006 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key); 8007 if (ret) { 8008 dev_info(&pf->pdev->dev, 8009 "Cannot set RSS key, err %s aq_err %s\n", 8010 i40e_stat_str(&pf->hw, ret), 8011 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 8012 goto config_rss_aq_out; 8013 } 8014 8015 if (vsi->type == I40E_VSI_MAIN) 8016 pf_lut = true; 8017 8018 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut, 8019 vsi->rss_table_size); 8020 if (ret) 8021 dev_info(&pf->pdev->dev, 8022 "Cannot set RSS lut, err %s aq_err %s\n", 8023 i40e_stat_str(&pf->hw, ret), 8024 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 8025 8026 config_rss_aq_out: 8027 kfree(rss_lut); 8028 return ret; 8029 } 8030 8031 /** 8032 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used 8033 * @vsi: VSI structure 8034 **/ 8035 static int i40e_vsi_config_rss(struct i40e_vsi *vsi) 8036 { 8037 u8 seed[I40E_HKEY_ARRAY_SIZE]; 8038 struct i40e_pf *pf = vsi->back; 8039 u8 *lut; 8040 int ret; 8041 8042 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)) 8043 return 0; 8044 8045 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); 8046 if (!lut) 8047 return -ENOMEM; 8048 8049 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); 8050 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); 8051 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs); 8052 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); 8053 kfree(lut); 8054 8055 return ret; 8056 } 8057 8058 /** 8059 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands 8060 * @vsi: Pointer to vsi structure 8061 * @seed: Buffter to store the hash keys 8062 * @lut: Buffer to store the lookup table entries 8063 * @lut_size: Size of buffer to store the lookup table entries 8064 * 8065 * Return 0 on success, negative on failure 8066 */ 8067 static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, 8068 u8 *lut, u16 lut_size) 8069 { 8070 struct i40e_pf *pf = vsi->back; 8071 struct i40e_hw *hw = &pf->hw; 8072 int ret = 0; 8073 8074 if (seed) { 8075 ret = i40e_aq_get_rss_key(hw, vsi->id, 8076 (struct i40e_aqc_get_set_rss_key_data *)seed); 8077 if (ret) { 8078 dev_info(&pf->pdev->dev, 8079 "Cannot get RSS key, err %s aq_err %s\n", 8080 i40e_stat_str(&pf->hw, ret), 8081 i40e_aq_str(&pf->hw, 8082 pf->hw.aq.asq_last_status)); 8083 return ret; 8084 } 8085 } 8086 8087 if (lut) { 8088 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; 8089 8090 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); 8091 if (ret) { 8092 dev_info(&pf->pdev->dev, 8093 "Cannot get RSS lut, err %s aq_err %s\n", 8094 i40e_stat_str(&pf->hw, ret), 8095 i40e_aq_str(&pf->hw, 8096 pf->hw.aq.asq_last_status)); 8097 return ret; 8098 } 8099 } 8100 8101 return ret; 8102 } 8103 8104 /** 8105 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers 8106 * @vsi: Pointer to vsi structure 8107 * @seed: RSS hash seed 8108 * @lut: Lookup table 8109 * @lut_size: Lookup table size 8110 * 8111 * Returns 0 on success, negative on failure 8112 **/ 8113 static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, 8114 const u8 *lut, u16 lut_size) 8115 { 8116 struct i40e_pf *pf = vsi->back; 8117 struct i40e_hw *hw = &pf->hw; 8118 u16 vf_id = vsi->vf_id; 8119 u8 i; 8120 8121 /* Fill out hash function seed */ 8122 if (seed) { 8123 u32 *seed_dw = (u32 *)seed; 8124 8125 if (vsi->type == I40E_VSI_MAIN) { 8126 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 8127 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), 8128 seed_dw[i]); 8129 } else if (vsi->type == I40E_VSI_SRIOV) { 8130 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) 8131 i40e_write_rx_ctl(hw, 8132 I40E_VFQF_HKEY1(i, vf_id), 8133 seed_dw[i]); 8134 } else { 8135 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); 8136 } 8137 } 8138 8139 if (lut) { 8140 u32 *lut_dw = (u32 *)lut; 8141 8142 if (vsi->type == I40E_VSI_MAIN) { 8143 if (lut_size != I40E_HLUT_ARRAY_SIZE) 8144 return -EINVAL; 8145 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) 8146 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); 8147 } else if (vsi->type == I40E_VSI_SRIOV) { 8148 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) 8149 return -EINVAL; 8150 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) 8151 i40e_write_rx_ctl(hw, 8152 I40E_VFQF_HLUT1(i, vf_id), 8153 lut_dw[i]); 8154 } else { 8155 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); 8156 } 8157 } 8158 i40e_flush(hw); 8159 8160 return 0; 8161 } 8162 8163 /** 8164 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers 8165 * @vsi: Pointer to VSI structure 8166 * @seed: Buffer to store the keys 8167 * @lut: Buffer to store the lookup table entries 8168 * @lut_size: Size of buffer to store the lookup table entries 8169 * 8170 * Returns 0 on success, negative on failure 8171 */ 8172 static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, 8173 u8 *lut, u16 lut_size) 8174 { 8175 struct i40e_pf *pf = vsi->back; 8176 struct i40e_hw *hw = &pf->hw; 8177 u16 i; 8178 8179 if (seed) { 8180 u32 *seed_dw = (u32 *)seed; 8181 8182 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) 8183 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); 8184 } 8185 if (lut) { 8186 u32 *lut_dw = (u32 *)lut; 8187 8188 if (lut_size != I40E_HLUT_ARRAY_SIZE) 8189 return -EINVAL; 8190 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) 8191 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); 8192 } 8193 8194 return 0; 8195 } 8196 8197 /** 8198 * i40e_config_rss - Configure RSS keys and lut 8199 * @vsi: Pointer to VSI structure 8200 * @seed: RSS hash seed 8201 * @lut: Lookup table 8202 * @lut_size: Lookup table size 8203 * 8204 * Returns 0 on success, negative on failure 8205 */ 8206 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) 8207 { 8208 struct i40e_pf *pf = vsi->back; 8209 8210 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) 8211 return i40e_config_rss_aq(vsi, seed, lut, lut_size); 8212 else 8213 return i40e_config_rss_reg(vsi, seed, lut, lut_size); 8214 } 8215 8216 /** 8217 * i40e_get_rss - Get RSS keys and lut 8218 * @vsi: Pointer to VSI structure 8219 * @seed: Buffer to store the keys 8220 * @lut: Buffer to store the lookup table entries 8221 * lut_size: Size of buffer to store the lookup table entries 8222 * 8223 * Returns 0 on success, negative on failure 8224 */ 8225 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) 8226 { 8227 struct i40e_pf *pf = vsi->back; 8228 8229 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) 8230 return i40e_get_rss_aq(vsi, seed, lut, lut_size); 8231 else 8232 return i40e_get_rss_reg(vsi, seed, lut, lut_size); 8233 } 8234 8235 /** 8236 * i40e_fill_rss_lut - Fill the RSS lookup table with default values 8237 * @pf: Pointer to board private structure 8238 * @lut: Lookup table 8239 * @rss_table_size: Lookup table size 8240 * @rss_size: Range of queue number for hashing 8241 */ 8242 static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 8243 u16 rss_table_size, u16 rss_size) 8244 { 8245 u16 i; 8246 8247 for (i = 0; i < rss_table_size; i++) 8248 lut[i] = i % rss_size; 8249 } 8250 8251 /** 8252 * i40e_pf_config_rss - Prepare for RSS if used 8253 * @pf: board private structure 8254 **/ 8255 static int i40e_pf_config_rss(struct i40e_pf *pf) 8256 { 8257 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 8258 u8 seed[I40E_HKEY_ARRAY_SIZE]; 8259 u8 *lut; 8260 struct i40e_hw *hw = &pf->hw; 8261 u32 reg_val; 8262 u64 hena; 8263 int ret; 8264 8265 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ 8266 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | 8267 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); 8268 hena |= i40e_pf_get_default_rss_hena(pf); 8269 8270 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); 8271 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 8272 8273 /* Determine the RSS table size based on the hardware capabilities */ 8274 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 8275 reg_val = (pf->rss_table_size == 512) ? 8276 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : 8277 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); 8278 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); 8279 8280 /* Determine the RSS size of the VSI */ 8281 if (!vsi->rss_size) 8282 vsi->rss_size = min_t(int, pf->alloc_rss_size, 8283 vsi->num_queue_pairs); 8284 8285 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); 8286 if (!lut) 8287 return -ENOMEM; 8288 8289 /* Use user configured lut if there is one, otherwise use default */ 8290 if (vsi->rss_lut_user) 8291 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); 8292 else 8293 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); 8294 8295 /* Use user configured hash key if there is one, otherwise 8296 * use default. 8297 */ 8298 if (vsi->rss_hkey_user) 8299 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); 8300 else 8301 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); 8302 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); 8303 kfree(lut); 8304 8305 return ret; 8306 } 8307 8308 /** 8309 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild 8310 * @pf: board private structure 8311 * @queue_count: the requested queue count for rss. 8312 * 8313 * returns 0 if rss is not enabled, if enabled returns the final rss queue 8314 * count which may be different from the requested queue count. 8315 **/ 8316 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) 8317 { 8318 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; 8319 int new_rss_size; 8320 8321 if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) 8322 return 0; 8323 8324 new_rss_size = min_t(int, queue_count, pf->rss_size_max); 8325 8326 if (queue_count != vsi->num_queue_pairs) { 8327 vsi->req_queue_pairs = queue_count; 8328 i40e_prep_for_reset(pf); 8329 8330 pf->alloc_rss_size = new_rss_size; 8331 8332 i40e_reset_and_rebuild(pf, true); 8333 8334 /* Discard the user configured hash keys and lut, if less 8335 * queues are enabled. 8336 */ 8337 if (queue_count < vsi->rss_size) { 8338 i40e_clear_rss_config_user(vsi); 8339 dev_dbg(&pf->pdev->dev, 8340 "discard user configured hash keys and lut\n"); 8341 } 8342 8343 /* Reset vsi->rss_size, as number of enabled queues changed */ 8344 vsi->rss_size = min_t(int, pf->alloc_rss_size, 8345 vsi->num_queue_pairs); 8346 8347 i40e_pf_config_rss(pf); 8348 } 8349 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n", 8350 pf->alloc_rss_size, pf->rss_size_max); 8351 return pf->alloc_rss_size; 8352 } 8353 8354 /** 8355 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition 8356 * @pf: board private structure 8357 **/ 8358 i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf) 8359 { 8360 i40e_status status; 8361 bool min_valid, max_valid; 8362 u32 max_bw, min_bw; 8363 8364 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, 8365 &min_valid, &max_valid); 8366 8367 if (!status) { 8368 if (min_valid) 8369 pf->npar_min_bw = min_bw; 8370 if (max_valid) 8371 pf->npar_max_bw = max_bw; 8372 } 8373 8374 return status; 8375 } 8376 8377 /** 8378 * i40e_set_npar_bw_setting - Set BW settings for this PF partition 8379 * @pf: board private structure 8380 **/ 8381 i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf) 8382 { 8383 struct i40e_aqc_configure_partition_bw_data bw_data; 8384 i40e_status status; 8385 8386 /* Set the valid bit for this PF */ 8387 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); 8388 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK; 8389 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK; 8390 8391 /* Set the new bandwidths */ 8392 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); 8393 8394 return status; 8395 } 8396 8397 /** 8398 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition 8399 * @pf: board private structure 8400 **/ 8401 i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf) 8402 { 8403 /* Commit temporary BW setting to permanent NVM image */ 8404 enum i40e_admin_queue_err last_aq_status; 8405 i40e_status ret; 8406 u16 nvm_word; 8407 8408 if (pf->hw.partition_id != 1) { 8409 dev_info(&pf->pdev->dev, 8410 "Commit BW only works on partition 1! This is partition %d", 8411 pf->hw.partition_id); 8412 ret = I40E_NOT_SUPPORTED; 8413 goto bw_commit_out; 8414 } 8415 8416 /* Acquire NVM for read access */ 8417 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); 8418 last_aq_status = pf->hw.aq.asq_last_status; 8419 if (ret) { 8420 dev_info(&pf->pdev->dev, 8421 "Cannot acquire NVM for read access, err %s aq_err %s\n", 8422 i40e_stat_str(&pf->hw, ret), 8423 i40e_aq_str(&pf->hw, last_aq_status)); 8424 goto bw_commit_out; 8425 } 8426 8427 /* Read word 0x10 of NVM - SW compatibility word 1 */ 8428 ret = i40e_aq_read_nvm(&pf->hw, 8429 I40E_SR_NVM_CONTROL_WORD, 8430 0x10, sizeof(nvm_word), &nvm_word, 8431 false, NULL); 8432 /* Save off last admin queue command status before releasing 8433 * the NVM 8434 */ 8435 last_aq_status = pf->hw.aq.asq_last_status; 8436 i40e_release_nvm(&pf->hw); 8437 if (ret) { 8438 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", 8439 i40e_stat_str(&pf->hw, ret), 8440 i40e_aq_str(&pf->hw, last_aq_status)); 8441 goto bw_commit_out; 8442 } 8443 8444 /* Wait a bit for NVM release to complete */ 8445 msleep(50); 8446 8447 /* Acquire NVM for write access */ 8448 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); 8449 last_aq_status = pf->hw.aq.asq_last_status; 8450 if (ret) { 8451 dev_info(&pf->pdev->dev, 8452 "Cannot acquire NVM for write access, err %s aq_err %s\n", 8453 i40e_stat_str(&pf->hw, ret), 8454 i40e_aq_str(&pf->hw, last_aq_status)); 8455 goto bw_commit_out; 8456 } 8457 /* Write it back out unchanged to initiate update NVM, 8458 * which will force a write of the shadow (alt) RAM to 8459 * the NVM - thus storing the bandwidth values permanently. 8460 */ 8461 ret = i40e_aq_update_nvm(&pf->hw, 8462 I40E_SR_NVM_CONTROL_WORD, 8463 0x10, sizeof(nvm_word), 8464 &nvm_word, true, NULL); 8465 /* Save off last admin queue command status before releasing 8466 * the NVM 8467 */ 8468 last_aq_status = pf->hw.aq.asq_last_status; 8469 i40e_release_nvm(&pf->hw); 8470 if (ret) 8471 dev_info(&pf->pdev->dev, 8472 "BW settings NOT SAVED, err %s aq_err %s\n", 8473 i40e_stat_str(&pf->hw, ret), 8474 i40e_aq_str(&pf->hw, last_aq_status)); 8475 bw_commit_out: 8476 8477 return ret; 8478 } 8479 8480 /** 8481 * i40e_sw_init - Initialize general software structures (struct i40e_pf) 8482 * @pf: board private structure to initialize 8483 * 8484 * i40e_sw_init initializes the Adapter private data structure. 8485 * Fields are initialized based on PCI device information and 8486 * OS network device settings (MTU size). 8487 **/ 8488 static int i40e_sw_init(struct i40e_pf *pf) 8489 { 8490 int err = 0; 8491 int size; 8492 8493 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE, 8494 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)); 8495 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) { 8496 if (I40E_DEBUG_USER & debug) 8497 pf->hw.debug_mask = debug; 8498 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER), 8499 I40E_DEFAULT_MSG_ENABLE); 8500 } 8501 8502 /* Set default capability flags */ 8503 pf->flags = I40E_FLAG_RX_CSUM_ENABLED | 8504 I40E_FLAG_MSI_ENABLED | 8505 I40E_FLAG_MSIX_ENABLED; 8506 8507 /* Set default ITR */ 8508 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF; 8509 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF; 8510 8511 /* Depending on PF configurations, it is possible that the RSS 8512 * maximum might end up larger than the available queues 8513 */ 8514 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); 8515 pf->alloc_rss_size = 1; 8516 pf->rss_table_size = pf->hw.func_caps.rss_table_size; 8517 pf->rss_size_max = min_t(int, pf->rss_size_max, 8518 pf->hw.func_caps.num_tx_qp); 8519 if (pf->hw.func_caps.rss) { 8520 pf->flags |= I40E_FLAG_RSS_ENABLED; 8521 pf->alloc_rss_size = min_t(int, pf->rss_size_max, 8522 num_online_cpus()); 8523 } 8524 8525 /* MFP mode enabled */ 8526 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { 8527 pf->flags |= I40E_FLAG_MFP_ENABLED; 8528 dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); 8529 if (i40e_get_npar_bw_setting(pf)) 8530 dev_warn(&pf->pdev->dev, 8531 "Could not get NPAR bw settings\n"); 8532 else 8533 dev_info(&pf->pdev->dev, 8534 "Min BW = %8.8x, Max BW = %8.8x\n", 8535 pf->npar_min_bw, pf->npar_max_bw); 8536 } 8537 8538 /* FW/NVM is not yet fixed in this regard */ 8539 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || 8540 (pf->hw.func_caps.fd_filters_best_effort > 0)) { 8541 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 8542 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; 8543 if (pf->flags & I40E_FLAG_MFP_ENABLED && 8544 pf->hw.num_partitions > 1) 8545 dev_info(&pf->pdev->dev, 8546 "Flow Director Sideband mode Disabled in MFP mode\n"); 8547 else 8548 pf->flags |= I40E_FLAG_FD_SB_ENABLED; 8549 pf->fdir_pf_filter_count = 8550 pf->hw.func_caps.fd_filters_guaranteed; 8551 pf->hw.fdir_shared_filter_count = 8552 pf->hw.func_caps.fd_filters_best_effort; 8553 } 8554 8555 if (i40e_is_mac_710(&pf->hw) && 8556 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || 8557 (pf->hw.aq.fw_maj_ver < 4))) { 8558 pf->flags |= I40E_FLAG_RESTART_AUTONEG; 8559 /* No DCB support for FW < v4.33 */ 8560 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT; 8561 } 8562 8563 /* Disable FW LLDP if FW < v4.3 */ 8564 if (i40e_is_mac_710(&pf->hw) && 8565 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || 8566 (pf->hw.aq.fw_maj_ver < 4))) 8567 pf->flags |= I40E_FLAG_STOP_FW_LLDP; 8568 8569 /* Use the FW Set LLDP MIB API if FW > v4.40 */ 8570 if (i40e_is_mac_710(&pf->hw) && 8571 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || 8572 (pf->hw.aq.fw_maj_ver >= 5))) 8573 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB; 8574 8575 if (pf->hw.func_caps.vmdq) { 8576 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; 8577 pf->flags |= I40E_FLAG_VMDQ_ENABLED; 8578 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); 8579 } 8580 8581 if (pf->hw.func_caps.iwarp) { 8582 pf->flags |= I40E_FLAG_IWARP_ENABLED; 8583 /* IWARP needs one extra vector for CQP just like MISC.*/ 8584 pf->num_iwarp_msix = (int)num_online_cpus() + 1; 8585 } 8586 8587 #ifdef I40E_FCOE 8588 i40e_init_pf_fcoe(pf); 8589 8590 #endif /* I40E_FCOE */ 8591 #ifdef CONFIG_PCI_IOV 8592 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { 8593 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; 8594 pf->flags |= I40E_FLAG_SRIOV_ENABLED; 8595 pf->num_req_vfs = min_t(int, 8596 pf->hw.func_caps.num_vfs, 8597 I40E_MAX_VF_COUNT); 8598 } 8599 #endif /* CONFIG_PCI_IOV */ 8600 if (pf->hw.mac.type == I40E_MAC_X722) { 8601 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE | 8602 I40E_FLAG_128_QP_RSS_CAPABLE | 8603 I40E_FLAG_HW_ATR_EVICT_CAPABLE | 8604 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE | 8605 I40E_FLAG_WB_ON_ITR_CAPABLE | 8606 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE | 8607 I40E_FLAG_NO_PCI_LINK_CHECK | 8608 I40E_FLAG_100M_SGMII_CAPABLE | 8609 I40E_FLAG_USE_SET_LLDP_MIB | 8610 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; 8611 } else if ((pf->hw.aq.api_maj_ver > 1) || 8612 ((pf->hw.aq.api_maj_ver == 1) && 8613 (pf->hw.aq.api_min_ver > 4))) { 8614 /* Supported in FW API version higher than 1.4 */ 8615 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE; 8616 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; 8617 } else { 8618 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE; 8619 } 8620 8621 pf->eeprom_version = 0xDEAD; 8622 pf->lan_veb = I40E_NO_VEB; 8623 pf->lan_vsi = I40E_NO_VSI; 8624 8625 /* By default FW has this off for performance reasons */ 8626 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; 8627 8628 /* set up queue assignment tracking */ 8629 size = sizeof(struct i40e_lump_tracking) 8630 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); 8631 pf->qp_pile = kzalloc(size, GFP_KERNEL); 8632 if (!pf->qp_pile) { 8633 err = -ENOMEM; 8634 goto sw_init_done; 8635 } 8636 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; 8637 pf->qp_pile->search_hint = 0; 8638 8639 pf->tx_timeout_recovery_level = 1; 8640 8641 mutex_init(&pf->switch_mutex); 8642 8643 /* If NPAR is enabled nudge the Tx scheduler */ 8644 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf))) 8645 i40e_set_npar_bw_setting(pf); 8646 8647 sw_init_done: 8648 return err; 8649 } 8650 8651 /** 8652 * i40e_set_ntuple - set the ntuple feature flag and take action 8653 * @pf: board private structure to initialize 8654 * @features: the feature set that the stack is suggesting 8655 * 8656 * returns a bool to indicate if reset needs to happen 8657 **/ 8658 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) 8659 { 8660 bool need_reset = false; 8661 8662 /* Check if Flow Director n-tuple support was enabled or disabled. If 8663 * the state changed, we need to reset. 8664 */ 8665 if (features & NETIF_F_NTUPLE) { 8666 /* Enable filters and mark for reset */ 8667 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) 8668 need_reset = true; 8669 /* enable FD_SB only if there is MSI-X vector */ 8670 if (pf->num_fdsb_msix > 0) 8671 pf->flags |= I40E_FLAG_FD_SB_ENABLED; 8672 } else { 8673 /* turn off filters, mark for reset and clear SW filter list */ 8674 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { 8675 need_reset = true; 8676 i40e_fdir_filter_exit(pf); 8677 } 8678 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; 8679 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED; 8680 /* reset fd counters */ 8681 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0; 8682 pf->fdir_pf_active_filters = 0; 8683 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 8684 if (I40E_DEBUG_FD & pf->hw.debug_mask) 8685 dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); 8686 /* if ATR was auto disabled it can be re-enabled. */ 8687 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && 8688 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 8689 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED; 8690 } 8691 return need_reset; 8692 } 8693 8694 /** 8695 * i40e_set_features - set the netdev feature flags 8696 * @netdev: ptr to the netdev being adjusted 8697 * @features: the feature set that the stack is suggesting 8698 **/ 8699 static int i40e_set_features(struct net_device *netdev, 8700 netdev_features_t features) 8701 { 8702 struct i40e_netdev_priv *np = netdev_priv(netdev); 8703 struct i40e_vsi *vsi = np->vsi; 8704 struct i40e_pf *pf = vsi->back; 8705 bool need_reset; 8706 8707 if (features & NETIF_F_HW_VLAN_CTAG_RX) 8708 i40e_vlan_stripping_enable(vsi); 8709 else 8710 i40e_vlan_stripping_disable(vsi); 8711 8712 need_reset = i40e_set_ntuple(pf, features); 8713 8714 if (need_reset) 8715 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); 8716 8717 return 0; 8718 } 8719 8720 /** 8721 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port 8722 * @pf: board private structure 8723 * @port: The UDP port to look up 8724 * 8725 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found 8726 **/ 8727 static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port) 8728 { 8729 u8 i; 8730 8731 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { 8732 if (pf->udp_ports[i].index == port) 8733 return i; 8734 } 8735 8736 return i; 8737 } 8738 8739 /** 8740 * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up 8741 * @netdev: This physical port's netdev 8742 * @ti: Tunnel endpoint information 8743 **/ 8744 static void i40e_udp_tunnel_add(struct net_device *netdev, 8745 struct udp_tunnel_info *ti) 8746 { 8747 struct i40e_netdev_priv *np = netdev_priv(netdev); 8748 struct i40e_vsi *vsi = np->vsi; 8749 struct i40e_pf *pf = vsi->back; 8750 __be16 port = ti->port; 8751 u8 next_idx; 8752 u8 idx; 8753 8754 idx = i40e_get_udp_port_idx(pf, port); 8755 8756 /* Check if port already exists */ 8757 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { 8758 netdev_info(netdev, "port %d already offloaded\n", 8759 ntohs(port)); 8760 return; 8761 } 8762 8763 /* Now check if there is space to add the new port */ 8764 next_idx = i40e_get_udp_port_idx(pf, 0); 8765 8766 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { 8767 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", 8768 ntohs(port)); 8769 return; 8770 } 8771 8772 switch (ti->type) { 8773 case UDP_TUNNEL_TYPE_VXLAN: 8774 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; 8775 break; 8776 case UDP_TUNNEL_TYPE_GENEVE: 8777 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE)) 8778 return; 8779 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; 8780 break; 8781 default: 8782 return; 8783 } 8784 8785 /* New port: add it and mark its index in the bitmap */ 8786 pf->udp_ports[next_idx].index = port; 8787 pf->pending_udp_bitmap |= BIT_ULL(next_idx); 8788 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; 8789 } 8790 8791 /** 8792 * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away 8793 * @netdev: This physical port's netdev 8794 * @ti: Tunnel endpoint information 8795 **/ 8796 static void i40e_udp_tunnel_del(struct net_device *netdev, 8797 struct udp_tunnel_info *ti) 8798 { 8799 struct i40e_netdev_priv *np = netdev_priv(netdev); 8800 struct i40e_vsi *vsi = np->vsi; 8801 struct i40e_pf *pf = vsi->back; 8802 __be16 port = ti->port; 8803 u8 idx; 8804 8805 idx = i40e_get_udp_port_idx(pf, port); 8806 8807 /* Check if port already exists */ 8808 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) 8809 goto not_found; 8810 8811 switch (ti->type) { 8812 case UDP_TUNNEL_TYPE_VXLAN: 8813 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) 8814 goto not_found; 8815 break; 8816 case UDP_TUNNEL_TYPE_GENEVE: 8817 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) 8818 goto not_found; 8819 break; 8820 default: 8821 goto not_found; 8822 } 8823 8824 /* if port exists, set it to 0 (mark for deletion) 8825 * and make it pending 8826 */ 8827 pf->udp_ports[idx].index = 0; 8828 pf->pending_udp_bitmap |= BIT_ULL(idx); 8829 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; 8830 8831 return; 8832 not_found: 8833 netdev_warn(netdev, "UDP port %d was not found, not deleting\n", 8834 ntohs(port)); 8835 } 8836 8837 static int i40e_get_phys_port_id(struct net_device *netdev, 8838 struct netdev_phys_item_id *ppid) 8839 { 8840 struct i40e_netdev_priv *np = netdev_priv(netdev); 8841 struct i40e_pf *pf = np->vsi->back; 8842 struct i40e_hw *hw = &pf->hw; 8843 8844 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID)) 8845 return -EOPNOTSUPP; 8846 8847 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); 8848 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); 8849 8850 return 0; 8851 } 8852 8853 /** 8854 * i40e_ndo_fdb_add - add an entry to the hardware database 8855 * @ndm: the input from the stack 8856 * @tb: pointer to array of nladdr (unused) 8857 * @dev: the net device pointer 8858 * @addr: the MAC address entry being added 8859 * @flags: instructions from stack about fdb operation 8860 */ 8861 static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 8862 struct net_device *dev, 8863 const unsigned char *addr, u16 vid, 8864 u16 flags) 8865 { 8866 struct i40e_netdev_priv *np = netdev_priv(dev); 8867 struct i40e_pf *pf = np->vsi->back; 8868 int err = 0; 8869 8870 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) 8871 return -EOPNOTSUPP; 8872 8873 if (vid) { 8874 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); 8875 return -EINVAL; 8876 } 8877 8878 /* Hardware does not support aging addresses so if a 8879 * ndm_state is given only allow permanent addresses 8880 */ 8881 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { 8882 netdev_info(dev, "FDB only supports static addresses\n"); 8883 return -EINVAL; 8884 } 8885 8886 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) 8887 err = dev_uc_add_excl(dev, addr); 8888 else if (is_multicast_ether_addr(addr)) 8889 err = dev_mc_add_excl(dev, addr); 8890 else 8891 err = -EINVAL; 8892 8893 /* Only return duplicate errors if NLM_F_EXCL is set */ 8894 if (err == -EEXIST && !(flags & NLM_F_EXCL)) 8895 err = 0; 8896 8897 return err; 8898 } 8899 8900 /** 8901 * i40e_ndo_bridge_setlink - Set the hardware bridge mode 8902 * @dev: the netdev being configured 8903 * @nlh: RTNL message 8904 * 8905 * Inserts a new hardware bridge if not already created and 8906 * enables the bridging mode requested (VEB or VEPA). If the 8907 * hardware bridge has already been inserted and the request 8908 * is to change the mode then that requires a PF reset to 8909 * allow rebuild of the components with required hardware 8910 * bridge mode enabled. 8911 **/ 8912 static int i40e_ndo_bridge_setlink(struct net_device *dev, 8913 struct nlmsghdr *nlh, 8914 u16 flags) 8915 { 8916 struct i40e_netdev_priv *np = netdev_priv(dev); 8917 struct i40e_vsi *vsi = np->vsi; 8918 struct i40e_pf *pf = vsi->back; 8919 struct i40e_veb *veb = NULL; 8920 struct nlattr *attr, *br_spec; 8921 int i, rem; 8922 8923 /* Only for PF VSI for now */ 8924 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) 8925 return -EOPNOTSUPP; 8926 8927 /* Find the HW bridge for PF VSI */ 8928 for (i = 0; i < I40E_MAX_VEB && !veb; i++) { 8929 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) 8930 veb = pf->veb[i]; 8931 } 8932 8933 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 8934 8935 nla_for_each_nested(attr, br_spec, rem) { 8936 __u16 mode; 8937 8938 if (nla_type(attr) != IFLA_BRIDGE_MODE) 8939 continue; 8940 8941 mode = nla_get_u16(attr); 8942 if ((mode != BRIDGE_MODE_VEPA) && 8943 (mode != BRIDGE_MODE_VEB)) 8944 return -EINVAL; 8945 8946 /* Insert a new HW bridge */ 8947 if (!veb) { 8948 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, 8949 vsi->tc_config.enabled_tc); 8950 if (veb) { 8951 veb->bridge_mode = mode; 8952 i40e_config_bridge_mode(veb); 8953 } else { 8954 /* No Bridge HW offload available */ 8955 return -ENOENT; 8956 } 8957 break; 8958 } else if (mode != veb->bridge_mode) { 8959 /* Existing HW bridge but different mode needs reset */ 8960 veb->bridge_mode = mode; 8961 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ 8962 if (mode == BRIDGE_MODE_VEB) 8963 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; 8964 else 8965 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; 8966 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); 8967 break; 8968 } 8969 } 8970 8971 return 0; 8972 } 8973 8974 /** 8975 * i40e_ndo_bridge_getlink - Get the hardware bridge mode 8976 * @skb: skb buff 8977 * @pid: process id 8978 * @seq: RTNL message seq # 8979 * @dev: the netdev being configured 8980 * @filter_mask: unused 8981 * @nlflags: netlink flags passed in 8982 * 8983 * Return the mode in which the hardware bridge is operating in 8984 * i.e VEB or VEPA. 8985 **/ 8986 static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 8987 struct net_device *dev, 8988 u32 __always_unused filter_mask, 8989 int nlflags) 8990 { 8991 struct i40e_netdev_priv *np = netdev_priv(dev); 8992 struct i40e_vsi *vsi = np->vsi; 8993 struct i40e_pf *pf = vsi->back; 8994 struct i40e_veb *veb = NULL; 8995 int i; 8996 8997 /* Only for PF VSI for now */ 8998 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) 8999 return -EOPNOTSUPP; 9000 9001 /* Find the HW bridge for the PF VSI */ 9002 for (i = 0; i < I40E_MAX_VEB && !veb; i++) { 9003 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) 9004 veb = pf->veb[i]; 9005 } 9006 9007 if (!veb) 9008 return 0; 9009 9010 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, 9011 nlflags, 0, 0, filter_mask, NULL); 9012 } 9013 9014 /* Hardware supports L4 tunnel length of 128B (=2^7) which includes 9015 * inner mac plus all inner ethertypes. 9016 */ 9017 #define I40E_MAX_TUNNEL_HDR_LEN 128 9018 /** 9019 * i40e_features_check - Validate encapsulated packet conforms to limits 9020 * @skb: skb buff 9021 * @dev: This physical port's netdev 9022 * @features: Offload features that the stack believes apply 9023 **/ 9024 static netdev_features_t i40e_features_check(struct sk_buff *skb, 9025 struct net_device *dev, 9026 netdev_features_t features) 9027 { 9028 if (skb->encapsulation && 9029 ((skb_inner_network_header(skb) - skb_transport_header(skb)) > 9030 I40E_MAX_TUNNEL_HDR_LEN)) 9031 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 9032 9033 return features; 9034 } 9035 9036 static const struct net_device_ops i40e_netdev_ops = { 9037 .ndo_open = i40e_open, 9038 .ndo_stop = i40e_close, 9039 .ndo_start_xmit = i40e_lan_xmit_frame, 9040 .ndo_get_stats64 = i40e_get_netdev_stats_struct, 9041 .ndo_set_rx_mode = i40e_set_rx_mode, 9042 .ndo_validate_addr = eth_validate_addr, 9043 .ndo_set_mac_address = i40e_set_mac, 9044 .ndo_change_mtu = i40e_change_mtu, 9045 .ndo_do_ioctl = i40e_ioctl, 9046 .ndo_tx_timeout = i40e_tx_timeout, 9047 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, 9048 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, 9049 #ifdef CONFIG_NET_POLL_CONTROLLER 9050 .ndo_poll_controller = i40e_netpoll, 9051 #endif 9052 .ndo_setup_tc = __i40e_setup_tc, 9053 #ifdef I40E_FCOE 9054 .ndo_fcoe_enable = i40e_fcoe_enable, 9055 .ndo_fcoe_disable = i40e_fcoe_disable, 9056 #endif 9057 .ndo_set_features = i40e_set_features, 9058 .ndo_set_vf_mac = i40e_ndo_set_vf_mac, 9059 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, 9060 .ndo_set_vf_rate = i40e_ndo_set_vf_bw, 9061 .ndo_get_vf_config = i40e_ndo_get_vf_config, 9062 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, 9063 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, 9064 .ndo_set_vf_trust = i40e_ndo_set_vf_trust, 9065 .ndo_udp_tunnel_add = i40e_udp_tunnel_add, 9066 .ndo_udp_tunnel_del = i40e_udp_tunnel_del, 9067 .ndo_get_phys_port_id = i40e_get_phys_port_id, 9068 .ndo_fdb_add = i40e_ndo_fdb_add, 9069 .ndo_features_check = i40e_features_check, 9070 .ndo_bridge_getlink = i40e_ndo_bridge_getlink, 9071 .ndo_bridge_setlink = i40e_ndo_bridge_setlink, 9072 }; 9073 9074 /** 9075 * i40e_config_netdev - Setup the netdev flags 9076 * @vsi: the VSI being configured 9077 * 9078 * Returns 0 on success, negative value on failure 9079 **/ 9080 static int i40e_config_netdev(struct i40e_vsi *vsi) 9081 { 9082 struct i40e_pf *pf = vsi->back; 9083 struct i40e_hw *hw = &pf->hw; 9084 struct i40e_netdev_priv *np; 9085 struct net_device *netdev; 9086 u8 mac_addr[ETH_ALEN]; 9087 int etherdev_size; 9088 9089 etherdev_size = sizeof(struct i40e_netdev_priv); 9090 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); 9091 if (!netdev) 9092 return -ENOMEM; 9093 9094 vsi->netdev = netdev; 9095 np = netdev_priv(netdev); 9096 np->vsi = vsi; 9097 9098 netdev->hw_enc_features |= NETIF_F_SG | 9099 NETIF_F_IP_CSUM | 9100 NETIF_F_IPV6_CSUM | 9101 NETIF_F_HIGHDMA | 9102 NETIF_F_SOFT_FEATURES | 9103 NETIF_F_TSO | 9104 NETIF_F_TSO_ECN | 9105 NETIF_F_TSO6 | 9106 NETIF_F_GSO_GRE | 9107 NETIF_F_GSO_GRE_CSUM | 9108 NETIF_F_GSO_IPXIP4 | 9109 NETIF_F_GSO_IPXIP6 | 9110 NETIF_F_GSO_UDP_TUNNEL | 9111 NETIF_F_GSO_UDP_TUNNEL_CSUM | 9112 NETIF_F_GSO_PARTIAL | 9113 NETIF_F_SCTP_CRC | 9114 NETIF_F_RXHASH | 9115 NETIF_F_RXCSUM | 9116 0; 9117 9118 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)) 9119 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 9120 9121 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 9122 9123 /* record features VLANs can make use of */ 9124 netdev->vlan_features |= netdev->hw_enc_features | 9125 NETIF_F_TSO_MANGLEID; 9126 9127 if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) 9128 netdev->hw_features |= NETIF_F_NTUPLE; 9129 9130 netdev->hw_features |= netdev->hw_enc_features | 9131 NETIF_F_HW_VLAN_CTAG_TX | 9132 NETIF_F_HW_VLAN_CTAG_RX; 9133 9134 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 9135 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 9136 9137 if (vsi->type == I40E_VSI_MAIN) { 9138 SET_NETDEV_DEV(netdev, &pf->pdev->dev); 9139 ether_addr_copy(mac_addr, hw->mac.perm_addr); 9140 /* The following steps are necessary to prevent reception 9141 * of tagged packets - some older NVM configurations load a 9142 * default a MAC-VLAN filter that accepts any tagged packet 9143 * which must be replaced by a normal filter. 9144 */ 9145 i40e_rm_default_mac_filter(vsi, mac_addr); 9146 spin_lock_bh(&vsi->mac_filter_list_lock); 9147 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true); 9148 spin_unlock_bh(&vsi->mac_filter_list_lock); 9149 } else { 9150 /* relate the VSI_VMDQ name to the VSI_MAIN name */ 9151 snprintf(netdev->name, IFNAMSIZ, "%sv%%d", 9152 pf->vsi[pf->lan_vsi]->netdev->name); 9153 random_ether_addr(mac_addr); 9154 9155 spin_lock_bh(&vsi->mac_filter_list_lock); 9156 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false); 9157 spin_unlock_bh(&vsi->mac_filter_list_lock); 9158 } 9159 9160 ether_addr_copy(netdev->dev_addr, mac_addr); 9161 ether_addr_copy(netdev->perm_addr, mac_addr); 9162 9163 netdev->priv_flags |= IFF_UNICAST_FLT; 9164 netdev->priv_flags |= IFF_SUPP_NOFCS; 9165 /* Setup netdev TC information */ 9166 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); 9167 9168 netdev->netdev_ops = &i40e_netdev_ops; 9169 netdev->watchdog_timeo = 5 * HZ; 9170 i40e_set_ethtool_ops(netdev); 9171 #ifdef I40E_FCOE 9172 i40e_fcoe_config_netdev(netdev, vsi); 9173 #endif 9174 9175 return 0; 9176 } 9177 9178 /** 9179 * i40e_vsi_delete - Delete a VSI from the switch 9180 * @vsi: the VSI being removed 9181 * 9182 * Returns 0 on success, negative value on failure 9183 **/ 9184 static void i40e_vsi_delete(struct i40e_vsi *vsi) 9185 { 9186 /* remove default VSI is not allowed */ 9187 if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) 9188 return; 9189 9190 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); 9191 } 9192 9193 /** 9194 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB 9195 * @vsi: the VSI being queried 9196 * 9197 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode 9198 **/ 9199 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) 9200 { 9201 struct i40e_veb *veb; 9202 struct i40e_pf *pf = vsi->back; 9203 9204 /* Uplink is not a bridge so default to VEB */ 9205 if (vsi->veb_idx == I40E_NO_VEB) 9206 return 1; 9207 9208 veb = pf->veb[vsi->veb_idx]; 9209 if (!veb) { 9210 dev_info(&pf->pdev->dev, 9211 "There is no veb associated with the bridge\n"); 9212 return -ENOENT; 9213 } 9214 9215 /* Uplink is a bridge in VEPA mode */ 9216 if (veb->bridge_mode & BRIDGE_MODE_VEPA) { 9217 return 0; 9218 } else { 9219 /* Uplink is a bridge in VEB mode */ 9220 return 1; 9221 } 9222 9223 /* VEPA is now default bridge, so return 0 */ 9224 return 0; 9225 } 9226 9227 /** 9228 * i40e_add_vsi - Add a VSI to the switch 9229 * @vsi: the VSI being configured 9230 * 9231 * This initializes a VSI context depending on the VSI type to be added and 9232 * passes it down to the add_vsi aq command. 9233 **/ 9234 static int i40e_add_vsi(struct i40e_vsi *vsi) 9235 { 9236 int ret = -ENODEV; 9237 i40e_status aq_ret = 0; 9238 struct i40e_pf *pf = vsi->back; 9239 struct i40e_hw *hw = &pf->hw; 9240 struct i40e_vsi_context ctxt; 9241 struct i40e_mac_filter *f, *ftmp; 9242 9243 u8 enabled_tc = 0x1; /* TC0 enabled */ 9244 int f_count = 0; 9245 9246 memset(&ctxt, 0, sizeof(ctxt)); 9247 switch (vsi->type) { 9248 case I40E_VSI_MAIN: 9249 /* The PF's main VSI is already setup as part of the 9250 * device initialization, so we'll not bother with 9251 * the add_vsi call, but we will retrieve the current 9252 * VSI context. 9253 */ 9254 ctxt.seid = pf->main_vsi_seid; 9255 ctxt.pf_num = pf->hw.pf_id; 9256 ctxt.vf_num = 0; 9257 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); 9258 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 9259 if (ret) { 9260 dev_info(&pf->pdev->dev, 9261 "couldn't get PF vsi config, err %s aq_err %s\n", 9262 i40e_stat_str(&pf->hw, ret), 9263 i40e_aq_str(&pf->hw, 9264 pf->hw.aq.asq_last_status)); 9265 return -ENOENT; 9266 } 9267 vsi->info = ctxt.info; 9268 vsi->info.valid_sections = 0; 9269 9270 vsi->seid = ctxt.seid; 9271 vsi->id = ctxt.vsi_number; 9272 9273 enabled_tc = i40e_pf_get_tc_map(pf); 9274 9275 /* MFP mode setup queue map and update VSI */ 9276 if ((pf->flags & I40E_FLAG_MFP_ENABLED) && 9277 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ 9278 memset(&ctxt, 0, sizeof(ctxt)); 9279 ctxt.seid = pf->main_vsi_seid; 9280 ctxt.pf_num = pf->hw.pf_id; 9281 ctxt.vf_num = 0; 9282 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); 9283 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 9284 if (ret) { 9285 dev_info(&pf->pdev->dev, 9286 "update vsi failed, err %s aq_err %s\n", 9287 i40e_stat_str(&pf->hw, ret), 9288 i40e_aq_str(&pf->hw, 9289 pf->hw.aq.asq_last_status)); 9290 ret = -ENOENT; 9291 goto err; 9292 } 9293 /* update the local VSI info queue map */ 9294 i40e_vsi_update_queue_map(vsi, &ctxt); 9295 vsi->info.valid_sections = 0; 9296 } else { 9297 /* Default/Main VSI is only enabled for TC0 9298 * reconfigure it to enable all TCs that are 9299 * available on the port in SFP mode. 9300 * For MFP case the iSCSI PF would use this 9301 * flow to enable LAN+iSCSI TC. 9302 */ 9303 ret = i40e_vsi_config_tc(vsi, enabled_tc); 9304 if (ret) { 9305 dev_info(&pf->pdev->dev, 9306 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", 9307 enabled_tc, 9308 i40e_stat_str(&pf->hw, ret), 9309 i40e_aq_str(&pf->hw, 9310 pf->hw.aq.asq_last_status)); 9311 ret = -ENOENT; 9312 } 9313 } 9314 break; 9315 9316 case I40E_VSI_FDIR: 9317 ctxt.pf_num = hw->pf_id; 9318 ctxt.vf_num = 0; 9319 ctxt.uplink_seid = vsi->uplink_seid; 9320 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; 9321 ctxt.flags = I40E_AQ_VSI_TYPE_PF; 9322 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && 9323 (i40e_is_vsi_uplink_mode_veb(vsi))) { 9324 ctxt.info.valid_sections |= 9325 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); 9326 ctxt.info.switch_id = 9327 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 9328 } 9329 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); 9330 break; 9331 9332 case I40E_VSI_VMDQ2: 9333 ctxt.pf_num = hw->pf_id; 9334 ctxt.vf_num = 0; 9335 ctxt.uplink_seid = vsi->uplink_seid; 9336 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; 9337 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; 9338 9339 /* This VSI is connected to VEB so the switch_id 9340 * should be set to zero by default. 9341 */ 9342 if (i40e_is_vsi_uplink_mode_veb(vsi)) { 9343 ctxt.info.valid_sections |= 9344 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); 9345 ctxt.info.switch_id = 9346 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 9347 } 9348 9349 /* Setup the VSI tx/rx queue map for TC0 only for now */ 9350 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); 9351 break; 9352 9353 case I40E_VSI_SRIOV: 9354 ctxt.pf_num = hw->pf_id; 9355 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; 9356 ctxt.uplink_seid = vsi->uplink_seid; 9357 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; 9358 ctxt.flags = I40E_AQ_VSI_TYPE_VF; 9359 9360 /* This VSI is connected to VEB so the switch_id 9361 * should be set to zero by default. 9362 */ 9363 if (i40e_is_vsi_uplink_mode_veb(vsi)) { 9364 ctxt.info.valid_sections |= 9365 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); 9366 ctxt.info.switch_id = 9367 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); 9368 } 9369 9370 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { 9371 ctxt.info.valid_sections |= 9372 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); 9373 ctxt.info.queueing_opt_flags |= 9374 (I40E_AQ_VSI_QUE_OPT_TCP_ENA | 9375 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); 9376 } 9377 9378 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); 9379 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; 9380 if (pf->vf[vsi->vf_id].spoofchk) { 9381 ctxt.info.valid_sections |= 9382 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); 9383 ctxt.info.sec_flags |= 9384 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | 9385 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); 9386 } 9387 /* Setup the VSI tx/rx queue map for TC0 only for now */ 9388 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); 9389 break; 9390 9391 #ifdef I40E_FCOE 9392 case I40E_VSI_FCOE: 9393 ret = i40e_fcoe_vsi_init(vsi, &ctxt); 9394 if (ret) { 9395 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n"); 9396 return ret; 9397 } 9398 break; 9399 9400 #endif /* I40E_FCOE */ 9401 case I40E_VSI_IWARP: 9402 /* send down message to iWARP */ 9403 break; 9404 9405 default: 9406 return -ENODEV; 9407 } 9408 9409 if (vsi->type != I40E_VSI_MAIN) { 9410 ret = i40e_aq_add_vsi(hw, &ctxt, NULL); 9411 if (ret) { 9412 dev_info(&vsi->back->pdev->dev, 9413 "add vsi failed, err %s aq_err %s\n", 9414 i40e_stat_str(&pf->hw, ret), 9415 i40e_aq_str(&pf->hw, 9416 pf->hw.aq.asq_last_status)); 9417 ret = -ENOENT; 9418 goto err; 9419 } 9420 vsi->info = ctxt.info; 9421 vsi->info.valid_sections = 0; 9422 vsi->seid = ctxt.seid; 9423 vsi->id = ctxt.vsi_number; 9424 } 9425 /* Except FDIR VSI, for all othet VSI set the broadcast filter */ 9426 if (vsi->type != I40E_VSI_FDIR) { 9427 aq_ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, true, NULL); 9428 if (aq_ret) { 9429 ret = i40e_aq_rc_to_posix(aq_ret, 9430 hw->aq.asq_last_status); 9431 dev_info(&pf->pdev->dev, 9432 "set brdcast promisc failed, err %s, aq_err %s\n", 9433 i40e_stat_str(hw, aq_ret), 9434 i40e_aq_str(hw, hw->aq.asq_last_status)); 9435 } 9436 } 9437 9438 vsi->active_filters = 0; 9439 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state); 9440 spin_lock_bh(&vsi->mac_filter_list_lock); 9441 /* If macvlan filters already exist, force them to get loaded */ 9442 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) { 9443 f->state = I40E_FILTER_NEW; 9444 f_count++; 9445 } 9446 spin_unlock_bh(&vsi->mac_filter_list_lock); 9447 9448 if (f_count) { 9449 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; 9450 pf->flags |= I40E_FLAG_FILTER_SYNC; 9451 } 9452 9453 /* Update VSI BW information */ 9454 ret = i40e_vsi_get_bw_info(vsi); 9455 if (ret) { 9456 dev_info(&pf->pdev->dev, 9457 "couldn't get vsi bw info, err %s aq_err %s\n", 9458 i40e_stat_str(&pf->hw, ret), 9459 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 9460 /* VSI is already added so not tearing that up */ 9461 ret = 0; 9462 } 9463 9464 err: 9465 return ret; 9466 } 9467 9468 /** 9469 * i40e_vsi_release - Delete a VSI and free its resources 9470 * @vsi: the VSI being removed 9471 * 9472 * Returns 0 on success or < 0 on error 9473 **/ 9474 int i40e_vsi_release(struct i40e_vsi *vsi) 9475 { 9476 struct i40e_mac_filter *f, *ftmp; 9477 struct i40e_veb *veb = NULL; 9478 struct i40e_pf *pf; 9479 u16 uplink_seid; 9480 int i, n; 9481 9482 pf = vsi->back; 9483 9484 /* release of a VEB-owner or last VSI is not allowed */ 9485 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { 9486 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", 9487 vsi->seid, vsi->uplink_seid); 9488 return -ENODEV; 9489 } 9490 if (vsi == pf->vsi[pf->lan_vsi] && 9491 !test_bit(__I40E_DOWN, &pf->state)) { 9492 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); 9493 return -ENODEV; 9494 } 9495 9496 uplink_seid = vsi->uplink_seid; 9497 if (vsi->type != I40E_VSI_SRIOV) { 9498 if (vsi->netdev_registered) { 9499 vsi->netdev_registered = false; 9500 if (vsi->netdev) { 9501 /* results in a call to i40e_close() */ 9502 unregister_netdev(vsi->netdev); 9503 } 9504 } else { 9505 i40e_vsi_close(vsi); 9506 } 9507 i40e_vsi_disable_irq(vsi); 9508 } 9509 9510 spin_lock_bh(&vsi->mac_filter_list_lock); 9511 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) 9512 i40e_del_filter(vsi, f->macaddr, f->vlan, 9513 f->is_vf, f->is_netdev); 9514 spin_unlock_bh(&vsi->mac_filter_list_lock); 9515 9516 i40e_sync_vsi_filters(vsi); 9517 9518 i40e_vsi_delete(vsi); 9519 i40e_vsi_free_q_vectors(vsi); 9520 if (vsi->netdev) { 9521 free_netdev(vsi->netdev); 9522 vsi->netdev = NULL; 9523 } 9524 i40e_vsi_clear_rings(vsi); 9525 i40e_vsi_clear(vsi); 9526 9527 /* If this was the last thing on the VEB, except for the 9528 * controlling VSI, remove the VEB, which puts the controlling 9529 * VSI onto the next level down in the switch. 9530 * 9531 * Well, okay, there's one more exception here: don't remove 9532 * the orphan VEBs yet. We'll wait for an explicit remove request 9533 * from up the network stack. 9534 */ 9535 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { 9536 if (pf->vsi[i] && 9537 pf->vsi[i]->uplink_seid == uplink_seid && 9538 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { 9539 n++; /* count the VSIs */ 9540 } 9541 } 9542 for (i = 0; i < I40E_MAX_VEB; i++) { 9543 if (!pf->veb[i]) 9544 continue; 9545 if (pf->veb[i]->uplink_seid == uplink_seid) 9546 n++; /* count the VEBs */ 9547 if (pf->veb[i]->seid == uplink_seid) 9548 veb = pf->veb[i]; 9549 } 9550 if (n == 0 && veb && veb->uplink_seid != 0) 9551 i40e_veb_release(veb); 9552 9553 return 0; 9554 } 9555 9556 /** 9557 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI 9558 * @vsi: ptr to the VSI 9559 * 9560 * This should only be called after i40e_vsi_mem_alloc() which allocates the 9561 * corresponding SW VSI structure and initializes num_queue_pairs for the 9562 * newly allocated VSI. 9563 * 9564 * Returns 0 on success or negative on failure 9565 **/ 9566 static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) 9567 { 9568 int ret = -ENOENT; 9569 struct i40e_pf *pf = vsi->back; 9570 9571 if (vsi->q_vectors[0]) { 9572 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", 9573 vsi->seid); 9574 return -EEXIST; 9575 } 9576 9577 if (vsi->base_vector) { 9578 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", 9579 vsi->seid, vsi->base_vector); 9580 return -EEXIST; 9581 } 9582 9583 ret = i40e_vsi_alloc_q_vectors(vsi); 9584 if (ret) { 9585 dev_info(&pf->pdev->dev, 9586 "failed to allocate %d q_vector for VSI %d, ret=%d\n", 9587 vsi->num_q_vectors, vsi->seid, ret); 9588 vsi->num_q_vectors = 0; 9589 goto vector_setup_out; 9590 } 9591 9592 /* In Legacy mode, we do not have to get any other vector since we 9593 * piggyback on the misc/ICR0 for queue interrupts. 9594 */ 9595 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) 9596 return ret; 9597 if (vsi->num_q_vectors) 9598 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, 9599 vsi->num_q_vectors, vsi->idx); 9600 if (vsi->base_vector < 0) { 9601 dev_info(&pf->pdev->dev, 9602 "failed to get tracking for %d vectors for VSI %d, err=%d\n", 9603 vsi->num_q_vectors, vsi->seid, vsi->base_vector); 9604 i40e_vsi_free_q_vectors(vsi); 9605 ret = -ENOENT; 9606 goto vector_setup_out; 9607 } 9608 9609 vector_setup_out: 9610 return ret; 9611 } 9612 9613 /** 9614 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI 9615 * @vsi: pointer to the vsi. 9616 * 9617 * This re-allocates a vsi's queue resources. 9618 * 9619 * Returns pointer to the successfully allocated and configured VSI sw struct 9620 * on success, otherwise returns NULL on failure. 9621 **/ 9622 static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) 9623 { 9624 struct i40e_pf *pf; 9625 u8 enabled_tc; 9626 int ret; 9627 9628 if (!vsi) 9629 return NULL; 9630 9631 pf = vsi->back; 9632 9633 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); 9634 i40e_vsi_clear_rings(vsi); 9635 9636 i40e_vsi_free_arrays(vsi, false); 9637 i40e_set_num_rings_in_vsi(vsi); 9638 ret = i40e_vsi_alloc_arrays(vsi, false); 9639 if (ret) 9640 goto err_vsi; 9641 9642 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx); 9643 if (ret < 0) { 9644 dev_info(&pf->pdev->dev, 9645 "failed to get tracking for %d queues for VSI %d err %d\n", 9646 vsi->alloc_queue_pairs, vsi->seid, ret); 9647 goto err_vsi; 9648 } 9649 vsi->base_queue = ret; 9650 9651 /* Update the FW view of the VSI. Force a reset of TC and queue 9652 * layout configurations. 9653 */ 9654 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; 9655 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; 9656 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; 9657 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); 9658 if (vsi->type == I40E_VSI_MAIN) 9659 i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); 9660 9661 /* assign it some queues */ 9662 ret = i40e_alloc_rings(vsi); 9663 if (ret) 9664 goto err_rings; 9665 9666 /* map all of the rings to the q_vectors */ 9667 i40e_vsi_map_rings_to_vectors(vsi); 9668 return vsi; 9669 9670 err_rings: 9671 i40e_vsi_free_q_vectors(vsi); 9672 if (vsi->netdev_registered) { 9673 vsi->netdev_registered = false; 9674 unregister_netdev(vsi->netdev); 9675 free_netdev(vsi->netdev); 9676 vsi->netdev = NULL; 9677 } 9678 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); 9679 err_vsi: 9680 i40e_vsi_clear(vsi); 9681 return NULL; 9682 } 9683 9684 /** 9685 * i40e_vsi_setup - Set up a VSI by a given type 9686 * @pf: board private structure 9687 * @type: VSI type 9688 * @uplink_seid: the switch element to link to 9689 * @param1: usage depends upon VSI type. For VF types, indicates VF id 9690 * 9691 * This allocates the sw VSI structure and its queue resources, then add a VSI 9692 * to the identified VEB. 9693 * 9694 * Returns pointer to the successfully allocated and configure VSI sw struct on 9695 * success, otherwise returns NULL on failure. 9696 **/ 9697 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 9698 u16 uplink_seid, u32 param1) 9699 { 9700 struct i40e_vsi *vsi = NULL; 9701 struct i40e_veb *veb = NULL; 9702 int ret, i; 9703 int v_idx; 9704 9705 /* The requested uplink_seid must be either 9706 * - the PF's port seid 9707 * no VEB is needed because this is the PF 9708 * or this is a Flow Director special case VSI 9709 * - seid of an existing VEB 9710 * - seid of a VSI that owns an existing VEB 9711 * - seid of a VSI that doesn't own a VEB 9712 * a new VEB is created and the VSI becomes the owner 9713 * - seid of the PF VSI, which is what creates the first VEB 9714 * this is a special case of the previous 9715 * 9716 * Find which uplink_seid we were given and create a new VEB if needed 9717 */ 9718 for (i = 0; i < I40E_MAX_VEB; i++) { 9719 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { 9720 veb = pf->veb[i]; 9721 break; 9722 } 9723 } 9724 9725 if (!veb && uplink_seid != pf->mac_seid) { 9726 9727 for (i = 0; i < pf->num_alloc_vsi; i++) { 9728 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { 9729 vsi = pf->vsi[i]; 9730 break; 9731 } 9732 } 9733 if (!vsi) { 9734 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", 9735 uplink_seid); 9736 return NULL; 9737 } 9738 9739 if (vsi->uplink_seid == pf->mac_seid) 9740 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, 9741 vsi->tc_config.enabled_tc); 9742 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) 9743 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, 9744 vsi->tc_config.enabled_tc); 9745 if (veb) { 9746 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { 9747 dev_info(&vsi->back->pdev->dev, 9748 "New VSI creation error, uplink seid of LAN VSI expected.\n"); 9749 return NULL; 9750 } 9751 /* We come up by default in VEPA mode if SRIOV is not 9752 * already enabled, in which case we can't force VEPA 9753 * mode. 9754 */ 9755 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { 9756 veb->bridge_mode = BRIDGE_MODE_VEPA; 9757 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; 9758 } 9759 i40e_config_bridge_mode(veb); 9760 } 9761 for (i = 0; i < I40E_MAX_VEB && !veb; i++) { 9762 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) 9763 veb = pf->veb[i]; 9764 } 9765 if (!veb) { 9766 dev_info(&pf->pdev->dev, "couldn't add VEB\n"); 9767 return NULL; 9768 } 9769 9770 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; 9771 uplink_seid = veb->seid; 9772 } 9773 9774 /* get vsi sw struct */ 9775 v_idx = i40e_vsi_mem_alloc(pf, type); 9776 if (v_idx < 0) 9777 goto err_alloc; 9778 vsi = pf->vsi[v_idx]; 9779 if (!vsi) 9780 goto err_alloc; 9781 vsi->type = type; 9782 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); 9783 9784 if (type == I40E_VSI_MAIN) 9785 pf->lan_vsi = v_idx; 9786 else if (type == I40E_VSI_SRIOV) 9787 vsi->vf_id = param1; 9788 /* assign it some queues */ 9789 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, 9790 vsi->idx); 9791 if (ret < 0) { 9792 dev_info(&pf->pdev->dev, 9793 "failed to get tracking for %d queues for VSI %d err=%d\n", 9794 vsi->alloc_queue_pairs, vsi->seid, ret); 9795 goto err_vsi; 9796 } 9797 vsi->base_queue = ret; 9798 9799 /* get a VSI from the hardware */ 9800 vsi->uplink_seid = uplink_seid; 9801 ret = i40e_add_vsi(vsi); 9802 if (ret) 9803 goto err_vsi; 9804 9805 switch (vsi->type) { 9806 /* setup the netdev if needed */ 9807 case I40E_VSI_MAIN: 9808 /* Apply relevant filters if a platform-specific mac 9809 * address was selected. 9810 */ 9811 if (!!(pf->flags & I40E_FLAG_PF_MAC)) { 9812 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr); 9813 if (ret) { 9814 dev_warn(&pf->pdev->dev, 9815 "could not set up macaddr; err %d\n", 9816 ret); 9817 } 9818 } 9819 case I40E_VSI_VMDQ2: 9820 case I40E_VSI_FCOE: 9821 ret = i40e_config_netdev(vsi); 9822 if (ret) 9823 goto err_netdev; 9824 ret = register_netdev(vsi->netdev); 9825 if (ret) 9826 goto err_netdev; 9827 vsi->netdev_registered = true; 9828 netif_carrier_off(vsi->netdev); 9829 #ifdef CONFIG_I40E_DCB 9830 /* Setup DCB netlink interface */ 9831 i40e_dcbnl_setup(vsi); 9832 #endif /* CONFIG_I40E_DCB */ 9833 /* fall through */ 9834 9835 case I40E_VSI_FDIR: 9836 /* set up vectors and rings if needed */ 9837 ret = i40e_vsi_setup_vectors(vsi); 9838 if (ret) 9839 goto err_msix; 9840 9841 ret = i40e_alloc_rings(vsi); 9842 if (ret) 9843 goto err_rings; 9844 9845 /* map all of the rings to the q_vectors */ 9846 i40e_vsi_map_rings_to_vectors(vsi); 9847 9848 i40e_vsi_reset_stats(vsi); 9849 break; 9850 9851 default: 9852 /* no netdev or rings for the other VSI types */ 9853 break; 9854 } 9855 9856 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) && 9857 (vsi->type == I40E_VSI_VMDQ2)) { 9858 ret = i40e_vsi_config_rss(vsi); 9859 } 9860 return vsi; 9861 9862 err_rings: 9863 i40e_vsi_free_q_vectors(vsi); 9864 err_msix: 9865 if (vsi->netdev_registered) { 9866 vsi->netdev_registered = false; 9867 unregister_netdev(vsi->netdev); 9868 free_netdev(vsi->netdev); 9869 vsi->netdev = NULL; 9870 } 9871 err_netdev: 9872 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); 9873 err_vsi: 9874 i40e_vsi_clear(vsi); 9875 err_alloc: 9876 return NULL; 9877 } 9878 9879 /** 9880 * i40e_veb_get_bw_info - Query VEB BW information 9881 * @veb: the veb to query 9882 * 9883 * Query the Tx scheduler BW configuration data for given VEB 9884 **/ 9885 static int i40e_veb_get_bw_info(struct i40e_veb *veb) 9886 { 9887 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; 9888 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; 9889 struct i40e_pf *pf = veb->pf; 9890 struct i40e_hw *hw = &pf->hw; 9891 u32 tc_bw_max; 9892 int ret = 0; 9893 int i; 9894 9895 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, 9896 &bw_data, NULL); 9897 if (ret) { 9898 dev_info(&pf->pdev->dev, 9899 "query veb bw config failed, err %s aq_err %s\n", 9900 i40e_stat_str(&pf->hw, ret), 9901 i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); 9902 goto out; 9903 } 9904 9905 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, 9906 &ets_data, NULL); 9907 if (ret) { 9908 dev_info(&pf->pdev->dev, 9909 "query veb bw ets config failed, err %s aq_err %s\n", 9910 i40e_stat_str(&pf->hw, ret), 9911 i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); 9912 goto out; 9913 } 9914 9915 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); 9916 veb->bw_max_quanta = ets_data.tc_bw_max; 9917 veb->is_abs_credits = bw_data.absolute_credits_enable; 9918 veb->enabled_tc = ets_data.tc_valid_bits; 9919 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | 9920 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); 9921 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 9922 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; 9923 veb->bw_tc_limit_credits[i] = 9924 le16_to_cpu(bw_data.tc_bw_limits[i]); 9925 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); 9926 } 9927 9928 out: 9929 return ret; 9930 } 9931 9932 /** 9933 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF 9934 * @pf: board private structure 9935 * 9936 * On error: returns error code (negative) 9937 * On success: returns vsi index in PF (positive) 9938 **/ 9939 static int i40e_veb_mem_alloc(struct i40e_pf *pf) 9940 { 9941 int ret = -ENOENT; 9942 struct i40e_veb *veb; 9943 int i; 9944 9945 /* Need to protect the allocation of switch elements at the PF level */ 9946 mutex_lock(&pf->switch_mutex); 9947 9948 /* VEB list may be fragmented if VEB creation/destruction has 9949 * been happening. We can afford to do a quick scan to look 9950 * for any free slots in the list. 9951 * 9952 * find next empty veb slot, looping back around if necessary 9953 */ 9954 i = 0; 9955 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) 9956 i++; 9957 if (i >= I40E_MAX_VEB) { 9958 ret = -ENOMEM; 9959 goto err_alloc_veb; /* out of VEB slots! */ 9960 } 9961 9962 veb = kzalloc(sizeof(*veb), GFP_KERNEL); 9963 if (!veb) { 9964 ret = -ENOMEM; 9965 goto err_alloc_veb; 9966 } 9967 veb->pf = pf; 9968 veb->idx = i; 9969 veb->enabled_tc = 1; 9970 9971 pf->veb[i] = veb; 9972 ret = i; 9973 err_alloc_veb: 9974 mutex_unlock(&pf->switch_mutex); 9975 return ret; 9976 } 9977 9978 /** 9979 * i40e_switch_branch_release - Delete a branch of the switch tree 9980 * @branch: where to start deleting 9981 * 9982 * This uses recursion to find the tips of the branch to be 9983 * removed, deleting until we get back to and can delete this VEB. 9984 **/ 9985 static void i40e_switch_branch_release(struct i40e_veb *branch) 9986 { 9987 struct i40e_pf *pf = branch->pf; 9988 u16 branch_seid = branch->seid; 9989 u16 veb_idx = branch->idx; 9990 int i; 9991 9992 /* release any VEBs on this VEB - RECURSION */ 9993 for (i = 0; i < I40E_MAX_VEB; i++) { 9994 if (!pf->veb[i]) 9995 continue; 9996 if (pf->veb[i]->uplink_seid == branch->seid) 9997 i40e_switch_branch_release(pf->veb[i]); 9998 } 9999 10000 /* Release the VSIs on this VEB, but not the owner VSI. 10001 * 10002 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing 10003 * the VEB itself, so don't use (*branch) after this loop. 10004 */ 10005 for (i = 0; i < pf->num_alloc_vsi; i++) { 10006 if (!pf->vsi[i]) 10007 continue; 10008 if (pf->vsi[i]->uplink_seid == branch_seid && 10009 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { 10010 i40e_vsi_release(pf->vsi[i]); 10011 } 10012 } 10013 10014 /* There's one corner case where the VEB might not have been 10015 * removed, so double check it here and remove it if needed. 10016 * This case happens if the veb was created from the debugfs 10017 * commands and no VSIs were added to it. 10018 */ 10019 if (pf->veb[veb_idx]) 10020 i40e_veb_release(pf->veb[veb_idx]); 10021 } 10022 10023 /** 10024 * i40e_veb_clear - remove veb struct 10025 * @veb: the veb to remove 10026 **/ 10027 static void i40e_veb_clear(struct i40e_veb *veb) 10028 { 10029 if (!veb) 10030 return; 10031 10032 if (veb->pf) { 10033 struct i40e_pf *pf = veb->pf; 10034 10035 mutex_lock(&pf->switch_mutex); 10036 if (pf->veb[veb->idx] == veb) 10037 pf->veb[veb->idx] = NULL; 10038 mutex_unlock(&pf->switch_mutex); 10039 } 10040 10041 kfree(veb); 10042 } 10043 10044 /** 10045 * i40e_veb_release - Delete a VEB and free its resources 10046 * @veb: the VEB being removed 10047 **/ 10048 void i40e_veb_release(struct i40e_veb *veb) 10049 { 10050 struct i40e_vsi *vsi = NULL; 10051 struct i40e_pf *pf; 10052 int i, n = 0; 10053 10054 pf = veb->pf; 10055 10056 /* find the remaining VSI and check for extras */ 10057 for (i = 0; i < pf->num_alloc_vsi; i++) { 10058 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { 10059 n++; 10060 vsi = pf->vsi[i]; 10061 } 10062 } 10063 if (n != 1) { 10064 dev_info(&pf->pdev->dev, 10065 "can't remove VEB %d with %d VSIs left\n", 10066 veb->seid, n); 10067 return; 10068 } 10069 10070 /* move the remaining VSI to uplink veb */ 10071 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; 10072 if (veb->uplink_seid) { 10073 vsi->uplink_seid = veb->uplink_seid; 10074 if (veb->uplink_seid == pf->mac_seid) 10075 vsi->veb_idx = I40E_NO_VEB; 10076 else 10077 vsi->veb_idx = veb->veb_idx; 10078 } else { 10079 /* floating VEB */ 10080 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; 10081 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; 10082 } 10083 10084 i40e_aq_delete_element(&pf->hw, veb->seid, NULL); 10085 i40e_veb_clear(veb); 10086 } 10087 10088 /** 10089 * i40e_add_veb - create the VEB in the switch 10090 * @veb: the VEB to be instantiated 10091 * @vsi: the controlling VSI 10092 **/ 10093 static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) 10094 { 10095 struct i40e_pf *pf = veb->pf; 10096 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); 10097 int ret; 10098 10099 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, 10100 veb->enabled_tc, false, 10101 &veb->seid, enable_stats, NULL); 10102 10103 /* get a VEB from the hardware */ 10104 if (ret) { 10105 dev_info(&pf->pdev->dev, 10106 "couldn't add VEB, err %s aq_err %s\n", 10107 i40e_stat_str(&pf->hw, ret), 10108 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10109 return -EPERM; 10110 } 10111 10112 /* get statistics counter */ 10113 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, 10114 &veb->stats_idx, NULL, NULL, NULL); 10115 if (ret) { 10116 dev_info(&pf->pdev->dev, 10117 "couldn't get VEB statistics idx, err %s aq_err %s\n", 10118 i40e_stat_str(&pf->hw, ret), 10119 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10120 return -EPERM; 10121 } 10122 ret = i40e_veb_get_bw_info(veb); 10123 if (ret) { 10124 dev_info(&pf->pdev->dev, 10125 "couldn't get VEB bw info, err %s aq_err %s\n", 10126 i40e_stat_str(&pf->hw, ret), 10127 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10128 i40e_aq_delete_element(&pf->hw, veb->seid, NULL); 10129 return -ENOENT; 10130 } 10131 10132 vsi->uplink_seid = veb->seid; 10133 vsi->veb_idx = veb->idx; 10134 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; 10135 10136 return 0; 10137 } 10138 10139 /** 10140 * i40e_veb_setup - Set up a VEB 10141 * @pf: board private structure 10142 * @flags: VEB setup flags 10143 * @uplink_seid: the switch element to link to 10144 * @vsi_seid: the initial VSI seid 10145 * @enabled_tc: Enabled TC bit-map 10146 * 10147 * This allocates the sw VEB structure and links it into the switch 10148 * It is possible and legal for this to be a duplicate of an already 10149 * existing VEB. It is also possible for both uplink and vsi seids 10150 * to be zero, in order to create a floating VEB. 10151 * 10152 * Returns pointer to the successfully allocated VEB sw struct on 10153 * success, otherwise returns NULL on failure. 10154 **/ 10155 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, 10156 u16 uplink_seid, u16 vsi_seid, 10157 u8 enabled_tc) 10158 { 10159 struct i40e_veb *veb, *uplink_veb = NULL; 10160 int vsi_idx, veb_idx; 10161 int ret; 10162 10163 /* if one seid is 0, the other must be 0 to create a floating relay */ 10164 if ((uplink_seid == 0 || vsi_seid == 0) && 10165 (uplink_seid + vsi_seid != 0)) { 10166 dev_info(&pf->pdev->dev, 10167 "one, not both seid's are 0: uplink=%d vsi=%d\n", 10168 uplink_seid, vsi_seid); 10169 return NULL; 10170 } 10171 10172 /* make sure there is such a vsi and uplink */ 10173 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) 10174 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) 10175 break; 10176 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) { 10177 dev_info(&pf->pdev->dev, "vsi seid %d not found\n", 10178 vsi_seid); 10179 return NULL; 10180 } 10181 10182 if (uplink_seid && uplink_seid != pf->mac_seid) { 10183 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { 10184 if (pf->veb[veb_idx] && 10185 pf->veb[veb_idx]->seid == uplink_seid) { 10186 uplink_veb = pf->veb[veb_idx]; 10187 break; 10188 } 10189 } 10190 if (!uplink_veb) { 10191 dev_info(&pf->pdev->dev, 10192 "uplink seid %d not found\n", uplink_seid); 10193 return NULL; 10194 } 10195 } 10196 10197 /* get veb sw struct */ 10198 veb_idx = i40e_veb_mem_alloc(pf); 10199 if (veb_idx < 0) 10200 goto err_alloc; 10201 veb = pf->veb[veb_idx]; 10202 veb->flags = flags; 10203 veb->uplink_seid = uplink_seid; 10204 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); 10205 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); 10206 10207 /* create the VEB in the switch */ 10208 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); 10209 if (ret) 10210 goto err_veb; 10211 if (vsi_idx == pf->lan_vsi) 10212 pf->lan_veb = veb->idx; 10213 10214 return veb; 10215 10216 err_veb: 10217 i40e_veb_clear(veb); 10218 err_alloc: 10219 return NULL; 10220 } 10221 10222 /** 10223 * i40e_setup_pf_switch_element - set PF vars based on switch type 10224 * @pf: board private structure 10225 * @ele: element we are building info from 10226 * @num_reported: total number of elements 10227 * @printconfig: should we print the contents 10228 * 10229 * helper function to assist in extracting a few useful SEID values. 10230 **/ 10231 static void i40e_setup_pf_switch_element(struct i40e_pf *pf, 10232 struct i40e_aqc_switch_config_element_resp *ele, 10233 u16 num_reported, bool printconfig) 10234 { 10235 u16 downlink_seid = le16_to_cpu(ele->downlink_seid); 10236 u16 uplink_seid = le16_to_cpu(ele->uplink_seid); 10237 u8 element_type = ele->element_type; 10238 u16 seid = le16_to_cpu(ele->seid); 10239 10240 if (printconfig) 10241 dev_info(&pf->pdev->dev, 10242 "type=%d seid=%d uplink=%d downlink=%d\n", 10243 element_type, seid, uplink_seid, downlink_seid); 10244 10245 switch (element_type) { 10246 case I40E_SWITCH_ELEMENT_TYPE_MAC: 10247 pf->mac_seid = seid; 10248 break; 10249 case I40E_SWITCH_ELEMENT_TYPE_VEB: 10250 /* Main VEB? */ 10251 if (uplink_seid != pf->mac_seid) 10252 break; 10253 if (pf->lan_veb == I40E_NO_VEB) { 10254 int v; 10255 10256 /* find existing or else empty VEB */ 10257 for (v = 0; v < I40E_MAX_VEB; v++) { 10258 if (pf->veb[v] && (pf->veb[v]->seid == seid)) { 10259 pf->lan_veb = v; 10260 break; 10261 } 10262 } 10263 if (pf->lan_veb == I40E_NO_VEB) { 10264 v = i40e_veb_mem_alloc(pf); 10265 if (v < 0) 10266 break; 10267 pf->lan_veb = v; 10268 } 10269 } 10270 10271 pf->veb[pf->lan_veb]->seid = seid; 10272 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; 10273 pf->veb[pf->lan_veb]->pf = pf; 10274 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; 10275 break; 10276 case I40E_SWITCH_ELEMENT_TYPE_VSI: 10277 if (num_reported != 1) 10278 break; 10279 /* This is immediately after a reset so we can assume this is 10280 * the PF's VSI 10281 */ 10282 pf->mac_seid = uplink_seid; 10283 pf->pf_seid = downlink_seid; 10284 pf->main_vsi_seid = seid; 10285 if (printconfig) 10286 dev_info(&pf->pdev->dev, 10287 "pf_seid=%d main_vsi_seid=%d\n", 10288 pf->pf_seid, pf->main_vsi_seid); 10289 break; 10290 case I40E_SWITCH_ELEMENT_TYPE_PF: 10291 case I40E_SWITCH_ELEMENT_TYPE_VF: 10292 case I40E_SWITCH_ELEMENT_TYPE_EMP: 10293 case I40E_SWITCH_ELEMENT_TYPE_BMC: 10294 case I40E_SWITCH_ELEMENT_TYPE_PE: 10295 case I40E_SWITCH_ELEMENT_TYPE_PA: 10296 /* ignore these for now */ 10297 break; 10298 default: 10299 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", 10300 element_type, seid); 10301 break; 10302 } 10303 } 10304 10305 /** 10306 * i40e_fetch_switch_configuration - Get switch config from firmware 10307 * @pf: board private structure 10308 * @printconfig: should we print the contents 10309 * 10310 * Get the current switch configuration from the device and 10311 * extract a few useful SEID values. 10312 **/ 10313 int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) 10314 { 10315 struct i40e_aqc_get_switch_config_resp *sw_config; 10316 u16 next_seid = 0; 10317 int ret = 0; 10318 u8 *aq_buf; 10319 int i; 10320 10321 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); 10322 if (!aq_buf) 10323 return -ENOMEM; 10324 10325 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 10326 do { 10327 u16 num_reported, num_total; 10328 10329 ret = i40e_aq_get_switch_config(&pf->hw, sw_config, 10330 I40E_AQ_LARGE_BUF, 10331 &next_seid, NULL); 10332 if (ret) { 10333 dev_info(&pf->pdev->dev, 10334 "get switch config failed err %s aq_err %s\n", 10335 i40e_stat_str(&pf->hw, ret), 10336 i40e_aq_str(&pf->hw, 10337 pf->hw.aq.asq_last_status)); 10338 kfree(aq_buf); 10339 return -ENOENT; 10340 } 10341 10342 num_reported = le16_to_cpu(sw_config->header.num_reported); 10343 num_total = le16_to_cpu(sw_config->header.num_total); 10344 10345 if (printconfig) 10346 dev_info(&pf->pdev->dev, 10347 "header: %d reported %d total\n", 10348 num_reported, num_total); 10349 10350 for (i = 0; i < num_reported; i++) { 10351 struct i40e_aqc_switch_config_element_resp *ele = 10352 &sw_config->element[i]; 10353 10354 i40e_setup_pf_switch_element(pf, ele, num_reported, 10355 printconfig); 10356 } 10357 } while (next_seid != 0); 10358 10359 kfree(aq_buf); 10360 return ret; 10361 } 10362 10363 /** 10364 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset 10365 * @pf: board private structure 10366 * @reinit: if the Main VSI needs to re-initialized. 10367 * 10368 * Returns 0 on success, negative value on failure 10369 **/ 10370 static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) 10371 { 10372 u16 flags = 0; 10373 int ret; 10374 10375 /* find out what's out there already */ 10376 ret = i40e_fetch_switch_configuration(pf, false); 10377 if (ret) { 10378 dev_info(&pf->pdev->dev, 10379 "couldn't fetch switch config, err %s aq_err %s\n", 10380 i40e_stat_str(&pf->hw, ret), 10381 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 10382 return ret; 10383 } 10384 i40e_pf_reset_stats(pf); 10385 10386 /* set the switch config bit for the whole device to 10387 * support limited promisc or true promisc 10388 * when user requests promisc. The default is limited 10389 * promisc. 10390 */ 10391 10392 if ((pf->hw.pf_id == 0) && 10393 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) 10394 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; 10395 10396 if (pf->hw.pf_id == 0) { 10397 u16 valid_flags; 10398 10399 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; 10400 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 10401 NULL); 10402 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { 10403 dev_info(&pf->pdev->dev, 10404 "couldn't set switch config bits, err %s aq_err %s\n", 10405 i40e_stat_str(&pf->hw, ret), 10406 i40e_aq_str(&pf->hw, 10407 pf->hw.aq.asq_last_status)); 10408 /* not a fatal problem, just keep going */ 10409 } 10410 } 10411 10412 /* first time setup */ 10413 if (pf->lan_vsi == I40E_NO_VSI || reinit) { 10414 struct i40e_vsi *vsi = NULL; 10415 u16 uplink_seid; 10416 10417 /* Set up the PF VSI associated with the PF's main VSI 10418 * that is already in the HW switch 10419 */ 10420 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) 10421 uplink_seid = pf->veb[pf->lan_veb]->seid; 10422 else 10423 uplink_seid = pf->mac_seid; 10424 if (pf->lan_vsi == I40E_NO_VSI) 10425 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); 10426 else if (reinit) 10427 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); 10428 if (!vsi) { 10429 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); 10430 i40e_fdir_teardown(pf); 10431 return -EAGAIN; 10432 } 10433 } else { 10434 /* force a reset of TC and queue layout configurations */ 10435 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; 10436 10437 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; 10438 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; 10439 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); 10440 } 10441 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); 10442 10443 i40e_fdir_sb_setup(pf); 10444 10445 /* Setup static PF queue filter control settings */ 10446 ret = i40e_setup_pf_filter_control(pf); 10447 if (ret) { 10448 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", 10449 ret); 10450 /* Failure here should not stop continuing other steps */ 10451 } 10452 10453 /* enable RSS in the HW, even for only one queue, as the stack can use 10454 * the hash 10455 */ 10456 if ((pf->flags & I40E_FLAG_RSS_ENABLED)) 10457 i40e_pf_config_rss(pf); 10458 10459 /* fill in link information and enable LSE reporting */ 10460 i40e_update_link_info(&pf->hw); 10461 i40e_link_event(pf); 10462 10463 /* Initialize user-specific link properties */ 10464 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & 10465 I40E_AQ_AN_COMPLETED) ? true : false); 10466 10467 i40e_ptp_init(pf); 10468 10469 return ret; 10470 } 10471 10472 /** 10473 * i40e_determine_queue_usage - Work out queue distribution 10474 * @pf: board private structure 10475 **/ 10476 static void i40e_determine_queue_usage(struct i40e_pf *pf) 10477 { 10478 int queues_left; 10479 10480 pf->num_lan_qps = 0; 10481 #ifdef I40E_FCOE 10482 pf->num_fcoe_qps = 0; 10483 #endif 10484 10485 /* Find the max queues to be put into basic use. We'll always be 10486 * using TC0, whether or not DCB is running, and TC0 will get the 10487 * big RSS set. 10488 */ 10489 queues_left = pf->hw.func_caps.num_tx_qp; 10490 10491 if ((queues_left == 1) || 10492 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { 10493 /* one qp for PF, no queues for anything else */ 10494 queues_left = 0; 10495 pf->alloc_rss_size = pf->num_lan_qps = 1; 10496 10497 /* make sure all the fancies are disabled */ 10498 pf->flags &= ~(I40E_FLAG_RSS_ENABLED | 10499 I40E_FLAG_IWARP_ENABLED | 10500 #ifdef I40E_FCOE 10501 I40E_FLAG_FCOE_ENABLED | 10502 #endif 10503 I40E_FLAG_FD_SB_ENABLED | 10504 I40E_FLAG_FD_ATR_ENABLED | 10505 I40E_FLAG_DCB_CAPABLE | 10506 I40E_FLAG_SRIOV_ENABLED | 10507 I40E_FLAG_VMDQ_ENABLED); 10508 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | 10509 I40E_FLAG_FD_SB_ENABLED | 10510 I40E_FLAG_FD_ATR_ENABLED | 10511 I40E_FLAG_DCB_CAPABLE))) { 10512 /* one qp for PF */ 10513 pf->alloc_rss_size = pf->num_lan_qps = 1; 10514 queues_left -= pf->num_lan_qps; 10515 10516 pf->flags &= ~(I40E_FLAG_RSS_ENABLED | 10517 I40E_FLAG_IWARP_ENABLED | 10518 #ifdef I40E_FCOE 10519 I40E_FLAG_FCOE_ENABLED | 10520 #endif 10521 I40E_FLAG_FD_SB_ENABLED | 10522 I40E_FLAG_FD_ATR_ENABLED | 10523 I40E_FLAG_DCB_ENABLED | 10524 I40E_FLAG_VMDQ_ENABLED); 10525 } else { 10526 /* Not enough queues for all TCs */ 10527 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && 10528 (queues_left < I40E_MAX_TRAFFIC_CLASS)) { 10529 pf->flags &= ~I40E_FLAG_DCB_CAPABLE; 10530 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); 10531 } 10532 pf->num_lan_qps = max_t(int, pf->rss_size_max, 10533 num_online_cpus()); 10534 pf->num_lan_qps = min_t(int, pf->num_lan_qps, 10535 pf->hw.func_caps.num_tx_qp); 10536 10537 queues_left -= pf->num_lan_qps; 10538 } 10539 10540 #ifdef I40E_FCOE 10541 if (pf->flags & I40E_FLAG_FCOE_ENABLED) { 10542 if (I40E_DEFAULT_FCOE <= queues_left) { 10543 pf->num_fcoe_qps = I40E_DEFAULT_FCOE; 10544 } else if (I40E_MINIMUM_FCOE <= queues_left) { 10545 pf->num_fcoe_qps = I40E_MINIMUM_FCOE; 10546 } else { 10547 pf->num_fcoe_qps = 0; 10548 pf->flags &= ~I40E_FLAG_FCOE_ENABLED; 10549 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n"); 10550 } 10551 10552 queues_left -= pf->num_fcoe_qps; 10553 } 10554 10555 #endif 10556 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { 10557 if (queues_left > 1) { 10558 queues_left -= 1; /* save 1 queue for FD */ 10559 } else { 10560 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; 10561 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); 10562 } 10563 } 10564 10565 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && 10566 pf->num_vf_qps && pf->num_req_vfs && queues_left) { 10567 pf->num_req_vfs = min_t(int, pf->num_req_vfs, 10568 (queues_left / pf->num_vf_qps)); 10569 queues_left -= (pf->num_req_vfs * pf->num_vf_qps); 10570 } 10571 10572 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && 10573 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { 10574 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, 10575 (queues_left / pf->num_vmdq_qps)); 10576 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); 10577 } 10578 10579 pf->queues_left = queues_left; 10580 dev_dbg(&pf->pdev->dev, 10581 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", 10582 pf->hw.func_caps.num_tx_qp, 10583 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), 10584 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, 10585 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, 10586 queues_left); 10587 #ifdef I40E_FCOE 10588 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps); 10589 #endif 10590 } 10591 10592 /** 10593 * i40e_setup_pf_filter_control - Setup PF static filter control 10594 * @pf: PF to be setup 10595 * 10596 * i40e_setup_pf_filter_control sets up a PF's initial filter control 10597 * settings. If PE/FCoE are enabled then it will also set the per PF 10598 * based filter sizes required for them. It also enables Flow director, 10599 * ethertype and macvlan type filter settings for the pf. 10600 * 10601 * Returns 0 on success, negative on failure 10602 **/ 10603 static int i40e_setup_pf_filter_control(struct i40e_pf *pf) 10604 { 10605 struct i40e_filter_control_settings *settings = &pf->filter_settings; 10606 10607 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; 10608 10609 /* Flow Director is enabled */ 10610 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) 10611 settings->enable_fdir = true; 10612 10613 /* Ethtype and MACVLAN filters enabled for PF */ 10614 settings->enable_ethtype = true; 10615 settings->enable_macvlan = true; 10616 10617 if (i40e_set_filter_control(&pf->hw, settings)) 10618 return -ENOENT; 10619 10620 return 0; 10621 } 10622 10623 #define INFO_STRING_LEN 255 10624 #define REMAIN(__x) (INFO_STRING_LEN - (__x)) 10625 static void i40e_print_features(struct i40e_pf *pf) 10626 { 10627 struct i40e_hw *hw = &pf->hw; 10628 char *buf; 10629 int i; 10630 10631 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); 10632 if (!buf) 10633 return; 10634 10635 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); 10636 #ifdef CONFIG_PCI_IOV 10637 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); 10638 #endif 10639 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", 10640 pf->hw.func_caps.num_vsis, 10641 pf->vsi[pf->lan_vsi]->num_queue_pairs); 10642 if (pf->flags & I40E_FLAG_RSS_ENABLED) 10643 i += snprintf(&buf[i], REMAIN(i), " RSS"); 10644 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) 10645 i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); 10646 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { 10647 i += snprintf(&buf[i], REMAIN(i), " FD_SB"); 10648 i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); 10649 } 10650 if (pf->flags & I40E_FLAG_DCB_CAPABLE) 10651 i += snprintf(&buf[i], REMAIN(i), " DCB"); 10652 i += snprintf(&buf[i], REMAIN(i), " VxLAN"); 10653 i += snprintf(&buf[i], REMAIN(i), " Geneve"); 10654 if (pf->flags & I40E_FLAG_PTP) 10655 i += snprintf(&buf[i], REMAIN(i), " PTP"); 10656 #ifdef I40E_FCOE 10657 if (pf->flags & I40E_FLAG_FCOE_ENABLED) 10658 i += snprintf(&buf[i], REMAIN(i), " FCOE"); 10659 #endif 10660 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) 10661 i += snprintf(&buf[i], REMAIN(i), " VEB"); 10662 else 10663 i += snprintf(&buf[i], REMAIN(i), " VEPA"); 10664 10665 dev_info(&pf->pdev->dev, "%s\n", buf); 10666 kfree(buf); 10667 WARN_ON(i > INFO_STRING_LEN); 10668 } 10669 10670 /** 10671 * i40e_get_platform_mac_addr - get platform-specific MAC address 10672 * 10673 * @pdev: PCI device information struct 10674 * @pf: board private structure 10675 * 10676 * Look up the MAC address in Open Firmware on systems that support it, 10677 * and use IDPROM on SPARC if no OF address is found. On return, the 10678 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value 10679 * has been selected. 10680 **/ 10681 static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) 10682 { 10683 pf->flags &= ~I40E_FLAG_PF_MAC; 10684 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) 10685 pf->flags |= I40E_FLAG_PF_MAC; 10686 } 10687 10688 /** 10689 * i40e_probe - Device initialization routine 10690 * @pdev: PCI device information struct 10691 * @ent: entry in i40e_pci_tbl 10692 * 10693 * i40e_probe initializes a PF identified by a pci_dev structure. 10694 * The OS initialization, configuring of the PF private structure, 10695 * and a hardware reset occur. 10696 * 10697 * Returns 0 on success, negative on failure 10698 **/ 10699 static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10700 { 10701 struct i40e_aq_get_phy_abilities_resp abilities; 10702 struct i40e_pf *pf; 10703 struct i40e_hw *hw; 10704 static u16 pfs_found; 10705 u16 wol_nvm_bits; 10706 u16 link_status; 10707 int err; 10708 u32 val; 10709 u32 i; 10710 u8 set_fc_aq_fail; 10711 10712 err = pci_enable_device_mem(pdev); 10713 if (err) 10714 return err; 10715 10716 /* set up for high or low dma */ 10717 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 10718 if (err) { 10719 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 10720 if (err) { 10721 dev_err(&pdev->dev, 10722 "DMA configuration failed: 0x%x\n", err); 10723 goto err_dma; 10724 } 10725 } 10726 10727 /* set up pci connections */ 10728 err = pci_request_mem_regions(pdev, i40e_driver_name); 10729 if (err) { 10730 dev_info(&pdev->dev, 10731 "pci_request_selected_regions failed %d\n", err); 10732 goto err_pci_reg; 10733 } 10734 10735 pci_enable_pcie_error_reporting(pdev); 10736 pci_set_master(pdev); 10737 10738 /* Now that we have a PCI connection, we need to do the 10739 * low level device setup. This is primarily setting up 10740 * the Admin Queue structures and then querying for the 10741 * device's current profile information. 10742 */ 10743 pf = kzalloc(sizeof(*pf), GFP_KERNEL); 10744 if (!pf) { 10745 err = -ENOMEM; 10746 goto err_pf_alloc; 10747 } 10748 pf->next_vsi = 0; 10749 pf->pdev = pdev; 10750 set_bit(__I40E_DOWN, &pf->state); 10751 10752 hw = &pf->hw; 10753 hw->back = pf; 10754 10755 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), 10756 I40E_MAX_CSR_SPACE); 10757 10758 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); 10759 if (!hw->hw_addr) { 10760 err = -EIO; 10761 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", 10762 (unsigned int)pci_resource_start(pdev, 0), 10763 pf->ioremap_len, err); 10764 goto err_ioremap; 10765 } 10766 hw->vendor_id = pdev->vendor; 10767 hw->device_id = pdev->device; 10768 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); 10769 hw->subsystem_vendor_id = pdev->subsystem_vendor; 10770 hw->subsystem_device_id = pdev->subsystem_device; 10771 hw->bus.device = PCI_SLOT(pdev->devfn); 10772 hw->bus.func = PCI_FUNC(pdev->devfn); 10773 pf->instance = pfs_found; 10774 10775 /* set up the locks for the AQ, do this only once in probe 10776 * and destroy them only once in remove 10777 */ 10778 mutex_init(&hw->aq.asq_mutex); 10779 mutex_init(&hw->aq.arq_mutex); 10780 10781 if (debug != -1) { 10782 pf->msg_enable = pf->hw.debug_mask; 10783 pf->msg_enable = debug; 10784 } 10785 10786 /* do a special CORER for clearing PXE mode once at init */ 10787 if (hw->revision_id == 0 && 10788 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { 10789 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); 10790 i40e_flush(hw); 10791 msleep(200); 10792 pf->corer_count++; 10793 10794 i40e_clear_pxe_mode(hw); 10795 } 10796 10797 /* Reset here to make sure all is clean and to define PF 'n' */ 10798 i40e_clear_hw(hw); 10799 err = i40e_pf_reset(hw); 10800 if (err) { 10801 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); 10802 goto err_pf_reset; 10803 } 10804 pf->pfr_count++; 10805 10806 hw->aq.num_arq_entries = I40E_AQ_LEN; 10807 hw->aq.num_asq_entries = I40E_AQ_LEN; 10808 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; 10809 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; 10810 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; 10811 10812 snprintf(pf->int_name, sizeof(pf->int_name) - 1, 10813 "%s-%s:misc", 10814 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); 10815 10816 err = i40e_init_shared_code(hw); 10817 if (err) { 10818 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", 10819 err); 10820 goto err_pf_reset; 10821 } 10822 10823 /* set up a default setting for link flow control */ 10824 pf->hw.fc.requested_mode = I40E_FC_NONE; 10825 10826 err = i40e_init_adminq(hw); 10827 if (err) { 10828 if (err == I40E_ERR_FIRMWARE_API_VERSION) 10829 dev_info(&pdev->dev, 10830 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); 10831 else 10832 dev_info(&pdev->dev, 10833 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); 10834 10835 goto err_pf_reset; 10836 } 10837 10838 /* provide nvm, fw, api versions */ 10839 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n", 10840 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, 10841 hw->aq.api_maj_ver, hw->aq.api_min_ver, 10842 i40e_nvm_version_str(hw)); 10843 10844 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 10845 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 10846 dev_info(&pdev->dev, 10847 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); 10848 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 10849 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 10850 dev_info(&pdev->dev, 10851 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); 10852 10853 i40e_verify_eeprom(pf); 10854 10855 /* Rev 0 hardware was never productized */ 10856 if (hw->revision_id < 1) 10857 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); 10858 10859 i40e_clear_pxe_mode(hw); 10860 err = i40e_get_capabilities(pf); 10861 if (err) 10862 goto err_adminq_setup; 10863 10864 err = i40e_sw_init(pf); 10865 if (err) { 10866 dev_info(&pdev->dev, "sw_init failed: %d\n", err); 10867 goto err_sw_init; 10868 } 10869 10870 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 10871 hw->func_caps.num_rx_qp, 10872 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num); 10873 if (err) { 10874 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); 10875 goto err_init_lan_hmc; 10876 } 10877 10878 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 10879 if (err) { 10880 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); 10881 err = -ENOENT; 10882 goto err_configure_lan_hmc; 10883 } 10884 10885 /* Disable LLDP for NICs that have firmware versions lower than v4.3. 10886 * Ignore error return codes because if it was already disabled via 10887 * hardware settings this will fail 10888 */ 10889 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) { 10890 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); 10891 i40e_aq_stop_lldp(hw, true, NULL); 10892 } 10893 10894 i40e_get_mac_addr(hw, hw->mac.addr); 10895 /* allow a platform config to override the HW addr */ 10896 i40e_get_platform_mac_addr(pdev, pf); 10897 if (!is_valid_ether_addr(hw->mac.addr)) { 10898 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); 10899 err = -EIO; 10900 goto err_mac_addr; 10901 } 10902 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); 10903 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); 10904 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 10905 if (is_valid_ether_addr(hw->mac.port_addr)) 10906 pf->flags |= I40E_FLAG_PORT_ID_VALID; 10907 #ifdef I40E_FCOE 10908 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr); 10909 if (err) 10910 dev_info(&pdev->dev, 10911 "(non-fatal) SAN MAC retrieval failed: %d\n", err); 10912 if (!is_valid_ether_addr(hw->mac.san_addr)) { 10913 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n", 10914 hw->mac.san_addr); 10915 ether_addr_copy(hw->mac.san_addr, hw->mac.addr); 10916 } 10917 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr); 10918 #endif /* I40E_FCOE */ 10919 10920 pci_set_drvdata(pdev, pf); 10921 pci_save_state(pdev); 10922 #ifdef CONFIG_I40E_DCB 10923 err = i40e_init_pf_dcb(pf); 10924 if (err) { 10925 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); 10926 pf->flags &= ~I40E_FLAG_DCB_CAPABLE; 10927 /* Continue without DCB enabled */ 10928 } 10929 #endif /* CONFIG_I40E_DCB */ 10930 10931 /* set up periodic task facility */ 10932 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf); 10933 pf->service_timer_period = HZ; 10934 10935 INIT_WORK(&pf->service_task, i40e_service_task); 10936 clear_bit(__I40E_SERVICE_SCHED, &pf->state); 10937 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE; 10938 10939 /* NVM bit on means WoL disabled for the port */ 10940 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); 10941 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) 10942 pf->wol_en = false; 10943 else 10944 pf->wol_en = true; 10945 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); 10946 10947 /* set up the main switch operations */ 10948 i40e_determine_queue_usage(pf); 10949 err = i40e_init_interrupt_scheme(pf); 10950 if (err) 10951 goto err_switch_setup; 10952 10953 /* The number of VSIs reported by the FW is the minimum guaranteed 10954 * to us; HW supports far more and we share the remaining pool with 10955 * the other PFs. We allocate space for more than the guarantee with 10956 * the understanding that we might not get them all later. 10957 */ 10958 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) 10959 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; 10960 else 10961 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; 10962 10963 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ 10964 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), 10965 GFP_KERNEL); 10966 if (!pf->vsi) { 10967 err = -ENOMEM; 10968 goto err_switch_setup; 10969 } 10970 10971 #ifdef CONFIG_PCI_IOV 10972 /* prep for VF support */ 10973 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && 10974 (pf->flags & I40E_FLAG_MSIX_ENABLED) && 10975 !test_bit(__I40E_BAD_EEPROM, &pf->state)) { 10976 if (pci_num_vf(pdev)) 10977 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; 10978 } 10979 #endif 10980 err = i40e_setup_pf_switch(pf, false); 10981 if (err) { 10982 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); 10983 goto err_vsis; 10984 } 10985 10986 /* Make sure flow control is set according to current settings */ 10987 err = i40e_set_fc(hw, &set_fc_aq_fail, true); 10988 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) 10989 dev_dbg(&pf->pdev->dev, 10990 "Set fc with err %s aq_err %s on get_phy_cap\n", 10991 i40e_stat_str(hw, err), 10992 i40e_aq_str(hw, hw->aq.asq_last_status)); 10993 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) 10994 dev_dbg(&pf->pdev->dev, 10995 "Set fc with err %s aq_err %s on set_phy_config\n", 10996 i40e_stat_str(hw, err), 10997 i40e_aq_str(hw, hw->aq.asq_last_status)); 10998 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) 10999 dev_dbg(&pf->pdev->dev, 11000 "Set fc with err %s aq_err %s on get_link_info\n", 11001 i40e_stat_str(hw, err), 11002 i40e_aq_str(hw, hw->aq.asq_last_status)); 11003 11004 /* if FDIR VSI was set up, start it now */ 11005 for (i = 0; i < pf->num_alloc_vsi; i++) { 11006 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { 11007 i40e_vsi_open(pf->vsi[i]); 11008 break; 11009 } 11010 } 11011 11012 /* The driver only wants link up/down and module qualification 11013 * reports from firmware. Note the negative logic. 11014 */ 11015 err = i40e_aq_set_phy_int_mask(&pf->hw, 11016 ~(I40E_AQ_EVENT_LINK_UPDOWN | 11017 I40E_AQ_EVENT_MEDIA_NA | 11018 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); 11019 if (err) 11020 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", 11021 i40e_stat_str(&pf->hw, err), 11022 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 11023 11024 /* Reconfigure hardware for allowing smaller MSS in the case 11025 * of TSO, so that we avoid the MDD being fired and causing 11026 * a reset in the case of small MSS+TSO. 11027 */ 11028 val = rd32(hw, I40E_REG_MSS); 11029 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { 11030 val &= ~I40E_REG_MSS_MIN_MASK; 11031 val |= I40E_64BYTE_MSS; 11032 wr32(hw, I40E_REG_MSS, val); 11033 } 11034 11035 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) { 11036 msleep(75); 11037 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); 11038 if (err) 11039 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", 11040 i40e_stat_str(&pf->hw, err), 11041 i40e_aq_str(&pf->hw, 11042 pf->hw.aq.asq_last_status)); 11043 } 11044 /* The main driver is (mostly) up and happy. We need to set this state 11045 * before setting up the misc vector or we get a race and the vector 11046 * ends up disabled forever. 11047 */ 11048 clear_bit(__I40E_DOWN, &pf->state); 11049 11050 /* In case of MSIX we are going to setup the misc vector right here 11051 * to handle admin queue events etc. In case of legacy and MSI 11052 * the misc functionality and queue processing is combined in 11053 * the same vector and that gets setup at open. 11054 */ 11055 if (pf->flags & I40E_FLAG_MSIX_ENABLED) { 11056 err = i40e_setup_misc_vector(pf); 11057 if (err) { 11058 dev_info(&pdev->dev, 11059 "setup of misc vector failed: %d\n", err); 11060 goto err_vsis; 11061 } 11062 } 11063 11064 #ifdef CONFIG_PCI_IOV 11065 /* prep for VF support */ 11066 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && 11067 (pf->flags & I40E_FLAG_MSIX_ENABLED) && 11068 !test_bit(__I40E_BAD_EEPROM, &pf->state)) { 11069 /* disable link interrupts for VFs */ 11070 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); 11071 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; 11072 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); 11073 i40e_flush(hw); 11074 11075 if (pci_num_vf(pdev)) { 11076 dev_info(&pdev->dev, 11077 "Active VFs found, allocating resources.\n"); 11078 err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); 11079 if (err) 11080 dev_info(&pdev->dev, 11081 "Error %d allocating resources for existing VFs\n", 11082 err); 11083 } 11084 } 11085 #endif /* CONFIG_PCI_IOV */ 11086 11087 if (pf->flags & I40E_FLAG_IWARP_ENABLED) { 11088 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, 11089 pf->num_iwarp_msix, 11090 I40E_IWARP_IRQ_PILE_ID); 11091 if (pf->iwarp_base_vector < 0) { 11092 dev_info(&pdev->dev, 11093 "failed to get tracking for %d vectors for IWARP err=%d\n", 11094 pf->num_iwarp_msix, pf->iwarp_base_vector); 11095 pf->flags &= ~I40E_FLAG_IWARP_ENABLED; 11096 } 11097 } 11098 11099 i40e_dbg_pf_init(pf); 11100 11101 /* tell the firmware that we're starting */ 11102 i40e_send_version(pf); 11103 11104 /* since everything's happy, start the service_task timer */ 11105 mod_timer(&pf->service_timer, 11106 round_jiffies(jiffies + pf->service_timer_period)); 11107 11108 /* add this PF to client device list and launch a client service task */ 11109 err = i40e_lan_add_device(pf); 11110 if (err) 11111 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", 11112 err); 11113 11114 #ifdef I40E_FCOE 11115 /* create FCoE interface */ 11116 i40e_fcoe_vsi_setup(pf); 11117 11118 #endif 11119 #define PCI_SPEED_SIZE 8 11120 #define PCI_WIDTH_SIZE 8 11121 /* Devices on the IOSF bus do not have this information 11122 * and will report PCI Gen 1 x 1 by default so don't bother 11123 * checking them. 11124 */ 11125 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) { 11126 char speed[PCI_SPEED_SIZE] = "Unknown"; 11127 char width[PCI_WIDTH_SIZE] = "Unknown"; 11128 11129 /* Get the negotiated link width and speed from PCI config 11130 * space 11131 */ 11132 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, 11133 &link_status); 11134 11135 i40e_set_pci_config_data(hw, link_status); 11136 11137 switch (hw->bus.speed) { 11138 case i40e_bus_speed_8000: 11139 strncpy(speed, "8.0", PCI_SPEED_SIZE); break; 11140 case i40e_bus_speed_5000: 11141 strncpy(speed, "5.0", PCI_SPEED_SIZE); break; 11142 case i40e_bus_speed_2500: 11143 strncpy(speed, "2.5", PCI_SPEED_SIZE); break; 11144 default: 11145 break; 11146 } 11147 switch (hw->bus.width) { 11148 case i40e_bus_width_pcie_x8: 11149 strncpy(width, "8", PCI_WIDTH_SIZE); break; 11150 case i40e_bus_width_pcie_x4: 11151 strncpy(width, "4", PCI_WIDTH_SIZE); break; 11152 case i40e_bus_width_pcie_x2: 11153 strncpy(width, "2", PCI_WIDTH_SIZE); break; 11154 case i40e_bus_width_pcie_x1: 11155 strncpy(width, "1", PCI_WIDTH_SIZE); break; 11156 default: 11157 break; 11158 } 11159 11160 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", 11161 speed, width); 11162 11163 if (hw->bus.width < i40e_bus_width_pcie_x8 || 11164 hw->bus.speed < i40e_bus_speed_8000) { 11165 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); 11166 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); 11167 } 11168 } 11169 11170 /* get the requested speeds from the fw */ 11171 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); 11172 if (err) 11173 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", 11174 i40e_stat_str(&pf->hw, err), 11175 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 11176 pf->hw.phy.link_info.requested_speeds = abilities.link_speed; 11177 11178 /* get the supported phy types from the fw */ 11179 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); 11180 if (err) 11181 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", 11182 i40e_stat_str(&pf->hw, err), 11183 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); 11184 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type); 11185 11186 /* Add a filter to drop all Flow control frames from any VSI from being 11187 * transmitted. By doing so we stop a malicious VF from sending out 11188 * PAUSE or PFC frames and potentially controlling traffic for other 11189 * PF/VF VSIs. 11190 * The FW can still send Flow control frames if enabled. 11191 */ 11192 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, 11193 pf->main_vsi_seid); 11194 11195 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || 11196 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) 11197 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY; 11198 11199 /* print a string summarizing features */ 11200 i40e_print_features(pf); 11201 11202 return 0; 11203 11204 /* Unwind what we've done if something failed in the setup */ 11205 err_vsis: 11206 set_bit(__I40E_DOWN, &pf->state); 11207 i40e_clear_interrupt_scheme(pf); 11208 kfree(pf->vsi); 11209 err_switch_setup: 11210 i40e_reset_interrupt_capability(pf); 11211 del_timer_sync(&pf->service_timer); 11212 err_mac_addr: 11213 err_configure_lan_hmc: 11214 (void)i40e_shutdown_lan_hmc(hw); 11215 err_init_lan_hmc: 11216 kfree(pf->qp_pile); 11217 err_sw_init: 11218 err_adminq_setup: 11219 err_pf_reset: 11220 iounmap(hw->hw_addr); 11221 err_ioremap: 11222 kfree(pf); 11223 err_pf_alloc: 11224 pci_disable_pcie_error_reporting(pdev); 11225 pci_release_mem_regions(pdev); 11226 err_pci_reg: 11227 err_dma: 11228 pci_disable_device(pdev); 11229 return err; 11230 } 11231 11232 /** 11233 * i40e_remove - Device removal routine 11234 * @pdev: PCI device information struct 11235 * 11236 * i40e_remove is called by the PCI subsystem to alert the driver 11237 * that is should release a PCI device. This could be caused by a 11238 * Hot-Plug event, or because the driver is going to be removed from 11239 * memory. 11240 **/ 11241 static void i40e_remove(struct pci_dev *pdev) 11242 { 11243 struct i40e_pf *pf = pci_get_drvdata(pdev); 11244 struct i40e_hw *hw = &pf->hw; 11245 i40e_status ret_code; 11246 int i; 11247 11248 i40e_dbg_pf_exit(pf); 11249 11250 i40e_ptp_stop(pf); 11251 11252 /* Disable RSS in hw */ 11253 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); 11254 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); 11255 11256 /* no more scheduling of any task */ 11257 set_bit(__I40E_SUSPENDED, &pf->state); 11258 set_bit(__I40E_DOWN, &pf->state); 11259 if (pf->service_timer.data) 11260 del_timer_sync(&pf->service_timer); 11261 if (pf->service_task.func) 11262 cancel_work_sync(&pf->service_task); 11263 11264 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { 11265 i40e_free_vfs(pf); 11266 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; 11267 } 11268 11269 i40e_fdir_teardown(pf); 11270 11271 /* If there is a switch structure or any orphans, remove them. 11272 * This will leave only the PF's VSI remaining. 11273 */ 11274 for (i = 0; i < I40E_MAX_VEB; i++) { 11275 if (!pf->veb[i]) 11276 continue; 11277 11278 if (pf->veb[i]->uplink_seid == pf->mac_seid || 11279 pf->veb[i]->uplink_seid == 0) 11280 i40e_switch_branch_release(pf->veb[i]); 11281 } 11282 11283 /* Now we can shutdown the PF's VSI, just before we kill 11284 * adminq and hmc. 11285 */ 11286 if (pf->vsi[pf->lan_vsi]) 11287 i40e_vsi_release(pf->vsi[pf->lan_vsi]); 11288 11289 /* remove attached clients */ 11290 ret_code = i40e_lan_del_device(pf); 11291 if (ret_code) { 11292 dev_warn(&pdev->dev, "Failed to delete client device: %d\n", 11293 ret_code); 11294 } 11295 11296 /* shutdown and destroy the HMC */ 11297 if (hw->hmc.hmc_obj) { 11298 ret_code = i40e_shutdown_lan_hmc(hw); 11299 if (ret_code) 11300 dev_warn(&pdev->dev, 11301 "Failed to destroy the HMC resources: %d\n", 11302 ret_code); 11303 } 11304 11305 /* shutdown the adminq */ 11306 ret_code = i40e_shutdown_adminq(hw); 11307 if (ret_code) 11308 dev_warn(&pdev->dev, 11309 "Failed to destroy the Admin Queue resources: %d\n", 11310 ret_code); 11311 11312 /* destroy the locks only once, here */ 11313 mutex_destroy(&hw->aq.arq_mutex); 11314 mutex_destroy(&hw->aq.asq_mutex); 11315 11316 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ 11317 i40e_clear_interrupt_scheme(pf); 11318 for (i = 0; i < pf->num_alloc_vsi; i++) { 11319 if (pf->vsi[i]) { 11320 i40e_vsi_clear_rings(pf->vsi[i]); 11321 i40e_vsi_clear(pf->vsi[i]); 11322 pf->vsi[i] = NULL; 11323 } 11324 } 11325 11326 for (i = 0; i < I40E_MAX_VEB; i++) { 11327 kfree(pf->veb[i]); 11328 pf->veb[i] = NULL; 11329 } 11330 11331 kfree(pf->qp_pile); 11332 kfree(pf->vsi); 11333 11334 iounmap(hw->hw_addr); 11335 kfree(pf); 11336 pci_release_mem_regions(pdev); 11337 11338 pci_disable_pcie_error_reporting(pdev); 11339 pci_disable_device(pdev); 11340 } 11341 11342 /** 11343 * i40e_pci_error_detected - warning that something funky happened in PCI land 11344 * @pdev: PCI device information struct 11345 * 11346 * Called to warn that something happened and the error handling steps 11347 * are in progress. Allows the driver to quiesce things, be ready for 11348 * remediation. 11349 **/ 11350 static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, 11351 enum pci_channel_state error) 11352 { 11353 struct i40e_pf *pf = pci_get_drvdata(pdev); 11354 11355 dev_info(&pdev->dev, "%s: error %d\n", __func__, error); 11356 11357 /* shutdown all operations */ 11358 if (!test_bit(__I40E_SUSPENDED, &pf->state)) { 11359 rtnl_lock(); 11360 i40e_prep_for_reset(pf); 11361 rtnl_unlock(); 11362 } 11363 11364 /* Request a slot reset */ 11365 return PCI_ERS_RESULT_NEED_RESET; 11366 } 11367 11368 /** 11369 * i40e_pci_error_slot_reset - a PCI slot reset just happened 11370 * @pdev: PCI device information struct 11371 * 11372 * Called to find if the driver can work with the device now that 11373 * the pci slot has been reset. If a basic connection seems good 11374 * (registers are readable and have sane content) then return a 11375 * happy little PCI_ERS_RESULT_xxx. 11376 **/ 11377 static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) 11378 { 11379 struct i40e_pf *pf = pci_get_drvdata(pdev); 11380 pci_ers_result_t result; 11381 int err; 11382 u32 reg; 11383 11384 dev_dbg(&pdev->dev, "%s\n", __func__); 11385 if (pci_enable_device_mem(pdev)) { 11386 dev_info(&pdev->dev, 11387 "Cannot re-enable PCI device after reset.\n"); 11388 result = PCI_ERS_RESULT_DISCONNECT; 11389 } else { 11390 pci_set_master(pdev); 11391 pci_restore_state(pdev); 11392 pci_save_state(pdev); 11393 pci_wake_from_d3(pdev, false); 11394 11395 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); 11396 if (reg == 0) 11397 result = PCI_ERS_RESULT_RECOVERED; 11398 else 11399 result = PCI_ERS_RESULT_DISCONNECT; 11400 } 11401 11402 err = pci_cleanup_aer_uncorrect_error_status(pdev); 11403 if (err) { 11404 dev_info(&pdev->dev, 11405 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 11406 err); 11407 /* non-fatal, continue */ 11408 } 11409 11410 return result; 11411 } 11412 11413 /** 11414 * i40e_pci_error_resume - restart operations after PCI error recovery 11415 * @pdev: PCI device information struct 11416 * 11417 * Called to allow the driver to bring things back up after PCI error 11418 * and/or reset recovery has finished. 11419 **/ 11420 static void i40e_pci_error_resume(struct pci_dev *pdev) 11421 { 11422 struct i40e_pf *pf = pci_get_drvdata(pdev); 11423 11424 dev_dbg(&pdev->dev, "%s\n", __func__); 11425 if (test_bit(__I40E_SUSPENDED, &pf->state)) 11426 return; 11427 11428 rtnl_lock(); 11429 i40e_handle_reset_warning(pf); 11430 rtnl_unlock(); 11431 } 11432 11433 /** 11434 * i40e_shutdown - PCI callback for shutting down 11435 * @pdev: PCI device information struct 11436 **/ 11437 static void i40e_shutdown(struct pci_dev *pdev) 11438 { 11439 struct i40e_pf *pf = pci_get_drvdata(pdev); 11440 struct i40e_hw *hw = &pf->hw; 11441 11442 set_bit(__I40E_SUSPENDED, &pf->state); 11443 set_bit(__I40E_DOWN, &pf->state); 11444 rtnl_lock(); 11445 i40e_prep_for_reset(pf); 11446 rtnl_unlock(); 11447 11448 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); 11449 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); 11450 11451 del_timer_sync(&pf->service_timer); 11452 cancel_work_sync(&pf->service_task); 11453 i40e_fdir_teardown(pf); 11454 11455 rtnl_lock(); 11456 i40e_prep_for_reset(pf); 11457 rtnl_unlock(); 11458 11459 wr32(hw, I40E_PFPM_APM, 11460 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); 11461 wr32(hw, I40E_PFPM_WUFC, 11462 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); 11463 11464 i40e_clear_interrupt_scheme(pf); 11465 11466 if (system_state == SYSTEM_POWER_OFF) { 11467 pci_wake_from_d3(pdev, pf->wol_en); 11468 pci_set_power_state(pdev, PCI_D3hot); 11469 } 11470 } 11471 11472 #ifdef CONFIG_PM 11473 /** 11474 * i40e_suspend - PCI callback for moving to D3 11475 * @pdev: PCI device information struct 11476 **/ 11477 static int i40e_suspend(struct pci_dev *pdev, pm_message_t state) 11478 { 11479 struct i40e_pf *pf = pci_get_drvdata(pdev); 11480 struct i40e_hw *hw = &pf->hw; 11481 int retval = 0; 11482 11483 set_bit(__I40E_SUSPENDED, &pf->state); 11484 set_bit(__I40E_DOWN, &pf->state); 11485 11486 rtnl_lock(); 11487 i40e_prep_for_reset(pf); 11488 rtnl_unlock(); 11489 11490 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); 11491 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); 11492 11493 i40e_stop_misc_vector(pf); 11494 11495 retval = pci_save_state(pdev); 11496 if (retval) 11497 return retval; 11498 11499 pci_wake_from_d3(pdev, pf->wol_en); 11500 pci_set_power_state(pdev, PCI_D3hot); 11501 11502 return retval; 11503 } 11504 11505 /** 11506 * i40e_resume - PCI callback for waking up from D3 11507 * @pdev: PCI device information struct 11508 **/ 11509 static int i40e_resume(struct pci_dev *pdev) 11510 { 11511 struct i40e_pf *pf = pci_get_drvdata(pdev); 11512 u32 err; 11513 11514 pci_set_power_state(pdev, PCI_D0); 11515 pci_restore_state(pdev); 11516 /* pci_restore_state() clears dev->state_saves, so 11517 * call pci_save_state() again to restore it. 11518 */ 11519 pci_save_state(pdev); 11520 11521 err = pci_enable_device_mem(pdev); 11522 if (err) { 11523 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); 11524 return err; 11525 } 11526 pci_set_master(pdev); 11527 11528 /* no wakeup events while running */ 11529 pci_wake_from_d3(pdev, false); 11530 11531 /* handling the reset will rebuild the device state */ 11532 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) { 11533 clear_bit(__I40E_DOWN, &pf->state); 11534 rtnl_lock(); 11535 i40e_reset_and_rebuild(pf, false); 11536 rtnl_unlock(); 11537 } 11538 11539 return 0; 11540 } 11541 11542 #endif 11543 static const struct pci_error_handlers i40e_err_handler = { 11544 .error_detected = i40e_pci_error_detected, 11545 .slot_reset = i40e_pci_error_slot_reset, 11546 .resume = i40e_pci_error_resume, 11547 }; 11548 11549 static struct pci_driver i40e_driver = { 11550 .name = i40e_driver_name, 11551 .id_table = i40e_pci_tbl, 11552 .probe = i40e_probe, 11553 .remove = i40e_remove, 11554 #ifdef CONFIG_PM 11555 .suspend = i40e_suspend, 11556 .resume = i40e_resume, 11557 #endif 11558 .shutdown = i40e_shutdown, 11559 .err_handler = &i40e_err_handler, 11560 .sriov_configure = i40e_pci_sriov_configure, 11561 }; 11562 11563 /** 11564 * i40e_init_module - Driver registration routine 11565 * 11566 * i40e_init_module is the first routine called when the driver is 11567 * loaded. All it does is register with the PCI subsystem. 11568 **/ 11569 static int __init i40e_init_module(void) 11570 { 11571 pr_info("%s: %s - version %s\n", i40e_driver_name, 11572 i40e_driver_string, i40e_driver_version_str); 11573 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); 11574 11575 /* we will see if single thread per module is enough for now, 11576 * it can't be any worse than using the system workqueue which 11577 * was already single threaded 11578 */ 11579 i40e_wq = create_singlethread_workqueue(i40e_driver_name); 11580 if (!i40e_wq) { 11581 pr_err("%s: Failed to create workqueue\n", i40e_driver_name); 11582 return -ENOMEM; 11583 } 11584 11585 i40e_dbg_init(); 11586 return pci_register_driver(&i40e_driver); 11587 } 11588 module_init(i40e_init_module); 11589 11590 /** 11591 * i40e_exit_module - Driver exit cleanup routine 11592 * 11593 * i40e_exit_module is called just before the driver is removed 11594 * from memory. 11595 **/ 11596 static void __exit i40e_exit_module(void) 11597 { 11598 pci_unregister_driver(&i40e_driver); 11599 destroy_workqueue(i40e_wq); 11600 i40e_dbg_exit(); 11601 } 11602 module_exit(i40e_exit_module); 11603