1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_diag.h" 28 #include "i40e_prototype.h" 29 30 /** 31 * i40e_diag_reg_pattern_test 32 * @hw: pointer to the hw struct 33 * @reg: reg to be tested 34 * @mask: bits to be touched 35 **/ 36 static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw, 37 u32 reg, u32 mask) 38 { 39 static const u32 patterns[] = { 40 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF 41 }; 42 u32 pat, val, orig_val; 43 int i; 44 45 orig_val = rd32(hw, reg); 46 for (i = 0; i < ARRAY_SIZE(patterns); i++) { 47 pat = patterns[i]; 48 wr32(hw, reg, (pat & mask)); 49 val = rd32(hw, reg); 50 if ((val & mask) != (pat & mask)) { 51 i40e_debug(hw, I40E_DEBUG_DIAG, 52 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n", 53 __func__, reg, pat, val); 54 return I40E_ERR_DIAG_TEST_FAILED; 55 } 56 } 57 58 wr32(hw, reg, orig_val); 59 val = rd32(hw, reg); 60 if (val != orig_val) { 61 i40e_debug(hw, I40E_DEBUG_DIAG, 62 "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n", 63 __func__, reg, orig_val, val); 64 return I40E_ERR_DIAG_TEST_FAILED; 65 } 66 67 return 0; 68 } 69 70 struct i40e_diag_reg_test_info i40e_reg_list[] = { 71 /* offset mask elements stride */ 72 {I40E_QTX_CTL(0), 0x0000FFBF, 1, 73 I40E_QTX_CTL(1) - I40E_QTX_CTL(0)}, 74 {I40E_PFINT_ITR0(0), 0x00000FFF, 3, 75 I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)}, 76 {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1, 77 I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)}, 78 {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1, 79 I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)}, 80 {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1, 81 I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)}, 82 {I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0}, 83 {I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0}, 84 {I40E_PFINT_LNKLSTN(0), 0x000007FF, 1, 85 I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)}, 86 {I40E_QINT_TQCTL(0), 0x000000FF, 1, 87 I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)}, 88 {I40E_QINT_RQCTL(0), 0x000000FF, 1, 89 I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)}, 90 {I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0}, 91 { 0 } 92 }; 93 94 /** 95 * i40e_diag_reg_test 96 * @hw: pointer to the hw struct 97 * 98 * Perform registers diagnostic test 99 **/ 100 i40e_status i40e_diag_reg_test(struct i40e_hw *hw) 101 { 102 i40e_status ret_code = 0; 103 u32 reg, mask; 104 u32 i, j; 105 106 for (i = 0; i40e_reg_list[i].offset != 0 && 107 !ret_code; i++) { 108 109 /* set actual reg range for dynamically allocated resources */ 110 if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) && 111 hw->func_caps.num_tx_qp != 0) 112 i40e_reg_list[i].elements = hw->func_caps.num_tx_qp; 113 if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) || 114 i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) || 115 i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) || 116 i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) || 117 i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) && 118 hw->func_caps.num_msix_vectors != 0) 119 i40e_reg_list[i].elements = 120 hw->func_caps.num_msix_vectors - 1; 121 122 /* test register access */ 123 mask = i40e_reg_list[i].mask; 124 for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) { 125 reg = i40e_reg_list[i].offset + 126 (j * i40e_reg_list[i].stride); 127 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); 128 } 129 } 130 131 return ret_code; 132 } 133 134 /** 135 * i40e_diag_eeprom_test 136 * @hw: pointer to the hw struct 137 * 138 * Perform EEPROM diagnostic test 139 **/ 140 i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw) 141 { 142 i40e_status ret_code; 143 u16 reg_val; 144 145 /* read NVM control word and if NVM valid, validate EEPROM checksum*/ 146 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val); 147 if (!ret_code && 148 ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) == 149 BIT(I40E_SR_CONTROL_WORD_1_SHIFT))) 150 return i40e_validate_nvm_checksum(hw, NULL); 151 else 152 return I40E_ERR_DIAG_TEST_FAILED; 153 } 154