1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_adminq.h" 28 #include "i40e_prototype.h" 29 #include "i40e_dcb.h" 30 31 /** 32 * i40e_get_dcbx_status 33 * @hw: pointer to the hw struct 34 * @status: Embedded DCBX Engine Status 35 * 36 * Get the DCBX status from the Firmware 37 **/ 38 i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status) 39 { 40 u32 reg; 41 42 if (!status) 43 return I40E_ERR_PARAM; 44 45 reg = rd32(hw, I40E_PRTDCB_GENS); 46 *status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >> 47 I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT); 48 49 return 0; 50 } 51 52 /** 53 * i40e_parse_ieee_etscfg_tlv 54 * @tlv: IEEE 802.1Qaz ETS CFG TLV 55 * @dcbcfg: Local store to update ETS CFG data 56 * 57 * Parses IEEE 802.1Qaz ETS CFG TLV 58 **/ 59 static void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv, 60 struct i40e_dcbx_config *dcbcfg) 61 { 62 struct i40e_dcb_ets_config *etscfg; 63 u8 *buf = tlv->tlvinfo; 64 u16 offset = 0; 65 u8 priority; 66 int i; 67 68 /* First Octet post subtype 69 * -------------------------- 70 * |will-|CBS | Re- | Max | 71 * |ing | |served| TCs | 72 * -------------------------- 73 * |1bit | 1bit|3 bits|3bits| 74 */ 75 etscfg = &dcbcfg->etscfg; 76 etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >> 77 I40E_IEEE_ETS_WILLING_SHIFT); 78 etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >> 79 I40E_IEEE_ETS_CBS_SHIFT); 80 etscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >> 81 I40E_IEEE_ETS_MAXTC_SHIFT); 82 83 /* Move offset to Priority Assignment Table */ 84 offset++; 85 86 /* Priority Assignment Table (4 octets) 87 * Octets:| 1 | 2 | 3 | 4 | 88 * ----------------------------------------- 89 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7| 90 * ----------------------------------------- 91 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0| 92 * ----------------------------------------- 93 */ 94 for (i = 0; i < 4; i++) { 95 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >> 96 I40E_IEEE_ETS_PRIO_1_SHIFT); 97 etscfg->prioritytable[i * 2] = priority; 98 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >> 99 I40E_IEEE_ETS_PRIO_0_SHIFT); 100 etscfg->prioritytable[i * 2 + 1] = priority; 101 offset++; 102 } 103 104 /* TC Bandwidth Table (8 octets) 105 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 106 * --------------------------------- 107 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| 108 * --------------------------------- 109 */ 110 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 111 etscfg->tcbwtable[i] = buf[offset++]; 112 113 /* TSA Assignment Table (8 octets) 114 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 115 * --------------------------------- 116 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| 117 * --------------------------------- 118 */ 119 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 120 etscfg->tsatable[i] = buf[offset++]; 121 } 122 123 /** 124 * i40e_parse_ieee_etsrec_tlv 125 * @tlv: IEEE 802.1Qaz ETS REC TLV 126 * @dcbcfg: Local store to update ETS REC data 127 * 128 * Parses IEEE 802.1Qaz ETS REC TLV 129 **/ 130 static void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv, 131 struct i40e_dcbx_config *dcbcfg) 132 { 133 u8 *buf = tlv->tlvinfo; 134 u16 offset = 0; 135 u8 priority; 136 int i; 137 138 /* Move offset to priority table */ 139 offset++; 140 141 /* Priority Assignment Table (4 octets) 142 * Octets:| 1 | 2 | 3 | 4 | 143 * ----------------------------------------- 144 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7| 145 * ----------------------------------------- 146 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0| 147 * ----------------------------------------- 148 */ 149 for (i = 0; i < 4; i++) { 150 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >> 151 I40E_IEEE_ETS_PRIO_1_SHIFT); 152 dcbcfg->etsrec.prioritytable[i*2] = priority; 153 priority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >> 154 I40E_IEEE_ETS_PRIO_0_SHIFT); 155 dcbcfg->etsrec.prioritytable[i*2 + 1] = priority; 156 offset++; 157 } 158 159 /* TC Bandwidth Table (8 octets) 160 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 161 * --------------------------------- 162 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| 163 * --------------------------------- 164 */ 165 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 166 dcbcfg->etsrec.tcbwtable[i] = buf[offset++]; 167 168 /* TSA Assignment Table (8 octets) 169 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 170 * --------------------------------- 171 * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| 172 * --------------------------------- 173 */ 174 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 175 dcbcfg->etsrec.tsatable[i] = buf[offset++]; 176 } 177 178 /** 179 * i40e_parse_ieee_pfccfg_tlv 180 * @tlv: IEEE 802.1Qaz PFC CFG TLV 181 * @dcbcfg: Local store to update PFC CFG data 182 * 183 * Parses IEEE 802.1Qaz PFC CFG TLV 184 **/ 185 static void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv, 186 struct i40e_dcbx_config *dcbcfg) 187 { 188 u8 *buf = tlv->tlvinfo; 189 190 /* ---------------------------------------- 191 * |will-|MBC | Re- | PFC | PFC Enable | 192 * |ing | |served| cap | | 193 * ----------------------------------------- 194 * |1bit | 1bit|2 bits|4bits| 1 octet | 195 */ 196 dcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >> 197 I40E_IEEE_PFC_WILLING_SHIFT); 198 dcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >> 199 I40E_IEEE_PFC_MBC_SHIFT); 200 dcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >> 201 I40E_IEEE_PFC_CAP_SHIFT); 202 dcbcfg->pfc.pfcenable = buf[1]; 203 } 204 205 /** 206 * i40e_parse_ieee_app_tlv 207 * @tlv: IEEE 802.1Qaz APP TLV 208 * @dcbcfg: Local store to update APP PRIO data 209 * 210 * Parses IEEE 802.1Qaz APP PRIO TLV 211 **/ 212 static void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv, 213 struct i40e_dcbx_config *dcbcfg) 214 { 215 u16 typelength; 216 u16 offset = 0; 217 u16 length; 218 int i = 0; 219 u8 *buf; 220 221 typelength = ntohs(tlv->typelength); 222 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 223 I40E_LLDP_TLV_LEN_SHIFT); 224 buf = tlv->tlvinfo; 225 226 /* The App priority table starts 5 octets after TLV header */ 227 length -= (sizeof(tlv->ouisubtype) + 1); 228 229 /* Move offset to App Priority Table */ 230 offset++; 231 232 /* Application Priority Table (3 octets) 233 * Octets:| 1 | 2 | 3 | 234 * ----------------------------------------- 235 * |Priority|Rsrvd| Sel | Protocol ID | 236 * ----------------------------------------- 237 * Bits:|23 21|20 19|18 16|15 0| 238 * ----------------------------------------- 239 */ 240 while (offset < length) { 241 dcbcfg->app[i].priority = (u8)((buf[offset] & 242 I40E_IEEE_APP_PRIO_MASK) >> 243 I40E_IEEE_APP_PRIO_SHIFT); 244 dcbcfg->app[i].selector = (u8)((buf[offset] & 245 I40E_IEEE_APP_SEL_MASK) >> 246 I40E_IEEE_APP_SEL_SHIFT); 247 dcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) | 248 buf[offset + 2]; 249 /* Move to next app */ 250 offset += 3; 251 i++; 252 if (i >= I40E_DCBX_MAX_APPS) 253 break; 254 } 255 256 dcbcfg->numapps = i; 257 } 258 259 /** 260 * i40e_parse_ieee_etsrec_tlv 261 * @tlv: IEEE 802.1Qaz TLV 262 * @dcbcfg: Local store to update ETS REC data 263 * 264 * Get the TLV subtype and send it to parsing function 265 * based on the subtype value 266 **/ 267 static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv, 268 struct i40e_dcbx_config *dcbcfg) 269 { 270 u32 ouisubtype; 271 u8 subtype; 272 273 ouisubtype = ntohl(tlv->ouisubtype); 274 subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >> 275 I40E_LLDP_TLV_SUBTYPE_SHIFT); 276 switch (subtype) { 277 case I40E_IEEE_SUBTYPE_ETS_CFG: 278 i40e_parse_ieee_etscfg_tlv(tlv, dcbcfg); 279 break; 280 case I40E_IEEE_SUBTYPE_ETS_REC: 281 i40e_parse_ieee_etsrec_tlv(tlv, dcbcfg); 282 break; 283 case I40E_IEEE_SUBTYPE_PFC_CFG: 284 i40e_parse_ieee_pfccfg_tlv(tlv, dcbcfg); 285 break; 286 case I40E_IEEE_SUBTYPE_APP_PRI: 287 i40e_parse_ieee_app_tlv(tlv, dcbcfg); 288 break; 289 default: 290 break; 291 } 292 } 293 294 /** 295 * i40e_parse_cee_pgcfg_tlv 296 * @tlv: CEE DCBX PG CFG TLV 297 * @dcbcfg: Local store to update ETS CFG data 298 * 299 * Parses CEE DCBX PG CFG TLV 300 **/ 301 static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv, 302 struct i40e_dcbx_config *dcbcfg) 303 { 304 struct i40e_dcb_ets_config *etscfg; 305 u8 *buf = tlv->tlvinfo; 306 u16 offset = 0; 307 u8 priority; 308 int i; 309 310 etscfg = &dcbcfg->etscfg; 311 312 if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK) 313 etscfg->willing = 1; 314 315 etscfg->cbs = 0; 316 /* Priority Group Table (4 octets) 317 * Octets:| 1 | 2 | 3 | 4 | 318 * ----------------------------------------- 319 * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7| 320 * ----------------------------------------- 321 * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0| 322 * ----------------------------------------- 323 */ 324 for (i = 0; i < 4; i++) { 325 priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >> 326 I40E_CEE_PGID_PRIO_1_SHIFT); 327 etscfg->prioritytable[i * 2] = priority; 328 priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >> 329 I40E_CEE_PGID_PRIO_0_SHIFT); 330 etscfg->prioritytable[i * 2 + 1] = priority; 331 offset++; 332 } 333 334 /* PG Percentage Table (8 octets) 335 * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 336 * --------------------------------- 337 * |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7| 338 * --------------------------------- 339 */ 340 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 341 etscfg->tcbwtable[i] = buf[offset++]; 342 343 /* Number of TCs supported (1 octet) */ 344 etscfg->maxtcs = buf[offset]; 345 } 346 347 /** 348 * i40e_parse_cee_pfccfg_tlv 349 * @tlv: CEE DCBX PFC CFG TLV 350 * @dcbcfg: Local store to update PFC CFG data 351 * 352 * Parses CEE DCBX PFC CFG TLV 353 **/ 354 static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv, 355 struct i40e_dcbx_config *dcbcfg) 356 { 357 u8 *buf = tlv->tlvinfo; 358 359 if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK) 360 dcbcfg->pfc.willing = 1; 361 362 /* ------------------------ 363 * | PFC Enable | PFC TCs | 364 * ------------------------ 365 * | 1 octet | 1 octet | 366 */ 367 dcbcfg->pfc.pfcenable = buf[0]; 368 dcbcfg->pfc.pfccap = buf[1]; 369 } 370 371 /** 372 * i40e_parse_cee_app_tlv 373 * @tlv: CEE DCBX APP TLV 374 * @dcbcfg: Local store to update APP PRIO data 375 * 376 * Parses CEE DCBX APP PRIO TLV 377 **/ 378 static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv, 379 struct i40e_dcbx_config *dcbcfg) 380 { 381 u16 length, typelength, offset = 0; 382 struct i40e_cee_app_prio *app; 383 u8 i; 384 385 typelength = ntohs(tlv->hdr.typelen); 386 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 387 I40E_LLDP_TLV_LEN_SHIFT); 388 389 dcbcfg->numapps = length / sizeof(*app); 390 391 if (!dcbcfg->numapps) 392 return; 393 if (dcbcfg->numapps > I40E_DCBX_MAX_APPS) 394 dcbcfg->numapps = I40E_DCBX_MAX_APPS; 395 396 for (i = 0; i < dcbcfg->numapps; i++) { 397 u8 up, selector; 398 399 app = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset); 400 for (up = 0; up < I40E_MAX_USER_PRIORITY; up++) { 401 if (app->prio_map & BIT(up)) 402 break; 403 } 404 dcbcfg->app[i].priority = up; 405 406 /* Get Selector from lower 2 bits, and convert to IEEE */ 407 selector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK); 408 switch (selector) { 409 case I40E_CEE_APP_SEL_ETHTYPE: 410 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE; 411 break; 412 case I40E_CEE_APP_SEL_TCPIP: 413 dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP; 414 break; 415 default: 416 /* Keep selector as it is for unknown types */ 417 dcbcfg->app[i].selector = selector; 418 } 419 420 dcbcfg->app[i].protocolid = ntohs(app->protocol); 421 /* Move to next app */ 422 offset += sizeof(*app); 423 } 424 } 425 426 /** 427 * i40e_parse_cee_tlv 428 * @tlv: CEE DCBX TLV 429 * @dcbcfg: Local store to update DCBX config data 430 * 431 * Get the TLV subtype and send it to parsing function 432 * based on the subtype value 433 **/ 434 static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv, 435 struct i40e_dcbx_config *dcbcfg) 436 { 437 u16 len, tlvlen, sublen, typelength; 438 struct i40e_cee_feat_tlv *sub_tlv; 439 u8 subtype, feat_tlv_count = 0; 440 u32 ouisubtype; 441 442 ouisubtype = ntohl(tlv->ouisubtype); 443 subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >> 444 I40E_LLDP_TLV_SUBTYPE_SHIFT); 445 /* Return if not CEE DCBX */ 446 if (subtype != I40E_CEE_DCBX_TYPE) 447 return; 448 449 typelength = ntohs(tlv->typelength); 450 tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 451 I40E_LLDP_TLV_LEN_SHIFT); 452 len = sizeof(tlv->typelength) + sizeof(ouisubtype) + 453 sizeof(struct i40e_cee_ctrl_tlv); 454 /* Return if no CEE DCBX Feature TLVs */ 455 if (tlvlen <= len) 456 return; 457 458 sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len); 459 while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) { 460 typelength = ntohs(sub_tlv->hdr.typelen); 461 sublen = (u16)((typelength & 462 I40E_LLDP_TLV_LEN_MASK) >> 463 I40E_LLDP_TLV_LEN_SHIFT); 464 subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >> 465 I40E_LLDP_TLV_TYPE_SHIFT); 466 switch (subtype) { 467 case I40E_CEE_SUBTYPE_PG_CFG: 468 i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg); 469 break; 470 case I40E_CEE_SUBTYPE_PFC_CFG: 471 i40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg); 472 break; 473 case I40E_CEE_SUBTYPE_APP_PRI: 474 i40e_parse_cee_app_tlv(sub_tlv, dcbcfg); 475 break; 476 default: 477 return; /* Invalid Sub-type return */ 478 } 479 feat_tlv_count++; 480 /* Move to next sub TLV */ 481 sub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv + 482 sizeof(sub_tlv->hdr.typelen) + 483 sublen); 484 } 485 } 486 487 /** 488 * i40e_parse_org_tlv 489 * @tlv: Organization specific TLV 490 * @dcbcfg: Local store to update ETS REC data 491 * 492 * Currently only IEEE 802.1Qaz TLV is supported, all others 493 * will be returned 494 **/ 495 static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv, 496 struct i40e_dcbx_config *dcbcfg) 497 { 498 u32 ouisubtype; 499 u32 oui; 500 501 ouisubtype = ntohl(tlv->ouisubtype); 502 oui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >> 503 I40E_LLDP_TLV_OUI_SHIFT); 504 switch (oui) { 505 case I40E_IEEE_8021QAZ_OUI: 506 i40e_parse_ieee_tlv(tlv, dcbcfg); 507 break; 508 case I40E_CEE_DCBX_OUI: 509 i40e_parse_cee_tlv(tlv, dcbcfg); 510 break; 511 default: 512 break; 513 } 514 } 515 516 /** 517 * i40e_lldp_to_dcb_config 518 * @lldpmib: LLDPDU to be parsed 519 * @dcbcfg: store for LLDPDU data 520 * 521 * Parse DCB configuration from the LLDPDU 522 **/ 523 i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib, 524 struct i40e_dcbx_config *dcbcfg) 525 { 526 i40e_status ret = 0; 527 struct i40e_lldp_org_tlv *tlv; 528 u16 type; 529 u16 length; 530 u16 typelength; 531 u16 offset = 0; 532 533 if (!lldpmib || !dcbcfg) 534 return I40E_ERR_PARAM; 535 536 /* set to the start of LLDPDU */ 537 lldpmib += ETH_HLEN; 538 tlv = (struct i40e_lldp_org_tlv *)lldpmib; 539 while (1) { 540 typelength = ntohs(tlv->typelength); 541 type = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >> 542 I40E_LLDP_TLV_TYPE_SHIFT); 543 length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >> 544 I40E_LLDP_TLV_LEN_SHIFT); 545 offset += sizeof(typelength) + length; 546 547 /* END TLV or beyond LLDPDU size */ 548 if ((type == I40E_TLV_TYPE_END) || (offset > I40E_LLDPDU_SIZE)) 549 break; 550 551 switch (type) { 552 case I40E_TLV_TYPE_ORG: 553 i40e_parse_org_tlv(tlv, dcbcfg); 554 break; 555 default: 556 break; 557 } 558 559 /* Move to next TLV */ 560 tlv = (struct i40e_lldp_org_tlv *)((char *)tlv + 561 sizeof(tlv->typelength) + 562 length); 563 } 564 565 return ret; 566 } 567 568 /** 569 * i40e_aq_get_dcb_config 570 * @hw: pointer to the hw struct 571 * @mib_type: mib type for the query 572 * @bridgetype: bridge type for the query (remote) 573 * @dcbcfg: store for LLDPDU data 574 * 575 * Query DCB configuration from the Firmware 576 **/ 577 i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, 578 u8 bridgetype, 579 struct i40e_dcbx_config *dcbcfg) 580 { 581 i40e_status ret = 0; 582 struct i40e_virt_mem mem; 583 u8 *lldpmib; 584 585 /* Allocate the LLDPDU */ 586 ret = i40e_allocate_virt_mem(hw, &mem, I40E_LLDPDU_SIZE); 587 if (ret) 588 return ret; 589 590 lldpmib = (u8 *)mem.va; 591 ret = i40e_aq_get_lldp_mib(hw, bridgetype, mib_type, 592 (void *)lldpmib, I40E_LLDPDU_SIZE, 593 NULL, NULL, NULL); 594 if (ret) 595 goto free_mem; 596 597 /* Parse LLDP MIB to get dcb configuration */ 598 ret = i40e_lldp_to_dcb_config(lldpmib, dcbcfg); 599 600 free_mem: 601 i40e_free_virt_mem(hw, &mem); 602 return ret; 603 } 604 605 /** 606 * i40e_cee_to_dcb_v1_config 607 * @cee_cfg: pointer to CEE v1 response configuration struct 608 * @dcbcfg: DCB configuration struct 609 * 610 * Convert CEE v1 configuration from firmware to DCB configuration 611 **/ 612 static void i40e_cee_to_dcb_v1_config( 613 struct i40e_aqc_get_cee_dcb_cfg_v1_resp *cee_cfg, 614 struct i40e_dcbx_config *dcbcfg) 615 { 616 u16 status, tlv_status = le16_to_cpu(cee_cfg->tlv_status); 617 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio); 618 u8 i, tc, err; 619 620 /* CEE PG data to ETS config */ 621 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc; 622 623 /* Note that the FW creates the oper_prio_tc nibbles reversed 624 * from those in the CEE Priority Group sub-TLV. 625 */ 626 for (i = 0; i < 4; i++) { 627 tc = (u8)((cee_cfg->oper_prio_tc[i] & 628 I40E_CEE_PGID_PRIO_0_MASK) >> 629 I40E_CEE_PGID_PRIO_0_SHIFT); 630 dcbcfg->etscfg.prioritytable[i * 2] = tc; 631 tc = (u8)((cee_cfg->oper_prio_tc[i] & 632 I40E_CEE_PGID_PRIO_1_MASK) >> 633 I40E_CEE_PGID_PRIO_1_SHIFT); 634 dcbcfg->etscfg.prioritytable[i*2 + 1] = tc; 635 } 636 637 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 638 dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i]; 639 640 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 641 if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) { 642 /* Map it to next empty TC */ 643 dcbcfg->etscfg.prioritytable[i] = 644 cee_cfg->oper_num_tc - 1; 645 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT; 646 } else { 647 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 648 } 649 } 650 651 /* CEE PFC data to ETS config */ 652 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en; 653 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 654 655 status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >> 656 I40E_AQC_CEE_APP_STATUS_SHIFT; 657 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 658 /* Add APPs if Error is False */ 659 if (!err) { 660 /* CEE operating configuration supports FCoE/iSCSI/FIP only */ 661 dcbcfg->numapps = I40E_CEE_OPER_MAX_APPS; 662 663 /* FCoE APP */ 664 dcbcfg->app[0].priority = 665 (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >> 666 I40E_AQC_CEE_APP_FCOE_SHIFT; 667 dcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE; 668 dcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE; 669 670 /* iSCSI APP */ 671 dcbcfg->app[1].priority = 672 (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >> 673 I40E_AQC_CEE_APP_ISCSI_SHIFT; 674 dcbcfg->app[1].selector = I40E_APP_SEL_TCPIP; 675 dcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI; 676 677 /* FIP APP */ 678 dcbcfg->app[2].priority = 679 (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >> 680 I40E_AQC_CEE_APP_FIP_SHIFT; 681 dcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE; 682 dcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP; 683 } 684 } 685 686 /** 687 * i40e_cee_to_dcb_config 688 * @cee_cfg: pointer to CEE configuration struct 689 * @dcbcfg: DCB configuration struct 690 * 691 * Convert CEE configuration from firmware to DCB configuration 692 **/ 693 static void i40e_cee_to_dcb_config( 694 struct i40e_aqc_get_cee_dcb_cfg_resp *cee_cfg, 695 struct i40e_dcbx_config *dcbcfg) 696 { 697 u32 status, tlv_status = le32_to_cpu(cee_cfg->tlv_status); 698 u16 app_prio = le16_to_cpu(cee_cfg->oper_app_prio); 699 u8 i, tc, err, sync, oper; 700 701 /* CEE PG data to ETS config */ 702 dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc; 703 704 /* Note that the FW creates the oper_prio_tc nibbles reversed 705 * from those in the CEE Priority Group sub-TLV. 706 */ 707 for (i = 0; i < 4; i++) { 708 tc = (u8)((cee_cfg->oper_prio_tc[i] & 709 I40E_CEE_PGID_PRIO_0_MASK) >> 710 I40E_CEE_PGID_PRIO_0_SHIFT); 711 dcbcfg->etscfg.prioritytable[i * 2] = tc; 712 tc = (u8)((cee_cfg->oper_prio_tc[i] & 713 I40E_CEE_PGID_PRIO_1_MASK) >> 714 I40E_CEE_PGID_PRIO_1_SHIFT); 715 dcbcfg->etscfg.prioritytable[i * 2 + 1] = tc; 716 } 717 718 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) 719 dcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i]; 720 721 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { 722 if (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) { 723 /* Map it to next empty TC */ 724 dcbcfg->etscfg.prioritytable[i] = 725 cee_cfg->oper_num_tc - 1; 726 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT; 727 } else { 728 dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS; 729 } 730 } 731 732 /* CEE PFC data to ETS config */ 733 dcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en; 734 dcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; 735 736 i = 0; 737 status = (tlv_status & I40E_AQC_CEE_FCOE_STATUS_MASK) >> 738 I40E_AQC_CEE_FCOE_STATUS_SHIFT; 739 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 740 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 741 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; 742 /* Add FCoE APP if Error is False and Oper/Sync is True */ 743 if (!err && sync && oper) { 744 /* FCoE APP */ 745 dcbcfg->app[i].priority = 746 (app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >> 747 I40E_AQC_CEE_APP_FCOE_SHIFT; 748 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE; 749 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FCOE; 750 i++; 751 } 752 753 status = (tlv_status & I40E_AQC_CEE_ISCSI_STATUS_MASK) >> 754 I40E_AQC_CEE_ISCSI_STATUS_SHIFT; 755 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 756 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 757 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; 758 /* Add iSCSI APP if Error is False and Oper/Sync is True */ 759 if (!err && sync && oper) { 760 /* iSCSI APP */ 761 dcbcfg->app[i].priority = 762 (app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >> 763 I40E_AQC_CEE_APP_ISCSI_SHIFT; 764 dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP; 765 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_ISCSI; 766 i++; 767 } 768 769 status = (tlv_status & I40E_AQC_CEE_FIP_STATUS_MASK) >> 770 I40E_AQC_CEE_FIP_STATUS_SHIFT; 771 err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0; 772 sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0; 773 oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0; 774 /* Add FIP APP if Error is False and Oper/Sync is True */ 775 if (!err && sync && oper) { 776 /* FIP APP */ 777 dcbcfg->app[i].priority = 778 (app_prio & I40E_AQC_CEE_APP_FIP_MASK) >> 779 I40E_AQC_CEE_APP_FIP_SHIFT; 780 dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE; 781 dcbcfg->app[i].protocolid = I40E_APP_PROTOID_FIP; 782 i++; 783 } 784 dcbcfg->numapps = i; 785 } 786 787 /** 788 * i40e_get_ieee_dcb_config 789 * @hw: pointer to the hw struct 790 * 791 * Get IEEE mode DCB configuration from the Firmware 792 **/ 793 static i40e_status i40e_get_ieee_dcb_config(struct i40e_hw *hw) 794 { 795 i40e_status ret = 0; 796 797 /* IEEE mode */ 798 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE; 799 /* Get Local DCB Config */ 800 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 801 &hw->local_dcbx_config); 802 if (ret) 803 goto out; 804 805 /* Get Remote DCB Config */ 806 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, 807 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 808 &hw->remote_dcbx_config); 809 /* Don't treat ENOENT as an error for Remote MIBs */ 810 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 811 ret = 0; 812 813 out: 814 return ret; 815 } 816 817 /** 818 * i40e_get_dcb_config 819 * @hw: pointer to the hw struct 820 * 821 * Get DCB configuration from the Firmware 822 **/ 823 i40e_status i40e_get_dcb_config(struct i40e_hw *hw) 824 { 825 i40e_status ret = 0; 826 struct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg; 827 struct i40e_aqc_get_cee_dcb_cfg_v1_resp cee_v1_cfg; 828 829 /* If Firmware version < v4.33 on X710/XL710, IEEE only */ 830 if ((hw->mac.type == I40E_MAC_XL710) && 831 (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 832 (hw->aq.fw_maj_ver < 4))) 833 return i40e_get_ieee_dcb_config(hw); 834 835 /* If Firmware version == v4.33 on X710/XL710, use old CEE struct */ 836 if ((hw->mac.type == I40E_MAC_XL710) && 837 ((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver == 33))) { 838 ret = i40e_aq_get_cee_dcb_config(hw, &cee_v1_cfg, 839 sizeof(cee_v1_cfg), NULL); 840 if (!ret) { 841 /* CEE mode */ 842 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE; 843 hw->local_dcbx_config.tlv_status = 844 le16_to_cpu(cee_v1_cfg.tlv_status); 845 i40e_cee_to_dcb_v1_config(&cee_v1_cfg, 846 &hw->local_dcbx_config); 847 } 848 } else { 849 ret = i40e_aq_get_cee_dcb_config(hw, &cee_cfg, 850 sizeof(cee_cfg), NULL); 851 if (!ret) { 852 /* CEE mode */ 853 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE; 854 hw->local_dcbx_config.tlv_status = 855 le32_to_cpu(cee_cfg.tlv_status); 856 i40e_cee_to_dcb_config(&cee_cfg, 857 &hw->local_dcbx_config); 858 } 859 } 860 861 /* CEE mode not enabled try querying IEEE data */ 862 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 863 return i40e_get_ieee_dcb_config(hw); 864 865 if (ret) 866 goto out; 867 868 /* Get CEE DCB Desired Config */ 869 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0, 870 &hw->desired_dcbx_config); 871 if (ret) 872 goto out; 873 874 /* Get Remote DCB Config */ 875 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, 876 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, 877 &hw->remote_dcbx_config); 878 /* Don't treat ENOENT as an error for Remote MIBs */ 879 if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) 880 ret = 0; 881 882 out: 883 return ret; 884 } 885 886 /** 887 * i40e_init_dcb 888 * @hw: pointer to the hw struct 889 * 890 * Update DCB configuration from the Firmware 891 **/ 892 i40e_status i40e_init_dcb(struct i40e_hw *hw) 893 { 894 i40e_status ret = 0; 895 struct i40e_lldp_variables lldp_cfg; 896 u8 adminstatus = 0; 897 898 if (!hw->func_caps.dcb) 899 return ret; 900 901 /* Read LLDP NVM area */ 902 ret = i40e_read_lldp_cfg(hw, &lldp_cfg); 903 if (ret) 904 return ret; 905 906 /* Get the LLDP AdminStatus for the current port */ 907 adminstatus = lldp_cfg.adminstatus >> (hw->port * 4); 908 adminstatus &= 0xF; 909 910 /* LLDP agent disabled */ 911 if (!adminstatus) { 912 hw->dcbx_status = I40E_DCBX_STATUS_DISABLED; 913 return ret; 914 } 915 916 /* Get DCBX status */ 917 ret = i40e_get_dcbx_status(hw, &hw->dcbx_status); 918 if (ret) 919 return ret; 920 921 /* Check the DCBX Status */ 922 switch (hw->dcbx_status) { 923 case I40E_DCBX_STATUS_DONE: 924 case I40E_DCBX_STATUS_IN_PROGRESS: 925 /* Get current DCBX configuration */ 926 ret = i40e_get_dcb_config(hw); 927 if (ret) 928 return ret; 929 break; 930 case I40E_DCBX_STATUS_DISABLED: 931 return ret; 932 case I40E_DCBX_STATUS_NOT_STARTED: 933 case I40E_DCBX_STATUS_MULTIPLE_PEERS: 934 default: 935 break; 936 } 937 938 /* Configure the LLDP MIB change event */ 939 ret = i40e_aq_cfg_lldp_mib_change_event(hw, true, NULL); 940 if (ret) 941 return ret; 942 943 return ret; 944 } 945 946 /** 947 * i40e_read_lldp_cfg - read LLDP Configuration data from NVM 948 * @hw: pointer to the HW structure 949 * @lldp_cfg: pointer to hold lldp configuration variables 950 * 951 * Reads the LLDP configuration data from NVM 952 **/ 953 i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw, 954 struct i40e_lldp_variables *lldp_cfg) 955 { 956 i40e_status ret = 0; 957 u32 offset = (2 * I40E_NVM_LLDP_CFG_PTR); 958 959 if (!lldp_cfg) 960 return I40E_ERR_PARAM; 961 962 ret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); 963 if (ret) 964 goto err_lldp_cfg; 965 966 ret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset, 967 sizeof(struct i40e_lldp_variables), 968 (u8 *)lldp_cfg, 969 true, NULL); 970 i40e_release_nvm(hw); 971 972 err_lldp_cfg: 973 return ret; 974 } 975