1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include "i40e_virtchnl.h" 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_A: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 case I40E_DEV_ID_10G_BASE_T: 54 hw->mac.type = I40E_MAC_XL710; 55 break; 56 case I40E_DEV_ID_VF: 57 case I40E_DEV_ID_VF_HV: 58 hw->mac.type = I40E_MAC_VF; 59 break; 60 default: 61 hw->mac.type = I40E_MAC_GENERIC; 62 break; 63 } 64 } else { 65 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 66 } 67 68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 69 hw->mac.type, status); 70 return status; 71 } 72 73 /** 74 * i40e_debug_aq 75 * @hw: debug mask related to admin queue 76 * @mask: debug mask 77 * @desc: pointer to admin queue descriptor 78 * @buffer: pointer to command buffer 79 * @buf_len: max length of buffer 80 * 81 * Dumps debug log about adminq command with descriptor contents. 82 **/ 83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 84 void *buffer, u16 buf_len) 85 { 86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 87 u16 len = le16_to_cpu(aq_desc->datalen); 88 u8 *aq_buffer = (u8 *)buffer; 89 u32 data[4]; 90 u32 i = 0; 91 92 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 93 return; 94 95 i40e_debug(hw, mask, 96 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 97 aq_desc->opcode, aq_desc->flags, aq_desc->datalen, 98 aq_desc->retval); 99 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 100 aq_desc->cookie_high, aq_desc->cookie_low); 101 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 102 aq_desc->params.internal.param0, 103 aq_desc->params.internal.param1); 104 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 105 aq_desc->params.external.addr_high, 106 aq_desc->params.external.addr_low); 107 108 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 109 memset(data, 0, sizeof(data)); 110 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 111 if (buf_len < len) 112 len = buf_len; 113 for (i = 0; i < len; i++) { 114 data[((i % 16) / 4)] |= 115 ((u32)aq_buffer[i]) << (8 * (i % 4)); 116 if ((i % 16) == 15) { 117 i40e_debug(hw, mask, 118 "\t0x%04X %08X %08X %08X %08X\n", 119 i - 15, data[0], data[1], data[2], 120 data[3]); 121 memset(data, 0, sizeof(data)); 122 } 123 } 124 if ((i % 16) != 0) 125 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n", 126 i - (i % 16), data[0], data[1], data[2], 127 data[3]); 128 } 129 } 130 131 /** 132 * i40e_check_asq_alive 133 * @hw: pointer to the hw struct 134 * 135 * Returns true if Queue is enabled else false. 136 **/ 137 bool i40e_check_asq_alive(struct i40e_hw *hw) 138 { 139 if (hw->aq.asq.len) 140 return !!(rd32(hw, hw->aq.asq.len) & 141 I40E_PF_ATQLEN_ATQENABLE_MASK); 142 else 143 return false; 144 } 145 146 /** 147 * i40e_aq_queue_shutdown 148 * @hw: pointer to the hw struct 149 * @unloading: is the driver unloading itself 150 * 151 * Tell the Firmware that we're shutting down the AdminQ and whether 152 * or not the driver is unloading as well. 153 **/ 154 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 155 bool unloading) 156 { 157 struct i40e_aq_desc desc; 158 struct i40e_aqc_queue_shutdown *cmd = 159 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 160 i40e_status status; 161 162 i40e_fill_default_direct_cmd_desc(&desc, 163 i40e_aqc_opc_queue_shutdown); 164 165 if (unloading) 166 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 167 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 168 169 return status; 170 } 171 172 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 173 * hardware to a bit-field that can be used by SW to more easily determine the 174 * packet type. 175 * 176 * Macros are used to shorten the table lines and make this table human 177 * readable. 178 * 179 * We store the PTYPE in the top byte of the bit field - this is just so that 180 * we can check that the table doesn't have a row missing, as the index into 181 * the table should be the PTYPE. 182 * 183 * Typical work flow: 184 * 185 * IF NOT i40e_ptype_lookup[ptype].known 186 * THEN 187 * Packet is unknown 188 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 189 * Use the rest of the fields to look at the tunnels, inner protocols, etc 190 * ELSE 191 * Use the enum i40e_rx_l2_ptype to decode the packet type 192 * ENDIF 193 */ 194 195 /* macro to make the table lines short */ 196 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 197 { PTYPE, \ 198 1, \ 199 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 200 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 201 I40E_RX_PTYPE_##OUTER_FRAG, \ 202 I40E_RX_PTYPE_TUNNEL_##T, \ 203 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 204 I40E_RX_PTYPE_##TEF, \ 205 I40E_RX_PTYPE_INNER_PROT_##I, \ 206 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 207 208 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 209 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 210 211 /* shorter macros makes the table fit but are terse */ 212 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 213 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 214 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 215 216 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 217 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 218 /* L2 Packet types */ 219 I40E_PTT_UNUSED_ENTRY(0), 220 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 221 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 222 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 223 I40E_PTT_UNUSED_ENTRY(4), 224 I40E_PTT_UNUSED_ENTRY(5), 225 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 226 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 227 I40E_PTT_UNUSED_ENTRY(8), 228 I40E_PTT_UNUSED_ENTRY(9), 229 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 230 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 231 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 232 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 233 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 234 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 235 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 236 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 237 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 238 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 239 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 240 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 241 242 /* Non Tunneled IPv4 */ 243 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 244 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 245 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 246 I40E_PTT_UNUSED_ENTRY(25), 247 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 248 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 249 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 250 251 /* IPv4 --> IPv4 */ 252 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 253 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 254 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 255 I40E_PTT_UNUSED_ENTRY(32), 256 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 257 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 258 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 259 260 /* IPv4 --> IPv6 */ 261 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 262 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 263 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 264 I40E_PTT_UNUSED_ENTRY(39), 265 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 266 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 267 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 268 269 /* IPv4 --> GRE/NAT */ 270 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 271 272 /* IPv4 --> GRE/NAT --> IPv4 */ 273 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 274 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 275 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 276 I40E_PTT_UNUSED_ENTRY(47), 277 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 278 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 279 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 280 281 /* IPv4 --> GRE/NAT --> IPv6 */ 282 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 283 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 284 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 285 I40E_PTT_UNUSED_ENTRY(54), 286 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 287 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 288 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 289 290 /* IPv4 --> GRE/NAT --> MAC */ 291 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 292 293 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 294 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 295 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 296 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 297 I40E_PTT_UNUSED_ENTRY(62), 298 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 299 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 300 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 301 302 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 303 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 304 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 305 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 306 I40E_PTT_UNUSED_ENTRY(69), 307 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 308 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 309 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 310 311 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 312 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 313 314 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 315 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 316 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 317 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 318 I40E_PTT_UNUSED_ENTRY(77), 319 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 320 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 321 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 322 323 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 324 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 325 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 326 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 327 I40E_PTT_UNUSED_ENTRY(84), 328 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 329 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 330 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 331 332 /* Non Tunneled IPv6 */ 333 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 334 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 335 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 336 I40E_PTT_UNUSED_ENTRY(91), 337 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 338 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 339 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 340 341 /* IPv6 --> IPv4 */ 342 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 343 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 344 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 345 I40E_PTT_UNUSED_ENTRY(98), 346 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 347 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 348 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 349 350 /* IPv6 --> IPv6 */ 351 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 352 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 353 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 354 I40E_PTT_UNUSED_ENTRY(105), 355 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 356 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 357 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 358 359 /* IPv6 --> GRE/NAT */ 360 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 361 362 /* IPv6 --> GRE/NAT -> IPv4 */ 363 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 364 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 365 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 366 I40E_PTT_UNUSED_ENTRY(113), 367 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 368 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 369 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 370 371 /* IPv6 --> GRE/NAT -> IPv6 */ 372 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 373 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 374 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 375 I40E_PTT_UNUSED_ENTRY(120), 376 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 377 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 378 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 379 380 /* IPv6 --> GRE/NAT -> MAC */ 381 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 382 383 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 384 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 385 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 386 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 387 I40E_PTT_UNUSED_ENTRY(128), 388 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 389 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 390 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 391 392 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 393 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 394 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 395 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 396 I40E_PTT_UNUSED_ENTRY(135), 397 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 398 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 399 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 400 401 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 402 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 403 404 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 405 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 406 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 407 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 408 I40E_PTT_UNUSED_ENTRY(143), 409 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 410 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 411 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 412 413 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 414 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 415 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 416 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 417 I40E_PTT_UNUSED_ENTRY(150), 418 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 419 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 420 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 421 422 /* unused entries */ 423 I40E_PTT_UNUSED_ENTRY(154), 424 I40E_PTT_UNUSED_ENTRY(155), 425 I40E_PTT_UNUSED_ENTRY(156), 426 I40E_PTT_UNUSED_ENTRY(157), 427 I40E_PTT_UNUSED_ENTRY(158), 428 I40E_PTT_UNUSED_ENTRY(159), 429 430 I40E_PTT_UNUSED_ENTRY(160), 431 I40E_PTT_UNUSED_ENTRY(161), 432 I40E_PTT_UNUSED_ENTRY(162), 433 I40E_PTT_UNUSED_ENTRY(163), 434 I40E_PTT_UNUSED_ENTRY(164), 435 I40E_PTT_UNUSED_ENTRY(165), 436 I40E_PTT_UNUSED_ENTRY(166), 437 I40E_PTT_UNUSED_ENTRY(167), 438 I40E_PTT_UNUSED_ENTRY(168), 439 I40E_PTT_UNUSED_ENTRY(169), 440 441 I40E_PTT_UNUSED_ENTRY(170), 442 I40E_PTT_UNUSED_ENTRY(171), 443 I40E_PTT_UNUSED_ENTRY(172), 444 I40E_PTT_UNUSED_ENTRY(173), 445 I40E_PTT_UNUSED_ENTRY(174), 446 I40E_PTT_UNUSED_ENTRY(175), 447 I40E_PTT_UNUSED_ENTRY(176), 448 I40E_PTT_UNUSED_ENTRY(177), 449 I40E_PTT_UNUSED_ENTRY(178), 450 I40E_PTT_UNUSED_ENTRY(179), 451 452 I40E_PTT_UNUSED_ENTRY(180), 453 I40E_PTT_UNUSED_ENTRY(181), 454 I40E_PTT_UNUSED_ENTRY(182), 455 I40E_PTT_UNUSED_ENTRY(183), 456 I40E_PTT_UNUSED_ENTRY(184), 457 I40E_PTT_UNUSED_ENTRY(185), 458 I40E_PTT_UNUSED_ENTRY(186), 459 I40E_PTT_UNUSED_ENTRY(187), 460 I40E_PTT_UNUSED_ENTRY(188), 461 I40E_PTT_UNUSED_ENTRY(189), 462 463 I40E_PTT_UNUSED_ENTRY(190), 464 I40E_PTT_UNUSED_ENTRY(191), 465 I40E_PTT_UNUSED_ENTRY(192), 466 I40E_PTT_UNUSED_ENTRY(193), 467 I40E_PTT_UNUSED_ENTRY(194), 468 I40E_PTT_UNUSED_ENTRY(195), 469 I40E_PTT_UNUSED_ENTRY(196), 470 I40E_PTT_UNUSED_ENTRY(197), 471 I40E_PTT_UNUSED_ENTRY(198), 472 I40E_PTT_UNUSED_ENTRY(199), 473 474 I40E_PTT_UNUSED_ENTRY(200), 475 I40E_PTT_UNUSED_ENTRY(201), 476 I40E_PTT_UNUSED_ENTRY(202), 477 I40E_PTT_UNUSED_ENTRY(203), 478 I40E_PTT_UNUSED_ENTRY(204), 479 I40E_PTT_UNUSED_ENTRY(205), 480 I40E_PTT_UNUSED_ENTRY(206), 481 I40E_PTT_UNUSED_ENTRY(207), 482 I40E_PTT_UNUSED_ENTRY(208), 483 I40E_PTT_UNUSED_ENTRY(209), 484 485 I40E_PTT_UNUSED_ENTRY(210), 486 I40E_PTT_UNUSED_ENTRY(211), 487 I40E_PTT_UNUSED_ENTRY(212), 488 I40E_PTT_UNUSED_ENTRY(213), 489 I40E_PTT_UNUSED_ENTRY(214), 490 I40E_PTT_UNUSED_ENTRY(215), 491 I40E_PTT_UNUSED_ENTRY(216), 492 I40E_PTT_UNUSED_ENTRY(217), 493 I40E_PTT_UNUSED_ENTRY(218), 494 I40E_PTT_UNUSED_ENTRY(219), 495 496 I40E_PTT_UNUSED_ENTRY(220), 497 I40E_PTT_UNUSED_ENTRY(221), 498 I40E_PTT_UNUSED_ENTRY(222), 499 I40E_PTT_UNUSED_ENTRY(223), 500 I40E_PTT_UNUSED_ENTRY(224), 501 I40E_PTT_UNUSED_ENTRY(225), 502 I40E_PTT_UNUSED_ENTRY(226), 503 I40E_PTT_UNUSED_ENTRY(227), 504 I40E_PTT_UNUSED_ENTRY(228), 505 I40E_PTT_UNUSED_ENTRY(229), 506 507 I40E_PTT_UNUSED_ENTRY(230), 508 I40E_PTT_UNUSED_ENTRY(231), 509 I40E_PTT_UNUSED_ENTRY(232), 510 I40E_PTT_UNUSED_ENTRY(233), 511 I40E_PTT_UNUSED_ENTRY(234), 512 I40E_PTT_UNUSED_ENTRY(235), 513 I40E_PTT_UNUSED_ENTRY(236), 514 I40E_PTT_UNUSED_ENTRY(237), 515 I40E_PTT_UNUSED_ENTRY(238), 516 I40E_PTT_UNUSED_ENTRY(239), 517 518 I40E_PTT_UNUSED_ENTRY(240), 519 I40E_PTT_UNUSED_ENTRY(241), 520 I40E_PTT_UNUSED_ENTRY(242), 521 I40E_PTT_UNUSED_ENTRY(243), 522 I40E_PTT_UNUSED_ENTRY(244), 523 I40E_PTT_UNUSED_ENTRY(245), 524 I40E_PTT_UNUSED_ENTRY(246), 525 I40E_PTT_UNUSED_ENTRY(247), 526 I40E_PTT_UNUSED_ENTRY(248), 527 I40E_PTT_UNUSED_ENTRY(249), 528 529 I40E_PTT_UNUSED_ENTRY(250), 530 I40E_PTT_UNUSED_ENTRY(251), 531 I40E_PTT_UNUSED_ENTRY(252), 532 I40E_PTT_UNUSED_ENTRY(253), 533 I40E_PTT_UNUSED_ENTRY(254), 534 I40E_PTT_UNUSED_ENTRY(255) 535 }; 536 537 538 /** 539 * i40e_init_shared_code - Initialize the shared code 540 * @hw: pointer to hardware structure 541 * 542 * This assigns the MAC type and PHY code and inits the NVM. 543 * Does not touch the hardware. This function must be called prior to any 544 * other function in the shared code. The i40e_hw structure should be 545 * memset to 0 prior to calling this function. The following fields in 546 * hw structure should be filled in prior to calling this function: 547 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 548 * subsystem_vendor_id, and revision_id 549 **/ 550 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 551 { 552 i40e_status status = 0; 553 u32 port, ari, func_rid; 554 555 i40e_set_mac_type(hw); 556 557 switch (hw->mac.type) { 558 case I40E_MAC_XL710: 559 break; 560 default: 561 return I40E_ERR_DEVICE_NOT_SUPPORTED; 562 } 563 564 hw->phy.get_link_info = true; 565 566 /* Determine port number and PF number*/ 567 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 568 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 569 hw->port = (u8)port; 570 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 571 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 572 func_rid = rd32(hw, I40E_PF_FUNC_RID); 573 if (ari) 574 hw->pf_id = (u8)(func_rid & 0xff); 575 else 576 hw->pf_id = (u8)(func_rid & 0x7); 577 578 status = i40e_init_nvm(hw); 579 return status; 580 } 581 582 /** 583 * i40e_aq_mac_address_read - Retrieve the MAC addresses 584 * @hw: pointer to the hw struct 585 * @flags: a return indicator of what addresses were added to the addr store 586 * @addrs: the requestor's mac addr store 587 * @cmd_details: pointer to command details structure or NULL 588 **/ 589 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 590 u16 *flags, 591 struct i40e_aqc_mac_address_read_data *addrs, 592 struct i40e_asq_cmd_details *cmd_details) 593 { 594 struct i40e_aq_desc desc; 595 struct i40e_aqc_mac_address_read *cmd_data = 596 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 597 i40e_status status; 598 599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 601 602 status = i40e_asq_send_command(hw, &desc, addrs, 603 sizeof(*addrs), cmd_details); 604 *flags = le16_to_cpu(cmd_data->command_flags); 605 606 return status; 607 } 608 609 /** 610 * i40e_aq_mac_address_write - Change the MAC addresses 611 * @hw: pointer to the hw struct 612 * @flags: indicates which MAC to be written 613 * @mac_addr: address to write 614 * @cmd_details: pointer to command details structure or NULL 615 **/ 616 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 617 u16 flags, u8 *mac_addr, 618 struct i40e_asq_cmd_details *cmd_details) 619 { 620 struct i40e_aq_desc desc; 621 struct i40e_aqc_mac_address_write *cmd_data = 622 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 623 i40e_status status; 624 625 i40e_fill_default_direct_cmd_desc(&desc, 626 i40e_aqc_opc_mac_address_write); 627 cmd_data->command_flags = cpu_to_le16(flags); 628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 630 ((u32)mac_addr[3] << 16) | 631 ((u32)mac_addr[4] << 8) | 632 mac_addr[5]); 633 634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 635 636 return status; 637 } 638 639 /** 640 * i40e_get_mac_addr - get MAC address 641 * @hw: pointer to the HW structure 642 * @mac_addr: pointer to MAC address 643 * 644 * Reads the adapter's MAC address from register 645 **/ 646 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 647 { 648 struct i40e_aqc_mac_address_read_data addrs; 649 i40e_status status; 650 u16 flags = 0; 651 652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 653 654 if (flags & I40E_AQC_LAN_ADDR_VALID) 655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 656 657 return status; 658 } 659 660 /** 661 * i40e_get_port_mac_addr - get Port MAC address 662 * @hw: pointer to the HW structure 663 * @mac_addr: pointer to Port MAC address 664 * 665 * Reads the adapter's Port MAC address 666 **/ 667 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 668 { 669 struct i40e_aqc_mac_address_read_data addrs; 670 i40e_status status; 671 u16 flags = 0; 672 673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 674 if (status) 675 return status; 676 677 if (flags & I40E_AQC_PORT_ADDR_VALID) 678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 679 else 680 status = I40E_ERR_INVALID_MAC_ADDR; 681 682 return status; 683 } 684 685 /** 686 * i40e_pre_tx_queue_cfg - pre tx queue configure 687 * @hw: pointer to the HW structure 688 * @queue: target pf queue index 689 * @enable: state change request 690 * 691 * Handles hw requirement to indicate intention to enable 692 * or disable target queue. 693 **/ 694 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 695 { 696 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 697 u32 reg_block = 0; 698 u32 reg_val; 699 700 if (abs_queue_idx >= 128) { 701 reg_block = abs_queue_idx / 128; 702 abs_queue_idx %= 128; 703 } 704 705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 708 709 if (enable) 710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 711 else 712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 713 714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 715 } 716 #ifdef I40E_FCOE 717 718 /** 719 * i40e_get_san_mac_addr - get SAN MAC address 720 * @hw: pointer to the HW structure 721 * @mac_addr: pointer to SAN MAC address 722 * 723 * Reads the adapter's SAN MAC address from NVM 724 **/ 725 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 726 { 727 struct i40e_aqc_mac_address_read_data addrs; 728 i40e_status status; 729 u16 flags = 0; 730 731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 732 if (status) 733 return status; 734 735 if (flags & I40E_AQC_SAN_ADDR_VALID) 736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac)); 737 else 738 status = I40E_ERR_INVALID_MAC_ADDR; 739 740 return status; 741 } 742 #endif 743 744 /** 745 * i40e_get_media_type - Gets media type 746 * @hw: pointer to the hardware structure 747 **/ 748 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 749 { 750 enum i40e_media_type media; 751 752 switch (hw->phy.link_info.phy_type) { 753 case I40E_PHY_TYPE_10GBASE_SR: 754 case I40E_PHY_TYPE_10GBASE_LR: 755 case I40E_PHY_TYPE_1000BASE_SX: 756 case I40E_PHY_TYPE_1000BASE_LX: 757 case I40E_PHY_TYPE_40GBASE_SR4: 758 case I40E_PHY_TYPE_40GBASE_LR4: 759 media = I40E_MEDIA_TYPE_FIBER; 760 break; 761 case I40E_PHY_TYPE_100BASE_TX: 762 case I40E_PHY_TYPE_1000BASE_T: 763 case I40E_PHY_TYPE_10GBASE_T: 764 media = I40E_MEDIA_TYPE_BASET; 765 break; 766 case I40E_PHY_TYPE_10GBASE_CR1_CU: 767 case I40E_PHY_TYPE_40GBASE_CR4_CU: 768 case I40E_PHY_TYPE_10GBASE_CR1: 769 case I40E_PHY_TYPE_40GBASE_CR4: 770 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 771 media = I40E_MEDIA_TYPE_DA; 772 break; 773 case I40E_PHY_TYPE_1000BASE_KX: 774 case I40E_PHY_TYPE_10GBASE_KX4: 775 case I40E_PHY_TYPE_10GBASE_KR: 776 case I40E_PHY_TYPE_40GBASE_KR4: 777 media = I40E_MEDIA_TYPE_BACKPLANE; 778 break; 779 case I40E_PHY_TYPE_SGMII: 780 case I40E_PHY_TYPE_XAUI: 781 case I40E_PHY_TYPE_XFI: 782 case I40E_PHY_TYPE_XLAUI: 783 case I40E_PHY_TYPE_XLPPI: 784 default: 785 media = I40E_MEDIA_TYPE_UNKNOWN; 786 break; 787 } 788 789 return media; 790 } 791 792 #define I40E_PF_RESET_WAIT_COUNT_A0 200 793 #define I40E_PF_RESET_WAIT_COUNT 110 794 /** 795 * i40e_pf_reset - Reset the PF 796 * @hw: pointer to the hardware structure 797 * 798 * Assuming someone else has triggered a global reset, 799 * assure the global reset is complete and then reset the PF 800 **/ 801 i40e_status i40e_pf_reset(struct i40e_hw *hw) 802 { 803 u32 cnt = 0; 804 u32 cnt1 = 0; 805 u32 reg = 0; 806 u32 grst_del; 807 808 /* Poll for Global Reset steady state in case of recent GRST. 809 * The grst delay value is in 100ms units, and we'll wait a 810 * couple counts longer to be sure we don't just miss the end. 811 */ 812 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK 813 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 814 for (cnt = 0; cnt < grst_del + 2; cnt++) { 815 reg = rd32(hw, I40E_GLGEN_RSTAT); 816 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 817 break; 818 msleep(100); 819 } 820 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 821 hw_dbg(hw, "Global reset polling failed to complete.\n"); 822 return I40E_ERR_RESET_FAILED; 823 } 824 825 /* Now Wait for the FW to be ready */ 826 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 827 reg = rd32(hw, I40E_GLNVM_ULD); 828 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 829 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 830 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 831 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 832 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 833 break; 834 } 835 usleep_range(10000, 20000); 836 } 837 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 838 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 839 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 840 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 841 return I40E_ERR_RESET_FAILED; 842 } 843 844 /* If there was a Global Reset in progress when we got here, 845 * we don't need to do the PF Reset 846 */ 847 if (!cnt) { 848 if (hw->revision_id == 0) 849 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 850 else 851 cnt = I40E_PF_RESET_WAIT_COUNT; 852 reg = rd32(hw, I40E_PFGEN_CTRL); 853 wr32(hw, I40E_PFGEN_CTRL, 854 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 855 for (; cnt; cnt--) { 856 reg = rd32(hw, I40E_PFGEN_CTRL); 857 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 858 break; 859 usleep_range(1000, 2000); 860 } 861 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 862 hw_dbg(hw, "PF reset polling failed to complete.\n"); 863 return I40E_ERR_RESET_FAILED; 864 } 865 } 866 867 i40e_clear_pxe_mode(hw); 868 869 return 0; 870 } 871 872 /** 873 * i40e_clear_hw - clear out any left over hw state 874 * @hw: pointer to the hw struct 875 * 876 * Clear queues and interrupts, typically called at init time, 877 * but after the capabilities have been found so we know how many 878 * queues and msix vectors have been allocated. 879 **/ 880 void i40e_clear_hw(struct i40e_hw *hw) 881 { 882 u32 num_queues, base_queue; 883 u32 num_pf_int; 884 u32 num_vf_int; 885 u32 num_vfs; 886 u32 i, j; 887 u32 val; 888 u32 eol = 0x7ff; 889 890 /* get number of interrupts, queues, and vfs */ 891 val = rd32(hw, I40E_GLPCI_CNF2); 892 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 893 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 894 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 895 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 896 897 val = rd32(hw, I40E_PFLAN_QALLOC); 898 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 899 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 900 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 901 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 902 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 903 num_queues = (j - base_queue) + 1; 904 else 905 num_queues = 0; 906 907 val = rd32(hw, I40E_PF_VT_PFALLOC); 908 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 909 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 910 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 911 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 912 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 913 num_vfs = (j - i) + 1; 914 else 915 num_vfs = 0; 916 917 /* stop all the interrupts */ 918 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 919 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 920 for (i = 0; i < num_pf_int - 2; i++) 921 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 922 923 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 924 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 925 wr32(hw, I40E_PFINT_LNKLST0, val); 926 for (i = 0; i < num_pf_int - 2; i++) 927 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 928 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 929 for (i = 0; i < num_vfs; i++) 930 wr32(hw, I40E_VPINT_LNKLST0(i), val); 931 for (i = 0; i < num_vf_int - 2; i++) 932 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 933 934 /* warn the HW of the coming Tx disables */ 935 for (i = 0; i < num_queues; i++) { 936 u32 abs_queue_idx = base_queue + i; 937 u32 reg_block = 0; 938 939 if (abs_queue_idx >= 128) { 940 reg_block = abs_queue_idx / 128; 941 abs_queue_idx %= 128; 942 } 943 944 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 945 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 946 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 947 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 948 949 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 950 } 951 udelay(400); 952 953 /* stop all the queues */ 954 for (i = 0; i < num_queues; i++) { 955 wr32(hw, I40E_QINT_TQCTL(i), 0); 956 wr32(hw, I40E_QTX_ENA(i), 0); 957 wr32(hw, I40E_QINT_RQCTL(i), 0); 958 wr32(hw, I40E_QRX_ENA(i), 0); 959 } 960 961 /* short wait for all queue disables to settle */ 962 udelay(50); 963 } 964 965 /** 966 * i40e_clear_pxe_mode - clear pxe operations mode 967 * @hw: pointer to the hw struct 968 * 969 * Make sure all PXE mode settings are cleared, including things 970 * like descriptor fetch/write-back mode. 971 **/ 972 void i40e_clear_pxe_mode(struct i40e_hw *hw) 973 { 974 u32 reg; 975 976 if (i40e_check_asq_alive(hw)) 977 i40e_aq_clear_pxe_mode(hw, NULL); 978 979 /* Clear single descriptor fetch/write-back mode */ 980 reg = rd32(hw, I40E_GLLAN_RCTL_0); 981 982 if (hw->revision_id == 0) { 983 /* As a work around clear PXE_MODE instead of setting it */ 984 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 985 } else { 986 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 987 } 988 } 989 990 /** 991 * i40e_led_is_mine - helper to find matching led 992 * @hw: pointer to the hw struct 993 * @idx: index into GPIO registers 994 * 995 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 996 */ 997 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 998 { 999 u32 gpio_val = 0; 1000 u32 port; 1001 1002 if (!hw->func_caps.led[idx]) 1003 return 0; 1004 1005 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1006 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1007 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1008 1009 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1010 * if it is not our port then ignore 1011 */ 1012 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1013 (port != hw->port)) 1014 return 0; 1015 1016 return gpio_val; 1017 } 1018 1019 #define I40E_LED0 22 1020 #define I40E_LINK_ACTIVITY 0xC 1021 1022 /** 1023 * i40e_led_get - return current on/off mode 1024 * @hw: pointer to the hw struct 1025 * 1026 * The value returned is the 'mode' field as defined in the 1027 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1028 * values are variations of possible behaviors relating to 1029 * blink, link, and wire. 1030 **/ 1031 u32 i40e_led_get(struct i40e_hw *hw) 1032 { 1033 u32 mode = 0; 1034 int i; 1035 1036 /* as per the documentation GPIO 22-29 are the LED 1037 * GPIO pins named LED0..LED7 1038 */ 1039 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1040 u32 gpio_val = i40e_led_is_mine(hw, i); 1041 1042 if (!gpio_val) 1043 continue; 1044 1045 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1046 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1047 break; 1048 } 1049 1050 return mode; 1051 } 1052 1053 /** 1054 * i40e_led_set - set new on/off mode 1055 * @hw: pointer to the hw struct 1056 * @mode: 0=off, 0xf=on (else see manual for mode details) 1057 * @blink: true if the LED should blink when on, false if steady 1058 * 1059 * if this function is used to turn on the blink it should 1060 * be used to disable the blink when restoring the original state. 1061 **/ 1062 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1063 { 1064 int i; 1065 1066 if (mode & 0xfffffff0) 1067 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1068 1069 /* as per the documentation GPIO 22-29 are the LED 1070 * GPIO pins named LED0..LED7 1071 */ 1072 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1073 u32 gpio_val = i40e_led_is_mine(hw, i); 1074 1075 if (!gpio_val) 1076 continue; 1077 1078 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1079 /* this & is a bit of paranoia, but serves as a range check */ 1080 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1081 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1082 1083 if (mode == I40E_LINK_ACTIVITY) 1084 blink = false; 1085 1086 gpio_val |= (blink ? 1 : 0) << 1087 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT; 1088 1089 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1090 break; 1091 } 1092 } 1093 1094 /* Admin command wrappers */ 1095 1096 /** 1097 * i40e_aq_get_phy_capabilities 1098 * @hw: pointer to the hw struct 1099 * @abilities: structure for PHY capabilities to be filled 1100 * @qualified_modules: report Qualified Modules 1101 * @report_init: report init capabilities (active are default) 1102 * @cmd_details: pointer to command details structure or NULL 1103 * 1104 * Returns the various PHY abilities supported on the Port. 1105 **/ 1106 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1107 bool qualified_modules, bool report_init, 1108 struct i40e_aq_get_phy_abilities_resp *abilities, 1109 struct i40e_asq_cmd_details *cmd_details) 1110 { 1111 struct i40e_aq_desc desc; 1112 i40e_status status; 1113 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1114 1115 if (!abilities) 1116 return I40E_ERR_PARAM; 1117 1118 i40e_fill_default_direct_cmd_desc(&desc, 1119 i40e_aqc_opc_get_phy_abilities); 1120 1121 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1122 if (abilities_size > I40E_AQ_LARGE_BUF) 1123 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1124 1125 if (qualified_modules) 1126 desc.params.external.param0 |= 1127 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1128 1129 if (report_init) 1130 desc.params.external.param0 |= 1131 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1132 1133 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1134 cmd_details); 1135 1136 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1137 status = I40E_ERR_UNKNOWN_PHY; 1138 1139 return status; 1140 } 1141 1142 /** 1143 * i40e_aq_set_phy_config 1144 * @hw: pointer to the hw struct 1145 * @config: structure with PHY configuration to be set 1146 * @cmd_details: pointer to command details structure or NULL 1147 * 1148 * Set the various PHY configuration parameters 1149 * supported on the Port.One or more of the Set PHY config parameters may be 1150 * ignored in an MFP mode as the PF may not have the privilege to set some 1151 * of the PHY Config parameters. This status will be indicated by the 1152 * command response. 1153 **/ 1154 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1155 struct i40e_aq_set_phy_config *config, 1156 struct i40e_asq_cmd_details *cmd_details) 1157 { 1158 struct i40e_aq_desc desc; 1159 struct i40e_aq_set_phy_config *cmd = 1160 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1161 enum i40e_status_code status; 1162 1163 if (!config) 1164 return I40E_ERR_PARAM; 1165 1166 i40e_fill_default_direct_cmd_desc(&desc, 1167 i40e_aqc_opc_set_phy_config); 1168 1169 *cmd = *config; 1170 1171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1172 1173 return status; 1174 } 1175 1176 /** 1177 * i40e_set_fc 1178 * @hw: pointer to the hw struct 1179 * 1180 * Set the requested flow control mode using set_phy_config. 1181 **/ 1182 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1183 bool atomic_restart) 1184 { 1185 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1186 struct i40e_aq_get_phy_abilities_resp abilities; 1187 struct i40e_aq_set_phy_config config; 1188 enum i40e_status_code status; 1189 u8 pause_mask = 0x0; 1190 1191 *aq_failures = 0x0; 1192 1193 switch (fc_mode) { 1194 case I40E_FC_FULL: 1195 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1196 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1197 break; 1198 case I40E_FC_RX_PAUSE: 1199 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1200 break; 1201 case I40E_FC_TX_PAUSE: 1202 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 /* Get the current phy config */ 1209 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1210 NULL); 1211 if (status) { 1212 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1213 return status; 1214 } 1215 1216 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1217 /* clear the old pause settings */ 1218 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1219 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1220 /* set the new abilities */ 1221 config.abilities |= pause_mask; 1222 /* If the abilities have changed, then set the new config */ 1223 if (config.abilities != abilities.abilities) { 1224 /* Auto restart link so settings take effect */ 1225 if (atomic_restart) 1226 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1227 /* Copy over all the old settings */ 1228 config.phy_type = abilities.phy_type; 1229 config.link_speed = abilities.link_speed; 1230 config.eee_capability = abilities.eee_capability; 1231 config.eeer = abilities.eeer_val; 1232 config.low_power_ctrl = abilities.d3_lpan; 1233 status = i40e_aq_set_phy_config(hw, &config, NULL); 1234 1235 if (status) 1236 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1237 } 1238 /* Update the link info */ 1239 status = i40e_update_link_info(hw, true); 1240 if (status) { 1241 /* Wait a little bit (on 40G cards it sometimes takes a really 1242 * long time for link to come back from the atomic reset) 1243 * and try once more 1244 */ 1245 msleep(1000); 1246 status = i40e_update_link_info(hw, true); 1247 } 1248 if (status) 1249 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1250 1251 return status; 1252 } 1253 1254 /** 1255 * i40e_aq_clear_pxe_mode 1256 * @hw: pointer to the hw struct 1257 * @cmd_details: pointer to command details structure or NULL 1258 * 1259 * Tell the firmware that the driver is taking over from PXE 1260 **/ 1261 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1262 struct i40e_asq_cmd_details *cmd_details) 1263 { 1264 i40e_status status; 1265 struct i40e_aq_desc desc; 1266 struct i40e_aqc_clear_pxe *cmd = 1267 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1268 1269 i40e_fill_default_direct_cmd_desc(&desc, 1270 i40e_aqc_opc_clear_pxe_mode); 1271 1272 cmd->rx_cnt = 0x2; 1273 1274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1275 1276 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1277 1278 return status; 1279 } 1280 1281 /** 1282 * i40e_aq_set_link_restart_an 1283 * @hw: pointer to the hw struct 1284 * @enable_link: if true: enable link, if false: disable link 1285 * @cmd_details: pointer to command details structure or NULL 1286 * 1287 * Sets up the link and restarts the Auto-Negotiation over the link. 1288 **/ 1289 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1290 bool enable_link, 1291 struct i40e_asq_cmd_details *cmd_details) 1292 { 1293 struct i40e_aq_desc desc; 1294 struct i40e_aqc_set_link_restart_an *cmd = 1295 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1296 i40e_status status; 1297 1298 i40e_fill_default_direct_cmd_desc(&desc, 1299 i40e_aqc_opc_set_link_restart_an); 1300 1301 cmd->command = I40E_AQ_PHY_RESTART_AN; 1302 if (enable_link) 1303 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1304 else 1305 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1306 1307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1308 1309 return status; 1310 } 1311 1312 /** 1313 * i40e_aq_get_link_info 1314 * @hw: pointer to the hw struct 1315 * @enable_lse: enable/disable LinkStatusEvent reporting 1316 * @link: pointer to link status structure - optional 1317 * @cmd_details: pointer to command details structure or NULL 1318 * 1319 * Returns the link status of the adapter. 1320 **/ 1321 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1322 bool enable_lse, struct i40e_link_status *link, 1323 struct i40e_asq_cmd_details *cmd_details) 1324 { 1325 struct i40e_aq_desc desc; 1326 struct i40e_aqc_get_link_status *resp = 1327 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1328 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1329 i40e_status status; 1330 bool tx_pause, rx_pause; 1331 u16 command_flags; 1332 1333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1334 1335 if (enable_lse) 1336 command_flags = I40E_AQ_LSE_ENABLE; 1337 else 1338 command_flags = I40E_AQ_LSE_DISABLE; 1339 resp->command_flags = cpu_to_le16(command_flags); 1340 1341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1342 1343 if (status) 1344 goto aq_get_link_info_exit; 1345 1346 /* save off old link status information */ 1347 hw->phy.link_info_old = *hw_link_info; 1348 1349 /* update link status */ 1350 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1351 hw->phy.media_type = i40e_get_media_type(hw); 1352 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1353 hw_link_info->link_info = resp->link_info; 1354 hw_link_info->an_info = resp->an_info; 1355 hw_link_info->ext_info = resp->ext_info; 1356 hw_link_info->loopback = resp->loopback; 1357 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1358 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1359 1360 /* update fc info */ 1361 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1362 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1363 if (tx_pause & rx_pause) 1364 hw->fc.current_mode = I40E_FC_FULL; 1365 else if (tx_pause) 1366 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1367 else if (rx_pause) 1368 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1369 else 1370 hw->fc.current_mode = I40E_FC_NONE; 1371 1372 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1373 hw_link_info->crc_enable = true; 1374 else 1375 hw_link_info->crc_enable = false; 1376 1377 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1378 hw_link_info->lse_enable = true; 1379 else 1380 hw_link_info->lse_enable = false; 1381 1382 /* save link status information */ 1383 if (link) 1384 *link = *hw_link_info; 1385 1386 /* flag cleared so helper functions don't call AQ again */ 1387 hw->phy.get_link_info = false; 1388 1389 aq_get_link_info_exit: 1390 return status; 1391 } 1392 1393 /** 1394 * i40e_update_link_info 1395 * @hw: pointer to the hw struct 1396 * @enable_lse: enable/disable LinkStatusEvent reporting 1397 * 1398 * Returns the link status of the adapter 1399 **/ 1400 i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse) 1401 { 1402 struct i40e_aq_get_phy_abilities_resp abilities; 1403 i40e_status status; 1404 1405 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL); 1406 if (status) 1407 return status; 1408 1409 status = i40e_aq_get_phy_capabilities(hw, false, false, 1410 &abilities, NULL); 1411 if (status) 1412 return status; 1413 1414 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED) 1415 hw->phy.link_info.an_enabled = true; 1416 else 1417 hw->phy.link_info.an_enabled = false; 1418 1419 return status; 1420 } 1421 1422 /** 1423 * i40e_aq_set_phy_int_mask 1424 * @hw: pointer to the hw struct 1425 * @mask: interrupt mask to be set 1426 * @cmd_details: pointer to command details structure or NULL 1427 * 1428 * Set link interrupt mask. 1429 **/ 1430 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1431 u16 mask, 1432 struct i40e_asq_cmd_details *cmd_details) 1433 { 1434 struct i40e_aq_desc desc; 1435 struct i40e_aqc_set_phy_int_mask *cmd = 1436 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1437 i40e_status status; 1438 1439 i40e_fill_default_direct_cmd_desc(&desc, 1440 i40e_aqc_opc_set_phy_int_mask); 1441 1442 cmd->event_mask = cpu_to_le16(mask); 1443 1444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1445 1446 return status; 1447 } 1448 1449 /** 1450 * i40e_aq_add_vsi 1451 * @hw: pointer to the hw struct 1452 * @vsi_ctx: pointer to a vsi context struct 1453 * @cmd_details: pointer to command details structure or NULL 1454 * 1455 * Add a VSI context to the hardware. 1456 **/ 1457 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1458 struct i40e_vsi_context *vsi_ctx, 1459 struct i40e_asq_cmd_details *cmd_details) 1460 { 1461 struct i40e_aq_desc desc; 1462 struct i40e_aqc_add_get_update_vsi *cmd = 1463 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1464 struct i40e_aqc_add_get_update_vsi_completion *resp = 1465 (struct i40e_aqc_add_get_update_vsi_completion *) 1466 &desc.params.raw; 1467 i40e_status status; 1468 1469 i40e_fill_default_direct_cmd_desc(&desc, 1470 i40e_aqc_opc_add_vsi); 1471 1472 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1473 cmd->connection_type = vsi_ctx->connection_type; 1474 cmd->vf_id = vsi_ctx->vf_num; 1475 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1476 1477 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1478 1479 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1480 sizeof(vsi_ctx->info), cmd_details); 1481 1482 if (status) 1483 goto aq_add_vsi_exit; 1484 1485 vsi_ctx->seid = le16_to_cpu(resp->seid); 1486 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1487 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1488 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1489 1490 aq_add_vsi_exit: 1491 return status; 1492 } 1493 1494 /** 1495 * i40e_aq_set_vsi_unicast_promiscuous 1496 * @hw: pointer to the hw struct 1497 * @seid: vsi number 1498 * @set: set unicast promiscuous enable/disable 1499 * @cmd_details: pointer to command details structure or NULL 1500 **/ 1501 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1502 u16 seid, bool set, 1503 struct i40e_asq_cmd_details *cmd_details) 1504 { 1505 struct i40e_aq_desc desc; 1506 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1507 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1508 i40e_status status; 1509 u16 flags = 0; 1510 1511 i40e_fill_default_direct_cmd_desc(&desc, 1512 i40e_aqc_opc_set_vsi_promiscuous_modes); 1513 1514 if (set) 1515 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1516 1517 cmd->promiscuous_flags = cpu_to_le16(flags); 1518 1519 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1520 1521 cmd->seid = cpu_to_le16(seid); 1522 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1523 1524 return status; 1525 } 1526 1527 /** 1528 * i40e_aq_set_vsi_multicast_promiscuous 1529 * @hw: pointer to the hw struct 1530 * @seid: vsi number 1531 * @set: set multicast promiscuous enable/disable 1532 * @cmd_details: pointer to command details structure or NULL 1533 **/ 1534 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1535 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1536 { 1537 struct i40e_aq_desc desc; 1538 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1539 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1540 i40e_status status; 1541 u16 flags = 0; 1542 1543 i40e_fill_default_direct_cmd_desc(&desc, 1544 i40e_aqc_opc_set_vsi_promiscuous_modes); 1545 1546 if (set) 1547 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1548 1549 cmd->promiscuous_flags = cpu_to_le16(flags); 1550 1551 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1552 1553 cmd->seid = cpu_to_le16(seid); 1554 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1555 1556 return status; 1557 } 1558 1559 /** 1560 * i40e_aq_set_vsi_broadcast 1561 * @hw: pointer to the hw struct 1562 * @seid: vsi number 1563 * @set_filter: true to set filter, false to clear filter 1564 * @cmd_details: pointer to command details structure or NULL 1565 * 1566 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1567 **/ 1568 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1569 u16 seid, bool set_filter, 1570 struct i40e_asq_cmd_details *cmd_details) 1571 { 1572 struct i40e_aq_desc desc; 1573 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1574 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1575 i40e_status status; 1576 1577 i40e_fill_default_direct_cmd_desc(&desc, 1578 i40e_aqc_opc_set_vsi_promiscuous_modes); 1579 1580 if (set_filter) 1581 cmd->promiscuous_flags 1582 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1583 else 1584 cmd->promiscuous_flags 1585 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1586 1587 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1588 cmd->seid = cpu_to_le16(seid); 1589 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1590 1591 return status; 1592 } 1593 1594 /** 1595 * i40e_get_vsi_params - get VSI configuration info 1596 * @hw: pointer to the hw struct 1597 * @vsi_ctx: pointer to a vsi context struct 1598 * @cmd_details: pointer to command details structure or NULL 1599 **/ 1600 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 1601 struct i40e_vsi_context *vsi_ctx, 1602 struct i40e_asq_cmd_details *cmd_details) 1603 { 1604 struct i40e_aq_desc desc; 1605 struct i40e_aqc_add_get_update_vsi *cmd = 1606 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1607 struct i40e_aqc_add_get_update_vsi_completion *resp = 1608 (struct i40e_aqc_add_get_update_vsi_completion *) 1609 &desc.params.raw; 1610 i40e_status status; 1611 1612 i40e_fill_default_direct_cmd_desc(&desc, 1613 i40e_aqc_opc_get_vsi_parameters); 1614 1615 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1616 1617 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1618 1619 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1620 sizeof(vsi_ctx->info), NULL); 1621 1622 if (status) 1623 goto aq_get_vsi_params_exit; 1624 1625 vsi_ctx->seid = le16_to_cpu(resp->seid); 1626 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1627 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1628 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1629 1630 aq_get_vsi_params_exit: 1631 return status; 1632 } 1633 1634 /** 1635 * i40e_aq_update_vsi_params 1636 * @hw: pointer to the hw struct 1637 * @vsi_ctx: pointer to a vsi context struct 1638 * @cmd_details: pointer to command details structure or NULL 1639 * 1640 * Update a VSI context. 1641 **/ 1642 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 1643 struct i40e_vsi_context *vsi_ctx, 1644 struct i40e_asq_cmd_details *cmd_details) 1645 { 1646 struct i40e_aq_desc desc; 1647 struct i40e_aqc_add_get_update_vsi *cmd = 1648 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1649 i40e_status status; 1650 1651 i40e_fill_default_direct_cmd_desc(&desc, 1652 i40e_aqc_opc_update_vsi_parameters); 1653 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1654 1655 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1656 1657 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1658 sizeof(vsi_ctx->info), cmd_details); 1659 1660 return status; 1661 } 1662 1663 /** 1664 * i40e_aq_get_switch_config 1665 * @hw: pointer to the hardware structure 1666 * @buf: pointer to the result buffer 1667 * @buf_size: length of input buffer 1668 * @start_seid: seid to start for the report, 0 == beginning 1669 * @cmd_details: pointer to command details structure or NULL 1670 * 1671 * Fill the buf with switch configuration returned from AdminQ command 1672 **/ 1673 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 1674 struct i40e_aqc_get_switch_config_resp *buf, 1675 u16 buf_size, u16 *start_seid, 1676 struct i40e_asq_cmd_details *cmd_details) 1677 { 1678 struct i40e_aq_desc desc; 1679 struct i40e_aqc_switch_seid *scfg = 1680 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1681 i40e_status status; 1682 1683 i40e_fill_default_direct_cmd_desc(&desc, 1684 i40e_aqc_opc_get_switch_config); 1685 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1686 if (buf_size > I40E_AQ_LARGE_BUF) 1687 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1688 scfg->seid = cpu_to_le16(*start_seid); 1689 1690 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1691 *start_seid = le16_to_cpu(scfg->seid); 1692 1693 return status; 1694 } 1695 1696 /** 1697 * i40e_aq_get_firmware_version 1698 * @hw: pointer to the hw struct 1699 * @fw_major_version: firmware major version 1700 * @fw_minor_version: firmware minor version 1701 * @api_major_version: major queue version 1702 * @api_minor_version: minor queue version 1703 * @cmd_details: pointer to command details structure or NULL 1704 * 1705 * Get the firmware version from the admin queue commands 1706 **/ 1707 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 1708 u16 *fw_major_version, u16 *fw_minor_version, 1709 u16 *api_major_version, u16 *api_minor_version, 1710 struct i40e_asq_cmd_details *cmd_details) 1711 { 1712 struct i40e_aq_desc desc; 1713 struct i40e_aqc_get_version *resp = 1714 (struct i40e_aqc_get_version *)&desc.params.raw; 1715 i40e_status status; 1716 1717 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1718 1719 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1720 1721 if (!status) { 1722 if (fw_major_version != NULL) 1723 *fw_major_version = le16_to_cpu(resp->fw_major); 1724 if (fw_minor_version != NULL) 1725 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1726 if (api_major_version != NULL) 1727 *api_major_version = le16_to_cpu(resp->api_major); 1728 if (api_minor_version != NULL) 1729 *api_minor_version = le16_to_cpu(resp->api_minor); 1730 } 1731 1732 return status; 1733 } 1734 1735 /** 1736 * i40e_aq_send_driver_version 1737 * @hw: pointer to the hw struct 1738 * @dv: driver's major, minor version 1739 * @cmd_details: pointer to command details structure or NULL 1740 * 1741 * Send the driver version to the firmware 1742 **/ 1743 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 1744 struct i40e_driver_version *dv, 1745 struct i40e_asq_cmd_details *cmd_details) 1746 { 1747 struct i40e_aq_desc desc; 1748 struct i40e_aqc_driver_version *cmd = 1749 (struct i40e_aqc_driver_version *)&desc.params.raw; 1750 i40e_status status; 1751 u16 len; 1752 1753 if (dv == NULL) 1754 return I40E_ERR_PARAM; 1755 1756 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1757 1758 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI); 1759 cmd->driver_major_ver = dv->major_version; 1760 cmd->driver_minor_ver = dv->minor_version; 1761 cmd->driver_build_ver = dv->build_version; 1762 cmd->driver_subbuild_ver = dv->subbuild_version; 1763 1764 len = 0; 1765 while (len < sizeof(dv->driver_string) && 1766 (dv->driver_string[len] < 0x80) && 1767 dv->driver_string[len]) 1768 len++; 1769 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1770 len, cmd_details); 1771 1772 return status; 1773 } 1774 1775 /** 1776 * i40e_get_link_status - get status of the HW network link 1777 * @hw: pointer to the hw struct 1778 * 1779 * Returns true if link is up, false if link is down. 1780 * 1781 * Side effect: LinkStatusEvent reporting becomes enabled 1782 **/ 1783 bool i40e_get_link_status(struct i40e_hw *hw) 1784 { 1785 i40e_status status = 0; 1786 bool link_status = false; 1787 1788 if (hw->phy.get_link_info) { 1789 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1790 1791 if (status) 1792 goto i40e_get_link_status_exit; 1793 } 1794 1795 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 1796 1797 i40e_get_link_status_exit: 1798 return link_status; 1799 } 1800 1801 /** 1802 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 1803 * @hw: pointer to the hw struct 1804 * @uplink_seid: the MAC or other gizmo SEID 1805 * @downlink_seid: the VSI SEID 1806 * @enabled_tc: bitmap of TCs to be enabled 1807 * @default_port: true for default port VSI, false for control port 1808 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support 1809 * @veb_seid: pointer to where to put the resulting VEB SEID 1810 * @cmd_details: pointer to command details structure or NULL 1811 * 1812 * This asks the FW to add a VEB between the uplink and downlink 1813 * elements. If the uplink SEID is 0, this will be a floating VEB. 1814 **/ 1815 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 1816 u16 downlink_seid, u8 enabled_tc, 1817 bool default_port, bool enable_l2_filtering, 1818 u16 *veb_seid, 1819 struct i40e_asq_cmd_details *cmd_details) 1820 { 1821 struct i40e_aq_desc desc; 1822 struct i40e_aqc_add_veb *cmd = 1823 (struct i40e_aqc_add_veb *)&desc.params.raw; 1824 struct i40e_aqc_add_veb_completion *resp = 1825 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 1826 i40e_status status; 1827 u16 veb_flags = 0; 1828 1829 /* SEIDs need to either both be set or both be 0 for floating VEB */ 1830 if (!!uplink_seid != !!downlink_seid) 1831 return I40E_ERR_PARAM; 1832 1833 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 1834 1835 cmd->uplink_seid = cpu_to_le16(uplink_seid); 1836 cmd->downlink_seid = cpu_to_le16(downlink_seid); 1837 cmd->enable_tcs = enabled_tc; 1838 if (!uplink_seid) 1839 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 1840 if (default_port) 1841 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 1842 else 1843 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 1844 1845 if (enable_l2_filtering) 1846 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 1847 1848 cmd->veb_flags = cpu_to_le16(veb_flags); 1849 1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1851 1852 if (!status && veb_seid) 1853 *veb_seid = le16_to_cpu(resp->veb_seid); 1854 1855 return status; 1856 } 1857 1858 /** 1859 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 1860 * @hw: pointer to the hw struct 1861 * @veb_seid: the SEID of the VEB to query 1862 * @switch_id: the uplink switch id 1863 * @floating: set to true if the VEB is floating 1864 * @statistic_index: index of the stats counter block for this VEB 1865 * @vebs_used: number of VEB's used by function 1866 * @vebs_free: total VEB's not reserved by any function 1867 * @cmd_details: pointer to command details structure or NULL 1868 * 1869 * This retrieves the parameters for a particular VEB, specified by 1870 * uplink_seid, and returns them to the caller. 1871 **/ 1872 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 1873 u16 veb_seid, u16 *switch_id, 1874 bool *floating, u16 *statistic_index, 1875 u16 *vebs_used, u16 *vebs_free, 1876 struct i40e_asq_cmd_details *cmd_details) 1877 { 1878 struct i40e_aq_desc desc; 1879 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 1880 (struct i40e_aqc_get_veb_parameters_completion *) 1881 &desc.params.raw; 1882 i40e_status status; 1883 1884 if (veb_seid == 0) 1885 return I40E_ERR_PARAM; 1886 1887 i40e_fill_default_direct_cmd_desc(&desc, 1888 i40e_aqc_opc_get_veb_parameters); 1889 cmd_resp->seid = cpu_to_le16(veb_seid); 1890 1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1892 if (status) 1893 goto get_veb_exit; 1894 1895 if (switch_id) 1896 *switch_id = le16_to_cpu(cmd_resp->switch_id); 1897 if (statistic_index) 1898 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 1899 if (vebs_used) 1900 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 1901 if (vebs_free) 1902 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 1903 if (floating) { 1904 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 1905 if (flags & I40E_AQC_ADD_VEB_FLOATING) 1906 *floating = true; 1907 else 1908 *floating = false; 1909 } 1910 1911 get_veb_exit: 1912 return status; 1913 } 1914 1915 /** 1916 * i40e_aq_add_macvlan 1917 * @hw: pointer to the hw struct 1918 * @seid: VSI for the mac address 1919 * @mv_list: list of macvlans to be added 1920 * @count: length of the list 1921 * @cmd_details: pointer to command details structure or NULL 1922 * 1923 * Add MAC/VLAN addresses to the HW filtering 1924 **/ 1925 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 1926 struct i40e_aqc_add_macvlan_element_data *mv_list, 1927 u16 count, struct i40e_asq_cmd_details *cmd_details) 1928 { 1929 struct i40e_aq_desc desc; 1930 struct i40e_aqc_macvlan *cmd = 1931 (struct i40e_aqc_macvlan *)&desc.params.raw; 1932 i40e_status status; 1933 u16 buf_size; 1934 1935 if (count == 0 || !mv_list || !hw) 1936 return I40E_ERR_PARAM; 1937 1938 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data); 1939 1940 /* prep the rest of the request */ 1941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 1942 cmd->num_addresses = cpu_to_le16(count); 1943 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 1944 cmd->seid[1] = 0; 1945 cmd->seid[2] = 0; 1946 1947 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1948 if (buf_size > I40E_AQ_LARGE_BUF) 1949 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1950 1951 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 1952 cmd_details); 1953 1954 return status; 1955 } 1956 1957 /** 1958 * i40e_aq_remove_macvlan 1959 * @hw: pointer to the hw struct 1960 * @seid: VSI for the mac address 1961 * @mv_list: list of macvlans to be removed 1962 * @count: length of the list 1963 * @cmd_details: pointer to command details structure or NULL 1964 * 1965 * Remove MAC/VLAN addresses from the HW filtering 1966 **/ 1967 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 1968 struct i40e_aqc_remove_macvlan_element_data *mv_list, 1969 u16 count, struct i40e_asq_cmd_details *cmd_details) 1970 { 1971 struct i40e_aq_desc desc; 1972 struct i40e_aqc_macvlan *cmd = 1973 (struct i40e_aqc_macvlan *)&desc.params.raw; 1974 i40e_status status; 1975 u16 buf_size; 1976 1977 if (count == 0 || !mv_list || !hw) 1978 return I40E_ERR_PARAM; 1979 1980 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data); 1981 1982 /* prep the rest of the request */ 1983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 1984 cmd->num_addresses = cpu_to_le16(count); 1985 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 1986 cmd->seid[1] = 0; 1987 cmd->seid[2] = 0; 1988 1989 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1990 if (buf_size > I40E_AQ_LARGE_BUF) 1991 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1992 1993 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 1994 cmd_details); 1995 1996 return status; 1997 } 1998 1999 /** 2000 * i40e_aq_send_msg_to_vf 2001 * @hw: pointer to the hardware structure 2002 * @vfid: vf id to send msg 2003 * @v_opcode: opcodes for VF-PF communication 2004 * @v_retval: return error code 2005 * @msg: pointer to the msg buffer 2006 * @msglen: msg length 2007 * @cmd_details: pointer to command details 2008 * 2009 * send msg to vf 2010 **/ 2011 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2012 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2013 struct i40e_asq_cmd_details *cmd_details) 2014 { 2015 struct i40e_aq_desc desc; 2016 struct i40e_aqc_pf_vf_message *cmd = 2017 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2018 i40e_status status; 2019 2020 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2021 cmd->id = cpu_to_le32(vfid); 2022 desc.cookie_high = cpu_to_le32(v_opcode); 2023 desc.cookie_low = cpu_to_le32(v_retval); 2024 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2025 if (msglen) { 2026 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2027 I40E_AQ_FLAG_RD)); 2028 if (msglen > I40E_AQ_LARGE_BUF) 2029 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2030 desc.datalen = cpu_to_le16(msglen); 2031 } 2032 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2033 2034 return status; 2035 } 2036 2037 /** 2038 * i40e_aq_debug_write_register 2039 * @hw: pointer to the hw struct 2040 * @reg_addr: register address 2041 * @reg_val: register value 2042 * @cmd_details: pointer to command details structure or NULL 2043 * 2044 * Write to a register using the admin queue commands 2045 **/ 2046 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2047 u32 reg_addr, u64 reg_val, 2048 struct i40e_asq_cmd_details *cmd_details) 2049 { 2050 struct i40e_aq_desc desc; 2051 struct i40e_aqc_debug_reg_read_write *cmd = 2052 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2053 i40e_status status; 2054 2055 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2056 2057 cmd->address = cpu_to_le32(reg_addr); 2058 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2059 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2060 2061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2062 2063 return status; 2064 } 2065 2066 /** 2067 * i40e_aq_set_hmc_resource_profile 2068 * @hw: pointer to the hw struct 2069 * @profile: type of profile the HMC is to be set as 2070 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2071 * @cmd_details: pointer to command details structure or NULL 2072 * 2073 * set the HMC profile of the device. 2074 **/ 2075 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2076 enum i40e_aq_hmc_profile profile, 2077 u8 pe_vf_enabled_count, 2078 struct i40e_asq_cmd_details *cmd_details) 2079 { 2080 struct i40e_aq_desc desc; 2081 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2082 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2083 i40e_status status; 2084 2085 i40e_fill_default_direct_cmd_desc(&desc, 2086 i40e_aqc_opc_set_hmc_resource_profile); 2087 2088 cmd->pm_profile = (u8)profile; 2089 cmd->pe_vf_enabled = pe_vf_enabled_count; 2090 2091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2092 2093 return status; 2094 } 2095 2096 /** 2097 * i40e_aq_request_resource 2098 * @hw: pointer to the hw struct 2099 * @resource: resource id 2100 * @access: access type 2101 * @sdp_number: resource number 2102 * @timeout: the maximum time in ms that the driver may hold the resource 2103 * @cmd_details: pointer to command details structure or NULL 2104 * 2105 * requests common resource using the admin queue commands 2106 **/ 2107 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2108 enum i40e_aq_resources_ids resource, 2109 enum i40e_aq_resource_access_type access, 2110 u8 sdp_number, u64 *timeout, 2111 struct i40e_asq_cmd_details *cmd_details) 2112 { 2113 struct i40e_aq_desc desc; 2114 struct i40e_aqc_request_resource *cmd_resp = 2115 (struct i40e_aqc_request_resource *)&desc.params.raw; 2116 i40e_status status; 2117 2118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2119 2120 cmd_resp->resource_id = cpu_to_le16(resource); 2121 cmd_resp->access_type = cpu_to_le16(access); 2122 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2123 2124 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2125 /* The completion specifies the maximum time in ms that the driver 2126 * may hold the resource in the Timeout field. 2127 * If the resource is held by someone else, the command completes with 2128 * busy return value and the timeout field indicates the maximum time 2129 * the current owner of the resource has to free it. 2130 */ 2131 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2132 *timeout = le32_to_cpu(cmd_resp->timeout); 2133 2134 return status; 2135 } 2136 2137 /** 2138 * i40e_aq_release_resource 2139 * @hw: pointer to the hw struct 2140 * @resource: resource id 2141 * @sdp_number: resource number 2142 * @cmd_details: pointer to command details structure or NULL 2143 * 2144 * release common resource using the admin queue commands 2145 **/ 2146 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2147 enum i40e_aq_resources_ids resource, 2148 u8 sdp_number, 2149 struct i40e_asq_cmd_details *cmd_details) 2150 { 2151 struct i40e_aq_desc desc; 2152 struct i40e_aqc_request_resource *cmd = 2153 (struct i40e_aqc_request_resource *)&desc.params.raw; 2154 i40e_status status; 2155 2156 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2157 2158 cmd->resource_id = cpu_to_le16(resource); 2159 cmd->resource_number = cpu_to_le32(sdp_number); 2160 2161 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2162 2163 return status; 2164 } 2165 2166 /** 2167 * i40e_aq_read_nvm 2168 * @hw: pointer to the hw struct 2169 * @module_pointer: module pointer location in words from the NVM beginning 2170 * @offset: byte offset from the module beginning 2171 * @length: length of the section to be read (in bytes from the offset) 2172 * @data: command buffer (size [bytes] = length) 2173 * @last_command: tells if this is the last command in a series 2174 * @cmd_details: pointer to command details structure or NULL 2175 * 2176 * Read the NVM using the admin queue commands 2177 **/ 2178 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2179 u32 offset, u16 length, void *data, 2180 bool last_command, 2181 struct i40e_asq_cmd_details *cmd_details) 2182 { 2183 struct i40e_aq_desc desc; 2184 struct i40e_aqc_nvm_update *cmd = 2185 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2186 i40e_status status; 2187 2188 /* In offset the highest byte must be zeroed. */ 2189 if (offset & 0xFF000000) { 2190 status = I40E_ERR_PARAM; 2191 goto i40e_aq_read_nvm_exit; 2192 } 2193 2194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2195 2196 /* If this is the last command in a series, set the proper flag. */ 2197 if (last_command) 2198 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2199 cmd->module_pointer = module_pointer; 2200 cmd->offset = cpu_to_le32(offset); 2201 cmd->length = cpu_to_le16(length); 2202 2203 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2204 if (length > I40E_AQ_LARGE_BUF) 2205 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2206 2207 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2208 2209 i40e_aq_read_nvm_exit: 2210 return status; 2211 } 2212 2213 /** 2214 * i40e_aq_erase_nvm 2215 * @hw: pointer to the hw struct 2216 * @module_pointer: module pointer location in words from the NVM beginning 2217 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2218 * @length: length of the section to be erased (expressed in 4 KB) 2219 * @last_command: tells if this is the last command in a series 2220 * @cmd_details: pointer to command details structure or NULL 2221 * 2222 * Erase the NVM sector using the admin queue commands 2223 **/ 2224 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2225 u32 offset, u16 length, bool last_command, 2226 struct i40e_asq_cmd_details *cmd_details) 2227 { 2228 struct i40e_aq_desc desc; 2229 struct i40e_aqc_nvm_update *cmd = 2230 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2231 i40e_status status; 2232 2233 /* In offset the highest byte must be zeroed. */ 2234 if (offset & 0xFF000000) { 2235 status = I40E_ERR_PARAM; 2236 goto i40e_aq_erase_nvm_exit; 2237 } 2238 2239 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2240 2241 /* If this is the last command in a series, set the proper flag. */ 2242 if (last_command) 2243 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2244 cmd->module_pointer = module_pointer; 2245 cmd->offset = cpu_to_le32(offset); 2246 cmd->length = cpu_to_le16(length); 2247 2248 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2249 2250 i40e_aq_erase_nvm_exit: 2251 return status; 2252 } 2253 2254 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2255 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2256 #define I40E_DEV_FUNC_CAP_NPAR 0x03 2257 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2258 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2259 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2260 #define I40E_DEV_FUNC_CAP_VF 0x13 2261 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 2262 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2263 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2264 #define I40E_DEV_FUNC_CAP_VSI 0x17 2265 #define I40E_DEV_FUNC_CAP_DCB 0x18 2266 #define I40E_DEV_FUNC_CAP_FCOE 0x21 2267 #define I40E_DEV_FUNC_CAP_RSS 0x40 2268 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2269 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2270 #define I40E_DEV_FUNC_CAP_MSIX 0x43 2271 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2272 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2273 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2274 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2275 #define I40E_DEV_FUNC_CAP_CEM 0xF2 2276 #define I40E_DEV_FUNC_CAP_IWARP 0x51 2277 #define I40E_DEV_FUNC_CAP_LED 0x61 2278 #define I40E_DEV_FUNC_CAP_SDP 0x62 2279 #define I40E_DEV_FUNC_CAP_MDIO 0x63 2280 2281 /** 2282 * i40e_parse_discover_capabilities 2283 * @hw: pointer to the hw struct 2284 * @buff: pointer to a buffer containing device/function capability records 2285 * @cap_count: number of capability records in the list 2286 * @list_type_opc: type of capabilities list to parse 2287 * 2288 * Parse the device/function capabilities list. 2289 **/ 2290 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2291 u32 cap_count, 2292 enum i40e_admin_queue_opc list_type_opc) 2293 { 2294 struct i40e_aqc_list_capabilities_element_resp *cap; 2295 u32 number, logical_id, phys_id; 2296 struct i40e_hw_capabilities *p; 2297 u32 i = 0; 2298 u16 id; 2299 2300 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2301 2302 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2303 p = &hw->dev_caps; 2304 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2305 p = &hw->func_caps; 2306 else 2307 return; 2308 2309 for (i = 0; i < cap_count; i++, cap++) { 2310 id = le16_to_cpu(cap->id); 2311 number = le32_to_cpu(cap->number); 2312 logical_id = le32_to_cpu(cap->logical_id); 2313 phys_id = le32_to_cpu(cap->phys_id); 2314 2315 switch (id) { 2316 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2317 p->switch_mode = number; 2318 break; 2319 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2320 p->management_mode = number; 2321 break; 2322 case I40E_DEV_FUNC_CAP_NPAR: 2323 p->npar_enable = number; 2324 break; 2325 case I40E_DEV_FUNC_CAP_OS2BMC: 2326 p->os2bmc = number; 2327 break; 2328 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2329 p->valid_functions = number; 2330 break; 2331 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2332 if (number == 1) 2333 p->sr_iov_1_1 = true; 2334 break; 2335 case I40E_DEV_FUNC_CAP_VF: 2336 p->num_vfs = number; 2337 p->vf_base_id = logical_id; 2338 break; 2339 case I40E_DEV_FUNC_CAP_VMDQ: 2340 if (number == 1) 2341 p->vmdq = true; 2342 break; 2343 case I40E_DEV_FUNC_CAP_802_1_QBG: 2344 if (number == 1) 2345 p->evb_802_1_qbg = true; 2346 break; 2347 case I40E_DEV_FUNC_CAP_802_1_QBH: 2348 if (number == 1) 2349 p->evb_802_1_qbh = true; 2350 break; 2351 case I40E_DEV_FUNC_CAP_VSI: 2352 p->num_vsis = number; 2353 break; 2354 case I40E_DEV_FUNC_CAP_DCB: 2355 if (number == 1) { 2356 p->dcb = true; 2357 p->enabled_tcmap = logical_id; 2358 p->maxtc = phys_id; 2359 } 2360 break; 2361 case I40E_DEV_FUNC_CAP_FCOE: 2362 if (number == 1) 2363 p->fcoe = true; 2364 break; 2365 case I40E_DEV_FUNC_CAP_RSS: 2366 p->rss = true; 2367 p->rss_table_size = number; 2368 p->rss_table_entry_width = logical_id; 2369 break; 2370 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2371 p->num_rx_qp = number; 2372 p->base_queue = phys_id; 2373 break; 2374 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2375 p->num_tx_qp = number; 2376 p->base_queue = phys_id; 2377 break; 2378 case I40E_DEV_FUNC_CAP_MSIX: 2379 p->num_msix_vectors = number; 2380 break; 2381 case I40E_DEV_FUNC_CAP_MSIX_VF: 2382 p->num_msix_vectors_vf = number; 2383 break; 2384 case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2385 if (number == 1) 2386 p->mfp_mode_1 = true; 2387 break; 2388 case I40E_DEV_FUNC_CAP_CEM: 2389 if (number == 1) 2390 p->mgmt_cem = true; 2391 break; 2392 case I40E_DEV_FUNC_CAP_IWARP: 2393 if (number == 1) 2394 p->iwarp = true; 2395 break; 2396 case I40E_DEV_FUNC_CAP_LED: 2397 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2398 p->led[phys_id] = true; 2399 break; 2400 case I40E_DEV_FUNC_CAP_SDP: 2401 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2402 p->sdp[phys_id] = true; 2403 break; 2404 case I40E_DEV_FUNC_CAP_MDIO: 2405 if (number == 1) { 2406 p->mdio_port_num = phys_id; 2407 p->mdio_port_mode = logical_id; 2408 } 2409 break; 2410 case I40E_DEV_FUNC_CAP_IEEE_1588: 2411 if (number == 1) 2412 p->ieee_1588 = true; 2413 break; 2414 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2415 p->fd = true; 2416 p->fd_filters_guaranteed = number; 2417 p->fd_filters_best_effort = logical_id; 2418 break; 2419 default: 2420 break; 2421 } 2422 } 2423 2424 /* Software override ensuring FCoE is disabled if npar or mfp 2425 * mode because it is not supported in these modes. 2426 */ 2427 if (p->npar_enable || p->mfp_mode_1) 2428 p->fcoe = false; 2429 2430 /* additional HW specific goodies that might 2431 * someday be HW version specific 2432 */ 2433 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2434 } 2435 2436 /** 2437 * i40e_aq_discover_capabilities 2438 * @hw: pointer to the hw struct 2439 * @buff: a virtual buffer to hold the capabilities 2440 * @buff_size: Size of the virtual buffer 2441 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2442 * @list_type_opc: capabilities type to discover - pass in the command opcode 2443 * @cmd_details: pointer to command details structure or NULL 2444 * 2445 * Get the device capabilities descriptions from the firmware 2446 **/ 2447 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 2448 void *buff, u16 buff_size, u16 *data_size, 2449 enum i40e_admin_queue_opc list_type_opc, 2450 struct i40e_asq_cmd_details *cmd_details) 2451 { 2452 struct i40e_aqc_list_capabilites *cmd; 2453 struct i40e_aq_desc desc; 2454 i40e_status status = 0; 2455 2456 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2457 2458 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2459 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2460 status = I40E_ERR_PARAM; 2461 goto exit; 2462 } 2463 2464 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2465 2466 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2467 if (buff_size > I40E_AQ_LARGE_BUF) 2468 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2469 2470 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2471 *data_size = le16_to_cpu(desc.datalen); 2472 2473 if (status) 2474 goto exit; 2475 2476 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2477 list_type_opc); 2478 2479 exit: 2480 return status; 2481 } 2482 2483 /** 2484 * i40e_aq_update_nvm 2485 * @hw: pointer to the hw struct 2486 * @module_pointer: module pointer location in words from the NVM beginning 2487 * @offset: byte offset from the module beginning 2488 * @length: length of the section to be written (in bytes from the offset) 2489 * @data: command buffer (size [bytes] = length) 2490 * @last_command: tells if this is the last command in a series 2491 * @cmd_details: pointer to command details structure or NULL 2492 * 2493 * Update the NVM using the admin queue commands 2494 **/ 2495 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2496 u32 offset, u16 length, void *data, 2497 bool last_command, 2498 struct i40e_asq_cmd_details *cmd_details) 2499 { 2500 struct i40e_aq_desc desc; 2501 struct i40e_aqc_nvm_update *cmd = 2502 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2503 i40e_status status; 2504 2505 /* In offset the highest byte must be zeroed. */ 2506 if (offset & 0xFF000000) { 2507 status = I40E_ERR_PARAM; 2508 goto i40e_aq_update_nvm_exit; 2509 } 2510 2511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2512 2513 /* If this is the last command in a series, set the proper flag. */ 2514 if (last_command) 2515 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2516 cmd->module_pointer = module_pointer; 2517 cmd->offset = cpu_to_le32(offset); 2518 cmd->length = cpu_to_le16(length); 2519 2520 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2521 if (length > I40E_AQ_LARGE_BUF) 2522 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2523 2524 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2525 2526 i40e_aq_update_nvm_exit: 2527 return status; 2528 } 2529 2530 /** 2531 * i40e_aq_get_lldp_mib 2532 * @hw: pointer to the hw struct 2533 * @bridge_type: type of bridge requested 2534 * @mib_type: Local, Remote or both Local and Remote MIBs 2535 * @buff: pointer to a user supplied buffer to store the MIB block 2536 * @buff_size: size of the buffer (in bytes) 2537 * @local_len : length of the returned Local LLDP MIB 2538 * @remote_len: length of the returned Remote LLDP MIB 2539 * @cmd_details: pointer to command details structure or NULL 2540 * 2541 * Requests the complete LLDP MIB (entire packet). 2542 **/ 2543 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2544 u8 mib_type, void *buff, u16 buff_size, 2545 u16 *local_len, u16 *remote_len, 2546 struct i40e_asq_cmd_details *cmd_details) 2547 { 2548 struct i40e_aq_desc desc; 2549 struct i40e_aqc_lldp_get_mib *cmd = 2550 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2551 struct i40e_aqc_lldp_get_mib *resp = 2552 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2553 i40e_status status; 2554 2555 if (buff_size == 0 || !buff) 2556 return I40E_ERR_PARAM; 2557 2558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2559 /* Indirect Command */ 2560 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2561 2562 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2563 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 2564 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 2565 2566 desc.datalen = cpu_to_le16(buff_size); 2567 2568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2569 if (buff_size > I40E_AQ_LARGE_BUF) 2570 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2571 2572 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2573 if (!status) { 2574 if (local_len != NULL) 2575 *local_len = le16_to_cpu(resp->local_len); 2576 if (remote_len != NULL) 2577 *remote_len = le16_to_cpu(resp->remote_len); 2578 } 2579 2580 return status; 2581 } 2582 2583 /** 2584 * i40e_aq_cfg_lldp_mib_change_event 2585 * @hw: pointer to the hw struct 2586 * @enable_update: Enable or Disable event posting 2587 * @cmd_details: pointer to command details structure or NULL 2588 * 2589 * Enable or Disable posting of an event on ARQ when LLDP MIB 2590 * associated with the interface changes 2591 **/ 2592 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 2593 bool enable_update, 2594 struct i40e_asq_cmd_details *cmd_details) 2595 { 2596 struct i40e_aq_desc desc; 2597 struct i40e_aqc_lldp_update_mib *cmd = 2598 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 2599 i40e_status status; 2600 2601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 2602 2603 if (!enable_update) 2604 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 2605 2606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2607 2608 return status; 2609 } 2610 2611 /** 2612 * i40e_aq_stop_lldp 2613 * @hw: pointer to the hw struct 2614 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 2615 * @cmd_details: pointer to command details structure or NULL 2616 * 2617 * Stop or Shutdown the embedded LLDP Agent 2618 **/ 2619 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 2620 struct i40e_asq_cmd_details *cmd_details) 2621 { 2622 struct i40e_aq_desc desc; 2623 struct i40e_aqc_lldp_stop *cmd = 2624 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 2625 i40e_status status; 2626 2627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 2628 2629 if (shutdown_agent) 2630 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 2631 2632 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2633 2634 return status; 2635 } 2636 2637 /** 2638 * i40e_aq_start_lldp 2639 * @hw: pointer to the hw struct 2640 * @cmd_details: pointer to command details structure or NULL 2641 * 2642 * Start the embedded LLDP Agent on all ports. 2643 **/ 2644 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 2645 struct i40e_asq_cmd_details *cmd_details) 2646 { 2647 struct i40e_aq_desc desc; 2648 struct i40e_aqc_lldp_start *cmd = 2649 (struct i40e_aqc_lldp_start *)&desc.params.raw; 2650 i40e_status status; 2651 2652 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 2653 2654 cmd->command = I40E_AQ_LLDP_AGENT_START; 2655 2656 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2657 2658 return status; 2659 } 2660 2661 /** 2662 * i40e_aq_get_cee_dcb_config 2663 * @hw: pointer to the hw struct 2664 * @buff: response buffer that stores CEE operational configuration 2665 * @buff_size: size of the buffer passed 2666 * @cmd_details: pointer to command details structure or NULL 2667 * 2668 * Get CEE DCBX mode operational configuration from firmware 2669 **/ 2670 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 2671 void *buff, u16 buff_size, 2672 struct i40e_asq_cmd_details *cmd_details) 2673 { 2674 struct i40e_aq_desc desc; 2675 i40e_status status; 2676 2677 if (buff_size == 0 || !buff) 2678 return I40E_ERR_PARAM; 2679 2680 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 2681 2682 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2683 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 2684 cmd_details); 2685 2686 return status; 2687 } 2688 2689 /** 2690 * i40e_aq_add_udp_tunnel 2691 * @hw: pointer to the hw struct 2692 * @udp_port: the UDP port to add 2693 * @header_len: length of the tunneling header length in DWords 2694 * @protocol_index: protocol index type 2695 * @filter_index: pointer to filter index 2696 * @cmd_details: pointer to command details structure or NULL 2697 **/ 2698 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 2699 u16 udp_port, u8 protocol_index, 2700 u8 *filter_index, 2701 struct i40e_asq_cmd_details *cmd_details) 2702 { 2703 struct i40e_aq_desc desc; 2704 struct i40e_aqc_add_udp_tunnel *cmd = 2705 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 2706 struct i40e_aqc_del_udp_tunnel_completion *resp = 2707 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 2708 i40e_status status; 2709 2710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 2711 2712 cmd->udp_port = cpu_to_le16(udp_port); 2713 cmd->protocol_type = protocol_index; 2714 2715 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2716 2717 if (!status) 2718 *filter_index = resp->index; 2719 2720 return status; 2721 } 2722 2723 /** 2724 * i40e_aq_del_udp_tunnel 2725 * @hw: pointer to the hw struct 2726 * @index: filter index 2727 * @cmd_details: pointer to command details structure or NULL 2728 **/ 2729 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 2730 struct i40e_asq_cmd_details *cmd_details) 2731 { 2732 struct i40e_aq_desc desc; 2733 struct i40e_aqc_remove_udp_tunnel *cmd = 2734 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 2735 i40e_status status; 2736 2737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 2738 2739 cmd->index = index; 2740 2741 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2742 2743 return status; 2744 } 2745 2746 /** 2747 * i40e_aq_delete_element - Delete switch element 2748 * @hw: pointer to the hw struct 2749 * @seid: the SEID to delete from the switch 2750 * @cmd_details: pointer to command details structure or NULL 2751 * 2752 * This deletes a switch element from the switch. 2753 **/ 2754 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 2755 struct i40e_asq_cmd_details *cmd_details) 2756 { 2757 struct i40e_aq_desc desc; 2758 struct i40e_aqc_switch_seid *cmd = 2759 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2760 i40e_status status; 2761 2762 if (seid == 0) 2763 return I40E_ERR_PARAM; 2764 2765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 2766 2767 cmd->seid = cpu_to_le16(seid); 2768 2769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2770 2771 return status; 2772 } 2773 2774 /** 2775 * i40e_aq_dcb_updated - DCB Updated Command 2776 * @hw: pointer to the hw struct 2777 * @cmd_details: pointer to command details structure or NULL 2778 * 2779 * EMP will return when the shared RPB settings have been 2780 * recomputed and modified. The retval field in the descriptor 2781 * will be set to 0 when RPB is modified. 2782 **/ 2783 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 2784 struct i40e_asq_cmd_details *cmd_details) 2785 { 2786 struct i40e_aq_desc desc; 2787 i40e_status status; 2788 2789 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 2790 2791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2792 2793 return status; 2794 } 2795 2796 /** 2797 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 2798 * @hw: pointer to the hw struct 2799 * @seid: seid for the physical port/switching component/vsi 2800 * @buff: Indirect buffer to hold data parameters and response 2801 * @buff_size: Indirect buffer size 2802 * @opcode: Tx scheduler AQ command opcode 2803 * @cmd_details: pointer to command details structure or NULL 2804 * 2805 * Generic command handler for Tx scheduler AQ commands 2806 **/ 2807 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 2808 void *buff, u16 buff_size, 2809 enum i40e_admin_queue_opc opcode, 2810 struct i40e_asq_cmd_details *cmd_details) 2811 { 2812 struct i40e_aq_desc desc; 2813 struct i40e_aqc_tx_sched_ind *cmd = 2814 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 2815 i40e_status status; 2816 bool cmd_param_flag = false; 2817 2818 switch (opcode) { 2819 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 2820 case i40e_aqc_opc_configure_vsi_tc_bw: 2821 case i40e_aqc_opc_enable_switching_comp_ets: 2822 case i40e_aqc_opc_modify_switching_comp_ets: 2823 case i40e_aqc_opc_disable_switching_comp_ets: 2824 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 2825 case i40e_aqc_opc_configure_switching_comp_bw_config: 2826 cmd_param_flag = true; 2827 break; 2828 case i40e_aqc_opc_query_vsi_bw_config: 2829 case i40e_aqc_opc_query_vsi_ets_sla_config: 2830 case i40e_aqc_opc_query_switching_comp_ets_config: 2831 case i40e_aqc_opc_query_port_ets_config: 2832 case i40e_aqc_opc_query_switching_comp_bw_config: 2833 cmd_param_flag = false; 2834 break; 2835 default: 2836 return I40E_ERR_PARAM; 2837 } 2838 2839 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2840 2841 /* Indirect command */ 2842 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2843 if (cmd_param_flag) 2844 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 2845 if (buff_size > I40E_AQ_LARGE_BUF) 2846 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2847 2848 desc.datalen = cpu_to_le16(buff_size); 2849 2850 cmd->vsi_seid = cpu_to_le16(seid); 2851 2852 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2853 2854 return status; 2855 } 2856 2857 /** 2858 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 2859 * @hw: pointer to the hw struct 2860 * @seid: VSI seid 2861 * @credit: BW limit credits (0 = disabled) 2862 * @max_credit: Max BW limit credits 2863 * @cmd_details: pointer to command details structure or NULL 2864 **/ 2865 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 2866 u16 seid, u16 credit, u8 max_credit, 2867 struct i40e_asq_cmd_details *cmd_details) 2868 { 2869 struct i40e_aq_desc desc; 2870 struct i40e_aqc_configure_vsi_bw_limit *cmd = 2871 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 2872 i40e_status status; 2873 2874 i40e_fill_default_direct_cmd_desc(&desc, 2875 i40e_aqc_opc_configure_vsi_bw_limit); 2876 2877 cmd->vsi_seid = cpu_to_le16(seid); 2878 cmd->credit = cpu_to_le16(credit); 2879 cmd->max_credit = max_credit; 2880 2881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2882 2883 return status; 2884 } 2885 2886 /** 2887 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 2888 * @hw: pointer to the hw struct 2889 * @seid: VSI seid 2890 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 2891 * @cmd_details: pointer to command details structure or NULL 2892 **/ 2893 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 2894 u16 seid, 2895 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 2896 struct i40e_asq_cmd_details *cmd_details) 2897 { 2898 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2899 i40e_aqc_opc_configure_vsi_tc_bw, 2900 cmd_details); 2901 } 2902 2903 /** 2904 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 2905 * @hw: pointer to the hw struct 2906 * @seid: seid of the switching component connected to Physical Port 2907 * @ets_data: Buffer holding ETS parameters 2908 * @cmd_details: pointer to command details structure or NULL 2909 **/ 2910 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 2911 u16 seid, 2912 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 2913 enum i40e_admin_queue_opc opcode, 2914 struct i40e_asq_cmd_details *cmd_details) 2915 { 2916 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 2917 sizeof(*ets_data), opcode, cmd_details); 2918 } 2919 2920 /** 2921 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 2922 * @hw: pointer to the hw struct 2923 * @seid: seid of the switching component 2924 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 2925 * @cmd_details: pointer to command details structure or NULL 2926 **/ 2927 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 2928 u16 seid, 2929 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 2930 struct i40e_asq_cmd_details *cmd_details) 2931 { 2932 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2933 i40e_aqc_opc_configure_switching_comp_bw_config, 2934 cmd_details); 2935 } 2936 2937 /** 2938 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 2939 * @hw: pointer to the hw struct 2940 * @seid: seid of the VSI 2941 * @bw_data: Buffer to hold VSI BW configuration 2942 * @cmd_details: pointer to command details structure or NULL 2943 **/ 2944 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 2945 u16 seid, 2946 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 2947 struct i40e_asq_cmd_details *cmd_details) 2948 { 2949 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2950 i40e_aqc_opc_query_vsi_bw_config, 2951 cmd_details); 2952 } 2953 2954 /** 2955 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 2956 * @hw: pointer to the hw struct 2957 * @seid: seid of the VSI 2958 * @bw_data: Buffer to hold VSI BW configuration per TC 2959 * @cmd_details: pointer to command details structure or NULL 2960 **/ 2961 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 2962 u16 seid, 2963 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 2964 struct i40e_asq_cmd_details *cmd_details) 2965 { 2966 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2967 i40e_aqc_opc_query_vsi_ets_sla_config, 2968 cmd_details); 2969 } 2970 2971 /** 2972 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 2973 * @hw: pointer to the hw struct 2974 * @seid: seid of the switching component 2975 * @bw_data: Buffer to hold switching component's per TC BW config 2976 * @cmd_details: pointer to command details structure or NULL 2977 **/ 2978 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 2979 u16 seid, 2980 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 2981 struct i40e_asq_cmd_details *cmd_details) 2982 { 2983 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2984 i40e_aqc_opc_query_switching_comp_ets_config, 2985 cmd_details); 2986 } 2987 2988 /** 2989 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 2990 * @hw: pointer to the hw struct 2991 * @seid: seid of the VSI or switching component connected to Physical Port 2992 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 2993 * @cmd_details: pointer to command details structure or NULL 2994 **/ 2995 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 2996 u16 seid, 2997 struct i40e_aqc_query_port_ets_config_resp *bw_data, 2998 struct i40e_asq_cmd_details *cmd_details) 2999 { 3000 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3001 i40e_aqc_opc_query_port_ets_config, 3002 cmd_details); 3003 } 3004 3005 /** 3006 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3007 * @hw: pointer to the hw struct 3008 * @seid: seid of the switching component 3009 * @bw_data: Buffer to hold switching component's BW configuration 3010 * @cmd_details: pointer to command details structure or NULL 3011 **/ 3012 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3013 u16 seid, 3014 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3015 struct i40e_asq_cmd_details *cmd_details) 3016 { 3017 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3018 i40e_aqc_opc_query_switching_comp_bw_config, 3019 cmd_details); 3020 } 3021 3022 /** 3023 * i40e_validate_filter_settings 3024 * @hw: pointer to the hardware structure 3025 * @settings: Filter control settings 3026 * 3027 * Check and validate the filter control settings passed. 3028 * The function checks for the valid filter/context sizes being 3029 * passed for FCoE and PE. 3030 * 3031 * Returns 0 if the values passed are valid and within 3032 * range else returns an error. 3033 **/ 3034 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3035 struct i40e_filter_control_settings *settings) 3036 { 3037 u32 fcoe_cntx_size, fcoe_filt_size; 3038 u32 pe_cntx_size, pe_filt_size; 3039 u32 fcoe_fmax; 3040 u32 val; 3041 3042 /* Validate FCoE settings passed */ 3043 switch (settings->fcoe_filt_num) { 3044 case I40E_HASH_FILTER_SIZE_1K: 3045 case I40E_HASH_FILTER_SIZE_2K: 3046 case I40E_HASH_FILTER_SIZE_4K: 3047 case I40E_HASH_FILTER_SIZE_8K: 3048 case I40E_HASH_FILTER_SIZE_16K: 3049 case I40E_HASH_FILTER_SIZE_32K: 3050 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3051 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3052 break; 3053 default: 3054 return I40E_ERR_PARAM; 3055 } 3056 3057 switch (settings->fcoe_cntx_num) { 3058 case I40E_DMA_CNTX_SIZE_512: 3059 case I40E_DMA_CNTX_SIZE_1K: 3060 case I40E_DMA_CNTX_SIZE_2K: 3061 case I40E_DMA_CNTX_SIZE_4K: 3062 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3063 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3064 break; 3065 default: 3066 return I40E_ERR_PARAM; 3067 } 3068 3069 /* Validate PE settings passed */ 3070 switch (settings->pe_filt_num) { 3071 case I40E_HASH_FILTER_SIZE_1K: 3072 case I40E_HASH_FILTER_SIZE_2K: 3073 case I40E_HASH_FILTER_SIZE_4K: 3074 case I40E_HASH_FILTER_SIZE_8K: 3075 case I40E_HASH_FILTER_SIZE_16K: 3076 case I40E_HASH_FILTER_SIZE_32K: 3077 case I40E_HASH_FILTER_SIZE_64K: 3078 case I40E_HASH_FILTER_SIZE_128K: 3079 case I40E_HASH_FILTER_SIZE_256K: 3080 case I40E_HASH_FILTER_SIZE_512K: 3081 case I40E_HASH_FILTER_SIZE_1M: 3082 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3083 pe_filt_size <<= (u32)settings->pe_filt_num; 3084 break; 3085 default: 3086 return I40E_ERR_PARAM; 3087 } 3088 3089 switch (settings->pe_cntx_num) { 3090 case I40E_DMA_CNTX_SIZE_512: 3091 case I40E_DMA_CNTX_SIZE_1K: 3092 case I40E_DMA_CNTX_SIZE_2K: 3093 case I40E_DMA_CNTX_SIZE_4K: 3094 case I40E_DMA_CNTX_SIZE_8K: 3095 case I40E_DMA_CNTX_SIZE_16K: 3096 case I40E_DMA_CNTX_SIZE_32K: 3097 case I40E_DMA_CNTX_SIZE_64K: 3098 case I40E_DMA_CNTX_SIZE_128K: 3099 case I40E_DMA_CNTX_SIZE_256K: 3100 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3101 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3102 break; 3103 default: 3104 return I40E_ERR_PARAM; 3105 } 3106 3107 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3108 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3109 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3110 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3111 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3112 return I40E_ERR_INVALID_SIZE; 3113 3114 return 0; 3115 } 3116 3117 /** 3118 * i40e_set_filter_control 3119 * @hw: pointer to the hardware structure 3120 * @settings: Filter control settings 3121 * 3122 * Set the Queue Filters for PE/FCoE and enable filters required 3123 * for a single PF. It is expected that these settings are programmed 3124 * at the driver initialization time. 3125 **/ 3126 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 3127 struct i40e_filter_control_settings *settings) 3128 { 3129 i40e_status ret = 0; 3130 u32 hash_lut_size = 0; 3131 u32 val; 3132 3133 if (!settings) 3134 return I40E_ERR_PARAM; 3135 3136 /* Validate the input settings */ 3137 ret = i40e_validate_filter_settings(hw, settings); 3138 if (ret) 3139 return ret; 3140 3141 /* Read the PF Queue Filter control register */ 3142 val = rd32(hw, I40E_PFQF_CTL_0); 3143 3144 /* Program required PE hash buckets for the PF */ 3145 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3146 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 3147 I40E_PFQF_CTL_0_PEHSIZE_MASK; 3148 /* Program required PE contexts for the PF */ 3149 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3150 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 3151 I40E_PFQF_CTL_0_PEDSIZE_MASK; 3152 3153 /* Program required FCoE hash buckets for the PF */ 3154 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3155 val |= ((u32)settings->fcoe_filt_num << 3156 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 3157 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3158 /* Program required FCoE DDP contexts for the PF */ 3159 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3160 val |= ((u32)settings->fcoe_cntx_num << 3161 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 3162 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3163 3164 /* Program Hash LUT size for the PF */ 3165 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3166 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3167 hash_lut_size = 1; 3168 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 3169 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3170 3171 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3172 if (settings->enable_fdir) 3173 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3174 if (settings->enable_ethtype) 3175 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3176 if (settings->enable_macvlan) 3177 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3178 3179 wr32(hw, I40E_PFQF_CTL_0, val); 3180 3181 return 0; 3182 } 3183 3184 /** 3185 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3186 * @hw: pointer to the hw struct 3187 * @mac_addr: MAC address to use in the filter 3188 * @ethtype: Ethertype to use in the filter 3189 * @flags: Flags that needs to be applied to the filter 3190 * @vsi_seid: seid of the control VSI 3191 * @queue: VSI queue number to send the packet to 3192 * @is_add: Add control packet filter if True else remove 3193 * @stats: Structure to hold information on control filter counts 3194 * @cmd_details: pointer to command details structure or NULL 3195 * 3196 * This command will Add or Remove control packet filter for a control VSI. 3197 * In return it will update the total number of perfect filter count in 3198 * the stats member. 3199 **/ 3200 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3201 u8 *mac_addr, u16 ethtype, u16 flags, 3202 u16 vsi_seid, u16 queue, bool is_add, 3203 struct i40e_control_filter_stats *stats, 3204 struct i40e_asq_cmd_details *cmd_details) 3205 { 3206 struct i40e_aq_desc desc; 3207 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3208 (struct i40e_aqc_add_remove_control_packet_filter *) 3209 &desc.params.raw; 3210 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3211 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3212 &desc.params.raw; 3213 i40e_status status; 3214 3215 if (vsi_seid == 0) 3216 return I40E_ERR_PARAM; 3217 3218 if (is_add) { 3219 i40e_fill_default_direct_cmd_desc(&desc, 3220 i40e_aqc_opc_add_control_packet_filter); 3221 cmd->queue = cpu_to_le16(queue); 3222 } else { 3223 i40e_fill_default_direct_cmd_desc(&desc, 3224 i40e_aqc_opc_remove_control_packet_filter); 3225 } 3226 3227 if (mac_addr) 3228 memcpy(cmd->mac, mac_addr, ETH_ALEN); 3229 3230 cmd->etype = cpu_to_le16(ethtype); 3231 cmd->flags = cpu_to_le16(flags); 3232 cmd->seid = cpu_to_le16(vsi_seid); 3233 3234 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3235 3236 if (!status && stats) { 3237 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3238 stats->etype_used = le16_to_cpu(resp->etype_used); 3239 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3240 stats->etype_free = le16_to_cpu(resp->etype_free); 3241 } 3242 3243 return status; 3244 } 3245 3246 /** 3247 * i40e_aq_resume_port_tx 3248 * @hw: pointer to the hardware structure 3249 * @cmd_details: pointer to command details structure or NULL 3250 * 3251 * Resume port's Tx traffic 3252 **/ 3253 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 3254 struct i40e_asq_cmd_details *cmd_details) 3255 { 3256 struct i40e_aq_desc desc; 3257 i40e_status status; 3258 3259 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3260 3261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3262 3263 return status; 3264 } 3265 3266 /** 3267 * i40e_set_pci_config_data - store PCI bus info 3268 * @hw: pointer to hardware structure 3269 * @link_status: the link status word from PCI config space 3270 * 3271 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3272 **/ 3273 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3274 { 3275 hw->bus.type = i40e_bus_type_pci_express; 3276 3277 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3278 case PCI_EXP_LNKSTA_NLW_X1: 3279 hw->bus.width = i40e_bus_width_pcie_x1; 3280 break; 3281 case PCI_EXP_LNKSTA_NLW_X2: 3282 hw->bus.width = i40e_bus_width_pcie_x2; 3283 break; 3284 case PCI_EXP_LNKSTA_NLW_X4: 3285 hw->bus.width = i40e_bus_width_pcie_x4; 3286 break; 3287 case PCI_EXP_LNKSTA_NLW_X8: 3288 hw->bus.width = i40e_bus_width_pcie_x8; 3289 break; 3290 default: 3291 hw->bus.width = i40e_bus_width_unknown; 3292 break; 3293 } 3294 3295 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3296 case PCI_EXP_LNKSTA_CLS_2_5GB: 3297 hw->bus.speed = i40e_bus_speed_2500; 3298 break; 3299 case PCI_EXP_LNKSTA_CLS_5_0GB: 3300 hw->bus.speed = i40e_bus_speed_5000; 3301 break; 3302 case PCI_EXP_LNKSTA_CLS_8_0GB: 3303 hw->bus.speed = i40e_bus_speed_8000; 3304 break; 3305 default: 3306 hw->bus.speed = i40e_bus_speed_unknown; 3307 break; 3308 } 3309 } 3310