1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 * 4 * Intel Ethernet Controller XL710 Family Linux Driver 5 * Copyright(c) 2013 - 2016 Intel Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 * 22 * Contact Information: 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * 26 ******************************************************************************/ 27 28 #include "i40e_type.h" 29 #include "i40e_adminq.h" 30 #include "i40e_prototype.h" 31 #include <linux/avf/virtchnl.h> 32 33 /** 34 * i40e_set_mac_type - Sets MAC type 35 * @hw: pointer to the HW structure 36 * 37 * This function sets the mac type of the adapter based on the 38 * vendor ID and device ID stored in the hw structure. 39 **/ 40 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 41 { 42 i40e_status status = 0; 43 44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 45 switch (hw->device_id) { 46 case I40E_DEV_ID_SFP_XL710: 47 case I40E_DEV_ID_QEMU: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 case I40E_DEV_ID_10G_BASE_T: 54 case I40E_DEV_ID_10G_BASE_T4: 55 case I40E_DEV_ID_20G_KR2: 56 case I40E_DEV_ID_20G_KR2_A: 57 case I40E_DEV_ID_25G_B: 58 case I40E_DEV_ID_25G_SFP28: 59 hw->mac.type = I40E_MAC_XL710; 60 break; 61 case I40E_DEV_ID_KX_X722: 62 case I40E_DEV_ID_QSFP_X722: 63 case I40E_DEV_ID_SFP_X722: 64 case I40E_DEV_ID_1G_BASE_T_X722: 65 case I40E_DEV_ID_10G_BASE_T_X722: 66 case I40E_DEV_ID_SFP_I_X722: 67 hw->mac.type = I40E_MAC_X722; 68 break; 69 default: 70 hw->mac.type = I40E_MAC_GENERIC; 71 break; 72 } 73 } else { 74 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 75 } 76 77 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 78 hw->mac.type, status); 79 return status; 80 } 81 82 /** 83 * i40e_aq_str - convert AQ err code to a string 84 * @hw: pointer to the HW structure 85 * @aq_err: the AQ error code to convert 86 **/ 87 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 88 { 89 switch (aq_err) { 90 case I40E_AQ_RC_OK: 91 return "OK"; 92 case I40E_AQ_RC_EPERM: 93 return "I40E_AQ_RC_EPERM"; 94 case I40E_AQ_RC_ENOENT: 95 return "I40E_AQ_RC_ENOENT"; 96 case I40E_AQ_RC_ESRCH: 97 return "I40E_AQ_RC_ESRCH"; 98 case I40E_AQ_RC_EINTR: 99 return "I40E_AQ_RC_EINTR"; 100 case I40E_AQ_RC_EIO: 101 return "I40E_AQ_RC_EIO"; 102 case I40E_AQ_RC_ENXIO: 103 return "I40E_AQ_RC_ENXIO"; 104 case I40E_AQ_RC_E2BIG: 105 return "I40E_AQ_RC_E2BIG"; 106 case I40E_AQ_RC_EAGAIN: 107 return "I40E_AQ_RC_EAGAIN"; 108 case I40E_AQ_RC_ENOMEM: 109 return "I40E_AQ_RC_ENOMEM"; 110 case I40E_AQ_RC_EACCES: 111 return "I40E_AQ_RC_EACCES"; 112 case I40E_AQ_RC_EFAULT: 113 return "I40E_AQ_RC_EFAULT"; 114 case I40E_AQ_RC_EBUSY: 115 return "I40E_AQ_RC_EBUSY"; 116 case I40E_AQ_RC_EEXIST: 117 return "I40E_AQ_RC_EEXIST"; 118 case I40E_AQ_RC_EINVAL: 119 return "I40E_AQ_RC_EINVAL"; 120 case I40E_AQ_RC_ENOTTY: 121 return "I40E_AQ_RC_ENOTTY"; 122 case I40E_AQ_RC_ENOSPC: 123 return "I40E_AQ_RC_ENOSPC"; 124 case I40E_AQ_RC_ENOSYS: 125 return "I40E_AQ_RC_ENOSYS"; 126 case I40E_AQ_RC_ERANGE: 127 return "I40E_AQ_RC_ERANGE"; 128 case I40E_AQ_RC_EFLUSHED: 129 return "I40E_AQ_RC_EFLUSHED"; 130 case I40E_AQ_RC_BAD_ADDR: 131 return "I40E_AQ_RC_BAD_ADDR"; 132 case I40E_AQ_RC_EMODE: 133 return "I40E_AQ_RC_EMODE"; 134 case I40E_AQ_RC_EFBIG: 135 return "I40E_AQ_RC_EFBIG"; 136 } 137 138 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 139 return hw->err_str; 140 } 141 142 /** 143 * i40e_stat_str - convert status err code to a string 144 * @hw: pointer to the HW structure 145 * @stat_err: the status error code to convert 146 **/ 147 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 148 { 149 switch (stat_err) { 150 case 0: 151 return "OK"; 152 case I40E_ERR_NVM: 153 return "I40E_ERR_NVM"; 154 case I40E_ERR_NVM_CHECKSUM: 155 return "I40E_ERR_NVM_CHECKSUM"; 156 case I40E_ERR_PHY: 157 return "I40E_ERR_PHY"; 158 case I40E_ERR_CONFIG: 159 return "I40E_ERR_CONFIG"; 160 case I40E_ERR_PARAM: 161 return "I40E_ERR_PARAM"; 162 case I40E_ERR_MAC_TYPE: 163 return "I40E_ERR_MAC_TYPE"; 164 case I40E_ERR_UNKNOWN_PHY: 165 return "I40E_ERR_UNKNOWN_PHY"; 166 case I40E_ERR_LINK_SETUP: 167 return "I40E_ERR_LINK_SETUP"; 168 case I40E_ERR_ADAPTER_STOPPED: 169 return "I40E_ERR_ADAPTER_STOPPED"; 170 case I40E_ERR_INVALID_MAC_ADDR: 171 return "I40E_ERR_INVALID_MAC_ADDR"; 172 case I40E_ERR_DEVICE_NOT_SUPPORTED: 173 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 174 case I40E_ERR_MASTER_REQUESTS_PENDING: 175 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 176 case I40E_ERR_INVALID_LINK_SETTINGS: 177 return "I40E_ERR_INVALID_LINK_SETTINGS"; 178 case I40E_ERR_AUTONEG_NOT_COMPLETE: 179 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 180 case I40E_ERR_RESET_FAILED: 181 return "I40E_ERR_RESET_FAILED"; 182 case I40E_ERR_SWFW_SYNC: 183 return "I40E_ERR_SWFW_SYNC"; 184 case I40E_ERR_NO_AVAILABLE_VSI: 185 return "I40E_ERR_NO_AVAILABLE_VSI"; 186 case I40E_ERR_NO_MEMORY: 187 return "I40E_ERR_NO_MEMORY"; 188 case I40E_ERR_BAD_PTR: 189 return "I40E_ERR_BAD_PTR"; 190 case I40E_ERR_RING_FULL: 191 return "I40E_ERR_RING_FULL"; 192 case I40E_ERR_INVALID_PD_ID: 193 return "I40E_ERR_INVALID_PD_ID"; 194 case I40E_ERR_INVALID_QP_ID: 195 return "I40E_ERR_INVALID_QP_ID"; 196 case I40E_ERR_INVALID_CQ_ID: 197 return "I40E_ERR_INVALID_CQ_ID"; 198 case I40E_ERR_INVALID_CEQ_ID: 199 return "I40E_ERR_INVALID_CEQ_ID"; 200 case I40E_ERR_INVALID_AEQ_ID: 201 return "I40E_ERR_INVALID_AEQ_ID"; 202 case I40E_ERR_INVALID_SIZE: 203 return "I40E_ERR_INVALID_SIZE"; 204 case I40E_ERR_INVALID_ARP_INDEX: 205 return "I40E_ERR_INVALID_ARP_INDEX"; 206 case I40E_ERR_INVALID_FPM_FUNC_ID: 207 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 208 case I40E_ERR_QP_INVALID_MSG_SIZE: 209 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 210 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 211 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 212 case I40E_ERR_INVALID_FRAG_COUNT: 213 return "I40E_ERR_INVALID_FRAG_COUNT"; 214 case I40E_ERR_QUEUE_EMPTY: 215 return "I40E_ERR_QUEUE_EMPTY"; 216 case I40E_ERR_INVALID_ALIGNMENT: 217 return "I40E_ERR_INVALID_ALIGNMENT"; 218 case I40E_ERR_FLUSHED_QUEUE: 219 return "I40E_ERR_FLUSHED_QUEUE"; 220 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 221 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 222 case I40E_ERR_INVALID_IMM_DATA_SIZE: 223 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 224 case I40E_ERR_TIMEOUT: 225 return "I40E_ERR_TIMEOUT"; 226 case I40E_ERR_OPCODE_MISMATCH: 227 return "I40E_ERR_OPCODE_MISMATCH"; 228 case I40E_ERR_CQP_COMPL_ERROR: 229 return "I40E_ERR_CQP_COMPL_ERROR"; 230 case I40E_ERR_INVALID_VF_ID: 231 return "I40E_ERR_INVALID_VF_ID"; 232 case I40E_ERR_INVALID_HMCFN_ID: 233 return "I40E_ERR_INVALID_HMCFN_ID"; 234 case I40E_ERR_BACKING_PAGE_ERROR: 235 return "I40E_ERR_BACKING_PAGE_ERROR"; 236 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 237 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 238 case I40E_ERR_INVALID_PBLE_INDEX: 239 return "I40E_ERR_INVALID_PBLE_INDEX"; 240 case I40E_ERR_INVALID_SD_INDEX: 241 return "I40E_ERR_INVALID_SD_INDEX"; 242 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 243 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 244 case I40E_ERR_INVALID_SD_TYPE: 245 return "I40E_ERR_INVALID_SD_TYPE"; 246 case I40E_ERR_MEMCPY_FAILED: 247 return "I40E_ERR_MEMCPY_FAILED"; 248 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 249 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 250 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 251 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 252 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 253 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 254 case I40E_ERR_SRQ_ENABLED: 255 return "I40E_ERR_SRQ_ENABLED"; 256 case I40E_ERR_ADMIN_QUEUE_ERROR: 257 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 258 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 259 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 260 case I40E_ERR_BUF_TOO_SHORT: 261 return "I40E_ERR_BUF_TOO_SHORT"; 262 case I40E_ERR_ADMIN_QUEUE_FULL: 263 return "I40E_ERR_ADMIN_QUEUE_FULL"; 264 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 265 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 266 case I40E_ERR_BAD_IWARP_CQE: 267 return "I40E_ERR_BAD_IWARP_CQE"; 268 case I40E_ERR_NVM_BLANK_MODE: 269 return "I40E_ERR_NVM_BLANK_MODE"; 270 case I40E_ERR_NOT_IMPLEMENTED: 271 return "I40E_ERR_NOT_IMPLEMENTED"; 272 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 273 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 274 case I40E_ERR_DIAG_TEST_FAILED: 275 return "I40E_ERR_DIAG_TEST_FAILED"; 276 case I40E_ERR_NOT_READY: 277 return "I40E_ERR_NOT_READY"; 278 case I40E_NOT_SUPPORTED: 279 return "I40E_NOT_SUPPORTED"; 280 case I40E_ERR_FIRMWARE_API_VERSION: 281 return "I40E_ERR_FIRMWARE_API_VERSION"; 282 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 283 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 284 } 285 286 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 287 return hw->err_str; 288 } 289 290 /** 291 * i40e_debug_aq 292 * @hw: debug mask related to admin queue 293 * @mask: debug mask 294 * @desc: pointer to admin queue descriptor 295 * @buffer: pointer to command buffer 296 * @buf_len: max length of buffer 297 * 298 * Dumps debug log about adminq command with descriptor contents. 299 **/ 300 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 301 void *buffer, u16 buf_len) 302 { 303 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 304 u16 len; 305 u8 *buf = (u8 *)buffer; 306 307 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 308 return; 309 310 len = le16_to_cpu(aq_desc->datalen); 311 312 i40e_debug(hw, mask, 313 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 314 le16_to_cpu(aq_desc->opcode), 315 le16_to_cpu(aq_desc->flags), 316 le16_to_cpu(aq_desc->datalen), 317 le16_to_cpu(aq_desc->retval)); 318 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->cookie_high), 320 le32_to_cpu(aq_desc->cookie_low)); 321 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.internal.param0), 323 le32_to_cpu(aq_desc->params.internal.param1)); 324 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 325 le32_to_cpu(aq_desc->params.external.addr_high), 326 le32_to_cpu(aq_desc->params.external.addr_low)); 327 328 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 329 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 330 if (buf_len < len) 331 len = buf_len; 332 /* write the full 16-byte chunks */ 333 if (hw->debug_mask & mask) { 334 char prefix[27]; 335 336 snprintf(prefix, sizeof(prefix), 337 "i40e %02x:%02x.%x: \t0x", 338 hw->bus.bus_id, 339 hw->bus.device, 340 hw->bus.func); 341 342 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 343 16, 1, buf, len, false); 344 } 345 } 346 } 347 348 /** 349 * i40e_check_asq_alive 350 * @hw: pointer to the hw struct 351 * 352 * Returns true if Queue is enabled else false. 353 **/ 354 bool i40e_check_asq_alive(struct i40e_hw *hw) 355 { 356 if (hw->aq.asq.len) 357 return !!(rd32(hw, hw->aq.asq.len) & 358 I40E_PF_ATQLEN_ATQENABLE_MASK); 359 else 360 return false; 361 } 362 363 /** 364 * i40e_aq_queue_shutdown 365 * @hw: pointer to the hw struct 366 * @unloading: is the driver unloading itself 367 * 368 * Tell the Firmware that we're shutting down the AdminQ and whether 369 * or not the driver is unloading as well. 370 **/ 371 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 372 bool unloading) 373 { 374 struct i40e_aq_desc desc; 375 struct i40e_aqc_queue_shutdown *cmd = 376 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 377 i40e_status status; 378 379 i40e_fill_default_direct_cmd_desc(&desc, 380 i40e_aqc_opc_queue_shutdown); 381 382 if (unloading) 383 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 384 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 385 386 return status; 387 } 388 389 /** 390 * i40e_aq_get_set_rss_lut 391 * @hw: pointer to the hardware structure 392 * @vsi_id: vsi fw index 393 * @pf_lut: for PF table set true, for VSI table set false 394 * @lut: pointer to the lut buffer provided by the caller 395 * @lut_size: size of the lut buffer 396 * @set: set true to set the table, false to get the table 397 * 398 * Internal function to get or set RSS look up table 399 **/ 400 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 401 u16 vsi_id, bool pf_lut, 402 u8 *lut, u16 lut_size, 403 bool set) 404 { 405 i40e_status status; 406 struct i40e_aq_desc desc; 407 struct i40e_aqc_get_set_rss_lut *cmd_resp = 408 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 409 410 if (set) 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_set_rss_lut); 413 else 414 i40e_fill_default_direct_cmd_desc(&desc, 415 i40e_aqc_opc_get_rss_lut); 416 417 /* Indirect command */ 418 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 419 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 420 421 cmd_resp->vsi_id = 422 cpu_to_le16((u16)((vsi_id << 423 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 424 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 425 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 426 427 if (pf_lut) 428 cmd_resp->flags |= cpu_to_le16((u16) 429 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 430 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 431 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 432 else 433 cmd_resp->flags |= cpu_to_le16((u16) 434 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 435 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 436 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 437 438 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 439 440 return status; 441 } 442 443 /** 444 * i40e_aq_get_rss_lut 445 * @hw: pointer to the hardware structure 446 * @vsi_id: vsi fw index 447 * @pf_lut: for PF table set true, for VSI table set false 448 * @lut: pointer to the lut buffer provided by the caller 449 * @lut_size: size of the lut buffer 450 * 451 * get the RSS lookup table, PF or VSI type 452 **/ 453 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 454 bool pf_lut, u8 *lut, u16 lut_size) 455 { 456 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 457 false); 458 } 459 460 /** 461 * i40e_aq_set_rss_lut 462 * @hw: pointer to the hardware structure 463 * @vsi_id: vsi fw index 464 * @pf_lut: for PF table set true, for VSI table set false 465 * @lut: pointer to the lut buffer provided by the caller 466 * @lut_size: size of the lut buffer 467 * 468 * set the RSS lookup table, PF or VSI type 469 **/ 470 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 471 bool pf_lut, u8 *lut, u16 lut_size) 472 { 473 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 474 } 475 476 /** 477 * i40e_aq_get_set_rss_key 478 * @hw: pointer to the hw struct 479 * @vsi_id: vsi fw index 480 * @key: pointer to key info struct 481 * @set: set true to set the key, false to get the key 482 * 483 * get the RSS key per VSI 484 **/ 485 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 486 u16 vsi_id, 487 struct i40e_aqc_get_set_rss_key_data *key, 488 bool set) 489 { 490 i40e_status status; 491 struct i40e_aq_desc desc; 492 struct i40e_aqc_get_set_rss_key *cmd_resp = 493 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 494 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 495 496 if (set) 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_set_rss_key); 499 else 500 i40e_fill_default_direct_cmd_desc(&desc, 501 i40e_aqc_opc_get_rss_key); 502 503 /* Indirect command */ 504 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 505 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 506 507 cmd_resp->vsi_id = 508 cpu_to_le16((u16)((vsi_id << 509 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 510 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 511 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 512 513 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 514 515 return status; 516 } 517 518 /** 519 * i40e_aq_get_rss_key 520 * @hw: pointer to the hw struct 521 * @vsi_id: vsi fw index 522 * @key: pointer to key info struct 523 * 524 **/ 525 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 526 u16 vsi_id, 527 struct i40e_aqc_get_set_rss_key_data *key) 528 { 529 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 530 } 531 532 /** 533 * i40e_aq_set_rss_key 534 * @hw: pointer to the hw struct 535 * @vsi_id: vsi fw index 536 * @key: pointer to key info struct 537 * 538 * set the RSS key per VSI 539 **/ 540 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 541 u16 vsi_id, 542 struct i40e_aqc_get_set_rss_key_data *key) 543 { 544 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 545 } 546 547 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 548 * hardware to a bit-field that can be used by SW to more easily determine the 549 * packet type. 550 * 551 * Macros are used to shorten the table lines and make this table human 552 * readable. 553 * 554 * We store the PTYPE in the top byte of the bit field - this is just so that 555 * we can check that the table doesn't have a row missing, as the index into 556 * the table should be the PTYPE. 557 * 558 * Typical work flow: 559 * 560 * IF NOT i40e_ptype_lookup[ptype].known 561 * THEN 562 * Packet is unknown 563 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 564 * Use the rest of the fields to look at the tunnels, inner protocols, etc 565 * ELSE 566 * Use the enum i40e_rx_l2_ptype to decode the packet type 567 * ENDIF 568 */ 569 570 /* macro to make the table lines short */ 571 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 572 { PTYPE, \ 573 1, \ 574 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 575 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 576 I40E_RX_PTYPE_##OUTER_FRAG, \ 577 I40E_RX_PTYPE_TUNNEL_##T, \ 578 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 579 I40E_RX_PTYPE_##TEF, \ 580 I40E_RX_PTYPE_INNER_PROT_##I, \ 581 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 582 583 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 584 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 585 586 /* shorter macros makes the table fit but are terse */ 587 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 588 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 589 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 590 591 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 592 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 593 /* L2 Packet types */ 594 I40E_PTT_UNUSED_ENTRY(0), 595 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 596 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 597 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT_UNUSED_ENTRY(4), 599 I40E_PTT_UNUSED_ENTRY(5), 600 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 601 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT_UNUSED_ENTRY(8), 603 I40E_PTT_UNUSED_ENTRY(9), 604 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 605 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 606 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 614 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 615 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 616 617 /* Non Tunneled IPv4 */ 618 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 619 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 620 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 621 I40E_PTT_UNUSED_ENTRY(25), 622 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 623 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 624 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 625 626 /* IPv4 --> IPv4 */ 627 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 628 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 629 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 630 I40E_PTT_UNUSED_ENTRY(32), 631 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 632 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 633 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 634 635 /* IPv4 --> IPv6 */ 636 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 637 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 638 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 639 I40E_PTT_UNUSED_ENTRY(39), 640 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 641 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 642 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 643 644 /* IPv4 --> GRE/NAT */ 645 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 646 647 /* IPv4 --> GRE/NAT --> IPv4 */ 648 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 649 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 650 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 651 I40E_PTT_UNUSED_ENTRY(47), 652 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 653 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 654 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 655 656 /* IPv4 --> GRE/NAT --> IPv6 */ 657 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 658 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 659 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(54), 661 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 662 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 663 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 664 665 /* IPv4 --> GRE/NAT --> MAC */ 666 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 667 668 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 669 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 670 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 671 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(62), 673 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 674 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 675 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 676 677 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 678 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 679 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 680 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(69), 682 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 683 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 684 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 685 686 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 687 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 688 689 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 690 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 691 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 692 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 693 I40E_PTT_UNUSED_ENTRY(77), 694 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 695 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 696 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 697 698 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 699 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 700 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 701 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(84), 703 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 704 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 705 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 706 707 /* Non Tunneled IPv6 */ 708 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 709 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 710 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(91), 712 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 713 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 714 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 715 716 /* IPv6 --> IPv4 */ 717 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 718 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 719 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 720 I40E_PTT_UNUSED_ENTRY(98), 721 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 722 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 723 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 724 725 /* IPv6 --> IPv6 */ 726 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 727 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 728 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 729 I40E_PTT_UNUSED_ENTRY(105), 730 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 731 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 732 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 733 734 /* IPv6 --> GRE/NAT */ 735 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 736 737 /* IPv6 --> GRE/NAT -> IPv4 */ 738 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 739 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 740 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(113), 742 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 743 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 744 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 745 746 /* IPv6 --> GRE/NAT -> IPv6 */ 747 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 748 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 749 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(120), 751 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 752 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 753 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 754 755 /* IPv6 --> GRE/NAT -> MAC */ 756 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 757 758 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 759 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 760 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 761 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(128), 763 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 764 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 765 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 766 767 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 768 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 769 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 770 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(135), 772 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 773 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 774 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 777 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 778 779 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 780 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 781 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 782 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 783 I40E_PTT_UNUSED_ENTRY(143), 784 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 785 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 786 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 787 788 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 789 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 790 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 791 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(150), 793 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 794 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 795 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 796 797 /* unused entries */ 798 I40E_PTT_UNUSED_ENTRY(154), 799 I40E_PTT_UNUSED_ENTRY(155), 800 I40E_PTT_UNUSED_ENTRY(156), 801 I40E_PTT_UNUSED_ENTRY(157), 802 I40E_PTT_UNUSED_ENTRY(158), 803 I40E_PTT_UNUSED_ENTRY(159), 804 805 I40E_PTT_UNUSED_ENTRY(160), 806 I40E_PTT_UNUSED_ENTRY(161), 807 I40E_PTT_UNUSED_ENTRY(162), 808 I40E_PTT_UNUSED_ENTRY(163), 809 I40E_PTT_UNUSED_ENTRY(164), 810 I40E_PTT_UNUSED_ENTRY(165), 811 I40E_PTT_UNUSED_ENTRY(166), 812 I40E_PTT_UNUSED_ENTRY(167), 813 I40E_PTT_UNUSED_ENTRY(168), 814 I40E_PTT_UNUSED_ENTRY(169), 815 816 I40E_PTT_UNUSED_ENTRY(170), 817 I40E_PTT_UNUSED_ENTRY(171), 818 I40E_PTT_UNUSED_ENTRY(172), 819 I40E_PTT_UNUSED_ENTRY(173), 820 I40E_PTT_UNUSED_ENTRY(174), 821 I40E_PTT_UNUSED_ENTRY(175), 822 I40E_PTT_UNUSED_ENTRY(176), 823 I40E_PTT_UNUSED_ENTRY(177), 824 I40E_PTT_UNUSED_ENTRY(178), 825 I40E_PTT_UNUSED_ENTRY(179), 826 827 I40E_PTT_UNUSED_ENTRY(180), 828 I40E_PTT_UNUSED_ENTRY(181), 829 I40E_PTT_UNUSED_ENTRY(182), 830 I40E_PTT_UNUSED_ENTRY(183), 831 I40E_PTT_UNUSED_ENTRY(184), 832 I40E_PTT_UNUSED_ENTRY(185), 833 I40E_PTT_UNUSED_ENTRY(186), 834 I40E_PTT_UNUSED_ENTRY(187), 835 I40E_PTT_UNUSED_ENTRY(188), 836 I40E_PTT_UNUSED_ENTRY(189), 837 838 I40E_PTT_UNUSED_ENTRY(190), 839 I40E_PTT_UNUSED_ENTRY(191), 840 I40E_PTT_UNUSED_ENTRY(192), 841 I40E_PTT_UNUSED_ENTRY(193), 842 I40E_PTT_UNUSED_ENTRY(194), 843 I40E_PTT_UNUSED_ENTRY(195), 844 I40E_PTT_UNUSED_ENTRY(196), 845 I40E_PTT_UNUSED_ENTRY(197), 846 I40E_PTT_UNUSED_ENTRY(198), 847 I40E_PTT_UNUSED_ENTRY(199), 848 849 I40E_PTT_UNUSED_ENTRY(200), 850 I40E_PTT_UNUSED_ENTRY(201), 851 I40E_PTT_UNUSED_ENTRY(202), 852 I40E_PTT_UNUSED_ENTRY(203), 853 I40E_PTT_UNUSED_ENTRY(204), 854 I40E_PTT_UNUSED_ENTRY(205), 855 I40E_PTT_UNUSED_ENTRY(206), 856 I40E_PTT_UNUSED_ENTRY(207), 857 I40E_PTT_UNUSED_ENTRY(208), 858 I40E_PTT_UNUSED_ENTRY(209), 859 860 I40E_PTT_UNUSED_ENTRY(210), 861 I40E_PTT_UNUSED_ENTRY(211), 862 I40E_PTT_UNUSED_ENTRY(212), 863 I40E_PTT_UNUSED_ENTRY(213), 864 I40E_PTT_UNUSED_ENTRY(214), 865 I40E_PTT_UNUSED_ENTRY(215), 866 I40E_PTT_UNUSED_ENTRY(216), 867 I40E_PTT_UNUSED_ENTRY(217), 868 I40E_PTT_UNUSED_ENTRY(218), 869 I40E_PTT_UNUSED_ENTRY(219), 870 871 I40E_PTT_UNUSED_ENTRY(220), 872 I40E_PTT_UNUSED_ENTRY(221), 873 I40E_PTT_UNUSED_ENTRY(222), 874 I40E_PTT_UNUSED_ENTRY(223), 875 I40E_PTT_UNUSED_ENTRY(224), 876 I40E_PTT_UNUSED_ENTRY(225), 877 I40E_PTT_UNUSED_ENTRY(226), 878 I40E_PTT_UNUSED_ENTRY(227), 879 I40E_PTT_UNUSED_ENTRY(228), 880 I40E_PTT_UNUSED_ENTRY(229), 881 882 I40E_PTT_UNUSED_ENTRY(230), 883 I40E_PTT_UNUSED_ENTRY(231), 884 I40E_PTT_UNUSED_ENTRY(232), 885 I40E_PTT_UNUSED_ENTRY(233), 886 I40E_PTT_UNUSED_ENTRY(234), 887 I40E_PTT_UNUSED_ENTRY(235), 888 I40E_PTT_UNUSED_ENTRY(236), 889 I40E_PTT_UNUSED_ENTRY(237), 890 I40E_PTT_UNUSED_ENTRY(238), 891 I40E_PTT_UNUSED_ENTRY(239), 892 893 I40E_PTT_UNUSED_ENTRY(240), 894 I40E_PTT_UNUSED_ENTRY(241), 895 I40E_PTT_UNUSED_ENTRY(242), 896 I40E_PTT_UNUSED_ENTRY(243), 897 I40E_PTT_UNUSED_ENTRY(244), 898 I40E_PTT_UNUSED_ENTRY(245), 899 I40E_PTT_UNUSED_ENTRY(246), 900 I40E_PTT_UNUSED_ENTRY(247), 901 I40E_PTT_UNUSED_ENTRY(248), 902 I40E_PTT_UNUSED_ENTRY(249), 903 904 I40E_PTT_UNUSED_ENTRY(250), 905 I40E_PTT_UNUSED_ENTRY(251), 906 I40E_PTT_UNUSED_ENTRY(252), 907 I40E_PTT_UNUSED_ENTRY(253), 908 I40E_PTT_UNUSED_ENTRY(254), 909 I40E_PTT_UNUSED_ENTRY(255) 910 }; 911 912 /** 913 * i40e_init_shared_code - Initialize the shared code 914 * @hw: pointer to hardware structure 915 * 916 * This assigns the MAC type and PHY code and inits the NVM. 917 * Does not touch the hardware. This function must be called prior to any 918 * other function in the shared code. The i40e_hw structure should be 919 * memset to 0 prior to calling this function. The following fields in 920 * hw structure should be filled in prior to calling this function: 921 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 922 * subsystem_vendor_id, and revision_id 923 **/ 924 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 925 { 926 i40e_status status = 0; 927 u32 port, ari, func_rid; 928 929 i40e_set_mac_type(hw); 930 931 switch (hw->mac.type) { 932 case I40E_MAC_XL710: 933 case I40E_MAC_X722: 934 break; 935 default: 936 return I40E_ERR_DEVICE_NOT_SUPPORTED; 937 } 938 939 hw->phy.get_link_info = true; 940 941 /* Determine port number and PF number*/ 942 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 943 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 944 hw->port = (u8)port; 945 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 946 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 947 func_rid = rd32(hw, I40E_PF_FUNC_RID); 948 if (ari) 949 hw->pf_id = (u8)(func_rid & 0xff); 950 else 951 hw->pf_id = (u8)(func_rid & 0x7); 952 953 if (hw->mac.type == I40E_MAC_X722) 954 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 955 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 956 957 status = i40e_init_nvm(hw); 958 return status; 959 } 960 961 /** 962 * i40e_aq_mac_address_read - Retrieve the MAC addresses 963 * @hw: pointer to the hw struct 964 * @flags: a return indicator of what addresses were added to the addr store 965 * @addrs: the requestor's mac addr store 966 * @cmd_details: pointer to command details structure or NULL 967 **/ 968 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 969 u16 *flags, 970 struct i40e_aqc_mac_address_read_data *addrs, 971 struct i40e_asq_cmd_details *cmd_details) 972 { 973 struct i40e_aq_desc desc; 974 struct i40e_aqc_mac_address_read *cmd_data = 975 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 976 i40e_status status; 977 978 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 979 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 980 981 status = i40e_asq_send_command(hw, &desc, addrs, 982 sizeof(*addrs), cmd_details); 983 *flags = le16_to_cpu(cmd_data->command_flags); 984 985 return status; 986 } 987 988 /** 989 * i40e_aq_mac_address_write - Change the MAC addresses 990 * @hw: pointer to the hw struct 991 * @flags: indicates which MAC to be written 992 * @mac_addr: address to write 993 * @cmd_details: pointer to command details structure or NULL 994 **/ 995 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 996 u16 flags, u8 *mac_addr, 997 struct i40e_asq_cmd_details *cmd_details) 998 { 999 struct i40e_aq_desc desc; 1000 struct i40e_aqc_mac_address_write *cmd_data = 1001 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1002 i40e_status status; 1003 1004 i40e_fill_default_direct_cmd_desc(&desc, 1005 i40e_aqc_opc_mac_address_write); 1006 cmd_data->command_flags = cpu_to_le16(flags); 1007 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1008 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1009 ((u32)mac_addr[3] << 16) | 1010 ((u32)mac_addr[4] << 8) | 1011 mac_addr[5]); 1012 1013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1014 1015 return status; 1016 } 1017 1018 /** 1019 * i40e_get_mac_addr - get MAC address 1020 * @hw: pointer to the HW structure 1021 * @mac_addr: pointer to MAC address 1022 * 1023 * Reads the adapter's MAC address from register 1024 **/ 1025 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1026 { 1027 struct i40e_aqc_mac_address_read_data addrs; 1028 i40e_status status; 1029 u16 flags = 0; 1030 1031 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1032 1033 if (flags & I40E_AQC_LAN_ADDR_VALID) 1034 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1035 1036 return status; 1037 } 1038 1039 /** 1040 * i40e_get_port_mac_addr - get Port MAC address 1041 * @hw: pointer to the HW structure 1042 * @mac_addr: pointer to Port MAC address 1043 * 1044 * Reads the adapter's Port MAC address 1045 **/ 1046 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1047 { 1048 struct i40e_aqc_mac_address_read_data addrs; 1049 i40e_status status; 1050 u16 flags = 0; 1051 1052 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1053 if (status) 1054 return status; 1055 1056 if (flags & I40E_AQC_PORT_ADDR_VALID) 1057 ether_addr_copy(mac_addr, addrs.port_mac); 1058 else 1059 status = I40E_ERR_INVALID_MAC_ADDR; 1060 1061 return status; 1062 } 1063 1064 /** 1065 * i40e_pre_tx_queue_cfg - pre tx queue configure 1066 * @hw: pointer to the HW structure 1067 * @queue: target PF queue index 1068 * @enable: state change request 1069 * 1070 * Handles hw requirement to indicate intention to enable 1071 * or disable target queue. 1072 **/ 1073 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1074 { 1075 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1076 u32 reg_block = 0; 1077 u32 reg_val; 1078 1079 if (abs_queue_idx >= 128) { 1080 reg_block = abs_queue_idx / 128; 1081 abs_queue_idx %= 128; 1082 } 1083 1084 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1085 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1086 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1087 1088 if (enable) 1089 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1090 else 1091 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1092 1093 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1094 } 1095 1096 /** 1097 * i40e_read_pba_string - Reads part number string from EEPROM 1098 * @hw: pointer to hardware structure 1099 * @pba_num: stores the part number string from the EEPROM 1100 * @pba_num_size: part number string buffer length 1101 * 1102 * Reads the part number string from the EEPROM. 1103 **/ 1104 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1105 u32 pba_num_size) 1106 { 1107 i40e_status status = 0; 1108 u16 pba_word = 0; 1109 u16 pba_size = 0; 1110 u16 pba_ptr = 0; 1111 u16 i = 0; 1112 1113 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1114 if (status || (pba_word != 0xFAFA)) { 1115 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1116 return status; 1117 } 1118 1119 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1120 if (status) { 1121 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1122 return status; 1123 } 1124 1125 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1126 if (status) { 1127 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1128 return status; 1129 } 1130 1131 /* Subtract one to get PBA word count (PBA Size word is included in 1132 * total size) 1133 */ 1134 pba_size--; 1135 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1136 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1137 return I40E_ERR_PARAM; 1138 } 1139 1140 for (i = 0; i < pba_size; i++) { 1141 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1142 if (status) { 1143 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1144 return status; 1145 } 1146 1147 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1148 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1149 } 1150 pba_num[(pba_size * 2)] = '\0'; 1151 1152 return status; 1153 } 1154 1155 /** 1156 * i40e_get_media_type - Gets media type 1157 * @hw: pointer to the hardware structure 1158 **/ 1159 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1160 { 1161 enum i40e_media_type media; 1162 1163 switch (hw->phy.link_info.phy_type) { 1164 case I40E_PHY_TYPE_10GBASE_SR: 1165 case I40E_PHY_TYPE_10GBASE_LR: 1166 case I40E_PHY_TYPE_1000BASE_SX: 1167 case I40E_PHY_TYPE_1000BASE_LX: 1168 case I40E_PHY_TYPE_40GBASE_SR4: 1169 case I40E_PHY_TYPE_40GBASE_LR4: 1170 case I40E_PHY_TYPE_25GBASE_LR: 1171 case I40E_PHY_TYPE_25GBASE_SR: 1172 media = I40E_MEDIA_TYPE_FIBER; 1173 break; 1174 case I40E_PHY_TYPE_100BASE_TX: 1175 case I40E_PHY_TYPE_1000BASE_T: 1176 case I40E_PHY_TYPE_10GBASE_T: 1177 media = I40E_MEDIA_TYPE_BASET; 1178 break; 1179 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1180 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1181 case I40E_PHY_TYPE_10GBASE_CR1: 1182 case I40E_PHY_TYPE_40GBASE_CR4: 1183 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1184 case I40E_PHY_TYPE_40GBASE_AOC: 1185 case I40E_PHY_TYPE_10GBASE_AOC: 1186 case I40E_PHY_TYPE_25GBASE_CR: 1187 case I40E_PHY_TYPE_25GBASE_AOC: 1188 case I40E_PHY_TYPE_25GBASE_ACC: 1189 media = I40E_MEDIA_TYPE_DA; 1190 break; 1191 case I40E_PHY_TYPE_1000BASE_KX: 1192 case I40E_PHY_TYPE_10GBASE_KX4: 1193 case I40E_PHY_TYPE_10GBASE_KR: 1194 case I40E_PHY_TYPE_40GBASE_KR4: 1195 case I40E_PHY_TYPE_20GBASE_KR2: 1196 case I40E_PHY_TYPE_25GBASE_KR: 1197 media = I40E_MEDIA_TYPE_BACKPLANE; 1198 break; 1199 case I40E_PHY_TYPE_SGMII: 1200 case I40E_PHY_TYPE_XAUI: 1201 case I40E_PHY_TYPE_XFI: 1202 case I40E_PHY_TYPE_XLAUI: 1203 case I40E_PHY_TYPE_XLPPI: 1204 default: 1205 media = I40E_MEDIA_TYPE_UNKNOWN; 1206 break; 1207 } 1208 1209 return media; 1210 } 1211 1212 /** 1213 * i40e_poll_globr - Poll for Global Reset completion 1214 * @hw: pointer to the hardware structure 1215 * @retry_limit: how many times to retry before failure 1216 **/ 1217 static i40e_status i40e_poll_globr(struct i40e_hw *hw, 1218 u32 retry_limit) 1219 { 1220 u32 cnt, reg = 0; 1221 1222 for (cnt = 0; cnt < retry_limit; cnt++) { 1223 reg = rd32(hw, I40E_GLGEN_RSTAT); 1224 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1225 return 0; 1226 msleep(100); 1227 } 1228 1229 hw_dbg(hw, "Global reset failed.\n"); 1230 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 1231 1232 return I40E_ERR_RESET_FAILED; 1233 } 1234 1235 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1236 #define I40E_PF_RESET_WAIT_COUNT 200 1237 /** 1238 * i40e_pf_reset - Reset the PF 1239 * @hw: pointer to the hardware structure 1240 * 1241 * Assuming someone else has triggered a global reset, 1242 * assure the global reset is complete and then reset the PF 1243 **/ 1244 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1245 { 1246 u32 cnt = 0; 1247 u32 cnt1 = 0; 1248 u32 reg = 0; 1249 u32 grst_del; 1250 1251 /* Poll for Global Reset steady state in case of recent GRST. 1252 * The grst delay value is in 100ms units, and we'll wait a 1253 * couple counts longer to be sure we don't just miss the end. 1254 */ 1255 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1256 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1257 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1258 1259 /* It can take upto 15 secs for GRST steady state. 1260 * Bump it to 16 secs max to be safe. 1261 */ 1262 grst_del = grst_del * 20; 1263 1264 for (cnt = 0; cnt < grst_del; cnt++) { 1265 reg = rd32(hw, I40E_GLGEN_RSTAT); 1266 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1267 break; 1268 msleep(100); 1269 } 1270 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1271 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1272 return I40E_ERR_RESET_FAILED; 1273 } 1274 1275 /* Now Wait for the FW to be ready */ 1276 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1277 reg = rd32(hw, I40E_GLNVM_ULD); 1278 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1279 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1280 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1281 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1282 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1283 break; 1284 } 1285 usleep_range(10000, 20000); 1286 } 1287 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1288 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1289 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1290 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1291 return I40E_ERR_RESET_FAILED; 1292 } 1293 1294 /* If there was a Global Reset in progress when we got here, 1295 * we don't need to do the PF Reset 1296 */ 1297 if (!cnt) { 1298 u32 reg2 = 0; 1299 if (hw->revision_id == 0) 1300 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1301 else 1302 cnt = I40E_PF_RESET_WAIT_COUNT; 1303 reg = rd32(hw, I40E_PFGEN_CTRL); 1304 wr32(hw, I40E_PFGEN_CTRL, 1305 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1306 for (; cnt; cnt--) { 1307 reg = rd32(hw, I40E_PFGEN_CTRL); 1308 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1309 break; 1310 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1311 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1312 break; 1313 usleep_range(1000, 2000); 1314 } 1315 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1316 if (i40e_poll_globr(hw, grst_del)) 1317 return I40E_ERR_RESET_FAILED; 1318 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1319 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1320 return I40E_ERR_RESET_FAILED; 1321 } 1322 } 1323 1324 i40e_clear_pxe_mode(hw); 1325 1326 return 0; 1327 } 1328 1329 /** 1330 * i40e_clear_hw - clear out any left over hw state 1331 * @hw: pointer to the hw struct 1332 * 1333 * Clear queues and interrupts, typically called at init time, 1334 * but after the capabilities have been found so we know how many 1335 * queues and msix vectors have been allocated. 1336 **/ 1337 void i40e_clear_hw(struct i40e_hw *hw) 1338 { 1339 u32 num_queues, base_queue; 1340 u32 num_pf_int; 1341 u32 num_vf_int; 1342 u32 num_vfs; 1343 u32 i, j; 1344 u32 val; 1345 u32 eol = 0x7ff; 1346 1347 /* get number of interrupts, queues, and VFs */ 1348 val = rd32(hw, I40E_GLPCI_CNF2); 1349 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1350 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1351 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1352 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1353 1354 val = rd32(hw, I40E_PFLAN_QALLOC); 1355 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1356 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1357 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1358 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1359 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1360 num_queues = (j - base_queue) + 1; 1361 else 1362 num_queues = 0; 1363 1364 val = rd32(hw, I40E_PF_VT_PFALLOC); 1365 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1366 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1367 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1368 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1369 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1370 num_vfs = (j - i) + 1; 1371 else 1372 num_vfs = 0; 1373 1374 /* stop all the interrupts */ 1375 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1376 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1377 for (i = 0; i < num_pf_int - 2; i++) 1378 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1379 1380 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1381 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1382 wr32(hw, I40E_PFINT_LNKLST0, val); 1383 for (i = 0; i < num_pf_int - 2; i++) 1384 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1385 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1386 for (i = 0; i < num_vfs; i++) 1387 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1388 for (i = 0; i < num_vf_int - 2; i++) 1389 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1390 1391 /* warn the HW of the coming Tx disables */ 1392 for (i = 0; i < num_queues; i++) { 1393 u32 abs_queue_idx = base_queue + i; 1394 u32 reg_block = 0; 1395 1396 if (abs_queue_idx >= 128) { 1397 reg_block = abs_queue_idx / 128; 1398 abs_queue_idx %= 128; 1399 } 1400 1401 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1402 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1403 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1404 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1405 1406 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1407 } 1408 udelay(400); 1409 1410 /* stop all the queues */ 1411 for (i = 0; i < num_queues; i++) { 1412 wr32(hw, I40E_QINT_TQCTL(i), 0); 1413 wr32(hw, I40E_QTX_ENA(i), 0); 1414 wr32(hw, I40E_QINT_RQCTL(i), 0); 1415 wr32(hw, I40E_QRX_ENA(i), 0); 1416 } 1417 1418 /* short wait for all queue disables to settle */ 1419 udelay(50); 1420 } 1421 1422 /** 1423 * i40e_clear_pxe_mode - clear pxe operations mode 1424 * @hw: pointer to the hw struct 1425 * 1426 * Make sure all PXE mode settings are cleared, including things 1427 * like descriptor fetch/write-back mode. 1428 **/ 1429 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1430 { 1431 u32 reg; 1432 1433 if (i40e_check_asq_alive(hw)) 1434 i40e_aq_clear_pxe_mode(hw, NULL); 1435 1436 /* Clear single descriptor fetch/write-back mode */ 1437 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1438 1439 if (hw->revision_id == 0) { 1440 /* As a work around clear PXE_MODE instead of setting it */ 1441 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1442 } else { 1443 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1444 } 1445 } 1446 1447 /** 1448 * i40e_led_is_mine - helper to find matching led 1449 * @hw: pointer to the hw struct 1450 * @idx: index into GPIO registers 1451 * 1452 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1453 */ 1454 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1455 { 1456 u32 gpio_val = 0; 1457 u32 port; 1458 1459 if (!hw->func_caps.led[idx]) 1460 return 0; 1461 1462 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1463 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1464 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1465 1466 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1467 * if it is not our port then ignore 1468 */ 1469 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1470 (port != hw->port)) 1471 return 0; 1472 1473 return gpio_val; 1474 } 1475 1476 #define I40E_COMBINED_ACTIVITY 0xA 1477 #define I40E_FILTER_ACTIVITY 0xE 1478 #define I40E_LINK_ACTIVITY 0xC 1479 #define I40E_MAC_ACTIVITY 0xD 1480 #define I40E_LED0 22 1481 1482 /** 1483 * i40e_led_get - return current on/off mode 1484 * @hw: pointer to the hw struct 1485 * 1486 * The value returned is the 'mode' field as defined in the 1487 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1488 * values are variations of possible behaviors relating to 1489 * blink, link, and wire. 1490 **/ 1491 u32 i40e_led_get(struct i40e_hw *hw) 1492 { 1493 u32 current_mode = 0; 1494 u32 mode = 0; 1495 int i; 1496 1497 /* as per the documentation GPIO 22-29 are the LED 1498 * GPIO pins named LED0..LED7 1499 */ 1500 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1501 u32 gpio_val = i40e_led_is_mine(hw, i); 1502 1503 if (!gpio_val) 1504 continue; 1505 1506 /* ignore gpio LED src mode entries related to the activity 1507 * LEDs 1508 */ 1509 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1510 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1511 switch (current_mode) { 1512 case I40E_COMBINED_ACTIVITY: 1513 case I40E_FILTER_ACTIVITY: 1514 case I40E_MAC_ACTIVITY: 1515 case I40E_LINK_ACTIVITY: 1516 continue; 1517 default: 1518 break; 1519 } 1520 1521 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1522 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1523 break; 1524 } 1525 1526 return mode; 1527 } 1528 1529 /** 1530 * i40e_led_set - set new on/off mode 1531 * @hw: pointer to the hw struct 1532 * @mode: 0=off, 0xf=on (else see manual for mode details) 1533 * @blink: true if the LED should blink when on, false if steady 1534 * 1535 * if this function is used to turn on the blink it should 1536 * be used to disable the blink when restoring the original state. 1537 **/ 1538 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1539 { 1540 u32 current_mode = 0; 1541 int i; 1542 1543 if (mode & 0xfffffff0) 1544 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1545 1546 /* as per the documentation GPIO 22-29 are the LED 1547 * GPIO pins named LED0..LED7 1548 */ 1549 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1550 u32 gpio_val = i40e_led_is_mine(hw, i); 1551 1552 if (!gpio_val) 1553 continue; 1554 1555 /* ignore gpio LED src mode entries related to the activity 1556 * LEDs 1557 */ 1558 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1559 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1560 switch (current_mode) { 1561 case I40E_COMBINED_ACTIVITY: 1562 case I40E_FILTER_ACTIVITY: 1563 case I40E_MAC_ACTIVITY: 1564 case I40E_LINK_ACTIVITY: 1565 continue; 1566 default: 1567 break; 1568 } 1569 1570 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1571 /* this & is a bit of paranoia, but serves as a range check */ 1572 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1573 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1574 1575 if (blink) 1576 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1577 else 1578 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1579 1580 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1581 break; 1582 } 1583 } 1584 1585 /* Admin command wrappers */ 1586 1587 /** 1588 * i40e_aq_get_phy_capabilities 1589 * @hw: pointer to the hw struct 1590 * @abilities: structure for PHY capabilities to be filled 1591 * @qualified_modules: report Qualified Modules 1592 * @report_init: report init capabilities (active are default) 1593 * @cmd_details: pointer to command details structure or NULL 1594 * 1595 * Returns the various PHY abilities supported on the Port. 1596 **/ 1597 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1598 bool qualified_modules, bool report_init, 1599 struct i40e_aq_get_phy_abilities_resp *abilities, 1600 struct i40e_asq_cmd_details *cmd_details) 1601 { 1602 struct i40e_aq_desc desc; 1603 i40e_status status; 1604 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1605 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1606 1607 if (!abilities) 1608 return I40E_ERR_PARAM; 1609 1610 do { 1611 i40e_fill_default_direct_cmd_desc(&desc, 1612 i40e_aqc_opc_get_phy_abilities); 1613 1614 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1615 if (abilities_size > I40E_AQ_LARGE_BUF) 1616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1617 1618 if (qualified_modules) 1619 desc.params.external.param0 |= 1620 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1621 1622 if (report_init) 1623 desc.params.external.param0 |= 1624 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1625 1626 status = i40e_asq_send_command(hw, &desc, abilities, 1627 abilities_size, cmd_details); 1628 1629 if (status) 1630 break; 1631 1632 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1633 status = I40E_ERR_UNKNOWN_PHY; 1634 break; 1635 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1636 usleep_range(1000, 2000); 1637 total_delay++; 1638 status = I40E_ERR_TIMEOUT; 1639 } 1640 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1641 (total_delay < max_delay)); 1642 1643 if (status) 1644 return status; 1645 1646 if (report_init) { 1647 if (hw->mac.type == I40E_MAC_XL710 && 1648 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1649 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1650 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1651 } else { 1652 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1653 hw->phy.phy_types |= 1654 ((u64)abilities->phy_type_ext << 32); 1655 } 1656 } 1657 1658 return status; 1659 } 1660 1661 /** 1662 * i40e_aq_set_phy_config 1663 * @hw: pointer to the hw struct 1664 * @config: structure with PHY configuration to be set 1665 * @cmd_details: pointer to command details structure or NULL 1666 * 1667 * Set the various PHY configuration parameters 1668 * supported on the Port.One or more of the Set PHY config parameters may be 1669 * ignored in an MFP mode as the PF may not have the privilege to set some 1670 * of the PHY Config parameters. This status will be indicated by the 1671 * command response. 1672 **/ 1673 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1674 struct i40e_aq_set_phy_config *config, 1675 struct i40e_asq_cmd_details *cmd_details) 1676 { 1677 struct i40e_aq_desc desc; 1678 struct i40e_aq_set_phy_config *cmd = 1679 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1680 enum i40e_status_code status; 1681 1682 if (!config) 1683 return I40E_ERR_PARAM; 1684 1685 i40e_fill_default_direct_cmd_desc(&desc, 1686 i40e_aqc_opc_set_phy_config); 1687 1688 *cmd = *config; 1689 1690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1691 1692 return status; 1693 } 1694 1695 /** 1696 * i40e_set_fc 1697 * @hw: pointer to the hw struct 1698 * 1699 * Set the requested flow control mode using set_phy_config. 1700 **/ 1701 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1702 bool atomic_restart) 1703 { 1704 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1705 struct i40e_aq_get_phy_abilities_resp abilities; 1706 struct i40e_aq_set_phy_config config; 1707 enum i40e_status_code status; 1708 u8 pause_mask = 0x0; 1709 1710 *aq_failures = 0x0; 1711 1712 switch (fc_mode) { 1713 case I40E_FC_FULL: 1714 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1715 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1716 break; 1717 case I40E_FC_RX_PAUSE: 1718 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1719 break; 1720 case I40E_FC_TX_PAUSE: 1721 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1722 break; 1723 default: 1724 break; 1725 } 1726 1727 /* Get the current phy config */ 1728 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1729 NULL); 1730 if (status) { 1731 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1732 return status; 1733 } 1734 1735 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1736 /* clear the old pause settings */ 1737 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1738 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1739 /* set the new abilities */ 1740 config.abilities |= pause_mask; 1741 /* If the abilities have changed, then set the new config */ 1742 if (config.abilities != abilities.abilities) { 1743 /* Auto restart link so settings take effect */ 1744 if (atomic_restart) 1745 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1746 /* Copy over all the old settings */ 1747 config.phy_type = abilities.phy_type; 1748 config.phy_type_ext = abilities.phy_type_ext; 1749 config.link_speed = abilities.link_speed; 1750 config.eee_capability = abilities.eee_capability; 1751 config.eeer = abilities.eeer_val; 1752 config.low_power_ctrl = abilities.d3_lpan; 1753 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1754 I40E_AQ_PHY_FEC_CONFIG_MASK; 1755 status = i40e_aq_set_phy_config(hw, &config, NULL); 1756 1757 if (status) 1758 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1759 } 1760 /* Update the link info */ 1761 status = i40e_update_link_info(hw); 1762 if (status) { 1763 /* Wait a little bit (on 40G cards it sometimes takes a really 1764 * long time for link to come back from the atomic reset) 1765 * and try once more 1766 */ 1767 msleep(1000); 1768 status = i40e_update_link_info(hw); 1769 } 1770 if (status) 1771 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1772 1773 return status; 1774 } 1775 1776 /** 1777 * i40e_aq_clear_pxe_mode 1778 * @hw: pointer to the hw struct 1779 * @cmd_details: pointer to command details structure or NULL 1780 * 1781 * Tell the firmware that the driver is taking over from PXE 1782 **/ 1783 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1784 struct i40e_asq_cmd_details *cmd_details) 1785 { 1786 i40e_status status; 1787 struct i40e_aq_desc desc; 1788 struct i40e_aqc_clear_pxe *cmd = 1789 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1790 1791 i40e_fill_default_direct_cmd_desc(&desc, 1792 i40e_aqc_opc_clear_pxe_mode); 1793 1794 cmd->rx_cnt = 0x2; 1795 1796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1797 1798 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1799 1800 return status; 1801 } 1802 1803 /** 1804 * i40e_aq_set_link_restart_an 1805 * @hw: pointer to the hw struct 1806 * @enable_link: if true: enable link, if false: disable link 1807 * @cmd_details: pointer to command details structure or NULL 1808 * 1809 * Sets up the link and restarts the Auto-Negotiation over the link. 1810 **/ 1811 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1812 bool enable_link, 1813 struct i40e_asq_cmd_details *cmd_details) 1814 { 1815 struct i40e_aq_desc desc; 1816 struct i40e_aqc_set_link_restart_an *cmd = 1817 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1818 i40e_status status; 1819 1820 i40e_fill_default_direct_cmd_desc(&desc, 1821 i40e_aqc_opc_set_link_restart_an); 1822 1823 cmd->command = I40E_AQ_PHY_RESTART_AN; 1824 if (enable_link) 1825 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1826 else 1827 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1828 1829 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1830 1831 return status; 1832 } 1833 1834 /** 1835 * i40e_aq_get_link_info 1836 * @hw: pointer to the hw struct 1837 * @enable_lse: enable/disable LinkStatusEvent reporting 1838 * @link: pointer to link status structure - optional 1839 * @cmd_details: pointer to command details structure or NULL 1840 * 1841 * Returns the link status of the adapter. 1842 **/ 1843 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1844 bool enable_lse, struct i40e_link_status *link, 1845 struct i40e_asq_cmd_details *cmd_details) 1846 { 1847 struct i40e_aq_desc desc; 1848 struct i40e_aqc_get_link_status *resp = 1849 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1850 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1851 i40e_status status; 1852 bool tx_pause, rx_pause; 1853 u16 command_flags; 1854 1855 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1856 1857 if (enable_lse) 1858 command_flags = I40E_AQ_LSE_ENABLE; 1859 else 1860 command_flags = I40E_AQ_LSE_DISABLE; 1861 resp->command_flags = cpu_to_le16(command_flags); 1862 1863 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1864 1865 if (status) 1866 goto aq_get_link_info_exit; 1867 1868 /* save off old link status information */ 1869 hw->phy.link_info_old = *hw_link_info; 1870 1871 /* update link status */ 1872 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1873 hw->phy.media_type = i40e_get_media_type(hw); 1874 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1875 hw_link_info->link_info = resp->link_info; 1876 hw_link_info->an_info = resp->an_info; 1877 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1878 I40E_AQ_CONFIG_FEC_RS_ENA); 1879 hw_link_info->ext_info = resp->ext_info; 1880 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1881 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1882 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1883 1884 /* update fc info */ 1885 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1886 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1887 if (tx_pause & rx_pause) 1888 hw->fc.current_mode = I40E_FC_FULL; 1889 else if (tx_pause) 1890 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1891 else if (rx_pause) 1892 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1893 else 1894 hw->fc.current_mode = I40E_FC_NONE; 1895 1896 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1897 hw_link_info->crc_enable = true; 1898 else 1899 hw_link_info->crc_enable = false; 1900 1901 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1902 hw_link_info->lse_enable = true; 1903 else 1904 hw_link_info->lse_enable = false; 1905 1906 if ((hw->mac.type == I40E_MAC_XL710) && 1907 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1908 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1909 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1910 1911 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1912 hw->aq.api_min_ver >= 7) { 1913 __le32 tmp; 1914 1915 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1916 hw->phy.phy_types = le32_to_cpu(tmp); 1917 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1918 } 1919 1920 /* save link status information */ 1921 if (link) 1922 *link = *hw_link_info; 1923 1924 /* flag cleared so helper functions don't call AQ again */ 1925 hw->phy.get_link_info = false; 1926 1927 aq_get_link_info_exit: 1928 return status; 1929 } 1930 1931 /** 1932 * i40e_aq_set_phy_int_mask 1933 * @hw: pointer to the hw struct 1934 * @mask: interrupt mask to be set 1935 * @cmd_details: pointer to command details structure or NULL 1936 * 1937 * Set link interrupt mask. 1938 **/ 1939 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1940 u16 mask, 1941 struct i40e_asq_cmd_details *cmd_details) 1942 { 1943 struct i40e_aq_desc desc; 1944 struct i40e_aqc_set_phy_int_mask *cmd = 1945 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1946 i40e_status status; 1947 1948 i40e_fill_default_direct_cmd_desc(&desc, 1949 i40e_aqc_opc_set_phy_int_mask); 1950 1951 cmd->event_mask = cpu_to_le16(mask); 1952 1953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1954 1955 return status; 1956 } 1957 1958 /** 1959 * i40e_aq_set_phy_debug 1960 * @hw: pointer to the hw struct 1961 * @cmd_flags: debug command flags 1962 * @cmd_details: pointer to command details structure or NULL 1963 * 1964 * Reset the external PHY. 1965 **/ 1966 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1967 struct i40e_asq_cmd_details *cmd_details) 1968 { 1969 struct i40e_aq_desc desc; 1970 struct i40e_aqc_set_phy_debug *cmd = 1971 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1972 i40e_status status; 1973 1974 i40e_fill_default_direct_cmd_desc(&desc, 1975 i40e_aqc_opc_set_phy_debug); 1976 1977 cmd->command_flags = cmd_flags; 1978 1979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1980 1981 return status; 1982 } 1983 1984 /** 1985 * i40e_aq_add_vsi 1986 * @hw: pointer to the hw struct 1987 * @vsi_ctx: pointer to a vsi context struct 1988 * @cmd_details: pointer to command details structure or NULL 1989 * 1990 * Add a VSI context to the hardware. 1991 **/ 1992 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1993 struct i40e_vsi_context *vsi_ctx, 1994 struct i40e_asq_cmd_details *cmd_details) 1995 { 1996 struct i40e_aq_desc desc; 1997 struct i40e_aqc_add_get_update_vsi *cmd = 1998 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1999 struct i40e_aqc_add_get_update_vsi_completion *resp = 2000 (struct i40e_aqc_add_get_update_vsi_completion *) 2001 &desc.params.raw; 2002 i40e_status status; 2003 2004 i40e_fill_default_direct_cmd_desc(&desc, 2005 i40e_aqc_opc_add_vsi); 2006 2007 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 2008 cmd->connection_type = vsi_ctx->connection_type; 2009 cmd->vf_id = vsi_ctx->vf_num; 2010 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 2011 2012 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2013 2014 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2015 sizeof(vsi_ctx->info), cmd_details); 2016 2017 if (status) 2018 goto aq_add_vsi_exit; 2019 2020 vsi_ctx->seid = le16_to_cpu(resp->seid); 2021 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2022 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2023 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2024 2025 aq_add_vsi_exit: 2026 return status; 2027 } 2028 2029 /** 2030 * i40e_aq_set_default_vsi 2031 * @hw: pointer to the hw struct 2032 * @seid: vsi number 2033 * @cmd_details: pointer to command details structure or NULL 2034 **/ 2035 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2036 u16 seid, 2037 struct i40e_asq_cmd_details *cmd_details) 2038 { 2039 struct i40e_aq_desc desc; 2040 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2041 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2042 &desc.params.raw; 2043 i40e_status status; 2044 2045 i40e_fill_default_direct_cmd_desc(&desc, 2046 i40e_aqc_opc_set_vsi_promiscuous_modes); 2047 2048 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2049 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2050 cmd->seid = cpu_to_le16(seid); 2051 2052 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2053 2054 return status; 2055 } 2056 2057 /** 2058 * i40e_aq_clear_default_vsi 2059 * @hw: pointer to the hw struct 2060 * @seid: vsi number 2061 * @cmd_details: pointer to command details structure or NULL 2062 **/ 2063 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2064 u16 seid, 2065 struct i40e_asq_cmd_details *cmd_details) 2066 { 2067 struct i40e_aq_desc desc; 2068 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2069 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2070 &desc.params.raw; 2071 i40e_status status; 2072 2073 i40e_fill_default_direct_cmd_desc(&desc, 2074 i40e_aqc_opc_set_vsi_promiscuous_modes); 2075 2076 cmd->promiscuous_flags = cpu_to_le16(0); 2077 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2078 cmd->seid = cpu_to_le16(seid); 2079 2080 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2081 2082 return status; 2083 } 2084 2085 /** 2086 * i40e_aq_set_vsi_unicast_promiscuous 2087 * @hw: pointer to the hw struct 2088 * @seid: vsi number 2089 * @set: set unicast promiscuous enable/disable 2090 * @cmd_details: pointer to command details structure or NULL 2091 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2092 **/ 2093 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2094 u16 seid, bool set, 2095 struct i40e_asq_cmd_details *cmd_details, 2096 bool rx_only_promisc) 2097 { 2098 struct i40e_aq_desc desc; 2099 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2100 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2101 i40e_status status; 2102 u16 flags = 0; 2103 2104 i40e_fill_default_direct_cmd_desc(&desc, 2105 i40e_aqc_opc_set_vsi_promiscuous_modes); 2106 2107 if (set) { 2108 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2109 if (rx_only_promisc && 2110 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2111 (hw->aq.api_maj_ver > 1))) 2112 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2113 } 2114 2115 cmd->promiscuous_flags = cpu_to_le16(flags); 2116 2117 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2118 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2119 (hw->aq.api_maj_ver > 1)) 2120 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2121 2122 cmd->seid = cpu_to_le16(seid); 2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2124 2125 return status; 2126 } 2127 2128 /** 2129 * i40e_aq_set_vsi_multicast_promiscuous 2130 * @hw: pointer to the hw struct 2131 * @seid: vsi number 2132 * @set: set multicast promiscuous enable/disable 2133 * @cmd_details: pointer to command details structure or NULL 2134 **/ 2135 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2136 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2137 { 2138 struct i40e_aq_desc desc; 2139 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2140 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2141 i40e_status status; 2142 u16 flags = 0; 2143 2144 i40e_fill_default_direct_cmd_desc(&desc, 2145 i40e_aqc_opc_set_vsi_promiscuous_modes); 2146 2147 if (set) 2148 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2149 2150 cmd->promiscuous_flags = cpu_to_le16(flags); 2151 2152 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2153 2154 cmd->seid = cpu_to_le16(seid); 2155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2156 2157 return status; 2158 } 2159 2160 /** 2161 * i40e_aq_set_vsi_mc_promisc_on_vlan 2162 * @hw: pointer to the hw struct 2163 * @seid: vsi number 2164 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2165 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2166 * @cmd_details: pointer to command details structure or NULL 2167 **/ 2168 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2169 u16 seid, bool enable, 2170 u16 vid, 2171 struct i40e_asq_cmd_details *cmd_details) 2172 { 2173 struct i40e_aq_desc desc; 2174 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2175 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2176 enum i40e_status_code status; 2177 u16 flags = 0; 2178 2179 i40e_fill_default_direct_cmd_desc(&desc, 2180 i40e_aqc_opc_set_vsi_promiscuous_modes); 2181 2182 if (enable) 2183 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2184 2185 cmd->promiscuous_flags = cpu_to_le16(flags); 2186 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2187 cmd->seid = cpu_to_le16(seid); 2188 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2189 2190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2191 2192 return status; 2193 } 2194 2195 /** 2196 * i40e_aq_set_vsi_uc_promisc_on_vlan 2197 * @hw: pointer to the hw struct 2198 * @seid: vsi number 2199 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2200 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2201 * @cmd_details: pointer to command details structure or NULL 2202 **/ 2203 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2204 u16 seid, bool enable, 2205 u16 vid, 2206 struct i40e_asq_cmd_details *cmd_details) 2207 { 2208 struct i40e_aq_desc desc; 2209 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2210 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2211 enum i40e_status_code status; 2212 u16 flags = 0; 2213 2214 i40e_fill_default_direct_cmd_desc(&desc, 2215 i40e_aqc_opc_set_vsi_promiscuous_modes); 2216 2217 if (enable) 2218 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2219 2220 cmd->promiscuous_flags = cpu_to_le16(flags); 2221 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2222 cmd->seid = cpu_to_le16(seid); 2223 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2224 2225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2226 2227 return status; 2228 } 2229 2230 /** 2231 * i40e_aq_set_vsi_bc_promisc_on_vlan 2232 * @hw: pointer to the hw struct 2233 * @seid: vsi number 2234 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2235 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2236 * @cmd_details: pointer to command details structure or NULL 2237 **/ 2238 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2239 u16 seid, bool enable, u16 vid, 2240 struct i40e_asq_cmd_details *cmd_details) 2241 { 2242 struct i40e_aq_desc desc; 2243 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2244 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2245 i40e_status status; 2246 u16 flags = 0; 2247 2248 i40e_fill_default_direct_cmd_desc(&desc, 2249 i40e_aqc_opc_set_vsi_promiscuous_modes); 2250 2251 if (enable) 2252 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2253 2254 cmd->promiscuous_flags = cpu_to_le16(flags); 2255 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2256 cmd->seid = cpu_to_le16(seid); 2257 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2258 2259 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2260 2261 return status; 2262 } 2263 2264 /** 2265 * i40e_aq_set_vsi_broadcast 2266 * @hw: pointer to the hw struct 2267 * @seid: vsi number 2268 * @set_filter: true to set filter, false to clear filter 2269 * @cmd_details: pointer to command details structure or NULL 2270 * 2271 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2272 **/ 2273 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2274 u16 seid, bool set_filter, 2275 struct i40e_asq_cmd_details *cmd_details) 2276 { 2277 struct i40e_aq_desc desc; 2278 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2279 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2280 i40e_status status; 2281 2282 i40e_fill_default_direct_cmd_desc(&desc, 2283 i40e_aqc_opc_set_vsi_promiscuous_modes); 2284 2285 if (set_filter) 2286 cmd->promiscuous_flags 2287 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2288 else 2289 cmd->promiscuous_flags 2290 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2291 2292 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2293 cmd->seid = cpu_to_le16(seid); 2294 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2295 2296 return status; 2297 } 2298 2299 /** 2300 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2301 * @hw: pointer to the hw struct 2302 * @seid: vsi number 2303 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2304 * @cmd_details: pointer to command details structure or NULL 2305 **/ 2306 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2307 u16 seid, bool enable, 2308 struct i40e_asq_cmd_details *cmd_details) 2309 { 2310 struct i40e_aq_desc desc; 2311 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2312 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2313 i40e_status status; 2314 u16 flags = 0; 2315 2316 i40e_fill_default_direct_cmd_desc(&desc, 2317 i40e_aqc_opc_set_vsi_promiscuous_modes); 2318 if (enable) 2319 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2320 2321 cmd->promiscuous_flags = cpu_to_le16(flags); 2322 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2323 cmd->seid = cpu_to_le16(seid); 2324 2325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2326 2327 return status; 2328 } 2329 2330 /** 2331 * i40e_get_vsi_params - get VSI configuration info 2332 * @hw: pointer to the hw struct 2333 * @vsi_ctx: pointer to a vsi context struct 2334 * @cmd_details: pointer to command details structure or NULL 2335 **/ 2336 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2337 struct i40e_vsi_context *vsi_ctx, 2338 struct i40e_asq_cmd_details *cmd_details) 2339 { 2340 struct i40e_aq_desc desc; 2341 struct i40e_aqc_add_get_update_vsi *cmd = 2342 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2343 struct i40e_aqc_add_get_update_vsi_completion *resp = 2344 (struct i40e_aqc_add_get_update_vsi_completion *) 2345 &desc.params.raw; 2346 i40e_status status; 2347 2348 i40e_fill_default_direct_cmd_desc(&desc, 2349 i40e_aqc_opc_get_vsi_parameters); 2350 2351 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2352 2353 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2354 2355 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2356 sizeof(vsi_ctx->info), NULL); 2357 2358 if (status) 2359 goto aq_get_vsi_params_exit; 2360 2361 vsi_ctx->seid = le16_to_cpu(resp->seid); 2362 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2363 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2364 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2365 2366 aq_get_vsi_params_exit: 2367 return status; 2368 } 2369 2370 /** 2371 * i40e_aq_update_vsi_params 2372 * @hw: pointer to the hw struct 2373 * @vsi_ctx: pointer to a vsi context struct 2374 * @cmd_details: pointer to command details structure or NULL 2375 * 2376 * Update a VSI context. 2377 **/ 2378 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2379 struct i40e_vsi_context *vsi_ctx, 2380 struct i40e_asq_cmd_details *cmd_details) 2381 { 2382 struct i40e_aq_desc desc; 2383 struct i40e_aqc_add_get_update_vsi *cmd = 2384 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2385 struct i40e_aqc_add_get_update_vsi_completion *resp = 2386 (struct i40e_aqc_add_get_update_vsi_completion *) 2387 &desc.params.raw; 2388 i40e_status status; 2389 2390 i40e_fill_default_direct_cmd_desc(&desc, 2391 i40e_aqc_opc_update_vsi_parameters); 2392 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2393 2394 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2395 2396 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2397 sizeof(vsi_ctx->info), cmd_details); 2398 2399 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2400 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2401 2402 return status; 2403 } 2404 2405 /** 2406 * i40e_aq_get_switch_config 2407 * @hw: pointer to the hardware structure 2408 * @buf: pointer to the result buffer 2409 * @buf_size: length of input buffer 2410 * @start_seid: seid to start for the report, 0 == beginning 2411 * @cmd_details: pointer to command details structure or NULL 2412 * 2413 * Fill the buf with switch configuration returned from AdminQ command 2414 **/ 2415 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2416 struct i40e_aqc_get_switch_config_resp *buf, 2417 u16 buf_size, u16 *start_seid, 2418 struct i40e_asq_cmd_details *cmd_details) 2419 { 2420 struct i40e_aq_desc desc; 2421 struct i40e_aqc_switch_seid *scfg = 2422 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2423 i40e_status status; 2424 2425 i40e_fill_default_direct_cmd_desc(&desc, 2426 i40e_aqc_opc_get_switch_config); 2427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2428 if (buf_size > I40E_AQ_LARGE_BUF) 2429 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2430 scfg->seid = cpu_to_le16(*start_seid); 2431 2432 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2433 *start_seid = le16_to_cpu(scfg->seid); 2434 2435 return status; 2436 } 2437 2438 /** 2439 * i40e_aq_set_switch_config 2440 * @hw: pointer to the hardware structure 2441 * @flags: bit flag values to set 2442 * @mode: cloud filter mode 2443 * @valid_flags: which bit flags to set 2444 * @mode: cloud filter mode 2445 * @cmd_details: pointer to command details structure or NULL 2446 * 2447 * Set switch configuration bits 2448 **/ 2449 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2450 u16 flags, 2451 u16 valid_flags, u8 mode, 2452 struct i40e_asq_cmd_details *cmd_details) 2453 { 2454 struct i40e_aq_desc desc; 2455 struct i40e_aqc_set_switch_config *scfg = 2456 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2457 enum i40e_status_code status; 2458 2459 i40e_fill_default_direct_cmd_desc(&desc, 2460 i40e_aqc_opc_set_switch_config); 2461 scfg->flags = cpu_to_le16(flags); 2462 scfg->valid_flags = cpu_to_le16(valid_flags); 2463 scfg->mode = mode; 2464 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2465 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2466 scfg->first_tag = cpu_to_le16(hw->first_tag); 2467 scfg->second_tag = cpu_to_le16(hw->second_tag); 2468 } 2469 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2470 2471 return status; 2472 } 2473 2474 /** 2475 * i40e_aq_get_firmware_version 2476 * @hw: pointer to the hw struct 2477 * @fw_major_version: firmware major version 2478 * @fw_minor_version: firmware minor version 2479 * @fw_build: firmware build number 2480 * @api_major_version: major queue version 2481 * @api_minor_version: minor queue version 2482 * @cmd_details: pointer to command details structure or NULL 2483 * 2484 * Get the firmware version from the admin queue commands 2485 **/ 2486 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2487 u16 *fw_major_version, u16 *fw_minor_version, 2488 u32 *fw_build, 2489 u16 *api_major_version, u16 *api_minor_version, 2490 struct i40e_asq_cmd_details *cmd_details) 2491 { 2492 struct i40e_aq_desc desc; 2493 struct i40e_aqc_get_version *resp = 2494 (struct i40e_aqc_get_version *)&desc.params.raw; 2495 i40e_status status; 2496 2497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2498 2499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2500 2501 if (!status) { 2502 if (fw_major_version) 2503 *fw_major_version = le16_to_cpu(resp->fw_major); 2504 if (fw_minor_version) 2505 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2506 if (fw_build) 2507 *fw_build = le32_to_cpu(resp->fw_build); 2508 if (api_major_version) 2509 *api_major_version = le16_to_cpu(resp->api_major); 2510 if (api_minor_version) 2511 *api_minor_version = le16_to_cpu(resp->api_minor); 2512 } 2513 2514 return status; 2515 } 2516 2517 /** 2518 * i40e_aq_send_driver_version 2519 * @hw: pointer to the hw struct 2520 * @dv: driver's major, minor version 2521 * @cmd_details: pointer to command details structure or NULL 2522 * 2523 * Send the driver version to the firmware 2524 **/ 2525 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2526 struct i40e_driver_version *dv, 2527 struct i40e_asq_cmd_details *cmd_details) 2528 { 2529 struct i40e_aq_desc desc; 2530 struct i40e_aqc_driver_version *cmd = 2531 (struct i40e_aqc_driver_version *)&desc.params.raw; 2532 i40e_status status; 2533 u16 len; 2534 2535 if (dv == NULL) 2536 return I40E_ERR_PARAM; 2537 2538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2539 2540 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2541 cmd->driver_major_ver = dv->major_version; 2542 cmd->driver_minor_ver = dv->minor_version; 2543 cmd->driver_build_ver = dv->build_version; 2544 cmd->driver_subbuild_ver = dv->subbuild_version; 2545 2546 len = 0; 2547 while (len < sizeof(dv->driver_string) && 2548 (dv->driver_string[len] < 0x80) && 2549 dv->driver_string[len]) 2550 len++; 2551 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2552 len, cmd_details); 2553 2554 return status; 2555 } 2556 2557 /** 2558 * i40e_get_link_status - get status of the HW network link 2559 * @hw: pointer to the hw struct 2560 * @link_up: pointer to bool (true/false = linkup/linkdown) 2561 * 2562 * Variable link_up true if link is up, false if link is down. 2563 * The variable link_up is invalid if returned value of status != 0 2564 * 2565 * Side effect: LinkStatusEvent reporting becomes enabled 2566 **/ 2567 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2568 { 2569 i40e_status status = 0; 2570 2571 if (hw->phy.get_link_info) { 2572 status = i40e_update_link_info(hw); 2573 2574 if (status) 2575 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2576 status); 2577 } 2578 2579 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2580 2581 return status; 2582 } 2583 2584 /** 2585 * i40e_updatelink_status - update status of the HW network link 2586 * @hw: pointer to the hw struct 2587 **/ 2588 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2589 { 2590 struct i40e_aq_get_phy_abilities_resp abilities; 2591 i40e_status status = 0; 2592 2593 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2594 if (status) 2595 return status; 2596 2597 /* extra checking needed to ensure link info to user is timely */ 2598 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2599 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2600 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2601 status = i40e_aq_get_phy_capabilities(hw, false, false, 2602 &abilities, NULL); 2603 if (status) 2604 return status; 2605 2606 hw->phy.link_info.req_fec_info = 2607 abilities.fec_cfg_curr_mod_ext_info & 2608 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2609 2610 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2611 sizeof(hw->phy.link_info.module_type)); 2612 } 2613 2614 return status; 2615 } 2616 2617 /** 2618 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2619 * @hw: pointer to the hw struct 2620 * @uplink_seid: the MAC or other gizmo SEID 2621 * @downlink_seid: the VSI SEID 2622 * @enabled_tc: bitmap of TCs to be enabled 2623 * @default_port: true for default port VSI, false for control port 2624 * @veb_seid: pointer to where to put the resulting VEB SEID 2625 * @enable_stats: true to turn on VEB stats 2626 * @cmd_details: pointer to command details structure or NULL 2627 * 2628 * This asks the FW to add a VEB between the uplink and downlink 2629 * elements. If the uplink SEID is 0, this will be a floating VEB. 2630 **/ 2631 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2632 u16 downlink_seid, u8 enabled_tc, 2633 bool default_port, u16 *veb_seid, 2634 bool enable_stats, 2635 struct i40e_asq_cmd_details *cmd_details) 2636 { 2637 struct i40e_aq_desc desc; 2638 struct i40e_aqc_add_veb *cmd = 2639 (struct i40e_aqc_add_veb *)&desc.params.raw; 2640 struct i40e_aqc_add_veb_completion *resp = 2641 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2642 i40e_status status; 2643 u16 veb_flags = 0; 2644 2645 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2646 if (!!uplink_seid != !!downlink_seid) 2647 return I40E_ERR_PARAM; 2648 2649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2650 2651 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2652 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2653 cmd->enable_tcs = enabled_tc; 2654 if (!uplink_seid) 2655 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2656 if (default_port) 2657 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2658 else 2659 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2660 2661 /* reverse logic here: set the bitflag to disable the stats */ 2662 if (!enable_stats) 2663 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2664 2665 cmd->veb_flags = cpu_to_le16(veb_flags); 2666 2667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2668 2669 if (!status && veb_seid) 2670 *veb_seid = le16_to_cpu(resp->veb_seid); 2671 2672 return status; 2673 } 2674 2675 /** 2676 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2677 * @hw: pointer to the hw struct 2678 * @veb_seid: the SEID of the VEB to query 2679 * @switch_id: the uplink switch id 2680 * @floating: set to true if the VEB is floating 2681 * @statistic_index: index of the stats counter block for this VEB 2682 * @vebs_used: number of VEB's used by function 2683 * @vebs_free: total VEB's not reserved by any function 2684 * @cmd_details: pointer to command details structure or NULL 2685 * 2686 * This retrieves the parameters for a particular VEB, specified by 2687 * uplink_seid, and returns them to the caller. 2688 **/ 2689 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2690 u16 veb_seid, u16 *switch_id, 2691 bool *floating, u16 *statistic_index, 2692 u16 *vebs_used, u16 *vebs_free, 2693 struct i40e_asq_cmd_details *cmd_details) 2694 { 2695 struct i40e_aq_desc desc; 2696 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2697 (struct i40e_aqc_get_veb_parameters_completion *) 2698 &desc.params.raw; 2699 i40e_status status; 2700 2701 if (veb_seid == 0) 2702 return I40E_ERR_PARAM; 2703 2704 i40e_fill_default_direct_cmd_desc(&desc, 2705 i40e_aqc_opc_get_veb_parameters); 2706 cmd_resp->seid = cpu_to_le16(veb_seid); 2707 2708 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2709 if (status) 2710 goto get_veb_exit; 2711 2712 if (switch_id) 2713 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2714 if (statistic_index) 2715 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2716 if (vebs_used) 2717 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2718 if (vebs_free) 2719 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2720 if (floating) { 2721 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2722 2723 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2724 *floating = true; 2725 else 2726 *floating = false; 2727 } 2728 2729 get_veb_exit: 2730 return status; 2731 } 2732 2733 /** 2734 * i40e_aq_add_macvlan 2735 * @hw: pointer to the hw struct 2736 * @seid: VSI for the mac address 2737 * @mv_list: list of macvlans to be added 2738 * @count: length of the list 2739 * @cmd_details: pointer to command details structure or NULL 2740 * 2741 * Add MAC/VLAN addresses to the HW filtering 2742 **/ 2743 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2744 struct i40e_aqc_add_macvlan_element_data *mv_list, 2745 u16 count, struct i40e_asq_cmd_details *cmd_details) 2746 { 2747 struct i40e_aq_desc desc; 2748 struct i40e_aqc_macvlan *cmd = 2749 (struct i40e_aqc_macvlan *)&desc.params.raw; 2750 i40e_status status; 2751 u16 buf_size; 2752 int i; 2753 2754 if (count == 0 || !mv_list || !hw) 2755 return I40E_ERR_PARAM; 2756 2757 buf_size = count * sizeof(*mv_list); 2758 2759 /* prep the rest of the request */ 2760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2761 cmd->num_addresses = cpu_to_le16(count); 2762 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2763 cmd->seid[1] = 0; 2764 cmd->seid[2] = 0; 2765 2766 for (i = 0; i < count; i++) 2767 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2768 mv_list[i].flags |= 2769 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2770 2771 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2772 if (buf_size > I40E_AQ_LARGE_BUF) 2773 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2774 2775 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2776 cmd_details); 2777 2778 return status; 2779 } 2780 2781 /** 2782 * i40e_aq_remove_macvlan 2783 * @hw: pointer to the hw struct 2784 * @seid: VSI for the mac address 2785 * @mv_list: list of macvlans to be removed 2786 * @count: length of the list 2787 * @cmd_details: pointer to command details structure or NULL 2788 * 2789 * Remove MAC/VLAN addresses from the HW filtering 2790 **/ 2791 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2792 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2793 u16 count, struct i40e_asq_cmd_details *cmd_details) 2794 { 2795 struct i40e_aq_desc desc; 2796 struct i40e_aqc_macvlan *cmd = 2797 (struct i40e_aqc_macvlan *)&desc.params.raw; 2798 i40e_status status; 2799 u16 buf_size; 2800 2801 if (count == 0 || !mv_list || !hw) 2802 return I40E_ERR_PARAM; 2803 2804 buf_size = count * sizeof(*mv_list); 2805 2806 /* prep the rest of the request */ 2807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2808 cmd->num_addresses = cpu_to_le16(count); 2809 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2810 cmd->seid[1] = 0; 2811 cmd->seid[2] = 0; 2812 2813 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2814 if (buf_size > I40E_AQ_LARGE_BUF) 2815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2816 2817 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2818 cmd_details); 2819 2820 return status; 2821 } 2822 2823 /** 2824 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2825 * @hw: pointer to the hw struct 2826 * @opcode: AQ opcode for add or delete mirror rule 2827 * @sw_seid: Switch SEID (to which rule refers) 2828 * @rule_type: Rule Type (ingress/egress/VLAN) 2829 * @id: Destination VSI SEID or Rule ID 2830 * @count: length of the list 2831 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2832 * @cmd_details: pointer to command details structure or NULL 2833 * @rule_id: Rule ID returned from FW 2834 * @rule_used: Number of rules used in internal switch 2835 * @rule_free: Number of rules free in internal switch 2836 * 2837 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2838 * VEBs/VEPA elements only 2839 **/ 2840 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2841 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2842 u16 count, __le16 *mr_list, 2843 struct i40e_asq_cmd_details *cmd_details, 2844 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2845 { 2846 struct i40e_aq_desc desc; 2847 struct i40e_aqc_add_delete_mirror_rule *cmd = 2848 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2849 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2850 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2851 i40e_status status; 2852 u16 buf_size; 2853 2854 buf_size = count * sizeof(*mr_list); 2855 2856 /* prep the rest of the request */ 2857 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2858 cmd->seid = cpu_to_le16(sw_seid); 2859 cmd->rule_type = cpu_to_le16(rule_type & 2860 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2861 cmd->num_entries = cpu_to_le16(count); 2862 /* Dest VSI for add, rule_id for delete */ 2863 cmd->destination = cpu_to_le16(id); 2864 if (mr_list) { 2865 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2866 I40E_AQ_FLAG_RD)); 2867 if (buf_size > I40E_AQ_LARGE_BUF) 2868 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2869 } 2870 2871 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2872 cmd_details); 2873 if (!status || 2874 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2875 if (rule_id) 2876 *rule_id = le16_to_cpu(resp->rule_id); 2877 if (rules_used) 2878 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2879 if (rules_free) 2880 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2881 } 2882 return status; 2883 } 2884 2885 /** 2886 * i40e_aq_add_mirrorrule - add a mirror rule 2887 * @hw: pointer to the hw struct 2888 * @sw_seid: Switch SEID (to which rule refers) 2889 * @rule_type: Rule Type (ingress/egress/VLAN) 2890 * @dest_vsi: SEID of VSI to which packets will be mirrored 2891 * @count: length of the list 2892 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2893 * @cmd_details: pointer to command details structure or NULL 2894 * @rule_id: Rule ID returned from FW 2895 * @rule_used: Number of rules used in internal switch 2896 * @rule_free: Number of rules free in internal switch 2897 * 2898 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2899 **/ 2900 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2901 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2902 struct i40e_asq_cmd_details *cmd_details, 2903 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2904 { 2905 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2906 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2907 if (count == 0 || !mr_list) 2908 return I40E_ERR_PARAM; 2909 } 2910 2911 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2912 rule_type, dest_vsi, count, mr_list, 2913 cmd_details, rule_id, rules_used, rules_free); 2914 } 2915 2916 /** 2917 * i40e_aq_delete_mirrorrule - delete a mirror rule 2918 * @hw: pointer to the hw struct 2919 * @sw_seid: Switch SEID (to which rule refers) 2920 * @rule_type: Rule Type (ingress/egress/VLAN) 2921 * @count: length of the list 2922 * @rule_id: Rule ID that is returned in the receive desc as part of 2923 * add_mirrorrule. 2924 * @mr_list: list of mirrored VLAN IDs to be removed 2925 * @cmd_details: pointer to command details structure or NULL 2926 * @rule_used: Number of rules used in internal switch 2927 * @rule_free: Number of rules free in internal switch 2928 * 2929 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2930 **/ 2931 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2932 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2933 struct i40e_asq_cmd_details *cmd_details, 2934 u16 *rules_used, u16 *rules_free) 2935 { 2936 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2937 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2938 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2939 * mirroring. For other rule_type, count and rule_type should 2940 * not matter. 2941 */ 2942 if (count == 0 || !mr_list) 2943 return I40E_ERR_PARAM; 2944 } 2945 2946 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2947 rule_type, rule_id, count, mr_list, 2948 cmd_details, NULL, rules_used, rules_free); 2949 } 2950 2951 /** 2952 * i40e_aq_send_msg_to_vf 2953 * @hw: pointer to the hardware structure 2954 * @vfid: VF id to send msg 2955 * @v_opcode: opcodes for VF-PF communication 2956 * @v_retval: return error code 2957 * @msg: pointer to the msg buffer 2958 * @msglen: msg length 2959 * @cmd_details: pointer to command details 2960 * 2961 * send msg to vf 2962 **/ 2963 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2964 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2965 struct i40e_asq_cmd_details *cmd_details) 2966 { 2967 struct i40e_aq_desc desc; 2968 struct i40e_aqc_pf_vf_message *cmd = 2969 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2970 i40e_status status; 2971 2972 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2973 cmd->id = cpu_to_le32(vfid); 2974 desc.cookie_high = cpu_to_le32(v_opcode); 2975 desc.cookie_low = cpu_to_le32(v_retval); 2976 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2977 if (msglen) { 2978 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2979 I40E_AQ_FLAG_RD)); 2980 if (msglen > I40E_AQ_LARGE_BUF) 2981 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2982 desc.datalen = cpu_to_le16(msglen); 2983 } 2984 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2985 2986 return status; 2987 } 2988 2989 /** 2990 * i40e_aq_debug_read_register 2991 * @hw: pointer to the hw struct 2992 * @reg_addr: register address 2993 * @reg_val: register value 2994 * @cmd_details: pointer to command details structure or NULL 2995 * 2996 * Read the register using the admin queue commands 2997 **/ 2998 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2999 u32 reg_addr, u64 *reg_val, 3000 struct i40e_asq_cmd_details *cmd_details) 3001 { 3002 struct i40e_aq_desc desc; 3003 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3004 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3005 i40e_status status; 3006 3007 if (reg_val == NULL) 3008 return I40E_ERR_PARAM; 3009 3010 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3011 3012 cmd_resp->address = cpu_to_le32(reg_addr); 3013 3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3015 3016 if (!status) { 3017 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 3018 (u64)le32_to_cpu(cmd_resp->value_low); 3019 } 3020 3021 return status; 3022 } 3023 3024 /** 3025 * i40e_aq_debug_write_register 3026 * @hw: pointer to the hw struct 3027 * @reg_addr: register address 3028 * @reg_val: register value 3029 * @cmd_details: pointer to command details structure or NULL 3030 * 3031 * Write to a register using the admin queue commands 3032 **/ 3033 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 3034 u32 reg_addr, u64 reg_val, 3035 struct i40e_asq_cmd_details *cmd_details) 3036 { 3037 struct i40e_aq_desc desc; 3038 struct i40e_aqc_debug_reg_read_write *cmd = 3039 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3040 i40e_status status; 3041 3042 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3043 3044 cmd->address = cpu_to_le32(reg_addr); 3045 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3046 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3047 3048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3049 3050 return status; 3051 } 3052 3053 /** 3054 * i40e_aq_request_resource 3055 * @hw: pointer to the hw struct 3056 * @resource: resource id 3057 * @access: access type 3058 * @sdp_number: resource number 3059 * @timeout: the maximum time in ms that the driver may hold the resource 3060 * @cmd_details: pointer to command details structure or NULL 3061 * 3062 * requests common resource using the admin queue commands 3063 **/ 3064 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3065 enum i40e_aq_resources_ids resource, 3066 enum i40e_aq_resource_access_type access, 3067 u8 sdp_number, u64 *timeout, 3068 struct i40e_asq_cmd_details *cmd_details) 3069 { 3070 struct i40e_aq_desc desc; 3071 struct i40e_aqc_request_resource *cmd_resp = 3072 (struct i40e_aqc_request_resource *)&desc.params.raw; 3073 i40e_status status; 3074 3075 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3076 3077 cmd_resp->resource_id = cpu_to_le16(resource); 3078 cmd_resp->access_type = cpu_to_le16(access); 3079 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3080 3081 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3082 /* The completion specifies the maximum time in ms that the driver 3083 * may hold the resource in the Timeout field. 3084 * If the resource is held by someone else, the command completes with 3085 * busy return value and the timeout field indicates the maximum time 3086 * the current owner of the resource has to free it. 3087 */ 3088 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3089 *timeout = le32_to_cpu(cmd_resp->timeout); 3090 3091 return status; 3092 } 3093 3094 /** 3095 * i40e_aq_release_resource 3096 * @hw: pointer to the hw struct 3097 * @resource: resource id 3098 * @sdp_number: resource number 3099 * @cmd_details: pointer to command details structure or NULL 3100 * 3101 * release common resource using the admin queue commands 3102 **/ 3103 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3104 enum i40e_aq_resources_ids resource, 3105 u8 sdp_number, 3106 struct i40e_asq_cmd_details *cmd_details) 3107 { 3108 struct i40e_aq_desc desc; 3109 struct i40e_aqc_request_resource *cmd = 3110 (struct i40e_aqc_request_resource *)&desc.params.raw; 3111 i40e_status status; 3112 3113 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3114 3115 cmd->resource_id = cpu_to_le16(resource); 3116 cmd->resource_number = cpu_to_le32(sdp_number); 3117 3118 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3119 3120 return status; 3121 } 3122 3123 /** 3124 * i40e_aq_read_nvm 3125 * @hw: pointer to the hw struct 3126 * @module_pointer: module pointer location in words from the NVM beginning 3127 * @offset: byte offset from the module beginning 3128 * @length: length of the section to be read (in bytes from the offset) 3129 * @data: command buffer (size [bytes] = length) 3130 * @last_command: tells if this is the last command in a series 3131 * @cmd_details: pointer to command details structure or NULL 3132 * 3133 * Read the NVM using the admin queue commands 3134 **/ 3135 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3136 u32 offset, u16 length, void *data, 3137 bool last_command, 3138 struct i40e_asq_cmd_details *cmd_details) 3139 { 3140 struct i40e_aq_desc desc; 3141 struct i40e_aqc_nvm_update *cmd = 3142 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3143 i40e_status status; 3144 3145 /* In offset the highest byte must be zeroed. */ 3146 if (offset & 0xFF000000) { 3147 status = I40E_ERR_PARAM; 3148 goto i40e_aq_read_nvm_exit; 3149 } 3150 3151 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3152 3153 /* If this is the last command in a series, set the proper flag. */ 3154 if (last_command) 3155 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3156 cmd->module_pointer = module_pointer; 3157 cmd->offset = cpu_to_le32(offset); 3158 cmd->length = cpu_to_le16(length); 3159 3160 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3161 if (length > I40E_AQ_LARGE_BUF) 3162 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3163 3164 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3165 3166 i40e_aq_read_nvm_exit: 3167 return status; 3168 } 3169 3170 /** 3171 * i40e_aq_erase_nvm 3172 * @hw: pointer to the hw struct 3173 * @module_pointer: module pointer location in words from the NVM beginning 3174 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3175 * @length: length of the section to be erased (expressed in 4 KB) 3176 * @last_command: tells if this is the last command in a series 3177 * @cmd_details: pointer to command details structure or NULL 3178 * 3179 * Erase the NVM sector using the admin queue commands 3180 **/ 3181 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3182 u32 offset, u16 length, bool last_command, 3183 struct i40e_asq_cmd_details *cmd_details) 3184 { 3185 struct i40e_aq_desc desc; 3186 struct i40e_aqc_nvm_update *cmd = 3187 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3188 i40e_status status; 3189 3190 /* In offset the highest byte must be zeroed. */ 3191 if (offset & 0xFF000000) { 3192 status = I40E_ERR_PARAM; 3193 goto i40e_aq_erase_nvm_exit; 3194 } 3195 3196 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3197 3198 /* If this is the last command in a series, set the proper flag. */ 3199 if (last_command) 3200 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3201 cmd->module_pointer = module_pointer; 3202 cmd->offset = cpu_to_le32(offset); 3203 cmd->length = cpu_to_le16(length); 3204 3205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3206 3207 i40e_aq_erase_nvm_exit: 3208 return status; 3209 } 3210 3211 /** 3212 * i40e_parse_discover_capabilities 3213 * @hw: pointer to the hw struct 3214 * @buff: pointer to a buffer containing device/function capability records 3215 * @cap_count: number of capability records in the list 3216 * @list_type_opc: type of capabilities list to parse 3217 * 3218 * Parse the device/function capabilities list. 3219 **/ 3220 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3221 u32 cap_count, 3222 enum i40e_admin_queue_opc list_type_opc) 3223 { 3224 struct i40e_aqc_list_capabilities_element_resp *cap; 3225 u32 valid_functions, num_functions; 3226 u32 number, logical_id, phys_id; 3227 struct i40e_hw_capabilities *p; 3228 u16 id, ocp_cfg_word0; 3229 i40e_status status; 3230 u8 major_rev; 3231 u32 i = 0; 3232 3233 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3234 3235 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3236 p = &hw->dev_caps; 3237 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3238 p = &hw->func_caps; 3239 else 3240 return; 3241 3242 for (i = 0; i < cap_count; i++, cap++) { 3243 id = le16_to_cpu(cap->id); 3244 number = le32_to_cpu(cap->number); 3245 logical_id = le32_to_cpu(cap->logical_id); 3246 phys_id = le32_to_cpu(cap->phys_id); 3247 major_rev = cap->major_rev; 3248 3249 switch (id) { 3250 case I40E_AQ_CAP_ID_SWITCH_MODE: 3251 p->switch_mode = number; 3252 break; 3253 case I40E_AQ_CAP_ID_MNG_MODE: 3254 p->management_mode = number; 3255 if (major_rev > 1) { 3256 p->mng_protocols_over_mctp = logical_id; 3257 i40e_debug(hw, I40E_DEBUG_INIT, 3258 "HW Capability: Protocols over MCTP = %d\n", 3259 p->mng_protocols_over_mctp); 3260 } else { 3261 p->mng_protocols_over_mctp = 0; 3262 } 3263 break; 3264 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3265 p->npar_enable = number; 3266 break; 3267 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3268 p->os2bmc = number; 3269 break; 3270 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3271 p->valid_functions = number; 3272 break; 3273 case I40E_AQ_CAP_ID_SRIOV: 3274 if (number == 1) 3275 p->sr_iov_1_1 = true; 3276 break; 3277 case I40E_AQ_CAP_ID_VF: 3278 p->num_vfs = number; 3279 p->vf_base_id = logical_id; 3280 break; 3281 case I40E_AQ_CAP_ID_VMDQ: 3282 if (number == 1) 3283 p->vmdq = true; 3284 break; 3285 case I40E_AQ_CAP_ID_8021QBG: 3286 if (number == 1) 3287 p->evb_802_1_qbg = true; 3288 break; 3289 case I40E_AQ_CAP_ID_8021QBR: 3290 if (number == 1) 3291 p->evb_802_1_qbh = true; 3292 break; 3293 case I40E_AQ_CAP_ID_VSI: 3294 p->num_vsis = number; 3295 break; 3296 case I40E_AQ_CAP_ID_DCB: 3297 if (number == 1) { 3298 p->dcb = true; 3299 p->enabled_tcmap = logical_id; 3300 p->maxtc = phys_id; 3301 } 3302 break; 3303 case I40E_AQ_CAP_ID_FCOE: 3304 if (number == 1) 3305 p->fcoe = true; 3306 break; 3307 case I40E_AQ_CAP_ID_ISCSI: 3308 if (number == 1) 3309 p->iscsi = true; 3310 break; 3311 case I40E_AQ_CAP_ID_RSS: 3312 p->rss = true; 3313 p->rss_table_size = number; 3314 p->rss_table_entry_width = logical_id; 3315 break; 3316 case I40E_AQ_CAP_ID_RXQ: 3317 p->num_rx_qp = number; 3318 p->base_queue = phys_id; 3319 break; 3320 case I40E_AQ_CAP_ID_TXQ: 3321 p->num_tx_qp = number; 3322 p->base_queue = phys_id; 3323 break; 3324 case I40E_AQ_CAP_ID_MSIX: 3325 p->num_msix_vectors = number; 3326 i40e_debug(hw, I40E_DEBUG_INIT, 3327 "HW Capability: MSIX vector count = %d\n", 3328 p->num_msix_vectors); 3329 break; 3330 case I40E_AQ_CAP_ID_VF_MSIX: 3331 p->num_msix_vectors_vf = number; 3332 break; 3333 case I40E_AQ_CAP_ID_FLEX10: 3334 if (major_rev == 1) { 3335 if (number == 1) { 3336 p->flex10_enable = true; 3337 p->flex10_capable = true; 3338 } 3339 } else { 3340 /* Capability revision >= 2 */ 3341 if (number & 1) 3342 p->flex10_enable = true; 3343 if (number & 2) 3344 p->flex10_capable = true; 3345 } 3346 p->flex10_mode = logical_id; 3347 p->flex10_status = phys_id; 3348 break; 3349 case I40E_AQ_CAP_ID_CEM: 3350 if (number == 1) 3351 p->mgmt_cem = true; 3352 break; 3353 case I40E_AQ_CAP_ID_IWARP: 3354 if (number == 1) 3355 p->iwarp = true; 3356 break; 3357 case I40E_AQ_CAP_ID_LED: 3358 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3359 p->led[phys_id] = true; 3360 break; 3361 case I40E_AQ_CAP_ID_SDP: 3362 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3363 p->sdp[phys_id] = true; 3364 break; 3365 case I40E_AQ_CAP_ID_MDIO: 3366 if (number == 1) { 3367 p->mdio_port_num = phys_id; 3368 p->mdio_port_mode = logical_id; 3369 } 3370 break; 3371 case I40E_AQ_CAP_ID_1588: 3372 if (number == 1) 3373 p->ieee_1588 = true; 3374 break; 3375 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3376 p->fd = true; 3377 p->fd_filters_guaranteed = number; 3378 p->fd_filters_best_effort = logical_id; 3379 break; 3380 case I40E_AQ_CAP_ID_WSR_PROT: 3381 p->wr_csr_prot = (u64)number; 3382 p->wr_csr_prot |= (u64)logical_id << 32; 3383 break; 3384 case I40E_AQ_CAP_ID_NVM_MGMT: 3385 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3386 p->sec_rev_disabled = true; 3387 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3388 p->update_disabled = true; 3389 break; 3390 default: 3391 break; 3392 } 3393 } 3394 3395 if (p->fcoe) 3396 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3397 3398 /* Software override ensuring FCoE is disabled if npar or mfp 3399 * mode because it is not supported in these modes. 3400 */ 3401 if (p->npar_enable || p->flex10_enable) 3402 p->fcoe = false; 3403 3404 /* count the enabled ports (aka the "not disabled" ports) */ 3405 hw->num_ports = 0; 3406 for (i = 0; i < 4; i++) { 3407 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3408 u64 port_cfg = 0; 3409 3410 /* use AQ read to get the physical register offset instead 3411 * of the port relative offset 3412 */ 3413 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3414 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3415 hw->num_ports++; 3416 } 3417 3418 /* OCP cards case: if a mezz is removed the Ethernet port is at 3419 * disabled state in PRTGEN_CNF register. Additional NVM read is 3420 * needed in order to check if we are dealing with OCP card. 3421 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3422 * physical ports results in wrong partition id calculation and thus 3423 * not supporting WoL. 3424 */ 3425 if (hw->mac.type == I40E_MAC_X722) { 3426 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 3427 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3428 2 * I40E_SR_OCP_CFG_WORD0, 3429 sizeof(ocp_cfg_word0), 3430 &ocp_cfg_word0, true, NULL); 3431 if (!status && 3432 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3433 hw->num_ports = 4; 3434 i40e_release_nvm(hw); 3435 } 3436 } 3437 3438 valid_functions = p->valid_functions; 3439 num_functions = 0; 3440 while (valid_functions) { 3441 if (valid_functions & 1) 3442 num_functions++; 3443 valid_functions >>= 1; 3444 } 3445 3446 /* partition id is 1-based, and functions are evenly spread 3447 * across the ports as partitions 3448 */ 3449 if (hw->num_ports != 0) { 3450 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3451 hw->num_partitions = num_functions / hw->num_ports; 3452 } 3453 3454 /* additional HW specific goodies that might 3455 * someday be HW version specific 3456 */ 3457 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3458 } 3459 3460 /** 3461 * i40e_aq_discover_capabilities 3462 * @hw: pointer to the hw struct 3463 * @buff: a virtual buffer to hold the capabilities 3464 * @buff_size: Size of the virtual buffer 3465 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3466 * @list_type_opc: capabilities type to discover - pass in the command opcode 3467 * @cmd_details: pointer to command details structure or NULL 3468 * 3469 * Get the device capabilities descriptions from the firmware 3470 **/ 3471 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3472 void *buff, u16 buff_size, u16 *data_size, 3473 enum i40e_admin_queue_opc list_type_opc, 3474 struct i40e_asq_cmd_details *cmd_details) 3475 { 3476 struct i40e_aqc_list_capabilites *cmd; 3477 struct i40e_aq_desc desc; 3478 i40e_status status = 0; 3479 3480 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3481 3482 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3483 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3484 status = I40E_ERR_PARAM; 3485 goto exit; 3486 } 3487 3488 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3489 3490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3491 if (buff_size > I40E_AQ_LARGE_BUF) 3492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3493 3494 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3495 *data_size = le16_to_cpu(desc.datalen); 3496 3497 if (status) 3498 goto exit; 3499 3500 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3501 list_type_opc); 3502 3503 exit: 3504 return status; 3505 } 3506 3507 /** 3508 * i40e_aq_update_nvm 3509 * @hw: pointer to the hw struct 3510 * @module_pointer: module pointer location in words from the NVM beginning 3511 * @offset: byte offset from the module beginning 3512 * @length: length of the section to be written (in bytes from the offset) 3513 * @data: command buffer (size [bytes] = length) 3514 * @last_command: tells if this is the last command in a series 3515 * @preservation_flags: Preservation mode flags 3516 * @cmd_details: pointer to command details structure or NULL 3517 * 3518 * Update the NVM using the admin queue commands 3519 **/ 3520 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3521 u32 offset, u16 length, void *data, 3522 bool last_command, u8 preservation_flags, 3523 struct i40e_asq_cmd_details *cmd_details) 3524 { 3525 struct i40e_aq_desc desc; 3526 struct i40e_aqc_nvm_update *cmd = 3527 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3528 i40e_status status; 3529 3530 /* In offset the highest byte must be zeroed. */ 3531 if (offset & 0xFF000000) { 3532 status = I40E_ERR_PARAM; 3533 goto i40e_aq_update_nvm_exit; 3534 } 3535 3536 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3537 3538 /* If this is the last command in a series, set the proper flag. */ 3539 if (last_command) 3540 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3541 if (hw->mac.type == I40E_MAC_X722) { 3542 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 3543 cmd->command_flags |= 3544 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3545 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3546 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3547 cmd->command_flags |= 3548 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3549 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3550 } 3551 cmd->module_pointer = module_pointer; 3552 cmd->offset = cpu_to_le32(offset); 3553 cmd->length = cpu_to_le16(length); 3554 3555 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3556 if (length > I40E_AQ_LARGE_BUF) 3557 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3558 3559 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3560 3561 i40e_aq_update_nvm_exit: 3562 return status; 3563 } 3564 3565 /** 3566 * i40e_aq_get_lldp_mib 3567 * @hw: pointer to the hw struct 3568 * @bridge_type: type of bridge requested 3569 * @mib_type: Local, Remote or both Local and Remote MIBs 3570 * @buff: pointer to a user supplied buffer to store the MIB block 3571 * @buff_size: size of the buffer (in bytes) 3572 * @local_len : length of the returned Local LLDP MIB 3573 * @remote_len: length of the returned Remote LLDP MIB 3574 * @cmd_details: pointer to command details structure or NULL 3575 * 3576 * Requests the complete LLDP MIB (entire packet). 3577 **/ 3578 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3579 u8 mib_type, void *buff, u16 buff_size, 3580 u16 *local_len, u16 *remote_len, 3581 struct i40e_asq_cmd_details *cmd_details) 3582 { 3583 struct i40e_aq_desc desc; 3584 struct i40e_aqc_lldp_get_mib *cmd = 3585 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3586 struct i40e_aqc_lldp_get_mib *resp = 3587 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3588 i40e_status status; 3589 3590 if (buff_size == 0 || !buff) 3591 return I40E_ERR_PARAM; 3592 3593 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3594 /* Indirect Command */ 3595 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3596 3597 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3598 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3599 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3600 3601 desc.datalen = cpu_to_le16(buff_size); 3602 3603 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3604 if (buff_size > I40E_AQ_LARGE_BUF) 3605 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3606 3607 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3608 if (!status) { 3609 if (local_len != NULL) 3610 *local_len = le16_to_cpu(resp->local_len); 3611 if (remote_len != NULL) 3612 *remote_len = le16_to_cpu(resp->remote_len); 3613 } 3614 3615 return status; 3616 } 3617 3618 /** 3619 * i40e_aq_cfg_lldp_mib_change_event 3620 * @hw: pointer to the hw struct 3621 * @enable_update: Enable or Disable event posting 3622 * @cmd_details: pointer to command details structure or NULL 3623 * 3624 * Enable or Disable posting of an event on ARQ when LLDP MIB 3625 * associated with the interface changes 3626 **/ 3627 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3628 bool enable_update, 3629 struct i40e_asq_cmd_details *cmd_details) 3630 { 3631 struct i40e_aq_desc desc; 3632 struct i40e_aqc_lldp_update_mib *cmd = 3633 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3634 i40e_status status; 3635 3636 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3637 3638 if (!enable_update) 3639 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3640 3641 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3642 3643 return status; 3644 } 3645 3646 /** 3647 * i40e_aq_stop_lldp 3648 * @hw: pointer to the hw struct 3649 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3650 * @cmd_details: pointer to command details structure or NULL 3651 * 3652 * Stop or Shutdown the embedded LLDP Agent 3653 **/ 3654 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3655 struct i40e_asq_cmd_details *cmd_details) 3656 { 3657 struct i40e_aq_desc desc; 3658 struct i40e_aqc_lldp_stop *cmd = 3659 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3660 i40e_status status; 3661 3662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3663 3664 if (shutdown_agent) 3665 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3666 3667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3668 3669 return status; 3670 } 3671 3672 /** 3673 * i40e_aq_start_lldp 3674 * @hw: pointer to the hw struct 3675 * @cmd_details: pointer to command details structure or NULL 3676 * 3677 * Start the embedded LLDP Agent on all ports. 3678 **/ 3679 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3680 struct i40e_asq_cmd_details *cmd_details) 3681 { 3682 struct i40e_aq_desc desc; 3683 struct i40e_aqc_lldp_start *cmd = 3684 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3685 i40e_status status; 3686 3687 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3688 3689 cmd->command = I40E_AQ_LLDP_AGENT_START; 3690 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3691 3692 return status; 3693 } 3694 3695 /** 3696 * i40e_aq_set_dcb_parameters 3697 * @hw: pointer to the hw struct 3698 * @cmd_details: pointer to command details structure or NULL 3699 * @dcb_enable: True if DCB configuration needs to be applied 3700 * 3701 **/ 3702 enum i40e_status_code 3703 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3704 struct i40e_asq_cmd_details *cmd_details) 3705 { 3706 struct i40e_aq_desc desc; 3707 struct i40e_aqc_set_dcb_parameters *cmd = 3708 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3709 i40e_status status; 3710 3711 i40e_fill_default_direct_cmd_desc(&desc, 3712 i40e_aqc_opc_set_dcb_parameters); 3713 3714 if (dcb_enable) { 3715 cmd->valid_flags = I40E_DCB_VALID; 3716 cmd->command = I40E_AQ_DCB_SET_AGENT; 3717 } 3718 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3719 3720 return status; 3721 } 3722 3723 /** 3724 * i40e_aq_get_cee_dcb_config 3725 * @hw: pointer to the hw struct 3726 * @buff: response buffer that stores CEE operational configuration 3727 * @buff_size: size of the buffer passed 3728 * @cmd_details: pointer to command details structure or NULL 3729 * 3730 * Get CEE DCBX mode operational configuration from firmware 3731 **/ 3732 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3733 void *buff, u16 buff_size, 3734 struct i40e_asq_cmd_details *cmd_details) 3735 { 3736 struct i40e_aq_desc desc; 3737 i40e_status status; 3738 3739 if (buff_size == 0 || !buff) 3740 return I40E_ERR_PARAM; 3741 3742 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3743 3744 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3745 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3746 cmd_details); 3747 3748 return status; 3749 } 3750 3751 /** 3752 * i40e_aq_add_udp_tunnel 3753 * @hw: pointer to the hw struct 3754 * @udp_port: the UDP port to add in Host byte order 3755 * @header_len: length of the tunneling header length in DWords 3756 * @protocol_index: protocol index type 3757 * @filter_index: pointer to filter index 3758 * @cmd_details: pointer to command details structure or NULL 3759 * 3760 * Note: Firmware expects the udp_port value to be in Little Endian format, 3761 * and this function will call cpu_to_le16 to convert from Host byte order to 3762 * Little Endian order. 3763 **/ 3764 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3765 u16 udp_port, u8 protocol_index, 3766 u8 *filter_index, 3767 struct i40e_asq_cmd_details *cmd_details) 3768 { 3769 struct i40e_aq_desc desc; 3770 struct i40e_aqc_add_udp_tunnel *cmd = 3771 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3772 struct i40e_aqc_del_udp_tunnel_completion *resp = 3773 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3774 i40e_status status; 3775 3776 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3777 3778 cmd->udp_port = cpu_to_le16(udp_port); 3779 cmd->protocol_type = protocol_index; 3780 3781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3782 3783 if (!status && filter_index) 3784 *filter_index = resp->index; 3785 3786 return status; 3787 } 3788 3789 /** 3790 * i40e_aq_del_udp_tunnel 3791 * @hw: pointer to the hw struct 3792 * @index: filter index 3793 * @cmd_details: pointer to command details structure or NULL 3794 **/ 3795 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3796 struct i40e_asq_cmd_details *cmd_details) 3797 { 3798 struct i40e_aq_desc desc; 3799 struct i40e_aqc_remove_udp_tunnel *cmd = 3800 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3801 i40e_status status; 3802 3803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3804 3805 cmd->index = index; 3806 3807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3808 3809 return status; 3810 } 3811 3812 /** 3813 * i40e_aq_delete_element - Delete switch element 3814 * @hw: pointer to the hw struct 3815 * @seid: the SEID to delete from the switch 3816 * @cmd_details: pointer to command details structure or NULL 3817 * 3818 * This deletes a switch element from the switch. 3819 **/ 3820 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3821 struct i40e_asq_cmd_details *cmd_details) 3822 { 3823 struct i40e_aq_desc desc; 3824 struct i40e_aqc_switch_seid *cmd = 3825 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3826 i40e_status status; 3827 3828 if (seid == 0) 3829 return I40E_ERR_PARAM; 3830 3831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3832 3833 cmd->seid = cpu_to_le16(seid); 3834 3835 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3836 3837 return status; 3838 } 3839 3840 /** 3841 * i40e_aq_dcb_updated - DCB Updated Command 3842 * @hw: pointer to the hw struct 3843 * @cmd_details: pointer to command details structure or NULL 3844 * 3845 * EMP will return when the shared RPB settings have been 3846 * recomputed and modified. The retval field in the descriptor 3847 * will be set to 0 when RPB is modified. 3848 **/ 3849 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3850 struct i40e_asq_cmd_details *cmd_details) 3851 { 3852 struct i40e_aq_desc desc; 3853 i40e_status status; 3854 3855 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3856 3857 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3858 3859 return status; 3860 } 3861 3862 /** 3863 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3864 * @hw: pointer to the hw struct 3865 * @seid: seid for the physical port/switching component/vsi 3866 * @buff: Indirect buffer to hold data parameters and response 3867 * @buff_size: Indirect buffer size 3868 * @opcode: Tx scheduler AQ command opcode 3869 * @cmd_details: pointer to command details structure or NULL 3870 * 3871 * Generic command handler for Tx scheduler AQ commands 3872 **/ 3873 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3874 void *buff, u16 buff_size, 3875 enum i40e_admin_queue_opc opcode, 3876 struct i40e_asq_cmd_details *cmd_details) 3877 { 3878 struct i40e_aq_desc desc; 3879 struct i40e_aqc_tx_sched_ind *cmd = 3880 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3881 i40e_status status; 3882 bool cmd_param_flag = false; 3883 3884 switch (opcode) { 3885 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3886 case i40e_aqc_opc_configure_vsi_tc_bw: 3887 case i40e_aqc_opc_enable_switching_comp_ets: 3888 case i40e_aqc_opc_modify_switching_comp_ets: 3889 case i40e_aqc_opc_disable_switching_comp_ets: 3890 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3891 case i40e_aqc_opc_configure_switching_comp_bw_config: 3892 cmd_param_flag = true; 3893 break; 3894 case i40e_aqc_opc_query_vsi_bw_config: 3895 case i40e_aqc_opc_query_vsi_ets_sla_config: 3896 case i40e_aqc_opc_query_switching_comp_ets_config: 3897 case i40e_aqc_opc_query_port_ets_config: 3898 case i40e_aqc_opc_query_switching_comp_bw_config: 3899 cmd_param_flag = false; 3900 break; 3901 default: 3902 return I40E_ERR_PARAM; 3903 } 3904 3905 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3906 3907 /* Indirect command */ 3908 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3909 if (cmd_param_flag) 3910 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3911 if (buff_size > I40E_AQ_LARGE_BUF) 3912 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3913 3914 desc.datalen = cpu_to_le16(buff_size); 3915 3916 cmd->vsi_seid = cpu_to_le16(seid); 3917 3918 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3919 3920 return status; 3921 } 3922 3923 /** 3924 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3925 * @hw: pointer to the hw struct 3926 * @seid: VSI seid 3927 * @credit: BW limit credits (0 = disabled) 3928 * @max_credit: Max BW limit credits 3929 * @cmd_details: pointer to command details structure or NULL 3930 **/ 3931 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3932 u16 seid, u16 credit, u8 max_credit, 3933 struct i40e_asq_cmd_details *cmd_details) 3934 { 3935 struct i40e_aq_desc desc; 3936 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3937 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3938 i40e_status status; 3939 3940 i40e_fill_default_direct_cmd_desc(&desc, 3941 i40e_aqc_opc_configure_vsi_bw_limit); 3942 3943 cmd->vsi_seid = cpu_to_le16(seid); 3944 cmd->credit = cpu_to_le16(credit); 3945 cmd->max_credit = max_credit; 3946 3947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3948 3949 return status; 3950 } 3951 3952 /** 3953 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3954 * @hw: pointer to the hw struct 3955 * @seid: VSI seid 3956 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3957 * @cmd_details: pointer to command details structure or NULL 3958 **/ 3959 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3960 u16 seid, 3961 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3962 struct i40e_asq_cmd_details *cmd_details) 3963 { 3964 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3965 i40e_aqc_opc_configure_vsi_tc_bw, 3966 cmd_details); 3967 } 3968 3969 /** 3970 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3971 * @hw: pointer to the hw struct 3972 * @seid: seid of the switching component connected to Physical Port 3973 * @ets_data: Buffer holding ETS parameters 3974 * @cmd_details: pointer to command details structure or NULL 3975 **/ 3976 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3977 u16 seid, 3978 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3979 enum i40e_admin_queue_opc opcode, 3980 struct i40e_asq_cmd_details *cmd_details) 3981 { 3982 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3983 sizeof(*ets_data), opcode, cmd_details); 3984 } 3985 3986 /** 3987 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3988 * @hw: pointer to the hw struct 3989 * @seid: seid of the switching component 3990 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3991 * @cmd_details: pointer to command details structure or NULL 3992 **/ 3993 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3994 u16 seid, 3995 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3996 struct i40e_asq_cmd_details *cmd_details) 3997 { 3998 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3999 i40e_aqc_opc_configure_switching_comp_bw_config, 4000 cmd_details); 4001 } 4002 4003 /** 4004 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4005 * @hw: pointer to the hw struct 4006 * @seid: seid of the VSI 4007 * @bw_data: Buffer to hold VSI BW configuration 4008 * @cmd_details: pointer to command details structure or NULL 4009 **/ 4010 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4011 u16 seid, 4012 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4013 struct i40e_asq_cmd_details *cmd_details) 4014 { 4015 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4016 i40e_aqc_opc_query_vsi_bw_config, 4017 cmd_details); 4018 } 4019 4020 /** 4021 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4022 * @hw: pointer to the hw struct 4023 * @seid: seid of the VSI 4024 * @bw_data: Buffer to hold VSI BW configuration per TC 4025 * @cmd_details: pointer to command details structure or NULL 4026 **/ 4027 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4028 u16 seid, 4029 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4030 struct i40e_asq_cmd_details *cmd_details) 4031 { 4032 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4033 i40e_aqc_opc_query_vsi_ets_sla_config, 4034 cmd_details); 4035 } 4036 4037 /** 4038 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4039 * @hw: pointer to the hw struct 4040 * @seid: seid of the switching component 4041 * @bw_data: Buffer to hold switching component's per TC BW config 4042 * @cmd_details: pointer to command details structure or NULL 4043 **/ 4044 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4045 u16 seid, 4046 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4047 struct i40e_asq_cmd_details *cmd_details) 4048 { 4049 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4050 i40e_aqc_opc_query_switching_comp_ets_config, 4051 cmd_details); 4052 } 4053 4054 /** 4055 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4056 * @hw: pointer to the hw struct 4057 * @seid: seid of the VSI or switching component connected to Physical Port 4058 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4059 * @cmd_details: pointer to command details structure or NULL 4060 **/ 4061 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4062 u16 seid, 4063 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4064 struct i40e_asq_cmd_details *cmd_details) 4065 { 4066 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4067 i40e_aqc_opc_query_port_ets_config, 4068 cmd_details); 4069 } 4070 4071 /** 4072 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4073 * @hw: pointer to the hw struct 4074 * @seid: seid of the switching component 4075 * @bw_data: Buffer to hold switching component's BW configuration 4076 * @cmd_details: pointer to command details structure or NULL 4077 **/ 4078 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4079 u16 seid, 4080 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4081 struct i40e_asq_cmd_details *cmd_details) 4082 { 4083 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4084 i40e_aqc_opc_query_switching_comp_bw_config, 4085 cmd_details); 4086 } 4087 4088 /** 4089 * i40e_validate_filter_settings 4090 * @hw: pointer to the hardware structure 4091 * @settings: Filter control settings 4092 * 4093 * Check and validate the filter control settings passed. 4094 * The function checks for the valid filter/context sizes being 4095 * passed for FCoE and PE. 4096 * 4097 * Returns 0 if the values passed are valid and within 4098 * range else returns an error. 4099 **/ 4100 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4101 struct i40e_filter_control_settings *settings) 4102 { 4103 u32 fcoe_cntx_size, fcoe_filt_size; 4104 u32 pe_cntx_size, pe_filt_size; 4105 u32 fcoe_fmax; 4106 u32 val; 4107 4108 /* Validate FCoE settings passed */ 4109 switch (settings->fcoe_filt_num) { 4110 case I40E_HASH_FILTER_SIZE_1K: 4111 case I40E_HASH_FILTER_SIZE_2K: 4112 case I40E_HASH_FILTER_SIZE_4K: 4113 case I40E_HASH_FILTER_SIZE_8K: 4114 case I40E_HASH_FILTER_SIZE_16K: 4115 case I40E_HASH_FILTER_SIZE_32K: 4116 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4117 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4118 break; 4119 default: 4120 return I40E_ERR_PARAM; 4121 } 4122 4123 switch (settings->fcoe_cntx_num) { 4124 case I40E_DMA_CNTX_SIZE_512: 4125 case I40E_DMA_CNTX_SIZE_1K: 4126 case I40E_DMA_CNTX_SIZE_2K: 4127 case I40E_DMA_CNTX_SIZE_4K: 4128 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4129 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4130 break; 4131 default: 4132 return I40E_ERR_PARAM; 4133 } 4134 4135 /* Validate PE settings passed */ 4136 switch (settings->pe_filt_num) { 4137 case I40E_HASH_FILTER_SIZE_1K: 4138 case I40E_HASH_FILTER_SIZE_2K: 4139 case I40E_HASH_FILTER_SIZE_4K: 4140 case I40E_HASH_FILTER_SIZE_8K: 4141 case I40E_HASH_FILTER_SIZE_16K: 4142 case I40E_HASH_FILTER_SIZE_32K: 4143 case I40E_HASH_FILTER_SIZE_64K: 4144 case I40E_HASH_FILTER_SIZE_128K: 4145 case I40E_HASH_FILTER_SIZE_256K: 4146 case I40E_HASH_FILTER_SIZE_512K: 4147 case I40E_HASH_FILTER_SIZE_1M: 4148 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4149 pe_filt_size <<= (u32)settings->pe_filt_num; 4150 break; 4151 default: 4152 return I40E_ERR_PARAM; 4153 } 4154 4155 switch (settings->pe_cntx_num) { 4156 case I40E_DMA_CNTX_SIZE_512: 4157 case I40E_DMA_CNTX_SIZE_1K: 4158 case I40E_DMA_CNTX_SIZE_2K: 4159 case I40E_DMA_CNTX_SIZE_4K: 4160 case I40E_DMA_CNTX_SIZE_8K: 4161 case I40E_DMA_CNTX_SIZE_16K: 4162 case I40E_DMA_CNTX_SIZE_32K: 4163 case I40E_DMA_CNTX_SIZE_64K: 4164 case I40E_DMA_CNTX_SIZE_128K: 4165 case I40E_DMA_CNTX_SIZE_256K: 4166 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4167 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4168 break; 4169 default: 4170 return I40E_ERR_PARAM; 4171 } 4172 4173 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4174 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4175 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4176 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4177 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4178 return I40E_ERR_INVALID_SIZE; 4179 4180 return 0; 4181 } 4182 4183 /** 4184 * i40e_set_filter_control 4185 * @hw: pointer to the hardware structure 4186 * @settings: Filter control settings 4187 * 4188 * Set the Queue Filters for PE/FCoE and enable filters required 4189 * for a single PF. It is expected that these settings are programmed 4190 * at the driver initialization time. 4191 **/ 4192 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4193 struct i40e_filter_control_settings *settings) 4194 { 4195 i40e_status ret = 0; 4196 u32 hash_lut_size = 0; 4197 u32 val; 4198 4199 if (!settings) 4200 return I40E_ERR_PARAM; 4201 4202 /* Validate the input settings */ 4203 ret = i40e_validate_filter_settings(hw, settings); 4204 if (ret) 4205 return ret; 4206 4207 /* Read the PF Queue Filter control register */ 4208 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4209 4210 /* Program required PE hash buckets for the PF */ 4211 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4212 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4213 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4214 /* Program required PE contexts for the PF */ 4215 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4216 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4217 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4218 4219 /* Program required FCoE hash buckets for the PF */ 4220 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4221 val |= ((u32)settings->fcoe_filt_num << 4222 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4223 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4224 /* Program required FCoE DDP contexts for the PF */ 4225 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4226 val |= ((u32)settings->fcoe_cntx_num << 4227 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4228 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4229 4230 /* Program Hash LUT size for the PF */ 4231 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4232 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4233 hash_lut_size = 1; 4234 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4235 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4236 4237 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4238 if (settings->enable_fdir) 4239 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4240 if (settings->enable_ethtype) 4241 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4242 if (settings->enable_macvlan) 4243 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4244 4245 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4246 4247 return 0; 4248 } 4249 4250 /** 4251 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4252 * @hw: pointer to the hw struct 4253 * @mac_addr: MAC address to use in the filter 4254 * @ethtype: Ethertype to use in the filter 4255 * @flags: Flags that needs to be applied to the filter 4256 * @vsi_seid: seid of the control VSI 4257 * @queue: VSI queue number to send the packet to 4258 * @is_add: Add control packet filter if True else remove 4259 * @stats: Structure to hold information on control filter counts 4260 * @cmd_details: pointer to command details structure or NULL 4261 * 4262 * This command will Add or Remove control packet filter for a control VSI. 4263 * In return it will update the total number of perfect filter count in 4264 * the stats member. 4265 **/ 4266 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4267 u8 *mac_addr, u16 ethtype, u16 flags, 4268 u16 vsi_seid, u16 queue, bool is_add, 4269 struct i40e_control_filter_stats *stats, 4270 struct i40e_asq_cmd_details *cmd_details) 4271 { 4272 struct i40e_aq_desc desc; 4273 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4274 (struct i40e_aqc_add_remove_control_packet_filter *) 4275 &desc.params.raw; 4276 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4277 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4278 &desc.params.raw; 4279 i40e_status status; 4280 4281 if (vsi_seid == 0) 4282 return I40E_ERR_PARAM; 4283 4284 if (is_add) { 4285 i40e_fill_default_direct_cmd_desc(&desc, 4286 i40e_aqc_opc_add_control_packet_filter); 4287 cmd->queue = cpu_to_le16(queue); 4288 } else { 4289 i40e_fill_default_direct_cmd_desc(&desc, 4290 i40e_aqc_opc_remove_control_packet_filter); 4291 } 4292 4293 if (mac_addr) 4294 ether_addr_copy(cmd->mac, mac_addr); 4295 4296 cmd->etype = cpu_to_le16(ethtype); 4297 cmd->flags = cpu_to_le16(flags); 4298 cmd->seid = cpu_to_le16(vsi_seid); 4299 4300 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4301 4302 if (!status && stats) { 4303 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4304 stats->etype_used = le16_to_cpu(resp->etype_used); 4305 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4306 stats->etype_free = le16_to_cpu(resp->etype_free); 4307 } 4308 4309 return status; 4310 } 4311 4312 /** 4313 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4314 * @hw: pointer to the hw struct 4315 * @seid: VSI seid to add ethertype filter from 4316 **/ 4317 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4318 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4319 u16 seid) 4320 { 4321 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4322 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4323 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4324 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4325 i40e_status status; 4326 4327 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4328 seid, 0, true, NULL, 4329 NULL); 4330 if (status) 4331 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4332 } 4333 4334 /** 4335 * i40e_aq_alternate_read 4336 * @hw: pointer to the hardware structure 4337 * @reg_addr0: address of first dword to be read 4338 * @reg_val0: pointer for data read from 'reg_addr0' 4339 * @reg_addr1: address of second dword to be read 4340 * @reg_val1: pointer for data read from 'reg_addr1' 4341 * 4342 * Read one or two dwords from alternate structure. Fields are indicated 4343 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4344 * is not passed then only register at 'reg_addr0' is read. 4345 * 4346 **/ 4347 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4348 u32 reg_addr0, u32 *reg_val0, 4349 u32 reg_addr1, u32 *reg_val1) 4350 { 4351 struct i40e_aq_desc desc; 4352 struct i40e_aqc_alternate_write *cmd_resp = 4353 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4354 i40e_status status; 4355 4356 if (!reg_val0) 4357 return I40E_ERR_PARAM; 4358 4359 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4360 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4361 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4362 4363 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4364 4365 if (!status) { 4366 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4367 4368 if (reg_val1) 4369 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4370 } 4371 4372 return status; 4373 } 4374 4375 /** 4376 * i40e_aq_resume_port_tx 4377 * @hw: pointer to the hardware structure 4378 * @cmd_details: pointer to command details structure or NULL 4379 * 4380 * Resume port's Tx traffic 4381 **/ 4382 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4383 struct i40e_asq_cmd_details *cmd_details) 4384 { 4385 struct i40e_aq_desc desc; 4386 i40e_status status; 4387 4388 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4389 4390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4391 4392 return status; 4393 } 4394 4395 /** 4396 * i40e_set_pci_config_data - store PCI bus info 4397 * @hw: pointer to hardware structure 4398 * @link_status: the link status word from PCI config space 4399 * 4400 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4401 **/ 4402 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4403 { 4404 hw->bus.type = i40e_bus_type_pci_express; 4405 4406 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4407 case PCI_EXP_LNKSTA_NLW_X1: 4408 hw->bus.width = i40e_bus_width_pcie_x1; 4409 break; 4410 case PCI_EXP_LNKSTA_NLW_X2: 4411 hw->bus.width = i40e_bus_width_pcie_x2; 4412 break; 4413 case PCI_EXP_LNKSTA_NLW_X4: 4414 hw->bus.width = i40e_bus_width_pcie_x4; 4415 break; 4416 case PCI_EXP_LNKSTA_NLW_X8: 4417 hw->bus.width = i40e_bus_width_pcie_x8; 4418 break; 4419 default: 4420 hw->bus.width = i40e_bus_width_unknown; 4421 break; 4422 } 4423 4424 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4425 case PCI_EXP_LNKSTA_CLS_2_5GB: 4426 hw->bus.speed = i40e_bus_speed_2500; 4427 break; 4428 case PCI_EXP_LNKSTA_CLS_5_0GB: 4429 hw->bus.speed = i40e_bus_speed_5000; 4430 break; 4431 case PCI_EXP_LNKSTA_CLS_8_0GB: 4432 hw->bus.speed = i40e_bus_speed_8000; 4433 break; 4434 default: 4435 hw->bus.speed = i40e_bus_speed_unknown; 4436 break; 4437 } 4438 } 4439 4440 /** 4441 * i40e_aq_debug_dump 4442 * @hw: pointer to the hardware structure 4443 * @cluster_id: specific cluster to dump 4444 * @table_id: table id within cluster 4445 * @start_index: index of line in the block to read 4446 * @buff_size: dump buffer size 4447 * @buff: dump buffer 4448 * @ret_buff_size: actual buffer size returned 4449 * @ret_next_table: next block to read 4450 * @ret_next_index: next index to read 4451 * 4452 * Dump internal FW/HW data for debug purposes. 4453 * 4454 **/ 4455 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4456 u8 table_id, u32 start_index, u16 buff_size, 4457 void *buff, u16 *ret_buff_size, 4458 u8 *ret_next_table, u32 *ret_next_index, 4459 struct i40e_asq_cmd_details *cmd_details) 4460 { 4461 struct i40e_aq_desc desc; 4462 struct i40e_aqc_debug_dump_internals *cmd = 4463 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4464 struct i40e_aqc_debug_dump_internals *resp = 4465 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4466 i40e_status status; 4467 4468 if (buff_size == 0 || !buff) 4469 return I40E_ERR_PARAM; 4470 4471 i40e_fill_default_direct_cmd_desc(&desc, 4472 i40e_aqc_opc_debug_dump_internals); 4473 /* Indirect Command */ 4474 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4475 if (buff_size > I40E_AQ_LARGE_BUF) 4476 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4477 4478 cmd->cluster_id = cluster_id; 4479 cmd->table_id = table_id; 4480 cmd->idx = cpu_to_le32(start_index); 4481 4482 desc.datalen = cpu_to_le16(buff_size); 4483 4484 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4485 if (!status) { 4486 if (ret_buff_size) 4487 *ret_buff_size = le16_to_cpu(desc.datalen); 4488 if (ret_next_table) 4489 *ret_next_table = resp->table_id; 4490 if (ret_next_index) 4491 *ret_next_index = le32_to_cpu(resp->idx); 4492 } 4493 4494 return status; 4495 } 4496 4497 /** 4498 * i40e_read_bw_from_alt_ram 4499 * @hw: pointer to the hardware structure 4500 * @max_bw: pointer for max_bw read 4501 * @min_bw: pointer for min_bw read 4502 * @min_valid: pointer for bool that is true if min_bw is a valid value 4503 * @max_valid: pointer for bool that is true if max_bw is a valid value 4504 * 4505 * Read bw from the alternate ram for the given pf 4506 **/ 4507 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4508 u32 *max_bw, u32 *min_bw, 4509 bool *min_valid, bool *max_valid) 4510 { 4511 i40e_status status; 4512 u32 max_bw_addr, min_bw_addr; 4513 4514 /* Calculate the address of the min/max bw registers */ 4515 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4516 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4517 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4518 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4519 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4520 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4521 4522 /* Read the bandwidths from alt ram */ 4523 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4524 min_bw_addr, min_bw); 4525 4526 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4527 *min_valid = true; 4528 else 4529 *min_valid = false; 4530 4531 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4532 *max_valid = true; 4533 else 4534 *max_valid = false; 4535 4536 return status; 4537 } 4538 4539 /** 4540 * i40e_aq_configure_partition_bw 4541 * @hw: pointer to the hardware structure 4542 * @bw_data: Buffer holding valid pfs and bw limits 4543 * @cmd_details: pointer to command details 4544 * 4545 * Configure partitions guaranteed/max bw 4546 **/ 4547 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4548 struct i40e_aqc_configure_partition_bw_data *bw_data, 4549 struct i40e_asq_cmd_details *cmd_details) 4550 { 4551 i40e_status status; 4552 struct i40e_aq_desc desc; 4553 u16 bwd_size = sizeof(*bw_data); 4554 4555 i40e_fill_default_direct_cmd_desc(&desc, 4556 i40e_aqc_opc_configure_partition_bw); 4557 4558 /* Indirect command */ 4559 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4560 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4561 4562 if (bwd_size > I40E_AQ_LARGE_BUF) 4563 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4564 4565 desc.datalen = cpu_to_le16(bwd_size); 4566 4567 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4568 cmd_details); 4569 4570 return status; 4571 } 4572 4573 /** 4574 * i40e_read_phy_register_clause22 4575 * @hw: pointer to the HW structure 4576 * @reg: register address in the page 4577 * @phy_adr: PHY address on MDIO interface 4578 * @value: PHY register value 4579 * 4580 * Reads specified PHY register value 4581 **/ 4582 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4583 u16 reg, u8 phy_addr, u16 *value) 4584 { 4585 i40e_status status = I40E_ERR_TIMEOUT; 4586 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4587 u32 command = 0; 4588 u16 retry = 1000; 4589 4590 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4591 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4592 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4593 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4594 (I40E_GLGEN_MSCA_MDICMD_MASK); 4595 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4596 do { 4597 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4598 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4599 status = 0; 4600 break; 4601 } 4602 udelay(10); 4603 retry--; 4604 } while (retry); 4605 4606 if (status) { 4607 i40e_debug(hw, I40E_DEBUG_PHY, 4608 "PHY: Can't write command to external PHY.\n"); 4609 } else { 4610 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4611 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4612 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4613 } 4614 4615 return status; 4616 } 4617 4618 /** 4619 * i40e_write_phy_register_clause22 4620 * @hw: pointer to the HW structure 4621 * @reg: register address in the page 4622 * @phy_adr: PHY address on MDIO interface 4623 * @value: PHY register value 4624 * 4625 * Writes specified PHY register value 4626 **/ 4627 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4628 u16 reg, u8 phy_addr, u16 value) 4629 { 4630 i40e_status status = I40E_ERR_TIMEOUT; 4631 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4632 u32 command = 0; 4633 u16 retry = 1000; 4634 4635 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4636 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4637 4638 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4639 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4640 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4641 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4642 (I40E_GLGEN_MSCA_MDICMD_MASK); 4643 4644 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4645 do { 4646 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4647 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4648 status = 0; 4649 break; 4650 } 4651 udelay(10); 4652 retry--; 4653 } while (retry); 4654 4655 return status; 4656 } 4657 4658 /** 4659 * i40e_read_phy_register_clause45 4660 * @hw: pointer to the HW structure 4661 * @page: registers page number 4662 * @reg: register address in the page 4663 * @phy_adr: PHY address on MDIO interface 4664 * @value: PHY register value 4665 * 4666 * Reads specified PHY register value 4667 **/ 4668 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4669 u8 page, u16 reg, u8 phy_addr, u16 *value) 4670 { 4671 i40e_status status = I40E_ERR_TIMEOUT; 4672 u32 command = 0; 4673 u16 retry = 1000; 4674 u8 port_num = hw->func_caps.mdio_port_num; 4675 4676 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4677 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4678 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4679 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4680 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4681 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4682 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4683 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4684 do { 4685 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4686 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4687 status = 0; 4688 break; 4689 } 4690 usleep_range(10, 20); 4691 retry--; 4692 } while (retry); 4693 4694 if (status) { 4695 i40e_debug(hw, I40E_DEBUG_PHY, 4696 "PHY: Can't write command to external PHY.\n"); 4697 goto phy_read_end; 4698 } 4699 4700 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4701 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4702 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4703 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4704 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4705 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4706 status = I40E_ERR_TIMEOUT; 4707 retry = 1000; 4708 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4709 do { 4710 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4711 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4712 status = 0; 4713 break; 4714 } 4715 usleep_range(10, 20); 4716 retry--; 4717 } while (retry); 4718 4719 if (!status) { 4720 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4721 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4722 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4723 } else { 4724 i40e_debug(hw, I40E_DEBUG_PHY, 4725 "PHY: Can't read register value from external PHY.\n"); 4726 } 4727 4728 phy_read_end: 4729 return status; 4730 } 4731 4732 /** 4733 * i40e_write_phy_register_clause45 4734 * @hw: pointer to the HW structure 4735 * @page: registers page number 4736 * @reg: register address in the page 4737 * @phy_adr: PHY address on MDIO interface 4738 * @value: PHY register value 4739 * 4740 * Writes value to specified PHY register 4741 **/ 4742 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4743 u8 page, u16 reg, u8 phy_addr, u16 value) 4744 { 4745 i40e_status status = I40E_ERR_TIMEOUT; 4746 u32 command = 0; 4747 u16 retry = 1000; 4748 u8 port_num = hw->func_caps.mdio_port_num; 4749 4750 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4751 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4752 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4753 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4754 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4755 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4756 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4757 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4758 do { 4759 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4760 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4761 status = 0; 4762 break; 4763 } 4764 usleep_range(10, 20); 4765 retry--; 4766 } while (retry); 4767 if (status) { 4768 i40e_debug(hw, I40E_DEBUG_PHY, 4769 "PHY: Can't write command to external PHY.\n"); 4770 goto phy_write_end; 4771 } 4772 4773 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4774 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4775 4776 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4777 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4778 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4779 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4780 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4781 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4782 status = I40E_ERR_TIMEOUT; 4783 retry = 1000; 4784 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4785 do { 4786 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4787 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4788 status = 0; 4789 break; 4790 } 4791 usleep_range(10, 20); 4792 retry--; 4793 } while (retry); 4794 4795 phy_write_end: 4796 return status; 4797 } 4798 4799 /** 4800 * i40e_write_phy_register 4801 * @hw: pointer to the HW structure 4802 * @page: registers page number 4803 * @reg: register address in the page 4804 * @phy_adr: PHY address on MDIO interface 4805 * @value: PHY register value 4806 * 4807 * Writes value to specified PHY register 4808 **/ 4809 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4810 u8 page, u16 reg, u8 phy_addr, u16 value) 4811 { 4812 i40e_status status; 4813 4814 switch (hw->device_id) { 4815 case I40E_DEV_ID_1G_BASE_T_X722: 4816 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4817 value); 4818 break; 4819 case I40E_DEV_ID_10G_BASE_T: 4820 case I40E_DEV_ID_10G_BASE_T4: 4821 case I40E_DEV_ID_10G_BASE_T_X722: 4822 case I40E_DEV_ID_25G_B: 4823 case I40E_DEV_ID_25G_SFP28: 4824 status = i40e_write_phy_register_clause45(hw, page, reg, 4825 phy_addr, value); 4826 break; 4827 default: 4828 status = I40E_ERR_UNKNOWN_PHY; 4829 break; 4830 } 4831 4832 return status; 4833 } 4834 4835 /** 4836 * i40e_read_phy_register 4837 * @hw: pointer to the HW structure 4838 * @page: registers page number 4839 * @reg: register address in the page 4840 * @phy_adr: PHY address on MDIO interface 4841 * @value: PHY register value 4842 * 4843 * Reads specified PHY register value 4844 **/ 4845 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4846 u8 page, u16 reg, u8 phy_addr, u16 *value) 4847 { 4848 i40e_status status; 4849 4850 switch (hw->device_id) { 4851 case I40E_DEV_ID_1G_BASE_T_X722: 4852 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4853 value); 4854 break; 4855 case I40E_DEV_ID_10G_BASE_T: 4856 case I40E_DEV_ID_10G_BASE_T4: 4857 case I40E_DEV_ID_10G_BASE_T_X722: 4858 case I40E_DEV_ID_25G_B: 4859 case I40E_DEV_ID_25G_SFP28: 4860 status = i40e_read_phy_register_clause45(hw, page, reg, 4861 phy_addr, value); 4862 break; 4863 default: 4864 status = I40E_ERR_UNKNOWN_PHY; 4865 break; 4866 } 4867 4868 return status; 4869 } 4870 4871 /** 4872 * i40e_get_phy_address 4873 * @hw: pointer to the HW structure 4874 * @dev_num: PHY port num that address we want 4875 * @phy_addr: Returned PHY address 4876 * 4877 * Gets PHY address for current port 4878 **/ 4879 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4880 { 4881 u8 port_num = hw->func_caps.mdio_port_num; 4882 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4883 4884 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4885 } 4886 4887 /** 4888 * i40e_blink_phy_led 4889 * @hw: pointer to the HW structure 4890 * @time: time how long led will blinks in secs 4891 * @interval: gap between LED on and off in msecs 4892 * 4893 * Blinks PHY link LED 4894 **/ 4895 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4896 u32 time, u32 interval) 4897 { 4898 i40e_status status = 0; 4899 u32 i; 4900 u16 led_ctl; 4901 u16 gpio_led_port; 4902 u16 led_reg; 4903 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4904 u8 phy_addr = 0; 4905 u8 port_num; 4906 4907 i = rd32(hw, I40E_PFGEN_PORTNUM); 4908 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4909 phy_addr = i40e_get_phy_address(hw, port_num); 4910 4911 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4912 led_addr++) { 4913 status = i40e_read_phy_register_clause45(hw, 4914 I40E_PHY_COM_REG_PAGE, 4915 led_addr, phy_addr, 4916 &led_reg); 4917 if (status) 4918 goto phy_blinking_end; 4919 led_ctl = led_reg; 4920 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4921 led_reg = 0; 4922 status = i40e_write_phy_register_clause45(hw, 4923 I40E_PHY_COM_REG_PAGE, 4924 led_addr, phy_addr, 4925 led_reg); 4926 if (status) 4927 goto phy_blinking_end; 4928 break; 4929 } 4930 } 4931 4932 if (time > 0 && interval > 0) { 4933 for (i = 0; i < time * 1000; i += interval) { 4934 status = i40e_read_phy_register_clause45(hw, 4935 I40E_PHY_COM_REG_PAGE, 4936 led_addr, phy_addr, &led_reg); 4937 if (status) 4938 goto restore_config; 4939 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4940 led_reg = 0; 4941 else 4942 led_reg = I40E_PHY_LED_MANUAL_ON; 4943 status = i40e_write_phy_register_clause45(hw, 4944 I40E_PHY_COM_REG_PAGE, 4945 led_addr, phy_addr, led_reg); 4946 if (status) 4947 goto restore_config; 4948 msleep(interval); 4949 } 4950 } 4951 4952 restore_config: 4953 status = i40e_write_phy_register_clause45(hw, 4954 I40E_PHY_COM_REG_PAGE, 4955 led_addr, phy_addr, led_ctl); 4956 4957 phy_blinking_end: 4958 return status; 4959 } 4960 4961 /** 4962 * i40e_led_get_reg - read LED register 4963 * @hw: pointer to the HW structure 4964 * @led_addr: LED register address 4965 * @reg_val: read register value 4966 **/ 4967 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4968 u32 *reg_val) 4969 { 4970 enum i40e_status_code status; 4971 u8 phy_addr = 0; 4972 u8 port_num; 4973 u32 i; 4974 4975 *reg_val = 0; 4976 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4977 status = 4978 i40e_aq_get_phy_register(hw, 4979 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4980 I40E_PHY_COM_REG_PAGE, 4981 I40E_PHY_LED_PROV_REG_1, 4982 reg_val, NULL); 4983 } else { 4984 i = rd32(hw, I40E_PFGEN_PORTNUM); 4985 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4986 phy_addr = i40e_get_phy_address(hw, port_num); 4987 status = i40e_read_phy_register_clause45(hw, 4988 I40E_PHY_COM_REG_PAGE, 4989 led_addr, phy_addr, 4990 (u16 *)reg_val); 4991 } 4992 return status; 4993 } 4994 4995 /** 4996 * i40e_led_set_reg - write LED register 4997 * @hw: pointer to the HW structure 4998 * @led_addr: LED register address 4999 * @reg_val: register value to write 5000 **/ 5001 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 5002 u32 reg_val) 5003 { 5004 enum i40e_status_code status; 5005 u8 phy_addr = 0; 5006 u8 port_num; 5007 u32 i; 5008 5009 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5010 status = 5011 i40e_aq_set_phy_register(hw, 5012 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5013 I40E_PHY_COM_REG_PAGE, 5014 I40E_PHY_LED_PROV_REG_1, 5015 reg_val, NULL); 5016 } else { 5017 i = rd32(hw, I40E_PFGEN_PORTNUM); 5018 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5019 phy_addr = i40e_get_phy_address(hw, port_num); 5020 status = i40e_write_phy_register_clause45(hw, 5021 I40E_PHY_COM_REG_PAGE, 5022 led_addr, phy_addr, 5023 (u16)reg_val); 5024 } 5025 5026 return status; 5027 } 5028 5029 /** 5030 * i40e_led_get_phy - return current on/off mode 5031 * @hw: pointer to the hw struct 5032 * @led_addr: address of led register to use 5033 * @val: original value of register to use 5034 * 5035 **/ 5036 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 5037 u16 *val) 5038 { 5039 i40e_status status = 0; 5040 u16 gpio_led_port; 5041 u8 phy_addr = 0; 5042 u16 reg_val; 5043 u16 temp_addr; 5044 u8 port_num; 5045 u32 i; 5046 u32 reg_val_aq; 5047 5048 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5049 status = 5050 i40e_aq_get_phy_register(hw, 5051 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5052 I40E_PHY_COM_REG_PAGE, 5053 I40E_PHY_LED_PROV_REG_1, 5054 ®_val_aq, NULL); 5055 if (status == I40E_SUCCESS) 5056 *val = (u16)reg_val_aq; 5057 return status; 5058 } 5059 temp_addr = I40E_PHY_LED_PROV_REG_1; 5060 i = rd32(hw, I40E_PFGEN_PORTNUM); 5061 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5062 phy_addr = i40e_get_phy_address(hw, port_num); 5063 5064 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5065 temp_addr++) { 5066 status = i40e_read_phy_register_clause45(hw, 5067 I40E_PHY_COM_REG_PAGE, 5068 temp_addr, phy_addr, 5069 ®_val); 5070 if (status) 5071 return status; 5072 *val = reg_val; 5073 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 5074 *led_addr = temp_addr; 5075 break; 5076 } 5077 } 5078 return status; 5079 } 5080 5081 /** 5082 * i40e_led_set_phy 5083 * @hw: pointer to the HW structure 5084 * @on: true or false 5085 * @mode: original val plus bit for set or ignore 5086 * Set led's on or off when controlled by the PHY 5087 * 5088 **/ 5089 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 5090 u16 led_addr, u32 mode) 5091 { 5092 i40e_status status = 0; 5093 u32 led_ctl = 0; 5094 u32 led_reg = 0; 5095 5096 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5097 if (status) 5098 return status; 5099 led_ctl = led_reg; 5100 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5101 led_reg = 0; 5102 status = i40e_led_set_reg(hw, led_addr, led_reg); 5103 if (status) 5104 return status; 5105 } 5106 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5107 if (status) 5108 goto restore_config; 5109 if (on) 5110 led_reg = I40E_PHY_LED_MANUAL_ON; 5111 else 5112 led_reg = 0; 5113 5114 status = i40e_led_set_reg(hw, led_addr, led_reg); 5115 if (status) 5116 goto restore_config; 5117 if (mode & I40E_PHY_LED_MODE_ORIG) { 5118 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5119 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5120 } 5121 return status; 5122 5123 restore_config: 5124 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5125 return status; 5126 } 5127 5128 /** 5129 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5130 * @hw: pointer to the hw struct 5131 * @reg_addr: register address 5132 * @reg_val: ptr to register value 5133 * @cmd_details: pointer to command details structure or NULL 5134 * 5135 * Use the firmware to read the Rx control register, 5136 * especially useful if the Rx unit is under heavy pressure 5137 **/ 5138 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5139 u32 reg_addr, u32 *reg_val, 5140 struct i40e_asq_cmd_details *cmd_details) 5141 { 5142 struct i40e_aq_desc desc; 5143 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5144 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5145 i40e_status status; 5146 5147 if (!reg_val) 5148 return I40E_ERR_PARAM; 5149 5150 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5151 5152 cmd_resp->address = cpu_to_le32(reg_addr); 5153 5154 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5155 5156 if (status == 0) 5157 *reg_val = le32_to_cpu(cmd_resp->value); 5158 5159 return status; 5160 } 5161 5162 /** 5163 * i40e_read_rx_ctl - read from an Rx control register 5164 * @hw: pointer to the hw struct 5165 * @reg_addr: register address 5166 **/ 5167 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5168 { 5169 i40e_status status = 0; 5170 bool use_register; 5171 int retry = 5; 5172 u32 val = 0; 5173 5174 use_register = (((hw->aq.api_maj_ver == 1) && 5175 (hw->aq.api_min_ver < 5)) || 5176 (hw->mac.type == I40E_MAC_X722)); 5177 if (!use_register) { 5178 do_retry: 5179 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5180 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5181 usleep_range(1000, 2000); 5182 retry--; 5183 goto do_retry; 5184 } 5185 } 5186 5187 /* if the AQ access failed, try the old-fashioned way */ 5188 if (status || use_register) 5189 val = rd32(hw, reg_addr); 5190 5191 return val; 5192 } 5193 5194 /** 5195 * i40e_aq_rx_ctl_write_register 5196 * @hw: pointer to the hw struct 5197 * @reg_addr: register address 5198 * @reg_val: register value 5199 * @cmd_details: pointer to command details structure or NULL 5200 * 5201 * Use the firmware to write to an Rx control register, 5202 * especially useful if the Rx unit is under heavy pressure 5203 **/ 5204 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5205 u32 reg_addr, u32 reg_val, 5206 struct i40e_asq_cmd_details *cmd_details) 5207 { 5208 struct i40e_aq_desc desc; 5209 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5210 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5211 i40e_status status; 5212 5213 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5214 5215 cmd->address = cpu_to_le32(reg_addr); 5216 cmd->value = cpu_to_le32(reg_val); 5217 5218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5219 5220 return status; 5221 } 5222 5223 /** 5224 * i40e_write_rx_ctl - write to an Rx control register 5225 * @hw: pointer to the hw struct 5226 * @reg_addr: register address 5227 * @reg_val: register value 5228 **/ 5229 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5230 { 5231 i40e_status status = 0; 5232 bool use_register; 5233 int retry = 5; 5234 5235 use_register = (((hw->aq.api_maj_ver == 1) && 5236 (hw->aq.api_min_ver < 5)) || 5237 (hw->mac.type == I40E_MAC_X722)); 5238 if (!use_register) { 5239 do_retry: 5240 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5241 reg_val, NULL); 5242 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5243 usleep_range(1000, 2000); 5244 retry--; 5245 goto do_retry; 5246 } 5247 } 5248 5249 /* if the AQ access failed, try the old-fashioned way */ 5250 if (status || use_register) 5251 wr32(hw, reg_addr, reg_val); 5252 } 5253 5254 /** 5255 * i40e_aq_set_phy_register 5256 * @hw: pointer to the hw struct 5257 * @phy_select: select which phy should be accessed 5258 * @dev_addr: PHY device address 5259 * @reg_addr: PHY register address 5260 * @reg_val: new register value 5261 * @cmd_details: pointer to command details structure or NULL 5262 * 5263 * Write the external PHY register. 5264 **/ 5265 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5266 u8 phy_select, u8 dev_addr, 5267 u32 reg_addr, u32 reg_val, 5268 struct i40e_asq_cmd_details *cmd_details) 5269 { 5270 struct i40e_aq_desc desc; 5271 struct i40e_aqc_phy_register_access *cmd = 5272 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5273 i40e_status status; 5274 5275 i40e_fill_default_direct_cmd_desc(&desc, 5276 i40e_aqc_opc_set_phy_register); 5277 5278 cmd->phy_interface = phy_select; 5279 cmd->dev_address = dev_addr; 5280 cmd->reg_address = cpu_to_le32(reg_addr); 5281 cmd->reg_value = cpu_to_le32(reg_val); 5282 5283 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5284 5285 return status; 5286 } 5287 5288 /** 5289 * i40e_aq_get_phy_register 5290 * @hw: pointer to the hw struct 5291 * @phy_select: select which phy should be accessed 5292 * @dev_addr: PHY device address 5293 * @reg_addr: PHY register address 5294 * @reg_val: read register value 5295 * @cmd_details: pointer to command details structure or NULL 5296 * 5297 * Read the external PHY register. 5298 **/ 5299 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5300 u8 phy_select, u8 dev_addr, 5301 u32 reg_addr, u32 *reg_val, 5302 struct i40e_asq_cmd_details *cmd_details) 5303 { 5304 struct i40e_aq_desc desc; 5305 struct i40e_aqc_phy_register_access *cmd = 5306 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5307 i40e_status status; 5308 5309 i40e_fill_default_direct_cmd_desc(&desc, 5310 i40e_aqc_opc_get_phy_register); 5311 5312 cmd->phy_interface = phy_select; 5313 cmd->dev_address = dev_addr; 5314 cmd->reg_address = cpu_to_le32(reg_addr); 5315 5316 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5317 if (!status) 5318 *reg_val = le32_to_cpu(cmd->reg_value); 5319 5320 return status; 5321 } 5322 5323 /** 5324 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 5325 * @hw: pointer to the hw struct 5326 * @buff: command buffer (size in bytes = buff_size) 5327 * @buff_size: buffer size in bytes 5328 * @track_id: package tracking id 5329 * @error_offset: returns error offset 5330 * @error_info: returns error information 5331 * @cmd_details: pointer to command details structure or NULL 5332 **/ 5333 enum 5334 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 5335 u16 buff_size, u32 track_id, 5336 u32 *error_offset, u32 *error_info, 5337 struct i40e_asq_cmd_details *cmd_details) 5338 { 5339 struct i40e_aq_desc desc; 5340 struct i40e_aqc_write_personalization_profile *cmd = 5341 (struct i40e_aqc_write_personalization_profile *) 5342 &desc.params.raw; 5343 struct i40e_aqc_write_ddp_resp *resp; 5344 i40e_status status; 5345 5346 i40e_fill_default_direct_cmd_desc(&desc, 5347 i40e_aqc_opc_write_personalization_profile); 5348 5349 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5350 if (buff_size > I40E_AQ_LARGE_BUF) 5351 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5352 5353 desc.datalen = cpu_to_le16(buff_size); 5354 5355 cmd->profile_track_id = cpu_to_le32(track_id); 5356 5357 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5358 if (!status) { 5359 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 5360 if (error_offset) 5361 *error_offset = le32_to_cpu(resp->error_offset); 5362 if (error_info) 5363 *error_info = le32_to_cpu(resp->error_info); 5364 } 5365 5366 return status; 5367 } 5368 5369 /** 5370 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 5371 * @hw: pointer to the hw struct 5372 * @buff: command buffer (size in bytes = buff_size) 5373 * @buff_size: buffer size in bytes 5374 * @cmd_details: pointer to command details structure or NULL 5375 **/ 5376 enum 5377 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 5378 u16 buff_size, u8 flags, 5379 struct i40e_asq_cmd_details *cmd_details) 5380 { 5381 struct i40e_aq_desc desc; 5382 struct i40e_aqc_get_applied_profiles *cmd = 5383 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5384 i40e_status status; 5385 5386 i40e_fill_default_direct_cmd_desc(&desc, 5387 i40e_aqc_opc_get_personalization_profile_list); 5388 5389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5390 if (buff_size > I40E_AQ_LARGE_BUF) 5391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5392 desc.datalen = cpu_to_le16(buff_size); 5393 5394 cmd->flags = flags; 5395 5396 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5397 5398 return status; 5399 } 5400 5401 /** 5402 * i40e_find_segment_in_package 5403 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5404 * @pkg_hdr: pointer to the package header to be searched 5405 * 5406 * This function searches a package file for a particular segment type. On 5407 * success it returns a pointer to the segment header, otherwise it will 5408 * return NULL. 5409 **/ 5410 struct i40e_generic_seg_header * 5411 i40e_find_segment_in_package(u32 segment_type, 5412 struct i40e_package_header *pkg_hdr) 5413 { 5414 struct i40e_generic_seg_header *segment; 5415 u32 i; 5416 5417 /* Search all package segments for the requested segment type */ 5418 for (i = 0; i < pkg_hdr->segment_count; i++) { 5419 segment = 5420 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5421 pkg_hdr->segment_offset[i]); 5422 5423 if (segment->type == segment_type) 5424 return segment; 5425 } 5426 5427 return NULL; 5428 } 5429 5430 /** 5431 * i40e_write_profile 5432 * @hw: pointer to the hardware structure 5433 * @profile: pointer to the profile segment of the package to be downloaded 5434 * @track_id: package tracking id 5435 * 5436 * Handles the download of a complete package. 5437 */ 5438 enum i40e_status_code 5439 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5440 u32 track_id) 5441 { 5442 i40e_status status = 0; 5443 struct i40e_section_table *sec_tbl; 5444 struct i40e_profile_section_header *sec = NULL; 5445 u32 dev_cnt; 5446 u32 vendor_dev_id; 5447 u32 *nvm; 5448 u32 section_size = 0; 5449 u32 offset = 0, info = 0; 5450 u32 i; 5451 5452 dev_cnt = profile->device_table_count; 5453 5454 for (i = 0; i < dev_cnt; i++) { 5455 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5456 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5457 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5458 break; 5459 } 5460 if (i == dev_cnt) { 5461 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP"); 5462 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5463 } 5464 5465 nvm = (u32 *)&profile->device_table[dev_cnt]; 5466 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5467 5468 for (i = 0; i < sec_tbl->section_count; i++) { 5469 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5470 sec_tbl->section_offset[i]); 5471 5472 /* Skip 'AQ', 'note' and 'name' sections */ 5473 if (sec->section.type != SECTION_TYPE_MMIO) 5474 continue; 5475 5476 section_size = sec->section.size + 5477 sizeof(struct i40e_profile_section_header); 5478 5479 /* Write profile */ 5480 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5481 track_id, &offset, &info, NULL); 5482 if (status) { 5483 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5484 "Failed to write profile: offset %d, info %d", 5485 offset, info); 5486 break; 5487 } 5488 } 5489 return status; 5490 } 5491 5492 /** 5493 * i40e_add_pinfo_to_list 5494 * @hw: pointer to the hardware structure 5495 * @profile: pointer to the profile segment of the package 5496 * @profile_info_sec: buffer for information section 5497 * @track_id: package tracking id 5498 * 5499 * Register a profile to the list of loaded profiles. 5500 */ 5501 enum i40e_status_code 5502 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5503 struct i40e_profile_segment *profile, 5504 u8 *profile_info_sec, u32 track_id) 5505 { 5506 i40e_status status = 0; 5507 struct i40e_profile_section_header *sec = NULL; 5508 struct i40e_profile_info *pinfo; 5509 u32 offset = 0, info = 0; 5510 5511 sec = (struct i40e_profile_section_header *)profile_info_sec; 5512 sec->tbl_size = 1; 5513 sec->data_end = sizeof(struct i40e_profile_section_header) + 5514 sizeof(struct i40e_profile_info); 5515 sec->section.type = SECTION_TYPE_INFO; 5516 sec->section.offset = sizeof(struct i40e_profile_section_header); 5517 sec->section.size = sizeof(struct i40e_profile_info); 5518 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5519 sec->section.offset); 5520 pinfo->track_id = track_id; 5521 pinfo->version = profile->version; 5522 pinfo->op = I40E_DDP_ADD_TRACKID; 5523 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); 5524 5525 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 5526 track_id, &offset, &info, NULL); 5527 5528 return status; 5529 } 5530 5531 /** 5532 * i40e_aq_add_cloud_filters 5533 * @hw: pointer to the hardware structure 5534 * @seid: VSI seid to add cloud filters from 5535 * @filters: Buffer which contains the filters to be added 5536 * @filter_count: number of filters contained in the buffer 5537 * 5538 * Set the cloud filters for a given VSI. The contents of the 5539 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5540 * of the function. 5541 * 5542 **/ 5543 enum i40e_status_code 5544 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5545 struct i40e_aqc_cloud_filters_element_data *filters, 5546 u8 filter_count) 5547 { 5548 struct i40e_aq_desc desc; 5549 struct i40e_aqc_add_remove_cloud_filters *cmd = 5550 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5551 enum i40e_status_code status; 5552 u16 buff_len; 5553 5554 i40e_fill_default_direct_cmd_desc(&desc, 5555 i40e_aqc_opc_add_cloud_filters); 5556 5557 buff_len = filter_count * sizeof(*filters); 5558 desc.datalen = cpu_to_le16(buff_len); 5559 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5560 cmd->num_filters = filter_count; 5561 cmd->seid = cpu_to_le16(seid); 5562 5563 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5564 5565 return status; 5566 } 5567 5568 /** 5569 * i40e_aq_add_cloud_filters_bb 5570 * @hw: pointer to the hardware structure 5571 * @seid: VSI seid to add cloud filters from 5572 * @filters: Buffer which contains the filters in big buffer to be added 5573 * @filter_count: number of filters contained in the buffer 5574 * 5575 * Set the big buffer cloud filters for a given VSI. The contents of the 5576 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5577 * function. 5578 * 5579 **/ 5580 enum i40e_status_code 5581 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5582 struct i40e_aqc_cloud_filters_element_bb *filters, 5583 u8 filter_count) 5584 { 5585 struct i40e_aq_desc desc; 5586 struct i40e_aqc_add_remove_cloud_filters *cmd = 5587 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5588 i40e_status status; 5589 u16 buff_len; 5590 int i; 5591 5592 i40e_fill_default_direct_cmd_desc(&desc, 5593 i40e_aqc_opc_add_cloud_filters); 5594 5595 buff_len = filter_count * sizeof(*filters); 5596 desc.datalen = cpu_to_le16(buff_len); 5597 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5598 cmd->num_filters = filter_count; 5599 cmd->seid = cpu_to_le16(seid); 5600 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5601 5602 for (i = 0; i < filter_count; i++) { 5603 u16 tnl_type; 5604 u32 ti; 5605 5606 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5607 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5608 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5609 5610 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5611 * one more byte further than normally used for Tenant ID in 5612 * other tunnel types. 5613 */ 5614 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5615 ti = le32_to_cpu(filters[i].element.tenant_id); 5616 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5617 } 5618 } 5619 5620 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5621 5622 return status; 5623 } 5624 5625 /** 5626 * i40e_aq_rem_cloud_filters 5627 * @hw: pointer to the hardware structure 5628 * @seid: VSI seid to remove cloud filters from 5629 * @filters: Buffer which contains the filters to be removed 5630 * @filter_count: number of filters contained in the buffer 5631 * 5632 * Remove the cloud filters for a given VSI. The contents of the 5633 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5634 * of the function. 5635 * 5636 **/ 5637 enum i40e_status_code 5638 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5639 struct i40e_aqc_cloud_filters_element_data *filters, 5640 u8 filter_count) 5641 { 5642 struct i40e_aq_desc desc; 5643 struct i40e_aqc_add_remove_cloud_filters *cmd = 5644 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5645 enum i40e_status_code status; 5646 u16 buff_len; 5647 5648 i40e_fill_default_direct_cmd_desc(&desc, 5649 i40e_aqc_opc_remove_cloud_filters); 5650 5651 buff_len = filter_count * sizeof(*filters); 5652 desc.datalen = cpu_to_le16(buff_len); 5653 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5654 cmd->num_filters = filter_count; 5655 cmd->seid = cpu_to_le16(seid); 5656 5657 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5658 5659 return status; 5660 } 5661 5662 /** 5663 * i40e_aq_rem_cloud_filters_bb 5664 * @hw: pointer to the hardware structure 5665 * @seid: VSI seid to remove cloud filters from 5666 * @filters: Buffer which contains the filters in big buffer to be removed 5667 * @filter_count: number of filters contained in the buffer 5668 * 5669 * Remove the big buffer cloud filters for a given VSI. The contents of the 5670 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5671 * function. 5672 * 5673 **/ 5674 enum i40e_status_code 5675 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5676 struct i40e_aqc_cloud_filters_element_bb *filters, 5677 u8 filter_count) 5678 { 5679 struct i40e_aq_desc desc; 5680 struct i40e_aqc_add_remove_cloud_filters *cmd = 5681 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5682 i40e_status status; 5683 u16 buff_len; 5684 int i; 5685 5686 i40e_fill_default_direct_cmd_desc(&desc, 5687 i40e_aqc_opc_remove_cloud_filters); 5688 5689 buff_len = filter_count * sizeof(*filters); 5690 desc.datalen = cpu_to_le16(buff_len); 5691 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5692 cmd->num_filters = filter_count; 5693 cmd->seid = cpu_to_le16(seid); 5694 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5695 5696 for (i = 0; i < filter_count; i++) { 5697 u16 tnl_type; 5698 u32 ti; 5699 5700 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5701 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5702 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5703 5704 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5705 * one more byte further than normally used for Tenant ID in 5706 * other tunnel types. 5707 */ 5708 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5709 ti = le32_to_cpu(filters[i].element.tenant_id); 5710 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5711 } 5712 } 5713 5714 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5715 5716 return status; 5717 } 5718