1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include "i40e_virtchnl.h" 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_A: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 case I40E_DEV_ID_10G_BASE_T: 54 case I40E_DEV_ID_20G_KR2: 55 hw->mac.type = I40E_MAC_XL710; 56 break; 57 case I40E_DEV_ID_SFP_X722: 58 case I40E_DEV_ID_1G_BASE_T_X722: 59 case I40E_DEV_ID_10G_BASE_T_X722: 60 hw->mac.type = I40E_MAC_X722; 61 break; 62 case I40E_DEV_ID_X722_VF: 63 case I40E_DEV_ID_X722_VF_HV: 64 hw->mac.type = I40E_MAC_X722_VF; 65 break; 66 case I40E_DEV_ID_VF: 67 case I40E_DEV_ID_VF_HV: 68 hw->mac.type = I40E_MAC_VF; 69 break; 70 default: 71 hw->mac.type = I40E_MAC_GENERIC; 72 break; 73 } 74 } else { 75 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 76 } 77 78 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 79 hw->mac.type, status); 80 return status; 81 } 82 83 /** 84 * i40e_aq_str - convert AQ err code to a string 85 * @hw: pointer to the HW structure 86 * @aq_err: the AQ error code to convert 87 **/ 88 char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 89 { 90 switch (aq_err) { 91 case I40E_AQ_RC_OK: 92 return "OK"; 93 case I40E_AQ_RC_EPERM: 94 return "I40E_AQ_RC_EPERM"; 95 case I40E_AQ_RC_ENOENT: 96 return "I40E_AQ_RC_ENOENT"; 97 case I40E_AQ_RC_ESRCH: 98 return "I40E_AQ_RC_ESRCH"; 99 case I40E_AQ_RC_EINTR: 100 return "I40E_AQ_RC_EINTR"; 101 case I40E_AQ_RC_EIO: 102 return "I40E_AQ_RC_EIO"; 103 case I40E_AQ_RC_ENXIO: 104 return "I40E_AQ_RC_ENXIO"; 105 case I40E_AQ_RC_E2BIG: 106 return "I40E_AQ_RC_E2BIG"; 107 case I40E_AQ_RC_EAGAIN: 108 return "I40E_AQ_RC_EAGAIN"; 109 case I40E_AQ_RC_ENOMEM: 110 return "I40E_AQ_RC_ENOMEM"; 111 case I40E_AQ_RC_EACCES: 112 return "I40E_AQ_RC_EACCES"; 113 case I40E_AQ_RC_EFAULT: 114 return "I40E_AQ_RC_EFAULT"; 115 case I40E_AQ_RC_EBUSY: 116 return "I40E_AQ_RC_EBUSY"; 117 case I40E_AQ_RC_EEXIST: 118 return "I40E_AQ_RC_EEXIST"; 119 case I40E_AQ_RC_EINVAL: 120 return "I40E_AQ_RC_EINVAL"; 121 case I40E_AQ_RC_ENOTTY: 122 return "I40E_AQ_RC_ENOTTY"; 123 case I40E_AQ_RC_ENOSPC: 124 return "I40E_AQ_RC_ENOSPC"; 125 case I40E_AQ_RC_ENOSYS: 126 return "I40E_AQ_RC_ENOSYS"; 127 case I40E_AQ_RC_ERANGE: 128 return "I40E_AQ_RC_ERANGE"; 129 case I40E_AQ_RC_EFLUSHED: 130 return "I40E_AQ_RC_EFLUSHED"; 131 case I40E_AQ_RC_BAD_ADDR: 132 return "I40E_AQ_RC_BAD_ADDR"; 133 case I40E_AQ_RC_EMODE: 134 return "I40E_AQ_RC_EMODE"; 135 case I40E_AQ_RC_EFBIG: 136 return "I40E_AQ_RC_EFBIG"; 137 } 138 139 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 140 return hw->err_str; 141 } 142 143 /** 144 * i40e_stat_str - convert status err code to a string 145 * @hw: pointer to the HW structure 146 * @stat_err: the status error code to convert 147 **/ 148 char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 149 { 150 switch (stat_err) { 151 case 0: 152 return "OK"; 153 case I40E_ERR_NVM: 154 return "I40E_ERR_NVM"; 155 case I40E_ERR_NVM_CHECKSUM: 156 return "I40E_ERR_NVM_CHECKSUM"; 157 case I40E_ERR_PHY: 158 return "I40E_ERR_PHY"; 159 case I40E_ERR_CONFIG: 160 return "I40E_ERR_CONFIG"; 161 case I40E_ERR_PARAM: 162 return "I40E_ERR_PARAM"; 163 case I40E_ERR_MAC_TYPE: 164 return "I40E_ERR_MAC_TYPE"; 165 case I40E_ERR_UNKNOWN_PHY: 166 return "I40E_ERR_UNKNOWN_PHY"; 167 case I40E_ERR_LINK_SETUP: 168 return "I40E_ERR_LINK_SETUP"; 169 case I40E_ERR_ADAPTER_STOPPED: 170 return "I40E_ERR_ADAPTER_STOPPED"; 171 case I40E_ERR_INVALID_MAC_ADDR: 172 return "I40E_ERR_INVALID_MAC_ADDR"; 173 case I40E_ERR_DEVICE_NOT_SUPPORTED: 174 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 175 case I40E_ERR_MASTER_REQUESTS_PENDING: 176 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 177 case I40E_ERR_INVALID_LINK_SETTINGS: 178 return "I40E_ERR_INVALID_LINK_SETTINGS"; 179 case I40E_ERR_AUTONEG_NOT_COMPLETE: 180 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 181 case I40E_ERR_RESET_FAILED: 182 return "I40E_ERR_RESET_FAILED"; 183 case I40E_ERR_SWFW_SYNC: 184 return "I40E_ERR_SWFW_SYNC"; 185 case I40E_ERR_NO_AVAILABLE_VSI: 186 return "I40E_ERR_NO_AVAILABLE_VSI"; 187 case I40E_ERR_NO_MEMORY: 188 return "I40E_ERR_NO_MEMORY"; 189 case I40E_ERR_BAD_PTR: 190 return "I40E_ERR_BAD_PTR"; 191 case I40E_ERR_RING_FULL: 192 return "I40E_ERR_RING_FULL"; 193 case I40E_ERR_INVALID_PD_ID: 194 return "I40E_ERR_INVALID_PD_ID"; 195 case I40E_ERR_INVALID_QP_ID: 196 return "I40E_ERR_INVALID_QP_ID"; 197 case I40E_ERR_INVALID_CQ_ID: 198 return "I40E_ERR_INVALID_CQ_ID"; 199 case I40E_ERR_INVALID_CEQ_ID: 200 return "I40E_ERR_INVALID_CEQ_ID"; 201 case I40E_ERR_INVALID_AEQ_ID: 202 return "I40E_ERR_INVALID_AEQ_ID"; 203 case I40E_ERR_INVALID_SIZE: 204 return "I40E_ERR_INVALID_SIZE"; 205 case I40E_ERR_INVALID_ARP_INDEX: 206 return "I40E_ERR_INVALID_ARP_INDEX"; 207 case I40E_ERR_INVALID_FPM_FUNC_ID: 208 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 209 case I40E_ERR_QP_INVALID_MSG_SIZE: 210 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 211 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 212 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 213 case I40E_ERR_INVALID_FRAG_COUNT: 214 return "I40E_ERR_INVALID_FRAG_COUNT"; 215 case I40E_ERR_QUEUE_EMPTY: 216 return "I40E_ERR_QUEUE_EMPTY"; 217 case I40E_ERR_INVALID_ALIGNMENT: 218 return "I40E_ERR_INVALID_ALIGNMENT"; 219 case I40E_ERR_FLUSHED_QUEUE: 220 return "I40E_ERR_FLUSHED_QUEUE"; 221 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 222 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 223 case I40E_ERR_INVALID_IMM_DATA_SIZE: 224 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 225 case I40E_ERR_TIMEOUT: 226 return "I40E_ERR_TIMEOUT"; 227 case I40E_ERR_OPCODE_MISMATCH: 228 return "I40E_ERR_OPCODE_MISMATCH"; 229 case I40E_ERR_CQP_COMPL_ERROR: 230 return "I40E_ERR_CQP_COMPL_ERROR"; 231 case I40E_ERR_INVALID_VF_ID: 232 return "I40E_ERR_INVALID_VF_ID"; 233 case I40E_ERR_INVALID_HMCFN_ID: 234 return "I40E_ERR_INVALID_HMCFN_ID"; 235 case I40E_ERR_BACKING_PAGE_ERROR: 236 return "I40E_ERR_BACKING_PAGE_ERROR"; 237 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 238 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 239 case I40E_ERR_INVALID_PBLE_INDEX: 240 return "I40E_ERR_INVALID_PBLE_INDEX"; 241 case I40E_ERR_INVALID_SD_INDEX: 242 return "I40E_ERR_INVALID_SD_INDEX"; 243 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 244 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 245 case I40E_ERR_INVALID_SD_TYPE: 246 return "I40E_ERR_INVALID_SD_TYPE"; 247 case I40E_ERR_MEMCPY_FAILED: 248 return "I40E_ERR_MEMCPY_FAILED"; 249 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 250 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 251 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 252 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 253 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 254 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 255 case I40E_ERR_SRQ_ENABLED: 256 return "I40E_ERR_SRQ_ENABLED"; 257 case I40E_ERR_ADMIN_QUEUE_ERROR: 258 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 259 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 260 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 261 case I40E_ERR_BUF_TOO_SHORT: 262 return "I40E_ERR_BUF_TOO_SHORT"; 263 case I40E_ERR_ADMIN_QUEUE_FULL: 264 return "I40E_ERR_ADMIN_QUEUE_FULL"; 265 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 266 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 267 case I40E_ERR_BAD_IWARP_CQE: 268 return "I40E_ERR_BAD_IWARP_CQE"; 269 case I40E_ERR_NVM_BLANK_MODE: 270 return "I40E_ERR_NVM_BLANK_MODE"; 271 case I40E_ERR_NOT_IMPLEMENTED: 272 return "I40E_ERR_NOT_IMPLEMENTED"; 273 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 274 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 275 case I40E_ERR_DIAG_TEST_FAILED: 276 return "I40E_ERR_DIAG_TEST_FAILED"; 277 case I40E_ERR_NOT_READY: 278 return "I40E_ERR_NOT_READY"; 279 case I40E_NOT_SUPPORTED: 280 return "I40E_NOT_SUPPORTED"; 281 case I40E_ERR_FIRMWARE_API_VERSION: 282 return "I40E_ERR_FIRMWARE_API_VERSION"; 283 } 284 285 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 286 return hw->err_str; 287 } 288 289 /** 290 * i40e_debug_aq 291 * @hw: debug mask related to admin queue 292 * @mask: debug mask 293 * @desc: pointer to admin queue descriptor 294 * @buffer: pointer to command buffer 295 * @buf_len: max length of buffer 296 * 297 * Dumps debug log about adminq command with descriptor contents. 298 **/ 299 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 300 void *buffer, u16 buf_len) 301 { 302 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 303 u16 len = le16_to_cpu(aq_desc->datalen); 304 u8 *buf = (u8 *)buffer; 305 u16 i = 0; 306 307 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 308 return; 309 310 i40e_debug(hw, mask, 311 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 312 le16_to_cpu(aq_desc->opcode), 313 le16_to_cpu(aq_desc->flags), 314 le16_to_cpu(aq_desc->datalen), 315 le16_to_cpu(aq_desc->retval)); 316 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 317 le32_to_cpu(aq_desc->cookie_high), 318 le32_to_cpu(aq_desc->cookie_low)); 319 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 320 le32_to_cpu(aq_desc->params.internal.param0), 321 le32_to_cpu(aq_desc->params.internal.param1)); 322 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 323 le32_to_cpu(aq_desc->params.external.addr_high), 324 le32_to_cpu(aq_desc->params.external.addr_low)); 325 326 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 327 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 328 if (buf_len < len) 329 len = buf_len; 330 /* write the full 16-byte chunks */ 331 for (i = 0; i < (len - 16); i += 16) 332 i40e_debug(hw, mask, 333 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 334 i, buf[i], buf[i + 1], buf[i + 2], 335 buf[i + 3], buf[i + 4], buf[i + 5], 336 buf[i + 6], buf[i + 7], buf[i + 8], 337 buf[i + 9], buf[i + 10], buf[i + 11], 338 buf[i + 12], buf[i + 13], buf[i + 14], 339 buf[i + 15]); 340 /* write whatever's left over without overrunning the buffer */ 341 if (i < len) { 342 char d_buf[80]; 343 int j = 0; 344 345 memset(d_buf, 0, sizeof(d_buf)); 346 j += sprintf(d_buf, "\t0x%04X ", i); 347 while (i < len) 348 j += sprintf(&d_buf[j], " %02X", buf[i++]); 349 i40e_debug(hw, mask, "%s\n", d_buf); 350 } 351 } 352 } 353 354 /** 355 * i40e_check_asq_alive 356 * @hw: pointer to the hw struct 357 * 358 * Returns true if Queue is enabled else false. 359 **/ 360 bool i40e_check_asq_alive(struct i40e_hw *hw) 361 { 362 if (hw->aq.asq.len) 363 return !!(rd32(hw, hw->aq.asq.len) & 364 I40E_PF_ATQLEN_ATQENABLE_MASK); 365 else 366 return false; 367 } 368 369 /** 370 * i40e_aq_queue_shutdown 371 * @hw: pointer to the hw struct 372 * @unloading: is the driver unloading itself 373 * 374 * Tell the Firmware that we're shutting down the AdminQ and whether 375 * or not the driver is unloading as well. 376 **/ 377 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 378 bool unloading) 379 { 380 struct i40e_aq_desc desc; 381 struct i40e_aqc_queue_shutdown *cmd = 382 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 383 i40e_status status; 384 385 i40e_fill_default_direct_cmd_desc(&desc, 386 i40e_aqc_opc_queue_shutdown); 387 388 if (unloading) 389 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 390 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 391 392 return status; 393 } 394 395 /** 396 * i40e_aq_get_set_rss_lut 397 * @hw: pointer to the hardware structure 398 * @vsi_id: vsi fw index 399 * @pf_lut: for PF table set true, for VSI table set false 400 * @lut: pointer to the lut buffer provided by the caller 401 * @lut_size: size of the lut buffer 402 * @set: set true to set the table, false to get the table 403 * 404 * Internal function to get or set RSS look up table 405 **/ 406 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 407 u16 vsi_id, bool pf_lut, 408 u8 *lut, u16 lut_size, 409 bool set) 410 { 411 i40e_status status; 412 struct i40e_aq_desc desc; 413 struct i40e_aqc_get_set_rss_lut *cmd_resp = 414 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 415 416 if (set) 417 i40e_fill_default_direct_cmd_desc(&desc, 418 i40e_aqc_opc_set_rss_lut); 419 else 420 i40e_fill_default_direct_cmd_desc(&desc, 421 i40e_aqc_opc_get_rss_lut); 422 423 /* Indirect command */ 424 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 425 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 426 427 cmd_resp->vsi_id = 428 cpu_to_le16((u16)((vsi_id << 429 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 430 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 431 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 432 433 if (pf_lut) 434 cmd_resp->flags |= cpu_to_le16((u16) 435 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 436 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 437 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 438 else 439 cmd_resp->flags |= cpu_to_le16((u16) 440 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 441 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 442 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 443 444 cmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)lut)); 445 cmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)lut)); 446 447 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 448 449 return status; 450 } 451 452 /** 453 * i40e_aq_get_rss_lut 454 * @hw: pointer to the hardware structure 455 * @vsi_id: vsi fw index 456 * @pf_lut: for PF table set true, for VSI table set false 457 * @lut: pointer to the lut buffer provided by the caller 458 * @lut_size: size of the lut buffer 459 * 460 * get the RSS lookup table, PF or VSI type 461 **/ 462 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 463 bool pf_lut, u8 *lut, u16 lut_size) 464 { 465 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 466 false); 467 } 468 469 /** 470 * i40e_aq_set_rss_lut 471 * @hw: pointer to the hardware structure 472 * @vsi_id: vsi fw index 473 * @pf_lut: for PF table set true, for VSI table set false 474 * @lut: pointer to the lut buffer provided by the caller 475 * @lut_size: size of the lut buffer 476 * 477 * set the RSS lookup table, PF or VSI type 478 **/ 479 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 480 bool pf_lut, u8 *lut, u16 lut_size) 481 { 482 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 483 } 484 485 /** 486 * i40e_aq_get_set_rss_key 487 * @hw: pointer to the hw struct 488 * @vsi_id: vsi fw index 489 * @key: pointer to key info struct 490 * @set: set true to set the key, false to get the key 491 * 492 * get the RSS key per VSI 493 **/ 494 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 495 u16 vsi_id, 496 struct i40e_aqc_get_set_rss_key_data *key, 497 bool set) 498 { 499 i40e_status status; 500 struct i40e_aq_desc desc; 501 struct i40e_aqc_get_set_rss_key *cmd_resp = 502 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 503 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 504 505 if (set) 506 i40e_fill_default_direct_cmd_desc(&desc, 507 i40e_aqc_opc_set_rss_key); 508 else 509 i40e_fill_default_direct_cmd_desc(&desc, 510 i40e_aqc_opc_get_rss_key); 511 512 /* Indirect command */ 513 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 514 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 515 516 cmd_resp->vsi_id = 517 cpu_to_le16((u16)((vsi_id << 518 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 519 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 520 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 521 cmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)key)); 522 cmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)key)); 523 524 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 525 526 return status; 527 } 528 529 /** 530 * i40e_aq_get_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 **/ 536 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 537 u16 vsi_id, 538 struct i40e_aqc_get_set_rss_key_data *key) 539 { 540 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 541 } 542 543 /** 544 * i40e_aq_set_rss_key 545 * @hw: pointer to the hw struct 546 * @vsi_id: vsi fw index 547 * @key: pointer to key info struct 548 * 549 * set the RSS key per VSI 550 **/ 551 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 552 u16 vsi_id, 553 struct i40e_aqc_get_set_rss_key_data *key) 554 { 555 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 556 } 557 558 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 559 * hardware to a bit-field that can be used by SW to more easily determine the 560 * packet type. 561 * 562 * Macros are used to shorten the table lines and make this table human 563 * readable. 564 * 565 * We store the PTYPE in the top byte of the bit field - this is just so that 566 * we can check that the table doesn't have a row missing, as the index into 567 * the table should be the PTYPE. 568 * 569 * Typical work flow: 570 * 571 * IF NOT i40e_ptype_lookup[ptype].known 572 * THEN 573 * Packet is unknown 574 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 575 * Use the rest of the fields to look at the tunnels, inner protocols, etc 576 * ELSE 577 * Use the enum i40e_rx_l2_ptype to decode the packet type 578 * ENDIF 579 */ 580 581 /* macro to make the table lines short */ 582 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 583 { PTYPE, \ 584 1, \ 585 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 586 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 587 I40E_RX_PTYPE_##OUTER_FRAG, \ 588 I40E_RX_PTYPE_TUNNEL_##T, \ 589 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 590 I40E_RX_PTYPE_##TEF, \ 591 I40E_RX_PTYPE_INNER_PROT_##I, \ 592 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 593 594 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 595 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 596 597 /* shorter macros makes the table fit but are terse */ 598 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 599 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 600 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 601 602 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 603 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 604 /* L2 Packet types */ 605 I40E_PTT_UNUSED_ENTRY(0), 606 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 607 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 608 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 609 I40E_PTT_UNUSED_ENTRY(4), 610 I40E_PTT_UNUSED_ENTRY(5), 611 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 612 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 613 I40E_PTT_UNUSED_ENTRY(8), 614 I40E_PTT_UNUSED_ENTRY(9), 615 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 616 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 617 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 618 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 619 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 620 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 621 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 622 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 623 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 624 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 625 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 626 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 627 628 /* Non Tunneled IPv4 */ 629 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 632 I40E_PTT_UNUSED_ENTRY(25), 633 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 634 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 635 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 636 637 /* IPv4 --> IPv4 */ 638 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 639 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 640 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 641 I40E_PTT_UNUSED_ENTRY(32), 642 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 643 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 644 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 645 646 /* IPv4 --> IPv6 */ 647 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 648 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 649 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 650 I40E_PTT_UNUSED_ENTRY(39), 651 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 652 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 653 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 654 655 /* IPv4 --> GRE/NAT */ 656 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 657 658 /* IPv4 --> GRE/NAT --> IPv4 */ 659 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 660 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 661 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 662 I40E_PTT_UNUSED_ENTRY(47), 663 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 664 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 665 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 666 667 /* IPv4 --> GRE/NAT --> IPv6 */ 668 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 669 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 670 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 671 I40E_PTT_UNUSED_ENTRY(54), 672 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 673 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 674 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 675 676 /* IPv4 --> GRE/NAT --> MAC */ 677 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 678 679 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 680 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 681 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 682 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 683 I40E_PTT_UNUSED_ENTRY(62), 684 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 685 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 686 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 687 688 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 689 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 690 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 691 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 692 I40E_PTT_UNUSED_ENTRY(69), 693 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 694 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 695 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 696 697 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 698 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 699 700 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 701 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 702 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 703 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 704 I40E_PTT_UNUSED_ENTRY(77), 705 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 706 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 707 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 708 709 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 710 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 711 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 712 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 713 I40E_PTT_UNUSED_ENTRY(84), 714 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 715 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 716 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 717 718 /* Non Tunneled IPv6 */ 719 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 720 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 721 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 722 I40E_PTT_UNUSED_ENTRY(91), 723 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 724 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 725 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 726 727 /* IPv6 --> IPv4 */ 728 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 729 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 730 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 731 I40E_PTT_UNUSED_ENTRY(98), 732 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 733 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 734 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 735 736 /* IPv6 --> IPv6 */ 737 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 738 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 739 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 740 I40E_PTT_UNUSED_ENTRY(105), 741 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 742 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 743 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 744 745 /* IPv6 --> GRE/NAT */ 746 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 747 748 /* IPv6 --> GRE/NAT -> IPv4 */ 749 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 750 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 751 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 752 I40E_PTT_UNUSED_ENTRY(113), 753 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 754 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 755 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 756 757 /* IPv6 --> GRE/NAT -> IPv6 */ 758 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 759 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 760 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 761 I40E_PTT_UNUSED_ENTRY(120), 762 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 763 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 764 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 765 766 /* IPv6 --> GRE/NAT -> MAC */ 767 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 768 769 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 770 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 771 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 772 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 773 I40E_PTT_UNUSED_ENTRY(128), 774 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 775 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 776 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 777 778 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 779 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 780 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 781 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 782 I40E_PTT_UNUSED_ENTRY(135), 783 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 784 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 785 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 786 787 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 788 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 789 790 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 791 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 792 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 793 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 794 I40E_PTT_UNUSED_ENTRY(143), 795 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 796 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 797 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 798 799 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 800 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 801 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 802 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 803 I40E_PTT_UNUSED_ENTRY(150), 804 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 805 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 806 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 807 808 /* unused entries */ 809 I40E_PTT_UNUSED_ENTRY(154), 810 I40E_PTT_UNUSED_ENTRY(155), 811 I40E_PTT_UNUSED_ENTRY(156), 812 I40E_PTT_UNUSED_ENTRY(157), 813 I40E_PTT_UNUSED_ENTRY(158), 814 I40E_PTT_UNUSED_ENTRY(159), 815 816 I40E_PTT_UNUSED_ENTRY(160), 817 I40E_PTT_UNUSED_ENTRY(161), 818 I40E_PTT_UNUSED_ENTRY(162), 819 I40E_PTT_UNUSED_ENTRY(163), 820 I40E_PTT_UNUSED_ENTRY(164), 821 I40E_PTT_UNUSED_ENTRY(165), 822 I40E_PTT_UNUSED_ENTRY(166), 823 I40E_PTT_UNUSED_ENTRY(167), 824 I40E_PTT_UNUSED_ENTRY(168), 825 I40E_PTT_UNUSED_ENTRY(169), 826 827 I40E_PTT_UNUSED_ENTRY(170), 828 I40E_PTT_UNUSED_ENTRY(171), 829 I40E_PTT_UNUSED_ENTRY(172), 830 I40E_PTT_UNUSED_ENTRY(173), 831 I40E_PTT_UNUSED_ENTRY(174), 832 I40E_PTT_UNUSED_ENTRY(175), 833 I40E_PTT_UNUSED_ENTRY(176), 834 I40E_PTT_UNUSED_ENTRY(177), 835 I40E_PTT_UNUSED_ENTRY(178), 836 I40E_PTT_UNUSED_ENTRY(179), 837 838 I40E_PTT_UNUSED_ENTRY(180), 839 I40E_PTT_UNUSED_ENTRY(181), 840 I40E_PTT_UNUSED_ENTRY(182), 841 I40E_PTT_UNUSED_ENTRY(183), 842 I40E_PTT_UNUSED_ENTRY(184), 843 I40E_PTT_UNUSED_ENTRY(185), 844 I40E_PTT_UNUSED_ENTRY(186), 845 I40E_PTT_UNUSED_ENTRY(187), 846 I40E_PTT_UNUSED_ENTRY(188), 847 I40E_PTT_UNUSED_ENTRY(189), 848 849 I40E_PTT_UNUSED_ENTRY(190), 850 I40E_PTT_UNUSED_ENTRY(191), 851 I40E_PTT_UNUSED_ENTRY(192), 852 I40E_PTT_UNUSED_ENTRY(193), 853 I40E_PTT_UNUSED_ENTRY(194), 854 I40E_PTT_UNUSED_ENTRY(195), 855 I40E_PTT_UNUSED_ENTRY(196), 856 I40E_PTT_UNUSED_ENTRY(197), 857 I40E_PTT_UNUSED_ENTRY(198), 858 I40E_PTT_UNUSED_ENTRY(199), 859 860 I40E_PTT_UNUSED_ENTRY(200), 861 I40E_PTT_UNUSED_ENTRY(201), 862 I40E_PTT_UNUSED_ENTRY(202), 863 I40E_PTT_UNUSED_ENTRY(203), 864 I40E_PTT_UNUSED_ENTRY(204), 865 I40E_PTT_UNUSED_ENTRY(205), 866 I40E_PTT_UNUSED_ENTRY(206), 867 I40E_PTT_UNUSED_ENTRY(207), 868 I40E_PTT_UNUSED_ENTRY(208), 869 I40E_PTT_UNUSED_ENTRY(209), 870 871 I40E_PTT_UNUSED_ENTRY(210), 872 I40E_PTT_UNUSED_ENTRY(211), 873 I40E_PTT_UNUSED_ENTRY(212), 874 I40E_PTT_UNUSED_ENTRY(213), 875 I40E_PTT_UNUSED_ENTRY(214), 876 I40E_PTT_UNUSED_ENTRY(215), 877 I40E_PTT_UNUSED_ENTRY(216), 878 I40E_PTT_UNUSED_ENTRY(217), 879 I40E_PTT_UNUSED_ENTRY(218), 880 I40E_PTT_UNUSED_ENTRY(219), 881 882 I40E_PTT_UNUSED_ENTRY(220), 883 I40E_PTT_UNUSED_ENTRY(221), 884 I40E_PTT_UNUSED_ENTRY(222), 885 I40E_PTT_UNUSED_ENTRY(223), 886 I40E_PTT_UNUSED_ENTRY(224), 887 I40E_PTT_UNUSED_ENTRY(225), 888 I40E_PTT_UNUSED_ENTRY(226), 889 I40E_PTT_UNUSED_ENTRY(227), 890 I40E_PTT_UNUSED_ENTRY(228), 891 I40E_PTT_UNUSED_ENTRY(229), 892 893 I40E_PTT_UNUSED_ENTRY(230), 894 I40E_PTT_UNUSED_ENTRY(231), 895 I40E_PTT_UNUSED_ENTRY(232), 896 I40E_PTT_UNUSED_ENTRY(233), 897 I40E_PTT_UNUSED_ENTRY(234), 898 I40E_PTT_UNUSED_ENTRY(235), 899 I40E_PTT_UNUSED_ENTRY(236), 900 I40E_PTT_UNUSED_ENTRY(237), 901 I40E_PTT_UNUSED_ENTRY(238), 902 I40E_PTT_UNUSED_ENTRY(239), 903 904 I40E_PTT_UNUSED_ENTRY(240), 905 I40E_PTT_UNUSED_ENTRY(241), 906 I40E_PTT_UNUSED_ENTRY(242), 907 I40E_PTT_UNUSED_ENTRY(243), 908 I40E_PTT_UNUSED_ENTRY(244), 909 I40E_PTT_UNUSED_ENTRY(245), 910 I40E_PTT_UNUSED_ENTRY(246), 911 I40E_PTT_UNUSED_ENTRY(247), 912 I40E_PTT_UNUSED_ENTRY(248), 913 I40E_PTT_UNUSED_ENTRY(249), 914 915 I40E_PTT_UNUSED_ENTRY(250), 916 I40E_PTT_UNUSED_ENTRY(251), 917 I40E_PTT_UNUSED_ENTRY(252), 918 I40E_PTT_UNUSED_ENTRY(253), 919 I40E_PTT_UNUSED_ENTRY(254), 920 I40E_PTT_UNUSED_ENTRY(255) 921 }; 922 923 /** 924 * i40e_init_shared_code - Initialize the shared code 925 * @hw: pointer to hardware structure 926 * 927 * This assigns the MAC type and PHY code and inits the NVM. 928 * Does not touch the hardware. This function must be called prior to any 929 * other function in the shared code. The i40e_hw structure should be 930 * memset to 0 prior to calling this function. The following fields in 931 * hw structure should be filled in prior to calling this function: 932 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 933 * subsystem_vendor_id, and revision_id 934 **/ 935 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 936 { 937 i40e_status status = 0; 938 u32 port, ari, func_rid; 939 940 i40e_set_mac_type(hw); 941 942 switch (hw->mac.type) { 943 case I40E_MAC_XL710: 944 case I40E_MAC_X722: 945 break; 946 default: 947 return I40E_ERR_DEVICE_NOT_SUPPORTED; 948 } 949 950 hw->phy.get_link_info = true; 951 952 /* Determine port number and PF number*/ 953 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 954 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 955 hw->port = (u8)port; 956 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 957 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 958 func_rid = rd32(hw, I40E_PF_FUNC_RID); 959 if (ari) 960 hw->pf_id = (u8)(func_rid & 0xff); 961 else 962 hw->pf_id = (u8)(func_rid & 0x7); 963 964 status = i40e_init_nvm(hw); 965 return status; 966 } 967 968 /** 969 * i40e_aq_mac_address_read - Retrieve the MAC addresses 970 * @hw: pointer to the hw struct 971 * @flags: a return indicator of what addresses were added to the addr store 972 * @addrs: the requestor's mac addr store 973 * @cmd_details: pointer to command details structure or NULL 974 **/ 975 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 976 u16 *flags, 977 struct i40e_aqc_mac_address_read_data *addrs, 978 struct i40e_asq_cmd_details *cmd_details) 979 { 980 struct i40e_aq_desc desc; 981 struct i40e_aqc_mac_address_read *cmd_data = 982 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 983 i40e_status status; 984 985 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 986 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 987 988 status = i40e_asq_send_command(hw, &desc, addrs, 989 sizeof(*addrs), cmd_details); 990 *flags = le16_to_cpu(cmd_data->command_flags); 991 992 return status; 993 } 994 995 /** 996 * i40e_aq_mac_address_write - Change the MAC addresses 997 * @hw: pointer to the hw struct 998 * @flags: indicates which MAC to be written 999 * @mac_addr: address to write 1000 * @cmd_details: pointer to command details structure or NULL 1001 **/ 1002 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 1003 u16 flags, u8 *mac_addr, 1004 struct i40e_asq_cmd_details *cmd_details) 1005 { 1006 struct i40e_aq_desc desc; 1007 struct i40e_aqc_mac_address_write *cmd_data = 1008 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1009 i40e_status status; 1010 1011 i40e_fill_default_direct_cmd_desc(&desc, 1012 i40e_aqc_opc_mac_address_write); 1013 cmd_data->command_flags = cpu_to_le16(flags); 1014 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1015 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1016 ((u32)mac_addr[3] << 16) | 1017 ((u32)mac_addr[4] << 8) | 1018 mac_addr[5]); 1019 1020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1021 1022 return status; 1023 } 1024 1025 /** 1026 * i40e_get_mac_addr - get MAC address 1027 * @hw: pointer to the HW structure 1028 * @mac_addr: pointer to MAC address 1029 * 1030 * Reads the adapter's MAC address from register 1031 **/ 1032 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1033 { 1034 struct i40e_aqc_mac_address_read_data addrs; 1035 i40e_status status; 1036 u16 flags = 0; 1037 1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1039 1040 if (flags & I40E_AQC_LAN_ADDR_VALID) 1041 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 1042 1043 return status; 1044 } 1045 1046 /** 1047 * i40e_get_port_mac_addr - get Port MAC address 1048 * @hw: pointer to the HW structure 1049 * @mac_addr: pointer to Port MAC address 1050 * 1051 * Reads the adapter's Port MAC address 1052 **/ 1053 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1054 { 1055 struct i40e_aqc_mac_address_read_data addrs; 1056 i40e_status status; 1057 u16 flags = 0; 1058 1059 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1060 if (status) 1061 return status; 1062 1063 if (flags & I40E_AQC_PORT_ADDR_VALID) 1064 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 1065 else 1066 status = I40E_ERR_INVALID_MAC_ADDR; 1067 1068 return status; 1069 } 1070 1071 /** 1072 * i40e_pre_tx_queue_cfg - pre tx queue configure 1073 * @hw: pointer to the HW structure 1074 * @queue: target PF queue index 1075 * @enable: state change request 1076 * 1077 * Handles hw requirement to indicate intention to enable 1078 * or disable target queue. 1079 **/ 1080 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1081 { 1082 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1083 u32 reg_block = 0; 1084 u32 reg_val; 1085 1086 if (abs_queue_idx >= 128) { 1087 reg_block = abs_queue_idx / 128; 1088 abs_queue_idx %= 128; 1089 } 1090 1091 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1092 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1093 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1094 1095 if (enable) 1096 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1097 else 1098 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1099 1100 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1101 } 1102 #ifdef I40E_FCOE 1103 1104 /** 1105 * i40e_get_san_mac_addr - get SAN MAC address 1106 * @hw: pointer to the HW structure 1107 * @mac_addr: pointer to SAN MAC address 1108 * 1109 * Reads the adapter's SAN MAC address from NVM 1110 **/ 1111 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1112 { 1113 struct i40e_aqc_mac_address_read_data addrs; 1114 i40e_status status; 1115 u16 flags = 0; 1116 1117 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1118 if (status) 1119 return status; 1120 1121 if (flags & I40E_AQC_SAN_ADDR_VALID) 1122 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac)); 1123 else 1124 status = I40E_ERR_INVALID_MAC_ADDR; 1125 1126 return status; 1127 } 1128 #endif 1129 1130 /** 1131 * i40e_read_pba_string - Reads part number string from EEPROM 1132 * @hw: pointer to hardware structure 1133 * @pba_num: stores the part number string from the EEPROM 1134 * @pba_num_size: part number string buffer length 1135 * 1136 * Reads the part number string from the EEPROM. 1137 **/ 1138 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1139 u32 pba_num_size) 1140 { 1141 i40e_status status = 0; 1142 u16 pba_word = 0; 1143 u16 pba_size = 0; 1144 u16 pba_ptr = 0; 1145 u16 i = 0; 1146 1147 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1148 if (status || (pba_word != 0xFAFA)) { 1149 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1150 return status; 1151 } 1152 1153 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1154 if (status) { 1155 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1156 return status; 1157 } 1158 1159 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1160 if (status) { 1161 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1162 return status; 1163 } 1164 1165 /* Subtract one to get PBA word count (PBA Size word is included in 1166 * total size) 1167 */ 1168 pba_size--; 1169 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1170 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1171 return I40E_ERR_PARAM; 1172 } 1173 1174 for (i = 0; i < pba_size; i++) { 1175 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1176 if (status) { 1177 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1178 return status; 1179 } 1180 1181 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1182 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1183 } 1184 pba_num[(pba_size * 2)] = '\0'; 1185 1186 return status; 1187 } 1188 1189 /** 1190 * i40e_get_media_type - Gets media type 1191 * @hw: pointer to the hardware structure 1192 **/ 1193 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1194 { 1195 enum i40e_media_type media; 1196 1197 switch (hw->phy.link_info.phy_type) { 1198 case I40E_PHY_TYPE_10GBASE_SR: 1199 case I40E_PHY_TYPE_10GBASE_LR: 1200 case I40E_PHY_TYPE_1000BASE_SX: 1201 case I40E_PHY_TYPE_1000BASE_LX: 1202 case I40E_PHY_TYPE_40GBASE_SR4: 1203 case I40E_PHY_TYPE_40GBASE_LR4: 1204 media = I40E_MEDIA_TYPE_FIBER; 1205 break; 1206 case I40E_PHY_TYPE_100BASE_TX: 1207 case I40E_PHY_TYPE_1000BASE_T: 1208 case I40E_PHY_TYPE_10GBASE_T: 1209 media = I40E_MEDIA_TYPE_BASET; 1210 break; 1211 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1212 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1213 case I40E_PHY_TYPE_10GBASE_CR1: 1214 case I40E_PHY_TYPE_40GBASE_CR4: 1215 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1216 case I40E_PHY_TYPE_40GBASE_AOC: 1217 case I40E_PHY_TYPE_10GBASE_AOC: 1218 media = I40E_MEDIA_TYPE_DA; 1219 break; 1220 case I40E_PHY_TYPE_1000BASE_KX: 1221 case I40E_PHY_TYPE_10GBASE_KX4: 1222 case I40E_PHY_TYPE_10GBASE_KR: 1223 case I40E_PHY_TYPE_40GBASE_KR4: 1224 case I40E_PHY_TYPE_20GBASE_KR2: 1225 media = I40E_MEDIA_TYPE_BACKPLANE; 1226 break; 1227 case I40E_PHY_TYPE_SGMII: 1228 case I40E_PHY_TYPE_XAUI: 1229 case I40E_PHY_TYPE_XFI: 1230 case I40E_PHY_TYPE_XLAUI: 1231 case I40E_PHY_TYPE_XLPPI: 1232 default: 1233 media = I40E_MEDIA_TYPE_UNKNOWN; 1234 break; 1235 } 1236 1237 return media; 1238 } 1239 1240 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1241 #define I40E_PF_RESET_WAIT_COUNT 200 1242 /** 1243 * i40e_pf_reset - Reset the PF 1244 * @hw: pointer to the hardware structure 1245 * 1246 * Assuming someone else has triggered a global reset, 1247 * assure the global reset is complete and then reset the PF 1248 **/ 1249 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1250 { 1251 u32 cnt = 0; 1252 u32 cnt1 = 0; 1253 u32 reg = 0; 1254 u32 grst_del; 1255 1256 /* Poll for Global Reset steady state in case of recent GRST. 1257 * The grst delay value is in 100ms units, and we'll wait a 1258 * couple counts longer to be sure we don't just miss the end. 1259 */ 1260 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1261 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1262 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1263 for (cnt = 0; cnt < grst_del + 2; cnt++) { 1264 reg = rd32(hw, I40E_GLGEN_RSTAT); 1265 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1266 break; 1267 msleep(100); 1268 } 1269 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1270 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1271 return I40E_ERR_RESET_FAILED; 1272 } 1273 1274 /* Now Wait for the FW to be ready */ 1275 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1276 reg = rd32(hw, I40E_GLNVM_ULD); 1277 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1278 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1279 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1280 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1281 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1282 break; 1283 } 1284 usleep_range(10000, 20000); 1285 } 1286 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1287 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1288 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1289 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1290 return I40E_ERR_RESET_FAILED; 1291 } 1292 1293 /* If there was a Global Reset in progress when we got here, 1294 * we don't need to do the PF Reset 1295 */ 1296 if (!cnt) { 1297 if (hw->revision_id == 0) 1298 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1299 else 1300 cnt = I40E_PF_RESET_WAIT_COUNT; 1301 reg = rd32(hw, I40E_PFGEN_CTRL); 1302 wr32(hw, I40E_PFGEN_CTRL, 1303 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1304 for (; cnt; cnt--) { 1305 reg = rd32(hw, I40E_PFGEN_CTRL); 1306 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1307 break; 1308 usleep_range(1000, 2000); 1309 } 1310 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1311 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1312 return I40E_ERR_RESET_FAILED; 1313 } 1314 } 1315 1316 i40e_clear_pxe_mode(hw); 1317 1318 return 0; 1319 } 1320 1321 /** 1322 * i40e_clear_hw - clear out any left over hw state 1323 * @hw: pointer to the hw struct 1324 * 1325 * Clear queues and interrupts, typically called at init time, 1326 * but after the capabilities have been found so we know how many 1327 * queues and msix vectors have been allocated. 1328 **/ 1329 void i40e_clear_hw(struct i40e_hw *hw) 1330 { 1331 u32 num_queues, base_queue; 1332 u32 num_pf_int; 1333 u32 num_vf_int; 1334 u32 num_vfs; 1335 u32 i, j; 1336 u32 val; 1337 u32 eol = 0x7ff; 1338 1339 /* get number of interrupts, queues, and VFs */ 1340 val = rd32(hw, I40E_GLPCI_CNF2); 1341 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1342 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1343 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1344 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1345 1346 val = rd32(hw, I40E_PFLAN_QALLOC); 1347 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1348 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1349 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1350 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1351 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1352 num_queues = (j - base_queue) + 1; 1353 else 1354 num_queues = 0; 1355 1356 val = rd32(hw, I40E_PF_VT_PFALLOC); 1357 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1358 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1359 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1360 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1361 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1362 num_vfs = (j - i) + 1; 1363 else 1364 num_vfs = 0; 1365 1366 /* stop all the interrupts */ 1367 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1368 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1369 for (i = 0; i < num_pf_int - 2; i++) 1370 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1371 1372 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1373 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1374 wr32(hw, I40E_PFINT_LNKLST0, val); 1375 for (i = 0; i < num_pf_int - 2; i++) 1376 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1377 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1378 for (i = 0; i < num_vfs; i++) 1379 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1380 for (i = 0; i < num_vf_int - 2; i++) 1381 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1382 1383 /* warn the HW of the coming Tx disables */ 1384 for (i = 0; i < num_queues; i++) { 1385 u32 abs_queue_idx = base_queue + i; 1386 u32 reg_block = 0; 1387 1388 if (abs_queue_idx >= 128) { 1389 reg_block = abs_queue_idx / 128; 1390 abs_queue_idx %= 128; 1391 } 1392 1393 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1394 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1395 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1396 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1397 1398 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1399 } 1400 udelay(400); 1401 1402 /* stop all the queues */ 1403 for (i = 0; i < num_queues; i++) { 1404 wr32(hw, I40E_QINT_TQCTL(i), 0); 1405 wr32(hw, I40E_QTX_ENA(i), 0); 1406 wr32(hw, I40E_QINT_RQCTL(i), 0); 1407 wr32(hw, I40E_QRX_ENA(i), 0); 1408 } 1409 1410 /* short wait for all queue disables to settle */ 1411 udelay(50); 1412 } 1413 1414 /** 1415 * i40e_clear_pxe_mode - clear pxe operations mode 1416 * @hw: pointer to the hw struct 1417 * 1418 * Make sure all PXE mode settings are cleared, including things 1419 * like descriptor fetch/write-back mode. 1420 **/ 1421 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1422 { 1423 u32 reg; 1424 1425 if (i40e_check_asq_alive(hw)) 1426 i40e_aq_clear_pxe_mode(hw, NULL); 1427 1428 /* Clear single descriptor fetch/write-back mode */ 1429 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1430 1431 if (hw->revision_id == 0) { 1432 /* As a work around clear PXE_MODE instead of setting it */ 1433 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1434 } else { 1435 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1436 } 1437 } 1438 1439 /** 1440 * i40e_led_is_mine - helper to find matching led 1441 * @hw: pointer to the hw struct 1442 * @idx: index into GPIO registers 1443 * 1444 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1445 */ 1446 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1447 { 1448 u32 gpio_val = 0; 1449 u32 port; 1450 1451 if (!hw->func_caps.led[idx]) 1452 return 0; 1453 1454 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1455 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1456 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1457 1458 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1459 * if it is not our port then ignore 1460 */ 1461 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1462 (port != hw->port)) 1463 return 0; 1464 1465 return gpio_val; 1466 } 1467 1468 #define I40E_COMBINED_ACTIVITY 0xA 1469 #define I40E_FILTER_ACTIVITY 0xE 1470 #define I40E_LINK_ACTIVITY 0xC 1471 #define I40E_MAC_ACTIVITY 0xD 1472 #define I40E_LED0 22 1473 1474 /** 1475 * i40e_led_get - return current on/off mode 1476 * @hw: pointer to the hw struct 1477 * 1478 * The value returned is the 'mode' field as defined in the 1479 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1480 * values are variations of possible behaviors relating to 1481 * blink, link, and wire. 1482 **/ 1483 u32 i40e_led_get(struct i40e_hw *hw) 1484 { 1485 u32 current_mode = 0; 1486 u32 mode = 0; 1487 int i; 1488 1489 /* as per the documentation GPIO 22-29 are the LED 1490 * GPIO pins named LED0..LED7 1491 */ 1492 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1493 u32 gpio_val = i40e_led_is_mine(hw, i); 1494 1495 if (!gpio_val) 1496 continue; 1497 1498 /* ignore gpio LED src mode entries related to the activity 1499 * LEDs 1500 */ 1501 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1502 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1503 switch (current_mode) { 1504 case I40E_COMBINED_ACTIVITY: 1505 case I40E_FILTER_ACTIVITY: 1506 case I40E_MAC_ACTIVITY: 1507 continue; 1508 default: 1509 break; 1510 } 1511 1512 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1513 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1514 break; 1515 } 1516 1517 return mode; 1518 } 1519 1520 /** 1521 * i40e_led_set - set new on/off mode 1522 * @hw: pointer to the hw struct 1523 * @mode: 0=off, 0xf=on (else see manual for mode details) 1524 * @blink: true if the LED should blink when on, false if steady 1525 * 1526 * if this function is used to turn on the blink it should 1527 * be used to disable the blink when restoring the original state. 1528 **/ 1529 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1530 { 1531 u32 current_mode = 0; 1532 int i; 1533 1534 if (mode & 0xfffffff0) 1535 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1536 1537 /* as per the documentation GPIO 22-29 are the LED 1538 * GPIO pins named LED0..LED7 1539 */ 1540 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1541 u32 gpio_val = i40e_led_is_mine(hw, i); 1542 1543 if (!gpio_val) 1544 continue; 1545 1546 /* ignore gpio LED src mode entries related to the activity 1547 * LEDs 1548 */ 1549 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1550 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1551 switch (current_mode) { 1552 case I40E_COMBINED_ACTIVITY: 1553 case I40E_FILTER_ACTIVITY: 1554 case I40E_MAC_ACTIVITY: 1555 continue; 1556 default: 1557 break; 1558 } 1559 1560 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1561 /* this & is a bit of paranoia, but serves as a range check */ 1562 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1563 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1564 1565 if (mode == I40E_LINK_ACTIVITY) 1566 blink = false; 1567 1568 if (blink) 1569 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1570 else 1571 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1572 1573 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1574 break; 1575 } 1576 } 1577 1578 /* Admin command wrappers */ 1579 1580 /** 1581 * i40e_aq_get_phy_capabilities 1582 * @hw: pointer to the hw struct 1583 * @abilities: structure for PHY capabilities to be filled 1584 * @qualified_modules: report Qualified Modules 1585 * @report_init: report init capabilities (active are default) 1586 * @cmd_details: pointer to command details structure or NULL 1587 * 1588 * Returns the various PHY abilities supported on the Port. 1589 **/ 1590 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1591 bool qualified_modules, bool report_init, 1592 struct i40e_aq_get_phy_abilities_resp *abilities, 1593 struct i40e_asq_cmd_details *cmd_details) 1594 { 1595 struct i40e_aq_desc desc; 1596 i40e_status status; 1597 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1598 1599 if (!abilities) 1600 return I40E_ERR_PARAM; 1601 1602 i40e_fill_default_direct_cmd_desc(&desc, 1603 i40e_aqc_opc_get_phy_abilities); 1604 1605 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1606 if (abilities_size > I40E_AQ_LARGE_BUF) 1607 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1608 1609 if (qualified_modules) 1610 desc.params.external.param0 |= 1611 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1612 1613 if (report_init) 1614 desc.params.external.param0 |= 1615 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1616 1617 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1618 cmd_details); 1619 1620 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1621 status = I40E_ERR_UNKNOWN_PHY; 1622 1623 return status; 1624 } 1625 1626 /** 1627 * i40e_aq_set_phy_config 1628 * @hw: pointer to the hw struct 1629 * @config: structure with PHY configuration to be set 1630 * @cmd_details: pointer to command details structure or NULL 1631 * 1632 * Set the various PHY configuration parameters 1633 * supported on the Port.One or more of the Set PHY config parameters may be 1634 * ignored in an MFP mode as the PF may not have the privilege to set some 1635 * of the PHY Config parameters. This status will be indicated by the 1636 * command response. 1637 **/ 1638 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1639 struct i40e_aq_set_phy_config *config, 1640 struct i40e_asq_cmd_details *cmd_details) 1641 { 1642 struct i40e_aq_desc desc; 1643 struct i40e_aq_set_phy_config *cmd = 1644 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1645 enum i40e_status_code status; 1646 1647 if (!config) 1648 return I40E_ERR_PARAM; 1649 1650 i40e_fill_default_direct_cmd_desc(&desc, 1651 i40e_aqc_opc_set_phy_config); 1652 1653 *cmd = *config; 1654 1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1656 1657 return status; 1658 } 1659 1660 /** 1661 * i40e_set_fc 1662 * @hw: pointer to the hw struct 1663 * 1664 * Set the requested flow control mode using set_phy_config. 1665 **/ 1666 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1667 bool atomic_restart) 1668 { 1669 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1670 struct i40e_aq_get_phy_abilities_resp abilities; 1671 struct i40e_aq_set_phy_config config; 1672 enum i40e_status_code status; 1673 u8 pause_mask = 0x0; 1674 1675 *aq_failures = 0x0; 1676 1677 switch (fc_mode) { 1678 case I40E_FC_FULL: 1679 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1680 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1681 break; 1682 case I40E_FC_RX_PAUSE: 1683 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1684 break; 1685 case I40E_FC_TX_PAUSE: 1686 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 /* Get the current phy config */ 1693 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1694 NULL); 1695 if (status) { 1696 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1697 return status; 1698 } 1699 1700 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1701 /* clear the old pause settings */ 1702 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1703 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1704 /* set the new abilities */ 1705 config.abilities |= pause_mask; 1706 /* If the abilities have changed, then set the new config */ 1707 if (config.abilities != abilities.abilities) { 1708 /* Auto restart link so settings take effect */ 1709 if (atomic_restart) 1710 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1711 /* Copy over all the old settings */ 1712 config.phy_type = abilities.phy_type; 1713 config.link_speed = abilities.link_speed; 1714 config.eee_capability = abilities.eee_capability; 1715 config.eeer = abilities.eeer_val; 1716 config.low_power_ctrl = abilities.d3_lpan; 1717 status = i40e_aq_set_phy_config(hw, &config, NULL); 1718 1719 if (status) 1720 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1721 } 1722 /* Update the link info */ 1723 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1724 if (status) { 1725 /* Wait a little bit (on 40G cards it sometimes takes a really 1726 * long time for link to come back from the atomic reset) 1727 * and try once more 1728 */ 1729 msleep(1000); 1730 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1731 } 1732 if (status) 1733 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1734 1735 return status; 1736 } 1737 1738 /** 1739 * i40e_aq_clear_pxe_mode 1740 * @hw: pointer to the hw struct 1741 * @cmd_details: pointer to command details structure or NULL 1742 * 1743 * Tell the firmware that the driver is taking over from PXE 1744 **/ 1745 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1746 struct i40e_asq_cmd_details *cmd_details) 1747 { 1748 i40e_status status; 1749 struct i40e_aq_desc desc; 1750 struct i40e_aqc_clear_pxe *cmd = 1751 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1752 1753 i40e_fill_default_direct_cmd_desc(&desc, 1754 i40e_aqc_opc_clear_pxe_mode); 1755 1756 cmd->rx_cnt = 0x2; 1757 1758 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1759 1760 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1761 1762 return status; 1763 } 1764 1765 /** 1766 * i40e_aq_set_link_restart_an 1767 * @hw: pointer to the hw struct 1768 * @enable_link: if true: enable link, if false: disable link 1769 * @cmd_details: pointer to command details structure or NULL 1770 * 1771 * Sets up the link and restarts the Auto-Negotiation over the link. 1772 **/ 1773 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1774 bool enable_link, 1775 struct i40e_asq_cmd_details *cmd_details) 1776 { 1777 struct i40e_aq_desc desc; 1778 struct i40e_aqc_set_link_restart_an *cmd = 1779 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1780 i40e_status status; 1781 1782 i40e_fill_default_direct_cmd_desc(&desc, 1783 i40e_aqc_opc_set_link_restart_an); 1784 1785 cmd->command = I40E_AQ_PHY_RESTART_AN; 1786 if (enable_link) 1787 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1788 else 1789 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1790 1791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1792 1793 return status; 1794 } 1795 1796 /** 1797 * i40e_aq_get_link_info 1798 * @hw: pointer to the hw struct 1799 * @enable_lse: enable/disable LinkStatusEvent reporting 1800 * @link: pointer to link status structure - optional 1801 * @cmd_details: pointer to command details structure or NULL 1802 * 1803 * Returns the link status of the adapter. 1804 **/ 1805 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1806 bool enable_lse, struct i40e_link_status *link, 1807 struct i40e_asq_cmd_details *cmd_details) 1808 { 1809 struct i40e_aq_desc desc; 1810 struct i40e_aqc_get_link_status *resp = 1811 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1812 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1813 i40e_status status; 1814 bool tx_pause, rx_pause; 1815 u16 command_flags; 1816 1817 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1818 1819 if (enable_lse) 1820 command_flags = I40E_AQ_LSE_ENABLE; 1821 else 1822 command_flags = I40E_AQ_LSE_DISABLE; 1823 resp->command_flags = cpu_to_le16(command_flags); 1824 1825 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1826 1827 if (status) 1828 goto aq_get_link_info_exit; 1829 1830 /* save off old link status information */ 1831 hw->phy.link_info_old = *hw_link_info; 1832 1833 /* update link status */ 1834 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1835 hw->phy.media_type = i40e_get_media_type(hw); 1836 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1837 hw_link_info->link_info = resp->link_info; 1838 hw_link_info->an_info = resp->an_info; 1839 hw_link_info->ext_info = resp->ext_info; 1840 hw_link_info->loopback = resp->loopback; 1841 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1842 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1843 1844 /* update fc info */ 1845 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1846 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1847 if (tx_pause & rx_pause) 1848 hw->fc.current_mode = I40E_FC_FULL; 1849 else if (tx_pause) 1850 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1851 else if (rx_pause) 1852 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1853 else 1854 hw->fc.current_mode = I40E_FC_NONE; 1855 1856 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1857 hw_link_info->crc_enable = true; 1858 else 1859 hw_link_info->crc_enable = false; 1860 1861 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1862 hw_link_info->lse_enable = true; 1863 else 1864 hw_link_info->lse_enable = false; 1865 1866 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1867 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1868 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1869 1870 /* save link status information */ 1871 if (link) 1872 *link = *hw_link_info; 1873 1874 /* flag cleared so helper functions don't call AQ again */ 1875 hw->phy.get_link_info = false; 1876 1877 aq_get_link_info_exit: 1878 return status; 1879 } 1880 1881 /** 1882 * i40e_aq_set_phy_int_mask 1883 * @hw: pointer to the hw struct 1884 * @mask: interrupt mask to be set 1885 * @cmd_details: pointer to command details structure or NULL 1886 * 1887 * Set link interrupt mask. 1888 **/ 1889 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1890 u16 mask, 1891 struct i40e_asq_cmd_details *cmd_details) 1892 { 1893 struct i40e_aq_desc desc; 1894 struct i40e_aqc_set_phy_int_mask *cmd = 1895 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1896 i40e_status status; 1897 1898 i40e_fill_default_direct_cmd_desc(&desc, 1899 i40e_aqc_opc_set_phy_int_mask); 1900 1901 cmd->event_mask = cpu_to_le16(mask); 1902 1903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1904 1905 return status; 1906 } 1907 1908 /** 1909 * i40e_aq_add_vsi 1910 * @hw: pointer to the hw struct 1911 * @vsi_ctx: pointer to a vsi context struct 1912 * @cmd_details: pointer to command details structure or NULL 1913 * 1914 * Add a VSI context to the hardware. 1915 **/ 1916 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1917 struct i40e_vsi_context *vsi_ctx, 1918 struct i40e_asq_cmd_details *cmd_details) 1919 { 1920 struct i40e_aq_desc desc; 1921 struct i40e_aqc_add_get_update_vsi *cmd = 1922 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1923 struct i40e_aqc_add_get_update_vsi_completion *resp = 1924 (struct i40e_aqc_add_get_update_vsi_completion *) 1925 &desc.params.raw; 1926 i40e_status status; 1927 1928 i40e_fill_default_direct_cmd_desc(&desc, 1929 i40e_aqc_opc_add_vsi); 1930 1931 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1932 cmd->connection_type = vsi_ctx->connection_type; 1933 cmd->vf_id = vsi_ctx->vf_num; 1934 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1935 1936 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1937 1938 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1939 sizeof(vsi_ctx->info), cmd_details); 1940 1941 if (status) 1942 goto aq_add_vsi_exit; 1943 1944 vsi_ctx->seid = le16_to_cpu(resp->seid); 1945 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1946 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1947 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1948 1949 aq_add_vsi_exit: 1950 return status; 1951 } 1952 1953 /** 1954 * i40e_aq_set_vsi_unicast_promiscuous 1955 * @hw: pointer to the hw struct 1956 * @seid: vsi number 1957 * @set: set unicast promiscuous enable/disable 1958 * @cmd_details: pointer to command details structure or NULL 1959 **/ 1960 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1961 u16 seid, bool set, 1962 struct i40e_asq_cmd_details *cmd_details) 1963 { 1964 struct i40e_aq_desc desc; 1965 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1966 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1967 i40e_status status; 1968 u16 flags = 0; 1969 1970 i40e_fill_default_direct_cmd_desc(&desc, 1971 i40e_aqc_opc_set_vsi_promiscuous_modes); 1972 1973 if (set) 1974 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1975 1976 cmd->promiscuous_flags = cpu_to_le16(flags); 1977 1978 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1979 1980 cmd->seid = cpu_to_le16(seid); 1981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1982 1983 return status; 1984 } 1985 1986 /** 1987 * i40e_aq_set_vsi_multicast_promiscuous 1988 * @hw: pointer to the hw struct 1989 * @seid: vsi number 1990 * @set: set multicast promiscuous enable/disable 1991 * @cmd_details: pointer to command details structure or NULL 1992 **/ 1993 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1994 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1995 { 1996 struct i40e_aq_desc desc; 1997 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1998 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1999 i40e_status status; 2000 u16 flags = 0; 2001 2002 i40e_fill_default_direct_cmd_desc(&desc, 2003 i40e_aqc_opc_set_vsi_promiscuous_modes); 2004 2005 if (set) 2006 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2007 2008 cmd->promiscuous_flags = cpu_to_le16(flags); 2009 2010 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2011 2012 cmd->seid = cpu_to_le16(seid); 2013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2014 2015 return status; 2016 } 2017 2018 /** 2019 * i40e_aq_set_vsi_broadcast 2020 * @hw: pointer to the hw struct 2021 * @seid: vsi number 2022 * @set_filter: true to set filter, false to clear filter 2023 * @cmd_details: pointer to command details structure or NULL 2024 * 2025 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2026 **/ 2027 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2028 u16 seid, bool set_filter, 2029 struct i40e_asq_cmd_details *cmd_details) 2030 { 2031 struct i40e_aq_desc desc; 2032 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2033 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2034 i40e_status status; 2035 2036 i40e_fill_default_direct_cmd_desc(&desc, 2037 i40e_aqc_opc_set_vsi_promiscuous_modes); 2038 2039 if (set_filter) 2040 cmd->promiscuous_flags 2041 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2042 else 2043 cmd->promiscuous_flags 2044 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2045 2046 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2047 cmd->seid = cpu_to_le16(seid); 2048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2049 2050 return status; 2051 } 2052 2053 /** 2054 * i40e_get_vsi_params - get VSI configuration info 2055 * @hw: pointer to the hw struct 2056 * @vsi_ctx: pointer to a vsi context struct 2057 * @cmd_details: pointer to command details structure or NULL 2058 **/ 2059 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2060 struct i40e_vsi_context *vsi_ctx, 2061 struct i40e_asq_cmd_details *cmd_details) 2062 { 2063 struct i40e_aq_desc desc; 2064 struct i40e_aqc_add_get_update_vsi *cmd = 2065 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2066 struct i40e_aqc_add_get_update_vsi_completion *resp = 2067 (struct i40e_aqc_add_get_update_vsi_completion *) 2068 &desc.params.raw; 2069 i40e_status status; 2070 2071 i40e_fill_default_direct_cmd_desc(&desc, 2072 i40e_aqc_opc_get_vsi_parameters); 2073 2074 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2075 2076 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2077 2078 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2079 sizeof(vsi_ctx->info), NULL); 2080 2081 if (status) 2082 goto aq_get_vsi_params_exit; 2083 2084 vsi_ctx->seid = le16_to_cpu(resp->seid); 2085 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2086 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2087 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2088 2089 aq_get_vsi_params_exit: 2090 return status; 2091 } 2092 2093 /** 2094 * i40e_aq_update_vsi_params 2095 * @hw: pointer to the hw struct 2096 * @vsi_ctx: pointer to a vsi context struct 2097 * @cmd_details: pointer to command details structure or NULL 2098 * 2099 * Update a VSI context. 2100 **/ 2101 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2102 struct i40e_vsi_context *vsi_ctx, 2103 struct i40e_asq_cmd_details *cmd_details) 2104 { 2105 struct i40e_aq_desc desc; 2106 struct i40e_aqc_add_get_update_vsi *cmd = 2107 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2108 i40e_status status; 2109 2110 i40e_fill_default_direct_cmd_desc(&desc, 2111 i40e_aqc_opc_update_vsi_parameters); 2112 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2113 2114 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2115 2116 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2117 sizeof(vsi_ctx->info), cmd_details); 2118 2119 return status; 2120 } 2121 2122 /** 2123 * i40e_aq_get_switch_config 2124 * @hw: pointer to the hardware structure 2125 * @buf: pointer to the result buffer 2126 * @buf_size: length of input buffer 2127 * @start_seid: seid to start for the report, 0 == beginning 2128 * @cmd_details: pointer to command details structure or NULL 2129 * 2130 * Fill the buf with switch configuration returned from AdminQ command 2131 **/ 2132 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2133 struct i40e_aqc_get_switch_config_resp *buf, 2134 u16 buf_size, u16 *start_seid, 2135 struct i40e_asq_cmd_details *cmd_details) 2136 { 2137 struct i40e_aq_desc desc; 2138 struct i40e_aqc_switch_seid *scfg = 2139 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2140 i40e_status status; 2141 2142 i40e_fill_default_direct_cmd_desc(&desc, 2143 i40e_aqc_opc_get_switch_config); 2144 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2145 if (buf_size > I40E_AQ_LARGE_BUF) 2146 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2147 scfg->seid = cpu_to_le16(*start_seid); 2148 2149 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2150 *start_seid = le16_to_cpu(scfg->seid); 2151 2152 return status; 2153 } 2154 2155 /** 2156 * i40e_aq_get_firmware_version 2157 * @hw: pointer to the hw struct 2158 * @fw_major_version: firmware major version 2159 * @fw_minor_version: firmware minor version 2160 * @fw_build: firmware build number 2161 * @api_major_version: major queue version 2162 * @api_minor_version: minor queue version 2163 * @cmd_details: pointer to command details structure or NULL 2164 * 2165 * Get the firmware version from the admin queue commands 2166 **/ 2167 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2168 u16 *fw_major_version, u16 *fw_minor_version, 2169 u32 *fw_build, 2170 u16 *api_major_version, u16 *api_minor_version, 2171 struct i40e_asq_cmd_details *cmd_details) 2172 { 2173 struct i40e_aq_desc desc; 2174 struct i40e_aqc_get_version *resp = 2175 (struct i40e_aqc_get_version *)&desc.params.raw; 2176 i40e_status status; 2177 2178 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2179 2180 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2181 2182 if (!status) { 2183 if (fw_major_version) 2184 *fw_major_version = le16_to_cpu(resp->fw_major); 2185 if (fw_minor_version) 2186 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2187 if (fw_build) 2188 *fw_build = le32_to_cpu(resp->fw_build); 2189 if (api_major_version) 2190 *api_major_version = le16_to_cpu(resp->api_major); 2191 if (api_minor_version) 2192 *api_minor_version = le16_to_cpu(resp->api_minor); 2193 } 2194 2195 return status; 2196 } 2197 2198 /** 2199 * i40e_aq_send_driver_version 2200 * @hw: pointer to the hw struct 2201 * @dv: driver's major, minor version 2202 * @cmd_details: pointer to command details structure or NULL 2203 * 2204 * Send the driver version to the firmware 2205 **/ 2206 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2207 struct i40e_driver_version *dv, 2208 struct i40e_asq_cmd_details *cmd_details) 2209 { 2210 struct i40e_aq_desc desc; 2211 struct i40e_aqc_driver_version *cmd = 2212 (struct i40e_aqc_driver_version *)&desc.params.raw; 2213 i40e_status status; 2214 u16 len; 2215 2216 if (dv == NULL) 2217 return I40E_ERR_PARAM; 2218 2219 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2220 2221 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2222 cmd->driver_major_ver = dv->major_version; 2223 cmd->driver_minor_ver = dv->minor_version; 2224 cmd->driver_build_ver = dv->build_version; 2225 cmd->driver_subbuild_ver = dv->subbuild_version; 2226 2227 len = 0; 2228 while (len < sizeof(dv->driver_string) && 2229 (dv->driver_string[len] < 0x80) && 2230 dv->driver_string[len]) 2231 len++; 2232 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2233 len, cmd_details); 2234 2235 return status; 2236 } 2237 2238 /** 2239 * i40e_get_link_status - get status of the HW network link 2240 * @hw: pointer to the hw struct 2241 * 2242 * Returns true if link is up, false if link is down. 2243 * 2244 * Side effect: LinkStatusEvent reporting becomes enabled 2245 **/ 2246 bool i40e_get_link_status(struct i40e_hw *hw) 2247 { 2248 i40e_status status = 0; 2249 bool link_status = false; 2250 2251 if (hw->phy.get_link_info) { 2252 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2253 2254 if (status) 2255 goto i40e_get_link_status_exit; 2256 } 2257 2258 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2259 2260 i40e_get_link_status_exit: 2261 return link_status; 2262 } 2263 2264 /** 2265 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2266 * @hw: pointer to the hw struct 2267 * @uplink_seid: the MAC or other gizmo SEID 2268 * @downlink_seid: the VSI SEID 2269 * @enabled_tc: bitmap of TCs to be enabled 2270 * @default_port: true for default port VSI, false for control port 2271 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support 2272 * @veb_seid: pointer to where to put the resulting VEB SEID 2273 * @cmd_details: pointer to command details structure or NULL 2274 * 2275 * This asks the FW to add a VEB between the uplink and downlink 2276 * elements. If the uplink SEID is 0, this will be a floating VEB. 2277 **/ 2278 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2279 u16 downlink_seid, u8 enabled_tc, 2280 bool default_port, bool enable_l2_filtering, 2281 u16 *veb_seid, 2282 struct i40e_asq_cmd_details *cmd_details) 2283 { 2284 struct i40e_aq_desc desc; 2285 struct i40e_aqc_add_veb *cmd = 2286 (struct i40e_aqc_add_veb *)&desc.params.raw; 2287 struct i40e_aqc_add_veb_completion *resp = 2288 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2289 i40e_status status; 2290 u16 veb_flags = 0; 2291 2292 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2293 if (!!uplink_seid != !!downlink_seid) 2294 return I40E_ERR_PARAM; 2295 2296 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2297 2298 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2299 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2300 cmd->enable_tcs = enabled_tc; 2301 if (!uplink_seid) 2302 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2303 if (default_port) 2304 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2305 else 2306 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2307 2308 if (enable_l2_filtering) 2309 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 2310 2311 cmd->veb_flags = cpu_to_le16(veb_flags); 2312 2313 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2314 2315 if (!status && veb_seid) 2316 *veb_seid = le16_to_cpu(resp->veb_seid); 2317 2318 return status; 2319 } 2320 2321 /** 2322 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2323 * @hw: pointer to the hw struct 2324 * @veb_seid: the SEID of the VEB to query 2325 * @switch_id: the uplink switch id 2326 * @floating: set to true if the VEB is floating 2327 * @statistic_index: index of the stats counter block for this VEB 2328 * @vebs_used: number of VEB's used by function 2329 * @vebs_free: total VEB's not reserved by any function 2330 * @cmd_details: pointer to command details structure or NULL 2331 * 2332 * This retrieves the parameters for a particular VEB, specified by 2333 * uplink_seid, and returns them to the caller. 2334 **/ 2335 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2336 u16 veb_seid, u16 *switch_id, 2337 bool *floating, u16 *statistic_index, 2338 u16 *vebs_used, u16 *vebs_free, 2339 struct i40e_asq_cmd_details *cmd_details) 2340 { 2341 struct i40e_aq_desc desc; 2342 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2343 (struct i40e_aqc_get_veb_parameters_completion *) 2344 &desc.params.raw; 2345 i40e_status status; 2346 2347 if (veb_seid == 0) 2348 return I40E_ERR_PARAM; 2349 2350 i40e_fill_default_direct_cmd_desc(&desc, 2351 i40e_aqc_opc_get_veb_parameters); 2352 cmd_resp->seid = cpu_to_le16(veb_seid); 2353 2354 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2355 if (status) 2356 goto get_veb_exit; 2357 2358 if (switch_id) 2359 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2360 if (statistic_index) 2361 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2362 if (vebs_used) 2363 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2364 if (vebs_free) 2365 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2366 if (floating) { 2367 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2368 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2369 *floating = true; 2370 else 2371 *floating = false; 2372 } 2373 2374 get_veb_exit: 2375 return status; 2376 } 2377 2378 /** 2379 * i40e_aq_add_macvlan 2380 * @hw: pointer to the hw struct 2381 * @seid: VSI for the mac address 2382 * @mv_list: list of macvlans to be added 2383 * @count: length of the list 2384 * @cmd_details: pointer to command details structure or NULL 2385 * 2386 * Add MAC/VLAN addresses to the HW filtering 2387 **/ 2388 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2389 struct i40e_aqc_add_macvlan_element_data *mv_list, 2390 u16 count, struct i40e_asq_cmd_details *cmd_details) 2391 { 2392 struct i40e_aq_desc desc; 2393 struct i40e_aqc_macvlan *cmd = 2394 (struct i40e_aqc_macvlan *)&desc.params.raw; 2395 i40e_status status; 2396 u16 buf_size; 2397 2398 if (count == 0 || !mv_list || !hw) 2399 return I40E_ERR_PARAM; 2400 2401 buf_size = count * sizeof(*mv_list); 2402 2403 /* prep the rest of the request */ 2404 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2405 cmd->num_addresses = cpu_to_le16(count); 2406 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2407 cmd->seid[1] = 0; 2408 cmd->seid[2] = 0; 2409 2410 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2411 if (buf_size > I40E_AQ_LARGE_BUF) 2412 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2413 2414 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2415 cmd_details); 2416 2417 return status; 2418 } 2419 2420 /** 2421 * i40e_aq_remove_macvlan 2422 * @hw: pointer to the hw struct 2423 * @seid: VSI for the mac address 2424 * @mv_list: list of macvlans to be removed 2425 * @count: length of the list 2426 * @cmd_details: pointer to command details structure or NULL 2427 * 2428 * Remove MAC/VLAN addresses from the HW filtering 2429 **/ 2430 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2431 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2432 u16 count, struct i40e_asq_cmd_details *cmd_details) 2433 { 2434 struct i40e_aq_desc desc; 2435 struct i40e_aqc_macvlan *cmd = 2436 (struct i40e_aqc_macvlan *)&desc.params.raw; 2437 i40e_status status; 2438 u16 buf_size; 2439 2440 if (count == 0 || !mv_list || !hw) 2441 return I40E_ERR_PARAM; 2442 2443 buf_size = count * sizeof(*mv_list); 2444 2445 /* prep the rest of the request */ 2446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2447 cmd->num_addresses = cpu_to_le16(count); 2448 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2449 cmd->seid[1] = 0; 2450 cmd->seid[2] = 0; 2451 2452 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2453 if (buf_size > I40E_AQ_LARGE_BUF) 2454 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2455 2456 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2457 cmd_details); 2458 2459 return status; 2460 } 2461 2462 /** 2463 * i40e_aq_send_msg_to_vf 2464 * @hw: pointer to the hardware structure 2465 * @vfid: VF id to send msg 2466 * @v_opcode: opcodes for VF-PF communication 2467 * @v_retval: return error code 2468 * @msg: pointer to the msg buffer 2469 * @msglen: msg length 2470 * @cmd_details: pointer to command details 2471 * 2472 * send msg to vf 2473 **/ 2474 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2475 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2476 struct i40e_asq_cmd_details *cmd_details) 2477 { 2478 struct i40e_aq_desc desc; 2479 struct i40e_aqc_pf_vf_message *cmd = 2480 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2481 i40e_status status; 2482 2483 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2484 cmd->id = cpu_to_le32(vfid); 2485 desc.cookie_high = cpu_to_le32(v_opcode); 2486 desc.cookie_low = cpu_to_le32(v_retval); 2487 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2488 if (msglen) { 2489 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2490 I40E_AQ_FLAG_RD)); 2491 if (msglen > I40E_AQ_LARGE_BUF) 2492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2493 desc.datalen = cpu_to_le16(msglen); 2494 } 2495 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2496 2497 return status; 2498 } 2499 2500 /** 2501 * i40e_aq_debug_read_register 2502 * @hw: pointer to the hw struct 2503 * @reg_addr: register address 2504 * @reg_val: register value 2505 * @cmd_details: pointer to command details structure or NULL 2506 * 2507 * Read the register using the admin queue commands 2508 **/ 2509 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2510 u32 reg_addr, u64 *reg_val, 2511 struct i40e_asq_cmd_details *cmd_details) 2512 { 2513 struct i40e_aq_desc desc; 2514 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2515 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2516 i40e_status status; 2517 2518 if (reg_val == NULL) 2519 return I40E_ERR_PARAM; 2520 2521 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2522 2523 cmd_resp->address = cpu_to_le32(reg_addr); 2524 2525 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2526 2527 if (!status) { 2528 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2529 (u64)le32_to_cpu(cmd_resp->value_low); 2530 } 2531 2532 return status; 2533 } 2534 2535 /** 2536 * i40e_aq_debug_write_register 2537 * @hw: pointer to the hw struct 2538 * @reg_addr: register address 2539 * @reg_val: register value 2540 * @cmd_details: pointer to command details structure or NULL 2541 * 2542 * Write to a register using the admin queue commands 2543 **/ 2544 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2545 u32 reg_addr, u64 reg_val, 2546 struct i40e_asq_cmd_details *cmd_details) 2547 { 2548 struct i40e_aq_desc desc; 2549 struct i40e_aqc_debug_reg_read_write *cmd = 2550 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2551 i40e_status status; 2552 2553 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2554 2555 cmd->address = cpu_to_le32(reg_addr); 2556 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2557 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2558 2559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2560 2561 return status; 2562 } 2563 2564 /** 2565 * i40e_aq_set_hmc_resource_profile 2566 * @hw: pointer to the hw struct 2567 * @profile: type of profile the HMC is to be set as 2568 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2569 * @cmd_details: pointer to command details structure or NULL 2570 * 2571 * set the HMC profile of the device. 2572 **/ 2573 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2574 enum i40e_aq_hmc_profile profile, 2575 u8 pe_vf_enabled_count, 2576 struct i40e_asq_cmd_details *cmd_details) 2577 { 2578 struct i40e_aq_desc desc; 2579 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2580 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2581 i40e_status status; 2582 2583 i40e_fill_default_direct_cmd_desc(&desc, 2584 i40e_aqc_opc_set_hmc_resource_profile); 2585 2586 cmd->pm_profile = (u8)profile; 2587 cmd->pe_vf_enabled = pe_vf_enabled_count; 2588 2589 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2590 2591 return status; 2592 } 2593 2594 /** 2595 * i40e_aq_request_resource 2596 * @hw: pointer to the hw struct 2597 * @resource: resource id 2598 * @access: access type 2599 * @sdp_number: resource number 2600 * @timeout: the maximum time in ms that the driver may hold the resource 2601 * @cmd_details: pointer to command details structure or NULL 2602 * 2603 * requests common resource using the admin queue commands 2604 **/ 2605 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2606 enum i40e_aq_resources_ids resource, 2607 enum i40e_aq_resource_access_type access, 2608 u8 sdp_number, u64 *timeout, 2609 struct i40e_asq_cmd_details *cmd_details) 2610 { 2611 struct i40e_aq_desc desc; 2612 struct i40e_aqc_request_resource *cmd_resp = 2613 (struct i40e_aqc_request_resource *)&desc.params.raw; 2614 i40e_status status; 2615 2616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2617 2618 cmd_resp->resource_id = cpu_to_le16(resource); 2619 cmd_resp->access_type = cpu_to_le16(access); 2620 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2621 2622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2623 /* The completion specifies the maximum time in ms that the driver 2624 * may hold the resource in the Timeout field. 2625 * If the resource is held by someone else, the command completes with 2626 * busy return value and the timeout field indicates the maximum time 2627 * the current owner of the resource has to free it. 2628 */ 2629 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2630 *timeout = le32_to_cpu(cmd_resp->timeout); 2631 2632 return status; 2633 } 2634 2635 /** 2636 * i40e_aq_release_resource 2637 * @hw: pointer to the hw struct 2638 * @resource: resource id 2639 * @sdp_number: resource number 2640 * @cmd_details: pointer to command details structure or NULL 2641 * 2642 * release common resource using the admin queue commands 2643 **/ 2644 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2645 enum i40e_aq_resources_ids resource, 2646 u8 sdp_number, 2647 struct i40e_asq_cmd_details *cmd_details) 2648 { 2649 struct i40e_aq_desc desc; 2650 struct i40e_aqc_request_resource *cmd = 2651 (struct i40e_aqc_request_resource *)&desc.params.raw; 2652 i40e_status status; 2653 2654 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2655 2656 cmd->resource_id = cpu_to_le16(resource); 2657 cmd->resource_number = cpu_to_le32(sdp_number); 2658 2659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2660 2661 return status; 2662 } 2663 2664 /** 2665 * i40e_aq_read_nvm 2666 * @hw: pointer to the hw struct 2667 * @module_pointer: module pointer location in words from the NVM beginning 2668 * @offset: byte offset from the module beginning 2669 * @length: length of the section to be read (in bytes from the offset) 2670 * @data: command buffer (size [bytes] = length) 2671 * @last_command: tells if this is the last command in a series 2672 * @cmd_details: pointer to command details structure or NULL 2673 * 2674 * Read the NVM using the admin queue commands 2675 **/ 2676 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2677 u32 offset, u16 length, void *data, 2678 bool last_command, 2679 struct i40e_asq_cmd_details *cmd_details) 2680 { 2681 struct i40e_aq_desc desc; 2682 struct i40e_aqc_nvm_update *cmd = 2683 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2684 i40e_status status; 2685 2686 /* In offset the highest byte must be zeroed. */ 2687 if (offset & 0xFF000000) { 2688 status = I40E_ERR_PARAM; 2689 goto i40e_aq_read_nvm_exit; 2690 } 2691 2692 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2693 2694 /* If this is the last command in a series, set the proper flag. */ 2695 if (last_command) 2696 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2697 cmd->module_pointer = module_pointer; 2698 cmd->offset = cpu_to_le32(offset); 2699 cmd->length = cpu_to_le16(length); 2700 2701 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2702 if (length > I40E_AQ_LARGE_BUF) 2703 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2704 2705 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2706 2707 i40e_aq_read_nvm_exit: 2708 return status; 2709 } 2710 2711 /** 2712 * i40e_aq_erase_nvm 2713 * @hw: pointer to the hw struct 2714 * @module_pointer: module pointer location in words from the NVM beginning 2715 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2716 * @length: length of the section to be erased (expressed in 4 KB) 2717 * @last_command: tells if this is the last command in a series 2718 * @cmd_details: pointer to command details structure or NULL 2719 * 2720 * Erase the NVM sector using the admin queue commands 2721 **/ 2722 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2723 u32 offset, u16 length, bool last_command, 2724 struct i40e_asq_cmd_details *cmd_details) 2725 { 2726 struct i40e_aq_desc desc; 2727 struct i40e_aqc_nvm_update *cmd = 2728 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2729 i40e_status status; 2730 2731 /* In offset the highest byte must be zeroed. */ 2732 if (offset & 0xFF000000) { 2733 status = I40E_ERR_PARAM; 2734 goto i40e_aq_erase_nvm_exit; 2735 } 2736 2737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2738 2739 /* If this is the last command in a series, set the proper flag. */ 2740 if (last_command) 2741 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2742 cmd->module_pointer = module_pointer; 2743 cmd->offset = cpu_to_le32(offset); 2744 cmd->length = cpu_to_le16(length); 2745 2746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2747 2748 i40e_aq_erase_nvm_exit: 2749 return status; 2750 } 2751 2752 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2753 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2754 #define I40E_DEV_FUNC_CAP_NPAR 0x03 2755 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2756 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2757 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2758 #define I40E_DEV_FUNC_CAP_VF 0x13 2759 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 2760 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2761 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2762 #define I40E_DEV_FUNC_CAP_VSI 0x17 2763 #define I40E_DEV_FUNC_CAP_DCB 0x18 2764 #define I40E_DEV_FUNC_CAP_FCOE 0x21 2765 #define I40E_DEV_FUNC_CAP_ISCSI 0x22 2766 #define I40E_DEV_FUNC_CAP_RSS 0x40 2767 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2768 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2769 #define I40E_DEV_FUNC_CAP_MSIX 0x43 2770 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2771 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2772 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2773 #define I40E_DEV_FUNC_CAP_FLEX10 0xF1 2774 #define I40E_DEV_FUNC_CAP_CEM 0xF2 2775 #define I40E_DEV_FUNC_CAP_IWARP 0x51 2776 #define I40E_DEV_FUNC_CAP_LED 0x61 2777 #define I40E_DEV_FUNC_CAP_SDP 0x62 2778 #define I40E_DEV_FUNC_CAP_MDIO 0x63 2779 #define I40E_DEV_FUNC_CAP_WR_CSR_PROT 0x64 2780 2781 /** 2782 * i40e_parse_discover_capabilities 2783 * @hw: pointer to the hw struct 2784 * @buff: pointer to a buffer containing device/function capability records 2785 * @cap_count: number of capability records in the list 2786 * @list_type_opc: type of capabilities list to parse 2787 * 2788 * Parse the device/function capabilities list. 2789 **/ 2790 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2791 u32 cap_count, 2792 enum i40e_admin_queue_opc list_type_opc) 2793 { 2794 struct i40e_aqc_list_capabilities_element_resp *cap; 2795 u32 valid_functions, num_functions; 2796 u32 number, logical_id, phys_id; 2797 struct i40e_hw_capabilities *p; 2798 u8 major_rev; 2799 u32 i = 0; 2800 u16 id; 2801 2802 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2803 2804 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2805 p = &hw->dev_caps; 2806 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2807 p = &hw->func_caps; 2808 else 2809 return; 2810 2811 for (i = 0; i < cap_count; i++, cap++) { 2812 id = le16_to_cpu(cap->id); 2813 number = le32_to_cpu(cap->number); 2814 logical_id = le32_to_cpu(cap->logical_id); 2815 phys_id = le32_to_cpu(cap->phys_id); 2816 major_rev = cap->major_rev; 2817 2818 switch (id) { 2819 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2820 p->switch_mode = number; 2821 break; 2822 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2823 p->management_mode = number; 2824 break; 2825 case I40E_DEV_FUNC_CAP_NPAR: 2826 p->npar_enable = number; 2827 break; 2828 case I40E_DEV_FUNC_CAP_OS2BMC: 2829 p->os2bmc = number; 2830 break; 2831 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2832 p->valid_functions = number; 2833 break; 2834 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2835 if (number == 1) 2836 p->sr_iov_1_1 = true; 2837 break; 2838 case I40E_DEV_FUNC_CAP_VF: 2839 p->num_vfs = number; 2840 p->vf_base_id = logical_id; 2841 break; 2842 case I40E_DEV_FUNC_CAP_VMDQ: 2843 if (number == 1) 2844 p->vmdq = true; 2845 break; 2846 case I40E_DEV_FUNC_CAP_802_1_QBG: 2847 if (number == 1) 2848 p->evb_802_1_qbg = true; 2849 break; 2850 case I40E_DEV_FUNC_CAP_802_1_QBH: 2851 if (number == 1) 2852 p->evb_802_1_qbh = true; 2853 break; 2854 case I40E_DEV_FUNC_CAP_VSI: 2855 p->num_vsis = number; 2856 break; 2857 case I40E_DEV_FUNC_CAP_DCB: 2858 if (number == 1) { 2859 p->dcb = true; 2860 p->enabled_tcmap = logical_id; 2861 p->maxtc = phys_id; 2862 } 2863 break; 2864 case I40E_DEV_FUNC_CAP_FCOE: 2865 if (number == 1) 2866 p->fcoe = true; 2867 break; 2868 case I40E_DEV_FUNC_CAP_ISCSI: 2869 if (number == 1) 2870 p->iscsi = true; 2871 break; 2872 case I40E_DEV_FUNC_CAP_RSS: 2873 p->rss = true; 2874 p->rss_table_size = number; 2875 p->rss_table_entry_width = logical_id; 2876 break; 2877 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2878 p->num_rx_qp = number; 2879 p->base_queue = phys_id; 2880 break; 2881 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2882 p->num_tx_qp = number; 2883 p->base_queue = phys_id; 2884 break; 2885 case I40E_DEV_FUNC_CAP_MSIX: 2886 p->num_msix_vectors = number; 2887 break; 2888 case I40E_DEV_FUNC_CAP_MSIX_VF: 2889 p->num_msix_vectors_vf = number; 2890 break; 2891 case I40E_DEV_FUNC_CAP_FLEX10: 2892 if (major_rev == 1) { 2893 if (number == 1) { 2894 p->flex10_enable = true; 2895 p->flex10_capable = true; 2896 } 2897 } else { 2898 /* Capability revision >= 2 */ 2899 if (number & 1) 2900 p->flex10_enable = true; 2901 if (number & 2) 2902 p->flex10_capable = true; 2903 } 2904 p->flex10_mode = logical_id; 2905 p->flex10_status = phys_id; 2906 break; 2907 case I40E_DEV_FUNC_CAP_CEM: 2908 if (number == 1) 2909 p->mgmt_cem = true; 2910 break; 2911 case I40E_DEV_FUNC_CAP_IWARP: 2912 if (number == 1) 2913 p->iwarp = true; 2914 break; 2915 case I40E_DEV_FUNC_CAP_LED: 2916 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2917 p->led[phys_id] = true; 2918 break; 2919 case I40E_DEV_FUNC_CAP_SDP: 2920 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2921 p->sdp[phys_id] = true; 2922 break; 2923 case I40E_DEV_FUNC_CAP_MDIO: 2924 if (number == 1) { 2925 p->mdio_port_num = phys_id; 2926 p->mdio_port_mode = logical_id; 2927 } 2928 break; 2929 case I40E_DEV_FUNC_CAP_IEEE_1588: 2930 if (number == 1) 2931 p->ieee_1588 = true; 2932 break; 2933 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2934 p->fd = true; 2935 p->fd_filters_guaranteed = number; 2936 p->fd_filters_best_effort = logical_id; 2937 break; 2938 case I40E_DEV_FUNC_CAP_WR_CSR_PROT: 2939 p->wr_csr_prot = (u64)number; 2940 p->wr_csr_prot |= (u64)logical_id << 32; 2941 break; 2942 default: 2943 break; 2944 } 2945 } 2946 2947 if (p->fcoe) 2948 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 2949 2950 /* Software override ensuring FCoE is disabled if npar or mfp 2951 * mode because it is not supported in these modes. 2952 */ 2953 if (p->npar_enable || p->flex10_enable) 2954 p->fcoe = false; 2955 2956 /* count the enabled ports (aka the "not disabled" ports) */ 2957 hw->num_ports = 0; 2958 for (i = 0; i < 4; i++) { 2959 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2960 u64 port_cfg = 0; 2961 2962 /* use AQ read to get the physical register offset instead 2963 * of the port relative offset 2964 */ 2965 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2966 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2967 hw->num_ports++; 2968 } 2969 2970 valid_functions = p->valid_functions; 2971 num_functions = 0; 2972 while (valid_functions) { 2973 if (valid_functions & 1) 2974 num_functions++; 2975 valid_functions >>= 1; 2976 } 2977 2978 /* partition id is 1-based, and functions are evenly spread 2979 * across the ports as partitions 2980 */ 2981 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2982 hw->num_partitions = num_functions / hw->num_ports; 2983 2984 /* additional HW specific goodies that might 2985 * someday be HW version specific 2986 */ 2987 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2988 } 2989 2990 /** 2991 * i40e_aq_discover_capabilities 2992 * @hw: pointer to the hw struct 2993 * @buff: a virtual buffer to hold the capabilities 2994 * @buff_size: Size of the virtual buffer 2995 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2996 * @list_type_opc: capabilities type to discover - pass in the command opcode 2997 * @cmd_details: pointer to command details structure or NULL 2998 * 2999 * Get the device capabilities descriptions from the firmware 3000 **/ 3001 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3002 void *buff, u16 buff_size, u16 *data_size, 3003 enum i40e_admin_queue_opc list_type_opc, 3004 struct i40e_asq_cmd_details *cmd_details) 3005 { 3006 struct i40e_aqc_list_capabilites *cmd; 3007 struct i40e_aq_desc desc; 3008 i40e_status status = 0; 3009 3010 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3011 3012 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3013 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3014 status = I40E_ERR_PARAM; 3015 goto exit; 3016 } 3017 3018 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3019 3020 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3021 if (buff_size > I40E_AQ_LARGE_BUF) 3022 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3023 3024 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3025 *data_size = le16_to_cpu(desc.datalen); 3026 3027 if (status) 3028 goto exit; 3029 3030 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3031 list_type_opc); 3032 3033 exit: 3034 return status; 3035 } 3036 3037 /** 3038 * i40e_aq_update_nvm 3039 * @hw: pointer to the hw struct 3040 * @module_pointer: module pointer location in words from the NVM beginning 3041 * @offset: byte offset from the module beginning 3042 * @length: length of the section to be written (in bytes from the offset) 3043 * @data: command buffer (size [bytes] = length) 3044 * @last_command: tells if this is the last command in a series 3045 * @cmd_details: pointer to command details structure or NULL 3046 * 3047 * Update the NVM using the admin queue commands 3048 **/ 3049 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3050 u32 offset, u16 length, void *data, 3051 bool last_command, 3052 struct i40e_asq_cmd_details *cmd_details) 3053 { 3054 struct i40e_aq_desc desc; 3055 struct i40e_aqc_nvm_update *cmd = 3056 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3057 i40e_status status; 3058 3059 /* In offset the highest byte must be zeroed. */ 3060 if (offset & 0xFF000000) { 3061 status = I40E_ERR_PARAM; 3062 goto i40e_aq_update_nvm_exit; 3063 } 3064 3065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3066 3067 /* If this is the last command in a series, set the proper flag. */ 3068 if (last_command) 3069 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3070 cmd->module_pointer = module_pointer; 3071 cmd->offset = cpu_to_le32(offset); 3072 cmd->length = cpu_to_le16(length); 3073 3074 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3075 if (length > I40E_AQ_LARGE_BUF) 3076 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3077 3078 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3079 3080 i40e_aq_update_nvm_exit: 3081 return status; 3082 } 3083 3084 /** 3085 * i40e_aq_get_lldp_mib 3086 * @hw: pointer to the hw struct 3087 * @bridge_type: type of bridge requested 3088 * @mib_type: Local, Remote or both Local and Remote MIBs 3089 * @buff: pointer to a user supplied buffer to store the MIB block 3090 * @buff_size: size of the buffer (in bytes) 3091 * @local_len : length of the returned Local LLDP MIB 3092 * @remote_len: length of the returned Remote LLDP MIB 3093 * @cmd_details: pointer to command details structure or NULL 3094 * 3095 * Requests the complete LLDP MIB (entire packet). 3096 **/ 3097 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3098 u8 mib_type, void *buff, u16 buff_size, 3099 u16 *local_len, u16 *remote_len, 3100 struct i40e_asq_cmd_details *cmd_details) 3101 { 3102 struct i40e_aq_desc desc; 3103 struct i40e_aqc_lldp_get_mib *cmd = 3104 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3105 struct i40e_aqc_lldp_get_mib *resp = 3106 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3107 i40e_status status; 3108 3109 if (buff_size == 0 || !buff) 3110 return I40E_ERR_PARAM; 3111 3112 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3113 /* Indirect Command */ 3114 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3115 3116 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3117 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3118 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3119 3120 desc.datalen = cpu_to_le16(buff_size); 3121 3122 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3123 if (buff_size > I40E_AQ_LARGE_BUF) 3124 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3125 3126 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3127 if (!status) { 3128 if (local_len != NULL) 3129 *local_len = le16_to_cpu(resp->local_len); 3130 if (remote_len != NULL) 3131 *remote_len = le16_to_cpu(resp->remote_len); 3132 } 3133 3134 return status; 3135 } 3136 3137 /** 3138 * i40e_aq_cfg_lldp_mib_change_event 3139 * @hw: pointer to the hw struct 3140 * @enable_update: Enable or Disable event posting 3141 * @cmd_details: pointer to command details structure or NULL 3142 * 3143 * Enable or Disable posting of an event on ARQ when LLDP MIB 3144 * associated with the interface changes 3145 **/ 3146 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3147 bool enable_update, 3148 struct i40e_asq_cmd_details *cmd_details) 3149 { 3150 struct i40e_aq_desc desc; 3151 struct i40e_aqc_lldp_update_mib *cmd = 3152 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3153 i40e_status status; 3154 3155 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3156 3157 if (!enable_update) 3158 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3159 3160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3161 3162 return status; 3163 } 3164 3165 /** 3166 * i40e_aq_stop_lldp 3167 * @hw: pointer to the hw struct 3168 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3169 * @cmd_details: pointer to command details structure or NULL 3170 * 3171 * Stop or Shutdown the embedded LLDP Agent 3172 **/ 3173 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3174 struct i40e_asq_cmd_details *cmd_details) 3175 { 3176 struct i40e_aq_desc desc; 3177 struct i40e_aqc_lldp_stop *cmd = 3178 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3179 i40e_status status; 3180 3181 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3182 3183 if (shutdown_agent) 3184 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3185 3186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3187 3188 return status; 3189 } 3190 3191 /** 3192 * i40e_aq_start_lldp 3193 * @hw: pointer to the hw struct 3194 * @cmd_details: pointer to command details structure or NULL 3195 * 3196 * Start the embedded LLDP Agent on all ports. 3197 **/ 3198 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3199 struct i40e_asq_cmd_details *cmd_details) 3200 { 3201 struct i40e_aq_desc desc; 3202 struct i40e_aqc_lldp_start *cmd = 3203 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3204 i40e_status status; 3205 3206 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3207 3208 cmd->command = I40E_AQ_LLDP_AGENT_START; 3209 3210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3211 3212 return status; 3213 } 3214 3215 /** 3216 * i40e_aq_get_cee_dcb_config 3217 * @hw: pointer to the hw struct 3218 * @buff: response buffer that stores CEE operational configuration 3219 * @buff_size: size of the buffer passed 3220 * @cmd_details: pointer to command details structure or NULL 3221 * 3222 * Get CEE DCBX mode operational configuration from firmware 3223 **/ 3224 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3225 void *buff, u16 buff_size, 3226 struct i40e_asq_cmd_details *cmd_details) 3227 { 3228 struct i40e_aq_desc desc; 3229 i40e_status status; 3230 3231 if (buff_size == 0 || !buff) 3232 return I40E_ERR_PARAM; 3233 3234 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3235 3236 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3237 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3238 cmd_details); 3239 3240 return status; 3241 } 3242 3243 /** 3244 * i40e_aq_add_udp_tunnel 3245 * @hw: pointer to the hw struct 3246 * @udp_port: the UDP port to add 3247 * @header_len: length of the tunneling header length in DWords 3248 * @protocol_index: protocol index type 3249 * @filter_index: pointer to filter index 3250 * @cmd_details: pointer to command details structure or NULL 3251 **/ 3252 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3253 u16 udp_port, u8 protocol_index, 3254 u8 *filter_index, 3255 struct i40e_asq_cmd_details *cmd_details) 3256 { 3257 struct i40e_aq_desc desc; 3258 struct i40e_aqc_add_udp_tunnel *cmd = 3259 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3260 struct i40e_aqc_del_udp_tunnel_completion *resp = 3261 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3262 i40e_status status; 3263 3264 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3265 3266 cmd->udp_port = cpu_to_le16(udp_port); 3267 cmd->protocol_type = protocol_index; 3268 3269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3270 3271 if (!status && filter_index) 3272 *filter_index = resp->index; 3273 3274 return status; 3275 } 3276 3277 /** 3278 * i40e_aq_del_udp_tunnel 3279 * @hw: pointer to the hw struct 3280 * @index: filter index 3281 * @cmd_details: pointer to command details structure or NULL 3282 **/ 3283 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3284 struct i40e_asq_cmd_details *cmd_details) 3285 { 3286 struct i40e_aq_desc desc; 3287 struct i40e_aqc_remove_udp_tunnel *cmd = 3288 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3289 i40e_status status; 3290 3291 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3292 3293 cmd->index = index; 3294 3295 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3296 3297 return status; 3298 } 3299 3300 /** 3301 * i40e_aq_delete_element - Delete switch element 3302 * @hw: pointer to the hw struct 3303 * @seid: the SEID to delete from the switch 3304 * @cmd_details: pointer to command details structure or NULL 3305 * 3306 * This deletes a switch element from the switch. 3307 **/ 3308 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3309 struct i40e_asq_cmd_details *cmd_details) 3310 { 3311 struct i40e_aq_desc desc; 3312 struct i40e_aqc_switch_seid *cmd = 3313 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3314 i40e_status status; 3315 3316 if (seid == 0) 3317 return I40E_ERR_PARAM; 3318 3319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3320 3321 cmd->seid = cpu_to_le16(seid); 3322 3323 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3324 3325 return status; 3326 } 3327 3328 /** 3329 * i40e_aq_dcb_updated - DCB Updated Command 3330 * @hw: pointer to the hw struct 3331 * @cmd_details: pointer to command details structure or NULL 3332 * 3333 * EMP will return when the shared RPB settings have been 3334 * recomputed and modified. The retval field in the descriptor 3335 * will be set to 0 when RPB is modified. 3336 **/ 3337 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3338 struct i40e_asq_cmd_details *cmd_details) 3339 { 3340 struct i40e_aq_desc desc; 3341 i40e_status status; 3342 3343 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3344 3345 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3346 3347 return status; 3348 } 3349 3350 /** 3351 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3352 * @hw: pointer to the hw struct 3353 * @seid: seid for the physical port/switching component/vsi 3354 * @buff: Indirect buffer to hold data parameters and response 3355 * @buff_size: Indirect buffer size 3356 * @opcode: Tx scheduler AQ command opcode 3357 * @cmd_details: pointer to command details structure or NULL 3358 * 3359 * Generic command handler for Tx scheduler AQ commands 3360 **/ 3361 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3362 void *buff, u16 buff_size, 3363 enum i40e_admin_queue_opc opcode, 3364 struct i40e_asq_cmd_details *cmd_details) 3365 { 3366 struct i40e_aq_desc desc; 3367 struct i40e_aqc_tx_sched_ind *cmd = 3368 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3369 i40e_status status; 3370 bool cmd_param_flag = false; 3371 3372 switch (opcode) { 3373 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3374 case i40e_aqc_opc_configure_vsi_tc_bw: 3375 case i40e_aqc_opc_enable_switching_comp_ets: 3376 case i40e_aqc_opc_modify_switching_comp_ets: 3377 case i40e_aqc_opc_disable_switching_comp_ets: 3378 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3379 case i40e_aqc_opc_configure_switching_comp_bw_config: 3380 cmd_param_flag = true; 3381 break; 3382 case i40e_aqc_opc_query_vsi_bw_config: 3383 case i40e_aqc_opc_query_vsi_ets_sla_config: 3384 case i40e_aqc_opc_query_switching_comp_ets_config: 3385 case i40e_aqc_opc_query_port_ets_config: 3386 case i40e_aqc_opc_query_switching_comp_bw_config: 3387 cmd_param_flag = false; 3388 break; 3389 default: 3390 return I40E_ERR_PARAM; 3391 } 3392 3393 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3394 3395 /* Indirect command */ 3396 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3397 if (cmd_param_flag) 3398 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3399 if (buff_size > I40E_AQ_LARGE_BUF) 3400 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3401 3402 desc.datalen = cpu_to_le16(buff_size); 3403 3404 cmd->vsi_seid = cpu_to_le16(seid); 3405 3406 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3407 3408 return status; 3409 } 3410 3411 /** 3412 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3413 * @hw: pointer to the hw struct 3414 * @seid: VSI seid 3415 * @credit: BW limit credits (0 = disabled) 3416 * @max_credit: Max BW limit credits 3417 * @cmd_details: pointer to command details structure or NULL 3418 **/ 3419 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3420 u16 seid, u16 credit, u8 max_credit, 3421 struct i40e_asq_cmd_details *cmd_details) 3422 { 3423 struct i40e_aq_desc desc; 3424 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3425 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3426 i40e_status status; 3427 3428 i40e_fill_default_direct_cmd_desc(&desc, 3429 i40e_aqc_opc_configure_vsi_bw_limit); 3430 3431 cmd->vsi_seid = cpu_to_le16(seid); 3432 cmd->credit = cpu_to_le16(credit); 3433 cmd->max_credit = max_credit; 3434 3435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3436 3437 return status; 3438 } 3439 3440 /** 3441 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3442 * @hw: pointer to the hw struct 3443 * @seid: VSI seid 3444 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3445 * @cmd_details: pointer to command details structure or NULL 3446 **/ 3447 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3448 u16 seid, 3449 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3450 struct i40e_asq_cmd_details *cmd_details) 3451 { 3452 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3453 i40e_aqc_opc_configure_vsi_tc_bw, 3454 cmd_details); 3455 } 3456 3457 /** 3458 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3459 * @hw: pointer to the hw struct 3460 * @seid: seid of the switching component connected to Physical Port 3461 * @ets_data: Buffer holding ETS parameters 3462 * @cmd_details: pointer to command details structure or NULL 3463 **/ 3464 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3465 u16 seid, 3466 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3467 enum i40e_admin_queue_opc opcode, 3468 struct i40e_asq_cmd_details *cmd_details) 3469 { 3470 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3471 sizeof(*ets_data), opcode, cmd_details); 3472 } 3473 3474 /** 3475 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3476 * @hw: pointer to the hw struct 3477 * @seid: seid of the switching component 3478 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3479 * @cmd_details: pointer to command details structure or NULL 3480 **/ 3481 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3482 u16 seid, 3483 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3484 struct i40e_asq_cmd_details *cmd_details) 3485 { 3486 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3487 i40e_aqc_opc_configure_switching_comp_bw_config, 3488 cmd_details); 3489 } 3490 3491 /** 3492 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3493 * @hw: pointer to the hw struct 3494 * @seid: seid of the VSI 3495 * @bw_data: Buffer to hold VSI BW configuration 3496 * @cmd_details: pointer to command details structure or NULL 3497 **/ 3498 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3499 u16 seid, 3500 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3501 struct i40e_asq_cmd_details *cmd_details) 3502 { 3503 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3504 i40e_aqc_opc_query_vsi_bw_config, 3505 cmd_details); 3506 } 3507 3508 /** 3509 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3510 * @hw: pointer to the hw struct 3511 * @seid: seid of the VSI 3512 * @bw_data: Buffer to hold VSI BW configuration per TC 3513 * @cmd_details: pointer to command details structure or NULL 3514 **/ 3515 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3516 u16 seid, 3517 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3518 struct i40e_asq_cmd_details *cmd_details) 3519 { 3520 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3521 i40e_aqc_opc_query_vsi_ets_sla_config, 3522 cmd_details); 3523 } 3524 3525 /** 3526 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3527 * @hw: pointer to the hw struct 3528 * @seid: seid of the switching component 3529 * @bw_data: Buffer to hold switching component's per TC BW config 3530 * @cmd_details: pointer to command details structure or NULL 3531 **/ 3532 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3533 u16 seid, 3534 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3535 struct i40e_asq_cmd_details *cmd_details) 3536 { 3537 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3538 i40e_aqc_opc_query_switching_comp_ets_config, 3539 cmd_details); 3540 } 3541 3542 /** 3543 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3544 * @hw: pointer to the hw struct 3545 * @seid: seid of the VSI or switching component connected to Physical Port 3546 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3547 * @cmd_details: pointer to command details structure or NULL 3548 **/ 3549 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3550 u16 seid, 3551 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3552 struct i40e_asq_cmd_details *cmd_details) 3553 { 3554 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3555 i40e_aqc_opc_query_port_ets_config, 3556 cmd_details); 3557 } 3558 3559 /** 3560 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3561 * @hw: pointer to the hw struct 3562 * @seid: seid of the switching component 3563 * @bw_data: Buffer to hold switching component's BW configuration 3564 * @cmd_details: pointer to command details structure or NULL 3565 **/ 3566 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3567 u16 seid, 3568 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3569 struct i40e_asq_cmd_details *cmd_details) 3570 { 3571 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3572 i40e_aqc_opc_query_switching_comp_bw_config, 3573 cmd_details); 3574 } 3575 3576 /** 3577 * i40e_validate_filter_settings 3578 * @hw: pointer to the hardware structure 3579 * @settings: Filter control settings 3580 * 3581 * Check and validate the filter control settings passed. 3582 * The function checks for the valid filter/context sizes being 3583 * passed for FCoE and PE. 3584 * 3585 * Returns 0 if the values passed are valid and within 3586 * range else returns an error. 3587 **/ 3588 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3589 struct i40e_filter_control_settings *settings) 3590 { 3591 u32 fcoe_cntx_size, fcoe_filt_size; 3592 u32 pe_cntx_size, pe_filt_size; 3593 u32 fcoe_fmax; 3594 u32 val; 3595 3596 /* Validate FCoE settings passed */ 3597 switch (settings->fcoe_filt_num) { 3598 case I40E_HASH_FILTER_SIZE_1K: 3599 case I40E_HASH_FILTER_SIZE_2K: 3600 case I40E_HASH_FILTER_SIZE_4K: 3601 case I40E_HASH_FILTER_SIZE_8K: 3602 case I40E_HASH_FILTER_SIZE_16K: 3603 case I40E_HASH_FILTER_SIZE_32K: 3604 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3605 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3606 break; 3607 default: 3608 return I40E_ERR_PARAM; 3609 } 3610 3611 switch (settings->fcoe_cntx_num) { 3612 case I40E_DMA_CNTX_SIZE_512: 3613 case I40E_DMA_CNTX_SIZE_1K: 3614 case I40E_DMA_CNTX_SIZE_2K: 3615 case I40E_DMA_CNTX_SIZE_4K: 3616 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3617 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3618 break; 3619 default: 3620 return I40E_ERR_PARAM; 3621 } 3622 3623 /* Validate PE settings passed */ 3624 switch (settings->pe_filt_num) { 3625 case I40E_HASH_FILTER_SIZE_1K: 3626 case I40E_HASH_FILTER_SIZE_2K: 3627 case I40E_HASH_FILTER_SIZE_4K: 3628 case I40E_HASH_FILTER_SIZE_8K: 3629 case I40E_HASH_FILTER_SIZE_16K: 3630 case I40E_HASH_FILTER_SIZE_32K: 3631 case I40E_HASH_FILTER_SIZE_64K: 3632 case I40E_HASH_FILTER_SIZE_128K: 3633 case I40E_HASH_FILTER_SIZE_256K: 3634 case I40E_HASH_FILTER_SIZE_512K: 3635 case I40E_HASH_FILTER_SIZE_1M: 3636 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3637 pe_filt_size <<= (u32)settings->pe_filt_num; 3638 break; 3639 default: 3640 return I40E_ERR_PARAM; 3641 } 3642 3643 switch (settings->pe_cntx_num) { 3644 case I40E_DMA_CNTX_SIZE_512: 3645 case I40E_DMA_CNTX_SIZE_1K: 3646 case I40E_DMA_CNTX_SIZE_2K: 3647 case I40E_DMA_CNTX_SIZE_4K: 3648 case I40E_DMA_CNTX_SIZE_8K: 3649 case I40E_DMA_CNTX_SIZE_16K: 3650 case I40E_DMA_CNTX_SIZE_32K: 3651 case I40E_DMA_CNTX_SIZE_64K: 3652 case I40E_DMA_CNTX_SIZE_128K: 3653 case I40E_DMA_CNTX_SIZE_256K: 3654 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3655 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3656 break; 3657 default: 3658 return I40E_ERR_PARAM; 3659 } 3660 3661 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3662 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3663 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3664 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3665 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3666 return I40E_ERR_INVALID_SIZE; 3667 3668 return 0; 3669 } 3670 3671 /** 3672 * i40e_set_filter_control 3673 * @hw: pointer to the hardware structure 3674 * @settings: Filter control settings 3675 * 3676 * Set the Queue Filters for PE/FCoE and enable filters required 3677 * for a single PF. It is expected that these settings are programmed 3678 * at the driver initialization time. 3679 **/ 3680 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 3681 struct i40e_filter_control_settings *settings) 3682 { 3683 i40e_status ret = 0; 3684 u32 hash_lut_size = 0; 3685 u32 val; 3686 3687 if (!settings) 3688 return I40E_ERR_PARAM; 3689 3690 /* Validate the input settings */ 3691 ret = i40e_validate_filter_settings(hw, settings); 3692 if (ret) 3693 return ret; 3694 3695 /* Read the PF Queue Filter control register */ 3696 val = rd32(hw, I40E_PFQF_CTL_0); 3697 3698 /* Program required PE hash buckets for the PF */ 3699 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3700 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 3701 I40E_PFQF_CTL_0_PEHSIZE_MASK; 3702 /* Program required PE contexts for the PF */ 3703 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3704 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 3705 I40E_PFQF_CTL_0_PEDSIZE_MASK; 3706 3707 /* Program required FCoE hash buckets for the PF */ 3708 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3709 val |= ((u32)settings->fcoe_filt_num << 3710 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 3711 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3712 /* Program required FCoE DDP contexts for the PF */ 3713 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3714 val |= ((u32)settings->fcoe_cntx_num << 3715 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 3716 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3717 3718 /* Program Hash LUT size for the PF */ 3719 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3720 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3721 hash_lut_size = 1; 3722 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 3723 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3724 3725 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3726 if (settings->enable_fdir) 3727 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3728 if (settings->enable_ethtype) 3729 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3730 if (settings->enable_macvlan) 3731 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3732 3733 wr32(hw, I40E_PFQF_CTL_0, val); 3734 3735 return 0; 3736 } 3737 3738 /** 3739 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3740 * @hw: pointer to the hw struct 3741 * @mac_addr: MAC address to use in the filter 3742 * @ethtype: Ethertype to use in the filter 3743 * @flags: Flags that needs to be applied to the filter 3744 * @vsi_seid: seid of the control VSI 3745 * @queue: VSI queue number to send the packet to 3746 * @is_add: Add control packet filter if True else remove 3747 * @stats: Structure to hold information on control filter counts 3748 * @cmd_details: pointer to command details structure or NULL 3749 * 3750 * This command will Add or Remove control packet filter for a control VSI. 3751 * In return it will update the total number of perfect filter count in 3752 * the stats member. 3753 **/ 3754 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3755 u8 *mac_addr, u16 ethtype, u16 flags, 3756 u16 vsi_seid, u16 queue, bool is_add, 3757 struct i40e_control_filter_stats *stats, 3758 struct i40e_asq_cmd_details *cmd_details) 3759 { 3760 struct i40e_aq_desc desc; 3761 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3762 (struct i40e_aqc_add_remove_control_packet_filter *) 3763 &desc.params.raw; 3764 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3765 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3766 &desc.params.raw; 3767 i40e_status status; 3768 3769 if (vsi_seid == 0) 3770 return I40E_ERR_PARAM; 3771 3772 if (is_add) { 3773 i40e_fill_default_direct_cmd_desc(&desc, 3774 i40e_aqc_opc_add_control_packet_filter); 3775 cmd->queue = cpu_to_le16(queue); 3776 } else { 3777 i40e_fill_default_direct_cmd_desc(&desc, 3778 i40e_aqc_opc_remove_control_packet_filter); 3779 } 3780 3781 if (mac_addr) 3782 memcpy(cmd->mac, mac_addr, ETH_ALEN); 3783 3784 cmd->etype = cpu_to_le16(ethtype); 3785 cmd->flags = cpu_to_le16(flags); 3786 cmd->seid = cpu_to_le16(vsi_seid); 3787 3788 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3789 3790 if (!status && stats) { 3791 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3792 stats->etype_used = le16_to_cpu(resp->etype_used); 3793 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3794 stats->etype_free = le16_to_cpu(resp->etype_free); 3795 } 3796 3797 return status; 3798 } 3799 3800 /** 3801 * i40e_aq_alternate_read 3802 * @hw: pointer to the hardware structure 3803 * @reg_addr0: address of first dword to be read 3804 * @reg_val0: pointer for data read from 'reg_addr0' 3805 * @reg_addr1: address of second dword to be read 3806 * @reg_val1: pointer for data read from 'reg_addr1' 3807 * 3808 * Read one or two dwords from alternate structure. Fields are indicated 3809 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3810 * is not passed then only register at 'reg_addr0' is read. 3811 * 3812 **/ 3813 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 3814 u32 reg_addr0, u32 *reg_val0, 3815 u32 reg_addr1, u32 *reg_val1) 3816 { 3817 struct i40e_aq_desc desc; 3818 struct i40e_aqc_alternate_write *cmd_resp = 3819 (struct i40e_aqc_alternate_write *)&desc.params.raw; 3820 i40e_status status; 3821 3822 if (!reg_val0) 3823 return I40E_ERR_PARAM; 3824 3825 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3826 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3827 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3828 3829 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3830 3831 if (!status) { 3832 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3833 3834 if (reg_val1) 3835 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3836 } 3837 3838 return status; 3839 } 3840 3841 /** 3842 * i40e_aq_resume_port_tx 3843 * @hw: pointer to the hardware structure 3844 * @cmd_details: pointer to command details structure or NULL 3845 * 3846 * Resume port's Tx traffic 3847 **/ 3848 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 3849 struct i40e_asq_cmd_details *cmd_details) 3850 { 3851 struct i40e_aq_desc desc; 3852 i40e_status status; 3853 3854 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3855 3856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3857 3858 return status; 3859 } 3860 3861 /** 3862 * i40e_set_pci_config_data - store PCI bus info 3863 * @hw: pointer to hardware structure 3864 * @link_status: the link status word from PCI config space 3865 * 3866 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3867 **/ 3868 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3869 { 3870 hw->bus.type = i40e_bus_type_pci_express; 3871 3872 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3873 case PCI_EXP_LNKSTA_NLW_X1: 3874 hw->bus.width = i40e_bus_width_pcie_x1; 3875 break; 3876 case PCI_EXP_LNKSTA_NLW_X2: 3877 hw->bus.width = i40e_bus_width_pcie_x2; 3878 break; 3879 case PCI_EXP_LNKSTA_NLW_X4: 3880 hw->bus.width = i40e_bus_width_pcie_x4; 3881 break; 3882 case PCI_EXP_LNKSTA_NLW_X8: 3883 hw->bus.width = i40e_bus_width_pcie_x8; 3884 break; 3885 default: 3886 hw->bus.width = i40e_bus_width_unknown; 3887 break; 3888 } 3889 3890 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3891 case PCI_EXP_LNKSTA_CLS_2_5GB: 3892 hw->bus.speed = i40e_bus_speed_2500; 3893 break; 3894 case PCI_EXP_LNKSTA_CLS_5_0GB: 3895 hw->bus.speed = i40e_bus_speed_5000; 3896 break; 3897 case PCI_EXP_LNKSTA_CLS_8_0GB: 3898 hw->bus.speed = i40e_bus_speed_8000; 3899 break; 3900 default: 3901 hw->bus.speed = i40e_bus_speed_unknown; 3902 break; 3903 } 3904 } 3905 3906 /** 3907 * i40e_aq_debug_dump 3908 * @hw: pointer to the hardware structure 3909 * @cluster_id: specific cluster to dump 3910 * @table_id: table id within cluster 3911 * @start_index: index of line in the block to read 3912 * @buff_size: dump buffer size 3913 * @buff: dump buffer 3914 * @ret_buff_size: actual buffer size returned 3915 * @ret_next_table: next block to read 3916 * @ret_next_index: next index to read 3917 * 3918 * Dump internal FW/HW data for debug purposes. 3919 * 3920 **/ 3921 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 3922 u8 table_id, u32 start_index, u16 buff_size, 3923 void *buff, u16 *ret_buff_size, 3924 u8 *ret_next_table, u32 *ret_next_index, 3925 struct i40e_asq_cmd_details *cmd_details) 3926 { 3927 struct i40e_aq_desc desc; 3928 struct i40e_aqc_debug_dump_internals *cmd = 3929 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 3930 struct i40e_aqc_debug_dump_internals *resp = 3931 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 3932 i40e_status status; 3933 3934 if (buff_size == 0 || !buff) 3935 return I40E_ERR_PARAM; 3936 3937 i40e_fill_default_direct_cmd_desc(&desc, 3938 i40e_aqc_opc_debug_dump_internals); 3939 /* Indirect Command */ 3940 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3941 if (buff_size > I40E_AQ_LARGE_BUF) 3942 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3943 3944 cmd->cluster_id = cluster_id; 3945 cmd->table_id = table_id; 3946 cmd->idx = cpu_to_le32(start_index); 3947 3948 desc.datalen = cpu_to_le16(buff_size); 3949 3950 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3951 if (!status) { 3952 if (ret_buff_size) 3953 *ret_buff_size = le16_to_cpu(desc.datalen); 3954 if (ret_next_table) 3955 *ret_next_table = resp->table_id; 3956 if (ret_next_index) 3957 *ret_next_index = le32_to_cpu(resp->idx); 3958 } 3959 3960 return status; 3961 } 3962 3963 /** 3964 * i40e_read_bw_from_alt_ram 3965 * @hw: pointer to the hardware structure 3966 * @max_bw: pointer for max_bw read 3967 * @min_bw: pointer for min_bw read 3968 * @min_valid: pointer for bool that is true if min_bw is a valid value 3969 * @max_valid: pointer for bool that is true if max_bw is a valid value 3970 * 3971 * Read bw from the alternate ram for the given pf 3972 **/ 3973 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 3974 u32 *max_bw, u32 *min_bw, 3975 bool *min_valid, bool *max_valid) 3976 { 3977 i40e_status status; 3978 u32 max_bw_addr, min_bw_addr; 3979 3980 /* Calculate the address of the min/max bw registers */ 3981 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3982 I40E_ALT_STRUCT_MAX_BW_OFFSET + 3983 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3984 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3985 I40E_ALT_STRUCT_MIN_BW_OFFSET + 3986 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3987 3988 /* Read the bandwidths from alt ram */ 3989 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 3990 min_bw_addr, min_bw); 3991 3992 if (*min_bw & I40E_ALT_BW_VALID_MASK) 3993 *min_valid = true; 3994 else 3995 *min_valid = false; 3996 3997 if (*max_bw & I40E_ALT_BW_VALID_MASK) 3998 *max_valid = true; 3999 else 4000 *max_valid = false; 4001 4002 return status; 4003 } 4004 4005 /** 4006 * i40e_aq_configure_partition_bw 4007 * @hw: pointer to the hardware structure 4008 * @bw_data: Buffer holding valid pfs and bw limits 4009 * @cmd_details: pointer to command details 4010 * 4011 * Configure partitions guaranteed/max bw 4012 **/ 4013 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4014 struct i40e_aqc_configure_partition_bw_data *bw_data, 4015 struct i40e_asq_cmd_details *cmd_details) 4016 { 4017 i40e_status status; 4018 struct i40e_aq_desc desc; 4019 u16 bwd_size = sizeof(*bw_data); 4020 4021 i40e_fill_default_direct_cmd_desc(&desc, 4022 i40e_aqc_opc_configure_partition_bw); 4023 4024 /* Indirect command */ 4025 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4026 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4027 4028 if (bwd_size > I40E_AQ_LARGE_BUF) 4029 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4030 4031 desc.datalen = cpu_to_le16(bwd_size); 4032 4033 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4034 cmd_details); 4035 4036 return status; 4037 } 4038