1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include "i40e_virtchnl.h" 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_A: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 case I40E_DEV_ID_10G_BASE_T: 54 hw->mac.type = I40E_MAC_XL710; 55 break; 56 case I40E_DEV_ID_VF: 57 case I40E_DEV_ID_VF_HV: 58 hw->mac.type = I40E_MAC_VF; 59 break; 60 default: 61 hw->mac.type = I40E_MAC_GENERIC; 62 break; 63 } 64 } else { 65 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 66 } 67 68 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 69 hw->mac.type, status); 70 return status; 71 } 72 73 /** 74 * i40e_debug_aq 75 * @hw: debug mask related to admin queue 76 * @mask: debug mask 77 * @desc: pointer to admin queue descriptor 78 * @buffer: pointer to command buffer 79 * @buf_len: max length of buffer 80 * 81 * Dumps debug log about adminq command with descriptor contents. 82 **/ 83 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 84 void *buffer, u16 buf_len) 85 { 86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 87 u16 len = le16_to_cpu(aq_desc->datalen); 88 u8 *buf = (u8 *)buffer; 89 u16 i = 0; 90 91 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 92 return; 93 94 i40e_debug(hw, mask, 95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 96 le16_to_cpu(aq_desc->opcode), 97 le16_to_cpu(aq_desc->flags), 98 le16_to_cpu(aq_desc->datalen), 99 le16_to_cpu(aq_desc->retval)); 100 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 101 le32_to_cpu(aq_desc->cookie_high), 102 le32_to_cpu(aq_desc->cookie_low)); 103 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 104 le32_to_cpu(aq_desc->params.internal.param0), 105 le32_to_cpu(aq_desc->params.internal.param1)); 106 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 107 le32_to_cpu(aq_desc->params.external.addr_high), 108 le32_to_cpu(aq_desc->params.external.addr_low)); 109 110 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 111 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 112 if (buf_len < len) 113 len = buf_len; 114 /* write the full 16-byte chunks */ 115 for (i = 0; i < (len - 16); i += 16) 116 i40e_debug(hw, mask, 117 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 118 i, buf[i], buf[i + 1], buf[i + 2], 119 buf[i + 3], buf[i + 4], buf[i + 5], 120 buf[i + 6], buf[i + 7], buf[i + 8], 121 buf[i + 9], buf[i + 10], buf[i + 11], 122 buf[i + 12], buf[i + 13], buf[i + 14], 123 buf[i + 15]); 124 /* write whatever's left over without overrunning the buffer */ 125 if (i < len) { 126 char d_buf[80]; 127 int j = 0; 128 129 memset(d_buf, 0, sizeof(d_buf)); 130 j += sprintf(d_buf, "\t0x%04X ", i); 131 while (i < len) 132 j += sprintf(&d_buf[j], " %02X", buf[i++]); 133 i40e_debug(hw, mask, "%s\n", d_buf); 134 } 135 } 136 } 137 138 /** 139 * i40e_check_asq_alive 140 * @hw: pointer to the hw struct 141 * 142 * Returns true if Queue is enabled else false. 143 **/ 144 bool i40e_check_asq_alive(struct i40e_hw *hw) 145 { 146 if (hw->aq.asq.len) 147 return !!(rd32(hw, hw->aq.asq.len) & 148 I40E_PF_ATQLEN_ATQENABLE_MASK); 149 else 150 return false; 151 } 152 153 /** 154 * i40e_aq_queue_shutdown 155 * @hw: pointer to the hw struct 156 * @unloading: is the driver unloading itself 157 * 158 * Tell the Firmware that we're shutting down the AdminQ and whether 159 * or not the driver is unloading as well. 160 **/ 161 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 162 bool unloading) 163 { 164 struct i40e_aq_desc desc; 165 struct i40e_aqc_queue_shutdown *cmd = 166 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 167 i40e_status status; 168 169 i40e_fill_default_direct_cmd_desc(&desc, 170 i40e_aqc_opc_queue_shutdown); 171 172 if (unloading) 173 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 174 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 175 176 return status; 177 } 178 179 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 180 * hardware to a bit-field that can be used by SW to more easily determine the 181 * packet type. 182 * 183 * Macros are used to shorten the table lines and make this table human 184 * readable. 185 * 186 * We store the PTYPE in the top byte of the bit field - this is just so that 187 * we can check that the table doesn't have a row missing, as the index into 188 * the table should be the PTYPE. 189 * 190 * Typical work flow: 191 * 192 * IF NOT i40e_ptype_lookup[ptype].known 193 * THEN 194 * Packet is unknown 195 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 196 * Use the rest of the fields to look at the tunnels, inner protocols, etc 197 * ELSE 198 * Use the enum i40e_rx_l2_ptype to decode the packet type 199 * ENDIF 200 */ 201 202 /* macro to make the table lines short */ 203 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 204 { PTYPE, \ 205 1, \ 206 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 207 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 208 I40E_RX_PTYPE_##OUTER_FRAG, \ 209 I40E_RX_PTYPE_TUNNEL_##T, \ 210 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 211 I40E_RX_PTYPE_##TEF, \ 212 I40E_RX_PTYPE_INNER_PROT_##I, \ 213 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 214 215 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 216 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 217 218 /* shorter macros makes the table fit but are terse */ 219 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 220 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 221 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 222 223 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 224 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 225 /* L2 Packet types */ 226 I40E_PTT_UNUSED_ENTRY(0), 227 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 228 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 229 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 230 I40E_PTT_UNUSED_ENTRY(4), 231 I40E_PTT_UNUSED_ENTRY(5), 232 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 233 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 234 I40E_PTT_UNUSED_ENTRY(8), 235 I40E_PTT_UNUSED_ENTRY(9), 236 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 237 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 238 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 239 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 240 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 241 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 242 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 243 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 244 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 245 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 246 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 247 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 248 249 /* Non Tunneled IPv4 */ 250 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 251 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 252 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 253 I40E_PTT_UNUSED_ENTRY(25), 254 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 255 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 256 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 257 258 /* IPv4 --> IPv4 */ 259 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 260 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 261 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 262 I40E_PTT_UNUSED_ENTRY(32), 263 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 264 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 265 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 266 267 /* IPv4 --> IPv6 */ 268 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 269 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 270 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 271 I40E_PTT_UNUSED_ENTRY(39), 272 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 273 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 274 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 275 276 /* IPv4 --> GRE/NAT */ 277 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 278 279 /* IPv4 --> GRE/NAT --> IPv4 */ 280 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 281 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 282 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 283 I40E_PTT_UNUSED_ENTRY(47), 284 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 285 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 286 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 287 288 /* IPv4 --> GRE/NAT --> IPv6 */ 289 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 290 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 291 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 292 I40E_PTT_UNUSED_ENTRY(54), 293 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 294 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 295 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 296 297 /* IPv4 --> GRE/NAT --> MAC */ 298 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 299 300 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 301 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 302 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 303 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 304 I40E_PTT_UNUSED_ENTRY(62), 305 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 306 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 307 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 308 309 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 310 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 311 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 312 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 313 I40E_PTT_UNUSED_ENTRY(69), 314 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 315 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 316 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 317 318 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 319 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 320 321 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 322 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 323 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 324 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 325 I40E_PTT_UNUSED_ENTRY(77), 326 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 327 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 328 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 329 330 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 331 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 332 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 333 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 334 I40E_PTT_UNUSED_ENTRY(84), 335 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 336 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 337 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 338 339 /* Non Tunneled IPv6 */ 340 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 341 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 342 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 343 I40E_PTT_UNUSED_ENTRY(91), 344 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 345 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 346 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 347 348 /* IPv6 --> IPv4 */ 349 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 350 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 351 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 352 I40E_PTT_UNUSED_ENTRY(98), 353 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 354 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 355 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 356 357 /* IPv6 --> IPv6 */ 358 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 359 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 360 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 361 I40E_PTT_UNUSED_ENTRY(105), 362 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 363 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 364 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 365 366 /* IPv6 --> GRE/NAT */ 367 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 368 369 /* IPv6 --> GRE/NAT -> IPv4 */ 370 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 371 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 372 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 373 I40E_PTT_UNUSED_ENTRY(113), 374 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 375 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 376 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 377 378 /* IPv6 --> GRE/NAT -> IPv6 */ 379 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 380 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 381 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 382 I40E_PTT_UNUSED_ENTRY(120), 383 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 384 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 385 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 386 387 /* IPv6 --> GRE/NAT -> MAC */ 388 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 389 390 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 391 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 392 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 393 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 394 I40E_PTT_UNUSED_ENTRY(128), 395 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 396 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 397 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 398 399 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 400 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 401 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 402 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 403 I40E_PTT_UNUSED_ENTRY(135), 404 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 405 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 406 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 407 408 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 409 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 410 411 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 412 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 413 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 414 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 415 I40E_PTT_UNUSED_ENTRY(143), 416 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 417 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 418 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 419 420 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 421 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 422 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 423 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 424 I40E_PTT_UNUSED_ENTRY(150), 425 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 426 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 427 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 428 429 /* unused entries */ 430 I40E_PTT_UNUSED_ENTRY(154), 431 I40E_PTT_UNUSED_ENTRY(155), 432 I40E_PTT_UNUSED_ENTRY(156), 433 I40E_PTT_UNUSED_ENTRY(157), 434 I40E_PTT_UNUSED_ENTRY(158), 435 I40E_PTT_UNUSED_ENTRY(159), 436 437 I40E_PTT_UNUSED_ENTRY(160), 438 I40E_PTT_UNUSED_ENTRY(161), 439 I40E_PTT_UNUSED_ENTRY(162), 440 I40E_PTT_UNUSED_ENTRY(163), 441 I40E_PTT_UNUSED_ENTRY(164), 442 I40E_PTT_UNUSED_ENTRY(165), 443 I40E_PTT_UNUSED_ENTRY(166), 444 I40E_PTT_UNUSED_ENTRY(167), 445 I40E_PTT_UNUSED_ENTRY(168), 446 I40E_PTT_UNUSED_ENTRY(169), 447 448 I40E_PTT_UNUSED_ENTRY(170), 449 I40E_PTT_UNUSED_ENTRY(171), 450 I40E_PTT_UNUSED_ENTRY(172), 451 I40E_PTT_UNUSED_ENTRY(173), 452 I40E_PTT_UNUSED_ENTRY(174), 453 I40E_PTT_UNUSED_ENTRY(175), 454 I40E_PTT_UNUSED_ENTRY(176), 455 I40E_PTT_UNUSED_ENTRY(177), 456 I40E_PTT_UNUSED_ENTRY(178), 457 I40E_PTT_UNUSED_ENTRY(179), 458 459 I40E_PTT_UNUSED_ENTRY(180), 460 I40E_PTT_UNUSED_ENTRY(181), 461 I40E_PTT_UNUSED_ENTRY(182), 462 I40E_PTT_UNUSED_ENTRY(183), 463 I40E_PTT_UNUSED_ENTRY(184), 464 I40E_PTT_UNUSED_ENTRY(185), 465 I40E_PTT_UNUSED_ENTRY(186), 466 I40E_PTT_UNUSED_ENTRY(187), 467 I40E_PTT_UNUSED_ENTRY(188), 468 I40E_PTT_UNUSED_ENTRY(189), 469 470 I40E_PTT_UNUSED_ENTRY(190), 471 I40E_PTT_UNUSED_ENTRY(191), 472 I40E_PTT_UNUSED_ENTRY(192), 473 I40E_PTT_UNUSED_ENTRY(193), 474 I40E_PTT_UNUSED_ENTRY(194), 475 I40E_PTT_UNUSED_ENTRY(195), 476 I40E_PTT_UNUSED_ENTRY(196), 477 I40E_PTT_UNUSED_ENTRY(197), 478 I40E_PTT_UNUSED_ENTRY(198), 479 I40E_PTT_UNUSED_ENTRY(199), 480 481 I40E_PTT_UNUSED_ENTRY(200), 482 I40E_PTT_UNUSED_ENTRY(201), 483 I40E_PTT_UNUSED_ENTRY(202), 484 I40E_PTT_UNUSED_ENTRY(203), 485 I40E_PTT_UNUSED_ENTRY(204), 486 I40E_PTT_UNUSED_ENTRY(205), 487 I40E_PTT_UNUSED_ENTRY(206), 488 I40E_PTT_UNUSED_ENTRY(207), 489 I40E_PTT_UNUSED_ENTRY(208), 490 I40E_PTT_UNUSED_ENTRY(209), 491 492 I40E_PTT_UNUSED_ENTRY(210), 493 I40E_PTT_UNUSED_ENTRY(211), 494 I40E_PTT_UNUSED_ENTRY(212), 495 I40E_PTT_UNUSED_ENTRY(213), 496 I40E_PTT_UNUSED_ENTRY(214), 497 I40E_PTT_UNUSED_ENTRY(215), 498 I40E_PTT_UNUSED_ENTRY(216), 499 I40E_PTT_UNUSED_ENTRY(217), 500 I40E_PTT_UNUSED_ENTRY(218), 501 I40E_PTT_UNUSED_ENTRY(219), 502 503 I40E_PTT_UNUSED_ENTRY(220), 504 I40E_PTT_UNUSED_ENTRY(221), 505 I40E_PTT_UNUSED_ENTRY(222), 506 I40E_PTT_UNUSED_ENTRY(223), 507 I40E_PTT_UNUSED_ENTRY(224), 508 I40E_PTT_UNUSED_ENTRY(225), 509 I40E_PTT_UNUSED_ENTRY(226), 510 I40E_PTT_UNUSED_ENTRY(227), 511 I40E_PTT_UNUSED_ENTRY(228), 512 I40E_PTT_UNUSED_ENTRY(229), 513 514 I40E_PTT_UNUSED_ENTRY(230), 515 I40E_PTT_UNUSED_ENTRY(231), 516 I40E_PTT_UNUSED_ENTRY(232), 517 I40E_PTT_UNUSED_ENTRY(233), 518 I40E_PTT_UNUSED_ENTRY(234), 519 I40E_PTT_UNUSED_ENTRY(235), 520 I40E_PTT_UNUSED_ENTRY(236), 521 I40E_PTT_UNUSED_ENTRY(237), 522 I40E_PTT_UNUSED_ENTRY(238), 523 I40E_PTT_UNUSED_ENTRY(239), 524 525 I40E_PTT_UNUSED_ENTRY(240), 526 I40E_PTT_UNUSED_ENTRY(241), 527 I40E_PTT_UNUSED_ENTRY(242), 528 I40E_PTT_UNUSED_ENTRY(243), 529 I40E_PTT_UNUSED_ENTRY(244), 530 I40E_PTT_UNUSED_ENTRY(245), 531 I40E_PTT_UNUSED_ENTRY(246), 532 I40E_PTT_UNUSED_ENTRY(247), 533 I40E_PTT_UNUSED_ENTRY(248), 534 I40E_PTT_UNUSED_ENTRY(249), 535 536 I40E_PTT_UNUSED_ENTRY(250), 537 I40E_PTT_UNUSED_ENTRY(251), 538 I40E_PTT_UNUSED_ENTRY(252), 539 I40E_PTT_UNUSED_ENTRY(253), 540 I40E_PTT_UNUSED_ENTRY(254), 541 I40E_PTT_UNUSED_ENTRY(255) 542 }; 543 544 /** 545 * i40e_init_shared_code - Initialize the shared code 546 * @hw: pointer to hardware structure 547 * 548 * This assigns the MAC type and PHY code and inits the NVM. 549 * Does not touch the hardware. This function must be called prior to any 550 * other function in the shared code. The i40e_hw structure should be 551 * memset to 0 prior to calling this function. The following fields in 552 * hw structure should be filled in prior to calling this function: 553 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 554 * subsystem_vendor_id, and revision_id 555 **/ 556 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 557 { 558 i40e_status status = 0; 559 u32 port, ari, func_rid; 560 561 i40e_set_mac_type(hw); 562 563 switch (hw->mac.type) { 564 case I40E_MAC_XL710: 565 break; 566 default: 567 return I40E_ERR_DEVICE_NOT_SUPPORTED; 568 } 569 570 hw->phy.get_link_info = true; 571 572 /* Determine port number and PF number*/ 573 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 574 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 575 hw->port = (u8)port; 576 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 577 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 578 func_rid = rd32(hw, I40E_PF_FUNC_RID); 579 if (ari) 580 hw->pf_id = (u8)(func_rid & 0xff); 581 else 582 hw->pf_id = (u8)(func_rid & 0x7); 583 584 status = i40e_init_nvm(hw); 585 return status; 586 } 587 588 /** 589 * i40e_aq_mac_address_read - Retrieve the MAC addresses 590 * @hw: pointer to the hw struct 591 * @flags: a return indicator of what addresses were added to the addr store 592 * @addrs: the requestor's mac addr store 593 * @cmd_details: pointer to command details structure or NULL 594 **/ 595 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 596 u16 *flags, 597 struct i40e_aqc_mac_address_read_data *addrs, 598 struct i40e_asq_cmd_details *cmd_details) 599 { 600 struct i40e_aq_desc desc; 601 struct i40e_aqc_mac_address_read *cmd_data = 602 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 603 i40e_status status; 604 605 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 606 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 607 608 status = i40e_asq_send_command(hw, &desc, addrs, 609 sizeof(*addrs), cmd_details); 610 *flags = le16_to_cpu(cmd_data->command_flags); 611 612 return status; 613 } 614 615 /** 616 * i40e_aq_mac_address_write - Change the MAC addresses 617 * @hw: pointer to the hw struct 618 * @flags: indicates which MAC to be written 619 * @mac_addr: address to write 620 * @cmd_details: pointer to command details structure or NULL 621 **/ 622 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 623 u16 flags, u8 *mac_addr, 624 struct i40e_asq_cmd_details *cmd_details) 625 { 626 struct i40e_aq_desc desc; 627 struct i40e_aqc_mac_address_write *cmd_data = 628 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 629 i40e_status status; 630 631 i40e_fill_default_direct_cmd_desc(&desc, 632 i40e_aqc_opc_mac_address_write); 633 cmd_data->command_flags = cpu_to_le16(flags); 634 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 635 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 636 ((u32)mac_addr[3] << 16) | 637 ((u32)mac_addr[4] << 8) | 638 mac_addr[5]); 639 640 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 641 642 return status; 643 } 644 645 /** 646 * i40e_get_mac_addr - get MAC address 647 * @hw: pointer to the HW structure 648 * @mac_addr: pointer to MAC address 649 * 650 * Reads the adapter's MAC address from register 651 **/ 652 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 653 { 654 struct i40e_aqc_mac_address_read_data addrs; 655 i40e_status status; 656 u16 flags = 0; 657 658 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 659 660 if (flags & I40E_AQC_LAN_ADDR_VALID) 661 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 662 663 return status; 664 } 665 666 /** 667 * i40e_get_port_mac_addr - get Port MAC address 668 * @hw: pointer to the HW structure 669 * @mac_addr: pointer to Port MAC address 670 * 671 * Reads the adapter's Port MAC address 672 **/ 673 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 674 { 675 struct i40e_aqc_mac_address_read_data addrs; 676 i40e_status status; 677 u16 flags = 0; 678 679 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 680 if (status) 681 return status; 682 683 if (flags & I40E_AQC_PORT_ADDR_VALID) 684 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 685 else 686 status = I40E_ERR_INVALID_MAC_ADDR; 687 688 return status; 689 } 690 691 /** 692 * i40e_pre_tx_queue_cfg - pre tx queue configure 693 * @hw: pointer to the HW structure 694 * @queue: target PF queue index 695 * @enable: state change request 696 * 697 * Handles hw requirement to indicate intention to enable 698 * or disable target queue. 699 **/ 700 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 701 { 702 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 703 u32 reg_block = 0; 704 u32 reg_val; 705 706 if (abs_queue_idx >= 128) { 707 reg_block = abs_queue_idx / 128; 708 abs_queue_idx %= 128; 709 } 710 711 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 712 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 713 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 714 715 if (enable) 716 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 717 else 718 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 719 720 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 721 } 722 #ifdef I40E_FCOE 723 724 /** 725 * i40e_get_san_mac_addr - get SAN MAC address 726 * @hw: pointer to the HW structure 727 * @mac_addr: pointer to SAN MAC address 728 * 729 * Reads the adapter's SAN MAC address from NVM 730 **/ 731 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 732 { 733 struct i40e_aqc_mac_address_read_data addrs; 734 i40e_status status; 735 u16 flags = 0; 736 737 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 738 if (status) 739 return status; 740 741 if (flags & I40E_AQC_SAN_ADDR_VALID) 742 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac)); 743 else 744 status = I40E_ERR_INVALID_MAC_ADDR; 745 746 return status; 747 } 748 #endif 749 750 /** 751 * i40e_read_pba_string - Reads part number string from EEPROM 752 * @hw: pointer to hardware structure 753 * @pba_num: stores the part number string from the EEPROM 754 * @pba_num_size: part number string buffer length 755 * 756 * Reads the part number string from the EEPROM. 757 **/ 758 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 759 u32 pba_num_size) 760 { 761 i40e_status status = 0; 762 u16 pba_word = 0; 763 u16 pba_size = 0; 764 u16 pba_ptr = 0; 765 u16 i = 0; 766 767 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 768 if (status || (pba_word != 0xFAFA)) { 769 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 770 return status; 771 } 772 773 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 774 if (status) { 775 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 776 return status; 777 } 778 779 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 780 if (status) { 781 hw_dbg(hw, "Failed to read PBA Block size.\n"); 782 return status; 783 } 784 785 /* Subtract one to get PBA word count (PBA Size word is included in 786 * total size) 787 */ 788 pba_size--; 789 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 790 hw_dbg(hw, "Buffer to small for PBA data.\n"); 791 return I40E_ERR_PARAM; 792 } 793 794 for (i = 0; i < pba_size; i++) { 795 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 796 if (status) { 797 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 798 return status; 799 } 800 801 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 802 pba_num[(i * 2) + 1] = pba_word & 0xFF; 803 } 804 pba_num[(pba_size * 2)] = '\0'; 805 806 return status; 807 } 808 809 /** 810 * i40e_get_media_type - Gets media type 811 * @hw: pointer to the hardware structure 812 **/ 813 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 814 { 815 enum i40e_media_type media; 816 817 switch (hw->phy.link_info.phy_type) { 818 case I40E_PHY_TYPE_10GBASE_SR: 819 case I40E_PHY_TYPE_10GBASE_LR: 820 case I40E_PHY_TYPE_1000BASE_SX: 821 case I40E_PHY_TYPE_1000BASE_LX: 822 case I40E_PHY_TYPE_40GBASE_SR4: 823 case I40E_PHY_TYPE_40GBASE_LR4: 824 media = I40E_MEDIA_TYPE_FIBER; 825 break; 826 case I40E_PHY_TYPE_100BASE_TX: 827 case I40E_PHY_TYPE_1000BASE_T: 828 case I40E_PHY_TYPE_10GBASE_T: 829 media = I40E_MEDIA_TYPE_BASET; 830 break; 831 case I40E_PHY_TYPE_10GBASE_CR1_CU: 832 case I40E_PHY_TYPE_40GBASE_CR4_CU: 833 case I40E_PHY_TYPE_10GBASE_CR1: 834 case I40E_PHY_TYPE_40GBASE_CR4: 835 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 836 case I40E_PHY_TYPE_40GBASE_AOC: 837 case I40E_PHY_TYPE_10GBASE_AOC: 838 media = I40E_MEDIA_TYPE_DA; 839 break; 840 case I40E_PHY_TYPE_1000BASE_KX: 841 case I40E_PHY_TYPE_10GBASE_KX4: 842 case I40E_PHY_TYPE_10GBASE_KR: 843 case I40E_PHY_TYPE_40GBASE_KR4: 844 media = I40E_MEDIA_TYPE_BACKPLANE; 845 break; 846 case I40E_PHY_TYPE_SGMII: 847 case I40E_PHY_TYPE_XAUI: 848 case I40E_PHY_TYPE_XFI: 849 case I40E_PHY_TYPE_XLAUI: 850 case I40E_PHY_TYPE_XLPPI: 851 default: 852 media = I40E_MEDIA_TYPE_UNKNOWN; 853 break; 854 } 855 856 return media; 857 } 858 859 #define I40E_PF_RESET_WAIT_COUNT_A0 200 860 #define I40E_PF_RESET_WAIT_COUNT 110 861 /** 862 * i40e_pf_reset - Reset the PF 863 * @hw: pointer to the hardware structure 864 * 865 * Assuming someone else has triggered a global reset, 866 * assure the global reset is complete and then reset the PF 867 **/ 868 i40e_status i40e_pf_reset(struct i40e_hw *hw) 869 { 870 u32 cnt = 0; 871 u32 cnt1 = 0; 872 u32 reg = 0; 873 u32 grst_del; 874 875 /* Poll for Global Reset steady state in case of recent GRST. 876 * The grst delay value is in 100ms units, and we'll wait a 877 * couple counts longer to be sure we don't just miss the end. 878 */ 879 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 880 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 881 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 882 for (cnt = 0; cnt < grst_del + 2; cnt++) { 883 reg = rd32(hw, I40E_GLGEN_RSTAT); 884 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 885 break; 886 msleep(100); 887 } 888 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 889 hw_dbg(hw, "Global reset polling failed to complete.\n"); 890 return I40E_ERR_RESET_FAILED; 891 } 892 893 /* Now Wait for the FW to be ready */ 894 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 895 reg = rd32(hw, I40E_GLNVM_ULD); 896 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 897 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 898 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 899 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 900 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 901 break; 902 } 903 usleep_range(10000, 20000); 904 } 905 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 906 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 907 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 908 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 909 return I40E_ERR_RESET_FAILED; 910 } 911 912 /* If there was a Global Reset in progress when we got here, 913 * we don't need to do the PF Reset 914 */ 915 if (!cnt) { 916 if (hw->revision_id == 0) 917 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 918 else 919 cnt = I40E_PF_RESET_WAIT_COUNT; 920 reg = rd32(hw, I40E_PFGEN_CTRL); 921 wr32(hw, I40E_PFGEN_CTRL, 922 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 923 for (; cnt; cnt--) { 924 reg = rd32(hw, I40E_PFGEN_CTRL); 925 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 926 break; 927 usleep_range(1000, 2000); 928 } 929 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 930 hw_dbg(hw, "PF reset polling failed to complete.\n"); 931 return I40E_ERR_RESET_FAILED; 932 } 933 } 934 935 i40e_clear_pxe_mode(hw); 936 937 return 0; 938 } 939 940 /** 941 * i40e_clear_hw - clear out any left over hw state 942 * @hw: pointer to the hw struct 943 * 944 * Clear queues and interrupts, typically called at init time, 945 * but after the capabilities have been found so we know how many 946 * queues and msix vectors have been allocated. 947 **/ 948 void i40e_clear_hw(struct i40e_hw *hw) 949 { 950 u32 num_queues, base_queue; 951 u32 num_pf_int; 952 u32 num_vf_int; 953 u32 num_vfs; 954 u32 i, j; 955 u32 val; 956 u32 eol = 0x7ff; 957 958 /* get number of interrupts, queues, and VFs */ 959 val = rd32(hw, I40E_GLPCI_CNF2); 960 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 961 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 962 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 963 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 964 965 val = rd32(hw, I40E_PFLAN_QALLOC); 966 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 967 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 968 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 969 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 970 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 971 num_queues = (j - base_queue) + 1; 972 else 973 num_queues = 0; 974 975 val = rd32(hw, I40E_PF_VT_PFALLOC); 976 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 977 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 978 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 979 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 980 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 981 num_vfs = (j - i) + 1; 982 else 983 num_vfs = 0; 984 985 /* stop all the interrupts */ 986 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 987 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 988 for (i = 0; i < num_pf_int - 2; i++) 989 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 990 991 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 992 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 993 wr32(hw, I40E_PFINT_LNKLST0, val); 994 for (i = 0; i < num_pf_int - 2; i++) 995 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 996 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 997 for (i = 0; i < num_vfs; i++) 998 wr32(hw, I40E_VPINT_LNKLST0(i), val); 999 for (i = 0; i < num_vf_int - 2; i++) 1000 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1001 1002 /* warn the HW of the coming Tx disables */ 1003 for (i = 0; i < num_queues; i++) { 1004 u32 abs_queue_idx = base_queue + i; 1005 u32 reg_block = 0; 1006 1007 if (abs_queue_idx >= 128) { 1008 reg_block = abs_queue_idx / 128; 1009 abs_queue_idx %= 128; 1010 } 1011 1012 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1013 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1014 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1015 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1016 1017 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1018 } 1019 udelay(400); 1020 1021 /* stop all the queues */ 1022 for (i = 0; i < num_queues; i++) { 1023 wr32(hw, I40E_QINT_TQCTL(i), 0); 1024 wr32(hw, I40E_QTX_ENA(i), 0); 1025 wr32(hw, I40E_QINT_RQCTL(i), 0); 1026 wr32(hw, I40E_QRX_ENA(i), 0); 1027 } 1028 1029 /* short wait for all queue disables to settle */ 1030 udelay(50); 1031 } 1032 1033 /** 1034 * i40e_clear_pxe_mode - clear pxe operations mode 1035 * @hw: pointer to the hw struct 1036 * 1037 * Make sure all PXE mode settings are cleared, including things 1038 * like descriptor fetch/write-back mode. 1039 **/ 1040 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1041 { 1042 u32 reg; 1043 1044 if (i40e_check_asq_alive(hw)) 1045 i40e_aq_clear_pxe_mode(hw, NULL); 1046 1047 /* Clear single descriptor fetch/write-back mode */ 1048 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1049 1050 if (hw->revision_id == 0) { 1051 /* As a work around clear PXE_MODE instead of setting it */ 1052 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1053 } else { 1054 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1055 } 1056 } 1057 1058 /** 1059 * i40e_led_is_mine - helper to find matching led 1060 * @hw: pointer to the hw struct 1061 * @idx: index into GPIO registers 1062 * 1063 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1064 */ 1065 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1066 { 1067 u32 gpio_val = 0; 1068 u32 port; 1069 1070 if (!hw->func_caps.led[idx]) 1071 return 0; 1072 1073 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1074 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1075 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1076 1077 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1078 * if it is not our port then ignore 1079 */ 1080 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1081 (port != hw->port)) 1082 return 0; 1083 1084 return gpio_val; 1085 } 1086 1087 #define I40E_COMBINED_ACTIVITY 0xA 1088 #define I40E_FILTER_ACTIVITY 0xE 1089 #define I40E_LINK_ACTIVITY 0xC 1090 #define I40E_MAC_ACTIVITY 0xD 1091 #define I40E_LED0 22 1092 1093 /** 1094 * i40e_led_get - return current on/off mode 1095 * @hw: pointer to the hw struct 1096 * 1097 * The value returned is the 'mode' field as defined in the 1098 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1099 * values are variations of possible behaviors relating to 1100 * blink, link, and wire. 1101 **/ 1102 u32 i40e_led_get(struct i40e_hw *hw) 1103 { 1104 u32 current_mode = 0; 1105 u32 mode = 0; 1106 int i; 1107 1108 /* as per the documentation GPIO 22-29 are the LED 1109 * GPIO pins named LED0..LED7 1110 */ 1111 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1112 u32 gpio_val = i40e_led_is_mine(hw, i); 1113 1114 if (!gpio_val) 1115 continue; 1116 1117 /* ignore gpio LED src mode entries related to the activity 1118 * LEDs 1119 */ 1120 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1121 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1122 switch (current_mode) { 1123 case I40E_COMBINED_ACTIVITY: 1124 case I40E_FILTER_ACTIVITY: 1125 case I40E_MAC_ACTIVITY: 1126 continue; 1127 default: 1128 break; 1129 } 1130 1131 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1132 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1133 break; 1134 } 1135 1136 return mode; 1137 } 1138 1139 /** 1140 * i40e_led_set - set new on/off mode 1141 * @hw: pointer to the hw struct 1142 * @mode: 0=off, 0xf=on (else see manual for mode details) 1143 * @blink: true if the LED should blink when on, false if steady 1144 * 1145 * if this function is used to turn on the blink it should 1146 * be used to disable the blink when restoring the original state. 1147 **/ 1148 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1149 { 1150 u32 current_mode = 0; 1151 int i; 1152 1153 if (mode & 0xfffffff0) 1154 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1155 1156 /* as per the documentation GPIO 22-29 are the LED 1157 * GPIO pins named LED0..LED7 1158 */ 1159 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1160 u32 gpio_val = i40e_led_is_mine(hw, i); 1161 1162 if (!gpio_val) 1163 continue; 1164 1165 /* ignore gpio LED src mode entries related to the activity 1166 * LEDs 1167 */ 1168 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1169 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1170 switch (current_mode) { 1171 case I40E_COMBINED_ACTIVITY: 1172 case I40E_FILTER_ACTIVITY: 1173 case I40E_MAC_ACTIVITY: 1174 continue; 1175 default: 1176 break; 1177 } 1178 1179 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1180 /* this & is a bit of paranoia, but serves as a range check */ 1181 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1182 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1183 1184 if (mode == I40E_LINK_ACTIVITY) 1185 blink = false; 1186 1187 if (blink) 1188 gpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1189 else 1190 gpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1191 1192 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1193 break; 1194 } 1195 } 1196 1197 /* Admin command wrappers */ 1198 1199 /** 1200 * i40e_aq_get_phy_capabilities 1201 * @hw: pointer to the hw struct 1202 * @abilities: structure for PHY capabilities to be filled 1203 * @qualified_modules: report Qualified Modules 1204 * @report_init: report init capabilities (active are default) 1205 * @cmd_details: pointer to command details structure or NULL 1206 * 1207 * Returns the various PHY abilities supported on the Port. 1208 **/ 1209 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1210 bool qualified_modules, bool report_init, 1211 struct i40e_aq_get_phy_abilities_resp *abilities, 1212 struct i40e_asq_cmd_details *cmd_details) 1213 { 1214 struct i40e_aq_desc desc; 1215 i40e_status status; 1216 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1217 1218 if (!abilities) 1219 return I40E_ERR_PARAM; 1220 1221 i40e_fill_default_direct_cmd_desc(&desc, 1222 i40e_aqc_opc_get_phy_abilities); 1223 1224 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1225 if (abilities_size > I40E_AQ_LARGE_BUF) 1226 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1227 1228 if (qualified_modules) 1229 desc.params.external.param0 |= 1230 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1231 1232 if (report_init) 1233 desc.params.external.param0 |= 1234 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1235 1236 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1237 cmd_details); 1238 1239 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1240 status = I40E_ERR_UNKNOWN_PHY; 1241 1242 return status; 1243 } 1244 1245 /** 1246 * i40e_aq_set_phy_config 1247 * @hw: pointer to the hw struct 1248 * @config: structure with PHY configuration to be set 1249 * @cmd_details: pointer to command details structure or NULL 1250 * 1251 * Set the various PHY configuration parameters 1252 * supported on the Port.One or more of the Set PHY config parameters may be 1253 * ignored in an MFP mode as the PF may not have the privilege to set some 1254 * of the PHY Config parameters. This status will be indicated by the 1255 * command response. 1256 **/ 1257 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1258 struct i40e_aq_set_phy_config *config, 1259 struct i40e_asq_cmd_details *cmd_details) 1260 { 1261 struct i40e_aq_desc desc; 1262 struct i40e_aq_set_phy_config *cmd = 1263 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1264 enum i40e_status_code status; 1265 1266 if (!config) 1267 return I40E_ERR_PARAM; 1268 1269 i40e_fill_default_direct_cmd_desc(&desc, 1270 i40e_aqc_opc_set_phy_config); 1271 1272 *cmd = *config; 1273 1274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1275 1276 return status; 1277 } 1278 1279 /** 1280 * i40e_set_fc 1281 * @hw: pointer to the hw struct 1282 * 1283 * Set the requested flow control mode using set_phy_config. 1284 **/ 1285 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1286 bool atomic_restart) 1287 { 1288 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1289 struct i40e_aq_get_phy_abilities_resp abilities; 1290 struct i40e_aq_set_phy_config config; 1291 enum i40e_status_code status; 1292 u8 pause_mask = 0x0; 1293 1294 *aq_failures = 0x0; 1295 1296 switch (fc_mode) { 1297 case I40E_FC_FULL: 1298 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1299 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1300 break; 1301 case I40E_FC_RX_PAUSE: 1302 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1303 break; 1304 case I40E_FC_TX_PAUSE: 1305 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1306 break; 1307 default: 1308 break; 1309 } 1310 1311 /* Get the current phy config */ 1312 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1313 NULL); 1314 if (status) { 1315 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1316 return status; 1317 } 1318 1319 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1320 /* clear the old pause settings */ 1321 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1322 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1323 /* set the new abilities */ 1324 config.abilities |= pause_mask; 1325 /* If the abilities have changed, then set the new config */ 1326 if (config.abilities != abilities.abilities) { 1327 /* Auto restart link so settings take effect */ 1328 if (atomic_restart) 1329 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1330 /* Copy over all the old settings */ 1331 config.phy_type = abilities.phy_type; 1332 config.link_speed = abilities.link_speed; 1333 config.eee_capability = abilities.eee_capability; 1334 config.eeer = abilities.eeer_val; 1335 config.low_power_ctrl = abilities.d3_lpan; 1336 status = i40e_aq_set_phy_config(hw, &config, NULL); 1337 1338 if (status) 1339 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1340 } 1341 /* Update the link info */ 1342 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1343 if (status) { 1344 /* Wait a little bit (on 40G cards it sometimes takes a really 1345 * long time for link to come back from the atomic reset) 1346 * and try once more 1347 */ 1348 msleep(1000); 1349 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1350 } 1351 if (status) 1352 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1353 1354 return status; 1355 } 1356 1357 /** 1358 * i40e_aq_clear_pxe_mode 1359 * @hw: pointer to the hw struct 1360 * @cmd_details: pointer to command details structure or NULL 1361 * 1362 * Tell the firmware that the driver is taking over from PXE 1363 **/ 1364 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1365 struct i40e_asq_cmd_details *cmd_details) 1366 { 1367 i40e_status status; 1368 struct i40e_aq_desc desc; 1369 struct i40e_aqc_clear_pxe *cmd = 1370 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1371 1372 i40e_fill_default_direct_cmd_desc(&desc, 1373 i40e_aqc_opc_clear_pxe_mode); 1374 1375 cmd->rx_cnt = 0x2; 1376 1377 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1378 1379 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1380 1381 return status; 1382 } 1383 1384 /** 1385 * i40e_aq_set_link_restart_an 1386 * @hw: pointer to the hw struct 1387 * @enable_link: if true: enable link, if false: disable link 1388 * @cmd_details: pointer to command details structure or NULL 1389 * 1390 * Sets up the link and restarts the Auto-Negotiation over the link. 1391 **/ 1392 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1393 bool enable_link, 1394 struct i40e_asq_cmd_details *cmd_details) 1395 { 1396 struct i40e_aq_desc desc; 1397 struct i40e_aqc_set_link_restart_an *cmd = 1398 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1399 i40e_status status; 1400 1401 i40e_fill_default_direct_cmd_desc(&desc, 1402 i40e_aqc_opc_set_link_restart_an); 1403 1404 cmd->command = I40E_AQ_PHY_RESTART_AN; 1405 if (enable_link) 1406 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1407 else 1408 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1409 1410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1411 1412 return status; 1413 } 1414 1415 /** 1416 * i40e_aq_get_link_info 1417 * @hw: pointer to the hw struct 1418 * @enable_lse: enable/disable LinkStatusEvent reporting 1419 * @link: pointer to link status structure - optional 1420 * @cmd_details: pointer to command details structure or NULL 1421 * 1422 * Returns the link status of the adapter. 1423 **/ 1424 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1425 bool enable_lse, struct i40e_link_status *link, 1426 struct i40e_asq_cmd_details *cmd_details) 1427 { 1428 struct i40e_aq_desc desc; 1429 struct i40e_aqc_get_link_status *resp = 1430 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1431 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1432 i40e_status status; 1433 bool tx_pause, rx_pause; 1434 u16 command_flags; 1435 1436 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1437 1438 if (enable_lse) 1439 command_flags = I40E_AQ_LSE_ENABLE; 1440 else 1441 command_flags = I40E_AQ_LSE_DISABLE; 1442 resp->command_flags = cpu_to_le16(command_flags); 1443 1444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1445 1446 if (status) 1447 goto aq_get_link_info_exit; 1448 1449 /* save off old link status information */ 1450 hw->phy.link_info_old = *hw_link_info; 1451 1452 /* update link status */ 1453 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1454 hw->phy.media_type = i40e_get_media_type(hw); 1455 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1456 hw_link_info->link_info = resp->link_info; 1457 hw_link_info->an_info = resp->an_info; 1458 hw_link_info->ext_info = resp->ext_info; 1459 hw_link_info->loopback = resp->loopback; 1460 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1461 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1462 1463 /* update fc info */ 1464 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1465 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1466 if (tx_pause & rx_pause) 1467 hw->fc.current_mode = I40E_FC_FULL; 1468 else if (tx_pause) 1469 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1470 else if (rx_pause) 1471 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1472 else 1473 hw->fc.current_mode = I40E_FC_NONE; 1474 1475 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1476 hw_link_info->crc_enable = true; 1477 else 1478 hw_link_info->crc_enable = false; 1479 1480 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1481 hw_link_info->lse_enable = true; 1482 else 1483 hw_link_info->lse_enable = false; 1484 1485 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1486 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1487 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1488 1489 /* save link status information */ 1490 if (link) 1491 *link = *hw_link_info; 1492 1493 /* flag cleared so helper functions don't call AQ again */ 1494 hw->phy.get_link_info = false; 1495 1496 aq_get_link_info_exit: 1497 return status; 1498 } 1499 1500 /** 1501 * i40e_aq_set_phy_int_mask 1502 * @hw: pointer to the hw struct 1503 * @mask: interrupt mask to be set 1504 * @cmd_details: pointer to command details structure or NULL 1505 * 1506 * Set link interrupt mask. 1507 **/ 1508 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1509 u16 mask, 1510 struct i40e_asq_cmd_details *cmd_details) 1511 { 1512 struct i40e_aq_desc desc; 1513 struct i40e_aqc_set_phy_int_mask *cmd = 1514 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1515 i40e_status status; 1516 1517 i40e_fill_default_direct_cmd_desc(&desc, 1518 i40e_aqc_opc_set_phy_int_mask); 1519 1520 cmd->event_mask = cpu_to_le16(mask); 1521 1522 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1523 1524 return status; 1525 } 1526 1527 /** 1528 * i40e_aq_add_vsi 1529 * @hw: pointer to the hw struct 1530 * @vsi_ctx: pointer to a vsi context struct 1531 * @cmd_details: pointer to command details structure or NULL 1532 * 1533 * Add a VSI context to the hardware. 1534 **/ 1535 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1536 struct i40e_vsi_context *vsi_ctx, 1537 struct i40e_asq_cmd_details *cmd_details) 1538 { 1539 struct i40e_aq_desc desc; 1540 struct i40e_aqc_add_get_update_vsi *cmd = 1541 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1542 struct i40e_aqc_add_get_update_vsi_completion *resp = 1543 (struct i40e_aqc_add_get_update_vsi_completion *) 1544 &desc.params.raw; 1545 i40e_status status; 1546 1547 i40e_fill_default_direct_cmd_desc(&desc, 1548 i40e_aqc_opc_add_vsi); 1549 1550 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1551 cmd->connection_type = vsi_ctx->connection_type; 1552 cmd->vf_id = vsi_ctx->vf_num; 1553 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1554 1555 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1556 1557 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1558 sizeof(vsi_ctx->info), cmd_details); 1559 1560 if (status) 1561 goto aq_add_vsi_exit; 1562 1563 vsi_ctx->seid = le16_to_cpu(resp->seid); 1564 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1565 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1566 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1567 1568 aq_add_vsi_exit: 1569 return status; 1570 } 1571 1572 /** 1573 * i40e_aq_set_vsi_unicast_promiscuous 1574 * @hw: pointer to the hw struct 1575 * @seid: vsi number 1576 * @set: set unicast promiscuous enable/disable 1577 * @cmd_details: pointer to command details structure or NULL 1578 **/ 1579 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1580 u16 seid, bool set, 1581 struct i40e_asq_cmd_details *cmd_details) 1582 { 1583 struct i40e_aq_desc desc; 1584 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1585 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1586 i40e_status status; 1587 u16 flags = 0; 1588 1589 i40e_fill_default_direct_cmd_desc(&desc, 1590 i40e_aqc_opc_set_vsi_promiscuous_modes); 1591 1592 if (set) 1593 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1594 1595 cmd->promiscuous_flags = cpu_to_le16(flags); 1596 1597 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1598 1599 cmd->seid = cpu_to_le16(seid); 1600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1601 1602 return status; 1603 } 1604 1605 /** 1606 * i40e_aq_set_vsi_multicast_promiscuous 1607 * @hw: pointer to the hw struct 1608 * @seid: vsi number 1609 * @set: set multicast promiscuous enable/disable 1610 * @cmd_details: pointer to command details structure or NULL 1611 **/ 1612 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1613 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1614 { 1615 struct i40e_aq_desc desc; 1616 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1617 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1618 i40e_status status; 1619 u16 flags = 0; 1620 1621 i40e_fill_default_direct_cmd_desc(&desc, 1622 i40e_aqc_opc_set_vsi_promiscuous_modes); 1623 1624 if (set) 1625 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1626 1627 cmd->promiscuous_flags = cpu_to_le16(flags); 1628 1629 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1630 1631 cmd->seid = cpu_to_le16(seid); 1632 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1633 1634 return status; 1635 } 1636 1637 /** 1638 * i40e_aq_set_vsi_broadcast 1639 * @hw: pointer to the hw struct 1640 * @seid: vsi number 1641 * @set_filter: true to set filter, false to clear filter 1642 * @cmd_details: pointer to command details structure or NULL 1643 * 1644 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1645 **/ 1646 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1647 u16 seid, bool set_filter, 1648 struct i40e_asq_cmd_details *cmd_details) 1649 { 1650 struct i40e_aq_desc desc; 1651 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1652 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1653 i40e_status status; 1654 1655 i40e_fill_default_direct_cmd_desc(&desc, 1656 i40e_aqc_opc_set_vsi_promiscuous_modes); 1657 1658 if (set_filter) 1659 cmd->promiscuous_flags 1660 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1661 else 1662 cmd->promiscuous_flags 1663 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1664 1665 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1666 cmd->seid = cpu_to_le16(seid); 1667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1668 1669 return status; 1670 } 1671 1672 /** 1673 * i40e_get_vsi_params - get VSI configuration info 1674 * @hw: pointer to the hw struct 1675 * @vsi_ctx: pointer to a vsi context struct 1676 * @cmd_details: pointer to command details structure or NULL 1677 **/ 1678 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 1679 struct i40e_vsi_context *vsi_ctx, 1680 struct i40e_asq_cmd_details *cmd_details) 1681 { 1682 struct i40e_aq_desc desc; 1683 struct i40e_aqc_add_get_update_vsi *cmd = 1684 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1685 struct i40e_aqc_add_get_update_vsi_completion *resp = 1686 (struct i40e_aqc_add_get_update_vsi_completion *) 1687 &desc.params.raw; 1688 i40e_status status; 1689 1690 i40e_fill_default_direct_cmd_desc(&desc, 1691 i40e_aqc_opc_get_vsi_parameters); 1692 1693 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1694 1695 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1696 1697 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1698 sizeof(vsi_ctx->info), NULL); 1699 1700 if (status) 1701 goto aq_get_vsi_params_exit; 1702 1703 vsi_ctx->seid = le16_to_cpu(resp->seid); 1704 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1705 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1706 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1707 1708 aq_get_vsi_params_exit: 1709 return status; 1710 } 1711 1712 /** 1713 * i40e_aq_update_vsi_params 1714 * @hw: pointer to the hw struct 1715 * @vsi_ctx: pointer to a vsi context struct 1716 * @cmd_details: pointer to command details structure or NULL 1717 * 1718 * Update a VSI context. 1719 **/ 1720 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 1721 struct i40e_vsi_context *vsi_ctx, 1722 struct i40e_asq_cmd_details *cmd_details) 1723 { 1724 struct i40e_aq_desc desc; 1725 struct i40e_aqc_add_get_update_vsi *cmd = 1726 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1727 i40e_status status; 1728 1729 i40e_fill_default_direct_cmd_desc(&desc, 1730 i40e_aqc_opc_update_vsi_parameters); 1731 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1732 1733 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1734 1735 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1736 sizeof(vsi_ctx->info), cmd_details); 1737 1738 return status; 1739 } 1740 1741 /** 1742 * i40e_aq_get_switch_config 1743 * @hw: pointer to the hardware structure 1744 * @buf: pointer to the result buffer 1745 * @buf_size: length of input buffer 1746 * @start_seid: seid to start for the report, 0 == beginning 1747 * @cmd_details: pointer to command details structure or NULL 1748 * 1749 * Fill the buf with switch configuration returned from AdminQ command 1750 **/ 1751 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 1752 struct i40e_aqc_get_switch_config_resp *buf, 1753 u16 buf_size, u16 *start_seid, 1754 struct i40e_asq_cmd_details *cmd_details) 1755 { 1756 struct i40e_aq_desc desc; 1757 struct i40e_aqc_switch_seid *scfg = 1758 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1759 i40e_status status; 1760 1761 i40e_fill_default_direct_cmd_desc(&desc, 1762 i40e_aqc_opc_get_switch_config); 1763 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1764 if (buf_size > I40E_AQ_LARGE_BUF) 1765 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1766 scfg->seid = cpu_to_le16(*start_seid); 1767 1768 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1769 *start_seid = le16_to_cpu(scfg->seid); 1770 1771 return status; 1772 } 1773 1774 /** 1775 * i40e_aq_get_firmware_version 1776 * @hw: pointer to the hw struct 1777 * @fw_major_version: firmware major version 1778 * @fw_minor_version: firmware minor version 1779 * @fw_build: firmware build number 1780 * @api_major_version: major queue version 1781 * @api_minor_version: minor queue version 1782 * @cmd_details: pointer to command details structure or NULL 1783 * 1784 * Get the firmware version from the admin queue commands 1785 **/ 1786 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 1787 u16 *fw_major_version, u16 *fw_minor_version, 1788 u32 *fw_build, 1789 u16 *api_major_version, u16 *api_minor_version, 1790 struct i40e_asq_cmd_details *cmd_details) 1791 { 1792 struct i40e_aq_desc desc; 1793 struct i40e_aqc_get_version *resp = 1794 (struct i40e_aqc_get_version *)&desc.params.raw; 1795 i40e_status status; 1796 1797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1798 1799 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1800 1801 if (!status) { 1802 if (fw_major_version) 1803 *fw_major_version = le16_to_cpu(resp->fw_major); 1804 if (fw_minor_version) 1805 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1806 if (fw_build) 1807 *fw_build = le32_to_cpu(resp->fw_build); 1808 if (api_major_version) 1809 *api_major_version = le16_to_cpu(resp->api_major); 1810 if (api_minor_version) 1811 *api_minor_version = le16_to_cpu(resp->api_minor); 1812 } 1813 1814 return status; 1815 } 1816 1817 /** 1818 * i40e_aq_send_driver_version 1819 * @hw: pointer to the hw struct 1820 * @dv: driver's major, minor version 1821 * @cmd_details: pointer to command details structure or NULL 1822 * 1823 * Send the driver version to the firmware 1824 **/ 1825 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 1826 struct i40e_driver_version *dv, 1827 struct i40e_asq_cmd_details *cmd_details) 1828 { 1829 struct i40e_aq_desc desc; 1830 struct i40e_aqc_driver_version *cmd = 1831 (struct i40e_aqc_driver_version *)&desc.params.raw; 1832 i40e_status status; 1833 u16 len; 1834 1835 if (dv == NULL) 1836 return I40E_ERR_PARAM; 1837 1838 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1839 1840 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 1841 cmd->driver_major_ver = dv->major_version; 1842 cmd->driver_minor_ver = dv->minor_version; 1843 cmd->driver_build_ver = dv->build_version; 1844 cmd->driver_subbuild_ver = dv->subbuild_version; 1845 1846 len = 0; 1847 while (len < sizeof(dv->driver_string) && 1848 (dv->driver_string[len] < 0x80) && 1849 dv->driver_string[len]) 1850 len++; 1851 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1852 len, cmd_details); 1853 1854 return status; 1855 } 1856 1857 /** 1858 * i40e_get_link_status - get status of the HW network link 1859 * @hw: pointer to the hw struct 1860 * 1861 * Returns true if link is up, false if link is down. 1862 * 1863 * Side effect: LinkStatusEvent reporting becomes enabled 1864 **/ 1865 bool i40e_get_link_status(struct i40e_hw *hw) 1866 { 1867 i40e_status status = 0; 1868 bool link_status = false; 1869 1870 if (hw->phy.get_link_info) { 1871 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1872 1873 if (status) 1874 goto i40e_get_link_status_exit; 1875 } 1876 1877 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 1878 1879 i40e_get_link_status_exit: 1880 return link_status; 1881 } 1882 1883 /** 1884 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 1885 * @hw: pointer to the hw struct 1886 * @uplink_seid: the MAC or other gizmo SEID 1887 * @downlink_seid: the VSI SEID 1888 * @enabled_tc: bitmap of TCs to be enabled 1889 * @default_port: true for default port VSI, false for control port 1890 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support 1891 * @veb_seid: pointer to where to put the resulting VEB SEID 1892 * @cmd_details: pointer to command details structure or NULL 1893 * 1894 * This asks the FW to add a VEB between the uplink and downlink 1895 * elements. If the uplink SEID is 0, this will be a floating VEB. 1896 **/ 1897 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 1898 u16 downlink_seid, u8 enabled_tc, 1899 bool default_port, bool enable_l2_filtering, 1900 u16 *veb_seid, 1901 struct i40e_asq_cmd_details *cmd_details) 1902 { 1903 struct i40e_aq_desc desc; 1904 struct i40e_aqc_add_veb *cmd = 1905 (struct i40e_aqc_add_veb *)&desc.params.raw; 1906 struct i40e_aqc_add_veb_completion *resp = 1907 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 1908 i40e_status status; 1909 u16 veb_flags = 0; 1910 1911 /* SEIDs need to either both be set or both be 0 for floating VEB */ 1912 if (!!uplink_seid != !!downlink_seid) 1913 return I40E_ERR_PARAM; 1914 1915 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 1916 1917 cmd->uplink_seid = cpu_to_le16(uplink_seid); 1918 cmd->downlink_seid = cpu_to_le16(downlink_seid); 1919 cmd->enable_tcs = enabled_tc; 1920 if (!uplink_seid) 1921 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 1922 if (default_port) 1923 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 1924 else 1925 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 1926 1927 if (enable_l2_filtering) 1928 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 1929 1930 cmd->veb_flags = cpu_to_le16(veb_flags); 1931 1932 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1933 1934 if (!status && veb_seid) 1935 *veb_seid = le16_to_cpu(resp->veb_seid); 1936 1937 return status; 1938 } 1939 1940 /** 1941 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 1942 * @hw: pointer to the hw struct 1943 * @veb_seid: the SEID of the VEB to query 1944 * @switch_id: the uplink switch id 1945 * @floating: set to true if the VEB is floating 1946 * @statistic_index: index of the stats counter block for this VEB 1947 * @vebs_used: number of VEB's used by function 1948 * @vebs_free: total VEB's not reserved by any function 1949 * @cmd_details: pointer to command details structure or NULL 1950 * 1951 * This retrieves the parameters for a particular VEB, specified by 1952 * uplink_seid, and returns them to the caller. 1953 **/ 1954 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 1955 u16 veb_seid, u16 *switch_id, 1956 bool *floating, u16 *statistic_index, 1957 u16 *vebs_used, u16 *vebs_free, 1958 struct i40e_asq_cmd_details *cmd_details) 1959 { 1960 struct i40e_aq_desc desc; 1961 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 1962 (struct i40e_aqc_get_veb_parameters_completion *) 1963 &desc.params.raw; 1964 i40e_status status; 1965 1966 if (veb_seid == 0) 1967 return I40E_ERR_PARAM; 1968 1969 i40e_fill_default_direct_cmd_desc(&desc, 1970 i40e_aqc_opc_get_veb_parameters); 1971 cmd_resp->seid = cpu_to_le16(veb_seid); 1972 1973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1974 if (status) 1975 goto get_veb_exit; 1976 1977 if (switch_id) 1978 *switch_id = le16_to_cpu(cmd_resp->switch_id); 1979 if (statistic_index) 1980 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 1981 if (vebs_used) 1982 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 1983 if (vebs_free) 1984 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 1985 if (floating) { 1986 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 1987 if (flags & I40E_AQC_ADD_VEB_FLOATING) 1988 *floating = true; 1989 else 1990 *floating = false; 1991 } 1992 1993 get_veb_exit: 1994 return status; 1995 } 1996 1997 /** 1998 * i40e_aq_add_macvlan 1999 * @hw: pointer to the hw struct 2000 * @seid: VSI for the mac address 2001 * @mv_list: list of macvlans to be added 2002 * @count: length of the list 2003 * @cmd_details: pointer to command details structure or NULL 2004 * 2005 * Add MAC/VLAN addresses to the HW filtering 2006 **/ 2007 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2008 struct i40e_aqc_add_macvlan_element_data *mv_list, 2009 u16 count, struct i40e_asq_cmd_details *cmd_details) 2010 { 2011 struct i40e_aq_desc desc; 2012 struct i40e_aqc_macvlan *cmd = 2013 (struct i40e_aqc_macvlan *)&desc.params.raw; 2014 i40e_status status; 2015 u16 buf_size; 2016 2017 if (count == 0 || !mv_list || !hw) 2018 return I40E_ERR_PARAM; 2019 2020 buf_size = count * sizeof(*mv_list); 2021 2022 /* prep the rest of the request */ 2023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2024 cmd->num_addresses = cpu_to_le16(count); 2025 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2026 cmd->seid[1] = 0; 2027 cmd->seid[2] = 0; 2028 2029 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2030 if (buf_size > I40E_AQ_LARGE_BUF) 2031 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2032 2033 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2034 cmd_details); 2035 2036 return status; 2037 } 2038 2039 /** 2040 * i40e_aq_remove_macvlan 2041 * @hw: pointer to the hw struct 2042 * @seid: VSI for the mac address 2043 * @mv_list: list of macvlans to be removed 2044 * @count: length of the list 2045 * @cmd_details: pointer to command details structure or NULL 2046 * 2047 * Remove MAC/VLAN addresses from the HW filtering 2048 **/ 2049 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2050 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2051 u16 count, struct i40e_asq_cmd_details *cmd_details) 2052 { 2053 struct i40e_aq_desc desc; 2054 struct i40e_aqc_macvlan *cmd = 2055 (struct i40e_aqc_macvlan *)&desc.params.raw; 2056 i40e_status status; 2057 u16 buf_size; 2058 2059 if (count == 0 || !mv_list || !hw) 2060 return I40E_ERR_PARAM; 2061 2062 buf_size = count * sizeof(*mv_list); 2063 2064 /* prep the rest of the request */ 2065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2066 cmd->num_addresses = cpu_to_le16(count); 2067 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2068 cmd->seid[1] = 0; 2069 cmd->seid[2] = 0; 2070 2071 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2072 if (buf_size > I40E_AQ_LARGE_BUF) 2073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2074 2075 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2076 cmd_details); 2077 2078 return status; 2079 } 2080 2081 /** 2082 * i40e_aq_send_msg_to_vf 2083 * @hw: pointer to the hardware structure 2084 * @vfid: VF id to send msg 2085 * @v_opcode: opcodes for VF-PF communication 2086 * @v_retval: return error code 2087 * @msg: pointer to the msg buffer 2088 * @msglen: msg length 2089 * @cmd_details: pointer to command details 2090 * 2091 * send msg to vf 2092 **/ 2093 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2094 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2095 struct i40e_asq_cmd_details *cmd_details) 2096 { 2097 struct i40e_aq_desc desc; 2098 struct i40e_aqc_pf_vf_message *cmd = 2099 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2100 i40e_status status; 2101 2102 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2103 cmd->id = cpu_to_le32(vfid); 2104 desc.cookie_high = cpu_to_le32(v_opcode); 2105 desc.cookie_low = cpu_to_le32(v_retval); 2106 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2107 if (msglen) { 2108 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2109 I40E_AQ_FLAG_RD)); 2110 if (msglen > I40E_AQ_LARGE_BUF) 2111 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2112 desc.datalen = cpu_to_le16(msglen); 2113 } 2114 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2115 2116 return status; 2117 } 2118 2119 /** 2120 * i40e_aq_debug_read_register 2121 * @hw: pointer to the hw struct 2122 * @reg_addr: register address 2123 * @reg_val: register value 2124 * @cmd_details: pointer to command details structure or NULL 2125 * 2126 * Read the register using the admin queue commands 2127 **/ 2128 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2129 u32 reg_addr, u64 *reg_val, 2130 struct i40e_asq_cmd_details *cmd_details) 2131 { 2132 struct i40e_aq_desc desc; 2133 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2134 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2135 i40e_status status; 2136 2137 if (reg_val == NULL) 2138 return I40E_ERR_PARAM; 2139 2140 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2141 2142 cmd_resp->address = cpu_to_le32(reg_addr); 2143 2144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2145 2146 if (!status) { 2147 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2148 (u64)le32_to_cpu(cmd_resp->value_low); 2149 } 2150 2151 return status; 2152 } 2153 2154 /** 2155 * i40e_aq_debug_write_register 2156 * @hw: pointer to the hw struct 2157 * @reg_addr: register address 2158 * @reg_val: register value 2159 * @cmd_details: pointer to command details structure or NULL 2160 * 2161 * Write to a register using the admin queue commands 2162 **/ 2163 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2164 u32 reg_addr, u64 reg_val, 2165 struct i40e_asq_cmd_details *cmd_details) 2166 { 2167 struct i40e_aq_desc desc; 2168 struct i40e_aqc_debug_reg_read_write *cmd = 2169 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2170 i40e_status status; 2171 2172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2173 2174 cmd->address = cpu_to_le32(reg_addr); 2175 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2176 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2177 2178 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2179 2180 return status; 2181 } 2182 2183 /** 2184 * i40e_aq_set_hmc_resource_profile 2185 * @hw: pointer to the hw struct 2186 * @profile: type of profile the HMC is to be set as 2187 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2188 * @cmd_details: pointer to command details structure or NULL 2189 * 2190 * set the HMC profile of the device. 2191 **/ 2192 i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2193 enum i40e_aq_hmc_profile profile, 2194 u8 pe_vf_enabled_count, 2195 struct i40e_asq_cmd_details *cmd_details) 2196 { 2197 struct i40e_aq_desc desc; 2198 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2199 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2200 i40e_status status; 2201 2202 i40e_fill_default_direct_cmd_desc(&desc, 2203 i40e_aqc_opc_set_hmc_resource_profile); 2204 2205 cmd->pm_profile = (u8)profile; 2206 cmd->pe_vf_enabled = pe_vf_enabled_count; 2207 2208 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2209 2210 return status; 2211 } 2212 2213 /** 2214 * i40e_aq_request_resource 2215 * @hw: pointer to the hw struct 2216 * @resource: resource id 2217 * @access: access type 2218 * @sdp_number: resource number 2219 * @timeout: the maximum time in ms that the driver may hold the resource 2220 * @cmd_details: pointer to command details structure or NULL 2221 * 2222 * requests common resource using the admin queue commands 2223 **/ 2224 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2225 enum i40e_aq_resources_ids resource, 2226 enum i40e_aq_resource_access_type access, 2227 u8 sdp_number, u64 *timeout, 2228 struct i40e_asq_cmd_details *cmd_details) 2229 { 2230 struct i40e_aq_desc desc; 2231 struct i40e_aqc_request_resource *cmd_resp = 2232 (struct i40e_aqc_request_resource *)&desc.params.raw; 2233 i40e_status status; 2234 2235 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2236 2237 cmd_resp->resource_id = cpu_to_le16(resource); 2238 cmd_resp->access_type = cpu_to_le16(access); 2239 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2240 2241 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2242 /* The completion specifies the maximum time in ms that the driver 2243 * may hold the resource in the Timeout field. 2244 * If the resource is held by someone else, the command completes with 2245 * busy return value and the timeout field indicates the maximum time 2246 * the current owner of the resource has to free it. 2247 */ 2248 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2249 *timeout = le32_to_cpu(cmd_resp->timeout); 2250 2251 return status; 2252 } 2253 2254 /** 2255 * i40e_aq_release_resource 2256 * @hw: pointer to the hw struct 2257 * @resource: resource id 2258 * @sdp_number: resource number 2259 * @cmd_details: pointer to command details structure or NULL 2260 * 2261 * release common resource using the admin queue commands 2262 **/ 2263 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2264 enum i40e_aq_resources_ids resource, 2265 u8 sdp_number, 2266 struct i40e_asq_cmd_details *cmd_details) 2267 { 2268 struct i40e_aq_desc desc; 2269 struct i40e_aqc_request_resource *cmd = 2270 (struct i40e_aqc_request_resource *)&desc.params.raw; 2271 i40e_status status; 2272 2273 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2274 2275 cmd->resource_id = cpu_to_le16(resource); 2276 cmd->resource_number = cpu_to_le32(sdp_number); 2277 2278 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2279 2280 return status; 2281 } 2282 2283 /** 2284 * i40e_aq_read_nvm 2285 * @hw: pointer to the hw struct 2286 * @module_pointer: module pointer location in words from the NVM beginning 2287 * @offset: byte offset from the module beginning 2288 * @length: length of the section to be read (in bytes from the offset) 2289 * @data: command buffer (size [bytes] = length) 2290 * @last_command: tells if this is the last command in a series 2291 * @cmd_details: pointer to command details structure or NULL 2292 * 2293 * Read the NVM using the admin queue commands 2294 **/ 2295 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2296 u32 offset, u16 length, void *data, 2297 bool last_command, 2298 struct i40e_asq_cmd_details *cmd_details) 2299 { 2300 struct i40e_aq_desc desc; 2301 struct i40e_aqc_nvm_update *cmd = 2302 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2303 i40e_status status; 2304 2305 /* In offset the highest byte must be zeroed. */ 2306 if (offset & 0xFF000000) { 2307 status = I40E_ERR_PARAM; 2308 goto i40e_aq_read_nvm_exit; 2309 } 2310 2311 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2312 2313 /* If this is the last command in a series, set the proper flag. */ 2314 if (last_command) 2315 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2316 cmd->module_pointer = module_pointer; 2317 cmd->offset = cpu_to_le32(offset); 2318 cmd->length = cpu_to_le16(length); 2319 2320 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2321 if (length > I40E_AQ_LARGE_BUF) 2322 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2323 2324 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2325 2326 i40e_aq_read_nvm_exit: 2327 return status; 2328 } 2329 2330 /** 2331 * i40e_aq_erase_nvm 2332 * @hw: pointer to the hw struct 2333 * @module_pointer: module pointer location in words from the NVM beginning 2334 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2335 * @length: length of the section to be erased (expressed in 4 KB) 2336 * @last_command: tells if this is the last command in a series 2337 * @cmd_details: pointer to command details structure or NULL 2338 * 2339 * Erase the NVM sector using the admin queue commands 2340 **/ 2341 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2342 u32 offset, u16 length, bool last_command, 2343 struct i40e_asq_cmd_details *cmd_details) 2344 { 2345 struct i40e_aq_desc desc; 2346 struct i40e_aqc_nvm_update *cmd = 2347 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2348 i40e_status status; 2349 2350 /* In offset the highest byte must be zeroed. */ 2351 if (offset & 0xFF000000) { 2352 status = I40E_ERR_PARAM; 2353 goto i40e_aq_erase_nvm_exit; 2354 } 2355 2356 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2357 2358 /* If this is the last command in a series, set the proper flag. */ 2359 if (last_command) 2360 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2361 cmd->module_pointer = module_pointer; 2362 cmd->offset = cpu_to_le32(offset); 2363 cmd->length = cpu_to_le16(length); 2364 2365 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2366 2367 i40e_aq_erase_nvm_exit: 2368 return status; 2369 } 2370 2371 #define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2372 #define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2373 #define I40E_DEV_FUNC_CAP_NPAR 0x03 2374 #define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2375 #define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2376 #define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2377 #define I40E_DEV_FUNC_CAP_VF 0x13 2378 #define I40E_DEV_FUNC_CAP_VMDQ 0x14 2379 #define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2380 #define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2381 #define I40E_DEV_FUNC_CAP_VSI 0x17 2382 #define I40E_DEV_FUNC_CAP_DCB 0x18 2383 #define I40E_DEV_FUNC_CAP_FCOE 0x21 2384 #define I40E_DEV_FUNC_CAP_ISCSI 0x22 2385 #define I40E_DEV_FUNC_CAP_RSS 0x40 2386 #define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2387 #define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2388 #define I40E_DEV_FUNC_CAP_MSIX 0x43 2389 #define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2390 #define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2391 #define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2392 #define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2393 #define I40E_DEV_FUNC_CAP_CEM 0xF2 2394 #define I40E_DEV_FUNC_CAP_IWARP 0x51 2395 #define I40E_DEV_FUNC_CAP_LED 0x61 2396 #define I40E_DEV_FUNC_CAP_SDP 0x62 2397 #define I40E_DEV_FUNC_CAP_MDIO 0x63 2398 2399 /** 2400 * i40e_parse_discover_capabilities 2401 * @hw: pointer to the hw struct 2402 * @buff: pointer to a buffer containing device/function capability records 2403 * @cap_count: number of capability records in the list 2404 * @list_type_opc: type of capabilities list to parse 2405 * 2406 * Parse the device/function capabilities list. 2407 **/ 2408 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2409 u32 cap_count, 2410 enum i40e_admin_queue_opc list_type_opc) 2411 { 2412 struct i40e_aqc_list_capabilities_element_resp *cap; 2413 u32 valid_functions, num_functions; 2414 u32 number, logical_id, phys_id; 2415 struct i40e_hw_capabilities *p; 2416 u32 i = 0; 2417 u16 id; 2418 2419 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2420 2421 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2422 p = &hw->dev_caps; 2423 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2424 p = &hw->func_caps; 2425 else 2426 return; 2427 2428 for (i = 0; i < cap_count; i++, cap++) { 2429 id = le16_to_cpu(cap->id); 2430 number = le32_to_cpu(cap->number); 2431 logical_id = le32_to_cpu(cap->logical_id); 2432 phys_id = le32_to_cpu(cap->phys_id); 2433 2434 switch (id) { 2435 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2436 p->switch_mode = number; 2437 break; 2438 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2439 p->management_mode = number; 2440 break; 2441 case I40E_DEV_FUNC_CAP_NPAR: 2442 p->npar_enable = number; 2443 break; 2444 case I40E_DEV_FUNC_CAP_OS2BMC: 2445 p->os2bmc = number; 2446 break; 2447 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2448 p->valid_functions = number; 2449 break; 2450 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2451 if (number == 1) 2452 p->sr_iov_1_1 = true; 2453 break; 2454 case I40E_DEV_FUNC_CAP_VF: 2455 p->num_vfs = number; 2456 p->vf_base_id = logical_id; 2457 break; 2458 case I40E_DEV_FUNC_CAP_VMDQ: 2459 if (number == 1) 2460 p->vmdq = true; 2461 break; 2462 case I40E_DEV_FUNC_CAP_802_1_QBG: 2463 if (number == 1) 2464 p->evb_802_1_qbg = true; 2465 break; 2466 case I40E_DEV_FUNC_CAP_802_1_QBH: 2467 if (number == 1) 2468 p->evb_802_1_qbh = true; 2469 break; 2470 case I40E_DEV_FUNC_CAP_VSI: 2471 p->num_vsis = number; 2472 break; 2473 case I40E_DEV_FUNC_CAP_DCB: 2474 if (number == 1) { 2475 p->dcb = true; 2476 p->enabled_tcmap = logical_id; 2477 p->maxtc = phys_id; 2478 } 2479 break; 2480 case I40E_DEV_FUNC_CAP_FCOE: 2481 if (number == 1) 2482 p->fcoe = true; 2483 break; 2484 case I40E_DEV_FUNC_CAP_ISCSI: 2485 if (number == 1) 2486 p->iscsi = true; 2487 break; 2488 case I40E_DEV_FUNC_CAP_RSS: 2489 p->rss = true; 2490 p->rss_table_size = number; 2491 p->rss_table_entry_width = logical_id; 2492 break; 2493 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2494 p->num_rx_qp = number; 2495 p->base_queue = phys_id; 2496 break; 2497 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2498 p->num_tx_qp = number; 2499 p->base_queue = phys_id; 2500 break; 2501 case I40E_DEV_FUNC_CAP_MSIX: 2502 p->num_msix_vectors = number; 2503 break; 2504 case I40E_DEV_FUNC_CAP_MSIX_VF: 2505 p->num_msix_vectors_vf = number; 2506 break; 2507 case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2508 if (number == 1) 2509 p->mfp_mode_1 = true; 2510 break; 2511 case I40E_DEV_FUNC_CAP_CEM: 2512 if (number == 1) 2513 p->mgmt_cem = true; 2514 break; 2515 case I40E_DEV_FUNC_CAP_IWARP: 2516 if (number == 1) 2517 p->iwarp = true; 2518 break; 2519 case I40E_DEV_FUNC_CAP_LED: 2520 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2521 p->led[phys_id] = true; 2522 break; 2523 case I40E_DEV_FUNC_CAP_SDP: 2524 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2525 p->sdp[phys_id] = true; 2526 break; 2527 case I40E_DEV_FUNC_CAP_MDIO: 2528 if (number == 1) { 2529 p->mdio_port_num = phys_id; 2530 p->mdio_port_mode = logical_id; 2531 } 2532 break; 2533 case I40E_DEV_FUNC_CAP_IEEE_1588: 2534 if (number == 1) 2535 p->ieee_1588 = true; 2536 break; 2537 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2538 p->fd = true; 2539 p->fd_filters_guaranteed = number; 2540 p->fd_filters_best_effort = logical_id; 2541 break; 2542 default: 2543 break; 2544 } 2545 } 2546 2547 /* Software override ensuring FCoE is disabled if npar or mfp 2548 * mode because it is not supported in these modes. 2549 */ 2550 if (p->npar_enable || p->mfp_mode_1) 2551 p->fcoe = false; 2552 2553 /* count the enabled ports (aka the "not disabled" ports) */ 2554 hw->num_ports = 0; 2555 for (i = 0; i < 4; i++) { 2556 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 2557 u64 port_cfg = 0; 2558 2559 /* use AQ read to get the physical register offset instead 2560 * of the port relative offset 2561 */ 2562 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 2563 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 2564 hw->num_ports++; 2565 } 2566 2567 valid_functions = p->valid_functions; 2568 num_functions = 0; 2569 while (valid_functions) { 2570 if (valid_functions & 1) 2571 num_functions++; 2572 valid_functions >>= 1; 2573 } 2574 2575 /* partition id is 1-based, and functions are evenly spread 2576 * across the ports as partitions 2577 */ 2578 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 2579 hw->num_partitions = num_functions / hw->num_ports; 2580 2581 /* additional HW specific goodies that might 2582 * someday be HW version specific 2583 */ 2584 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2585 } 2586 2587 /** 2588 * i40e_aq_discover_capabilities 2589 * @hw: pointer to the hw struct 2590 * @buff: a virtual buffer to hold the capabilities 2591 * @buff_size: Size of the virtual buffer 2592 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2593 * @list_type_opc: capabilities type to discover - pass in the command opcode 2594 * @cmd_details: pointer to command details structure or NULL 2595 * 2596 * Get the device capabilities descriptions from the firmware 2597 **/ 2598 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 2599 void *buff, u16 buff_size, u16 *data_size, 2600 enum i40e_admin_queue_opc list_type_opc, 2601 struct i40e_asq_cmd_details *cmd_details) 2602 { 2603 struct i40e_aqc_list_capabilites *cmd; 2604 struct i40e_aq_desc desc; 2605 i40e_status status = 0; 2606 2607 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2608 2609 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2610 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2611 status = I40E_ERR_PARAM; 2612 goto exit; 2613 } 2614 2615 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2616 2617 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2618 if (buff_size > I40E_AQ_LARGE_BUF) 2619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2620 2621 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2622 *data_size = le16_to_cpu(desc.datalen); 2623 2624 if (status) 2625 goto exit; 2626 2627 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2628 list_type_opc); 2629 2630 exit: 2631 return status; 2632 } 2633 2634 /** 2635 * i40e_aq_update_nvm 2636 * @hw: pointer to the hw struct 2637 * @module_pointer: module pointer location in words from the NVM beginning 2638 * @offset: byte offset from the module beginning 2639 * @length: length of the section to be written (in bytes from the offset) 2640 * @data: command buffer (size [bytes] = length) 2641 * @last_command: tells if this is the last command in a series 2642 * @cmd_details: pointer to command details structure or NULL 2643 * 2644 * Update the NVM using the admin queue commands 2645 **/ 2646 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2647 u32 offset, u16 length, void *data, 2648 bool last_command, 2649 struct i40e_asq_cmd_details *cmd_details) 2650 { 2651 struct i40e_aq_desc desc; 2652 struct i40e_aqc_nvm_update *cmd = 2653 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2654 i40e_status status; 2655 2656 /* In offset the highest byte must be zeroed. */ 2657 if (offset & 0xFF000000) { 2658 status = I40E_ERR_PARAM; 2659 goto i40e_aq_update_nvm_exit; 2660 } 2661 2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2663 2664 /* If this is the last command in a series, set the proper flag. */ 2665 if (last_command) 2666 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2667 cmd->module_pointer = module_pointer; 2668 cmd->offset = cpu_to_le32(offset); 2669 cmd->length = cpu_to_le16(length); 2670 2671 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2672 if (length > I40E_AQ_LARGE_BUF) 2673 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2674 2675 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2676 2677 i40e_aq_update_nvm_exit: 2678 return status; 2679 } 2680 2681 /** 2682 * i40e_aq_get_lldp_mib 2683 * @hw: pointer to the hw struct 2684 * @bridge_type: type of bridge requested 2685 * @mib_type: Local, Remote or both Local and Remote MIBs 2686 * @buff: pointer to a user supplied buffer to store the MIB block 2687 * @buff_size: size of the buffer (in bytes) 2688 * @local_len : length of the returned Local LLDP MIB 2689 * @remote_len: length of the returned Remote LLDP MIB 2690 * @cmd_details: pointer to command details structure or NULL 2691 * 2692 * Requests the complete LLDP MIB (entire packet). 2693 **/ 2694 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2695 u8 mib_type, void *buff, u16 buff_size, 2696 u16 *local_len, u16 *remote_len, 2697 struct i40e_asq_cmd_details *cmd_details) 2698 { 2699 struct i40e_aq_desc desc; 2700 struct i40e_aqc_lldp_get_mib *cmd = 2701 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2702 struct i40e_aqc_lldp_get_mib *resp = 2703 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2704 i40e_status status; 2705 2706 if (buff_size == 0 || !buff) 2707 return I40E_ERR_PARAM; 2708 2709 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2710 /* Indirect Command */ 2711 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2712 2713 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2714 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 2715 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 2716 2717 desc.datalen = cpu_to_le16(buff_size); 2718 2719 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2720 if (buff_size > I40E_AQ_LARGE_BUF) 2721 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2722 2723 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2724 if (!status) { 2725 if (local_len != NULL) 2726 *local_len = le16_to_cpu(resp->local_len); 2727 if (remote_len != NULL) 2728 *remote_len = le16_to_cpu(resp->remote_len); 2729 } 2730 2731 return status; 2732 } 2733 2734 /** 2735 * i40e_aq_cfg_lldp_mib_change_event 2736 * @hw: pointer to the hw struct 2737 * @enable_update: Enable or Disable event posting 2738 * @cmd_details: pointer to command details structure or NULL 2739 * 2740 * Enable or Disable posting of an event on ARQ when LLDP MIB 2741 * associated with the interface changes 2742 **/ 2743 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 2744 bool enable_update, 2745 struct i40e_asq_cmd_details *cmd_details) 2746 { 2747 struct i40e_aq_desc desc; 2748 struct i40e_aqc_lldp_update_mib *cmd = 2749 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 2750 i40e_status status; 2751 2752 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 2753 2754 if (!enable_update) 2755 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 2756 2757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2758 2759 return status; 2760 } 2761 2762 /** 2763 * i40e_aq_stop_lldp 2764 * @hw: pointer to the hw struct 2765 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 2766 * @cmd_details: pointer to command details structure or NULL 2767 * 2768 * Stop or Shutdown the embedded LLDP Agent 2769 **/ 2770 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 2771 struct i40e_asq_cmd_details *cmd_details) 2772 { 2773 struct i40e_aq_desc desc; 2774 struct i40e_aqc_lldp_stop *cmd = 2775 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 2776 i40e_status status; 2777 2778 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 2779 2780 if (shutdown_agent) 2781 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 2782 2783 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2784 2785 return status; 2786 } 2787 2788 /** 2789 * i40e_aq_start_lldp 2790 * @hw: pointer to the hw struct 2791 * @cmd_details: pointer to command details structure or NULL 2792 * 2793 * Start the embedded LLDP Agent on all ports. 2794 **/ 2795 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 2796 struct i40e_asq_cmd_details *cmd_details) 2797 { 2798 struct i40e_aq_desc desc; 2799 struct i40e_aqc_lldp_start *cmd = 2800 (struct i40e_aqc_lldp_start *)&desc.params.raw; 2801 i40e_status status; 2802 2803 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 2804 2805 cmd->command = I40E_AQ_LLDP_AGENT_START; 2806 2807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2808 2809 return status; 2810 } 2811 2812 /** 2813 * i40e_aq_get_cee_dcb_config 2814 * @hw: pointer to the hw struct 2815 * @buff: response buffer that stores CEE operational configuration 2816 * @buff_size: size of the buffer passed 2817 * @cmd_details: pointer to command details structure or NULL 2818 * 2819 * Get CEE DCBX mode operational configuration from firmware 2820 **/ 2821 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 2822 void *buff, u16 buff_size, 2823 struct i40e_asq_cmd_details *cmd_details) 2824 { 2825 struct i40e_aq_desc desc; 2826 i40e_status status; 2827 2828 if (buff_size == 0 || !buff) 2829 return I40E_ERR_PARAM; 2830 2831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 2832 2833 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2834 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 2835 cmd_details); 2836 2837 return status; 2838 } 2839 2840 /** 2841 * i40e_aq_add_udp_tunnel 2842 * @hw: pointer to the hw struct 2843 * @udp_port: the UDP port to add 2844 * @header_len: length of the tunneling header length in DWords 2845 * @protocol_index: protocol index type 2846 * @filter_index: pointer to filter index 2847 * @cmd_details: pointer to command details structure or NULL 2848 **/ 2849 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 2850 u16 udp_port, u8 protocol_index, 2851 u8 *filter_index, 2852 struct i40e_asq_cmd_details *cmd_details) 2853 { 2854 struct i40e_aq_desc desc; 2855 struct i40e_aqc_add_udp_tunnel *cmd = 2856 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 2857 struct i40e_aqc_del_udp_tunnel_completion *resp = 2858 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 2859 i40e_status status; 2860 2861 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 2862 2863 cmd->udp_port = cpu_to_le16(udp_port); 2864 cmd->protocol_type = protocol_index; 2865 2866 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2867 2868 if (!status && filter_index) 2869 *filter_index = resp->index; 2870 2871 return status; 2872 } 2873 2874 /** 2875 * i40e_aq_del_udp_tunnel 2876 * @hw: pointer to the hw struct 2877 * @index: filter index 2878 * @cmd_details: pointer to command details structure or NULL 2879 **/ 2880 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 2881 struct i40e_asq_cmd_details *cmd_details) 2882 { 2883 struct i40e_aq_desc desc; 2884 struct i40e_aqc_remove_udp_tunnel *cmd = 2885 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 2886 i40e_status status; 2887 2888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 2889 2890 cmd->index = index; 2891 2892 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2893 2894 return status; 2895 } 2896 2897 /** 2898 * i40e_aq_delete_element - Delete switch element 2899 * @hw: pointer to the hw struct 2900 * @seid: the SEID to delete from the switch 2901 * @cmd_details: pointer to command details structure or NULL 2902 * 2903 * This deletes a switch element from the switch. 2904 **/ 2905 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 2906 struct i40e_asq_cmd_details *cmd_details) 2907 { 2908 struct i40e_aq_desc desc; 2909 struct i40e_aqc_switch_seid *cmd = 2910 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2911 i40e_status status; 2912 2913 if (seid == 0) 2914 return I40E_ERR_PARAM; 2915 2916 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 2917 2918 cmd->seid = cpu_to_le16(seid); 2919 2920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2921 2922 return status; 2923 } 2924 2925 /** 2926 * i40e_aq_dcb_updated - DCB Updated Command 2927 * @hw: pointer to the hw struct 2928 * @cmd_details: pointer to command details structure or NULL 2929 * 2930 * EMP will return when the shared RPB settings have been 2931 * recomputed and modified. The retval field in the descriptor 2932 * will be set to 0 when RPB is modified. 2933 **/ 2934 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 2935 struct i40e_asq_cmd_details *cmd_details) 2936 { 2937 struct i40e_aq_desc desc; 2938 i40e_status status; 2939 2940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 2941 2942 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2943 2944 return status; 2945 } 2946 2947 /** 2948 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 2949 * @hw: pointer to the hw struct 2950 * @seid: seid for the physical port/switching component/vsi 2951 * @buff: Indirect buffer to hold data parameters and response 2952 * @buff_size: Indirect buffer size 2953 * @opcode: Tx scheduler AQ command opcode 2954 * @cmd_details: pointer to command details structure or NULL 2955 * 2956 * Generic command handler for Tx scheduler AQ commands 2957 **/ 2958 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 2959 void *buff, u16 buff_size, 2960 enum i40e_admin_queue_opc opcode, 2961 struct i40e_asq_cmd_details *cmd_details) 2962 { 2963 struct i40e_aq_desc desc; 2964 struct i40e_aqc_tx_sched_ind *cmd = 2965 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 2966 i40e_status status; 2967 bool cmd_param_flag = false; 2968 2969 switch (opcode) { 2970 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 2971 case i40e_aqc_opc_configure_vsi_tc_bw: 2972 case i40e_aqc_opc_enable_switching_comp_ets: 2973 case i40e_aqc_opc_modify_switching_comp_ets: 2974 case i40e_aqc_opc_disable_switching_comp_ets: 2975 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 2976 case i40e_aqc_opc_configure_switching_comp_bw_config: 2977 cmd_param_flag = true; 2978 break; 2979 case i40e_aqc_opc_query_vsi_bw_config: 2980 case i40e_aqc_opc_query_vsi_ets_sla_config: 2981 case i40e_aqc_opc_query_switching_comp_ets_config: 2982 case i40e_aqc_opc_query_port_ets_config: 2983 case i40e_aqc_opc_query_switching_comp_bw_config: 2984 cmd_param_flag = false; 2985 break; 2986 default: 2987 return I40E_ERR_PARAM; 2988 } 2989 2990 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2991 2992 /* Indirect command */ 2993 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2994 if (cmd_param_flag) 2995 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 2996 if (buff_size > I40E_AQ_LARGE_BUF) 2997 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2998 2999 desc.datalen = cpu_to_le16(buff_size); 3000 3001 cmd->vsi_seid = cpu_to_le16(seid); 3002 3003 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3004 3005 return status; 3006 } 3007 3008 /** 3009 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3010 * @hw: pointer to the hw struct 3011 * @seid: VSI seid 3012 * @credit: BW limit credits (0 = disabled) 3013 * @max_credit: Max BW limit credits 3014 * @cmd_details: pointer to command details structure or NULL 3015 **/ 3016 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3017 u16 seid, u16 credit, u8 max_credit, 3018 struct i40e_asq_cmd_details *cmd_details) 3019 { 3020 struct i40e_aq_desc desc; 3021 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3022 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3023 i40e_status status; 3024 3025 i40e_fill_default_direct_cmd_desc(&desc, 3026 i40e_aqc_opc_configure_vsi_bw_limit); 3027 3028 cmd->vsi_seid = cpu_to_le16(seid); 3029 cmd->credit = cpu_to_le16(credit); 3030 cmd->max_credit = max_credit; 3031 3032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3033 3034 return status; 3035 } 3036 3037 /** 3038 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3039 * @hw: pointer to the hw struct 3040 * @seid: VSI seid 3041 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3042 * @cmd_details: pointer to command details structure or NULL 3043 **/ 3044 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3045 u16 seid, 3046 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3047 struct i40e_asq_cmd_details *cmd_details) 3048 { 3049 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3050 i40e_aqc_opc_configure_vsi_tc_bw, 3051 cmd_details); 3052 } 3053 3054 /** 3055 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3056 * @hw: pointer to the hw struct 3057 * @seid: seid of the switching component connected to Physical Port 3058 * @ets_data: Buffer holding ETS parameters 3059 * @cmd_details: pointer to command details structure or NULL 3060 **/ 3061 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3062 u16 seid, 3063 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3064 enum i40e_admin_queue_opc opcode, 3065 struct i40e_asq_cmd_details *cmd_details) 3066 { 3067 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3068 sizeof(*ets_data), opcode, cmd_details); 3069 } 3070 3071 /** 3072 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3073 * @hw: pointer to the hw struct 3074 * @seid: seid of the switching component 3075 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3076 * @cmd_details: pointer to command details structure or NULL 3077 **/ 3078 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3079 u16 seid, 3080 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3081 struct i40e_asq_cmd_details *cmd_details) 3082 { 3083 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3084 i40e_aqc_opc_configure_switching_comp_bw_config, 3085 cmd_details); 3086 } 3087 3088 /** 3089 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3090 * @hw: pointer to the hw struct 3091 * @seid: seid of the VSI 3092 * @bw_data: Buffer to hold VSI BW configuration 3093 * @cmd_details: pointer to command details structure or NULL 3094 **/ 3095 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3096 u16 seid, 3097 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3098 struct i40e_asq_cmd_details *cmd_details) 3099 { 3100 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3101 i40e_aqc_opc_query_vsi_bw_config, 3102 cmd_details); 3103 } 3104 3105 /** 3106 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3107 * @hw: pointer to the hw struct 3108 * @seid: seid of the VSI 3109 * @bw_data: Buffer to hold VSI BW configuration per TC 3110 * @cmd_details: pointer to command details structure or NULL 3111 **/ 3112 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3113 u16 seid, 3114 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3115 struct i40e_asq_cmd_details *cmd_details) 3116 { 3117 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3118 i40e_aqc_opc_query_vsi_ets_sla_config, 3119 cmd_details); 3120 } 3121 3122 /** 3123 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3124 * @hw: pointer to the hw struct 3125 * @seid: seid of the switching component 3126 * @bw_data: Buffer to hold switching component's per TC BW config 3127 * @cmd_details: pointer to command details structure or NULL 3128 **/ 3129 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3130 u16 seid, 3131 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3132 struct i40e_asq_cmd_details *cmd_details) 3133 { 3134 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3135 i40e_aqc_opc_query_switching_comp_ets_config, 3136 cmd_details); 3137 } 3138 3139 /** 3140 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3141 * @hw: pointer to the hw struct 3142 * @seid: seid of the VSI or switching component connected to Physical Port 3143 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3144 * @cmd_details: pointer to command details structure or NULL 3145 **/ 3146 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3147 u16 seid, 3148 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3149 struct i40e_asq_cmd_details *cmd_details) 3150 { 3151 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3152 i40e_aqc_opc_query_port_ets_config, 3153 cmd_details); 3154 } 3155 3156 /** 3157 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3158 * @hw: pointer to the hw struct 3159 * @seid: seid of the switching component 3160 * @bw_data: Buffer to hold switching component's BW configuration 3161 * @cmd_details: pointer to command details structure or NULL 3162 **/ 3163 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3164 u16 seid, 3165 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3166 struct i40e_asq_cmd_details *cmd_details) 3167 { 3168 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3169 i40e_aqc_opc_query_switching_comp_bw_config, 3170 cmd_details); 3171 } 3172 3173 /** 3174 * i40e_validate_filter_settings 3175 * @hw: pointer to the hardware structure 3176 * @settings: Filter control settings 3177 * 3178 * Check and validate the filter control settings passed. 3179 * The function checks for the valid filter/context sizes being 3180 * passed for FCoE and PE. 3181 * 3182 * Returns 0 if the values passed are valid and within 3183 * range else returns an error. 3184 **/ 3185 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3186 struct i40e_filter_control_settings *settings) 3187 { 3188 u32 fcoe_cntx_size, fcoe_filt_size; 3189 u32 pe_cntx_size, pe_filt_size; 3190 u32 fcoe_fmax; 3191 u32 val; 3192 3193 /* Validate FCoE settings passed */ 3194 switch (settings->fcoe_filt_num) { 3195 case I40E_HASH_FILTER_SIZE_1K: 3196 case I40E_HASH_FILTER_SIZE_2K: 3197 case I40E_HASH_FILTER_SIZE_4K: 3198 case I40E_HASH_FILTER_SIZE_8K: 3199 case I40E_HASH_FILTER_SIZE_16K: 3200 case I40E_HASH_FILTER_SIZE_32K: 3201 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3202 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3203 break; 3204 default: 3205 return I40E_ERR_PARAM; 3206 } 3207 3208 switch (settings->fcoe_cntx_num) { 3209 case I40E_DMA_CNTX_SIZE_512: 3210 case I40E_DMA_CNTX_SIZE_1K: 3211 case I40E_DMA_CNTX_SIZE_2K: 3212 case I40E_DMA_CNTX_SIZE_4K: 3213 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3214 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3215 break; 3216 default: 3217 return I40E_ERR_PARAM; 3218 } 3219 3220 /* Validate PE settings passed */ 3221 switch (settings->pe_filt_num) { 3222 case I40E_HASH_FILTER_SIZE_1K: 3223 case I40E_HASH_FILTER_SIZE_2K: 3224 case I40E_HASH_FILTER_SIZE_4K: 3225 case I40E_HASH_FILTER_SIZE_8K: 3226 case I40E_HASH_FILTER_SIZE_16K: 3227 case I40E_HASH_FILTER_SIZE_32K: 3228 case I40E_HASH_FILTER_SIZE_64K: 3229 case I40E_HASH_FILTER_SIZE_128K: 3230 case I40E_HASH_FILTER_SIZE_256K: 3231 case I40E_HASH_FILTER_SIZE_512K: 3232 case I40E_HASH_FILTER_SIZE_1M: 3233 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3234 pe_filt_size <<= (u32)settings->pe_filt_num; 3235 break; 3236 default: 3237 return I40E_ERR_PARAM; 3238 } 3239 3240 switch (settings->pe_cntx_num) { 3241 case I40E_DMA_CNTX_SIZE_512: 3242 case I40E_DMA_CNTX_SIZE_1K: 3243 case I40E_DMA_CNTX_SIZE_2K: 3244 case I40E_DMA_CNTX_SIZE_4K: 3245 case I40E_DMA_CNTX_SIZE_8K: 3246 case I40E_DMA_CNTX_SIZE_16K: 3247 case I40E_DMA_CNTX_SIZE_32K: 3248 case I40E_DMA_CNTX_SIZE_64K: 3249 case I40E_DMA_CNTX_SIZE_128K: 3250 case I40E_DMA_CNTX_SIZE_256K: 3251 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3252 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3253 break; 3254 default: 3255 return I40E_ERR_PARAM; 3256 } 3257 3258 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3259 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3260 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3261 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3262 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3263 return I40E_ERR_INVALID_SIZE; 3264 3265 return 0; 3266 } 3267 3268 /** 3269 * i40e_set_filter_control 3270 * @hw: pointer to the hardware structure 3271 * @settings: Filter control settings 3272 * 3273 * Set the Queue Filters for PE/FCoE and enable filters required 3274 * for a single PF. It is expected that these settings are programmed 3275 * at the driver initialization time. 3276 **/ 3277 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 3278 struct i40e_filter_control_settings *settings) 3279 { 3280 i40e_status ret = 0; 3281 u32 hash_lut_size = 0; 3282 u32 val; 3283 3284 if (!settings) 3285 return I40E_ERR_PARAM; 3286 3287 /* Validate the input settings */ 3288 ret = i40e_validate_filter_settings(hw, settings); 3289 if (ret) 3290 return ret; 3291 3292 /* Read the PF Queue Filter control register */ 3293 val = rd32(hw, I40E_PFQF_CTL_0); 3294 3295 /* Program required PE hash buckets for the PF */ 3296 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3297 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 3298 I40E_PFQF_CTL_0_PEHSIZE_MASK; 3299 /* Program required PE contexts for the PF */ 3300 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3301 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 3302 I40E_PFQF_CTL_0_PEDSIZE_MASK; 3303 3304 /* Program required FCoE hash buckets for the PF */ 3305 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3306 val |= ((u32)settings->fcoe_filt_num << 3307 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 3308 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3309 /* Program required FCoE DDP contexts for the PF */ 3310 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3311 val |= ((u32)settings->fcoe_cntx_num << 3312 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 3313 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3314 3315 /* Program Hash LUT size for the PF */ 3316 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3317 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3318 hash_lut_size = 1; 3319 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 3320 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3321 3322 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3323 if (settings->enable_fdir) 3324 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3325 if (settings->enable_ethtype) 3326 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3327 if (settings->enable_macvlan) 3328 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3329 3330 wr32(hw, I40E_PFQF_CTL_0, val); 3331 3332 return 0; 3333 } 3334 3335 /** 3336 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3337 * @hw: pointer to the hw struct 3338 * @mac_addr: MAC address to use in the filter 3339 * @ethtype: Ethertype to use in the filter 3340 * @flags: Flags that needs to be applied to the filter 3341 * @vsi_seid: seid of the control VSI 3342 * @queue: VSI queue number to send the packet to 3343 * @is_add: Add control packet filter if True else remove 3344 * @stats: Structure to hold information on control filter counts 3345 * @cmd_details: pointer to command details structure or NULL 3346 * 3347 * This command will Add or Remove control packet filter for a control VSI. 3348 * In return it will update the total number of perfect filter count in 3349 * the stats member. 3350 **/ 3351 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3352 u8 *mac_addr, u16 ethtype, u16 flags, 3353 u16 vsi_seid, u16 queue, bool is_add, 3354 struct i40e_control_filter_stats *stats, 3355 struct i40e_asq_cmd_details *cmd_details) 3356 { 3357 struct i40e_aq_desc desc; 3358 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3359 (struct i40e_aqc_add_remove_control_packet_filter *) 3360 &desc.params.raw; 3361 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3362 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3363 &desc.params.raw; 3364 i40e_status status; 3365 3366 if (vsi_seid == 0) 3367 return I40E_ERR_PARAM; 3368 3369 if (is_add) { 3370 i40e_fill_default_direct_cmd_desc(&desc, 3371 i40e_aqc_opc_add_control_packet_filter); 3372 cmd->queue = cpu_to_le16(queue); 3373 } else { 3374 i40e_fill_default_direct_cmd_desc(&desc, 3375 i40e_aqc_opc_remove_control_packet_filter); 3376 } 3377 3378 if (mac_addr) 3379 memcpy(cmd->mac, mac_addr, ETH_ALEN); 3380 3381 cmd->etype = cpu_to_le16(ethtype); 3382 cmd->flags = cpu_to_le16(flags); 3383 cmd->seid = cpu_to_le16(vsi_seid); 3384 3385 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3386 3387 if (!status && stats) { 3388 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3389 stats->etype_used = le16_to_cpu(resp->etype_used); 3390 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3391 stats->etype_free = le16_to_cpu(resp->etype_free); 3392 } 3393 3394 return status; 3395 } 3396 3397 /** 3398 * i40e_aq_alternate_read 3399 * @hw: pointer to the hardware structure 3400 * @reg_addr0: address of first dword to be read 3401 * @reg_val0: pointer for data read from 'reg_addr0' 3402 * @reg_addr1: address of second dword to be read 3403 * @reg_val1: pointer for data read from 'reg_addr1' 3404 * 3405 * Read one or two dwords from alternate structure. Fields are indicated 3406 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 3407 * is not passed then only register at 'reg_addr0' is read. 3408 * 3409 **/ 3410 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 3411 u32 reg_addr0, u32 *reg_val0, 3412 u32 reg_addr1, u32 *reg_val1) 3413 { 3414 struct i40e_aq_desc desc; 3415 struct i40e_aqc_alternate_write *cmd_resp = 3416 (struct i40e_aqc_alternate_write *)&desc.params.raw; 3417 i40e_status status; 3418 3419 if (!reg_val0) 3420 return I40E_ERR_PARAM; 3421 3422 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 3423 cmd_resp->address0 = cpu_to_le32(reg_addr0); 3424 cmd_resp->address1 = cpu_to_le32(reg_addr1); 3425 3426 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 3427 3428 if (!status) { 3429 *reg_val0 = le32_to_cpu(cmd_resp->data0); 3430 3431 if (reg_val1) 3432 *reg_val1 = le32_to_cpu(cmd_resp->data1); 3433 } 3434 3435 return status; 3436 } 3437 3438 /** 3439 * i40e_aq_resume_port_tx 3440 * @hw: pointer to the hardware structure 3441 * @cmd_details: pointer to command details structure or NULL 3442 * 3443 * Resume port's Tx traffic 3444 **/ 3445 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 3446 struct i40e_asq_cmd_details *cmd_details) 3447 { 3448 struct i40e_aq_desc desc; 3449 i40e_status status; 3450 3451 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 3452 3453 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3454 3455 return status; 3456 } 3457 3458 /** 3459 * i40e_set_pci_config_data - store PCI bus info 3460 * @hw: pointer to hardware structure 3461 * @link_status: the link status word from PCI config space 3462 * 3463 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3464 **/ 3465 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3466 { 3467 hw->bus.type = i40e_bus_type_pci_express; 3468 3469 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3470 case PCI_EXP_LNKSTA_NLW_X1: 3471 hw->bus.width = i40e_bus_width_pcie_x1; 3472 break; 3473 case PCI_EXP_LNKSTA_NLW_X2: 3474 hw->bus.width = i40e_bus_width_pcie_x2; 3475 break; 3476 case PCI_EXP_LNKSTA_NLW_X4: 3477 hw->bus.width = i40e_bus_width_pcie_x4; 3478 break; 3479 case PCI_EXP_LNKSTA_NLW_X8: 3480 hw->bus.width = i40e_bus_width_pcie_x8; 3481 break; 3482 default: 3483 hw->bus.width = i40e_bus_width_unknown; 3484 break; 3485 } 3486 3487 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3488 case PCI_EXP_LNKSTA_CLS_2_5GB: 3489 hw->bus.speed = i40e_bus_speed_2500; 3490 break; 3491 case PCI_EXP_LNKSTA_CLS_5_0GB: 3492 hw->bus.speed = i40e_bus_speed_5000; 3493 break; 3494 case PCI_EXP_LNKSTA_CLS_8_0GB: 3495 hw->bus.speed = i40e_bus_speed_8000; 3496 break; 3497 default: 3498 hw->bus.speed = i40e_bus_speed_unknown; 3499 break; 3500 } 3501 } 3502 3503 /** 3504 * i40e_read_bw_from_alt_ram 3505 * @hw: pointer to the hardware structure 3506 * @max_bw: pointer for max_bw read 3507 * @min_bw: pointer for min_bw read 3508 * @min_valid: pointer for bool that is true if min_bw is a valid value 3509 * @max_valid: pointer for bool that is true if max_bw is a valid value 3510 * 3511 * Read bw from the alternate ram for the given pf 3512 **/ 3513 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 3514 u32 *max_bw, u32 *min_bw, 3515 bool *min_valid, bool *max_valid) 3516 { 3517 i40e_status status; 3518 u32 max_bw_addr, min_bw_addr; 3519 3520 /* Calculate the address of the min/max bw registers */ 3521 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3522 I40E_ALT_STRUCT_MAX_BW_OFFSET + 3523 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3524 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 3525 I40E_ALT_STRUCT_MIN_BW_OFFSET + 3526 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 3527 3528 /* Read the bandwidths from alt ram */ 3529 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 3530 min_bw_addr, min_bw); 3531 3532 if (*min_bw & I40E_ALT_BW_VALID_MASK) 3533 *min_valid = true; 3534 else 3535 *min_valid = false; 3536 3537 if (*max_bw & I40E_ALT_BW_VALID_MASK) 3538 *max_valid = true; 3539 else 3540 *max_valid = false; 3541 3542 return status; 3543 } 3544 3545 /** 3546 * i40e_aq_configure_partition_bw 3547 * @hw: pointer to the hardware structure 3548 * @bw_data: Buffer holding valid pfs and bw limits 3549 * @cmd_details: pointer to command details 3550 * 3551 * Configure partitions guaranteed/max bw 3552 **/ 3553 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 3554 struct i40e_aqc_configure_partition_bw_data *bw_data, 3555 struct i40e_asq_cmd_details *cmd_details) 3556 { 3557 i40e_status status; 3558 struct i40e_aq_desc desc; 3559 u16 bwd_size = sizeof(*bw_data); 3560 3561 i40e_fill_default_direct_cmd_desc(&desc, 3562 i40e_aqc_opc_configure_partition_bw); 3563 3564 /* Indirect command */ 3565 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3566 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3567 3568 if (bwd_size > I40E_AQ_LARGE_BUF) 3569 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3570 3571 desc.datalen = cpu_to_le16(bwd_size); 3572 3573 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 3574 cmd_details); 3575 3576 return status; 3577 } 3578