1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include "i40e_type.h" 6 #include "i40e_adminq.h" 7 #include "i40e_prototype.h" 8 #include <linux/avf/virtchnl.h> 9 10 /** 11 * i40e_set_mac_type - Sets MAC type 12 * @hw: pointer to the HW structure 13 * 14 * This function sets the mac type of the adapter based on the 15 * vendor ID and device ID stored in the hw structure. 16 **/ 17 i40e_status i40e_set_mac_type(struct i40e_hw *hw) 18 { 19 i40e_status status = 0; 20 21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 22 switch (hw->device_id) { 23 case I40E_DEV_ID_SFP_XL710: 24 case I40E_DEV_ID_QEMU: 25 case I40E_DEV_ID_KX_B: 26 case I40E_DEV_ID_KX_C: 27 case I40E_DEV_ID_QSFP_A: 28 case I40E_DEV_ID_QSFP_B: 29 case I40E_DEV_ID_QSFP_C: 30 case I40E_DEV_ID_5G_BASE_T_BC: 31 case I40E_DEV_ID_10G_BASE_T: 32 case I40E_DEV_ID_10G_BASE_T4: 33 case I40E_DEV_ID_10G_BASE_T_BC: 34 case I40E_DEV_ID_10G_B: 35 case I40E_DEV_ID_10G_SFP: 36 case I40E_DEV_ID_20G_KR2: 37 case I40E_DEV_ID_20G_KR2_A: 38 case I40E_DEV_ID_25G_B: 39 case I40E_DEV_ID_25G_SFP28: 40 case I40E_DEV_ID_X710_N3000: 41 case I40E_DEV_ID_XXV710_N3000: 42 hw->mac.type = I40E_MAC_XL710; 43 break; 44 case I40E_DEV_ID_KX_X722: 45 case I40E_DEV_ID_QSFP_X722: 46 case I40E_DEV_ID_SFP_X722: 47 case I40E_DEV_ID_1G_BASE_T_X722: 48 case I40E_DEV_ID_10G_BASE_T_X722: 49 case I40E_DEV_ID_SFP_I_X722: 50 hw->mac.type = I40E_MAC_X722; 51 break; 52 default: 53 hw->mac.type = I40E_MAC_GENERIC; 54 break; 55 } 56 } else { 57 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 58 } 59 60 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 61 hw->mac.type, status); 62 return status; 63 } 64 65 /** 66 * i40e_aq_str - convert AQ err code to a string 67 * @hw: pointer to the HW structure 68 * @aq_err: the AQ error code to convert 69 **/ 70 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 71 { 72 switch (aq_err) { 73 case I40E_AQ_RC_OK: 74 return "OK"; 75 case I40E_AQ_RC_EPERM: 76 return "I40E_AQ_RC_EPERM"; 77 case I40E_AQ_RC_ENOENT: 78 return "I40E_AQ_RC_ENOENT"; 79 case I40E_AQ_RC_ESRCH: 80 return "I40E_AQ_RC_ESRCH"; 81 case I40E_AQ_RC_EINTR: 82 return "I40E_AQ_RC_EINTR"; 83 case I40E_AQ_RC_EIO: 84 return "I40E_AQ_RC_EIO"; 85 case I40E_AQ_RC_ENXIO: 86 return "I40E_AQ_RC_ENXIO"; 87 case I40E_AQ_RC_E2BIG: 88 return "I40E_AQ_RC_E2BIG"; 89 case I40E_AQ_RC_EAGAIN: 90 return "I40E_AQ_RC_EAGAIN"; 91 case I40E_AQ_RC_ENOMEM: 92 return "I40E_AQ_RC_ENOMEM"; 93 case I40E_AQ_RC_EACCES: 94 return "I40E_AQ_RC_EACCES"; 95 case I40E_AQ_RC_EFAULT: 96 return "I40E_AQ_RC_EFAULT"; 97 case I40E_AQ_RC_EBUSY: 98 return "I40E_AQ_RC_EBUSY"; 99 case I40E_AQ_RC_EEXIST: 100 return "I40E_AQ_RC_EEXIST"; 101 case I40E_AQ_RC_EINVAL: 102 return "I40E_AQ_RC_EINVAL"; 103 case I40E_AQ_RC_ENOTTY: 104 return "I40E_AQ_RC_ENOTTY"; 105 case I40E_AQ_RC_ENOSPC: 106 return "I40E_AQ_RC_ENOSPC"; 107 case I40E_AQ_RC_ENOSYS: 108 return "I40E_AQ_RC_ENOSYS"; 109 case I40E_AQ_RC_ERANGE: 110 return "I40E_AQ_RC_ERANGE"; 111 case I40E_AQ_RC_EFLUSHED: 112 return "I40E_AQ_RC_EFLUSHED"; 113 case I40E_AQ_RC_BAD_ADDR: 114 return "I40E_AQ_RC_BAD_ADDR"; 115 case I40E_AQ_RC_EMODE: 116 return "I40E_AQ_RC_EMODE"; 117 case I40E_AQ_RC_EFBIG: 118 return "I40E_AQ_RC_EFBIG"; 119 } 120 121 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 122 return hw->err_str; 123 } 124 125 /** 126 * i40e_stat_str - convert status err code to a string 127 * @hw: pointer to the HW structure 128 * @stat_err: the status error code to convert 129 **/ 130 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 131 { 132 switch (stat_err) { 133 case 0: 134 return "OK"; 135 case I40E_ERR_NVM: 136 return "I40E_ERR_NVM"; 137 case I40E_ERR_NVM_CHECKSUM: 138 return "I40E_ERR_NVM_CHECKSUM"; 139 case I40E_ERR_PHY: 140 return "I40E_ERR_PHY"; 141 case I40E_ERR_CONFIG: 142 return "I40E_ERR_CONFIG"; 143 case I40E_ERR_PARAM: 144 return "I40E_ERR_PARAM"; 145 case I40E_ERR_MAC_TYPE: 146 return "I40E_ERR_MAC_TYPE"; 147 case I40E_ERR_UNKNOWN_PHY: 148 return "I40E_ERR_UNKNOWN_PHY"; 149 case I40E_ERR_LINK_SETUP: 150 return "I40E_ERR_LINK_SETUP"; 151 case I40E_ERR_ADAPTER_STOPPED: 152 return "I40E_ERR_ADAPTER_STOPPED"; 153 case I40E_ERR_INVALID_MAC_ADDR: 154 return "I40E_ERR_INVALID_MAC_ADDR"; 155 case I40E_ERR_DEVICE_NOT_SUPPORTED: 156 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 157 case I40E_ERR_PRIMARY_REQUESTS_PENDING: 158 return "I40E_ERR_PRIMARY_REQUESTS_PENDING"; 159 case I40E_ERR_INVALID_LINK_SETTINGS: 160 return "I40E_ERR_INVALID_LINK_SETTINGS"; 161 case I40E_ERR_AUTONEG_NOT_COMPLETE: 162 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 163 case I40E_ERR_RESET_FAILED: 164 return "I40E_ERR_RESET_FAILED"; 165 case I40E_ERR_SWFW_SYNC: 166 return "I40E_ERR_SWFW_SYNC"; 167 case I40E_ERR_NO_AVAILABLE_VSI: 168 return "I40E_ERR_NO_AVAILABLE_VSI"; 169 case I40E_ERR_NO_MEMORY: 170 return "I40E_ERR_NO_MEMORY"; 171 case I40E_ERR_BAD_PTR: 172 return "I40E_ERR_BAD_PTR"; 173 case I40E_ERR_RING_FULL: 174 return "I40E_ERR_RING_FULL"; 175 case I40E_ERR_INVALID_PD_ID: 176 return "I40E_ERR_INVALID_PD_ID"; 177 case I40E_ERR_INVALID_QP_ID: 178 return "I40E_ERR_INVALID_QP_ID"; 179 case I40E_ERR_INVALID_CQ_ID: 180 return "I40E_ERR_INVALID_CQ_ID"; 181 case I40E_ERR_INVALID_CEQ_ID: 182 return "I40E_ERR_INVALID_CEQ_ID"; 183 case I40E_ERR_INVALID_AEQ_ID: 184 return "I40E_ERR_INVALID_AEQ_ID"; 185 case I40E_ERR_INVALID_SIZE: 186 return "I40E_ERR_INVALID_SIZE"; 187 case I40E_ERR_INVALID_ARP_INDEX: 188 return "I40E_ERR_INVALID_ARP_INDEX"; 189 case I40E_ERR_INVALID_FPM_FUNC_ID: 190 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 191 case I40E_ERR_QP_INVALID_MSG_SIZE: 192 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 193 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 194 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 195 case I40E_ERR_INVALID_FRAG_COUNT: 196 return "I40E_ERR_INVALID_FRAG_COUNT"; 197 case I40E_ERR_QUEUE_EMPTY: 198 return "I40E_ERR_QUEUE_EMPTY"; 199 case I40E_ERR_INVALID_ALIGNMENT: 200 return "I40E_ERR_INVALID_ALIGNMENT"; 201 case I40E_ERR_FLUSHED_QUEUE: 202 return "I40E_ERR_FLUSHED_QUEUE"; 203 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 204 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 205 case I40E_ERR_INVALID_IMM_DATA_SIZE: 206 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 207 case I40E_ERR_TIMEOUT: 208 return "I40E_ERR_TIMEOUT"; 209 case I40E_ERR_OPCODE_MISMATCH: 210 return "I40E_ERR_OPCODE_MISMATCH"; 211 case I40E_ERR_CQP_COMPL_ERROR: 212 return "I40E_ERR_CQP_COMPL_ERROR"; 213 case I40E_ERR_INVALID_VF_ID: 214 return "I40E_ERR_INVALID_VF_ID"; 215 case I40E_ERR_INVALID_HMCFN_ID: 216 return "I40E_ERR_INVALID_HMCFN_ID"; 217 case I40E_ERR_BACKING_PAGE_ERROR: 218 return "I40E_ERR_BACKING_PAGE_ERROR"; 219 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 220 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 221 case I40E_ERR_INVALID_PBLE_INDEX: 222 return "I40E_ERR_INVALID_PBLE_INDEX"; 223 case I40E_ERR_INVALID_SD_INDEX: 224 return "I40E_ERR_INVALID_SD_INDEX"; 225 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 226 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 227 case I40E_ERR_INVALID_SD_TYPE: 228 return "I40E_ERR_INVALID_SD_TYPE"; 229 case I40E_ERR_MEMCPY_FAILED: 230 return "I40E_ERR_MEMCPY_FAILED"; 231 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 232 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 233 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 234 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 235 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 236 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 237 case I40E_ERR_SRQ_ENABLED: 238 return "I40E_ERR_SRQ_ENABLED"; 239 case I40E_ERR_ADMIN_QUEUE_ERROR: 240 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 241 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 242 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 243 case I40E_ERR_BUF_TOO_SHORT: 244 return "I40E_ERR_BUF_TOO_SHORT"; 245 case I40E_ERR_ADMIN_QUEUE_FULL: 246 return "I40E_ERR_ADMIN_QUEUE_FULL"; 247 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 248 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 249 case I40E_ERR_BAD_IWARP_CQE: 250 return "I40E_ERR_BAD_IWARP_CQE"; 251 case I40E_ERR_NVM_BLANK_MODE: 252 return "I40E_ERR_NVM_BLANK_MODE"; 253 case I40E_ERR_NOT_IMPLEMENTED: 254 return "I40E_ERR_NOT_IMPLEMENTED"; 255 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 256 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 257 case I40E_ERR_DIAG_TEST_FAILED: 258 return "I40E_ERR_DIAG_TEST_FAILED"; 259 case I40E_ERR_NOT_READY: 260 return "I40E_ERR_NOT_READY"; 261 case I40E_NOT_SUPPORTED: 262 return "I40E_NOT_SUPPORTED"; 263 case I40E_ERR_FIRMWARE_API_VERSION: 264 return "I40E_ERR_FIRMWARE_API_VERSION"; 265 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 266 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 267 } 268 269 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 270 return hw->err_str; 271 } 272 273 /** 274 * i40e_debug_aq 275 * @hw: debug mask related to admin queue 276 * @mask: debug mask 277 * @desc: pointer to admin queue descriptor 278 * @buffer: pointer to command buffer 279 * @buf_len: max length of buffer 280 * 281 * Dumps debug log about adminq command with descriptor contents. 282 **/ 283 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 284 void *buffer, u16 buf_len) 285 { 286 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 287 u32 effective_mask = hw->debug_mask & mask; 288 char prefix[27]; 289 u16 len; 290 u8 *buf = (u8 *)buffer; 291 292 if (!effective_mask || !desc) 293 return; 294 295 len = le16_to_cpu(aq_desc->datalen); 296 297 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 298 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 299 le16_to_cpu(aq_desc->opcode), 300 le16_to_cpu(aq_desc->flags), 301 le16_to_cpu(aq_desc->datalen), 302 le16_to_cpu(aq_desc->retval)); 303 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 304 "\tcookie (h,l) 0x%08X 0x%08X\n", 305 le32_to_cpu(aq_desc->cookie_high), 306 le32_to_cpu(aq_desc->cookie_low)); 307 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 308 "\tparam (0,1) 0x%08X 0x%08X\n", 309 le32_to_cpu(aq_desc->params.internal.param0), 310 le32_to_cpu(aq_desc->params.internal.param1)); 311 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 312 "\taddr (h,l) 0x%08X 0x%08X\n", 313 le32_to_cpu(aq_desc->params.external.addr_high), 314 le32_to_cpu(aq_desc->params.external.addr_low)); 315 316 if (buffer && buf_len != 0 && len != 0 && 317 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 318 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 319 if (buf_len < len) 320 len = buf_len; 321 322 snprintf(prefix, sizeof(prefix), 323 "i40e %02x:%02x.%x: \t0x", 324 hw->bus.bus_id, 325 hw->bus.device, 326 hw->bus.func); 327 328 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 329 16, 1, buf, len, false); 330 } 331 } 332 333 /** 334 * i40e_check_asq_alive 335 * @hw: pointer to the hw struct 336 * 337 * Returns true if Queue is enabled else false. 338 **/ 339 bool i40e_check_asq_alive(struct i40e_hw *hw) 340 { 341 if (hw->aq.asq.len) 342 return !!(rd32(hw, hw->aq.asq.len) & 343 I40E_PF_ATQLEN_ATQENABLE_MASK); 344 else 345 return false; 346 } 347 348 /** 349 * i40e_aq_queue_shutdown 350 * @hw: pointer to the hw struct 351 * @unloading: is the driver unloading itself 352 * 353 * Tell the Firmware that we're shutting down the AdminQ and whether 354 * or not the driver is unloading as well. 355 **/ 356 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 357 bool unloading) 358 { 359 struct i40e_aq_desc desc; 360 struct i40e_aqc_queue_shutdown *cmd = 361 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 362 i40e_status status; 363 364 i40e_fill_default_direct_cmd_desc(&desc, 365 i40e_aqc_opc_queue_shutdown); 366 367 if (unloading) 368 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 369 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 370 371 return status; 372 } 373 374 /** 375 * i40e_aq_get_set_rss_lut 376 * @hw: pointer to the hardware structure 377 * @vsi_id: vsi fw index 378 * @pf_lut: for PF table set true, for VSI table set false 379 * @lut: pointer to the lut buffer provided by the caller 380 * @lut_size: size of the lut buffer 381 * @set: set true to set the table, false to get the table 382 * 383 * Internal function to get or set RSS look up table 384 **/ 385 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 386 u16 vsi_id, bool pf_lut, 387 u8 *lut, u16 lut_size, 388 bool set) 389 { 390 i40e_status status; 391 struct i40e_aq_desc desc; 392 struct i40e_aqc_get_set_rss_lut *cmd_resp = 393 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 394 395 if (set) 396 i40e_fill_default_direct_cmd_desc(&desc, 397 i40e_aqc_opc_set_rss_lut); 398 else 399 i40e_fill_default_direct_cmd_desc(&desc, 400 i40e_aqc_opc_get_rss_lut); 401 402 /* Indirect command */ 403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 404 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 405 406 cmd_resp->vsi_id = 407 cpu_to_le16((u16)((vsi_id << 408 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 409 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 410 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 411 412 if (pf_lut) 413 cmd_resp->flags |= cpu_to_le16((u16) 414 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 415 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 416 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 417 else 418 cmd_resp->flags |= cpu_to_le16((u16) 419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 422 423 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 424 425 return status; 426 } 427 428 /** 429 * i40e_aq_get_rss_lut 430 * @hw: pointer to the hardware structure 431 * @vsi_id: vsi fw index 432 * @pf_lut: for PF table set true, for VSI table set false 433 * @lut: pointer to the lut buffer provided by the caller 434 * @lut_size: size of the lut buffer 435 * 436 * get the RSS lookup table, PF or VSI type 437 **/ 438 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 439 bool pf_lut, u8 *lut, u16 lut_size) 440 { 441 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 442 false); 443 } 444 445 /** 446 * i40e_aq_set_rss_lut 447 * @hw: pointer to the hardware structure 448 * @vsi_id: vsi fw index 449 * @pf_lut: for PF table set true, for VSI table set false 450 * @lut: pointer to the lut buffer provided by the caller 451 * @lut_size: size of the lut buffer 452 * 453 * set the RSS lookup table, PF or VSI type 454 **/ 455 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 456 bool pf_lut, u8 *lut, u16 lut_size) 457 { 458 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 459 } 460 461 /** 462 * i40e_aq_get_set_rss_key 463 * @hw: pointer to the hw struct 464 * @vsi_id: vsi fw index 465 * @key: pointer to key info struct 466 * @set: set true to set the key, false to get the key 467 * 468 * get the RSS key per VSI 469 **/ 470 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 471 u16 vsi_id, 472 struct i40e_aqc_get_set_rss_key_data *key, 473 bool set) 474 { 475 i40e_status status; 476 struct i40e_aq_desc desc; 477 struct i40e_aqc_get_set_rss_key *cmd_resp = 478 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 479 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 480 481 if (set) 482 i40e_fill_default_direct_cmd_desc(&desc, 483 i40e_aqc_opc_set_rss_key); 484 else 485 i40e_fill_default_direct_cmd_desc(&desc, 486 i40e_aqc_opc_get_rss_key); 487 488 /* Indirect command */ 489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 491 492 cmd_resp->vsi_id = 493 cpu_to_le16((u16)((vsi_id << 494 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 495 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 496 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 497 498 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 499 500 return status; 501 } 502 503 /** 504 * i40e_aq_get_rss_key 505 * @hw: pointer to the hw struct 506 * @vsi_id: vsi fw index 507 * @key: pointer to key info struct 508 * 509 **/ 510 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 511 u16 vsi_id, 512 struct i40e_aqc_get_set_rss_key_data *key) 513 { 514 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 515 } 516 517 /** 518 * i40e_aq_set_rss_key 519 * @hw: pointer to the hw struct 520 * @vsi_id: vsi fw index 521 * @key: pointer to key info struct 522 * 523 * set the RSS key per VSI 524 **/ 525 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 526 u16 vsi_id, 527 struct i40e_aqc_get_set_rss_key_data *key) 528 { 529 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 530 } 531 532 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 533 * hardware to a bit-field that can be used by SW to more easily determine the 534 * packet type. 535 * 536 * Macros are used to shorten the table lines and make this table human 537 * readable. 538 * 539 * We store the PTYPE in the top byte of the bit field - this is just so that 540 * we can check that the table doesn't have a row missing, as the index into 541 * the table should be the PTYPE. 542 * 543 * Typical work flow: 544 * 545 * IF NOT i40e_ptype_lookup[ptype].known 546 * THEN 547 * Packet is unknown 548 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 549 * Use the rest of the fields to look at the tunnels, inner protocols, etc 550 * ELSE 551 * Use the enum i40e_rx_l2_ptype to decode the packet type 552 * ENDIF 553 */ 554 555 /* macro to make the table lines short, use explicit indexing with [PTYPE] */ 556 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 557 [PTYPE] = { \ 558 1, \ 559 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 560 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 561 I40E_RX_PTYPE_##OUTER_FRAG, \ 562 I40E_RX_PTYPE_TUNNEL_##T, \ 563 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 564 I40E_RX_PTYPE_##TEF, \ 565 I40E_RX_PTYPE_INNER_PROT_##I, \ 566 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 567 568 #define I40E_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 569 570 /* shorter macros makes the table fit but are terse */ 571 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 572 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 573 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 574 575 /* Lookup table mapping in the 8-bit HW PTYPE to the bit field for decoding */ 576 struct i40e_rx_ptype_decoded i40e_ptype_lookup[BIT(8)] = { 577 /* L2 Packet types */ 578 I40E_PTT_UNUSED_ENTRY(0), 579 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 580 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 581 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 582 I40E_PTT_UNUSED_ENTRY(4), 583 I40E_PTT_UNUSED_ENTRY(5), 584 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 585 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 586 I40E_PTT_UNUSED_ENTRY(8), 587 I40E_PTT_UNUSED_ENTRY(9), 588 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 589 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 590 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 591 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 592 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 593 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 594 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 595 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 596 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 597 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 598 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 599 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 600 601 /* Non Tunneled IPv4 */ 602 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 605 I40E_PTT_UNUSED_ENTRY(25), 606 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 607 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 608 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 609 610 /* IPv4 --> IPv4 */ 611 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 612 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 613 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 614 I40E_PTT_UNUSED_ENTRY(32), 615 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 616 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 617 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 618 619 /* IPv4 --> IPv6 */ 620 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 621 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 622 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 623 I40E_PTT_UNUSED_ENTRY(39), 624 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 625 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 626 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 627 628 /* IPv4 --> GRE/NAT */ 629 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 630 631 /* IPv4 --> GRE/NAT --> IPv4 */ 632 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 633 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 634 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 635 I40E_PTT_UNUSED_ENTRY(47), 636 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 637 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 638 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 639 640 /* IPv4 --> GRE/NAT --> IPv6 */ 641 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 642 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 643 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 644 I40E_PTT_UNUSED_ENTRY(54), 645 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 646 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 647 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 648 649 /* IPv4 --> GRE/NAT --> MAC */ 650 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 651 652 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 653 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 654 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 655 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 656 I40E_PTT_UNUSED_ENTRY(62), 657 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 658 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 659 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 660 661 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 662 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 663 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 664 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 665 I40E_PTT_UNUSED_ENTRY(69), 666 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 667 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 668 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 669 670 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 671 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 672 673 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 674 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 675 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 676 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 677 I40E_PTT_UNUSED_ENTRY(77), 678 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 679 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 680 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 681 682 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 683 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 684 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 685 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 686 I40E_PTT_UNUSED_ENTRY(84), 687 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 688 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 689 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 690 691 /* Non Tunneled IPv6 */ 692 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 693 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 694 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 695 I40E_PTT_UNUSED_ENTRY(91), 696 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 697 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 698 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 699 700 /* IPv6 --> IPv4 */ 701 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 702 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 703 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 704 I40E_PTT_UNUSED_ENTRY(98), 705 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 706 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 707 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 708 709 /* IPv6 --> IPv6 */ 710 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 711 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 712 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 713 I40E_PTT_UNUSED_ENTRY(105), 714 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 715 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 716 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 717 718 /* IPv6 --> GRE/NAT */ 719 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 720 721 /* IPv6 --> GRE/NAT -> IPv4 */ 722 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 723 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 724 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 725 I40E_PTT_UNUSED_ENTRY(113), 726 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 727 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 728 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 729 730 /* IPv6 --> GRE/NAT -> IPv6 */ 731 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 732 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 733 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 734 I40E_PTT_UNUSED_ENTRY(120), 735 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 736 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 737 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 738 739 /* IPv6 --> GRE/NAT -> MAC */ 740 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 741 742 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 743 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 744 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 745 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 746 I40E_PTT_UNUSED_ENTRY(128), 747 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 748 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 749 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 750 751 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 752 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 753 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 754 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 755 I40E_PTT_UNUSED_ENTRY(135), 756 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 757 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 758 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 759 760 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 761 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 762 763 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 764 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 765 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 766 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 767 I40E_PTT_UNUSED_ENTRY(143), 768 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 769 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 770 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 771 772 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 773 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 774 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 775 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 776 I40E_PTT_UNUSED_ENTRY(150), 777 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 778 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 779 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 780 781 /* unused entries */ 782 [154 ... 255] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 783 }; 784 785 /** 786 * i40e_init_shared_code - Initialize the shared code 787 * @hw: pointer to hardware structure 788 * 789 * This assigns the MAC type and PHY code and inits the NVM. 790 * Does not touch the hardware. This function must be called prior to any 791 * other function in the shared code. The i40e_hw structure should be 792 * memset to 0 prior to calling this function. The following fields in 793 * hw structure should be filled in prior to calling this function: 794 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 795 * subsystem_vendor_id, and revision_id 796 **/ 797 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 798 { 799 i40e_status status = 0; 800 u32 port, ari, func_rid; 801 802 i40e_set_mac_type(hw); 803 804 switch (hw->mac.type) { 805 case I40E_MAC_XL710: 806 case I40E_MAC_X722: 807 break; 808 default: 809 return I40E_ERR_DEVICE_NOT_SUPPORTED; 810 } 811 812 hw->phy.get_link_info = true; 813 814 /* Determine port number and PF number*/ 815 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 816 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 817 hw->port = (u8)port; 818 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 819 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 820 func_rid = rd32(hw, I40E_PF_FUNC_RID); 821 if (ari) 822 hw->pf_id = (u8)(func_rid & 0xff); 823 else 824 hw->pf_id = (u8)(func_rid & 0x7); 825 826 status = i40e_init_nvm(hw); 827 return status; 828 } 829 830 /** 831 * i40e_aq_mac_address_read - Retrieve the MAC addresses 832 * @hw: pointer to the hw struct 833 * @flags: a return indicator of what addresses were added to the addr store 834 * @addrs: the requestor's mac addr store 835 * @cmd_details: pointer to command details structure or NULL 836 **/ 837 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 838 u16 *flags, 839 struct i40e_aqc_mac_address_read_data *addrs, 840 struct i40e_asq_cmd_details *cmd_details) 841 { 842 struct i40e_aq_desc desc; 843 struct i40e_aqc_mac_address_read *cmd_data = 844 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 845 i40e_status status; 846 847 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 848 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 849 850 status = i40e_asq_send_command(hw, &desc, addrs, 851 sizeof(*addrs), cmd_details); 852 *flags = le16_to_cpu(cmd_data->command_flags); 853 854 return status; 855 } 856 857 /** 858 * i40e_aq_mac_address_write - Change the MAC addresses 859 * @hw: pointer to the hw struct 860 * @flags: indicates which MAC to be written 861 * @mac_addr: address to write 862 * @cmd_details: pointer to command details structure or NULL 863 **/ 864 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 865 u16 flags, u8 *mac_addr, 866 struct i40e_asq_cmd_details *cmd_details) 867 { 868 struct i40e_aq_desc desc; 869 struct i40e_aqc_mac_address_write *cmd_data = 870 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 871 i40e_status status; 872 873 i40e_fill_default_direct_cmd_desc(&desc, 874 i40e_aqc_opc_mac_address_write); 875 cmd_data->command_flags = cpu_to_le16(flags); 876 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 877 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 878 ((u32)mac_addr[3] << 16) | 879 ((u32)mac_addr[4] << 8) | 880 mac_addr[5]); 881 882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 883 884 return status; 885 } 886 887 /** 888 * i40e_get_mac_addr - get MAC address 889 * @hw: pointer to the HW structure 890 * @mac_addr: pointer to MAC address 891 * 892 * Reads the adapter's MAC address from register 893 **/ 894 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 895 { 896 struct i40e_aqc_mac_address_read_data addrs; 897 i40e_status status; 898 u16 flags = 0; 899 900 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 901 902 if (flags & I40E_AQC_LAN_ADDR_VALID) 903 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 904 905 return status; 906 } 907 908 /** 909 * i40e_get_port_mac_addr - get Port MAC address 910 * @hw: pointer to the HW structure 911 * @mac_addr: pointer to Port MAC address 912 * 913 * Reads the adapter's Port MAC address 914 **/ 915 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 916 { 917 struct i40e_aqc_mac_address_read_data addrs; 918 i40e_status status; 919 u16 flags = 0; 920 921 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 922 if (status) 923 return status; 924 925 if (flags & I40E_AQC_PORT_ADDR_VALID) 926 ether_addr_copy(mac_addr, addrs.port_mac); 927 else 928 status = I40E_ERR_INVALID_MAC_ADDR; 929 930 return status; 931 } 932 933 /** 934 * i40e_pre_tx_queue_cfg - pre tx queue configure 935 * @hw: pointer to the HW structure 936 * @queue: target PF queue index 937 * @enable: state change request 938 * 939 * Handles hw requirement to indicate intention to enable 940 * or disable target queue. 941 **/ 942 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 943 { 944 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 945 u32 reg_block = 0; 946 u32 reg_val; 947 948 if (abs_queue_idx >= 128) { 949 reg_block = abs_queue_idx / 128; 950 abs_queue_idx %= 128; 951 } 952 953 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 954 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 955 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 956 957 if (enable) 958 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 959 else 960 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 961 962 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 963 } 964 965 /** 966 * i40e_read_pba_string - Reads part number string from EEPROM 967 * @hw: pointer to hardware structure 968 * @pba_num: stores the part number string from the EEPROM 969 * @pba_num_size: part number string buffer length 970 * 971 * Reads the part number string from the EEPROM. 972 **/ 973 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 974 u32 pba_num_size) 975 { 976 i40e_status status = 0; 977 u16 pba_word = 0; 978 u16 pba_size = 0; 979 u16 pba_ptr = 0; 980 u16 i = 0; 981 982 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 983 if (status || (pba_word != 0xFAFA)) { 984 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 985 return status; 986 } 987 988 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 989 if (status) { 990 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 991 return status; 992 } 993 994 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 995 if (status) { 996 hw_dbg(hw, "Failed to read PBA Block size.\n"); 997 return status; 998 } 999 1000 /* Subtract one to get PBA word count (PBA Size word is included in 1001 * total size) 1002 */ 1003 pba_size--; 1004 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1005 hw_dbg(hw, "Buffer too small for PBA data.\n"); 1006 return I40E_ERR_PARAM; 1007 } 1008 1009 for (i = 0; i < pba_size; i++) { 1010 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1011 if (status) { 1012 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1013 return status; 1014 } 1015 1016 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1017 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1018 } 1019 pba_num[(pba_size * 2)] = '\0'; 1020 1021 return status; 1022 } 1023 1024 /** 1025 * i40e_get_media_type - Gets media type 1026 * @hw: pointer to the hardware structure 1027 **/ 1028 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1029 { 1030 enum i40e_media_type media; 1031 1032 switch (hw->phy.link_info.phy_type) { 1033 case I40E_PHY_TYPE_10GBASE_SR: 1034 case I40E_PHY_TYPE_10GBASE_LR: 1035 case I40E_PHY_TYPE_1000BASE_SX: 1036 case I40E_PHY_TYPE_1000BASE_LX: 1037 case I40E_PHY_TYPE_40GBASE_SR4: 1038 case I40E_PHY_TYPE_40GBASE_LR4: 1039 case I40E_PHY_TYPE_25GBASE_LR: 1040 case I40E_PHY_TYPE_25GBASE_SR: 1041 media = I40E_MEDIA_TYPE_FIBER; 1042 break; 1043 case I40E_PHY_TYPE_100BASE_TX: 1044 case I40E_PHY_TYPE_1000BASE_T: 1045 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS: 1046 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS: 1047 case I40E_PHY_TYPE_10GBASE_T: 1048 media = I40E_MEDIA_TYPE_BASET; 1049 break; 1050 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1051 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1052 case I40E_PHY_TYPE_10GBASE_CR1: 1053 case I40E_PHY_TYPE_40GBASE_CR4: 1054 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1055 case I40E_PHY_TYPE_40GBASE_AOC: 1056 case I40E_PHY_TYPE_10GBASE_AOC: 1057 case I40E_PHY_TYPE_25GBASE_CR: 1058 case I40E_PHY_TYPE_25GBASE_AOC: 1059 case I40E_PHY_TYPE_25GBASE_ACC: 1060 media = I40E_MEDIA_TYPE_DA; 1061 break; 1062 case I40E_PHY_TYPE_1000BASE_KX: 1063 case I40E_PHY_TYPE_10GBASE_KX4: 1064 case I40E_PHY_TYPE_10GBASE_KR: 1065 case I40E_PHY_TYPE_40GBASE_KR4: 1066 case I40E_PHY_TYPE_20GBASE_KR2: 1067 case I40E_PHY_TYPE_25GBASE_KR: 1068 media = I40E_MEDIA_TYPE_BACKPLANE; 1069 break; 1070 case I40E_PHY_TYPE_SGMII: 1071 case I40E_PHY_TYPE_XAUI: 1072 case I40E_PHY_TYPE_XFI: 1073 case I40E_PHY_TYPE_XLAUI: 1074 case I40E_PHY_TYPE_XLPPI: 1075 default: 1076 media = I40E_MEDIA_TYPE_UNKNOWN; 1077 break; 1078 } 1079 1080 return media; 1081 } 1082 1083 /** 1084 * i40e_poll_globr - Poll for Global Reset completion 1085 * @hw: pointer to the hardware structure 1086 * @retry_limit: how many times to retry before failure 1087 **/ 1088 static i40e_status i40e_poll_globr(struct i40e_hw *hw, 1089 u32 retry_limit) 1090 { 1091 u32 cnt, reg = 0; 1092 1093 for (cnt = 0; cnt < retry_limit; cnt++) { 1094 reg = rd32(hw, I40E_GLGEN_RSTAT); 1095 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1096 return 0; 1097 msleep(100); 1098 } 1099 1100 hw_dbg(hw, "Global reset failed.\n"); 1101 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 1102 1103 return I40E_ERR_RESET_FAILED; 1104 } 1105 1106 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1107 #define I40E_PF_RESET_WAIT_COUNT 200 1108 /** 1109 * i40e_pf_reset - Reset the PF 1110 * @hw: pointer to the hardware structure 1111 * 1112 * Assuming someone else has triggered a global reset, 1113 * assure the global reset is complete and then reset the PF 1114 **/ 1115 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1116 { 1117 u32 cnt = 0; 1118 u32 cnt1 = 0; 1119 u32 reg = 0; 1120 u32 grst_del; 1121 1122 /* Poll for Global Reset steady state in case of recent GRST. 1123 * The grst delay value is in 100ms units, and we'll wait a 1124 * couple counts longer to be sure we don't just miss the end. 1125 */ 1126 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1127 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1128 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1129 1130 /* It can take upto 15 secs for GRST steady state. 1131 * Bump it to 16 secs max to be safe. 1132 */ 1133 grst_del = grst_del * 20; 1134 1135 for (cnt = 0; cnt < grst_del; cnt++) { 1136 reg = rd32(hw, I40E_GLGEN_RSTAT); 1137 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1138 break; 1139 msleep(100); 1140 } 1141 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1142 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1143 return I40E_ERR_RESET_FAILED; 1144 } 1145 1146 /* Now Wait for the FW to be ready */ 1147 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1148 reg = rd32(hw, I40E_GLNVM_ULD); 1149 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1150 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1151 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1152 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1153 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1154 break; 1155 } 1156 usleep_range(10000, 20000); 1157 } 1158 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1159 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1160 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1161 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1162 return I40E_ERR_RESET_FAILED; 1163 } 1164 1165 /* If there was a Global Reset in progress when we got here, 1166 * we don't need to do the PF Reset 1167 */ 1168 if (!cnt) { 1169 u32 reg2 = 0; 1170 if (hw->revision_id == 0) 1171 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1172 else 1173 cnt = I40E_PF_RESET_WAIT_COUNT; 1174 reg = rd32(hw, I40E_PFGEN_CTRL); 1175 wr32(hw, I40E_PFGEN_CTRL, 1176 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1177 for (; cnt; cnt--) { 1178 reg = rd32(hw, I40E_PFGEN_CTRL); 1179 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1180 break; 1181 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1182 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1183 break; 1184 usleep_range(1000, 2000); 1185 } 1186 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1187 if (i40e_poll_globr(hw, grst_del)) 1188 return I40E_ERR_RESET_FAILED; 1189 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1190 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1191 return I40E_ERR_RESET_FAILED; 1192 } 1193 } 1194 1195 i40e_clear_pxe_mode(hw); 1196 1197 return 0; 1198 } 1199 1200 /** 1201 * i40e_clear_hw - clear out any left over hw state 1202 * @hw: pointer to the hw struct 1203 * 1204 * Clear queues and interrupts, typically called at init time, 1205 * but after the capabilities have been found so we know how many 1206 * queues and msix vectors have been allocated. 1207 **/ 1208 void i40e_clear_hw(struct i40e_hw *hw) 1209 { 1210 u32 num_queues, base_queue; 1211 u32 num_pf_int; 1212 u32 num_vf_int; 1213 u32 num_vfs; 1214 u32 i, j; 1215 u32 val; 1216 u32 eol = 0x7ff; 1217 1218 /* get number of interrupts, queues, and VFs */ 1219 val = rd32(hw, I40E_GLPCI_CNF2); 1220 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1221 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1222 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1223 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1224 1225 val = rd32(hw, I40E_PFLAN_QALLOC); 1226 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1227 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1228 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1229 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1230 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1231 num_queues = (j - base_queue) + 1; 1232 else 1233 num_queues = 0; 1234 1235 val = rd32(hw, I40E_PF_VT_PFALLOC); 1236 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1237 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1238 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1239 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1240 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1241 num_vfs = (j - i) + 1; 1242 else 1243 num_vfs = 0; 1244 1245 /* stop all the interrupts */ 1246 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1247 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1248 for (i = 0; i < num_pf_int - 2; i++) 1249 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1250 1251 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1252 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1253 wr32(hw, I40E_PFINT_LNKLST0, val); 1254 for (i = 0; i < num_pf_int - 2; i++) 1255 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1256 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1257 for (i = 0; i < num_vfs; i++) 1258 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1259 for (i = 0; i < num_vf_int - 2; i++) 1260 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1261 1262 /* warn the HW of the coming Tx disables */ 1263 for (i = 0; i < num_queues; i++) { 1264 u32 abs_queue_idx = base_queue + i; 1265 u32 reg_block = 0; 1266 1267 if (abs_queue_idx >= 128) { 1268 reg_block = abs_queue_idx / 128; 1269 abs_queue_idx %= 128; 1270 } 1271 1272 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1273 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1274 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1275 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1276 1277 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1278 } 1279 udelay(400); 1280 1281 /* stop all the queues */ 1282 for (i = 0; i < num_queues; i++) { 1283 wr32(hw, I40E_QINT_TQCTL(i), 0); 1284 wr32(hw, I40E_QTX_ENA(i), 0); 1285 wr32(hw, I40E_QINT_RQCTL(i), 0); 1286 wr32(hw, I40E_QRX_ENA(i), 0); 1287 } 1288 1289 /* short wait for all queue disables to settle */ 1290 udelay(50); 1291 } 1292 1293 /** 1294 * i40e_clear_pxe_mode - clear pxe operations mode 1295 * @hw: pointer to the hw struct 1296 * 1297 * Make sure all PXE mode settings are cleared, including things 1298 * like descriptor fetch/write-back mode. 1299 **/ 1300 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1301 { 1302 u32 reg; 1303 1304 if (i40e_check_asq_alive(hw)) 1305 i40e_aq_clear_pxe_mode(hw, NULL); 1306 1307 /* Clear single descriptor fetch/write-back mode */ 1308 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1309 1310 if (hw->revision_id == 0) { 1311 /* As a work around clear PXE_MODE instead of setting it */ 1312 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1313 } else { 1314 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1315 } 1316 } 1317 1318 /** 1319 * i40e_led_is_mine - helper to find matching led 1320 * @hw: pointer to the hw struct 1321 * @idx: index into GPIO registers 1322 * 1323 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1324 */ 1325 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1326 { 1327 u32 gpio_val = 0; 1328 u32 port; 1329 1330 if (!I40E_IS_X710TL_DEVICE(hw->device_id) && 1331 !hw->func_caps.led[idx]) 1332 return 0; 1333 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1334 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1335 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1336 1337 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1338 * if it is not our port then ignore 1339 */ 1340 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1341 (port != hw->port)) 1342 return 0; 1343 1344 return gpio_val; 1345 } 1346 1347 #define I40E_FW_LED BIT(4) 1348 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \ 1349 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 1350 1351 #define I40E_LED0 22 1352 1353 #define I40E_PIN_FUNC_SDP 0x0 1354 #define I40E_PIN_FUNC_LED 0x1 1355 1356 /** 1357 * i40e_led_get - return current on/off mode 1358 * @hw: pointer to the hw struct 1359 * 1360 * The value returned is the 'mode' field as defined in the 1361 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1362 * values are variations of possible behaviors relating to 1363 * blink, link, and wire. 1364 **/ 1365 u32 i40e_led_get(struct i40e_hw *hw) 1366 { 1367 u32 mode = 0; 1368 int i; 1369 1370 /* as per the documentation GPIO 22-29 are the LED 1371 * GPIO pins named LED0..LED7 1372 */ 1373 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1374 u32 gpio_val = i40e_led_is_mine(hw, i); 1375 1376 if (!gpio_val) 1377 continue; 1378 1379 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1380 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1381 break; 1382 } 1383 1384 return mode; 1385 } 1386 1387 /** 1388 * i40e_led_set - set new on/off mode 1389 * @hw: pointer to the hw struct 1390 * @mode: 0=off, 0xf=on (else see manual for mode details) 1391 * @blink: true if the LED should blink when on, false if steady 1392 * 1393 * if this function is used to turn on the blink it should 1394 * be used to disable the blink when restoring the original state. 1395 **/ 1396 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1397 { 1398 int i; 1399 1400 if (mode & ~I40E_LED_MODE_VALID) { 1401 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1402 return; 1403 } 1404 1405 /* as per the documentation GPIO 22-29 are the LED 1406 * GPIO pins named LED0..LED7 1407 */ 1408 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1409 u32 gpio_val = i40e_led_is_mine(hw, i); 1410 1411 if (!gpio_val) 1412 continue; 1413 1414 if (I40E_IS_X710TL_DEVICE(hw->device_id)) { 1415 u32 pin_func = 0; 1416 1417 if (mode & I40E_FW_LED) 1418 pin_func = I40E_PIN_FUNC_SDP; 1419 else 1420 pin_func = I40E_PIN_FUNC_LED; 1421 1422 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK; 1423 gpio_val |= ((pin_func << 1424 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) & 1425 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK); 1426 } 1427 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1428 /* this & is a bit of paranoia, but serves as a range check */ 1429 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1430 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1431 1432 if (blink) 1433 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1434 else 1435 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1436 1437 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1438 break; 1439 } 1440 } 1441 1442 /* Admin command wrappers */ 1443 1444 /** 1445 * i40e_aq_get_phy_capabilities 1446 * @hw: pointer to the hw struct 1447 * @abilities: structure for PHY capabilities to be filled 1448 * @qualified_modules: report Qualified Modules 1449 * @report_init: report init capabilities (active are default) 1450 * @cmd_details: pointer to command details structure or NULL 1451 * 1452 * Returns the various PHY abilities supported on the Port. 1453 **/ 1454 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1455 bool qualified_modules, bool report_init, 1456 struct i40e_aq_get_phy_abilities_resp *abilities, 1457 struct i40e_asq_cmd_details *cmd_details) 1458 { 1459 struct i40e_aq_desc desc; 1460 i40e_status status; 1461 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1462 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1463 1464 if (!abilities) 1465 return I40E_ERR_PARAM; 1466 1467 do { 1468 i40e_fill_default_direct_cmd_desc(&desc, 1469 i40e_aqc_opc_get_phy_abilities); 1470 1471 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1472 if (abilities_size > I40E_AQ_LARGE_BUF) 1473 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1474 1475 if (qualified_modules) 1476 desc.params.external.param0 |= 1477 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1478 1479 if (report_init) 1480 desc.params.external.param0 |= 1481 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1482 1483 status = i40e_asq_send_command(hw, &desc, abilities, 1484 abilities_size, cmd_details); 1485 1486 switch (hw->aq.asq_last_status) { 1487 case I40E_AQ_RC_EIO: 1488 status = I40E_ERR_UNKNOWN_PHY; 1489 break; 1490 case I40E_AQ_RC_EAGAIN: 1491 usleep_range(1000, 2000); 1492 total_delay++; 1493 status = I40E_ERR_TIMEOUT; 1494 break; 1495 /* also covers I40E_AQ_RC_OK */ 1496 default: 1497 break; 1498 } 1499 1500 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1501 (total_delay < max_delay)); 1502 1503 if (status) 1504 return status; 1505 1506 if (report_init) { 1507 if (hw->mac.type == I40E_MAC_XL710 && 1508 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1509 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1510 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1511 } else { 1512 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1513 hw->phy.phy_types |= 1514 ((u64)abilities->phy_type_ext << 32); 1515 } 1516 } 1517 1518 return status; 1519 } 1520 1521 /** 1522 * i40e_aq_set_phy_config 1523 * @hw: pointer to the hw struct 1524 * @config: structure with PHY configuration to be set 1525 * @cmd_details: pointer to command details structure or NULL 1526 * 1527 * Set the various PHY configuration parameters 1528 * supported on the Port.One or more of the Set PHY config parameters may be 1529 * ignored in an MFP mode as the PF may not have the privilege to set some 1530 * of the PHY Config parameters. This status will be indicated by the 1531 * command response. 1532 **/ 1533 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1534 struct i40e_aq_set_phy_config *config, 1535 struct i40e_asq_cmd_details *cmd_details) 1536 { 1537 struct i40e_aq_desc desc; 1538 struct i40e_aq_set_phy_config *cmd = 1539 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1540 enum i40e_status_code status; 1541 1542 if (!config) 1543 return I40E_ERR_PARAM; 1544 1545 i40e_fill_default_direct_cmd_desc(&desc, 1546 i40e_aqc_opc_set_phy_config); 1547 1548 *cmd = *config; 1549 1550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1551 1552 return status; 1553 } 1554 1555 static noinline_for_stack enum i40e_status_code 1556 i40e_set_fc_status(struct i40e_hw *hw, 1557 struct i40e_aq_get_phy_abilities_resp *abilities, 1558 bool atomic_restart) 1559 { 1560 struct i40e_aq_set_phy_config config; 1561 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1562 u8 pause_mask = 0x0; 1563 1564 switch (fc_mode) { 1565 case I40E_FC_FULL: 1566 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1567 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1568 break; 1569 case I40E_FC_RX_PAUSE: 1570 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1571 break; 1572 case I40E_FC_TX_PAUSE: 1573 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1580 /* clear the old pause settings */ 1581 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1582 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1583 /* set the new abilities */ 1584 config.abilities |= pause_mask; 1585 /* If the abilities have changed, then set the new config */ 1586 if (config.abilities == abilities->abilities) 1587 return 0; 1588 1589 /* Auto restart link so settings take effect */ 1590 if (atomic_restart) 1591 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1592 /* Copy over all the old settings */ 1593 config.phy_type = abilities->phy_type; 1594 config.phy_type_ext = abilities->phy_type_ext; 1595 config.link_speed = abilities->link_speed; 1596 config.eee_capability = abilities->eee_capability; 1597 config.eeer = abilities->eeer_val; 1598 config.low_power_ctrl = abilities->d3_lpan; 1599 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1600 I40E_AQ_PHY_FEC_CONFIG_MASK; 1601 1602 return i40e_aq_set_phy_config(hw, &config, NULL); 1603 } 1604 1605 /** 1606 * i40e_set_fc 1607 * @hw: pointer to the hw struct 1608 * @aq_failures: buffer to return AdminQ failure information 1609 * @atomic_restart: whether to enable atomic link restart 1610 * 1611 * Set the requested flow control mode using set_phy_config. 1612 **/ 1613 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1614 bool atomic_restart) 1615 { 1616 struct i40e_aq_get_phy_abilities_resp abilities; 1617 enum i40e_status_code status; 1618 1619 *aq_failures = 0x0; 1620 1621 /* Get the current phy config */ 1622 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1623 NULL); 1624 if (status) { 1625 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1626 return status; 1627 } 1628 1629 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1630 if (status) 1631 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1632 1633 /* Update the link info */ 1634 status = i40e_update_link_info(hw); 1635 if (status) { 1636 /* Wait a little bit (on 40G cards it sometimes takes a really 1637 * long time for link to come back from the atomic reset) 1638 * and try once more 1639 */ 1640 msleep(1000); 1641 status = i40e_update_link_info(hw); 1642 } 1643 if (status) 1644 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1645 1646 return status; 1647 } 1648 1649 /** 1650 * i40e_aq_clear_pxe_mode 1651 * @hw: pointer to the hw struct 1652 * @cmd_details: pointer to command details structure or NULL 1653 * 1654 * Tell the firmware that the driver is taking over from PXE 1655 **/ 1656 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1657 struct i40e_asq_cmd_details *cmd_details) 1658 { 1659 i40e_status status; 1660 struct i40e_aq_desc desc; 1661 struct i40e_aqc_clear_pxe *cmd = 1662 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1663 1664 i40e_fill_default_direct_cmd_desc(&desc, 1665 i40e_aqc_opc_clear_pxe_mode); 1666 1667 cmd->rx_cnt = 0x2; 1668 1669 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1670 1671 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1672 1673 return status; 1674 } 1675 1676 /** 1677 * i40e_aq_set_link_restart_an 1678 * @hw: pointer to the hw struct 1679 * @enable_link: if true: enable link, if false: disable link 1680 * @cmd_details: pointer to command details structure or NULL 1681 * 1682 * Sets up the link and restarts the Auto-Negotiation over the link. 1683 **/ 1684 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1685 bool enable_link, 1686 struct i40e_asq_cmd_details *cmd_details) 1687 { 1688 struct i40e_aq_desc desc; 1689 struct i40e_aqc_set_link_restart_an *cmd = 1690 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1691 i40e_status status; 1692 1693 i40e_fill_default_direct_cmd_desc(&desc, 1694 i40e_aqc_opc_set_link_restart_an); 1695 1696 cmd->command = I40E_AQ_PHY_RESTART_AN; 1697 if (enable_link) 1698 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1699 else 1700 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1701 1702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1703 1704 return status; 1705 } 1706 1707 /** 1708 * i40e_aq_get_link_info 1709 * @hw: pointer to the hw struct 1710 * @enable_lse: enable/disable LinkStatusEvent reporting 1711 * @link: pointer to link status structure - optional 1712 * @cmd_details: pointer to command details structure or NULL 1713 * 1714 * Returns the link status of the adapter. 1715 **/ 1716 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1717 bool enable_lse, struct i40e_link_status *link, 1718 struct i40e_asq_cmd_details *cmd_details) 1719 { 1720 struct i40e_aq_desc desc; 1721 struct i40e_aqc_get_link_status *resp = 1722 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1723 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1724 i40e_status status; 1725 bool tx_pause, rx_pause; 1726 u16 command_flags; 1727 1728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1729 1730 if (enable_lse) 1731 command_flags = I40E_AQ_LSE_ENABLE; 1732 else 1733 command_flags = I40E_AQ_LSE_DISABLE; 1734 resp->command_flags = cpu_to_le16(command_flags); 1735 1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1737 1738 if (status) 1739 goto aq_get_link_info_exit; 1740 1741 /* save off old link status information */ 1742 hw->phy.link_info_old = *hw_link_info; 1743 1744 /* update link status */ 1745 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1746 hw->phy.media_type = i40e_get_media_type(hw); 1747 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1748 hw_link_info->link_info = resp->link_info; 1749 hw_link_info->an_info = resp->an_info; 1750 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1751 I40E_AQ_CONFIG_FEC_RS_ENA); 1752 hw_link_info->ext_info = resp->ext_info; 1753 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1754 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1755 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1756 1757 /* update fc info */ 1758 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1759 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1760 if (tx_pause & rx_pause) 1761 hw->fc.current_mode = I40E_FC_FULL; 1762 else if (tx_pause) 1763 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1764 else if (rx_pause) 1765 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1766 else 1767 hw->fc.current_mode = I40E_FC_NONE; 1768 1769 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1770 hw_link_info->crc_enable = true; 1771 else 1772 hw_link_info->crc_enable = false; 1773 1774 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1775 hw_link_info->lse_enable = true; 1776 else 1777 hw_link_info->lse_enable = false; 1778 1779 if ((hw->mac.type == I40E_MAC_XL710) && 1780 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1781 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1782 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1783 1784 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE && 1785 hw->mac.type != I40E_MAC_X722) { 1786 __le32 tmp; 1787 1788 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1789 hw->phy.phy_types = le32_to_cpu(tmp); 1790 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1791 } 1792 1793 /* save link status information */ 1794 if (link) 1795 *link = *hw_link_info; 1796 1797 /* flag cleared so helper functions don't call AQ again */ 1798 hw->phy.get_link_info = false; 1799 1800 aq_get_link_info_exit: 1801 return status; 1802 } 1803 1804 /** 1805 * i40e_aq_set_phy_int_mask 1806 * @hw: pointer to the hw struct 1807 * @mask: interrupt mask to be set 1808 * @cmd_details: pointer to command details structure or NULL 1809 * 1810 * Set link interrupt mask. 1811 **/ 1812 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1813 u16 mask, 1814 struct i40e_asq_cmd_details *cmd_details) 1815 { 1816 struct i40e_aq_desc desc; 1817 struct i40e_aqc_set_phy_int_mask *cmd = 1818 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1819 i40e_status status; 1820 1821 i40e_fill_default_direct_cmd_desc(&desc, 1822 i40e_aqc_opc_set_phy_int_mask); 1823 1824 cmd->event_mask = cpu_to_le16(mask); 1825 1826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1827 1828 return status; 1829 } 1830 1831 /** 1832 * i40e_aq_set_phy_debug 1833 * @hw: pointer to the hw struct 1834 * @cmd_flags: debug command flags 1835 * @cmd_details: pointer to command details structure or NULL 1836 * 1837 * Reset the external PHY. 1838 **/ 1839 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1840 struct i40e_asq_cmd_details *cmd_details) 1841 { 1842 struct i40e_aq_desc desc; 1843 struct i40e_aqc_set_phy_debug *cmd = 1844 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1845 i40e_status status; 1846 1847 i40e_fill_default_direct_cmd_desc(&desc, 1848 i40e_aqc_opc_set_phy_debug); 1849 1850 cmd->command_flags = cmd_flags; 1851 1852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1853 1854 return status; 1855 } 1856 1857 /** 1858 * i40e_is_aq_api_ver_ge 1859 * @aq: pointer to AdminQ info containing HW API version to compare 1860 * @maj: API major value 1861 * @min: API minor value 1862 * 1863 * Assert whether current HW API version is greater/equal than provided. 1864 **/ 1865 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj, 1866 u16 min) 1867 { 1868 return (aq->api_maj_ver > maj || 1869 (aq->api_maj_ver == maj && aq->api_min_ver >= min)); 1870 } 1871 1872 /** 1873 * i40e_aq_add_vsi 1874 * @hw: pointer to the hw struct 1875 * @vsi_ctx: pointer to a vsi context struct 1876 * @cmd_details: pointer to command details structure or NULL 1877 * 1878 * Add a VSI context to the hardware. 1879 **/ 1880 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1881 struct i40e_vsi_context *vsi_ctx, 1882 struct i40e_asq_cmd_details *cmd_details) 1883 { 1884 struct i40e_aq_desc desc; 1885 struct i40e_aqc_add_get_update_vsi *cmd = 1886 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1887 struct i40e_aqc_add_get_update_vsi_completion *resp = 1888 (struct i40e_aqc_add_get_update_vsi_completion *) 1889 &desc.params.raw; 1890 i40e_status status; 1891 1892 i40e_fill_default_direct_cmd_desc(&desc, 1893 i40e_aqc_opc_add_vsi); 1894 1895 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1896 cmd->connection_type = vsi_ctx->connection_type; 1897 cmd->vf_id = vsi_ctx->vf_num; 1898 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1899 1900 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1901 1902 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1903 sizeof(vsi_ctx->info), cmd_details); 1904 1905 if (status) 1906 goto aq_add_vsi_exit; 1907 1908 vsi_ctx->seid = le16_to_cpu(resp->seid); 1909 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1910 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1911 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1912 1913 aq_add_vsi_exit: 1914 return status; 1915 } 1916 1917 /** 1918 * i40e_aq_set_default_vsi 1919 * @hw: pointer to the hw struct 1920 * @seid: vsi number 1921 * @cmd_details: pointer to command details structure or NULL 1922 **/ 1923 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 1924 u16 seid, 1925 struct i40e_asq_cmd_details *cmd_details) 1926 { 1927 struct i40e_aq_desc desc; 1928 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1929 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1930 &desc.params.raw; 1931 i40e_status status; 1932 1933 i40e_fill_default_direct_cmd_desc(&desc, 1934 i40e_aqc_opc_set_vsi_promiscuous_modes); 1935 1936 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1937 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1938 cmd->seid = cpu_to_le16(seid); 1939 1940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1941 1942 return status; 1943 } 1944 1945 /** 1946 * i40e_aq_clear_default_vsi 1947 * @hw: pointer to the hw struct 1948 * @seid: vsi number 1949 * @cmd_details: pointer to command details structure or NULL 1950 **/ 1951 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1952 u16 seid, 1953 struct i40e_asq_cmd_details *cmd_details) 1954 { 1955 struct i40e_aq_desc desc; 1956 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1957 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1958 &desc.params.raw; 1959 i40e_status status; 1960 1961 i40e_fill_default_direct_cmd_desc(&desc, 1962 i40e_aqc_opc_set_vsi_promiscuous_modes); 1963 1964 cmd->promiscuous_flags = cpu_to_le16(0); 1965 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1966 cmd->seid = cpu_to_le16(seid); 1967 1968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1969 1970 return status; 1971 } 1972 1973 /** 1974 * i40e_aq_set_vsi_unicast_promiscuous 1975 * @hw: pointer to the hw struct 1976 * @seid: vsi number 1977 * @set: set unicast promiscuous enable/disable 1978 * @cmd_details: pointer to command details structure or NULL 1979 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 1980 **/ 1981 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1982 u16 seid, bool set, 1983 struct i40e_asq_cmd_details *cmd_details, 1984 bool rx_only_promisc) 1985 { 1986 struct i40e_aq_desc desc; 1987 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1988 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1989 i40e_status status; 1990 u16 flags = 0; 1991 1992 i40e_fill_default_direct_cmd_desc(&desc, 1993 i40e_aqc_opc_set_vsi_promiscuous_modes); 1994 1995 if (set) { 1996 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1997 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5)) 1998 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 1999 } 2000 2001 cmd->promiscuous_flags = cpu_to_le16(flags); 2002 2003 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2004 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5)) 2005 cmd->valid_flags |= 2006 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2007 2008 cmd->seid = cpu_to_le16(seid); 2009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2010 2011 return status; 2012 } 2013 2014 /** 2015 * i40e_aq_set_vsi_multicast_promiscuous 2016 * @hw: pointer to the hw struct 2017 * @seid: vsi number 2018 * @set: set multicast promiscuous enable/disable 2019 * @cmd_details: pointer to command details structure or NULL 2020 **/ 2021 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2022 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2023 { 2024 struct i40e_aq_desc desc; 2025 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2026 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2027 i40e_status status; 2028 u16 flags = 0; 2029 2030 i40e_fill_default_direct_cmd_desc(&desc, 2031 i40e_aqc_opc_set_vsi_promiscuous_modes); 2032 2033 if (set) 2034 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2035 2036 cmd->promiscuous_flags = cpu_to_le16(flags); 2037 2038 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2039 2040 cmd->seid = cpu_to_le16(seid); 2041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2042 2043 return status; 2044 } 2045 2046 /** 2047 * i40e_aq_set_vsi_mc_promisc_on_vlan 2048 * @hw: pointer to the hw struct 2049 * @seid: vsi number 2050 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2051 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2052 * @cmd_details: pointer to command details structure or NULL 2053 **/ 2054 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2055 u16 seid, bool enable, 2056 u16 vid, 2057 struct i40e_asq_cmd_details *cmd_details) 2058 { 2059 struct i40e_aq_desc desc; 2060 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2061 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2062 enum i40e_status_code status; 2063 u16 flags = 0; 2064 2065 i40e_fill_default_direct_cmd_desc(&desc, 2066 i40e_aqc_opc_set_vsi_promiscuous_modes); 2067 2068 if (enable) 2069 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2070 2071 cmd->promiscuous_flags = cpu_to_le16(flags); 2072 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2073 cmd->seid = cpu_to_le16(seid); 2074 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2075 2076 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 2077 cmd_details, true); 2078 2079 return status; 2080 } 2081 2082 /** 2083 * i40e_aq_set_vsi_uc_promisc_on_vlan 2084 * @hw: pointer to the hw struct 2085 * @seid: vsi number 2086 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2087 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2088 * @cmd_details: pointer to command details structure or NULL 2089 **/ 2090 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2091 u16 seid, bool enable, 2092 u16 vid, 2093 struct i40e_asq_cmd_details *cmd_details) 2094 { 2095 struct i40e_aq_desc desc; 2096 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2097 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2098 enum i40e_status_code status; 2099 u16 flags = 0; 2100 2101 i40e_fill_default_direct_cmd_desc(&desc, 2102 i40e_aqc_opc_set_vsi_promiscuous_modes); 2103 2104 if (enable) { 2105 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2106 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5)) 2107 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY; 2108 } 2109 2110 cmd->promiscuous_flags = cpu_to_le16(flags); 2111 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2112 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5)) 2113 cmd->valid_flags |= 2114 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY); 2115 cmd->seid = cpu_to_le16(seid); 2116 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2117 2118 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0, 2119 cmd_details, true); 2120 2121 return status; 2122 } 2123 2124 /** 2125 * i40e_aq_set_vsi_bc_promisc_on_vlan 2126 * @hw: pointer to the hw struct 2127 * @seid: vsi number 2128 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2129 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2130 * @cmd_details: pointer to command details structure or NULL 2131 **/ 2132 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2133 u16 seid, bool enable, u16 vid, 2134 struct i40e_asq_cmd_details *cmd_details) 2135 { 2136 struct i40e_aq_desc desc; 2137 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2138 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2139 i40e_status status; 2140 u16 flags = 0; 2141 2142 i40e_fill_default_direct_cmd_desc(&desc, 2143 i40e_aqc_opc_set_vsi_promiscuous_modes); 2144 2145 if (enable) 2146 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2147 2148 cmd->promiscuous_flags = cpu_to_le16(flags); 2149 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2150 cmd->seid = cpu_to_le16(seid); 2151 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2152 2153 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2154 2155 return status; 2156 } 2157 2158 /** 2159 * i40e_aq_set_vsi_broadcast 2160 * @hw: pointer to the hw struct 2161 * @seid: vsi number 2162 * @set_filter: true to set filter, false to clear filter 2163 * @cmd_details: pointer to command details structure or NULL 2164 * 2165 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2166 **/ 2167 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2168 u16 seid, bool set_filter, 2169 struct i40e_asq_cmd_details *cmd_details) 2170 { 2171 struct i40e_aq_desc desc; 2172 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2173 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2174 i40e_status status; 2175 2176 i40e_fill_default_direct_cmd_desc(&desc, 2177 i40e_aqc_opc_set_vsi_promiscuous_modes); 2178 2179 if (set_filter) 2180 cmd->promiscuous_flags 2181 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2182 else 2183 cmd->promiscuous_flags 2184 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2185 2186 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2187 cmd->seid = cpu_to_le16(seid); 2188 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2189 2190 return status; 2191 } 2192 2193 /** 2194 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2195 * @hw: pointer to the hw struct 2196 * @seid: vsi number 2197 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2198 * @cmd_details: pointer to command details structure or NULL 2199 **/ 2200 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2201 u16 seid, bool enable, 2202 struct i40e_asq_cmd_details *cmd_details) 2203 { 2204 struct i40e_aq_desc desc; 2205 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2206 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2207 i40e_status status; 2208 u16 flags = 0; 2209 2210 i40e_fill_default_direct_cmd_desc(&desc, 2211 i40e_aqc_opc_set_vsi_promiscuous_modes); 2212 if (enable) 2213 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2214 2215 cmd->promiscuous_flags = cpu_to_le16(flags); 2216 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2217 cmd->seid = cpu_to_le16(seid); 2218 2219 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2220 2221 return status; 2222 } 2223 2224 /** 2225 * i40e_aq_get_vsi_params - get VSI configuration info 2226 * @hw: pointer to the hw struct 2227 * @vsi_ctx: pointer to a vsi context struct 2228 * @cmd_details: pointer to command details structure or NULL 2229 **/ 2230 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2231 struct i40e_vsi_context *vsi_ctx, 2232 struct i40e_asq_cmd_details *cmd_details) 2233 { 2234 struct i40e_aq_desc desc; 2235 struct i40e_aqc_add_get_update_vsi *cmd = 2236 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2237 struct i40e_aqc_add_get_update_vsi_completion *resp = 2238 (struct i40e_aqc_add_get_update_vsi_completion *) 2239 &desc.params.raw; 2240 i40e_status status; 2241 2242 i40e_fill_default_direct_cmd_desc(&desc, 2243 i40e_aqc_opc_get_vsi_parameters); 2244 2245 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2246 2247 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2248 2249 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2250 sizeof(vsi_ctx->info), NULL); 2251 2252 if (status) 2253 goto aq_get_vsi_params_exit; 2254 2255 vsi_ctx->seid = le16_to_cpu(resp->seid); 2256 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2257 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2258 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2259 2260 aq_get_vsi_params_exit: 2261 return status; 2262 } 2263 2264 /** 2265 * i40e_aq_update_vsi_params 2266 * @hw: pointer to the hw struct 2267 * @vsi_ctx: pointer to a vsi context struct 2268 * @cmd_details: pointer to command details structure or NULL 2269 * 2270 * Update a VSI context. 2271 **/ 2272 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2273 struct i40e_vsi_context *vsi_ctx, 2274 struct i40e_asq_cmd_details *cmd_details) 2275 { 2276 struct i40e_aq_desc desc; 2277 struct i40e_aqc_add_get_update_vsi *cmd = 2278 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2279 struct i40e_aqc_add_get_update_vsi_completion *resp = 2280 (struct i40e_aqc_add_get_update_vsi_completion *) 2281 &desc.params.raw; 2282 i40e_status status; 2283 2284 i40e_fill_default_direct_cmd_desc(&desc, 2285 i40e_aqc_opc_update_vsi_parameters); 2286 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2287 2288 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2289 2290 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2291 sizeof(vsi_ctx->info), cmd_details); 2292 2293 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2294 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2295 2296 return status; 2297 } 2298 2299 /** 2300 * i40e_aq_get_switch_config 2301 * @hw: pointer to the hardware structure 2302 * @buf: pointer to the result buffer 2303 * @buf_size: length of input buffer 2304 * @start_seid: seid to start for the report, 0 == beginning 2305 * @cmd_details: pointer to command details structure or NULL 2306 * 2307 * Fill the buf with switch configuration returned from AdminQ command 2308 **/ 2309 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2310 struct i40e_aqc_get_switch_config_resp *buf, 2311 u16 buf_size, u16 *start_seid, 2312 struct i40e_asq_cmd_details *cmd_details) 2313 { 2314 struct i40e_aq_desc desc; 2315 struct i40e_aqc_switch_seid *scfg = 2316 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2317 i40e_status status; 2318 2319 i40e_fill_default_direct_cmd_desc(&desc, 2320 i40e_aqc_opc_get_switch_config); 2321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2322 if (buf_size > I40E_AQ_LARGE_BUF) 2323 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2324 scfg->seid = cpu_to_le16(*start_seid); 2325 2326 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2327 *start_seid = le16_to_cpu(scfg->seid); 2328 2329 return status; 2330 } 2331 2332 /** 2333 * i40e_aq_set_switch_config 2334 * @hw: pointer to the hardware structure 2335 * @flags: bit flag values to set 2336 * @mode: cloud filter mode 2337 * @valid_flags: which bit flags to set 2338 * @mode: cloud filter mode 2339 * @cmd_details: pointer to command details structure or NULL 2340 * 2341 * Set switch configuration bits 2342 **/ 2343 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2344 u16 flags, 2345 u16 valid_flags, u8 mode, 2346 struct i40e_asq_cmd_details *cmd_details) 2347 { 2348 struct i40e_aq_desc desc; 2349 struct i40e_aqc_set_switch_config *scfg = 2350 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2351 enum i40e_status_code status; 2352 2353 i40e_fill_default_direct_cmd_desc(&desc, 2354 i40e_aqc_opc_set_switch_config); 2355 scfg->flags = cpu_to_le16(flags); 2356 scfg->valid_flags = cpu_to_le16(valid_flags); 2357 scfg->mode = mode; 2358 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2359 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2360 scfg->first_tag = cpu_to_le16(hw->first_tag); 2361 scfg->second_tag = cpu_to_le16(hw->second_tag); 2362 } 2363 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2364 2365 return status; 2366 } 2367 2368 /** 2369 * i40e_aq_get_firmware_version 2370 * @hw: pointer to the hw struct 2371 * @fw_major_version: firmware major version 2372 * @fw_minor_version: firmware minor version 2373 * @fw_build: firmware build number 2374 * @api_major_version: major queue version 2375 * @api_minor_version: minor queue version 2376 * @cmd_details: pointer to command details structure or NULL 2377 * 2378 * Get the firmware version from the admin queue commands 2379 **/ 2380 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2381 u16 *fw_major_version, u16 *fw_minor_version, 2382 u32 *fw_build, 2383 u16 *api_major_version, u16 *api_minor_version, 2384 struct i40e_asq_cmd_details *cmd_details) 2385 { 2386 struct i40e_aq_desc desc; 2387 struct i40e_aqc_get_version *resp = 2388 (struct i40e_aqc_get_version *)&desc.params.raw; 2389 i40e_status status; 2390 2391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2392 2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2394 2395 if (!status) { 2396 if (fw_major_version) 2397 *fw_major_version = le16_to_cpu(resp->fw_major); 2398 if (fw_minor_version) 2399 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2400 if (fw_build) 2401 *fw_build = le32_to_cpu(resp->fw_build); 2402 if (api_major_version) 2403 *api_major_version = le16_to_cpu(resp->api_major); 2404 if (api_minor_version) 2405 *api_minor_version = le16_to_cpu(resp->api_minor); 2406 } 2407 2408 return status; 2409 } 2410 2411 /** 2412 * i40e_aq_send_driver_version 2413 * @hw: pointer to the hw struct 2414 * @dv: driver's major, minor version 2415 * @cmd_details: pointer to command details structure or NULL 2416 * 2417 * Send the driver version to the firmware 2418 **/ 2419 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2420 struct i40e_driver_version *dv, 2421 struct i40e_asq_cmd_details *cmd_details) 2422 { 2423 struct i40e_aq_desc desc; 2424 struct i40e_aqc_driver_version *cmd = 2425 (struct i40e_aqc_driver_version *)&desc.params.raw; 2426 i40e_status status; 2427 u16 len; 2428 2429 if (dv == NULL) 2430 return I40E_ERR_PARAM; 2431 2432 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2433 2434 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2435 cmd->driver_major_ver = dv->major_version; 2436 cmd->driver_minor_ver = dv->minor_version; 2437 cmd->driver_build_ver = dv->build_version; 2438 cmd->driver_subbuild_ver = dv->subbuild_version; 2439 2440 len = 0; 2441 while (len < sizeof(dv->driver_string) && 2442 (dv->driver_string[len] < 0x80) && 2443 dv->driver_string[len]) 2444 len++; 2445 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2446 len, cmd_details); 2447 2448 return status; 2449 } 2450 2451 /** 2452 * i40e_get_link_status - get status of the HW network link 2453 * @hw: pointer to the hw struct 2454 * @link_up: pointer to bool (true/false = linkup/linkdown) 2455 * 2456 * Variable link_up true if link is up, false if link is down. 2457 * The variable link_up is invalid if returned value of status != 0 2458 * 2459 * Side effect: LinkStatusEvent reporting becomes enabled 2460 **/ 2461 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2462 { 2463 i40e_status status = 0; 2464 2465 if (hw->phy.get_link_info) { 2466 status = i40e_update_link_info(hw); 2467 2468 if (status) 2469 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2470 status); 2471 } 2472 2473 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2474 2475 return status; 2476 } 2477 2478 /** 2479 * i40e_update_link_info - update status of the HW network link 2480 * @hw: pointer to the hw struct 2481 **/ 2482 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw) 2483 { 2484 struct i40e_aq_get_phy_abilities_resp abilities; 2485 i40e_status status = 0; 2486 2487 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2488 if (status) 2489 return status; 2490 2491 /* extra checking needed to ensure link info to user is timely */ 2492 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2493 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2494 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2495 status = i40e_aq_get_phy_capabilities(hw, false, false, 2496 &abilities, NULL); 2497 if (status) 2498 return status; 2499 2500 if (abilities.fec_cfg_curr_mod_ext_info & 2501 I40E_AQ_ENABLE_FEC_AUTO) 2502 hw->phy.link_info.req_fec_info = 2503 (I40E_AQ_REQUEST_FEC_KR | 2504 I40E_AQ_REQUEST_FEC_RS); 2505 else 2506 hw->phy.link_info.req_fec_info = 2507 abilities.fec_cfg_curr_mod_ext_info & 2508 (I40E_AQ_REQUEST_FEC_KR | 2509 I40E_AQ_REQUEST_FEC_RS); 2510 2511 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2512 sizeof(hw->phy.link_info.module_type)); 2513 } 2514 2515 return status; 2516 } 2517 2518 /** 2519 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2520 * @hw: pointer to the hw struct 2521 * @uplink_seid: the MAC or other gizmo SEID 2522 * @downlink_seid: the VSI SEID 2523 * @enabled_tc: bitmap of TCs to be enabled 2524 * @default_port: true for default port VSI, false for control port 2525 * @veb_seid: pointer to where to put the resulting VEB SEID 2526 * @enable_stats: true to turn on VEB stats 2527 * @cmd_details: pointer to command details structure or NULL 2528 * 2529 * This asks the FW to add a VEB between the uplink and downlink 2530 * elements. If the uplink SEID is 0, this will be a floating VEB. 2531 **/ 2532 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2533 u16 downlink_seid, u8 enabled_tc, 2534 bool default_port, u16 *veb_seid, 2535 bool enable_stats, 2536 struct i40e_asq_cmd_details *cmd_details) 2537 { 2538 struct i40e_aq_desc desc; 2539 struct i40e_aqc_add_veb *cmd = 2540 (struct i40e_aqc_add_veb *)&desc.params.raw; 2541 struct i40e_aqc_add_veb_completion *resp = 2542 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2543 i40e_status status; 2544 u16 veb_flags = 0; 2545 2546 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2547 if (!!uplink_seid != !!downlink_seid) 2548 return I40E_ERR_PARAM; 2549 2550 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2551 2552 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2553 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2554 cmd->enable_tcs = enabled_tc; 2555 if (!uplink_seid) 2556 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2557 if (default_port) 2558 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2559 else 2560 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2561 2562 /* reverse logic here: set the bitflag to disable the stats */ 2563 if (!enable_stats) 2564 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2565 2566 cmd->veb_flags = cpu_to_le16(veb_flags); 2567 2568 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2569 2570 if (!status && veb_seid) 2571 *veb_seid = le16_to_cpu(resp->veb_seid); 2572 2573 return status; 2574 } 2575 2576 /** 2577 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2578 * @hw: pointer to the hw struct 2579 * @veb_seid: the SEID of the VEB to query 2580 * @switch_id: the uplink switch id 2581 * @floating: set to true if the VEB is floating 2582 * @statistic_index: index of the stats counter block for this VEB 2583 * @vebs_used: number of VEB's used by function 2584 * @vebs_free: total VEB's not reserved by any function 2585 * @cmd_details: pointer to command details structure or NULL 2586 * 2587 * This retrieves the parameters for a particular VEB, specified by 2588 * uplink_seid, and returns them to the caller. 2589 **/ 2590 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2591 u16 veb_seid, u16 *switch_id, 2592 bool *floating, u16 *statistic_index, 2593 u16 *vebs_used, u16 *vebs_free, 2594 struct i40e_asq_cmd_details *cmd_details) 2595 { 2596 struct i40e_aq_desc desc; 2597 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2598 (struct i40e_aqc_get_veb_parameters_completion *) 2599 &desc.params.raw; 2600 i40e_status status; 2601 2602 if (veb_seid == 0) 2603 return I40E_ERR_PARAM; 2604 2605 i40e_fill_default_direct_cmd_desc(&desc, 2606 i40e_aqc_opc_get_veb_parameters); 2607 cmd_resp->seid = cpu_to_le16(veb_seid); 2608 2609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2610 if (status) 2611 goto get_veb_exit; 2612 2613 if (switch_id) 2614 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2615 if (statistic_index) 2616 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2617 if (vebs_used) 2618 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2619 if (vebs_free) 2620 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2621 if (floating) { 2622 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2623 2624 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2625 *floating = true; 2626 else 2627 *floating = false; 2628 } 2629 2630 get_veb_exit: 2631 return status; 2632 } 2633 2634 /** 2635 * i40e_aq_add_macvlan 2636 * @hw: pointer to the hw struct 2637 * @seid: VSI for the mac address 2638 * @mv_list: list of macvlans to be added 2639 * @count: length of the list 2640 * @cmd_details: pointer to command details structure or NULL 2641 * 2642 * Add MAC/VLAN addresses to the HW filtering 2643 **/ 2644 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2645 struct i40e_aqc_add_macvlan_element_data *mv_list, 2646 u16 count, struct i40e_asq_cmd_details *cmd_details) 2647 { 2648 struct i40e_aq_desc desc; 2649 struct i40e_aqc_macvlan *cmd = 2650 (struct i40e_aqc_macvlan *)&desc.params.raw; 2651 i40e_status status; 2652 u16 buf_size; 2653 int i; 2654 2655 if (count == 0 || !mv_list || !hw) 2656 return I40E_ERR_PARAM; 2657 2658 buf_size = count * sizeof(*mv_list); 2659 2660 /* prep the rest of the request */ 2661 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2662 cmd->num_addresses = cpu_to_le16(count); 2663 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2664 cmd->seid[1] = 0; 2665 cmd->seid[2] = 0; 2666 2667 for (i = 0; i < count; i++) 2668 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2669 mv_list[i].flags |= 2670 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2671 2672 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2673 if (buf_size > I40E_AQ_LARGE_BUF) 2674 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2675 2676 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2677 cmd_details); 2678 2679 return status; 2680 } 2681 2682 /** 2683 * i40e_aq_remove_macvlan 2684 * @hw: pointer to the hw struct 2685 * @seid: VSI for the mac address 2686 * @mv_list: list of macvlans to be removed 2687 * @count: length of the list 2688 * @cmd_details: pointer to command details structure or NULL 2689 * 2690 * Remove MAC/VLAN addresses from the HW filtering 2691 **/ 2692 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2693 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2694 u16 count, struct i40e_asq_cmd_details *cmd_details) 2695 { 2696 struct i40e_aq_desc desc; 2697 struct i40e_aqc_macvlan *cmd = 2698 (struct i40e_aqc_macvlan *)&desc.params.raw; 2699 i40e_status status; 2700 u16 buf_size; 2701 2702 if (count == 0 || !mv_list || !hw) 2703 return I40E_ERR_PARAM; 2704 2705 buf_size = count * sizeof(*mv_list); 2706 2707 /* prep the rest of the request */ 2708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2709 cmd->num_addresses = cpu_to_le16(count); 2710 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2711 cmd->seid[1] = 0; 2712 cmd->seid[2] = 0; 2713 2714 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2715 if (buf_size > I40E_AQ_LARGE_BUF) 2716 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2717 2718 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2719 cmd_details); 2720 2721 return status; 2722 } 2723 2724 /** 2725 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2726 * @hw: pointer to the hw struct 2727 * @opcode: AQ opcode for add or delete mirror rule 2728 * @sw_seid: Switch SEID (to which rule refers) 2729 * @rule_type: Rule Type (ingress/egress/VLAN) 2730 * @id: Destination VSI SEID or Rule ID 2731 * @count: length of the list 2732 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2733 * @cmd_details: pointer to command details structure or NULL 2734 * @rule_id: Rule ID returned from FW 2735 * @rules_used: Number of rules used in internal switch 2736 * @rules_free: Number of rules free in internal switch 2737 * 2738 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2739 * VEBs/VEPA elements only 2740 **/ 2741 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2742 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2743 u16 count, __le16 *mr_list, 2744 struct i40e_asq_cmd_details *cmd_details, 2745 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2746 { 2747 struct i40e_aq_desc desc; 2748 struct i40e_aqc_add_delete_mirror_rule *cmd = 2749 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2750 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2751 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2752 i40e_status status; 2753 u16 buf_size; 2754 2755 buf_size = count * sizeof(*mr_list); 2756 2757 /* prep the rest of the request */ 2758 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2759 cmd->seid = cpu_to_le16(sw_seid); 2760 cmd->rule_type = cpu_to_le16(rule_type & 2761 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2762 cmd->num_entries = cpu_to_le16(count); 2763 /* Dest VSI for add, rule_id for delete */ 2764 cmd->destination = cpu_to_le16(id); 2765 if (mr_list) { 2766 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2767 I40E_AQ_FLAG_RD)); 2768 if (buf_size > I40E_AQ_LARGE_BUF) 2769 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2770 } 2771 2772 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2773 cmd_details); 2774 if (!status || 2775 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2776 if (rule_id) 2777 *rule_id = le16_to_cpu(resp->rule_id); 2778 if (rules_used) 2779 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2780 if (rules_free) 2781 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2782 } 2783 return status; 2784 } 2785 2786 /** 2787 * i40e_aq_add_mirrorrule - add a mirror rule 2788 * @hw: pointer to the hw struct 2789 * @sw_seid: Switch SEID (to which rule refers) 2790 * @rule_type: Rule Type (ingress/egress/VLAN) 2791 * @dest_vsi: SEID of VSI to which packets will be mirrored 2792 * @count: length of the list 2793 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2794 * @cmd_details: pointer to command details structure or NULL 2795 * @rule_id: Rule ID returned from FW 2796 * @rules_used: Number of rules used in internal switch 2797 * @rules_free: Number of rules free in internal switch 2798 * 2799 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2800 **/ 2801 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2802 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2803 struct i40e_asq_cmd_details *cmd_details, 2804 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2805 { 2806 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2807 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2808 if (count == 0 || !mr_list) 2809 return I40E_ERR_PARAM; 2810 } 2811 2812 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2813 rule_type, dest_vsi, count, mr_list, 2814 cmd_details, rule_id, rules_used, rules_free); 2815 } 2816 2817 /** 2818 * i40e_aq_delete_mirrorrule - delete a mirror rule 2819 * @hw: pointer to the hw struct 2820 * @sw_seid: Switch SEID (to which rule refers) 2821 * @rule_type: Rule Type (ingress/egress/VLAN) 2822 * @count: length of the list 2823 * @rule_id: Rule ID that is returned in the receive desc as part of 2824 * add_mirrorrule. 2825 * @mr_list: list of mirrored VLAN IDs to be removed 2826 * @cmd_details: pointer to command details structure or NULL 2827 * @rules_used: Number of rules used in internal switch 2828 * @rules_free: Number of rules free in internal switch 2829 * 2830 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2831 **/ 2832 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2833 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2834 struct i40e_asq_cmd_details *cmd_details, 2835 u16 *rules_used, u16 *rules_free) 2836 { 2837 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2838 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2839 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2840 * mirroring. For other rule_type, count and rule_type should 2841 * not matter. 2842 */ 2843 if (count == 0 || !mr_list) 2844 return I40E_ERR_PARAM; 2845 } 2846 2847 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2848 rule_type, rule_id, count, mr_list, 2849 cmd_details, NULL, rules_used, rules_free); 2850 } 2851 2852 /** 2853 * i40e_aq_send_msg_to_vf 2854 * @hw: pointer to the hardware structure 2855 * @vfid: VF id to send msg 2856 * @v_opcode: opcodes for VF-PF communication 2857 * @v_retval: return error code 2858 * @msg: pointer to the msg buffer 2859 * @msglen: msg length 2860 * @cmd_details: pointer to command details 2861 * 2862 * send msg to vf 2863 **/ 2864 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2865 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2866 struct i40e_asq_cmd_details *cmd_details) 2867 { 2868 struct i40e_aq_desc desc; 2869 struct i40e_aqc_pf_vf_message *cmd = 2870 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2871 i40e_status status; 2872 2873 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2874 cmd->id = cpu_to_le32(vfid); 2875 desc.cookie_high = cpu_to_le32(v_opcode); 2876 desc.cookie_low = cpu_to_le32(v_retval); 2877 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2878 if (msglen) { 2879 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2880 I40E_AQ_FLAG_RD)); 2881 if (msglen > I40E_AQ_LARGE_BUF) 2882 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2883 desc.datalen = cpu_to_le16(msglen); 2884 } 2885 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2886 2887 return status; 2888 } 2889 2890 /** 2891 * i40e_aq_debug_read_register 2892 * @hw: pointer to the hw struct 2893 * @reg_addr: register address 2894 * @reg_val: register value 2895 * @cmd_details: pointer to command details structure or NULL 2896 * 2897 * Read the register using the admin queue commands 2898 **/ 2899 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2900 u32 reg_addr, u64 *reg_val, 2901 struct i40e_asq_cmd_details *cmd_details) 2902 { 2903 struct i40e_aq_desc desc; 2904 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2905 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2906 i40e_status status; 2907 2908 if (reg_val == NULL) 2909 return I40E_ERR_PARAM; 2910 2911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2912 2913 cmd_resp->address = cpu_to_le32(reg_addr); 2914 2915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2916 2917 if (!status) { 2918 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2919 (u64)le32_to_cpu(cmd_resp->value_low); 2920 } 2921 2922 return status; 2923 } 2924 2925 /** 2926 * i40e_aq_debug_write_register 2927 * @hw: pointer to the hw struct 2928 * @reg_addr: register address 2929 * @reg_val: register value 2930 * @cmd_details: pointer to command details structure or NULL 2931 * 2932 * Write to a register using the admin queue commands 2933 **/ 2934 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2935 u32 reg_addr, u64 reg_val, 2936 struct i40e_asq_cmd_details *cmd_details) 2937 { 2938 struct i40e_aq_desc desc; 2939 struct i40e_aqc_debug_reg_read_write *cmd = 2940 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2941 i40e_status status; 2942 2943 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2944 2945 cmd->address = cpu_to_le32(reg_addr); 2946 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2947 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2948 2949 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2950 2951 return status; 2952 } 2953 2954 /** 2955 * i40e_aq_request_resource 2956 * @hw: pointer to the hw struct 2957 * @resource: resource id 2958 * @access: access type 2959 * @sdp_number: resource number 2960 * @timeout: the maximum time in ms that the driver may hold the resource 2961 * @cmd_details: pointer to command details structure or NULL 2962 * 2963 * requests common resource using the admin queue commands 2964 **/ 2965 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2966 enum i40e_aq_resources_ids resource, 2967 enum i40e_aq_resource_access_type access, 2968 u8 sdp_number, u64 *timeout, 2969 struct i40e_asq_cmd_details *cmd_details) 2970 { 2971 struct i40e_aq_desc desc; 2972 struct i40e_aqc_request_resource *cmd_resp = 2973 (struct i40e_aqc_request_resource *)&desc.params.raw; 2974 i40e_status status; 2975 2976 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2977 2978 cmd_resp->resource_id = cpu_to_le16(resource); 2979 cmd_resp->access_type = cpu_to_le16(access); 2980 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2981 2982 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2983 /* The completion specifies the maximum time in ms that the driver 2984 * may hold the resource in the Timeout field. 2985 * If the resource is held by someone else, the command completes with 2986 * busy return value and the timeout field indicates the maximum time 2987 * the current owner of the resource has to free it. 2988 */ 2989 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2990 *timeout = le32_to_cpu(cmd_resp->timeout); 2991 2992 return status; 2993 } 2994 2995 /** 2996 * i40e_aq_release_resource 2997 * @hw: pointer to the hw struct 2998 * @resource: resource id 2999 * @sdp_number: resource number 3000 * @cmd_details: pointer to command details structure or NULL 3001 * 3002 * release common resource using the admin queue commands 3003 **/ 3004 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3005 enum i40e_aq_resources_ids resource, 3006 u8 sdp_number, 3007 struct i40e_asq_cmd_details *cmd_details) 3008 { 3009 struct i40e_aq_desc desc; 3010 struct i40e_aqc_request_resource *cmd = 3011 (struct i40e_aqc_request_resource *)&desc.params.raw; 3012 i40e_status status; 3013 3014 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3015 3016 cmd->resource_id = cpu_to_le16(resource); 3017 cmd->resource_number = cpu_to_le32(sdp_number); 3018 3019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3020 3021 return status; 3022 } 3023 3024 /** 3025 * i40e_aq_read_nvm 3026 * @hw: pointer to the hw struct 3027 * @module_pointer: module pointer location in words from the NVM beginning 3028 * @offset: byte offset from the module beginning 3029 * @length: length of the section to be read (in bytes from the offset) 3030 * @data: command buffer (size [bytes] = length) 3031 * @last_command: tells if this is the last command in a series 3032 * @cmd_details: pointer to command details structure or NULL 3033 * 3034 * Read the NVM using the admin queue commands 3035 **/ 3036 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3037 u32 offset, u16 length, void *data, 3038 bool last_command, 3039 struct i40e_asq_cmd_details *cmd_details) 3040 { 3041 struct i40e_aq_desc desc; 3042 struct i40e_aqc_nvm_update *cmd = 3043 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3044 i40e_status status; 3045 3046 /* In offset the highest byte must be zeroed. */ 3047 if (offset & 0xFF000000) { 3048 status = I40E_ERR_PARAM; 3049 goto i40e_aq_read_nvm_exit; 3050 } 3051 3052 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3053 3054 /* If this is the last command in a series, set the proper flag. */ 3055 if (last_command) 3056 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3057 cmd->module_pointer = module_pointer; 3058 cmd->offset = cpu_to_le32(offset); 3059 cmd->length = cpu_to_le16(length); 3060 3061 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3062 if (length > I40E_AQ_LARGE_BUF) 3063 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3064 3065 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3066 3067 i40e_aq_read_nvm_exit: 3068 return status; 3069 } 3070 3071 /** 3072 * i40e_aq_erase_nvm 3073 * @hw: pointer to the hw struct 3074 * @module_pointer: module pointer location in words from the NVM beginning 3075 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3076 * @length: length of the section to be erased (expressed in 4 KB) 3077 * @last_command: tells if this is the last command in a series 3078 * @cmd_details: pointer to command details structure or NULL 3079 * 3080 * Erase the NVM sector using the admin queue commands 3081 **/ 3082 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3083 u32 offset, u16 length, bool last_command, 3084 struct i40e_asq_cmd_details *cmd_details) 3085 { 3086 struct i40e_aq_desc desc; 3087 struct i40e_aqc_nvm_update *cmd = 3088 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3089 i40e_status status; 3090 3091 /* In offset the highest byte must be zeroed. */ 3092 if (offset & 0xFF000000) { 3093 status = I40E_ERR_PARAM; 3094 goto i40e_aq_erase_nvm_exit; 3095 } 3096 3097 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3098 3099 /* If this is the last command in a series, set the proper flag. */ 3100 if (last_command) 3101 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3102 cmd->module_pointer = module_pointer; 3103 cmd->offset = cpu_to_le32(offset); 3104 cmd->length = cpu_to_le16(length); 3105 3106 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3107 3108 i40e_aq_erase_nvm_exit: 3109 return status; 3110 } 3111 3112 /** 3113 * i40e_parse_discover_capabilities 3114 * @hw: pointer to the hw struct 3115 * @buff: pointer to a buffer containing device/function capability records 3116 * @cap_count: number of capability records in the list 3117 * @list_type_opc: type of capabilities list to parse 3118 * 3119 * Parse the device/function capabilities list. 3120 **/ 3121 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3122 u32 cap_count, 3123 enum i40e_admin_queue_opc list_type_opc) 3124 { 3125 struct i40e_aqc_list_capabilities_element_resp *cap; 3126 u32 valid_functions, num_functions; 3127 u32 number, logical_id, phys_id; 3128 struct i40e_hw_capabilities *p; 3129 u16 id, ocp_cfg_word0; 3130 i40e_status status; 3131 u8 major_rev; 3132 u32 i = 0; 3133 3134 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3135 3136 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3137 p = &hw->dev_caps; 3138 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3139 p = &hw->func_caps; 3140 else 3141 return; 3142 3143 for (i = 0; i < cap_count; i++, cap++) { 3144 id = le16_to_cpu(cap->id); 3145 number = le32_to_cpu(cap->number); 3146 logical_id = le32_to_cpu(cap->logical_id); 3147 phys_id = le32_to_cpu(cap->phys_id); 3148 major_rev = cap->major_rev; 3149 3150 switch (id) { 3151 case I40E_AQ_CAP_ID_SWITCH_MODE: 3152 p->switch_mode = number; 3153 break; 3154 case I40E_AQ_CAP_ID_MNG_MODE: 3155 p->management_mode = number; 3156 if (major_rev > 1) { 3157 p->mng_protocols_over_mctp = logical_id; 3158 i40e_debug(hw, I40E_DEBUG_INIT, 3159 "HW Capability: Protocols over MCTP = %d\n", 3160 p->mng_protocols_over_mctp); 3161 } else { 3162 p->mng_protocols_over_mctp = 0; 3163 } 3164 break; 3165 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3166 p->npar_enable = number; 3167 break; 3168 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3169 p->os2bmc = number; 3170 break; 3171 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3172 p->valid_functions = number; 3173 break; 3174 case I40E_AQ_CAP_ID_SRIOV: 3175 if (number == 1) 3176 p->sr_iov_1_1 = true; 3177 break; 3178 case I40E_AQ_CAP_ID_VF: 3179 p->num_vfs = number; 3180 p->vf_base_id = logical_id; 3181 break; 3182 case I40E_AQ_CAP_ID_VMDQ: 3183 if (number == 1) 3184 p->vmdq = true; 3185 break; 3186 case I40E_AQ_CAP_ID_8021QBG: 3187 if (number == 1) 3188 p->evb_802_1_qbg = true; 3189 break; 3190 case I40E_AQ_CAP_ID_8021QBR: 3191 if (number == 1) 3192 p->evb_802_1_qbh = true; 3193 break; 3194 case I40E_AQ_CAP_ID_VSI: 3195 p->num_vsis = number; 3196 break; 3197 case I40E_AQ_CAP_ID_DCB: 3198 if (number == 1) { 3199 p->dcb = true; 3200 p->enabled_tcmap = logical_id; 3201 p->maxtc = phys_id; 3202 } 3203 break; 3204 case I40E_AQ_CAP_ID_FCOE: 3205 if (number == 1) 3206 p->fcoe = true; 3207 break; 3208 case I40E_AQ_CAP_ID_ISCSI: 3209 if (number == 1) 3210 p->iscsi = true; 3211 break; 3212 case I40E_AQ_CAP_ID_RSS: 3213 p->rss = true; 3214 p->rss_table_size = number; 3215 p->rss_table_entry_width = logical_id; 3216 break; 3217 case I40E_AQ_CAP_ID_RXQ: 3218 p->num_rx_qp = number; 3219 p->base_queue = phys_id; 3220 break; 3221 case I40E_AQ_CAP_ID_TXQ: 3222 p->num_tx_qp = number; 3223 p->base_queue = phys_id; 3224 break; 3225 case I40E_AQ_CAP_ID_MSIX: 3226 p->num_msix_vectors = number; 3227 i40e_debug(hw, I40E_DEBUG_INIT, 3228 "HW Capability: MSIX vector count = %d\n", 3229 p->num_msix_vectors); 3230 break; 3231 case I40E_AQ_CAP_ID_VF_MSIX: 3232 p->num_msix_vectors_vf = number; 3233 break; 3234 case I40E_AQ_CAP_ID_FLEX10: 3235 if (major_rev == 1) { 3236 if (number == 1) { 3237 p->flex10_enable = true; 3238 p->flex10_capable = true; 3239 } 3240 } else { 3241 /* Capability revision >= 2 */ 3242 if (number & 1) 3243 p->flex10_enable = true; 3244 if (number & 2) 3245 p->flex10_capable = true; 3246 } 3247 p->flex10_mode = logical_id; 3248 p->flex10_status = phys_id; 3249 break; 3250 case I40E_AQ_CAP_ID_CEM: 3251 if (number == 1) 3252 p->mgmt_cem = true; 3253 break; 3254 case I40E_AQ_CAP_ID_IWARP: 3255 if (number == 1) 3256 p->iwarp = true; 3257 break; 3258 case I40E_AQ_CAP_ID_LED: 3259 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3260 p->led[phys_id] = true; 3261 break; 3262 case I40E_AQ_CAP_ID_SDP: 3263 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3264 p->sdp[phys_id] = true; 3265 break; 3266 case I40E_AQ_CAP_ID_MDIO: 3267 if (number == 1) { 3268 p->mdio_port_num = phys_id; 3269 p->mdio_port_mode = logical_id; 3270 } 3271 break; 3272 case I40E_AQ_CAP_ID_1588: 3273 if (number == 1) 3274 p->ieee_1588 = true; 3275 break; 3276 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3277 p->fd = true; 3278 p->fd_filters_guaranteed = number; 3279 p->fd_filters_best_effort = logical_id; 3280 break; 3281 case I40E_AQ_CAP_ID_WSR_PROT: 3282 p->wr_csr_prot = (u64)number; 3283 p->wr_csr_prot |= (u64)logical_id << 32; 3284 break; 3285 case I40E_AQ_CAP_ID_NVM_MGMT: 3286 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3287 p->sec_rev_disabled = true; 3288 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3289 p->update_disabled = true; 3290 break; 3291 default: 3292 break; 3293 } 3294 } 3295 3296 if (p->fcoe) 3297 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3298 3299 /* Software override ensuring FCoE is disabled if npar or mfp 3300 * mode because it is not supported in these modes. 3301 */ 3302 if (p->npar_enable || p->flex10_enable) 3303 p->fcoe = false; 3304 3305 /* count the enabled ports (aka the "not disabled" ports) */ 3306 hw->num_ports = 0; 3307 for (i = 0; i < 4; i++) { 3308 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3309 u64 port_cfg = 0; 3310 3311 /* use AQ read to get the physical register offset instead 3312 * of the port relative offset 3313 */ 3314 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3315 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3316 hw->num_ports++; 3317 } 3318 3319 /* OCP cards case: if a mezz is removed the Ethernet port is at 3320 * disabled state in PRTGEN_CNF register. Additional NVM read is 3321 * needed in order to check if we are dealing with OCP card. 3322 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3323 * physical ports results in wrong partition id calculation and thus 3324 * not supporting WoL. 3325 */ 3326 if (hw->mac.type == I40E_MAC_X722) { 3327 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 3328 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3329 2 * I40E_SR_OCP_CFG_WORD0, 3330 sizeof(ocp_cfg_word0), 3331 &ocp_cfg_word0, true, NULL); 3332 if (!status && 3333 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3334 hw->num_ports = 4; 3335 i40e_release_nvm(hw); 3336 } 3337 } 3338 3339 valid_functions = p->valid_functions; 3340 num_functions = 0; 3341 while (valid_functions) { 3342 if (valid_functions & 1) 3343 num_functions++; 3344 valid_functions >>= 1; 3345 } 3346 3347 /* partition id is 1-based, and functions are evenly spread 3348 * across the ports as partitions 3349 */ 3350 if (hw->num_ports != 0) { 3351 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3352 hw->num_partitions = num_functions / hw->num_ports; 3353 } 3354 3355 /* additional HW specific goodies that might 3356 * someday be HW version specific 3357 */ 3358 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3359 } 3360 3361 /** 3362 * i40e_aq_discover_capabilities 3363 * @hw: pointer to the hw struct 3364 * @buff: a virtual buffer to hold the capabilities 3365 * @buff_size: Size of the virtual buffer 3366 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3367 * @list_type_opc: capabilities type to discover - pass in the command opcode 3368 * @cmd_details: pointer to command details structure or NULL 3369 * 3370 * Get the device capabilities descriptions from the firmware 3371 **/ 3372 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3373 void *buff, u16 buff_size, u16 *data_size, 3374 enum i40e_admin_queue_opc list_type_opc, 3375 struct i40e_asq_cmd_details *cmd_details) 3376 { 3377 struct i40e_aqc_list_capabilites *cmd; 3378 struct i40e_aq_desc desc; 3379 i40e_status status = 0; 3380 3381 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3382 3383 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3384 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3385 status = I40E_ERR_PARAM; 3386 goto exit; 3387 } 3388 3389 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3390 3391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3392 if (buff_size > I40E_AQ_LARGE_BUF) 3393 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3394 3395 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3396 *data_size = le16_to_cpu(desc.datalen); 3397 3398 if (status) 3399 goto exit; 3400 3401 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3402 list_type_opc); 3403 3404 exit: 3405 return status; 3406 } 3407 3408 /** 3409 * i40e_aq_update_nvm 3410 * @hw: pointer to the hw struct 3411 * @module_pointer: module pointer location in words from the NVM beginning 3412 * @offset: byte offset from the module beginning 3413 * @length: length of the section to be written (in bytes from the offset) 3414 * @data: command buffer (size [bytes] = length) 3415 * @last_command: tells if this is the last command in a series 3416 * @preservation_flags: Preservation mode flags 3417 * @cmd_details: pointer to command details structure or NULL 3418 * 3419 * Update the NVM using the admin queue commands 3420 **/ 3421 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3422 u32 offset, u16 length, void *data, 3423 bool last_command, u8 preservation_flags, 3424 struct i40e_asq_cmd_details *cmd_details) 3425 { 3426 struct i40e_aq_desc desc; 3427 struct i40e_aqc_nvm_update *cmd = 3428 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3429 i40e_status status; 3430 3431 /* In offset the highest byte must be zeroed. */ 3432 if (offset & 0xFF000000) { 3433 status = I40E_ERR_PARAM; 3434 goto i40e_aq_update_nvm_exit; 3435 } 3436 3437 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3438 3439 /* If this is the last command in a series, set the proper flag. */ 3440 if (last_command) 3441 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3442 if (hw->mac.type == I40E_MAC_X722) { 3443 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 3444 cmd->command_flags |= 3445 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3446 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3447 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3448 cmd->command_flags |= 3449 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3450 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3451 } 3452 cmd->module_pointer = module_pointer; 3453 cmd->offset = cpu_to_le32(offset); 3454 cmd->length = cpu_to_le16(length); 3455 3456 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3457 if (length > I40E_AQ_LARGE_BUF) 3458 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3459 3460 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3461 3462 i40e_aq_update_nvm_exit: 3463 return status; 3464 } 3465 3466 /** 3467 * i40e_aq_rearrange_nvm 3468 * @hw: pointer to the hw struct 3469 * @rearrange_nvm: defines direction of rearrangement 3470 * @cmd_details: pointer to command details structure or NULL 3471 * 3472 * Rearrange NVM structure, available only for transition FW 3473 **/ 3474 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw, 3475 u8 rearrange_nvm, 3476 struct i40e_asq_cmd_details *cmd_details) 3477 { 3478 struct i40e_aqc_nvm_update *cmd; 3479 i40e_status status; 3480 struct i40e_aq_desc desc; 3481 3482 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 3483 3484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3485 3486 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 3487 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 3488 3489 if (!rearrange_nvm) { 3490 status = I40E_ERR_PARAM; 3491 goto i40e_aq_rearrange_nvm_exit; 3492 } 3493 3494 cmd->command_flags |= rearrange_nvm; 3495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3496 3497 i40e_aq_rearrange_nvm_exit: 3498 return status; 3499 } 3500 3501 /** 3502 * i40e_aq_get_lldp_mib 3503 * @hw: pointer to the hw struct 3504 * @bridge_type: type of bridge requested 3505 * @mib_type: Local, Remote or both Local and Remote MIBs 3506 * @buff: pointer to a user supplied buffer to store the MIB block 3507 * @buff_size: size of the buffer (in bytes) 3508 * @local_len : length of the returned Local LLDP MIB 3509 * @remote_len: length of the returned Remote LLDP MIB 3510 * @cmd_details: pointer to command details structure or NULL 3511 * 3512 * Requests the complete LLDP MIB (entire packet). 3513 **/ 3514 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3515 u8 mib_type, void *buff, u16 buff_size, 3516 u16 *local_len, u16 *remote_len, 3517 struct i40e_asq_cmd_details *cmd_details) 3518 { 3519 struct i40e_aq_desc desc; 3520 struct i40e_aqc_lldp_get_mib *cmd = 3521 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3522 struct i40e_aqc_lldp_get_mib *resp = 3523 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3524 i40e_status status; 3525 3526 if (buff_size == 0 || !buff) 3527 return I40E_ERR_PARAM; 3528 3529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3530 /* Indirect Command */ 3531 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3532 3533 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3534 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3535 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3536 3537 desc.datalen = cpu_to_le16(buff_size); 3538 3539 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3540 if (buff_size > I40E_AQ_LARGE_BUF) 3541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3542 3543 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3544 if (!status) { 3545 if (local_len != NULL) 3546 *local_len = le16_to_cpu(resp->local_len); 3547 if (remote_len != NULL) 3548 *remote_len = le16_to_cpu(resp->remote_len); 3549 } 3550 3551 return status; 3552 } 3553 3554 /** 3555 * i40e_aq_set_lldp_mib - Set the LLDP MIB 3556 * @hw: pointer to the hw struct 3557 * @mib_type: Local, Remote or both Local and Remote MIBs 3558 * @buff: pointer to a user supplied buffer to store the MIB block 3559 * @buff_size: size of the buffer (in bytes) 3560 * @cmd_details: pointer to command details structure or NULL 3561 * 3562 * Set the LLDP MIB. 3563 **/ 3564 enum i40e_status_code 3565 i40e_aq_set_lldp_mib(struct i40e_hw *hw, 3566 u8 mib_type, void *buff, u16 buff_size, 3567 struct i40e_asq_cmd_details *cmd_details) 3568 { 3569 struct i40e_aqc_lldp_set_local_mib *cmd; 3570 enum i40e_status_code status; 3571 struct i40e_aq_desc desc; 3572 3573 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 3574 if (buff_size == 0 || !buff) 3575 return I40E_ERR_PARAM; 3576 3577 i40e_fill_default_direct_cmd_desc(&desc, 3578 i40e_aqc_opc_lldp_set_local_mib); 3579 /* Indirect Command */ 3580 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3581 if (buff_size > I40E_AQ_LARGE_BUF) 3582 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3583 desc.datalen = cpu_to_le16(buff_size); 3584 3585 cmd->type = mib_type; 3586 cmd->length = cpu_to_le16(buff_size); 3587 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); 3588 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); 3589 3590 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3591 return status; 3592 } 3593 3594 /** 3595 * i40e_aq_cfg_lldp_mib_change_event 3596 * @hw: pointer to the hw struct 3597 * @enable_update: Enable or Disable event posting 3598 * @cmd_details: pointer to command details structure or NULL 3599 * 3600 * Enable or Disable posting of an event on ARQ when LLDP MIB 3601 * associated with the interface changes 3602 **/ 3603 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3604 bool enable_update, 3605 struct i40e_asq_cmd_details *cmd_details) 3606 { 3607 struct i40e_aq_desc desc; 3608 struct i40e_aqc_lldp_update_mib *cmd = 3609 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3610 i40e_status status; 3611 3612 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3613 3614 if (!enable_update) 3615 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3616 3617 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3618 3619 return status; 3620 } 3621 3622 /** 3623 * i40e_aq_restore_lldp 3624 * @hw: pointer to the hw struct 3625 * @setting: pointer to factory setting variable or NULL 3626 * @restore: True if factory settings should be restored 3627 * @cmd_details: pointer to command details structure or NULL 3628 * 3629 * Restore LLDP Agent factory settings if @restore set to True. In other case 3630 * only returns factory setting in AQ response. 3631 **/ 3632 enum i40e_status_code 3633 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 3634 struct i40e_asq_cmd_details *cmd_details) 3635 { 3636 struct i40e_aq_desc desc; 3637 struct i40e_aqc_lldp_restore *cmd = 3638 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 3639 i40e_status status; 3640 3641 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) { 3642 i40e_debug(hw, I40E_DEBUG_ALL, 3643 "Restore LLDP not supported by current FW version.\n"); 3644 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3645 } 3646 3647 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 3648 3649 if (restore) 3650 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 3651 3652 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3653 3654 if (setting) 3655 *setting = cmd->command & 1; 3656 3657 return status; 3658 } 3659 3660 /** 3661 * i40e_aq_stop_lldp 3662 * @hw: pointer to the hw struct 3663 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3664 * @persist: True if stop of LLDP should be persistent across power cycles 3665 * @cmd_details: pointer to command details structure or NULL 3666 * 3667 * Stop or Shutdown the embedded LLDP Agent 3668 **/ 3669 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3670 bool persist, 3671 struct i40e_asq_cmd_details *cmd_details) 3672 { 3673 struct i40e_aq_desc desc; 3674 struct i40e_aqc_lldp_stop *cmd = 3675 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3676 i40e_status status; 3677 3678 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3679 3680 if (shutdown_agent) 3681 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3682 3683 if (persist) { 3684 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3685 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3686 else 3687 i40e_debug(hw, I40E_DEBUG_ALL, 3688 "Persistent Stop LLDP not supported by current FW version.\n"); 3689 } 3690 3691 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3692 3693 return status; 3694 } 3695 3696 /** 3697 * i40e_aq_start_lldp 3698 * @hw: pointer to the hw struct 3699 * @persist: True if start of LLDP should be persistent across power cycles 3700 * @cmd_details: pointer to command details structure or NULL 3701 * 3702 * Start the embedded LLDP Agent on all ports. 3703 **/ 3704 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3705 struct i40e_asq_cmd_details *cmd_details) 3706 { 3707 struct i40e_aq_desc desc; 3708 struct i40e_aqc_lldp_start *cmd = 3709 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3710 i40e_status status; 3711 3712 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3713 3714 cmd->command = I40E_AQ_LLDP_AGENT_START; 3715 3716 if (persist) { 3717 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3718 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3719 else 3720 i40e_debug(hw, I40E_DEBUG_ALL, 3721 "Persistent Start LLDP not supported by current FW version.\n"); 3722 } 3723 3724 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3725 3726 return status; 3727 } 3728 3729 /** 3730 * i40e_aq_set_dcb_parameters 3731 * @hw: pointer to the hw struct 3732 * @cmd_details: pointer to command details structure or NULL 3733 * @dcb_enable: True if DCB configuration needs to be applied 3734 * 3735 **/ 3736 enum i40e_status_code 3737 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3738 struct i40e_asq_cmd_details *cmd_details) 3739 { 3740 struct i40e_aq_desc desc; 3741 struct i40e_aqc_set_dcb_parameters *cmd = 3742 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3743 i40e_status status; 3744 3745 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 3746 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3747 3748 i40e_fill_default_direct_cmd_desc(&desc, 3749 i40e_aqc_opc_set_dcb_parameters); 3750 3751 if (dcb_enable) { 3752 cmd->valid_flags = I40E_DCB_VALID; 3753 cmd->command = I40E_AQ_DCB_SET_AGENT; 3754 } 3755 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3756 3757 return status; 3758 } 3759 3760 /** 3761 * i40e_aq_get_cee_dcb_config 3762 * @hw: pointer to the hw struct 3763 * @buff: response buffer that stores CEE operational configuration 3764 * @buff_size: size of the buffer passed 3765 * @cmd_details: pointer to command details structure or NULL 3766 * 3767 * Get CEE DCBX mode operational configuration from firmware 3768 **/ 3769 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3770 void *buff, u16 buff_size, 3771 struct i40e_asq_cmd_details *cmd_details) 3772 { 3773 struct i40e_aq_desc desc; 3774 i40e_status status; 3775 3776 if (buff_size == 0 || !buff) 3777 return I40E_ERR_PARAM; 3778 3779 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3780 3781 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3782 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3783 cmd_details); 3784 3785 return status; 3786 } 3787 3788 /** 3789 * i40e_aq_add_udp_tunnel 3790 * @hw: pointer to the hw struct 3791 * @udp_port: the UDP port to add in Host byte order 3792 * @protocol_index: protocol index type 3793 * @filter_index: pointer to filter index 3794 * @cmd_details: pointer to command details structure or NULL 3795 * 3796 * Note: Firmware expects the udp_port value to be in Little Endian format, 3797 * and this function will call cpu_to_le16 to convert from Host byte order to 3798 * Little Endian order. 3799 **/ 3800 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3801 u16 udp_port, u8 protocol_index, 3802 u8 *filter_index, 3803 struct i40e_asq_cmd_details *cmd_details) 3804 { 3805 struct i40e_aq_desc desc; 3806 struct i40e_aqc_add_udp_tunnel *cmd = 3807 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3808 struct i40e_aqc_del_udp_tunnel_completion *resp = 3809 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3810 i40e_status status; 3811 3812 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3813 3814 cmd->udp_port = cpu_to_le16(udp_port); 3815 cmd->protocol_type = protocol_index; 3816 3817 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3818 3819 if (!status && filter_index) 3820 *filter_index = resp->index; 3821 3822 return status; 3823 } 3824 3825 /** 3826 * i40e_aq_del_udp_tunnel 3827 * @hw: pointer to the hw struct 3828 * @index: filter index 3829 * @cmd_details: pointer to command details structure or NULL 3830 **/ 3831 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3832 struct i40e_asq_cmd_details *cmd_details) 3833 { 3834 struct i40e_aq_desc desc; 3835 struct i40e_aqc_remove_udp_tunnel *cmd = 3836 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3837 i40e_status status; 3838 3839 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3840 3841 cmd->index = index; 3842 3843 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3844 3845 return status; 3846 } 3847 3848 /** 3849 * i40e_aq_delete_element - Delete switch element 3850 * @hw: pointer to the hw struct 3851 * @seid: the SEID to delete from the switch 3852 * @cmd_details: pointer to command details structure or NULL 3853 * 3854 * This deletes a switch element from the switch. 3855 **/ 3856 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3857 struct i40e_asq_cmd_details *cmd_details) 3858 { 3859 struct i40e_aq_desc desc; 3860 struct i40e_aqc_switch_seid *cmd = 3861 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3862 i40e_status status; 3863 3864 if (seid == 0) 3865 return I40E_ERR_PARAM; 3866 3867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3868 3869 cmd->seid = cpu_to_le16(seid); 3870 3871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3872 3873 return status; 3874 } 3875 3876 /** 3877 * i40e_aq_dcb_updated - DCB Updated Command 3878 * @hw: pointer to the hw struct 3879 * @cmd_details: pointer to command details structure or NULL 3880 * 3881 * EMP will return when the shared RPB settings have been 3882 * recomputed and modified. The retval field in the descriptor 3883 * will be set to 0 when RPB is modified. 3884 **/ 3885 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3886 struct i40e_asq_cmd_details *cmd_details) 3887 { 3888 struct i40e_aq_desc desc; 3889 i40e_status status; 3890 3891 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3892 3893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3894 3895 return status; 3896 } 3897 3898 /** 3899 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3900 * @hw: pointer to the hw struct 3901 * @seid: seid for the physical port/switching component/vsi 3902 * @buff: Indirect buffer to hold data parameters and response 3903 * @buff_size: Indirect buffer size 3904 * @opcode: Tx scheduler AQ command opcode 3905 * @cmd_details: pointer to command details structure or NULL 3906 * 3907 * Generic command handler for Tx scheduler AQ commands 3908 **/ 3909 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3910 void *buff, u16 buff_size, 3911 enum i40e_admin_queue_opc opcode, 3912 struct i40e_asq_cmd_details *cmd_details) 3913 { 3914 struct i40e_aq_desc desc; 3915 struct i40e_aqc_tx_sched_ind *cmd = 3916 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3917 i40e_status status; 3918 bool cmd_param_flag = false; 3919 3920 switch (opcode) { 3921 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3922 case i40e_aqc_opc_configure_vsi_tc_bw: 3923 case i40e_aqc_opc_enable_switching_comp_ets: 3924 case i40e_aqc_opc_modify_switching_comp_ets: 3925 case i40e_aqc_opc_disable_switching_comp_ets: 3926 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3927 case i40e_aqc_opc_configure_switching_comp_bw_config: 3928 cmd_param_flag = true; 3929 break; 3930 case i40e_aqc_opc_query_vsi_bw_config: 3931 case i40e_aqc_opc_query_vsi_ets_sla_config: 3932 case i40e_aqc_opc_query_switching_comp_ets_config: 3933 case i40e_aqc_opc_query_port_ets_config: 3934 case i40e_aqc_opc_query_switching_comp_bw_config: 3935 cmd_param_flag = false; 3936 break; 3937 default: 3938 return I40E_ERR_PARAM; 3939 } 3940 3941 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3942 3943 /* Indirect command */ 3944 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3945 if (cmd_param_flag) 3946 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3947 if (buff_size > I40E_AQ_LARGE_BUF) 3948 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3949 3950 desc.datalen = cpu_to_le16(buff_size); 3951 3952 cmd->vsi_seid = cpu_to_le16(seid); 3953 3954 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3955 3956 return status; 3957 } 3958 3959 /** 3960 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3961 * @hw: pointer to the hw struct 3962 * @seid: VSI seid 3963 * @credit: BW limit credits (0 = disabled) 3964 * @max_credit: Max BW limit credits 3965 * @cmd_details: pointer to command details structure or NULL 3966 **/ 3967 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3968 u16 seid, u16 credit, u8 max_credit, 3969 struct i40e_asq_cmd_details *cmd_details) 3970 { 3971 struct i40e_aq_desc desc; 3972 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3973 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3974 i40e_status status; 3975 3976 i40e_fill_default_direct_cmd_desc(&desc, 3977 i40e_aqc_opc_configure_vsi_bw_limit); 3978 3979 cmd->vsi_seid = cpu_to_le16(seid); 3980 cmd->credit = cpu_to_le16(credit); 3981 cmd->max_credit = max_credit; 3982 3983 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3984 3985 return status; 3986 } 3987 3988 /** 3989 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3990 * @hw: pointer to the hw struct 3991 * @seid: VSI seid 3992 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3993 * @cmd_details: pointer to command details structure or NULL 3994 **/ 3995 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3996 u16 seid, 3997 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3998 struct i40e_asq_cmd_details *cmd_details) 3999 { 4000 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4001 i40e_aqc_opc_configure_vsi_tc_bw, 4002 cmd_details); 4003 } 4004 4005 /** 4006 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 4007 * @hw: pointer to the hw struct 4008 * @seid: seid of the switching component connected to Physical Port 4009 * @ets_data: Buffer holding ETS parameters 4010 * @opcode: Tx scheduler AQ command opcode 4011 * @cmd_details: pointer to command details structure or NULL 4012 **/ 4013 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 4014 u16 seid, 4015 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 4016 enum i40e_admin_queue_opc opcode, 4017 struct i40e_asq_cmd_details *cmd_details) 4018 { 4019 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 4020 sizeof(*ets_data), opcode, cmd_details); 4021 } 4022 4023 /** 4024 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 4025 * @hw: pointer to the hw struct 4026 * @seid: seid of the switching component 4027 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 4028 * @cmd_details: pointer to command details structure or NULL 4029 **/ 4030 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 4031 u16 seid, 4032 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 4033 struct i40e_asq_cmd_details *cmd_details) 4034 { 4035 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4036 i40e_aqc_opc_configure_switching_comp_bw_config, 4037 cmd_details); 4038 } 4039 4040 /** 4041 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4042 * @hw: pointer to the hw struct 4043 * @seid: seid of the VSI 4044 * @bw_data: Buffer to hold VSI BW configuration 4045 * @cmd_details: pointer to command details structure or NULL 4046 **/ 4047 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4048 u16 seid, 4049 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4050 struct i40e_asq_cmd_details *cmd_details) 4051 { 4052 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4053 i40e_aqc_opc_query_vsi_bw_config, 4054 cmd_details); 4055 } 4056 4057 /** 4058 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4059 * @hw: pointer to the hw struct 4060 * @seid: seid of the VSI 4061 * @bw_data: Buffer to hold VSI BW configuration per TC 4062 * @cmd_details: pointer to command details structure or NULL 4063 **/ 4064 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4065 u16 seid, 4066 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4067 struct i40e_asq_cmd_details *cmd_details) 4068 { 4069 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4070 i40e_aqc_opc_query_vsi_ets_sla_config, 4071 cmd_details); 4072 } 4073 4074 /** 4075 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4076 * @hw: pointer to the hw struct 4077 * @seid: seid of the switching component 4078 * @bw_data: Buffer to hold switching component's per TC BW config 4079 * @cmd_details: pointer to command details structure or NULL 4080 **/ 4081 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4082 u16 seid, 4083 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4084 struct i40e_asq_cmd_details *cmd_details) 4085 { 4086 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4087 i40e_aqc_opc_query_switching_comp_ets_config, 4088 cmd_details); 4089 } 4090 4091 /** 4092 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4093 * @hw: pointer to the hw struct 4094 * @seid: seid of the VSI or switching component connected to Physical Port 4095 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4096 * @cmd_details: pointer to command details structure or NULL 4097 **/ 4098 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4099 u16 seid, 4100 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4101 struct i40e_asq_cmd_details *cmd_details) 4102 { 4103 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4104 i40e_aqc_opc_query_port_ets_config, 4105 cmd_details); 4106 } 4107 4108 /** 4109 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4110 * @hw: pointer to the hw struct 4111 * @seid: seid of the switching component 4112 * @bw_data: Buffer to hold switching component's BW configuration 4113 * @cmd_details: pointer to command details structure or NULL 4114 **/ 4115 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4116 u16 seid, 4117 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4118 struct i40e_asq_cmd_details *cmd_details) 4119 { 4120 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4121 i40e_aqc_opc_query_switching_comp_bw_config, 4122 cmd_details); 4123 } 4124 4125 /** 4126 * i40e_validate_filter_settings 4127 * @hw: pointer to the hardware structure 4128 * @settings: Filter control settings 4129 * 4130 * Check and validate the filter control settings passed. 4131 * The function checks for the valid filter/context sizes being 4132 * passed for FCoE and PE. 4133 * 4134 * Returns 0 if the values passed are valid and within 4135 * range else returns an error. 4136 **/ 4137 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4138 struct i40e_filter_control_settings *settings) 4139 { 4140 u32 fcoe_cntx_size, fcoe_filt_size; 4141 u32 fcoe_fmax; 4142 u32 val; 4143 4144 /* Validate FCoE settings passed */ 4145 switch (settings->fcoe_filt_num) { 4146 case I40E_HASH_FILTER_SIZE_1K: 4147 case I40E_HASH_FILTER_SIZE_2K: 4148 case I40E_HASH_FILTER_SIZE_4K: 4149 case I40E_HASH_FILTER_SIZE_8K: 4150 case I40E_HASH_FILTER_SIZE_16K: 4151 case I40E_HASH_FILTER_SIZE_32K: 4152 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4153 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4154 break; 4155 default: 4156 return I40E_ERR_PARAM; 4157 } 4158 4159 switch (settings->fcoe_cntx_num) { 4160 case I40E_DMA_CNTX_SIZE_512: 4161 case I40E_DMA_CNTX_SIZE_1K: 4162 case I40E_DMA_CNTX_SIZE_2K: 4163 case I40E_DMA_CNTX_SIZE_4K: 4164 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4165 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4166 break; 4167 default: 4168 return I40E_ERR_PARAM; 4169 } 4170 4171 /* Validate PE settings passed */ 4172 switch (settings->pe_filt_num) { 4173 case I40E_HASH_FILTER_SIZE_1K: 4174 case I40E_HASH_FILTER_SIZE_2K: 4175 case I40E_HASH_FILTER_SIZE_4K: 4176 case I40E_HASH_FILTER_SIZE_8K: 4177 case I40E_HASH_FILTER_SIZE_16K: 4178 case I40E_HASH_FILTER_SIZE_32K: 4179 case I40E_HASH_FILTER_SIZE_64K: 4180 case I40E_HASH_FILTER_SIZE_128K: 4181 case I40E_HASH_FILTER_SIZE_256K: 4182 case I40E_HASH_FILTER_SIZE_512K: 4183 case I40E_HASH_FILTER_SIZE_1M: 4184 break; 4185 default: 4186 return I40E_ERR_PARAM; 4187 } 4188 4189 switch (settings->pe_cntx_num) { 4190 case I40E_DMA_CNTX_SIZE_512: 4191 case I40E_DMA_CNTX_SIZE_1K: 4192 case I40E_DMA_CNTX_SIZE_2K: 4193 case I40E_DMA_CNTX_SIZE_4K: 4194 case I40E_DMA_CNTX_SIZE_8K: 4195 case I40E_DMA_CNTX_SIZE_16K: 4196 case I40E_DMA_CNTX_SIZE_32K: 4197 case I40E_DMA_CNTX_SIZE_64K: 4198 case I40E_DMA_CNTX_SIZE_128K: 4199 case I40E_DMA_CNTX_SIZE_256K: 4200 break; 4201 default: 4202 return I40E_ERR_PARAM; 4203 } 4204 4205 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4206 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4207 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4208 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4209 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4210 return I40E_ERR_INVALID_SIZE; 4211 4212 return 0; 4213 } 4214 4215 /** 4216 * i40e_set_filter_control 4217 * @hw: pointer to the hardware structure 4218 * @settings: Filter control settings 4219 * 4220 * Set the Queue Filters for PE/FCoE and enable filters required 4221 * for a single PF. It is expected that these settings are programmed 4222 * at the driver initialization time. 4223 **/ 4224 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4225 struct i40e_filter_control_settings *settings) 4226 { 4227 i40e_status ret = 0; 4228 u32 hash_lut_size = 0; 4229 u32 val; 4230 4231 if (!settings) 4232 return I40E_ERR_PARAM; 4233 4234 /* Validate the input settings */ 4235 ret = i40e_validate_filter_settings(hw, settings); 4236 if (ret) 4237 return ret; 4238 4239 /* Read the PF Queue Filter control register */ 4240 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4241 4242 /* Program required PE hash buckets for the PF */ 4243 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4244 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4245 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4246 /* Program required PE contexts for the PF */ 4247 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4248 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4249 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4250 4251 /* Program required FCoE hash buckets for the PF */ 4252 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4253 val |= ((u32)settings->fcoe_filt_num << 4254 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4255 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4256 /* Program required FCoE DDP contexts for the PF */ 4257 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4258 val |= ((u32)settings->fcoe_cntx_num << 4259 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4260 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4261 4262 /* Program Hash LUT size for the PF */ 4263 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4264 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4265 hash_lut_size = 1; 4266 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4267 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4268 4269 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4270 if (settings->enable_fdir) 4271 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4272 if (settings->enable_ethtype) 4273 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4274 if (settings->enable_macvlan) 4275 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4276 4277 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4278 4279 return 0; 4280 } 4281 4282 /** 4283 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4284 * @hw: pointer to the hw struct 4285 * @mac_addr: MAC address to use in the filter 4286 * @ethtype: Ethertype to use in the filter 4287 * @flags: Flags that needs to be applied to the filter 4288 * @vsi_seid: seid of the control VSI 4289 * @queue: VSI queue number to send the packet to 4290 * @is_add: Add control packet filter if True else remove 4291 * @stats: Structure to hold information on control filter counts 4292 * @cmd_details: pointer to command details structure or NULL 4293 * 4294 * This command will Add or Remove control packet filter for a control VSI. 4295 * In return it will update the total number of perfect filter count in 4296 * the stats member. 4297 **/ 4298 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4299 u8 *mac_addr, u16 ethtype, u16 flags, 4300 u16 vsi_seid, u16 queue, bool is_add, 4301 struct i40e_control_filter_stats *stats, 4302 struct i40e_asq_cmd_details *cmd_details) 4303 { 4304 struct i40e_aq_desc desc; 4305 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4306 (struct i40e_aqc_add_remove_control_packet_filter *) 4307 &desc.params.raw; 4308 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4309 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4310 &desc.params.raw; 4311 i40e_status status; 4312 4313 if (vsi_seid == 0) 4314 return I40E_ERR_PARAM; 4315 4316 if (is_add) { 4317 i40e_fill_default_direct_cmd_desc(&desc, 4318 i40e_aqc_opc_add_control_packet_filter); 4319 cmd->queue = cpu_to_le16(queue); 4320 } else { 4321 i40e_fill_default_direct_cmd_desc(&desc, 4322 i40e_aqc_opc_remove_control_packet_filter); 4323 } 4324 4325 if (mac_addr) 4326 ether_addr_copy(cmd->mac, mac_addr); 4327 4328 cmd->etype = cpu_to_le16(ethtype); 4329 cmd->flags = cpu_to_le16(flags); 4330 cmd->seid = cpu_to_le16(vsi_seid); 4331 4332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4333 4334 if (!status && stats) { 4335 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4336 stats->etype_used = le16_to_cpu(resp->etype_used); 4337 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4338 stats->etype_free = le16_to_cpu(resp->etype_free); 4339 } 4340 4341 return status; 4342 } 4343 4344 /** 4345 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4346 * @hw: pointer to the hw struct 4347 * @seid: VSI seid to add ethertype filter from 4348 **/ 4349 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4350 u16 seid) 4351 { 4352 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4353 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4354 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4355 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4356 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4357 i40e_status status; 4358 4359 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4360 seid, 0, true, NULL, 4361 NULL); 4362 if (status) 4363 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4364 } 4365 4366 /** 4367 * i40e_aq_alternate_read 4368 * @hw: pointer to the hardware structure 4369 * @reg_addr0: address of first dword to be read 4370 * @reg_val0: pointer for data read from 'reg_addr0' 4371 * @reg_addr1: address of second dword to be read 4372 * @reg_val1: pointer for data read from 'reg_addr1' 4373 * 4374 * Read one or two dwords from alternate structure. Fields are indicated 4375 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4376 * is not passed then only register at 'reg_addr0' is read. 4377 * 4378 **/ 4379 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4380 u32 reg_addr0, u32 *reg_val0, 4381 u32 reg_addr1, u32 *reg_val1) 4382 { 4383 struct i40e_aq_desc desc; 4384 struct i40e_aqc_alternate_write *cmd_resp = 4385 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4386 i40e_status status; 4387 4388 if (!reg_val0) 4389 return I40E_ERR_PARAM; 4390 4391 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4392 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4393 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4394 4395 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4396 4397 if (!status) { 4398 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4399 4400 if (reg_val1) 4401 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4402 } 4403 4404 return status; 4405 } 4406 4407 /** 4408 * i40e_aq_suspend_port_tx 4409 * @hw: pointer to the hardware structure 4410 * @seid: port seid 4411 * @cmd_details: pointer to command details structure or NULL 4412 * 4413 * Suspend port's Tx traffic 4414 **/ 4415 i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, 4416 struct i40e_asq_cmd_details *cmd_details) 4417 { 4418 struct i40e_aqc_tx_sched_ind *cmd; 4419 struct i40e_aq_desc desc; 4420 i40e_status status; 4421 4422 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); 4424 cmd->vsi_seid = cpu_to_le16(seid); 4425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4426 4427 return status; 4428 } 4429 4430 /** 4431 * i40e_aq_resume_port_tx 4432 * @hw: pointer to the hardware structure 4433 * @cmd_details: pointer to command details structure or NULL 4434 * 4435 * Resume port's Tx traffic 4436 **/ 4437 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4438 struct i40e_asq_cmd_details *cmd_details) 4439 { 4440 struct i40e_aq_desc desc; 4441 i40e_status status; 4442 4443 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4444 4445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4446 4447 return status; 4448 } 4449 4450 /** 4451 * i40e_set_pci_config_data - store PCI bus info 4452 * @hw: pointer to hardware structure 4453 * @link_status: the link status word from PCI config space 4454 * 4455 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4456 **/ 4457 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4458 { 4459 hw->bus.type = i40e_bus_type_pci_express; 4460 4461 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4462 case PCI_EXP_LNKSTA_NLW_X1: 4463 hw->bus.width = i40e_bus_width_pcie_x1; 4464 break; 4465 case PCI_EXP_LNKSTA_NLW_X2: 4466 hw->bus.width = i40e_bus_width_pcie_x2; 4467 break; 4468 case PCI_EXP_LNKSTA_NLW_X4: 4469 hw->bus.width = i40e_bus_width_pcie_x4; 4470 break; 4471 case PCI_EXP_LNKSTA_NLW_X8: 4472 hw->bus.width = i40e_bus_width_pcie_x8; 4473 break; 4474 default: 4475 hw->bus.width = i40e_bus_width_unknown; 4476 break; 4477 } 4478 4479 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4480 case PCI_EXP_LNKSTA_CLS_2_5GB: 4481 hw->bus.speed = i40e_bus_speed_2500; 4482 break; 4483 case PCI_EXP_LNKSTA_CLS_5_0GB: 4484 hw->bus.speed = i40e_bus_speed_5000; 4485 break; 4486 case PCI_EXP_LNKSTA_CLS_8_0GB: 4487 hw->bus.speed = i40e_bus_speed_8000; 4488 break; 4489 default: 4490 hw->bus.speed = i40e_bus_speed_unknown; 4491 break; 4492 } 4493 } 4494 4495 /** 4496 * i40e_aq_debug_dump 4497 * @hw: pointer to the hardware structure 4498 * @cluster_id: specific cluster to dump 4499 * @table_id: table id within cluster 4500 * @start_index: index of line in the block to read 4501 * @buff_size: dump buffer size 4502 * @buff: dump buffer 4503 * @ret_buff_size: actual buffer size returned 4504 * @ret_next_table: next block to read 4505 * @ret_next_index: next index to read 4506 * @cmd_details: pointer to command details structure or NULL 4507 * 4508 * Dump internal FW/HW data for debug purposes. 4509 * 4510 **/ 4511 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4512 u8 table_id, u32 start_index, u16 buff_size, 4513 void *buff, u16 *ret_buff_size, 4514 u8 *ret_next_table, u32 *ret_next_index, 4515 struct i40e_asq_cmd_details *cmd_details) 4516 { 4517 struct i40e_aq_desc desc; 4518 struct i40e_aqc_debug_dump_internals *cmd = 4519 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4520 struct i40e_aqc_debug_dump_internals *resp = 4521 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4522 i40e_status status; 4523 4524 if (buff_size == 0 || !buff) 4525 return I40E_ERR_PARAM; 4526 4527 i40e_fill_default_direct_cmd_desc(&desc, 4528 i40e_aqc_opc_debug_dump_internals); 4529 /* Indirect Command */ 4530 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4531 if (buff_size > I40E_AQ_LARGE_BUF) 4532 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4533 4534 cmd->cluster_id = cluster_id; 4535 cmd->table_id = table_id; 4536 cmd->idx = cpu_to_le32(start_index); 4537 4538 desc.datalen = cpu_to_le16(buff_size); 4539 4540 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4541 if (!status) { 4542 if (ret_buff_size) 4543 *ret_buff_size = le16_to_cpu(desc.datalen); 4544 if (ret_next_table) 4545 *ret_next_table = resp->table_id; 4546 if (ret_next_index) 4547 *ret_next_index = le32_to_cpu(resp->idx); 4548 } 4549 4550 return status; 4551 } 4552 4553 /** 4554 * i40e_read_bw_from_alt_ram 4555 * @hw: pointer to the hardware structure 4556 * @max_bw: pointer for max_bw read 4557 * @min_bw: pointer for min_bw read 4558 * @min_valid: pointer for bool that is true if min_bw is a valid value 4559 * @max_valid: pointer for bool that is true if max_bw is a valid value 4560 * 4561 * Read bw from the alternate ram for the given pf 4562 **/ 4563 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4564 u32 *max_bw, u32 *min_bw, 4565 bool *min_valid, bool *max_valid) 4566 { 4567 i40e_status status; 4568 u32 max_bw_addr, min_bw_addr; 4569 4570 /* Calculate the address of the min/max bw registers */ 4571 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4572 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4573 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4574 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4575 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4576 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4577 4578 /* Read the bandwidths from alt ram */ 4579 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4580 min_bw_addr, min_bw); 4581 4582 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4583 *min_valid = true; 4584 else 4585 *min_valid = false; 4586 4587 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4588 *max_valid = true; 4589 else 4590 *max_valid = false; 4591 4592 return status; 4593 } 4594 4595 /** 4596 * i40e_aq_configure_partition_bw 4597 * @hw: pointer to the hardware structure 4598 * @bw_data: Buffer holding valid pfs and bw limits 4599 * @cmd_details: pointer to command details 4600 * 4601 * Configure partitions guaranteed/max bw 4602 **/ 4603 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4604 struct i40e_aqc_configure_partition_bw_data *bw_data, 4605 struct i40e_asq_cmd_details *cmd_details) 4606 { 4607 i40e_status status; 4608 struct i40e_aq_desc desc; 4609 u16 bwd_size = sizeof(*bw_data); 4610 4611 i40e_fill_default_direct_cmd_desc(&desc, 4612 i40e_aqc_opc_configure_partition_bw); 4613 4614 /* Indirect command */ 4615 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4617 4618 if (bwd_size > I40E_AQ_LARGE_BUF) 4619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4620 4621 desc.datalen = cpu_to_le16(bwd_size); 4622 4623 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4624 cmd_details); 4625 4626 return status; 4627 } 4628 4629 /** 4630 * i40e_read_phy_register_clause22 4631 * @hw: pointer to the HW structure 4632 * @reg: register address in the page 4633 * @phy_addr: PHY address on MDIO interface 4634 * @value: PHY register value 4635 * 4636 * Reads specified PHY register value 4637 **/ 4638 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4639 u16 reg, u8 phy_addr, u16 *value) 4640 { 4641 i40e_status status = I40E_ERR_TIMEOUT; 4642 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4643 u32 command = 0; 4644 u16 retry = 1000; 4645 4646 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4647 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4648 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4649 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4650 (I40E_GLGEN_MSCA_MDICMD_MASK); 4651 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4652 do { 4653 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4654 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4655 status = 0; 4656 break; 4657 } 4658 udelay(10); 4659 retry--; 4660 } while (retry); 4661 4662 if (status) { 4663 i40e_debug(hw, I40E_DEBUG_PHY, 4664 "PHY: Can't write command to external PHY.\n"); 4665 } else { 4666 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4667 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4668 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4669 } 4670 4671 return status; 4672 } 4673 4674 /** 4675 * i40e_write_phy_register_clause22 4676 * @hw: pointer to the HW structure 4677 * @reg: register address in the page 4678 * @phy_addr: PHY address on MDIO interface 4679 * @value: PHY register value 4680 * 4681 * Writes specified PHY register value 4682 **/ 4683 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4684 u16 reg, u8 phy_addr, u16 value) 4685 { 4686 i40e_status status = I40E_ERR_TIMEOUT; 4687 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4688 u32 command = 0; 4689 u16 retry = 1000; 4690 4691 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4692 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4693 4694 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4695 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4696 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4697 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4698 (I40E_GLGEN_MSCA_MDICMD_MASK); 4699 4700 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4701 do { 4702 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4703 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4704 status = 0; 4705 break; 4706 } 4707 udelay(10); 4708 retry--; 4709 } while (retry); 4710 4711 return status; 4712 } 4713 4714 /** 4715 * i40e_read_phy_register_clause45 4716 * @hw: pointer to the HW structure 4717 * @page: registers page number 4718 * @reg: register address in the page 4719 * @phy_addr: PHY address on MDIO interface 4720 * @value: PHY register value 4721 * 4722 * Reads specified PHY register value 4723 **/ 4724 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4725 u8 page, u16 reg, u8 phy_addr, u16 *value) 4726 { 4727 i40e_status status = I40E_ERR_TIMEOUT; 4728 u32 command = 0; 4729 u16 retry = 1000; 4730 u8 port_num = hw->func_caps.mdio_port_num; 4731 4732 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4733 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4734 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4735 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4736 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4737 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4738 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4739 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4740 do { 4741 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4742 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4743 status = 0; 4744 break; 4745 } 4746 usleep_range(10, 20); 4747 retry--; 4748 } while (retry); 4749 4750 if (status) { 4751 i40e_debug(hw, I40E_DEBUG_PHY, 4752 "PHY: Can't write command to external PHY.\n"); 4753 goto phy_read_end; 4754 } 4755 4756 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4757 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4758 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4759 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4760 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4761 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4762 status = I40E_ERR_TIMEOUT; 4763 retry = 1000; 4764 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4765 do { 4766 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4767 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4768 status = 0; 4769 break; 4770 } 4771 usleep_range(10, 20); 4772 retry--; 4773 } while (retry); 4774 4775 if (!status) { 4776 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4777 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4778 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4779 } else { 4780 i40e_debug(hw, I40E_DEBUG_PHY, 4781 "PHY: Can't read register value from external PHY.\n"); 4782 } 4783 4784 phy_read_end: 4785 return status; 4786 } 4787 4788 /** 4789 * i40e_write_phy_register_clause45 4790 * @hw: pointer to the HW structure 4791 * @page: registers page number 4792 * @reg: register address in the page 4793 * @phy_addr: PHY address on MDIO interface 4794 * @value: PHY register value 4795 * 4796 * Writes value to specified PHY register 4797 **/ 4798 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4799 u8 page, u16 reg, u8 phy_addr, u16 value) 4800 { 4801 i40e_status status = I40E_ERR_TIMEOUT; 4802 u32 command = 0; 4803 u16 retry = 1000; 4804 u8 port_num = hw->func_caps.mdio_port_num; 4805 4806 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4807 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4808 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4809 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4810 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4811 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4812 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4813 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4814 do { 4815 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4816 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4817 status = 0; 4818 break; 4819 } 4820 usleep_range(10, 20); 4821 retry--; 4822 } while (retry); 4823 if (status) { 4824 i40e_debug(hw, I40E_DEBUG_PHY, 4825 "PHY: Can't write command to external PHY.\n"); 4826 goto phy_write_end; 4827 } 4828 4829 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4830 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4831 4832 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4833 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4834 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4835 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4836 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4837 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4838 status = I40E_ERR_TIMEOUT; 4839 retry = 1000; 4840 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4841 do { 4842 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4843 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4844 status = 0; 4845 break; 4846 } 4847 usleep_range(10, 20); 4848 retry--; 4849 } while (retry); 4850 4851 phy_write_end: 4852 return status; 4853 } 4854 4855 /** 4856 * i40e_write_phy_register 4857 * @hw: pointer to the HW structure 4858 * @page: registers page number 4859 * @reg: register address in the page 4860 * @phy_addr: PHY address on MDIO interface 4861 * @value: PHY register value 4862 * 4863 * Writes value to specified PHY register 4864 **/ 4865 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4866 u8 page, u16 reg, u8 phy_addr, u16 value) 4867 { 4868 i40e_status status; 4869 4870 switch (hw->device_id) { 4871 case I40E_DEV_ID_1G_BASE_T_X722: 4872 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4873 value); 4874 break; 4875 case I40E_DEV_ID_5G_BASE_T_BC: 4876 case I40E_DEV_ID_10G_BASE_T: 4877 case I40E_DEV_ID_10G_BASE_T4: 4878 case I40E_DEV_ID_10G_BASE_T_BC: 4879 case I40E_DEV_ID_10G_BASE_T_X722: 4880 case I40E_DEV_ID_25G_B: 4881 case I40E_DEV_ID_25G_SFP28: 4882 status = i40e_write_phy_register_clause45(hw, page, reg, 4883 phy_addr, value); 4884 break; 4885 default: 4886 status = I40E_ERR_UNKNOWN_PHY; 4887 break; 4888 } 4889 4890 return status; 4891 } 4892 4893 /** 4894 * i40e_read_phy_register 4895 * @hw: pointer to the HW structure 4896 * @page: registers page number 4897 * @reg: register address in the page 4898 * @phy_addr: PHY address on MDIO interface 4899 * @value: PHY register value 4900 * 4901 * Reads specified PHY register value 4902 **/ 4903 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4904 u8 page, u16 reg, u8 phy_addr, u16 *value) 4905 { 4906 i40e_status status; 4907 4908 switch (hw->device_id) { 4909 case I40E_DEV_ID_1G_BASE_T_X722: 4910 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4911 value); 4912 break; 4913 case I40E_DEV_ID_5G_BASE_T_BC: 4914 case I40E_DEV_ID_10G_BASE_T: 4915 case I40E_DEV_ID_10G_BASE_T4: 4916 case I40E_DEV_ID_10G_BASE_T_BC: 4917 case I40E_DEV_ID_10G_BASE_T_X722: 4918 case I40E_DEV_ID_25G_B: 4919 case I40E_DEV_ID_25G_SFP28: 4920 status = i40e_read_phy_register_clause45(hw, page, reg, 4921 phy_addr, value); 4922 break; 4923 default: 4924 status = I40E_ERR_UNKNOWN_PHY; 4925 break; 4926 } 4927 4928 return status; 4929 } 4930 4931 /** 4932 * i40e_get_phy_address 4933 * @hw: pointer to the HW structure 4934 * @dev_num: PHY port num that address we want 4935 * 4936 * Gets PHY address for current port 4937 **/ 4938 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4939 { 4940 u8 port_num = hw->func_caps.mdio_port_num; 4941 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4942 4943 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4944 } 4945 4946 /** 4947 * i40e_blink_phy_link_led 4948 * @hw: pointer to the HW structure 4949 * @time: time how long led will blinks in secs 4950 * @interval: gap between LED on and off in msecs 4951 * 4952 * Blinks PHY link LED 4953 **/ 4954 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4955 u32 time, u32 interval) 4956 { 4957 i40e_status status = 0; 4958 u32 i; 4959 u16 led_ctl; 4960 u16 gpio_led_port; 4961 u16 led_reg; 4962 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4963 u8 phy_addr = 0; 4964 u8 port_num; 4965 4966 i = rd32(hw, I40E_PFGEN_PORTNUM); 4967 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4968 phy_addr = i40e_get_phy_address(hw, port_num); 4969 4970 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4971 led_addr++) { 4972 status = i40e_read_phy_register_clause45(hw, 4973 I40E_PHY_COM_REG_PAGE, 4974 led_addr, phy_addr, 4975 &led_reg); 4976 if (status) 4977 goto phy_blinking_end; 4978 led_ctl = led_reg; 4979 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4980 led_reg = 0; 4981 status = i40e_write_phy_register_clause45(hw, 4982 I40E_PHY_COM_REG_PAGE, 4983 led_addr, phy_addr, 4984 led_reg); 4985 if (status) 4986 goto phy_blinking_end; 4987 break; 4988 } 4989 } 4990 4991 if (time > 0 && interval > 0) { 4992 for (i = 0; i < time * 1000; i += interval) { 4993 status = i40e_read_phy_register_clause45(hw, 4994 I40E_PHY_COM_REG_PAGE, 4995 led_addr, phy_addr, &led_reg); 4996 if (status) 4997 goto restore_config; 4998 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4999 led_reg = 0; 5000 else 5001 led_reg = I40E_PHY_LED_MANUAL_ON; 5002 status = i40e_write_phy_register_clause45(hw, 5003 I40E_PHY_COM_REG_PAGE, 5004 led_addr, phy_addr, led_reg); 5005 if (status) 5006 goto restore_config; 5007 msleep(interval); 5008 } 5009 } 5010 5011 restore_config: 5012 status = i40e_write_phy_register_clause45(hw, 5013 I40E_PHY_COM_REG_PAGE, 5014 led_addr, phy_addr, led_ctl); 5015 5016 phy_blinking_end: 5017 return status; 5018 } 5019 5020 /** 5021 * i40e_led_get_reg - read LED register 5022 * @hw: pointer to the HW structure 5023 * @led_addr: LED register address 5024 * @reg_val: read register value 5025 **/ 5026 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 5027 u32 *reg_val) 5028 { 5029 enum i40e_status_code status; 5030 u8 phy_addr = 0; 5031 u8 port_num; 5032 u32 i; 5033 5034 *reg_val = 0; 5035 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5036 status = 5037 i40e_aq_get_phy_register(hw, 5038 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5039 I40E_PHY_COM_REG_PAGE, true, 5040 I40E_PHY_LED_PROV_REG_1, 5041 reg_val, NULL); 5042 } else { 5043 i = rd32(hw, I40E_PFGEN_PORTNUM); 5044 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5045 phy_addr = i40e_get_phy_address(hw, port_num); 5046 status = i40e_read_phy_register_clause45(hw, 5047 I40E_PHY_COM_REG_PAGE, 5048 led_addr, phy_addr, 5049 (u16 *)reg_val); 5050 } 5051 return status; 5052 } 5053 5054 /** 5055 * i40e_led_set_reg - write LED register 5056 * @hw: pointer to the HW structure 5057 * @led_addr: LED register address 5058 * @reg_val: register value to write 5059 **/ 5060 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 5061 u32 reg_val) 5062 { 5063 enum i40e_status_code status; 5064 u8 phy_addr = 0; 5065 u8 port_num; 5066 u32 i; 5067 5068 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5069 status = 5070 i40e_aq_set_phy_register(hw, 5071 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5072 I40E_PHY_COM_REG_PAGE, true, 5073 I40E_PHY_LED_PROV_REG_1, 5074 reg_val, NULL); 5075 } else { 5076 i = rd32(hw, I40E_PFGEN_PORTNUM); 5077 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5078 phy_addr = i40e_get_phy_address(hw, port_num); 5079 status = i40e_write_phy_register_clause45(hw, 5080 I40E_PHY_COM_REG_PAGE, 5081 led_addr, phy_addr, 5082 (u16)reg_val); 5083 } 5084 5085 return status; 5086 } 5087 5088 /** 5089 * i40e_led_get_phy - return current on/off mode 5090 * @hw: pointer to the hw struct 5091 * @led_addr: address of led register to use 5092 * @val: original value of register to use 5093 * 5094 **/ 5095 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 5096 u16 *val) 5097 { 5098 i40e_status status = 0; 5099 u16 gpio_led_port; 5100 u8 phy_addr = 0; 5101 u16 reg_val; 5102 u16 temp_addr; 5103 u8 port_num; 5104 u32 i; 5105 u32 reg_val_aq; 5106 5107 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5108 status = 5109 i40e_aq_get_phy_register(hw, 5110 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5111 I40E_PHY_COM_REG_PAGE, true, 5112 I40E_PHY_LED_PROV_REG_1, 5113 ®_val_aq, NULL); 5114 if (status == I40E_SUCCESS) 5115 *val = (u16)reg_val_aq; 5116 return status; 5117 } 5118 temp_addr = I40E_PHY_LED_PROV_REG_1; 5119 i = rd32(hw, I40E_PFGEN_PORTNUM); 5120 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5121 phy_addr = i40e_get_phy_address(hw, port_num); 5122 5123 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5124 temp_addr++) { 5125 status = i40e_read_phy_register_clause45(hw, 5126 I40E_PHY_COM_REG_PAGE, 5127 temp_addr, phy_addr, 5128 ®_val); 5129 if (status) 5130 return status; 5131 *val = reg_val; 5132 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 5133 *led_addr = temp_addr; 5134 break; 5135 } 5136 } 5137 return status; 5138 } 5139 5140 /** 5141 * i40e_led_set_phy 5142 * @hw: pointer to the HW structure 5143 * @on: true or false 5144 * @led_addr: address of led register to use 5145 * @mode: original val plus bit for set or ignore 5146 * 5147 * Set led's on or off when controlled by the PHY 5148 * 5149 **/ 5150 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 5151 u16 led_addr, u32 mode) 5152 { 5153 i40e_status status = 0; 5154 u32 led_ctl = 0; 5155 u32 led_reg = 0; 5156 5157 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5158 if (status) 5159 return status; 5160 led_ctl = led_reg; 5161 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5162 led_reg = 0; 5163 status = i40e_led_set_reg(hw, led_addr, led_reg); 5164 if (status) 5165 return status; 5166 } 5167 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5168 if (status) 5169 goto restore_config; 5170 if (on) 5171 led_reg = I40E_PHY_LED_MANUAL_ON; 5172 else 5173 led_reg = 0; 5174 5175 status = i40e_led_set_reg(hw, led_addr, led_reg); 5176 if (status) 5177 goto restore_config; 5178 if (mode & I40E_PHY_LED_MODE_ORIG) { 5179 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5180 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5181 } 5182 return status; 5183 5184 restore_config: 5185 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5186 return status; 5187 } 5188 5189 /** 5190 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5191 * @hw: pointer to the hw struct 5192 * @reg_addr: register address 5193 * @reg_val: ptr to register value 5194 * @cmd_details: pointer to command details structure or NULL 5195 * 5196 * Use the firmware to read the Rx control register, 5197 * especially useful if the Rx unit is under heavy pressure 5198 **/ 5199 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5200 u32 reg_addr, u32 *reg_val, 5201 struct i40e_asq_cmd_details *cmd_details) 5202 { 5203 struct i40e_aq_desc desc; 5204 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5205 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5206 i40e_status status; 5207 5208 if (!reg_val) 5209 return I40E_ERR_PARAM; 5210 5211 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5212 5213 cmd_resp->address = cpu_to_le32(reg_addr); 5214 5215 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5216 5217 if (status == 0) 5218 *reg_val = le32_to_cpu(cmd_resp->value); 5219 5220 return status; 5221 } 5222 5223 /** 5224 * i40e_read_rx_ctl - read from an Rx control register 5225 * @hw: pointer to the hw struct 5226 * @reg_addr: register address 5227 **/ 5228 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5229 { 5230 i40e_status status = 0; 5231 bool use_register; 5232 int retry = 5; 5233 u32 val = 0; 5234 5235 use_register = (((hw->aq.api_maj_ver == 1) && 5236 (hw->aq.api_min_ver < 5)) || 5237 (hw->mac.type == I40E_MAC_X722)); 5238 if (!use_register) { 5239 do_retry: 5240 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5241 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5242 usleep_range(1000, 2000); 5243 retry--; 5244 goto do_retry; 5245 } 5246 } 5247 5248 /* if the AQ access failed, try the old-fashioned way */ 5249 if (status || use_register) 5250 val = rd32(hw, reg_addr); 5251 5252 return val; 5253 } 5254 5255 /** 5256 * i40e_aq_rx_ctl_write_register 5257 * @hw: pointer to the hw struct 5258 * @reg_addr: register address 5259 * @reg_val: register value 5260 * @cmd_details: pointer to command details structure or NULL 5261 * 5262 * Use the firmware to write to an Rx control register, 5263 * especially useful if the Rx unit is under heavy pressure 5264 **/ 5265 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5266 u32 reg_addr, u32 reg_val, 5267 struct i40e_asq_cmd_details *cmd_details) 5268 { 5269 struct i40e_aq_desc desc; 5270 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5271 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5272 i40e_status status; 5273 5274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5275 5276 cmd->address = cpu_to_le32(reg_addr); 5277 cmd->value = cpu_to_le32(reg_val); 5278 5279 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5280 5281 return status; 5282 } 5283 5284 /** 5285 * i40e_write_rx_ctl - write to an Rx control register 5286 * @hw: pointer to the hw struct 5287 * @reg_addr: register address 5288 * @reg_val: register value 5289 **/ 5290 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5291 { 5292 i40e_status status = 0; 5293 bool use_register; 5294 int retry = 5; 5295 5296 use_register = (((hw->aq.api_maj_ver == 1) && 5297 (hw->aq.api_min_ver < 5)) || 5298 (hw->mac.type == I40E_MAC_X722)); 5299 if (!use_register) { 5300 do_retry: 5301 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5302 reg_val, NULL); 5303 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5304 usleep_range(1000, 2000); 5305 retry--; 5306 goto do_retry; 5307 } 5308 } 5309 5310 /* if the AQ access failed, try the old-fashioned way */ 5311 if (status || use_register) 5312 wr32(hw, reg_addr, reg_val); 5313 } 5314 5315 /** 5316 * i40e_mdio_if_number_selection - MDIO I/F number selection 5317 * @hw: pointer to the hw struct 5318 * @set_mdio: use MDIO I/F number specified by mdio_num 5319 * @mdio_num: MDIO I/F number 5320 * @cmd: pointer to PHY Register command structure 5321 **/ 5322 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, 5323 u8 mdio_num, 5324 struct i40e_aqc_phy_register_access *cmd) 5325 { 5326 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) { 5327 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED) 5328 cmd->cmd_flags |= 5329 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER | 5330 ((mdio_num << 5331 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) & 5332 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK); 5333 else 5334 i40e_debug(hw, I40E_DEBUG_PHY, 5335 "MDIO I/F number selection not supported by current FW version.\n"); 5336 } 5337 } 5338 5339 /** 5340 * i40e_aq_set_phy_register_ext 5341 * @hw: pointer to the hw struct 5342 * @phy_select: select which phy should be accessed 5343 * @dev_addr: PHY device address 5344 * @page_change: flag to indicate if phy page should be updated 5345 * @set_mdio: use MDIO I/F number specified by mdio_num 5346 * @mdio_num: MDIO I/F number 5347 * @reg_addr: PHY register address 5348 * @reg_val: new register value 5349 * @cmd_details: pointer to command details structure or NULL 5350 * 5351 * Write the external PHY register. 5352 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5353 * may use simple wrapper i40e_aq_set_phy_register. 5354 **/ 5355 enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw, 5356 u8 phy_select, u8 dev_addr, bool page_change, 5357 bool set_mdio, u8 mdio_num, 5358 u32 reg_addr, u32 reg_val, 5359 struct i40e_asq_cmd_details *cmd_details) 5360 { 5361 struct i40e_aq_desc desc; 5362 struct i40e_aqc_phy_register_access *cmd = 5363 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5364 i40e_status status; 5365 5366 i40e_fill_default_direct_cmd_desc(&desc, 5367 i40e_aqc_opc_set_phy_register); 5368 5369 cmd->phy_interface = phy_select; 5370 cmd->dev_address = dev_addr; 5371 cmd->reg_address = cpu_to_le32(reg_addr); 5372 cmd->reg_value = cpu_to_le32(reg_val); 5373 5374 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5375 5376 if (!page_change) 5377 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5378 5379 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5380 5381 return status; 5382 } 5383 5384 /** 5385 * i40e_aq_get_phy_register_ext 5386 * @hw: pointer to the hw struct 5387 * @phy_select: select which phy should be accessed 5388 * @dev_addr: PHY device address 5389 * @page_change: flag to indicate if phy page should be updated 5390 * @set_mdio: use MDIO I/F number specified by mdio_num 5391 * @mdio_num: MDIO I/F number 5392 * @reg_addr: PHY register address 5393 * @reg_val: read register value 5394 * @cmd_details: pointer to command details structure or NULL 5395 * 5396 * Read the external PHY register. 5397 * NOTE: In common cases MDIO I/F number should not be changed, thats why you 5398 * may use simple wrapper i40e_aq_get_phy_register. 5399 **/ 5400 enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw, 5401 u8 phy_select, u8 dev_addr, bool page_change, 5402 bool set_mdio, u8 mdio_num, 5403 u32 reg_addr, u32 *reg_val, 5404 struct i40e_asq_cmd_details *cmd_details) 5405 { 5406 struct i40e_aq_desc desc; 5407 struct i40e_aqc_phy_register_access *cmd = 5408 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5409 i40e_status status; 5410 5411 i40e_fill_default_direct_cmd_desc(&desc, 5412 i40e_aqc_opc_get_phy_register); 5413 5414 cmd->phy_interface = phy_select; 5415 cmd->dev_address = dev_addr; 5416 cmd->reg_address = cpu_to_le32(reg_addr); 5417 5418 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd); 5419 5420 if (!page_change) 5421 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE; 5422 5423 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5424 if (!status) 5425 *reg_val = le32_to_cpu(cmd->reg_value); 5426 5427 return status; 5428 } 5429 5430 /** 5431 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 5432 * @hw: pointer to the hw struct 5433 * @buff: command buffer (size in bytes = buff_size) 5434 * @buff_size: buffer size in bytes 5435 * @track_id: package tracking id 5436 * @error_offset: returns error offset 5437 * @error_info: returns error information 5438 * @cmd_details: pointer to command details structure or NULL 5439 **/ 5440 enum 5441 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 5442 u16 buff_size, u32 track_id, 5443 u32 *error_offset, u32 *error_info, 5444 struct i40e_asq_cmd_details *cmd_details) 5445 { 5446 struct i40e_aq_desc desc; 5447 struct i40e_aqc_write_personalization_profile *cmd = 5448 (struct i40e_aqc_write_personalization_profile *) 5449 &desc.params.raw; 5450 struct i40e_aqc_write_ddp_resp *resp; 5451 i40e_status status; 5452 5453 i40e_fill_default_direct_cmd_desc(&desc, 5454 i40e_aqc_opc_write_personalization_profile); 5455 5456 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5457 if (buff_size > I40E_AQ_LARGE_BUF) 5458 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5459 5460 desc.datalen = cpu_to_le16(buff_size); 5461 5462 cmd->profile_track_id = cpu_to_le32(track_id); 5463 5464 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5465 if (!status) { 5466 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 5467 if (error_offset) 5468 *error_offset = le32_to_cpu(resp->error_offset); 5469 if (error_info) 5470 *error_info = le32_to_cpu(resp->error_info); 5471 } 5472 5473 return status; 5474 } 5475 5476 /** 5477 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 5478 * @hw: pointer to the hw struct 5479 * @buff: command buffer (size in bytes = buff_size) 5480 * @buff_size: buffer size in bytes 5481 * @flags: AdminQ command flags 5482 * @cmd_details: pointer to command details structure or NULL 5483 **/ 5484 enum 5485 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 5486 u16 buff_size, u8 flags, 5487 struct i40e_asq_cmd_details *cmd_details) 5488 { 5489 struct i40e_aq_desc desc; 5490 struct i40e_aqc_get_applied_profiles *cmd = 5491 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5492 i40e_status status; 5493 5494 i40e_fill_default_direct_cmd_desc(&desc, 5495 i40e_aqc_opc_get_personalization_profile_list); 5496 5497 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5498 if (buff_size > I40E_AQ_LARGE_BUF) 5499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5500 desc.datalen = cpu_to_le16(buff_size); 5501 5502 cmd->flags = flags; 5503 5504 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5505 5506 return status; 5507 } 5508 5509 /** 5510 * i40e_find_segment_in_package 5511 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5512 * @pkg_hdr: pointer to the package header to be searched 5513 * 5514 * This function searches a package file for a particular segment type. On 5515 * success it returns a pointer to the segment header, otherwise it will 5516 * return NULL. 5517 **/ 5518 struct i40e_generic_seg_header * 5519 i40e_find_segment_in_package(u32 segment_type, 5520 struct i40e_package_header *pkg_hdr) 5521 { 5522 struct i40e_generic_seg_header *segment; 5523 u32 i; 5524 5525 /* Search all package segments for the requested segment type */ 5526 for (i = 0; i < pkg_hdr->segment_count; i++) { 5527 segment = 5528 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5529 pkg_hdr->segment_offset[i]); 5530 5531 if (segment->type == segment_type) 5532 return segment; 5533 } 5534 5535 return NULL; 5536 } 5537 5538 /* Get section table in profile */ 5539 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 5540 do { \ 5541 struct i40e_profile_segment *p = (profile); \ 5542 u32 count; \ 5543 u32 *nvm; \ 5544 count = p->device_table_count; \ 5545 nvm = (u32 *)&p->device_table[count]; \ 5546 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 5547 } while (0) 5548 5549 /* Get section header in profile */ 5550 #define I40E_SECTION_HEADER(profile, offset) \ 5551 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 5552 5553 /** 5554 * i40e_find_section_in_profile 5555 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 5556 * @profile: pointer to the i40e segment header to be searched 5557 * 5558 * This function searches i40e segment for a particular section type. On 5559 * success it returns a pointer to the section header, otherwise it will 5560 * return NULL. 5561 **/ 5562 struct i40e_profile_section_header * 5563 i40e_find_section_in_profile(u32 section_type, 5564 struct i40e_profile_segment *profile) 5565 { 5566 struct i40e_profile_section_header *sec; 5567 struct i40e_section_table *sec_tbl; 5568 u32 sec_off; 5569 u32 i; 5570 5571 if (profile->header.type != SEGMENT_TYPE_I40E) 5572 return NULL; 5573 5574 I40E_SECTION_TABLE(profile, sec_tbl); 5575 5576 for (i = 0; i < sec_tbl->section_count; i++) { 5577 sec_off = sec_tbl->section_offset[i]; 5578 sec = I40E_SECTION_HEADER(profile, sec_off); 5579 if (sec->section.type == section_type) 5580 return sec; 5581 } 5582 5583 return NULL; 5584 } 5585 5586 /** 5587 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 5588 * @hw: pointer to the hw struct 5589 * @aq: command buffer containing all data to execute AQ 5590 **/ 5591 static enum 5592 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 5593 struct i40e_profile_aq_section *aq) 5594 { 5595 i40e_status status; 5596 struct i40e_aq_desc desc; 5597 u8 *msg = NULL; 5598 u16 msglen; 5599 5600 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 5601 desc.flags |= cpu_to_le16(aq->flags); 5602 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 5603 5604 msglen = aq->datalen; 5605 if (msglen) { 5606 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 5607 I40E_AQ_FLAG_RD)); 5608 if (msglen > I40E_AQ_LARGE_BUF) 5609 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5610 desc.datalen = cpu_to_le16(msglen); 5611 msg = &aq->data[0]; 5612 } 5613 5614 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 5615 5616 if (status) { 5617 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5618 "unable to exec DDP AQ opcode %u, error %d\n", 5619 aq->opcode, status); 5620 return status; 5621 } 5622 5623 /* copy returned desc to aq_buf */ 5624 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 5625 5626 return 0; 5627 } 5628 5629 /** 5630 * i40e_validate_profile 5631 * @hw: pointer to the hardware structure 5632 * @profile: pointer to the profile segment of the package to be validated 5633 * @track_id: package tracking id 5634 * @rollback: flag if the profile is for rollback. 5635 * 5636 * Validates supported devices and profile's sections. 5637 */ 5638 static enum i40e_status_code 5639 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5640 u32 track_id, bool rollback) 5641 { 5642 struct i40e_profile_section_header *sec = NULL; 5643 i40e_status status = 0; 5644 struct i40e_section_table *sec_tbl; 5645 u32 vendor_dev_id; 5646 u32 dev_cnt; 5647 u32 sec_off; 5648 u32 i; 5649 5650 if (track_id == I40E_DDP_TRACKID_INVALID) { 5651 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 5652 return I40E_NOT_SUPPORTED; 5653 } 5654 5655 dev_cnt = profile->device_table_count; 5656 for (i = 0; i < dev_cnt; i++) { 5657 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5658 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 5659 hw->device_id == (vendor_dev_id & 0xFFFF)) 5660 break; 5661 } 5662 if (dev_cnt && i == dev_cnt) { 5663 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5664 "Device doesn't support DDP\n"); 5665 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5666 } 5667 5668 I40E_SECTION_TABLE(profile, sec_tbl); 5669 5670 /* Validate sections types */ 5671 for (i = 0; i < sec_tbl->section_count; i++) { 5672 sec_off = sec_tbl->section_offset[i]; 5673 sec = I40E_SECTION_HEADER(profile, sec_off); 5674 if (rollback) { 5675 if (sec->section.type == SECTION_TYPE_MMIO || 5676 sec->section.type == SECTION_TYPE_AQ || 5677 sec->section.type == SECTION_TYPE_RB_AQ) { 5678 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5679 "Not a roll-back package\n"); 5680 return I40E_NOT_SUPPORTED; 5681 } 5682 } else { 5683 if (sec->section.type == SECTION_TYPE_RB_AQ || 5684 sec->section.type == SECTION_TYPE_RB_MMIO) { 5685 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5686 "Not an original package\n"); 5687 return I40E_NOT_SUPPORTED; 5688 } 5689 } 5690 } 5691 5692 return status; 5693 } 5694 5695 /** 5696 * i40e_write_profile 5697 * @hw: pointer to the hardware structure 5698 * @profile: pointer to the profile segment of the package to be downloaded 5699 * @track_id: package tracking id 5700 * 5701 * Handles the download of a complete package. 5702 */ 5703 enum i40e_status_code 5704 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5705 u32 track_id) 5706 { 5707 i40e_status status = 0; 5708 struct i40e_section_table *sec_tbl; 5709 struct i40e_profile_section_header *sec = NULL; 5710 struct i40e_profile_aq_section *ddp_aq; 5711 u32 section_size = 0; 5712 u32 offset = 0, info = 0; 5713 u32 sec_off; 5714 u32 i; 5715 5716 status = i40e_validate_profile(hw, profile, track_id, false); 5717 if (status) 5718 return status; 5719 5720 I40E_SECTION_TABLE(profile, sec_tbl); 5721 5722 for (i = 0; i < sec_tbl->section_count; i++) { 5723 sec_off = sec_tbl->section_offset[i]; 5724 sec = I40E_SECTION_HEADER(profile, sec_off); 5725 /* Process generic admin command */ 5726 if (sec->section.type == SECTION_TYPE_AQ) { 5727 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5728 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5729 if (status) { 5730 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5731 "Failed to execute aq: section %d, opcode %u\n", 5732 i, ddp_aq->opcode); 5733 break; 5734 } 5735 sec->section.type = SECTION_TYPE_RB_AQ; 5736 } 5737 5738 /* Skip any non-mmio sections */ 5739 if (sec->section.type != SECTION_TYPE_MMIO) 5740 continue; 5741 5742 section_size = sec->section.size + 5743 sizeof(struct i40e_profile_section_header); 5744 5745 /* Write MMIO section */ 5746 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5747 track_id, &offset, &info, NULL); 5748 if (status) { 5749 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5750 "Failed to write profile: section %d, offset %d, info %d\n", 5751 i, offset, info); 5752 break; 5753 } 5754 } 5755 return status; 5756 } 5757 5758 /** 5759 * i40e_rollback_profile 5760 * @hw: pointer to the hardware structure 5761 * @profile: pointer to the profile segment of the package to be removed 5762 * @track_id: package tracking id 5763 * 5764 * Rolls back previously loaded package. 5765 */ 5766 enum i40e_status_code 5767 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5768 u32 track_id) 5769 { 5770 struct i40e_profile_section_header *sec = NULL; 5771 i40e_status status = 0; 5772 struct i40e_section_table *sec_tbl; 5773 u32 offset = 0, info = 0; 5774 u32 section_size = 0; 5775 u32 sec_off; 5776 int i; 5777 5778 status = i40e_validate_profile(hw, profile, track_id, true); 5779 if (status) 5780 return status; 5781 5782 I40E_SECTION_TABLE(profile, sec_tbl); 5783 5784 /* For rollback write sections in reverse */ 5785 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5786 sec_off = sec_tbl->section_offset[i]; 5787 sec = I40E_SECTION_HEADER(profile, sec_off); 5788 5789 /* Skip any non-rollback sections */ 5790 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5791 continue; 5792 5793 section_size = sec->section.size + 5794 sizeof(struct i40e_profile_section_header); 5795 5796 /* Write roll-back MMIO section */ 5797 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5798 track_id, &offset, &info, NULL); 5799 if (status) { 5800 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5801 "Failed to write profile: section %d, offset %d, info %d\n", 5802 i, offset, info); 5803 break; 5804 } 5805 } 5806 return status; 5807 } 5808 5809 /** 5810 * i40e_add_pinfo_to_list 5811 * @hw: pointer to the hardware structure 5812 * @profile: pointer to the profile segment of the package 5813 * @profile_info_sec: buffer for information section 5814 * @track_id: package tracking id 5815 * 5816 * Register a profile to the list of loaded profiles. 5817 */ 5818 enum i40e_status_code 5819 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5820 struct i40e_profile_segment *profile, 5821 u8 *profile_info_sec, u32 track_id) 5822 { 5823 i40e_status status = 0; 5824 struct i40e_profile_section_header *sec = NULL; 5825 struct i40e_profile_info *pinfo; 5826 u32 offset = 0, info = 0; 5827 5828 sec = (struct i40e_profile_section_header *)profile_info_sec; 5829 sec->tbl_size = 1; 5830 sec->data_end = sizeof(struct i40e_profile_section_header) + 5831 sizeof(struct i40e_profile_info); 5832 sec->section.type = SECTION_TYPE_INFO; 5833 sec->section.offset = sizeof(struct i40e_profile_section_header); 5834 sec->section.size = sizeof(struct i40e_profile_info); 5835 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5836 sec->section.offset); 5837 pinfo->track_id = track_id; 5838 pinfo->version = profile->version; 5839 pinfo->op = I40E_DDP_ADD_TRACKID; 5840 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); 5841 5842 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 5843 track_id, &offset, &info, NULL); 5844 5845 return status; 5846 } 5847 5848 /** 5849 * i40e_aq_add_cloud_filters 5850 * @hw: pointer to the hardware structure 5851 * @seid: VSI seid to add cloud filters from 5852 * @filters: Buffer which contains the filters to be added 5853 * @filter_count: number of filters contained in the buffer 5854 * 5855 * Set the cloud filters for a given VSI. The contents of the 5856 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5857 * of the function. 5858 * 5859 **/ 5860 enum i40e_status_code 5861 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5862 struct i40e_aqc_cloud_filters_element_data *filters, 5863 u8 filter_count) 5864 { 5865 struct i40e_aq_desc desc; 5866 struct i40e_aqc_add_remove_cloud_filters *cmd = 5867 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5868 enum i40e_status_code status; 5869 u16 buff_len; 5870 5871 i40e_fill_default_direct_cmd_desc(&desc, 5872 i40e_aqc_opc_add_cloud_filters); 5873 5874 buff_len = filter_count * sizeof(*filters); 5875 desc.datalen = cpu_to_le16(buff_len); 5876 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5877 cmd->num_filters = filter_count; 5878 cmd->seid = cpu_to_le16(seid); 5879 5880 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5881 5882 return status; 5883 } 5884 5885 /** 5886 * i40e_aq_add_cloud_filters_bb 5887 * @hw: pointer to the hardware structure 5888 * @seid: VSI seid to add cloud filters from 5889 * @filters: Buffer which contains the filters in big buffer to be added 5890 * @filter_count: number of filters contained in the buffer 5891 * 5892 * Set the big buffer cloud filters for a given VSI. The contents of the 5893 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5894 * function. 5895 * 5896 **/ 5897 enum i40e_status_code 5898 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5899 struct i40e_aqc_cloud_filters_element_bb *filters, 5900 u8 filter_count) 5901 { 5902 struct i40e_aq_desc desc; 5903 struct i40e_aqc_add_remove_cloud_filters *cmd = 5904 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5905 i40e_status status; 5906 u16 buff_len; 5907 int i; 5908 5909 i40e_fill_default_direct_cmd_desc(&desc, 5910 i40e_aqc_opc_add_cloud_filters); 5911 5912 buff_len = filter_count * sizeof(*filters); 5913 desc.datalen = cpu_to_le16(buff_len); 5914 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5915 cmd->num_filters = filter_count; 5916 cmd->seid = cpu_to_le16(seid); 5917 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5918 5919 for (i = 0; i < filter_count; i++) { 5920 u16 tnl_type; 5921 u32 ti; 5922 5923 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5924 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5925 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5926 5927 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5928 * one more byte further than normally used for Tenant ID in 5929 * other tunnel types. 5930 */ 5931 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5932 ti = le32_to_cpu(filters[i].element.tenant_id); 5933 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5934 } 5935 } 5936 5937 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5938 5939 return status; 5940 } 5941 5942 /** 5943 * i40e_aq_rem_cloud_filters 5944 * @hw: pointer to the hardware structure 5945 * @seid: VSI seid to remove cloud filters from 5946 * @filters: Buffer which contains the filters to be removed 5947 * @filter_count: number of filters contained in the buffer 5948 * 5949 * Remove the cloud filters for a given VSI. The contents of the 5950 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5951 * of the function. 5952 * 5953 **/ 5954 enum i40e_status_code 5955 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5956 struct i40e_aqc_cloud_filters_element_data *filters, 5957 u8 filter_count) 5958 { 5959 struct i40e_aq_desc desc; 5960 struct i40e_aqc_add_remove_cloud_filters *cmd = 5961 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5962 enum i40e_status_code status; 5963 u16 buff_len; 5964 5965 i40e_fill_default_direct_cmd_desc(&desc, 5966 i40e_aqc_opc_remove_cloud_filters); 5967 5968 buff_len = filter_count * sizeof(*filters); 5969 desc.datalen = cpu_to_le16(buff_len); 5970 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5971 cmd->num_filters = filter_count; 5972 cmd->seid = cpu_to_le16(seid); 5973 5974 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5975 5976 return status; 5977 } 5978 5979 /** 5980 * i40e_aq_rem_cloud_filters_bb 5981 * @hw: pointer to the hardware structure 5982 * @seid: VSI seid to remove cloud filters from 5983 * @filters: Buffer which contains the filters in big buffer to be removed 5984 * @filter_count: number of filters contained in the buffer 5985 * 5986 * Remove the big buffer cloud filters for a given VSI. The contents of the 5987 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5988 * function. 5989 * 5990 **/ 5991 enum i40e_status_code 5992 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5993 struct i40e_aqc_cloud_filters_element_bb *filters, 5994 u8 filter_count) 5995 { 5996 struct i40e_aq_desc desc; 5997 struct i40e_aqc_add_remove_cloud_filters *cmd = 5998 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5999 i40e_status status; 6000 u16 buff_len; 6001 int i; 6002 6003 i40e_fill_default_direct_cmd_desc(&desc, 6004 i40e_aqc_opc_remove_cloud_filters); 6005 6006 buff_len = filter_count * sizeof(*filters); 6007 desc.datalen = cpu_to_le16(buff_len); 6008 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 6009 cmd->num_filters = filter_count; 6010 cmd->seid = cpu_to_le16(seid); 6011 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 6012 6013 for (i = 0; i < filter_count; i++) { 6014 u16 tnl_type; 6015 u32 ti; 6016 6017 tnl_type = (le16_to_cpu(filters[i].element.flags) & 6018 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 6019 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 6020 6021 /* Due to hardware eccentricities, the VNI for Geneve is shifted 6022 * one more byte further than normally used for Tenant ID in 6023 * other tunnel types. 6024 */ 6025 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 6026 ti = le32_to_cpu(filters[i].element.tenant_id); 6027 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 6028 } 6029 } 6030 6031 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 6032 6033 return status; 6034 } 6035