1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include "i40e_virtchnl.h" 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 u16 i = 0; 304 305 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 306 return; 307 308 len = le16_to_cpu(aq_desc->datalen); 309 310 i40e_debug(hw, mask, 311 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 312 le16_to_cpu(aq_desc->opcode), 313 le16_to_cpu(aq_desc->flags), 314 le16_to_cpu(aq_desc->datalen), 315 le16_to_cpu(aq_desc->retval)); 316 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 317 le32_to_cpu(aq_desc->cookie_high), 318 le32_to_cpu(aq_desc->cookie_low)); 319 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 320 le32_to_cpu(aq_desc->params.internal.param0), 321 le32_to_cpu(aq_desc->params.internal.param1)); 322 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 323 le32_to_cpu(aq_desc->params.external.addr_high), 324 le32_to_cpu(aq_desc->params.external.addr_low)); 325 326 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 327 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 328 if (buf_len < len) 329 len = buf_len; 330 /* write the full 16-byte chunks */ 331 for (i = 0; i < (len - 16); i += 16) 332 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i); 333 /* write whatever's left over without overrunning the buffer */ 334 if (i < len) 335 i40e_debug(hw, mask, "\t0x%04X %*ph\n", 336 i, len - i, buf + i); 337 } 338 } 339 340 /** 341 * i40e_check_asq_alive 342 * @hw: pointer to the hw struct 343 * 344 * Returns true if Queue is enabled else false. 345 **/ 346 bool i40e_check_asq_alive(struct i40e_hw *hw) 347 { 348 if (hw->aq.asq.len) 349 return !!(rd32(hw, hw->aq.asq.len) & 350 I40E_PF_ATQLEN_ATQENABLE_MASK); 351 else 352 return false; 353 } 354 355 /** 356 * i40e_aq_queue_shutdown 357 * @hw: pointer to the hw struct 358 * @unloading: is the driver unloading itself 359 * 360 * Tell the Firmware that we're shutting down the AdminQ and whether 361 * or not the driver is unloading as well. 362 **/ 363 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 364 bool unloading) 365 { 366 struct i40e_aq_desc desc; 367 struct i40e_aqc_queue_shutdown *cmd = 368 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 369 i40e_status status; 370 371 i40e_fill_default_direct_cmd_desc(&desc, 372 i40e_aqc_opc_queue_shutdown); 373 374 if (unloading) 375 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 376 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 377 378 return status; 379 } 380 381 /** 382 * i40e_aq_get_set_rss_lut 383 * @hw: pointer to the hardware structure 384 * @vsi_id: vsi fw index 385 * @pf_lut: for PF table set true, for VSI table set false 386 * @lut: pointer to the lut buffer provided by the caller 387 * @lut_size: size of the lut buffer 388 * @set: set true to set the table, false to get the table 389 * 390 * Internal function to get or set RSS look up table 391 **/ 392 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 393 u16 vsi_id, bool pf_lut, 394 u8 *lut, u16 lut_size, 395 bool set) 396 { 397 i40e_status status; 398 struct i40e_aq_desc desc; 399 struct i40e_aqc_get_set_rss_lut *cmd_resp = 400 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 401 402 if (set) 403 i40e_fill_default_direct_cmd_desc(&desc, 404 i40e_aqc_opc_set_rss_lut); 405 else 406 i40e_fill_default_direct_cmd_desc(&desc, 407 i40e_aqc_opc_get_rss_lut); 408 409 /* Indirect command */ 410 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 411 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 412 413 cmd_resp->vsi_id = 414 cpu_to_le16((u16)((vsi_id << 415 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 416 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 417 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 418 419 if (pf_lut) 420 cmd_resp->flags |= cpu_to_le16((u16) 421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 424 else 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 430 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 431 432 return status; 433 } 434 435 /** 436 * i40e_aq_get_rss_lut 437 * @hw: pointer to the hardware structure 438 * @vsi_id: vsi fw index 439 * @pf_lut: for PF table set true, for VSI table set false 440 * @lut: pointer to the lut buffer provided by the caller 441 * @lut_size: size of the lut buffer 442 * 443 * get the RSS lookup table, PF or VSI type 444 **/ 445 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 446 bool pf_lut, u8 *lut, u16 lut_size) 447 { 448 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 449 false); 450 } 451 452 /** 453 * i40e_aq_set_rss_lut 454 * @hw: pointer to the hardware structure 455 * @vsi_id: vsi fw index 456 * @pf_lut: for PF table set true, for VSI table set false 457 * @lut: pointer to the lut buffer provided by the caller 458 * @lut_size: size of the lut buffer 459 * 460 * set the RSS lookup table, PF or VSI type 461 **/ 462 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 463 bool pf_lut, u8 *lut, u16 lut_size) 464 { 465 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 466 } 467 468 /** 469 * i40e_aq_get_set_rss_key 470 * @hw: pointer to the hw struct 471 * @vsi_id: vsi fw index 472 * @key: pointer to key info struct 473 * @set: set true to set the key, false to get the key 474 * 475 * get the RSS key per VSI 476 **/ 477 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 478 u16 vsi_id, 479 struct i40e_aqc_get_set_rss_key_data *key, 480 bool set) 481 { 482 i40e_status status; 483 struct i40e_aq_desc desc; 484 struct i40e_aqc_get_set_rss_key *cmd_resp = 485 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 486 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 487 488 if (set) 489 i40e_fill_default_direct_cmd_desc(&desc, 490 i40e_aqc_opc_set_rss_key); 491 else 492 i40e_fill_default_direct_cmd_desc(&desc, 493 i40e_aqc_opc_get_rss_key); 494 495 /* Indirect command */ 496 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 497 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 498 499 cmd_resp->vsi_id = 500 cpu_to_le16((u16)((vsi_id << 501 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 502 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 503 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 504 505 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 506 507 return status; 508 } 509 510 /** 511 * i40e_aq_get_rss_key 512 * @hw: pointer to the hw struct 513 * @vsi_id: vsi fw index 514 * @key: pointer to key info struct 515 * 516 **/ 517 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 518 u16 vsi_id, 519 struct i40e_aqc_get_set_rss_key_data *key) 520 { 521 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 522 } 523 524 /** 525 * i40e_aq_set_rss_key 526 * @hw: pointer to the hw struct 527 * @vsi_id: vsi fw index 528 * @key: pointer to key info struct 529 * 530 * set the RSS key per VSI 531 **/ 532 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 533 u16 vsi_id, 534 struct i40e_aqc_get_set_rss_key_data *key) 535 { 536 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 537 } 538 539 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 540 * hardware to a bit-field that can be used by SW to more easily determine the 541 * packet type. 542 * 543 * Macros are used to shorten the table lines and make this table human 544 * readable. 545 * 546 * We store the PTYPE in the top byte of the bit field - this is just so that 547 * we can check that the table doesn't have a row missing, as the index into 548 * the table should be the PTYPE. 549 * 550 * Typical work flow: 551 * 552 * IF NOT i40e_ptype_lookup[ptype].known 553 * THEN 554 * Packet is unknown 555 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 556 * Use the rest of the fields to look at the tunnels, inner protocols, etc 557 * ELSE 558 * Use the enum i40e_rx_l2_ptype to decode the packet type 559 * ENDIF 560 */ 561 562 /* macro to make the table lines short */ 563 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 564 { PTYPE, \ 565 1, \ 566 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 567 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 568 I40E_RX_PTYPE_##OUTER_FRAG, \ 569 I40E_RX_PTYPE_TUNNEL_##T, \ 570 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 571 I40E_RX_PTYPE_##TEF, \ 572 I40E_RX_PTYPE_INNER_PROT_##I, \ 573 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 574 575 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 576 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 577 578 /* shorter macros makes the table fit but are terse */ 579 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 580 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 581 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 582 583 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 584 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 585 /* L2 Packet types */ 586 I40E_PTT_UNUSED_ENTRY(0), 587 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 588 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 589 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 590 I40E_PTT_UNUSED_ENTRY(4), 591 I40E_PTT_UNUSED_ENTRY(5), 592 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 594 I40E_PTT_UNUSED_ENTRY(8), 595 I40E_PTT_UNUSED_ENTRY(9), 596 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 597 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 598 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 599 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 600 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 601 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 602 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 609 /* Non Tunneled IPv4 */ 610 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 613 I40E_PTT_UNUSED_ENTRY(25), 614 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 615 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 616 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 617 618 /* IPv4 --> IPv4 */ 619 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 620 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 621 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 622 I40E_PTT_UNUSED_ENTRY(32), 623 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 624 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 625 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 626 627 /* IPv4 --> IPv6 */ 628 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 629 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 630 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 631 I40E_PTT_UNUSED_ENTRY(39), 632 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 633 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 634 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 635 636 /* IPv4 --> GRE/NAT */ 637 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 638 639 /* IPv4 --> GRE/NAT --> IPv4 */ 640 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 641 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 642 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 643 I40E_PTT_UNUSED_ENTRY(47), 644 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 645 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 646 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 647 648 /* IPv4 --> GRE/NAT --> IPv6 */ 649 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 650 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 651 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 652 I40E_PTT_UNUSED_ENTRY(54), 653 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 654 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 655 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 656 657 /* IPv4 --> GRE/NAT --> MAC */ 658 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 659 660 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 661 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 662 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 663 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 664 I40E_PTT_UNUSED_ENTRY(62), 665 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 666 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 667 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 668 669 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 670 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 671 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 672 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 673 I40E_PTT_UNUSED_ENTRY(69), 674 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 675 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 676 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 677 678 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 679 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 680 681 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 682 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 683 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 684 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 685 I40E_PTT_UNUSED_ENTRY(77), 686 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 687 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 688 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 689 690 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 691 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 692 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 693 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 694 I40E_PTT_UNUSED_ENTRY(84), 695 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 696 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 697 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 698 699 /* Non Tunneled IPv6 */ 700 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 701 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 702 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 703 I40E_PTT_UNUSED_ENTRY(91), 704 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 705 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 706 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 707 708 /* IPv6 --> IPv4 */ 709 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 710 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 711 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 712 I40E_PTT_UNUSED_ENTRY(98), 713 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 714 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 715 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 716 717 /* IPv6 --> IPv6 */ 718 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 719 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 720 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 721 I40E_PTT_UNUSED_ENTRY(105), 722 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 723 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 724 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 725 726 /* IPv6 --> GRE/NAT */ 727 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 728 729 /* IPv6 --> GRE/NAT -> IPv4 */ 730 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 731 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 732 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 733 I40E_PTT_UNUSED_ENTRY(113), 734 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 735 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 736 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 737 738 /* IPv6 --> GRE/NAT -> IPv6 */ 739 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 740 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 741 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 742 I40E_PTT_UNUSED_ENTRY(120), 743 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 744 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 745 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 746 747 /* IPv6 --> GRE/NAT -> MAC */ 748 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 749 750 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 751 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 752 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 753 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 754 I40E_PTT_UNUSED_ENTRY(128), 755 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 756 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 757 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 758 759 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 760 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 761 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 762 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 763 I40E_PTT_UNUSED_ENTRY(135), 764 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 765 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 766 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 767 768 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 769 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 770 771 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 772 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 773 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 774 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 775 I40E_PTT_UNUSED_ENTRY(143), 776 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 777 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 778 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 779 780 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 781 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 782 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 783 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 784 I40E_PTT_UNUSED_ENTRY(150), 785 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 786 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 787 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 788 789 /* unused entries */ 790 I40E_PTT_UNUSED_ENTRY(154), 791 I40E_PTT_UNUSED_ENTRY(155), 792 I40E_PTT_UNUSED_ENTRY(156), 793 I40E_PTT_UNUSED_ENTRY(157), 794 I40E_PTT_UNUSED_ENTRY(158), 795 I40E_PTT_UNUSED_ENTRY(159), 796 797 I40E_PTT_UNUSED_ENTRY(160), 798 I40E_PTT_UNUSED_ENTRY(161), 799 I40E_PTT_UNUSED_ENTRY(162), 800 I40E_PTT_UNUSED_ENTRY(163), 801 I40E_PTT_UNUSED_ENTRY(164), 802 I40E_PTT_UNUSED_ENTRY(165), 803 I40E_PTT_UNUSED_ENTRY(166), 804 I40E_PTT_UNUSED_ENTRY(167), 805 I40E_PTT_UNUSED_ENTRY(168), 806 I40E_PTT_UNUSED_ENTRY(169), 807 808 I40E_PTT_UNUSED_ENTRY(170), 809 I40E_PTT_UNUSED_ENTRY(171), 810 I40E_PTT_UNUSED_ENTRY(172), 811 I40E_PTT_UNUSED_ENTRY(173), 812 I40E_PTT_UNUSED_ENTRY(174), 813 I40E_PTT_UNUSED_ENTRY(175), 814 I40E_PTT_UNUSED_ENTRY(176), 815 I40E_PTT_UNUSED_ENTRY(177), 816 I40E_PTT_UNUSED_ENTRY(178), 817 I40E_PTT_UNUSED_ENTRY(179), 818 819 I40E_PTT_UNUSED_ENTRY(180), 820 I40E_PTT_UNUSED_ENTRY(181), 821 I40E_PTT_UNUSED_ENTRY(182), 822 I40E_PTT_UNUSED_ENTRY(183), 823 I40E_PTT_UNUSED_ENTRY(184), 824 I40E_PTT_UNUSED_ENTRY(185), 825 I40E_PTT_UNUSED_ENTRY(186), 826 I40E_PTT_UNUSED_ENTRY(187), 827 I40E_PTT_UNUSED_ENTRY(188), 828 I40E_PTT_UNUSED_ENTRY(189), 829 830 I40E_PTT_UNUSED_ENTRY(190), 831 I40E_PTT_UNUSED_ENTRY(191), 832 I40E_PTT_UNUSED_ENTRY(192), 833 I40E_PTT_UNUSED_ENTRY(193), 834 I40E_PTT_UNUSED_ENTRY(194), 835 I40E_PTT_UNUSED_ENTRY(195), 836 I40E_PTT_UNUSED_ENTRY(196), 837 I40E_PTT_UNUSED_ENTRY(197), 838 I40E_PTT_UNUSED_ENTRY(198), 839 I40E_PTT_UNUSED_ENTRY(199), 840 841 I40E_PTT_UNUSED_ENTRY(200), 842 I40E_PTT_UNUSED_ENTRY(201), 843 I40E_PTT_UNUSED_ENTRY(202), 844 I40E_PTT_UNUSED_ENTRY(203), 845 I40E_PTT_UNUSED_ENTRY(204), 846 I40E_PTT_UNUSED_ENTRY(205), 847 I40E_PTT_UNUSED_ENTRY(206), 848 I40E_PTT_UNUSED_ENTRY(207), 849 I40E_PTT_UNUSED_ENTRY(208), 850 I40E_PTT_UNUSED_ENTRY(209), 851 852 I40E_PTT_UNUSED_ENTRY(210), 853 I40E_PTT_UNUSED_ENTRY(211), 854 I40E_PTT_UNUSED_ENTRY(212), 855 I40E_PTT_UNUSED_ENTRY(213), 856 I40E_PTT_UNUSED_ENTRY(214), 857 I40E_PTT_UNUSED_ENTRY(215), 858 I40E_PTT_UNUSED_ENTRY(216), 859 I40E_PTT_UNUSED_ENTRY(217), 860 I40E_PTT_UNUSED_ENTRY(218), 861 I40E_PTT_UNUSED_ENTRY(219), 862 863 I40E_PTT_UNUSED_ENTRY(220), 864 I40E_PTT_UNUSED_ENTRY(221), 865 I40E_PTT_UNUSED_ENTRY(222), 866 I40E_PTT_UNUSED_ENTRY(223), 867 I40E_PTT_UNUSED_ENTRY(224), 868 I40E_PTT_UNUSED_ENTRY(225), 869 I40E_PTT_UNUSED_ENTRY(226), 870 I40E_PTT_UNUSED_ENTRY(227), 871 I40E_PTT_UNUSED_ENTRY(228), 872 I40E_PTT_UNUSED_ENTRY(229), 873 874 I40E_PTT_UNUSED_ENTRY(230), 875 I40E_PTT_UNUSED_ENTRY(231), 876 I40E_PTT_UNUSED_ENTRY(232), 877 I40E_PTT_UNUSED_ENTRY(233), 878 I40E_PTT_UNUSED_ENTRY(234), 879 I40E_PTT_UNUSED_ENTRY(235), 880 I40E_PTT_UNUSED_ENTRY(236), 881 I40E_PTT_UNUSED_ENTRY(237), 882 I40E_PTT_UNUSED_ENTRY(238), 883 I40E_PTT_UNUSED_ENTRY(239), 884 885 I40E_PTT_UNUSED_ENTRY(240), 886 I40E_PTT_UNUSED_ENTRY(241), 887 I40E_PTT_UNUSED_ENTRY(242), 888 I40E_PTT_UNUSED_ENTRY(243), 889 I40E_PTT_UNUSED_ENTRY(244), 890 I40E_PTT_UNUSED_ENTRY(245), 891 I40E_PTT_UNUSED_ENTRY(246), 892 I40E_PTT_UNUSED_ENTRY(247), 893 I40E_PTT_UNUSED_ENTRY(248), 894 I40E_PTT_UNUSED_ENTRY(249), 895 896 I40E_PTT_UNUSED_ENTRY(250), 897 I40E_PTT_UNUSED_ENTRY(251), 898 I40E_PTT_UNUSED_ENTRY(252), 899 I40E_PTT_UNUSED_ENTRY(253), 900 I40E_PTT_UNUSED_ENTRY(254), 901 I40E_PTT_UNUSED_ENTRY(255) 902 }; 903 904 /** 905 * i40e_init_shared_code - Initialize the shared code 906 * @hw: pointer to hardware structure 907 * 908 * This assigns the MAC type and PHY code and inits the NVM. 909 * Does not touch the hardware. This function must be called prior to any 910 * other function in the shared code. The i40e_hw structure should be 911 * memset to 0 prior to calling this function. The following fields in 912 * hw structure should be filled in prior to calling this function: 913 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 914 * subsystem_vendor_id, and revision_id 915 **/ 916 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 917 { 918 i40e_status status = 0; 919 u32 port, ari, func_rid; 920 921 i40e_set_mac_type(hw); 922 923 switch (hw->mac.type) { 924 case I40E_MAC_XL710: 925 case I40E_MAC_X722: 926 break; 927 default: 928 return I40E_ERR_DEVICE_NOT_SUPPORTED; 929 } 930 931 hw->phy.get_link_info = true; 932 933 /* Determine port number and PF number*/ 934 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 935 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 936 hw->port = (u8)port; 937 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 938 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 939 func_rid = rd32(hw, I40E_PF_FUNC_RID); 940 if (ari) 941 hw->pf_id = (u8)(func_rid & 0xff); 942 else 943 hw->pf_id = (u8)(func_rid & 0x7); 944 945 if (hw->mac.type == I40E_MAC_X722) 946 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 947 948 status = i40e_init_nvm(hw); 949 return status; 950 } 951 952 /** 953 * i40e_aq_mac_address_read - Retrieve the MAC addresses 954 * @hw: pointer to the hw struct 955 * @flags: a return indicator of what addresses were added to the addr store 956 * @addrs: the requestor's mac addr store 957 * @cmd_details: pointer to command details structure or NULL 958 **/ 959 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 960 u16 *flags, 961 struct i40e_aqc_mac_address_read_data *addrs, 962 struct i40e_asq_cmd_details *cmd_details) 963 { 964 struct i40e_aq_desc desc; 965 struct i40e_aqc_mac_address_read *cmd_data = 966 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 967 i40e_status status; 968 969 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 970 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 971 972 status = i40e_asq_send_command(hw, &desc, addrs, 973 sizeof(*addrs), cmd_details); 974 *flags = le16_to_cpu(cmd_data->command_flags); 975 976 return status; 977 } 978 979 /** 980 * i40e_aq_mac_address_write - Change the MAC addresses 981 * @hw: pointer to the hw struct 982 * @flags: indicates which MAC to be written 983 * @mac_addr: address to write 984 * @cmd_details: pointer to command details structure or NULL 985 **/ 986 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 987 u16 flags, u8 *mac_addr, 988 struct i40e_asq_cmd_details *cmd_details) 989 { 990 struct i40e_aq_desc desc; 991 struct i40e_aqc_mac_address_write *cmd_data = 992 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 993 i40e_status status; 994 995 i40e_fill_default_direct_cmd_desc(&desc, 996 i40e_aqc_opc_mac_address_write); 997 cmd_data->command_flags = cpu_to_le16(flags); 998 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 999 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1000 ((u32)mac_addr[3] << 16) | 1001 ((u32)mac_addr[4] << 8) | 1002 mac_addr[5]); 1003 1004 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1005 1006 return status; 1007 } 1008 1009 /** 1010 * i40e_get_mac_addr - get MAC address 1011 * @hw: pointer to the HW structure 1012 * @mac_addr: pointer to MAC address 1013 * 1014 * Reads the adapter's MAC address from register 1015 **/ 1016 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1017 { 1018 struct i40e_aqc_mac_address_read_data addrs; 1019 i40e_status status; 1020 u16 flags = 0; 1021 1022 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1023 1024 if (flags & I40E_AQC_LAN_ADDR_VALID) 1025 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1026 1027 return status; 1028 } 1029 1030 /** 1031 * i40e_get_port_mac_addr - get Port MAC address 1032 * @hw: pointer to the HW structure 1033 * @mac_addr: pointer to Port MAC address 1034 * 1035 * Reads the adapter's Port MAC address 1036 **/ 1037 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1038 { 1039 struct i40e_aqc_mac_address_read_data addrs; 1040 i40e_status status; 1041 u16 flags = 0; 1042 1043 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1044 if (status) 1045 return status; 1046 1047 if (flags & I40E_AQC_PORT_ADDR_VALID) 1048 ether_addr_copy(mac_addr, addrs.port_mac); 1049 else 1050 status = I40E_ERR_INVALID_MAC_ADDR; 1051 1052 return status; 1053 } 1054 1055 /** 1056 * i40e_pre_tx_queue_cfg - pre tx queue configure 1057 * @hw: pointer to the HW structure 1058 * @queue: target PF queue index 1059 * @enable: state change request 1060 * 1061 * Handles hw requirement to indicate intention to enable 1062 * or disable target queue. 1063 **/ 1064 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1065 { 1066 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1067 u32 reg_block = 0; 1068 u32 reg_val; 1069 1070 if (abs_queue_idx >= 128) { 1071 reg_block = abs_queue_idx / 128; 1072 abs_queue_idx %= 128; 1073 } 1074 1075 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1076 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1077 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1078 1079 if (enable) 1080 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1081 else 1082 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1083 1084 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1085 } 1086 #ifdef I40E_FCOE 1087 1088 /** 1089 * i40e_get_san_mac_addr - get SAN MAC address 1090 * @hw: pointer to the HW structure 1091 * @mac_addr: pointer to SAN MAC address 1092 * 1093 * Reads the adapter's SAN MAC address from NVM 1094 **/ 1095 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1096 { 1097 struct i40e_aqc_mac_address_read_data addrs; 1098 i40e_status status; 1099 u16 flags = 0; 1100 1101 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1102 if (status) 1103 return status; 1104 1105 if (flags & I40E_AQC_SAN_ADDR_VALID) 1106 ether_addr_copy(mac_addr, addrs.pf_san_mac); 1107 else 1108 status = I40E_ERR_INVALID_MAC_ADDR; 1109 1110 return status; 1111 } 1112 #endif 1113 1114 /** 1115 * i40e_read_pba_string - Reads part number string from EEPROM 1116 * @hw: pointer to hardware structure 1117 * @pba_num: stores the part number string from the EEPROM 1118 * @pba_num_size: part number string buffer length 1119 * 1120 * Reads the part number string from the EEPROM. 1121 **/ 1122 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1123 u32 pba_num_size) 1124 { 1125 i40e_status status = 0; 1126 u16 pba_word = 0; 1127 u16 pba_size = 0; 1128 u16 pba_ptr = 0; 1129 u16 i = 0; 1130 1131 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1132 if (status || (pba_word != 0xFAFA)) { 1133 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1134 return status; 1135 } 1136 1137 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1138 if (status) { 1139 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1140 return status; 1141 } 1142 1143 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1144 if (status) { 1145 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1146 return status; 1147 } 1148 1149 /* Subtract one to get PBA word count (PBA Size word is included in 1150 * total size) 1151 */ 1152 pba_size--; 1153 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1154 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1155 return I40E_ERR_PARAM; 1156 } 1157 1158 for (i = 0; i < pba_size; i++) { 1159 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1160 if (status) { 1161 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1162 return status; 1163 } 1164 1165 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1166 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1167 } 1168 pba_num[(pba_size * 2)] = '\0'; 1169 1170 return status; 1171 } 1172 1173 /** 1174 * i40e_get_media_type - Gets media type 1175 * @hw: pointer to the hardware structure 1176 **/ 1177 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1178 { 1179 enum i40e_media_type media; 1180 1181 switch (hw->phy.link_info.phy_type) { 1182 case I40E_PHY_TYPE_10GBASE_SR: 1183 case I40E_PHY_TYPE_10GBASE_LR: 1184 case I40E_PHY_TYPE_1000BASE_SX: 1185 case I40E_PHY_TYPE_1000BASE_LX: 1186 case I40E_PHY_TYPE_40GBASE_SR4: 1187 case I40E_PHY_TYPE_40GBASE_LR4: 1188 case I40E_PHY_TYPE_25GBASE_LR: 1189 case I40E_PHY_TYPE_25GBASE_SR: 1190 media = I40E_MEDIA_TYPE_FIBER; 1191 break; 1192 case I40E_PHY_TYPE_100BASE_TX: 1193 case I40E_PHY_TYPE_1000BASE_T: 1194 case I40E_PHY_TYPE_10GBASE_T: 1195 media = I40E_MEDIA_TYPE_BASET; 1196 break; 1197 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1198 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1199 case I40E_PHY_TYPE_10GBASE_CR1: 1200 case I40E_PHY_TYPE_40GBASE_CR4: 1201 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1202 case I40E_PHY_TYPE_40GBASE_AOC: 1203 case I40E_PHY_TYPE_10GBASE_AOC: 1204 case I40E_PHY_TYPE_25GBASE_CR: 1205 media = I40E_MEDIA_TYPE_DA; 1206 break; 1207 case I40E_PHY_TYPE_1000BASE_KX: 1208 case I40E_PHY_TYPE_10GBASE_KX4: 1209 case I40E_PHY_TYPE_10GBASE_KR: 1210 case I40E_PHY_TYPE_40GBASE_KR4: 1211 case I40E_PHY_TYPE_20GBASE_KR2: 1212 case I40E_PHY_TYPE_25GBASE_KR: 1213 media = I40E_MEDIA_TYPE_BACKPLANE; 1214 break; 1215 case I40E_PHY_TYPE_SGMII: 1216 case I40E_PHY_TYPE_XAUI: 1217 case I40E_PHY_TYPE_XFI: 1218 case I40E_PHY_TYPE_XLAUI: 1219 case I40E_PHY_TYPE_XLPPI: 1220 default: 1221 media = I40E_MEDIA_TYPE_UNKNOWN; 1222 break; 1223 } 1224 1225 return media; 1226 } 1227 1228 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1229 #define I40E_PF_RESET_WAIT_COUNT 200 1230 /** 1231 * i40e_pf_reset - Reset the PF 1232 * @hw: pointer to the hardware structure 1233 * 1234 * Assuming someone else has triggered a global reset, 1235 * assure the global reset is complete and then reset the PF 1236 **/ 1237 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1238 { 1239 u32 cnt = 0; 1240 u32 cnt1 = 0; 1241 u32 reg = 0; 1242 u32 grst_del; 1243 1244 /* Poll for Global Reset steady state in case of recent GRST. 1245 * The grst delay value is in 100ms units, and we'll wait a 1246 * couple counts longer to be sure we don't just miss the end. 1247 */ 1248 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1249 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1250 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1251 1252 /* It can take upto 15 secs for GRST steady state. 1253 * Bump it to 16 secs max to be safe. 1254 */ 1255 grst_del = grst_del * 20; 1256 1257 for (cnt = 0; cnt < grst_del; cnt++) { 1258 reg = rd32(hw, I40E_GLGEN_RSTAT); 1259 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1260 break; 1261 msleep(100); 1262 } 1263 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1264 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1265 return I40E_ERR_RESET_FAILED; 1266 } 1267 1268 /* Now Wait for the FW to be ready */ 1269 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1270 reg = rd32(hw, I40E_GLNVM_ULD); 1271 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1273 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1274 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1275 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1276 break; 1277 } 1278 usleep_range(10000, 20000); 1279 } 1280 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1281 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1282 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1283 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1284 return I40E_ERR_RESET_FAILED; 1285 } 1286 1287 /* If there was a Global Reset in progress when we got here, 1288 * we don't need to do the PF Reset 1289 */ 1290 if (!cnt) { 1291 if (hw->revision_id == 0) 1292 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1293 else 1294 cnt = I40E_PF_RESET_WAIT_COUNT; 1295 reg = rd32(hw, I40E_PFGEN_CTRL); 1296 wr32(hw, I40E_PFGEN_CTRL, 1297 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1298 for (; cnt; cnt--) { 1299 reg = rd32(hw, I40E_PFGEN_CTRL); 1300 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1301 break; 1302 usleep_range(1000, 2000); 1303 } 1304 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1305 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1306 return I40E_ERR_RESET_FAILED; 1307 } 1308 } 1309 1310 i40e_clear_pxe_mode(hw); 1311 1312 return 0; 1313 } 1314 1315 /** 1316 * i40e_clear_hw - clear out any left over hw state 1317 * @hw: pointer to the hw struct 1318 * 1319 * Clear queues and interrupts, typically called at init time, 1320 * but after the capabilities have been found so we know how many 1321 * queues and msix vectors have been allocated. 1322 **/ 1323 void i40e_clear_hw(struct i40e_hw *hw) 1324 { 1325 u32 num_queues, base_queue; 1326 u32 num_pf_int; 1327 u32 num_vf_int; 1328 u32 num_vfs; 1329 u32 i, j; 1330 u32 val; 1331 u32 eol = 0x7ff; 1332 1333 /* get number of interrupts, queues, and VFs */ 1334 val = rd32(hw, I40E_GLPCI_CNF2); 1335 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1336 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1337 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1338 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1339 1340 val = rd32(hw, I40E_PFLAN_QALLOC); 1341 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1342 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1343 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1344 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1345 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1346 num_queues = (j - base_queue) + 1; 1347 else 1348 num_queues = 0; 1349 1350 val = rd32(hw, I40E_PF_VT_PFALLOC); 1351 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1352 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1353 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1354 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1355 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1356 num_vfs = (j - i) + 1; 1357 else 1358 num_vfs = 0; 1359 1360 /* stop all the interrupts */ 1361 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1362 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1363 for (i = 0; i < num_pf_int - 2; i++) 1364 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1365 1366 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1367 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1368 wr32(hw, I40E_PFINT_LNKLST0, val); 1369 for (i = 0; i < num_pf_int - 2; i++) 1370 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1371 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1372 for (i = 0; i < num_vfs; i++) 1373 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1374 for (i = 0; i < num_vf_int - 2; i++) 1375 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1376 1377 /* warn the HW of the coming Tx disables */ 1378 for (i = 0; i < num_queues; i++) { 1379 u32 abs_queue_idx = base_queue + i; 1380 u32 reg_block = 0; 1381 1382 if (abs_queue_idx >= 128) { 1383 reg_block = abs_queue_idx / 128; 1384 abs_queue_idx %= 128; 1385 } 1386 1387 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1388 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1389 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1390 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1391 1392 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1393 } 1394 udelay(400); 1395 1396 /* stop all the queues */ 1397 for (i = 0; i < num_queues; i++) { 1398 wr32(hw, I40E_QINT_TQCTL(i), 0); 1399 wr32(hw, I40E_QTX_ENA(i), 0); 1400 wr32(hw, I40E_QINT_RQCTL(i), 0); 1401 wr32(hw, I40E_QRX_ENA(i), 0); 1402 } 1403 1404 /* short wait for all queue disables to settle */ 1405 udelay(50); 1406 } 1407 1408 /** 1409 * i40e_clear_pxe_mode - clear pxe operations mode 1410 * @hw: pointer to the hw struct 1411 * 1412 * Make sure all PXE mode settings are cleared, including things 1413 * like descriptor fetch/write-back mode. 1414 **/ 1415 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1416 { 1417 u32 reg; 1418 1419 if (i40e_check_asq_alive(hw)) 1420 i40e_aq_clear_pxe_mode(hw, NULL); 1421 1422 /* Clear single descriptor fetch/write-back mode */ 1423 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1424 1425 if (hw->revision_id == 0) { 1426 /* As a work around clear PXE_MODE instead of setting it */ 1427 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1428 } else { 1429 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1430 } 1431 } 1432 1433 /** 1434 * i40e_led_is_mine - helper to find matching led 1435 * @hw: pointer to the hw struct 1436 * @idx: index into GPIO registers 1437 * 1438 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1439 */ 1440 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1441 { 1442 u32 gpio_val = 0; 1443 u32 port; 1444 1445 if (!hw->func_caps.led[idx]) 1446 return 0; 1447 1448 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1449 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1450 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1451 1452 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1453 * if it is not our port then ignore 1454 */ 1455 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1456 (port != hw->port)) 1457 return 0; 1458 1459 return gpio_val; 1460 } 1461 1462 #define I40E_COMBINED_ACTIVITY 0xA 1463 #define I40E_FILTER_ACTIVITY 0xE 1464 #define I40E_LINK_ACTIVITY 0xC 1465 #define I40E_MAC_ACTIVITY 0xD 1466 #define I40E_LED0 22 1467 1468 /** 1469 * i40e_led_get - return current on/off mode 1470 * @hw: pointer to the hw struct 1471 * 1472 * The value returned is the 'mode' field as defined in the 1473 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1474 * values are variations of possible behaviors relating to 1475 * blink, link, and wire. 1476 **/ 1477 u32 i40e_led_get(struct i40e_hw *hw) 1478 { 1479 u32 current_mode = 0; 1480 u32 mode = 0; 1481 int i; 1482 1483 /* as per the documentation GPIO 22-29 are the LED 1484 * GPIO pins named LED0..LED7 1485 */ 1486 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1487 u32 gpio_val = i40e_led_is_mine(hw, i); 1488 1489 if (!gpio_val) 1490 continue; 1491 1492 /* ignore gpio LED src mode entries related to the activity 1493 * LEDs 1494 */ 1495 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1496 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1497 switch (current_mode) { 1498 case I40E_COMBINED_ACTIVITY: 1499 case I40E_FILTER_ACTIVITY: 1500 case I40E_MAC_ACTIVITY: 1501 continue; 1502 default: 1503 break; 1504 } 1505 1506 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1507 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1508 break; 1509 } 1510 1511 return mode; 1512 } 1513 1514 /** 1515 * i40e_led_set - set new on/off mode 1516 * @hw: pointer to the hw struct 1517 * @mode: 0=off, 0xf=on (else see manual for mode details) 1518 * @blink: true if the LED should blink when on, false if steady 1519 * 1520 * if this function is used to turn on the blink it should 1521 * be used to disable the blink when restoring the original state. 1522 **/ 1523 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1524 { 1525 u32 current_mode = 0; 1526 int i; 1527 1528 if (mode & 0xfffffff0) 1529 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1530 1531 /* as per the documentation GPIO 22-29 are the LED 1532 * GPIO pins named LED0..LED7 1533 */ 1534 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1535 u32 gpio_val = i40e_led_is_mine(hw, i); 1536 1537 if (!gpio_val) 1538 continue; 1539 1540 /* ignore gpio LED src mode entries related to the activity 1541 * LEDs 1542 */ 1543 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1544 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1545 switch (current_mode) { 1546 case I40E_COMBINED_ACTIVITY: 1547 case I40E_FILTER_ACTIVITY: 1548 case I40E_MAC_ACTIVITY: 1549 continue; 1550 default: 1551 break; 1552 } 1553 1554 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1555 /* this & is a bit of paranoia, but serves as a range check */ 1556 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1557 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1558 1559 if (mode == I40E_LINK_ACTIVITY) 1560 blink = false; 1561 1562 if (blink) 1563 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1564 else 1565 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1566 1567 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1568 break; 1569 } 1570 } 1571 1572 /* Admin command wrappers */ 1573 1574 /** 1575 * i40e_aq_get_phy_capabilities 1576 * @hw: pointer to the hw struct 1577 * @abilities: structure for PHY capabilities to be filled 1578 * @qualified_modules: report Qualified Modules 1579 * @report_init: report init capabilities (active are default) 1580 * @cmd_details: pointer to command details structure or NULL 1581 * 1582 * Returns the various PHY abilities supported on the Port. 1583 **/ 1584 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1585 bool qualified_modules, bool report_init, 1586 struct i40e_aq_get_phy_abilities_resp *abilities, 1587 struct i40e_asq_cmd_details *cmd_details) 1588 { 1589 struct i40e_aq_desc desc; 1590 i40e_status status; 1591 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1592 1593 if (!abilities) 1594 return I40E_ERR_PARAM; 1595 1596 i40e_fill_default_direct_cmd_desc(&desc, 1597 i40e_aqc_opc_get_phy_abilities); 1598 1599 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1600 if (abilities_size > I40E_AQ_LARGE_BUF) 1601 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1602 1603 if (qualified_modules) 1604 desc.params.external.param0 |= 1605 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1606 1607 if (report_init) 1608 desc.params.external.param0 |= 1609 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1610 1611 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1612 cmd_details); 1613 1614 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1615 status = I40E_ERR_UNKNOWN_PHY; 1616 1617 if (report_init) { 1618 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1619 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); 1620 } 1621 1622 return status; 1623 } 1624 1625 /** 1626 * i40e_aq_set_phy_config 1627 * @hw: pointer to the hw struct 1628 * @config: structure with PHY configuration to be set 1629 * @cmd_details: pointer to command details structure or NULL 1630 * 1631 * Set the various PHY configuration parameters 1632 * supported on the Port.One or more of the Set PHY config parameters may be 1633 * ignored in an MFP mode as the PF may not have the privilege to set some 1634 * of the PHY Config parameters. This status will be indicated by the 1635 * command response. 1636 **/ 1637 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1638 struct i40e_aq_set_phy_config *config, 1639 struct i40e_asq_cmd_details *cmd_details) 1640 { 1641 struct i40e_aq_desc desc; 1642 struct i40e_aq_set_phy_config *cmd = 1643 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1644 enum i40e_status_code status; 1645 1646 if (!config) 1647 return I40E_ERR_PARAM; 1648 1649 i40e_fill_default_direct_cmd_desc(&desc, 1650 i40e_aqc_opc_set_phy_config); 1651 1652 *cmd = *config; 1653 1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1655 1656 return status; 1657 } 1658 1659 /** 1660 * i40e_set_fc 1661 * @hw: pointer to the hw struct 1662 * 1663 * Set the requested flow control mode using set_phy_config. 1664 **/ 1665 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1666 bool atomic_restart) 1667 { 1668 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1669 struct i40e_aq_get_phy_abilities_resp abilities; 1670 struct i40e_aq_set_phy_config config; 1671 enum i40e_status_code status; 1672 u8 pause_mask = 0x0; 1673 1674 *aq_failures = 0x0; 1675 1676 switch (fc_mode) { 1677 case I40E_FC_FULL: 1678 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1679 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1680 break; 1681 case I40E_FC_RX_PAUSE: 1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1683 break; 1684 case I40E_FC_TX_PAUSE: 1685 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1686 break; 1687 default: 1688 break; 1689 } 1690 1691 /* Get the current phy config */ 1692 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1693 NULL); 1694 if (status) { 1695 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1696 return status; 1697 } 1698 1699 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1700 /* clear the old pause settings */ 1701 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1702 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1703 /* set the new abilities */ 1704 config.abilities |= pause_mask; 1705 /* If the abilities have changed, then set the new config */ 1706 if (config.abilities != abilities.abilities) { 1707 /* Auto restart link so settings take effect */ 1708 if (atomic_restart) 1709 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1710 /* Copy over all the old settings */ 1711 config.phy_type = abilities.phy_type; 1712 config.phy_type_ext = abilities.phy_type_ext; 1713 config.link_speed = abilities.link_speed; 1714 config.eee_capability = abilities.eee_capability; 1715 config.eeer = abilities.eeer_val; 1716 config.low_power_ctrl = abilities.d3_lpan; 1717 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1718 I40E_AQ_PHY_FEC_CONFIG_MASK; 1719 status = i40e_aq_set_phy_config(hw, &config, NULL); 1720 1721 if (status) 1722 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1723 } 1724 /* Update the link info */ 1725 status = i40e_update_link_info(hw); 1726 if (status) { 1727 /* Wait a little bit (on 40G cards it sometimes takes a really 1728 * long time for link to come back from the atomic reset) 1729 * and try once more 1730 */ 1731 msleep(1000); 1732 status = i40e_update_link_info(hw); 1733 } 1734 if (status) 1735 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1736 1737 return status; 1738 } 1739 1740 /** 1741 * i40e_aq_clear_pxe_mode 1742 * @hw: pointer to the hw struct 1743 * @cmd_details: pointer to command details structure or NULL 1744 * 1745 * Tell the firmware that the driver is taking over from PXE 1746 **/ 1747 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1748 struct i40e_asq_cmd_details *cmd_details) 1749 { 1750 i40e_status status; 1751 struct i40e_aq_desc desc; 1752 struct i40e_aqc_clear_pxe *cmd = 1753 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1754 1755 i40e_fill_default_direct_cmd_desc(&desc, 1756 i40e_aqc_opc_clear_pxe_mode); 1757 1758 cmd->rx_cnt = 0x2; 1759 1760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1761 1762 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1763 1764 return status; 1765 } 1766 1767 /** 1768 * i40e_aq_set_link_restart_an 1769 * @hw: pointer to the hw struct 1770 * @enable_link: if true: enable link, if false: disable link 1771 * @cmd_details: pointer to command details structure or NULL 1772 * 1773 * Sets up the link and restarts the Auto-Negotiation over the link. 1774 **/ 1775 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1776 bool enable_link, 1777 struct i40e_asq_cmd_details *cmd_details) 1778 { 1779 struct i40e_aq_desc desc; 1780 struct i40e_aqc_set_link_restart_an *cmd = 1781 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1782 i40e_status status; 1783 1784 i40e_fill_default_direct_cmd_desc(&desc, 1785 i40e_aqc_opc_set_link_restart_an); 1786 1787 cmd->command = I40E_AQ_PHY_RESTART_AN; 1788 if (enable_link) 1789 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1790 else 1791 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1792 1793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1794 1795 return status; 1796 } 1797 1798 /** 1799 * i40e_aq_get_link_info 1800 * @hw: pointer to the hw struct 1801 * @enable_lse: enable/disable LinkStatusEvent reporting 1802 * @link: pointer to link status structure - optional 1803 * @cmd_details: pointer to command details structure or NULL 1804 * 1805 * Returns the link status of the adapter. 1806 **/ 1807 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1808 bool enable_lse, struct i40e_link_status *link, 1809 struct i40e_asq_cmd_details *cmd_details) 1810 { 1811 struct i40e_aq_desc desc; 1812 struct i40e_aqc_get_link_status *resp = 1813 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1814 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1815 i40e_status status; 1816 bool tx_pause, rx_pause; 1817 u16 command_flags; 1818 1819 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1820 1821 if (enable_lse) 1822 command_flags = I40E_AQ_LSE_ENABLE; 1823 else 1824 command_flags = I40E_AQ_LSE_DISABLE; 1825 resp->command_flags = cpu_to_le16(command_flags); 1826 1827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1828 1829 if (status) 1830 goto aq_get_link_info_exit; 1831 1832 /* save off old link status information */ 1833 hw->phy.link_info_old = *hw_link_info; 1834 1835 /* update link status */ 1836 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1837 hw->phy.media_type = i40e_get_media_type(hw); 1838 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1839 hw_link_info->link_info = resp->link_info; 1840 hw_link_info->an_info = resp->an_info; 1841 hw_link_info->ext_info = resp->ext_info; 1842 hw_link_info->loopback = resp->loopback; 1843 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1844 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1845 1846 /* update fc info */ 1847 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1848 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1849 if (tx_pause & rx_pause) 1850 hw->fc.current_mode = I40E_FC_FULL; 1851 else if (tx_pause) 1852 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1853 else if (rx_pause) 1854 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1855 else 1856 hw->fc.current_mode = I40E_FC_NONE; 1857 1858 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1859 hw_link_info->crc_enable = true; 1860 else 1861 hw_link_info->crc_enable = false; 1862 1863 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1864 hw_link_info->lse_enable = true; 1865 else 1866 hw_link_info->lse_enable = false; 1867 1868 if ((hw->mac.type == I40E_MAC_XL710) && 1869 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1870 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1871 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1872 1873 /* save link status information */ 1874 if (link) 1875 *link = *hw_link_info; 1876 1877 /* flag cleared so helper functions don't call AQ again */ 1878 hw->phy.get_link_info = false; 1879 1880 aq_get_link_info_exit: 1881 return status; 1882 } 1883 1884 /** 1885 * i40e_aq_set_phy_int_mask 1886 * @hw: pointer to the hw struct 1887 * @mask: interrupt mask to be set 1888 * @cmd_details: pointer to command details structure or NULL 1889 * 1890 * Set link interrupt mask. 1891 **/ 1892 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1893 u16 mask, 1894 struct i40e_asq_cmd_details *cmd_details) 1895 { 1896 struct i40e_aq_desc desc; 1897 struct i40e_aqc_set_phy_int_mask *cmd = 1898 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1899 i40e_status status; 1900 1901 i40e_fill_default_direct_cmd_desc(&desc, 1902 i40e_aqc_opc_set_phy_int_mask); 1903 1904 cmd->event_mask = cpu_to_le16(mask); 1905 1906 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1907 1908 return status; 1909 } 1910 1911 /** 1912 * i40e_aq_set_phy_debug 1913 * @hw: pointer to the hw struct 1914 * @cmd_flags: debug command flags 1915 * @cmd_details: pointer to command details structure or NULL 1916 * 1917 * Reset the external PHY. 1918 **/ 1919 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1920 struct i40e_asq_cmd_details *cmd_details) 1921 { 1922 struct i40e_aq_desc desc; 1923 struct i40e_aqc_set_phy_debug *cmd = 1924 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1925 i40e_status status; 1926 1927 i40e_fill_default_direct_cmd_desc(&desc, 1928 i40e_aqc_opc_set_phy_debug); 1929 1930 cmd->command_flags = cmd_flags; 1931 1932 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1933 1934 return status; 1935 } 1936 1937 /** 1938 * i40e_aq_add_vsi 1939 * @hw: pointer to the hw struct 1940 * @vsi_ctx: pointer to a vsi context struct 1941 * @cmd_details: pointer to command details structure or NULL 1942 * 1943 * Add a VSI context to the hardware. 1944 **/ 1945 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1946 struct i40e_vsi_context *vsi_ctx, 1947 struct i40e_asq_cmd_details *cmd_details) 1948 { 1949 struct i40e_aq_desc desc; 1950 struct i40e_aqc_add_get_update_vsi *cmd = 1951 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1952 struct i40e_aqc_add_get_update_vsi_completion *resp = 1953 (struct i40e_aqc_add_get_update_vsi_completion *) 1954 &desc.params.raw; 1955 i40e_status status; 1956 1957 i40e_fill_default_direct_cmd_desc(&desc, 1958 i40e_aqc_opc_add_vsi); 1959 1960 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1961 cmd->connection_type = vsi_ctx->connection_type; 1962 cmd->vf_id = vsi_ctx->vf_num; 1963 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1964 1965 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1966 1967 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1968 sizeof(vsi_ctx->info), cmd_details); 1969 1970 if (status) 1971 goto aq_add_vsi_exit; 1972 1973 vsi_ctx->seid = le16_to_cpu(resp->seid); 1974 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1975 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1976 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1977 1978 aq_add_vsi_exit: 1979 return status; 1980 } 1981 1982 /** 1983 * i40e_aq_set_default_vsi 1984 * @hw: pointer to the hw struct 1985 * @seid: vsi number 1986 * @cmd_details: pointer to command details structure or NULL 1987 **/ 1988 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 1989 u16 seid, 1990 struct i40e_asq_cmd_details *cmd_details) 1991 { 1992 struct i40e_aq_desc desc; 1993 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1994 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1995 &desc.params.raw; 1996 i40e_status status; 1997 1998 i40e_fill_default_direct_cmd_desc(&desc, 1999 i40e_aqc_opc_set_vsi_promiscuous_modes); 2000 2001 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2002 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2003 cmd->seid = cpu_to_le16(seid); 2004 2005 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2006 2007 return status; 2008 } 2009 2010 /** 2011 * i40e_aq_clear_default_vsi 2012 * @hw: pointer to the hw struct 2013 * @seid: vsi number 2014 * @cmd_details: pointer to command details structure or NULL 2015 **/ 2016 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2017 u16 seid, 2018 struct i40e_asq_cmd_details *cmd_details) 2019 { 2020 struct i40e_aq_desc desc; 2021 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2022 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2023 &desc.params.raw; 2024 i40e_status status; 2025 2026 i40e_fill_default_direct_cmd_desc(&desc, 2027 i40e_aqc_opc_set_vsi_promiscuous_modes); 2028 2029 cmd->promiscuous_flags = cpu_to_le16(0); 2030 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2031 cmd->seid = cpu_to_le16(seid); 2032 2033 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2034 2035 return status; 2036 } 2037 2038 /** 2039 * i40e_aq_set_vsi_unicast_promiscuous 2040 * @hw: pointer to the hw struct 2041 * @seid: vsi number 2042 * @set: set unicast promiscuous enable/disable 2043 * @cmd_details: pointer to command details structure or NULL 2044 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2045 **/ 2046 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2047 u16 seid, bool set, 2048 struct i40e_asq_cmd_details *cmd_details, 2049 bool rx_only_promisc) 2050 { 2051 struct i40e_aq_desc desc; 2052 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2053 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2054 i40e_status status; 2055 u16 flags = 0; 2056 2057 i40e_fill_default_direct_cmd_desc(&desc, 2058 i40e_aqc_opc_set_vsi_promiscuous_modes); 2059 2060 if (set) { 2061 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2062 if (rx_only_promisc && 2063 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2064 (hw->aq.api_maj_ver > 1))) 2065 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2066 } 2067 2068 cmd->promiscuous_flags = cpu_to_le16(flags); 2069 2070 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2071 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2072 (hw->aq.api_maj_ver > 1)) 2073 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2074 2075 cmd->seid = cpu_to_le16(seid); 2076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2077 2078 return status; 2079 } 2080 2081 /** 2082 * i40e_aq_set_vsi_multicast_promiscuous 2083 * @hw: pointer to the hw struct 2084 * @seid: vsi number 2085 * @set: set multicast promiscuous enable/disable 2086 * @cmd_details: pointer to command details structure or NULL 2087 **/ 2088 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2089 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2090 { 2091 struct i40e_aq_desc desc; 2092 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2093 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2094 i40e_status status; 2095 u16 flags = 0; 2096 2097 i40e_fill_default_direct_cmd_desc(&desc, 2098 i40e_aqc_opc_set_vsi_promiscuous_modes); 2099 2100 if (set) 2101 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2102 2103 cmd->promiscuous_flags = cpu_to_le16(flags); 2104 2105 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2106 2107 cmd->seid = cpu_to_le16(seid); 2108 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2109 2110 return status; 2111 } 2112 2113 /** 2114 * i40e_aq_set_vsi_mc_promisc_on_vlan 2115 * @hw: pointer to the hw struct 2116 * @seid: vsi number 2117 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2118 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2119 * @cmd_details: pointer to command details structure or NULL 2120 **/ 2121 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2122 u16 seid, bool enable, 2123 u16 vid, 2124 struct i40e_asq_cmd_details *cmd_details) 2125 { 2126 struct i40e_aq_desc desc; 2127 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2128 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2129 enum i40e_status_code status; 2130 u16 flags = 0; 2131 2132 i40e_fill_default_direct_cmd_desc(&desc, 2133 i40e_aqc_opc_set_vsi_promiscuous_modes); 2134 2135 if (enable) 2136 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2137 2138 cmd->promiscuous_flags = cpu_to_le16(flags); 2139 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2140 cmd->seid = cpu_to_le16(seid); 2141 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2142 2143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2144 2145 return status; 2146 } 2147 2148 /** 2149 * i40e_aq_set_vsi_uc_promisc_on_vlan 2150 * @hw: pointer to the hw struct 2151 * @seid: vsi number 2152 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2153 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2154 * @cmd_details: pointer to command details structure or NULL 2155 **/ 2156 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2157 u16 seid, bool enable, 2158 u16 vid, 2159 struct i40e_asq_cmd_details *cmd_details) 2160 { 2161 struct i40e_aq_desc desc; 2162 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2163 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2164 enum i40e_status_code status; 2165 u16 flags = 0; 2166 2167 i40e_fill_default_direct_cmd_desc(&desc, 2168 i40e_aqc_opc_set_vsi_promiscuous_modes); 2169 2170 if (enable) 2171 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2172 2173 cmd->promiscuous_flags = cpu_to_le16(flags); 2174 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2175 cmd->seid = cpu_to_le16(seid); 2176 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2177 2178 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2179 2180 return status; 2181 } 2182 2183 /** 2184 * i40e_aq_set_vsi_bc_promisc_on_vlan 2185 * @hw: pointer to the hw struct 2186 * @seid: vsi number 2187 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2188 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2189 * @cmd_details: pointer to command details structure or NULL 2190 **/ 2191 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2192 u16 seid, bool enable, u16 vid, 2193 struct i40e_asq_cmd_details *cmd_details) 2194 { 2195 struct i40e_aq_desc desc; 2196 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2197 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2198 i40e_status status; 2199 u16 flags = 0; 2200 2201 i40e_fill_default_direct_cmd_desc(&desc, 2202 i40e_aqc_opc_set_vsi_promiscuous_modes); 2203 2204 if (enable) 2205 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2206 2207 cmd->promiscuous_flags = cpu_to_le16(flags); 2208 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2209 cmd->seid = cpu_to_le16(seid); 2210 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2211 2212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2213 2214 return status; 2215 } 2216 2217 /** 2218 * i40e_aq_set_vsi_broadcast 2219 * @hw: pointer to the hw struct 2220 * @seid: vsi number 2221 * @set_filter: true to set filter, false to clear filter 2222 * @cmd_details: pointer to command details structure or NULL 2223 * 2224 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2225 **/ 2226 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2227 u16 seid, bool set_filter, 2228 struct i40e_asq_cmd_details *cmd_details) 2229 { 2230 struct i40e_aq_desc desc; 2231 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2232 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2233 i40e_status status; 2234 2235 i40e_fill_default_direct_cmd_desc(&desc, 2236 i40e_aqc_opc_set_vsi_promiscuous_modes); 2237 2238 if (set_filter) 2239 cmd->promiscuous_flags 2240 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2241 else 2242 cmd->promiscuous_flags 2243 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2244 2245 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2246 cmd->seid = cpu_to_le16(seid); 2247 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2248 2249 return status; 2250 } 2251 2252 /** 2253 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2254 * @hw: pointer to the hw struct 2255 * @seid: vsi number 2256 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2257 * @cmd_details: pointer to command details structure or NULL 2258 **/ 2259 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2260 u16 seid, bool enable, 2261 struct i40e_asq_cmd_details *cmd_details) 2262 { 2263 struct i40e_aq_desc desc; 2264 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2265 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2266 i40e_status status; 2267 u16 flags = 0; 2268 2269 i40e_fill_default_direct_cmd_desc(&desc, 2270 i40e_aqc_opc_set_vsi_promiscuous_modes); 2271 if (enable) 2272 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2273 2274 cmd->promiscuous_flags = cpu_to_le16(flags); 2275 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2276 cmd->seid = cpu_to_le16(seid); 2277 2278 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2279 2280 return status; 2281 } 2282 2283 /** 2284 * i40e_get_vsi_params - get VSI configuration info 2285 * @hw: pointer to the hw struct 2286 * @vsi_ctx: pointer to a vsi context struct 2287 * @cmd_details: pointer to command details structure or NULL 2288 **/ 2289 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2290 struct i40e_vsi_context *vsi_ctx, 2291 struct i40e_asq_cmd_details *cmd_details) 2292 { 2293 struct i40e_aq_desc desc; 2294 struct i40e_aqc_add_get_update_vsi *cmd = 2295 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2296 struct i40e_aqc_add_get_update_vsi_completion *resp = 2297 (struct i40e_aqc_add_get_update_vsi_completion *) 2298 &desc.params.raw; 2299 i40e_status status; 2300 2301 i40e_fill_default_direct_cmd_desc(&desc, 2302 i40e_aqc_opc_get_vsi_parameters); 2303 2304 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2305 2306 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2307 2308 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2309 sizeof(vsi_ctx->info), NULL); 2310 2311 if (status) 2312 goto aq_get_vsi_params_exit; 2313 2314 vsi_ctx->seid = le16_to_cpu(resp->seid); 2315 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2316 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2317 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2318 2319 aq_get_vsi_params_exit: 2320 return status; 2321 } 2322 2323 /** 2324 * i40e_aq_update_vsi_params 2325 * @hw: pointer to the hw struct 2326 * @vsi_ctx: pointer to a vsi context struct 2327 * @cmd_details: pointer to command details structure or NULL 2328 * 2329 * Update a VSI context. 2330 **/ 2331 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2332 struct i40e_vsi_context *vsi_ctx, 2333 struct i40e_asq_cmd_details *cmd_details) 2334 { 2335 struct i40e_aq_desc desc; 2336 struct i40e_aqc_add_get_update_vsi *cmd = 2337 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2338 struct i40e_aqc_add_get_update_vsi_completion *resp = 2339 (struct i40e_aqc_add_get_update_vsi_completion *) 2340 &desc.params.raw; 2341 i40e_status status; 2342 2343 i40e_fill_default_direct_cmd_desc(&desc, 2344 i40e_aqc_opc_update_vsi_parameters); 2345 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2346 2347 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2348 2349 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2350 sizeof(vsi_ctx->info), cmd_details); 2351 2352 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2353 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2354 2355 return status; 2356 } 2357 2358 /** 2359 * i40e_aq_get_switch_config 2360 * @hw: pointer to the hardware structure 2361 * @buf: pointer to the result buffer 2362 * @buf_size: length of input buffer 2363 * @start_seid: seid to start for the report, 0 == beginning 2364 * @cmd_details: pointer to command details structure or NULL 2365 * 2366 * Fill the buf with switch configuration returned from AdminQ command 2367 **/ 2368 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2369 struct i40e_aqc_get_switch_config_resp *buf, 2370 u16 buf_size, u16 *start_seid, 2371 struct i40e_asq_cmd_details *cmd_details) 2372 { 2373 struct i40e_aq_desc desc; 2374 struct i40e_aqc_switch_seid *scfg = 2375 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2376 i40e_status status; 2377 2378 i40e_fill_default_direct_cmd_desc(&desc, 2379 i40e_aqc_opc_get_switch_config); 2380 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2381 if (buf_size > I40E_AQ_LARGE_BUF) 2382 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2383 scfg->seid = cpu_to_le16(*start_seid); 2384 2385 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2386 *start_seid = le16_to_cpu(scfg->seid); 2387 2388 return status; 2389 } 2390 2391 /** 2392 * i40e_aq_set_switch_config 2393 * @hw: pointer to the hardware structure 2394 * @flags: bit flag values to set 2395 * @valid_flags: which bit flags to set 2396 * @cmd_details: pointer to command details structure or NULL 2397 * 2398 * Set switch configuration bits 2399 **/ 2400 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2401 u16 flags, 2402 u16 valid_flags, 2403 struct i40e_asq_cmd_details *cmd_details) 2404 { 2405 struct i40e_aq_desc desc; 2406 struct i40e_aqc_set_switch_config *scfg = 2407 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2408 enum i40e_status_code status; 2409 2410 i40e_fill_default_direct_cmd_desc(&desc, 2411 i40e_aqc_opc_set_switch_config); 2412 scfg->flags = cpu_to_le16(flags); 2413 scfg->valid_flags = cpu_to_le16(valid_flags); 2414 2415 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2416 2417 return status; 2418 } 2419 2420 /** 2421 * i40e_aq_get_firmware_version 2422 * @hw: pointer to the hw struct 2423 * @fw_major_version: firmware major version 2424 * @fw_minor_version: firmware minor version 2425 * @fw_build: firmware build number 2426 * @api_major_version: major queue version 2427 * @api_minor_version: minor queue version 2428 * @cmd_details: pointer to command details structure or NULL 2429 * 2430 * Get the firmware version from the admin queue commands 2431 **/ 2432 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2433 u16 *fw_major_version, u16 *fw_minor_version, 2434 u32 *fw_build, 2435 u16 *api_major_version, u16 *api_minor_version, 2436 struct i40e_asq_cmd_details *cmd_details) 2437 { 2438 struct i40e_aq_desc desc; 2439 struct i40e_aqc_get_version *resp = 2440 (struct i40e_aqc_get_version *)&desc.params.raw; 2441 i40e_status status; 2442 2443 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2444 2445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2446 2447 if (!status) { 2448 if (fw_major_version) 2449 *fw_major_version = le16_to_cpu(resp->fw_major); 2450 if (fw_minor_version) 2451 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2452 if (fw_build) 2453 *fw_build = le32_to_cpu(resp->fw_build); 2454 if (api_major_version) 2455 *api_major_version = le16_to_cpu(resp->api_major); 2456 if (api_minor_version) 2457 *api_minor_version = le16_to_cpu(resp->api_minor); 2458 } 2459 2460 return status; 2461 } 2462 2463 /** 2464 * i40e_aq_send_driver_version 2465 * @hw: pointer to the hw struct 2466 * @dv: driver's major, minor version 2467 * @cmd_details: pointer to command details structure or NULL 2468 * 2469 * Send the driver version to the firmware 2470 **/ 2471 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2472 struct i40e_driver_version *dv, 2473 struct i40e_asq_cmd_details *cmd_details) 2474 { 2475 struct i40e_aq_desc desc; 2476 struct i40e_aqc_driver_version *cmd = 2477 (struct i40e_aqc_driver_version *)&desc.params.raw; 2478 i40e_status status; 2479 u16 len; 2480 2481 if (dv == NULL) 2482 return I40E_ERR_PARAM; 2483 2484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2485 2486 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2487 cmd->driver_major_ver = dv->major_version; 2488 cmd->driver_minor_ver = dv->minor_version; 2489 cmd->driver_build_ver = dv->build_version; 2490 cmd->driver_subbuild_ver = dv->subbuild_version; 2491 2492 len = 0; 2493 while (len < sizeof(dv->driver_string) && 2494 (dv->driver_string[len] < 0x80) && 2495 dv->driver_string[len]) 2496 len++; 2497 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2498 len, cmd_details); 2499 2500 return status; 2501 } 2502 2503 /** 2504 * i40e_get_link_status - get status of the HW network link 2505 * @hw: pointer to the hw struct 2506 * @link_up: pointer to bool (true/false = linkup/linkdown) 2507 * 2508 * Variable link_up true if link is up, false if link is down. 2509 * The variable link_up is invalid if returned value of status != 0 2510 * 2511 * Side effect: LinkStatusEvent reporting becomes enabled 2512 **/ 2513 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2514 { 2515 i40e_status status = 0; 2516 2517 if (hw->phy.get_link_info) { 2518 status = i40e_update_link_info(hw); 2519 2520 if (status) 2521 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2522 status); 2523 } 2524 2525 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2526 2527 return status; 2528 } 2529 2530 /** 2531 * i40e_updatelink_status - update status of the HW network link 2532 * @hw: pointer to the hw struct 2533 **/ 2534 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2535 { 2536 struct i40e_aq_get_phy_abilities_resp abilities; 2537 i40e_status status = 0; 2538 2539 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2540 if (status) 2541 return status; 2542 2543 /* extra checking needed to ensure link info to user is timely */ 2544 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2545 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2546 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2547 status = i40e_aq_get_phy_capabilities(hw, false, false, 2548 &abilities, NULL); 2549 if (status) 2550 return status; 2551 2552 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2553 sizeof(hw->phy.link_info.module_type)); 2554 } 2555 2556 return status; 2557 } 2558 2559 /** 2560 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2561 * @hw: pointer to the hw struct 2562 * @uplink_seid: the MAC or other gizmo SEID 2563 * @downlink_seid: the VSI SEID 2564 * @enabled_tc: bitmap of TCs to be enabled 2565 * @default_port: true for default port VSI, false for control port 2566 * @veb_seid: pointer to where to put the resulting VEB SEID 2567 * @enable_stats: true to turn on VEB stats 2568 * @cmd_details: pointer to command details structure or NULL 2569 * 2570 * This asks the FW to add a VEB between the uplink and downlink 2571 * elements. If the uplink SEID is 0, this will be a floating VEB. 2572 **/ 2573 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2574 u16 downlink_seid, u8 enabled_tc, 2575 bool default_port, u16 *veb_seid, 2576 bool enable_stats, 2577 struct i40e_asq_cmd_details *cmd_details) 2578 { 2579 struct i40e_aq_desc desc; 2580 struct i40e_aqc_add_veb *cmd = 2581 (struct i40e_aqc_add_veb *)&desc.params.raw; 2582 struct i40e_aqc_add_veb_completion *resp = 2583 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2584 i40e_status status; 2585 u16 veb_flags = 0; 2586 2587 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2588 if (!!uplink_seid != !!downlink_seid) 2589 return I40E_ERR_PARAM; 2590 2591 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2592 2593 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2594 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2595 cmd->enable_tcs = enabled_tc; 2596 if (!uplink_seid) 2597 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2598 if (default_port) 2599 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2600 else 2601 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2602 2603 /* reverse logic here: set the bitflag to disable the stats */ 2604 if (!enable_stats) 2605 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2606 2607 cmd->veb_flags = cpu_to_le16(veb_flags); 2608 2609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2610 2611 if (!status && veb_seid) 2612 *veb_seid = le16_to_cpu(resp->veb_seid); 2613 2614 return status; 2615 } 2616 2617 /** 2618 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2619 * @hw: pointer to the hw struct 2620 * @veb_seid: the SEID of the VEB to query 2621 * @switch_id: the uplink switch id 2622 * @floating: set to true if the VEB is floating 2623 * @statistic_index: index of the stats counter block for this VEB 2624 * @vebs_used: number of VEB's used by function 2625 * @vebs_free: total VEB's not reserved by any function 2626 * @cmd_details: pointer to command details structure or NULL 2627 * 2628 * This retrieves the parameters for a particular VEB, specified by 2629 * uplink_seid, and returns them to the caller. 2630 **/ 2631 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2632 u16 veb_seid, u16 *switch_id, 2633 bool *floating, u16 *statistic_index, 2634 u16 *vebs_used, u16 *vebs_free, 2635 struct i40e_asq_cmd_details *cmd_details) 2636 { 2637 struct i40e_aq_desc desc; 2638 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2639 (struct i40e_aqc_get_veb_parameters_completion *) 2640 &desc.params.raw; 2641 i40e_status status; 2642 2643 if (veb_seid == 0) 2644 return I40E_ERR_PARAM; 2645 2646 i40e_fill_default_direct_cmd_desc(&desc, 2647 i40e_aqc_opc_get_veb_parameters); 2648 cmd_resp->seid = cpu_to_le16(veb_seid); 2649 2650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2651 if (status) 2652 goto get_veb_exit; 2653 2654 if (switch_id) 2655 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2656 if (statistic_index) 2657 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2658 if (vebs_used) 2659 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2660 if (vebs_free) 2661 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2662 if (floating) { 2663 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2664 2665 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2666 *floating = true; 2667 else 2668 *floating = false; 2669 } 2670 2671 get_veb_exit: 2672 return status; 2673 } 2674 2675 /** 2676 * i40e_aq_add_macvlan 2677 * @hw: pointer to the hw struct 2678 * @seid: VSI for the mac address 2679 * @mv_list: list of macvlans to be added 2680 * @count: length of the list 2681 * @cmd_details: pointer to command details structure or NULL 2682 * 2683 * Add MAC/VLAN addresses to the HW filtering 2684 **/ 2685 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2686 struct i40e_aqc_add_macvlan_element_data *mv_list, 2687 u16 count, struct i40e_asq_cmd_details *cmd_details) 2688 { 2689 struct i40e_aq_desc desc; 2690 struct i40e_aqc_macvlan *cmd = 2691 (struct i40e_aqc_macvlan *)&desc.params.raw; 2692 i40e_status status; 2693 u16 buf_size; 2694 int i; 2695 2696 if (count == 0 || !mv_list || !hw) 2697 return I40E_ERR_PARAM; 2698 2699 buf_size = count * sizeof(*mv_list); 2700 2701 /* prep the rest of the request */ 2702 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2703 cmd->num_addresses = cpu_to_le16(count); 2704 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2705 cmd->seid[1] = 0; 2706 cmd->seid[2] = 0; 2707 2708 for (i = 0; i < count; i++) 2709 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2710 mv_list[i].flags |= 2711 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2712 2713 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2714 if (buf_size > I40E_AQ_LARGE_BUF) 2715 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2716 2717 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2718 cmd_details); 2719 2720 return status; 2721 } 2722 2723 /** 2724 * i40e_aq_remove_macvlan 2725 * @hw: pointer to the hw struct 2726 * @seid: VSI for the mac address 2727 * @mv_list: list of macvlans to be removed 2728 * @count: length of the list 2729 * @cmd_details: pointer to command details structure or NULL 2730 * 2731 * Remove MAC/VLAN addresses from the HW filtering 2732 **/ 2733 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2734 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2735 u16 count, struct i40e_asq_cmd_details *cmd_details) 2736 { 2737 struct i40e_aq_desc desc; 2738 struct i40e_aqc_macvlan *cmd = 2739 (struct i40e_aqc_macvlan *)&desc.params.raw; 2740 i40e_status status; 2741 u16 buf_size; 2742 2743 if (count == 0 || !mv_list || !hw) 2744 return I40E_ERR_PARAM; 2745 2746 buf_size = count * sizeof(*mv_list); 2747 2748 /* prep the rest of the request */ 2749 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2750 cmd->num_addresses = cpu_to_le16(count); 2751 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2752 cmd->seid[1] = 0; 2753 cmd->seid[2] = 0; 2754 2755 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2756 if (buf_size > I40E_AQ_LARGE_BUF) 2757 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2758 2759 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2760 cmd_details); 2761 2762 return status; 2763 } 2764 2765 /** 2766 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2767 * @hw: pointer to the hw struct 2768 * @opcode: AQ opcode for add or delete mirror rule 2769 * @sw_seid: Switch SEID (to which rule refers) 2770 * @rule_type: Rule Type (ingress/egress/VLAN) 2771 * @id: Destination VSI SEID or Rule ID 2772 * @count: length of the list 2773 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2774 * @cmd_details: pointer to command details structure or NULL 2775 * @rule_id: Rule ID returned from FW 2776 * @rule_used: Number of rules used in internal switch 2777 * @rule_free: Number of rules free in internal switch 2778 * 2779 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2780 * VEBs/VEPA elements only 2781 **/ 2782 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2783 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2784 u16 count, __le16 *mr_list, 2785 struct i40e_asq_cmd_details *cmd_details, 2786 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2787 { 2788 struct i40e_aq_desc desc; 2789 struct i40e_aqc_add_delete_mirror_rule *cmd = 2790 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2791 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2792 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2793 i40e_status status; 2794 u16 buf_size; 2795 2796 buf_size = count * sizeof(*mr_list); 2797 2798 /* prep the rest of the request */ 2799 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2800 cmd->seid = cpu_to_le16(sw_seid); 2801 cmd->rule_type = cpu_to_le16(rule_type & 2802 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2803 cmd->num_entries = cpu_to_le16(count); 2804 /* Dest VSI for add, rule_id for delete */ 2805 cmd->destination = cpu_to_le16(id); 2806 if (mr_list) { 2807 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2808 I40E_AQ_FLAG_RD)); 2809 if (buf_size > I40E_AQ_LARGE_BUF) 2810 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2811 } 2812 2813 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2814 cmd_details); 2815 if (!status || 2816 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2817 if (rule_id) 2818 *rule_id = le16_to_cpu(resp->rule_id); 2819 if (rules_used) 2820 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2821 if (rules_free) 2822 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2823 } 2824 return status; 2825 } 2826 2827 /** 2828 * i40e_aq_add_mirrorrule - add a mirror rule 2829 * @hw: pointer to the hw struct 2830 * @sw_seid: Switch SEID (to which rule refers) 2831 * @rule_type: Rule Type (ingress/egress/VLAN) 2832 * @dest_vsi: SEID of VSI to which packets will be mirrored 2833 * @count: length of the list 2834 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2835 * @cmd_details: pointer to command details structure or NULL 2836 * @rule_id: Rule ID returned from FW 2837 * @rule_used: Number of rules used in internal switch 2838 * @rule_free: Number of rules free in internal switch 2839 * 2840 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2841 **/ 2842 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2843 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2844 struct i40e_asq_cmd_details *cmd_details, 2845 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2846 { 2847 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2848 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2849 if (count == 0 || !mr_list) 2850 return I40E_ERR_PARAM; 2851 } 2852 2853 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2854 rule_type, dest_vsi, count, mr_list, 2855 cmd_details, rule_id, rules_used, rules_free); 2856 } 2857 2858 /** 2859 * i40e_aq_delete_mirrorrule - delete a mirror rule 2860 * @hw: pointer to the hw struct 2861 * @sw_seid: Switch SEID (to which rule refers) 2862 * @rule_type: Rule Type (ingress/egress/VLAN) 2863 * @count: length of the list 2864 * @rule_id: Rule ID that is returned in the receive desc as part of 2865 * add_mirrorrule. 2866 * @mr_list: list of mirrored VLAN IDs to be removed 2867 * @cmd_details: pointer to command details structure or NULL 2868 * @rule_used: Number of rules used in internal switch 2869 * @rule_free: Number of rules free in internal switch 2870 * 2871 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2872 **/ 2873 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2874 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2875 struct i40e_asq_cmd_details *cmd_details, 2876 u16 *rules_used, u16 *rules_free) 2877 { 2878 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2879 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2880 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2881 * mirroring. For other rule_type, count and rule_type should 2882 * not matter. 2883 */ 2884 if (count == 0 || !mr_list) 2885 return I40E_ERR_PARAM; 2886 } 2887 2888 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2889 rule_type, rule_id, count, mr_list, 2890 cmd_details, NULL, rules_used, rules_free); 2891 } 2892 2893 /** 2894 * i40e_aq_send_msg_to_vf 2895 * @hw: pointer to the hardware structure 2896 * @vfid: VF id to send msg 2897 * @v_opcode: opcodes for VF-PF communication 2898 * @v_retval: return error code 2899 * @msg: pointer to the msg buffer 2900 * @msglen: msg length 2901 * @cmd_details: pointer to command details 2902 * 2903 * send msg to vf 2904 **/ 2905 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2906 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2907 struct i40e_asq_cmd_details *cmd_details) 2908 { 2909 struct i40e_aq_desc desc; 2910 struct i40e_aqc_pf_vf_message *cmd = 2911 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2912 i40e_status status; 2913 2914 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2915 cmd->id = cpu_to_le32(vfid); 2916 desc.cookie_high = cpu_to_le32(v_opcode); 2917 desc.cookie_low = cpu_to_le32(v_retval); 2918 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2919 if (msglen) { 2920 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2921 I40E_AQ_FLAG_RD)); 2922 if (msglen > I40E_AQ_LARGE_BUF) 2923 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2924 desc.datalen = cpu_to_le16(msglen); 2925 } 2926 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2927 2928 return status; 2929 } 2930 2931 /** 2932 * i40e_aq_debug_read_register 2933 * @hw: pointer to the hw struct 2934 * @reg_addr: register address 2935 * @reg_val: register value 2936 * @cmd_details: pointer to command details structure or NULL 2937 * 2938 * Read the register using the admin queue commands 2939 **/ 2940 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2941 u32 reg_addr, u64 *reg_val, 2942 struct i40e_asq_cmd_details *cmd_details) 2943 { 2944 struct i40e_aq_desc desc; 2945 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2946 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2947 i40e_status status; 2948 2949 if (reg_val == NULL) 2950 return I40E_ERR_PARAM; 2951 2952 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2953 2954 cmd_resp->address = cpu_to_le32(reg_addr); 2955 2956 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2957 2958 if (!status) { 2959 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2960 (u64)le32_to_cpu(cmd_resp->value_low); 2961 } 2962 2963 return status; 2964 } 2965 2966 /** 2967 * i40e_aq_debug_write_register 2968 * @hw: pointer to the hw struct 2969 * @reg_addr: register address 2970 * @reg_val: register value 2971 * @cmd_details: pointer to command details structure or NULL 2972 * 2973 * Write to a register using the admin queue commands 2974 **/ 2975 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2976 u32 reg_addr, u64 reg_val, 2977 struct i40e_asq_cmd_details *cmd_details) 2978 { 2979 struct i40e_aq_desc desc; 2980 struct i40e_aqc_debug_reg_read_write *cmd = 2981 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2982 i40e_status status; 2983 2984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2985 2986 cmd->address = cpu_to_le32(reg_addr); 2987 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2988 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2989 2990 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2991 2992 return status; 2993 } 2994 2995 /** 2996 * i40e_aq_request_resource 2997 * @hw: pointer to the hw struct 2998 * @resource: resource id 2999 * @access: access type 3000 * @sdp_number: resource number 3001 * @timeout: the maximum time in ms that the driver may hold the resource 3002 * @cmd_details: pointer to command details structure or NULL 3003 * 3004 * requests common resource using the admin queue commands 3005 **/ 3006 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3007 enum i40e_aq_resources_ids resource, 3008 enum i40e_aq_resource_access_type access, 3009 u8 sdp_number, u64 *timeout, 3010 struct i40e_asq_cmd_details *cmd_details) 3011 { 3012 struct i40e_aq_desc desc; 3013 struct i40e_aqc_request_resource *cmd_resp = 3014 (struct i40e_aqc_request_resource *)&desc.params.raw; 3015 i40e_status status; 3016 3017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3018 3019 cmd_resp->resource_id = cpu_to_le16(resource); 3020 cmd_resp->access_type = cpu_to_le16(access); 3021 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3022 3023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3024 /* The completion specifies the maximum time in ms that the driver 3025 * may hold the resource in the Timeout field. 3026 * If the resource is held by someone else, the command completes with 3027 * busy return value and the timeout field indicates the maximum time 3028 * the current owner of the resource has to free it. 3029 */ 3030 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3031 *timeout = le32_to_cpu(cmd_resp->timeout); 3032 3033 return status; 3034 } 3035 3036 /** 3037 * i40e_aq_release_resource 3038 * @hw: pointer to the hw struct 3039 * @resource: resource id 3040 * @sdp_number: resource number 3041 * @cmd_details: pointer to command details structure or NULL 3042 * 3043 * release common resource using the admin queue commands 3044 **/ 3045 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3046 enum i40e_aq_resources_ids resource, 3047 u8 sdp_number, 3048 struct i40e_asq_cmd_details *cmd_details) 3049 { 3050 struct i40e_aq_desc desc; 3051 struct i40e_aqc_request_resource *cmd = 3052 (struct i40e_aqc_request_resource *)&desc.params.raw; 3053 i40e_status status; 3054 3055 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3056 3057 cmd->resource_id = cpu_to_le16(resource); 3058 cmd->resource_number = cpu_to_le32(sdp_number); 3059 3060 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3061 3062 return status; 3063 } 3064 3065 /** 3066 * i40e_aq_read_nvm 3067 * @hw: pointer to the hw struct 3068 * @module_pointer: module pointer location in words from the NVM beginning 3069 * @offset: byte offset from the module beginning 3070 * @length: length of the section to be read (in bytes from the offset) 3071 * @data: command buffer (size [bytes] = length) 3072 * @last_command: tells if this is the last command in a series 3073 * @cmd_details: pointer to command details structure or NULL 3074 * 3075 * Read the NVM using the admin queue commands 3076 **/ 3077 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3078 u32 offset, u16 length, void *data, 3079 bool last_command, 3080 struct i40e_asq_cmd_details *cmd_details) 3081 { 3082 struct i40e_aq_desc desc; 3083 struct i40e_aqc_nvm_update *cmd = 3084 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3085 i40e_status status; 3086 3087 /* In offset the highest byte must be zeroed. */ 3088 if (offset & 0xFF000000) { 3089 status = I40E_ERR_PARAM; 3090 goto i40e_aq_read_nvm_exit; 3091 } 3092 3093 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3094 3095 /* If this is the last command in a series, set the proper flag. */ 3096 if (last_command) 3097 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3098 cmd->module_pointer = module_pointer; 3099 cmd->offset = cpu_to_le32(offset); 3100 cmd->length = cpu_to_le16(length); 3101 3102 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3103 if (length > I40E_AQ_LARGE_BUF) 3104 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3105 3106 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3107 3108 i40e_aq_read_nvm_exit: 3109 return status; 3110 } 3111 3112 /** 3113 * i40e_aq_erase_nvm 3114 * @hw: pointer to the hw struct 3115 * @module_pointer: module pointer location in words from the NVM beginning 3116 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3117 * @length: length of the section to be erased (expressed in 4 KB) 3118 * @last_command: tells if this is the last command in a series 3119 * @cmd_details: pointer to command details structure or NULL 3120 * 3121 * Erase the NVM sector using the admin queue commands 3122 **/ 3123 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3124 u32 offset, u16 length, bool last_command, 3125 struct i40e_asq_cmd_details *cmd_details) 3126 { 3127 struct i40e_aq_desc desc; 3128 struct i40e_aqc_nvm_update *cmd = 3129 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3130 i40e_status status; 3131 3132 /* In offset the highest byte must be zeroed. */ 3133 if (offset & 0xFF000000) { 3134 status = I40E_ERR_PARAM; 3135 goto i40e_aq_erase_nvm_exit; 3136 } 3137 3138 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3139 3140 /* If this is the last command in a series, set the proper flag. */ 3141 if (last_command) 3142 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3143 cmd->module_pointer = module_pointer; 3144 cmd->offset = cpu_to_le32(offset); 3145 cmd->length = cpu_to_le16(length); 3146 3147 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3148 3149 i40e_aq_erase_nvm_exit: 3150 return status; 3151 } 3152 3153 /** 3154 * i40e_parse_discover_capabilities 3155 * @hw: pointer to the hw struct 3156 * @buff: pointer to a buffer containing device/function capability records 3157 * @cap_count: number of capability records in the list 3158 * @list_type_opc: type of capabilities list to parse 3159 * 3160 * Parse the device/function capabilities list. 3161 **/ 3162 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3163 u32 cap_count, 3164 enum i40e_admin_queue_opc list_type_opc) 3165 { 3166 struct i40e_aqc_list_capabilities_element_resp *cap; 3167 u32 valid_functions, num_functions; 3168 u32 number, logical_id, phys_id; 3169 struct i40e_hw_capabilities *p; 3170 u8 major_rev; 3171 u32 i = 0; 3172 u16 id; 3173 3174 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3175 3176 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3177 p = &hw->dev_caps; 3178 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3179 p = &hw->func_caps; 3180 else 3181 return; 3182 3183 for (i = 0; i < cap_count; i++, cap++) { 3184 id = le16_to_cpu(cap->id); 3185 number = le32_to_cpu(cap->number); 3186 logical_id = le32_to_cpu(cap->logical_id); 3187 phys_id = le32_to_cpu(cap->phys_id); 3188 major_rev = cap->major_rev; 3189 3190 switch (id) { 3191 case I40E_AQ_CAP_ID_SWITCH_MODE: 3192 p->switch_mode = number; 3193 break; 3194 case I40E_AQ_CAP_ID_MNG_MODE: 3195 p->management_mode = number; 3196 if (major_rev > 1) { 3197 p->mng_protocols_over_mctp = logical_id; 3198 i40e_debug(hw, I40E_DEBUG_INIT, 3199 "HW Capability: Protocols over MCTP = %d\n", 3200 p->mng_protocols_over_mctp); 3201 } else { 3202 p->mng_protocols_over_mctp = 0; 3203 } 3204 break; 3205 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3206 p->npar_enable = number; 3207 break; 3208 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3209 p->os2bmc = number; 3210 break; 3211 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3212 p->valid_functions = number; 3213 break; 3214 case I40E_AQ_CAP_ID_SRIOV: 3215 if (number == 1) 3216 p->sr_iov_1_1 = true; 3217 break; 3218 case I40E_AQ_CAP_ID_VF: 3219 p->num_vfs = number; 3220 p->vf_base_id = logical_id; 3221 break; 3222 case I40E_AQ_CAP_ID_VMDQ: 3223 if (number == 1) 3224 p->vmdq = true; 3225 break; 3226 case I40E_AQ_CAP_ID_8021QBG: 3227 if (number == 1) 3228 p->evb_802_1_qbg = true; 3229 break; 3230 case I40E_AQ_CAP_ID_8021QBR: 3231 if (number == 1) 3232 p->evb_802_1_qbh = true; 3233 break; 3234 case I40E_AQ_CAP_ID_VSI: 3235 p->num_vsis = number; 3236 break; 3237 case I40E_AQ_CAP_ID_DCB: 3238 if (number == 1) { 3239 p->dcb = true; 3240 p->enabled_tcmap = logical_id; 3241 p->maxtc = phys_id; 3242 } 3243 break; 3244 case I40E_AQ_CAP_ID_FCOE: 3245 if (number == 1) 3246 p->fcoe = true; 3247 break; 3248 case I40E_AQ_CAP_ID_ISCSI: 3249 if (number == 1) 3250 p->iscsi = true; 3251 break; 3252 case I40E_AQ_CAP_ID_RSS: 3253 p->rss = true; 3254 p->rss_table_size = number; 3255 p->rss_table_entry_width = logical_id; 3256 break; 3257 case I40E_AQ_CAP_ID_RXQ: 3258 p->num_rx_qp = number; 3259 p->base_queue = phys_id; 3260 break; 3261 case I40E_AQ_CAP_ID_TXQ: 3262 p->num_tx_qp = number; 3263 p->base_queue = phys_id; 3264 break; 3265 case I40E_AQ_CAP_ID_MSIX: 3266 p->num_msix_vectors = number; 3267 i40e_debug(hw, I40E_DEBUG_INIT, 3268 "HW Capability: MSIX vector count = %d\n", 3269 p->num_msix_vectors); 3270 break; 3271 case I40E_AQ_CAP_ID_VF_MSIX: 3272 p->num_msix_vectors_vf = number; 3273 break; 3274 case I40E_AQ_CAP_ID_FLEX10: 3275 if (major_rev == 1) { 3276 if (number == 1) { 3277 p->flex10_enable = true; 3278 p->flex10_capable = true; 3279 } 3280 } else { 3281 /* Capability revision >= 2 */ 3282 if (number & 1) 3283 p->flex10_enable = true; 3284 if (number & 2) 3285 p->flex10_capable = true; 3286 } 3287 p->flex10_mode = logical_id; 3288 p->flex10_status = phys_id; 3289 break; 3290 case I40E_AQ_CAP_ID_CEM: 3291 if (number == 1) 3292 p->mgmt_cem = true; 3293 break; 3294 case I40E_AQ_CAP_ID_IWARP: 3295 if (number == 1) 3296 p->iwarp = true; 3297 break; 3298 case I40E_AQ_CAP_ID_LED: 3299 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3300 p->led[phys_id] = true; 3301 break; 3302 case I40E_AQ_CAP_ID_SDP: 3303 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3304 p->sdp[phys_id] = true; 3305 break; 3306 case I40E_AQ_CAP_ID_MDIO: 3307 if (number == 1) { 3308 p->mdio_port_num = phys_id; 3309 p->mdio_port_mode = logical_id; 3310 } 3311 break; 3312 case I40E_AQ_CAP_ID_1588: 3313 if (number == 1) 3314 p->ieee_1588 = true; 3315 break; 3316 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3317 p->fd = true; 3318 p->fd_filters_guaranteed = number; 3319 p->fd_filters_best_effort = logical_id; 3320 break; 3321 case I40E_AQ_CAP_ID_WSR_PROT: 3322 p->wr_csr_prot = (u64)number; 3323 p->wr_csr_prot |= (u64)logical_id << 32; 3324 break; 3325 case I40E_AQ_CAP_ID_NVM_MGMT: 3326 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3327 p->sec_rev_disabled = true; 3328 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3329 p->update_disabled = true; 3330 break; 3331 default: 3332 break; 3333 } 3334 } 3335 3336 if (p->fcoe) 3337 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3338 3339 /* Software override ensuring FCoE is disabled if npar or mfp 3340 * mode because it is not supported in these modes. 3341 */ 3342 if (p->npar_enable || p->flex10_enable) 3343 p->fcoe = false; 3344 3345 /* count the enabled ports (aka the "not disabled" ports) */ 3346 hw->num_ports = 0; 3347 for (i = 0; i < 4; i++) { 3348 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3349 u64 port_cfg = 0; 3350 3351 /* use AQ read to get the physical register offset instead 3352 * of the port relative offset 3353 */ 3354 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3355 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3356 hw->num_ports++; 3357 } 3358 3359 valid_functions = p->valid_functions; 3360 num_functions = 0; 3361 while (valid_functions) { 3362 if (valid_functions & 1) 3363 num_functions++; 3364 valid_functions >>= 1; 3365 } 3366 3367 /* partition id is 1-based, and functions are evenly spread 3368 * across the ports as partitions 3369 */ 3370 if (hw->num_ports != 0) { 3371 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3372 hw->num_partitions = num_functions / hw->num_ports; 3373 } 3374 3375 /* additional HW specific goodies that might 3376 * someday be HW version specific 3377 */ 3378 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3379 } 3380 3381 /** 3382 * i40e_aq_discover_capabilities 3383 * @hw: pointer to the hw struct 3384 * @buff: a virtual buffer to hold the capabilities 3385 * @buff_size: Size of the virtual buffer 3386 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3387 * @list_type_opc: capabilities type to discover - pass in the command opcode 3388 * @cmd_details: pointer to command details structure or NULL 3389 * 3390 * Get the device capabilities descriptions from the firmware 3391 **/ 3392 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3393 void *buff, u16 buff_size, u16 *data_size, 3394 enum i40e_admin_queue_opc list_type_opc, 3395 struct i40e_asq_cmd_details *cmd_details) 3396 { 3397 struct i40e_aqc_list_capabilites *cmd; 3398 struct i40e_aq_desc desc; 3399 i40e_status status = 0; 3400 3401 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3402 3403 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3404 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3405 status = I40E_ERR_PARAM; 3406 goto exit; 3407 } 3408 3409 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3410 3411 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3412 if (buff_size > I40E_AQ_LARGE_BUF) 3413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3414 3415 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3416 *data_size = le16_to_cpu(desc.datalen); 3417 3418 if (status) 3419 goto exit; 3420 3421 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3422 list_type_opc); 3423 3424 exit: 3425 return status; 3426 } 3427 3428 /** 3429 * i40e_aq_update_nvm 3430 * @hw: pointer to the hw struct 3431 * @module_pointer: module pointer location in words from the NVM beginning 3432 * @offset: byte offset from the module beginning 3433 * @length: length of the section to be written (in bytes from the offset) 3434 * @data: command buffer (size [bytes] = length) 3435 * @last_command: tells if this is the last command in a series 3436 * @cmd_details: pointer to command details structure or NULL 3437 * 3438 * Update the NVM using the admin queue commands 3439 **/ 3440 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3441 u32 offset, u16 length, void *data, 3442 bool last_command, 3443 struct i40e_asq_cmd_details *cmd_details) 3444 { 3445 struct i40e_aq_desc desc; 3446 struct i40e_aqc_nvm_update *cmd = 3447 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3448 i40e_status status; 3449 3450 /* In offset the highest byte must be zeroed. */ 3451 if (offset & 0xFF000000) { 3452 status = I40E_ERR_PARAM; 3453 goto i40e_aq_update_nvm_exit; 3454 } 3455 3456 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3457 3458 /* If this is the last command in a series, set the proper flag. */ 3459 if (last_command) 3460 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3461 cmd->module_pointer = module_pointer; 3462 cmd->offset = cpu_to_le32(offset); 3463 cmd->length = cpu_to_le16(length); 3464 3465 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3466 if (length > I40E_AQ_LARGE_BUF) 3467 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3468 3469 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3470 3471 i40e_aq_update_nvm_exit: 3472 return status; 3473 } 3474 3475 /** 3476 * i40e_aq_get_lldp_mib 3477 * @hw: pointer to the hw struct 3478 * @bridge_type: type of bridge requested 3479 * @mib_type: Local, Remote or both Local and Remote MIBs 3480 * @buff: pointer to a user supplied buffer to store the MIB block 3481 * @buff_size: size of the buffer (in bytes) 3482 * @local_len : length of the returned Local LLDP MIB 3483 * @remote_len: length of the returned Remote LLDP MIB 3484 * @cmd_details: pointer to command details structure or NULL 3485 * 3486 * Requests the complete LLDP MIB (entire packet). 3487 **/ 3488 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3489 u8 mib_type, void *buff, u16 buff_size, 3490 u16 *local_len, u16 *remote_len, 3491 struct i40e_asq_cmd_details *cmd_details) 3492 { 3493 struct i40e_aq_desc desc; 3494 struct i40e_aqc_lldp_get_mib *cmd = 3495 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3496 struct i40e_aqc_lldp_get_mib *resp = 3497 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3498 i40e_status status; 3499 3500 if (buff_size == 0 || !buff) 3501 return I40E_ERR_PARAM; 3502 3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3504 /* Indirect Command */ 3505 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3506 3507 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3508 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3509 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3510 3511 desc.datalen = cpu_to_le16(buff_size); 3512 3513 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3514 if (buff_size > I40E_AQ_LARGE_BUF) 3515 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3516 3517 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3518 if (!status) { 3519 if (local_len != NULL) 3520 *local_len = le16_to_cpu(resp->local_len); 3521 if (remote_len != NULL) 3522 *remote_len = le16_to_cpu(resp->remote_len); 3523 } 3524 3525 return status; 3526 } 3527 3528 /** 3529 * i40e_aq_cfg_lldp_mib_change_event 3530 * @hw: pointer to the hw struct 3531 * @enable_update: Enable or Disable event posting 3532 * @cmd_details: pointer to command details structure or NULL 3533 * 3534 * Enable or Disable posting of an event on ARQ when LLDP MIB 3535 * associated with the interface changes 3536 **/ 3537 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3538 bool enable_update, 3539 struct i40e_asq_cmd_details *cmd_details) 3540 { 3541 struct i40e_aq_desc desc; 3542 struct i40e_aqc_lldp_update_mib *cmd = 3543 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3544 i40e_status status; 3545 3546 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3547 3548 if (!enable_update) 3549 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3550 3551 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3552 3553 return status; 3554 } 3555 3556 /** 3557 * i40e_aq_stop_lldp 3558 * @hw: pointer to the hw struct 3559 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3560 * @cmd_details: pointer to command details structure or NULL 3561 * 3562 * Stop or Shutdown the embedded LLDP Agent 3563 **/ 3564 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3565 struct i40e_asq_cmd_details *cmd_details) 3566 { 3567 struct i40e_aq_desc desc; 3568 struct i40e_aqc_lldp_stop *cmd = 3569 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3570 i40e_status status; 3571 3572 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3573 3574 if (shutdown_agent) 3575 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3576 3577 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3578 3579 return status; 3580 } 3581 3582 /** 3583 * i40e_aq_start_lldp 3584 * @hw: pointer to the hw struct 3585 * @cmd_details: pointer to command details structure or NULL 3586 * 3587 * Start the embedded LLDP Agent on all ports. 3588 **/ 3589 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3590 struct i40e_asq_cmd_details *cmd_details) 3591 { 3592 struct i40e_aq_desc desc; 3593 struct i40e_aqc_lldp_start *cmd = 3594 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3595 i40e_status status; 3596 3597 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3598 3599 cmd->command = I40E_AQ_LLDP_AGENT_START; 3600 3601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3602 3603 return status; 3604 } 3605 3606 /** 3607 * i40e_aq_get_cee_dcb_config 3608 * @hw: pointer to the hw struct 3609 * @buff: response buffer that stores CEE operational configuration 3610 * @buff_size: size of the buffer passed 3611 * @cmd_details: pointer to command details structure or NULL 3612 * 3613 * Get CEE DCBX mode operational configuration from firmware 3614 **/ 3615 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3616 void *buff, u16 buff_size, 3617 struct i40e_asq_cmd_details *cmd_details) 3618 { 3619 struct i40e_aq_desc desc; 3620 i40e_status status; 3621 3622 if (buff_size == 0 || !buff) 3623 return I40E_ERR_PARAM; 3624 3625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3626 3627 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3628 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3629 cmd_details); 3630 3631 return status; 3632 } 3633 3634 /** 3635 * i40e_aq_add_udp_tunnel 3636 * @hw: pointer to the hw struct 3637 * @udp_port: the UDP port to add 3638 * @header_len: length of the tunneling header length in DWords 3639 * @protocol_index: protocol index type 3640 * @filter_index: pointer to filter index 3641 * @cmd_details: pointer to command details structure or NULL 3642 **/ 3643 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3644 u16 udp_port, u8 protocol_index, 3645 u8 *filter_index, 3646 struct i40e_asq_cmd_details *cmd_details) 3647 { 3648 struct i40e_aq_desc desc; 3649 struct i40e_aqc_add_udp_tunnel *cmd = 3650 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3651 struct i40e_aqc_del_udp_tunnel_completion *resp = 3652 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3653 i40e_status status; 3654 3655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3656 3657 cmd->udp_port = cpu_to_le16(udp_port); 3658 cmd->protocol_type = protocol_index; 3659 3660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3661 3662 if (!status && filter_index) 3663 *filter_index = resp->index; 3664 3665 return status; 3666 } 3667 3668 /** 3669 * i40e_aq_del_udp_tunnel 3670 * @hw: pointer to the hw struct 3671 * @index: filter index 3672 * @cmd_details: pointer to command details structure or NULL 3673 **/ 3674 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3675 struct i40e_asq_cmd_details *cmd_details) 3676 { 3677 struct i40e_aq_desc desc; 3678 struct i40e_aqc_remove_udp_tunnel *cmd = 3679 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3680 i40e_status status; 3681 3682 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3683 3684 cmd->index = index; 3685 3686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3687 3688 return status; 3689 } 3690 3691 /** 3692 * i40e_aq_delete_element - Delete switch element 3693 * @hw: pointer to the hw struct 3694 * @seid: the SEID to delete from the switch 3695 * @cmd_details: pointer to command details structure or NULL 3696 * 3697 * This deletes a switch element from the switch. 3698 **/ 3699 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3700 struct i40e_asq_cmd_details *cmd_details) 3701 { 3702 struct i40e_aq_desc desc; 3703 struct i40e_aqc_switch_seid *cmd = 3704 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3705 i40e_status status; 3706 3707 if (seid == 0) 3708 return I40E_ERR_PARAM; 3709 3710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3711 3712 cmd->seid = cpu_to_le16(seid); 3713 3714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3715 3716 return status; 3717 } 3718 3719 /** 3720 * i40e_aq_dcb_updated - DCB Updated Command 3721 * @hw: pointer to the hw struct 3722 * @cmd_details: pointer to command details structure or NULL 3723 * 3724 * EMP will return when the shared RPB settings have been 3725 * recomputed and modified. The retval field in the descriptor 3726 * will be set to 0 when RPB is modified. 3727 **/ 3728 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3729 struct i40e_asq_cmd_details *cmd_details) 3730 { 3731 struct i40e_aq_desc desc; 3732 i40e_status status; 3733 3734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3735 3736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3737 3738 return status; 3739 } 3740 3741 /** 3742 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3743 * @hw: pointer to the hw struct 3744 * @seid: seid for the physical port/switching component/vsi 3745 * @buff: Indirect buffer to hold data parameters and response 3746 * @buff_size: Indirect buffer size 3747 * @opcode: Tx scheduler AQ command opcode 3748 * @cmd_details: pointer to command details structure or NULL 3749 * 3750 * Generic command handler for Tx scheduler AQ commands 3751 **/ 3752 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3753 void *buff, u16 buff_size, 3754 enum i40e_admin_queue_opc opcode, 3755 struct i40e_asq_cmd_details *cmd_details) 3756 { 3757 struct i40e_aq_desc desc; 3758 struct i40e_aqc_tx_sched_ind *cmd = 3759 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3760 i40e_status status; 3761 bool cmd_param_flag = false; 3762 3763 switch (opcode) { 3764 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3765 case i40e_aqc_opc_configure_vsi_tc_bw: 3766 case i40e_aqc_opc_enable_switching_comp_ets: 3767 case i40e_aqc_opc_modify_switching_comp_ets: 3768 case i40e_aqc_opc_disable_switching_comp_ets: 3769 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3770 case i40e_aqc_opc_configure_switching_comp_bw_config: 3771 cmd_param_flag = true; 3772 break; 3773 case i40e_aqc_opc_query_vsi_bw_config: 3774 case i40e_aqc_opc_query_vsi_ets_sla_config: 3775 case i40e_aqc_opc_query_switching_comp_ets_config: 3776 case i40e_aqc_opc_query_port_ets_config: 3777 case i40e_aqc_opc_query_switching_comp_bw_config: 3778 cmd_param_flag = false; 3779 break; 3780 default: 3781 return I40E_ERR_PARAM; 3782 } 3783 3784 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3785 3786 /* Indirect command */ 3787 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3788 if (cmd_param_flag) 3789 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3790 if (buff_size > I40E_AQ_LARGE_BUF) 3791 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3792 3793 desc.datalen = cpu_to_le16(buff_size); 3794 3795 cmd->vsi_seid = cpu_to_le16(seid); 3796 3797 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3798 3799 return status; 3800 } 3801 3802 /** 3803 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3804 * @hw: pointer to the hw struct 3805 * @seid: VSI seid 3806 * @credit: BW limit credits (0 = disabled) 3807 * @max_credit: Max BW limit credits 3808 * @cmd_details: pointer to command details structure or NULL 3809 **/ 3810 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3811 u16 seid, u16 credit, u8 max_credit, 3812 struct i40e_asq_cmd_details *cmd_details) 3813 { 3814 struct i40e_aq_desc desc; 3815 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3816 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3817 i40e_status status; 3818 3819 i40e_fill_default_direct_cmd_desc(&desc, 3820 i40e_aqc_opc_configure_vsi_bw_limit); 3821 3822 cmd->vsi_seid = cpu_to_le16(seid); 3823 cmd->credit = cpu_to_le16(credit); 3824 cmd->max_credit = max_credit; 3825 3826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3827 3828 return status; 3829 } 3830 3831 /** 3832 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3833 * @hw: pointer to the hw struct 3834 * @seid: VSI seid 3835 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3836 * @cmd_details: pointer to command details structure or NULL 3837 **/ 3838 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3839 u16 seid, 3840 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3841 struct i40e_asq_cmd_details *cmd_details) 3842 { 3843 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3844 i40e_aqc_opc_configure_vsi_tc_bw, 3845 cmd_details); 3846 } 3847 3848 /** 3849 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3850 * @hw: pointer to the hw struct 3851 * @seid: seid of the switching component connected to Physical Port 3852 * @ets_data: Buffer holding ETS parameters 3853 * @cmd_details: pointer to command details structure or NULL 3854 **/ 3855 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3856 u16 seid, 3857 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3858 enum i40e_admin_queue_opc opcode, 3859 struct i40e_asq_cmd_details *cmd_details) 3860 { 3861 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3862 sizeof(*ets_data), opcode, cmd_details); 3863 } 3864 3865 /** 3866 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3867 * @hw: pointer to the hw struct 3868 * @seid: seid of the switching component 3869 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3870 * @cmd_details: pointer to command details structure or NULL 3871 **/ 3872 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3873 u16 seid, 3874 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3875 struct i40e_asq_cmd_details *cmd_details) 3876 { 3877 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3878 i40e_aqc_opc_configure_switching_comp_bw_config, 3879 cmd_details); 3880 } 3881 3882 /** 3883 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3884 * @hw: pointer to the hw struct 3885 * @seid: seid of the VSI 3886 * @bw_data: Buffer to hold VSI BW configuration 3887 * @cmd_details: pointer to command details structure or NULL 3888 **/ 3889 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3890 u16 seid, 3891 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3892 struct i40e_asq_cmd_details *cmd_details) 3893 { 3894 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3895 i40e_aqc_opc_query_vsi_bw_config, 3896 cmd_details); 3897 } 3898 3899 /** 3900 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3901 * @hw: pointer to the hw struct 3902 * @seid: seid of the VSI 3903 * @bw_data: Buffer to hold VSI BW configuration per TC 3904 * @cmd_details: pointer to command details structure or NULL 3905 **/ 3906 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3907 u16 seid, 3908 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3909 struct i40e_asq_cmd_details *cmd_details) 3910 { 3911 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3912 i40e_aqc_opc_query_vsi_ets_sla_config, 3913 cmd_details); 3914 } 3915 3916 /** 3917 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3918 * @hw: pointer to the hw struct 3919 * @seid: seid of the switching component 3920 * @bw_data: Buffer to hold switching component's per TC BW config 3921 * @cmd_details: pointer to command details structure or NULL 3922 **/ 3923 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3924 u16 seid, 3925 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3926 struct i40e_asq_cmd_details *cmd_details) 3927 { 3928 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3929 i40e_aqc_opc_query_switching_comp_ets_config, 3930 cmd_details); 3931 } 3932 3933 /** 3934 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3935 * @hw: pointer to the hw struct 3936 * @seid: seid of the VSI or switching component connected to Physical Port 3937 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3938 * @cmd_details: pointer to command details structure or NULL 3939 **/ 3940 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3941 u16 seid, 3942 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3943 struct i40e_asq_cmd_details *cmd_details) 3944 { 3945 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3946 i40e_aqc_opc_query_port_ets_config, 3947 cmd_details); 3948 } 3949 3950 /** 3951 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3952 * @hw: pointer to the hw struct 3953 * @seid: seid of the switching component 3954 * @bw_data: Buffer to hold switching component's BW configuration 3955 * @cmd_details: pointer to command details structure or NULL 3956 **/ 3957 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3958 u16 seid, 3959 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3960 struct i40e_asq_cmd_details *cmd_details) 3961 { 3962 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3963 i40e_aqc_opc_query_switching_comp_bw_config, 3964 cmd_details); 3965 } 3966 3967 /** 3968 * i40e_validate_filter_settings 3969 * @hw: pointer to the hardware structure 3970 * @settings: Filter control settings 3971 * 3972 * Check and validate the filter control settings passed. 3973 * The function checks for the valid filter/context sizes being 3974 * passed for FCoE and PE. 3975 * 3976 * Returns 0 if the values passed are valid and within 3977 * range else returns an error. 3978 **/ 3979 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3980 struct i40e_filter_control_settings *settings) 3981 { 3982 u32 fcoe_cntx_size, fcoe_filt_size; 3983 u32 pe_cntx_size, pe_filt_size; 3984 u32 fcoe_fmax; 3985 u32 val; 3986 3987 /* Validate FCoE settings passed */ 3988 switch (settings->fcoe_filt_num) { 3989 case I40E_HASH_FILTER_SIZE_1K: 3990 case I40E_HASH_FILTER_SIZE_2K: 3991 case I40E_HASH_FILTER_SIZE_4K: 3992 case I40E_HASH_FILTER_SIZE_8K: 3993 case I40E_HASH_FILTER_SIZE_16K: 3994 case I40E_HASH_FILTER_SIZE_32K: 3995 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3996 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3997 break; 3998 default: 3999 return I40E_ERR_PARAM; 4000 } 4001 4002 switch (settings->fcoe_cntx_num) { 4003 case I40E_DMA_CNTX_SIZE_512: 4004 case I40E_DMA_CNTX_SIZE_1K: 4005 case I40E_DMA_CNTX_SIZE_2K: 4006 case I40E_DMA_CNTX_SIZE_4K: 4007 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4008 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4009 break; 4010 default: 4011 return I40E_ERR_PARAM; 4012 } 4013 4014 /* Validate PE settings passed */ 4015 switch (settings->pe_filt_num) { 4016 case I40E_HASH_FILTER_SIZE_1K: 4017 case I40E_HASH_FILTER_SIZE_2K: 4018 case I40E_HASH_FILTER_SIZE_4K: 4019 case I40E_HASH_FILTER_SIZE_8K: 4020 case I40E_HASH_FILTER_SIZE_16K: 4021 case I40E_HASH_FILTER_SIZE_32K: 4022 case I40E_HASH_FILTER_SIZE_64K: 4023 case I40E_HASH_FILTER_SIZE_128K: 4024 case I40E_HASH_FILTER_SIZE_256K: 4025 case I40E_HASH_FILTER_SIZE_512K: 4026 case I40E_HASH_FILTER_SIZE_1M: 4027 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4028 pe_filt_size <<= (u32)settings->pe_filt_num; 4029 break; 4030 default: 4031 return I40E_ERR_PARAM; 4032 } 4033 4034 switch (settings->pe_cntx_num) { 4035 case I40E_DMA_CNTX_SIZE_512: 4036 case I40E_DMA_CNTX_SIZE_1K: 4037 case I40E_DMA_CNTX_SIZE_2K: 4038 case I40E_DMA_CNTX_SIZE_4K: 4039 case I40E_DMA_CNTX_SIZE_8K: 4040 case I40E_DMA_CNTX_SIZE_16K: 4041 case I40E_DMA_CNTX_SIZE_32K: 4042 case I40E_DMA_CNTX_SIZE_64K: 4043 case I40E_DMA_CNTX_SIZE_128K: 4044 case I40E_DMA_CNTX_SIZE_256K: 4045 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4046 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4047 break; 4048 default: 4049 return I40E_ERR_PARAM; 4050 } 4051 4052 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4053 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4054 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4055 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4056 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4057 return I40E_ERR_INVALID_SIZE; 4058 4059 return 0; 4060 } 4061 4062 /** 4063 * i40e_set_filter_control 4064 * @hw: pointer to the hardware structure 4065 * @settings: Filter control settings 4066 * 4067 * Set the Queue Filters for PE/FCoE and enable filters required 4068 * for a single PF. It is expected that these settings are programmed 4069 * at the driver initialization time. 4070 **/ 4071 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4072 struct i40e_filter_control_settings *settings) 4073 { 4074 i40e_status ret = 0; 4075 u32 hash_lut_size = 0; 4076 u32 val; 4077 4078 if (!settings) 4079 return I40E_ERR_PARAM; 4080 4081 /* Validate the input settings */ 4082 ret = i40e_validate_filter_settings(hw, settings); 4083 if (ret) 4084 return ret; 4085 4086 /* Read the PF Queue Filter control register */ 4087 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4088 4089 /* Program required PE hash buckets for the PF */ 4090 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4091 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4092 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4093 /* Program required PE contexts for the PF */ 4094 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4095 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4096 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4097 4098 /* Program required FCoE hash buckets for the PF */ 4099 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4100 val |= ((u32)settings->fcoe_filt_num << 4101 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4102 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4103 /* Program required FCoE DDP contexts for the PF */ 4104 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4105 val |= ((u32)settings->fcoe_cntx_num << 4106 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4107 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4108 4109 /* Program Hash LUT size for the PF */ 4110 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4111 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4112 hash_lut_size = 1; 4113 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4114 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4115 4116 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4117 if (settings->enable_fdir) 4118 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4119 if (settings->enable_ethtype) 4120 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4121 if (settings->enable_macvlan) 4122 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4123 4124 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4125 4126 return 0; 4127 } 4128 4129 /** 4130 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4131 * @hw: pointer to the hw struct 4132 * @mac_addr: MAC address to use in the filter 4133 * @ethtype: Ethertype to use in the filter 4134 * @flags: Flags that needs to be applied to the filter 4135 * @vsi_seid: seid of the control VSI 4136 * @queue: VSI queue number to send the packet to 4137 * @is_add: Add control packet filter if True else remove 4138 * @stats: Structure to hold information on control filter counts 4139 * @cmd_details: pointer to command details structure or NULL 4140 * 4141 * This command will Add or Remove control packet filter for a control VSI. 4142 * In return it will update the total number of perfect filter count in 4143 * the stats member. 4144 **/ 4145 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4146 u8 *mac_addr, u16 ethtype, u16 flags, 4147 u16 vsi_seid, u16 queue, bool is_add, 4148 struct i40e_control_filter_stats *stats, 4149 struct i40e_asq_cmd_details *cmd_details) 4150 { 4151 struct i40e_aq_desc desc; 4152 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4153 (struct i40e_aqc_add_remove_control_packet_filter *) 4154 &desc.params.raw; 4155 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4156 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4157 &desc.params.raw; 4158 i40e_status status; 4159 4160 if (vsi_seid == 0) 4161 return I40E_ERR_PARAM; 4162 4163 if (is_add) { 4164 i40e_fill_default_direct_cmd_desc(&desc, 4165 i40e_aqc_opc_add_control_packet_filter); 4166 cmd->queue = cpu_to_le16(queue); 4167 } else { 4168 i40e_fill_default_direct_cmd_desc(&desc, 4169 i40e_aqc_opc_remove_control_packet_filter); 4170 } 4171 4172 if (mac_addr) 4173 ether_addr_copy(cmd->mac, mac_addr); 4174 4175 cmd->etype = cpu_to_le16(ethtype); 4176 cmd->flags = cpu_to_le16(flags); 4177 cmd->seid = cpu_to_le16(vsi_seid); 4178 4179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4180 4181 if (!status && stats) { 4182 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4183 stats->etype_used = le16_to_cpu(resp->etype_used); 4184 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4185 stats->etype_free = le16_to_cpu(resp->etype_free); 4186 } 4187 4188 return status; 4189 } 4190 4191 /** 4192 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4193 * @hw: pointer to the hw struct 4194 * @seid: VSI seid to add ethertype filter from 4195 **/ 4196 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4197 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4198 u16 seid) 4199 { 4200 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4201 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4202 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4203 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4204 i40e_status status; 4205 4206 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4207 seid, 0, true, NULL, 4208 NULL); 4209 if (status) 4210 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4211 } 4212 4213 /** 4214 * i40e_aq_alternate_read 4215 * @hw: pointer to the hardware structure 4216 * @reg_addr0: address of first dword to be read 4217 * @reg_val0: pointer for data read from 'reg_addr0' 4218 * @reg_addr1: address of second dword to be read 4219 * @reg_val1: pointer for data read from 'reg_addr1' 4220 * 4221 * Read one or two dwords from alternate structure. Fields are indicated 4222 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4223 * is not passed then only register at 'reg_addr0' is read. 4224 * 4225 **/ 4226 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4227 u32 reg_addr0, u32 *reg_val0, 4228 u32 reg_addr1, u32 *reg_val1) 4229 { 4230 struct i40e_aq_desc desc; 4231 struct i40e_aqc_alternate_write *cmd_resp = 4232 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4233 i40e_status status; 4234 4235 if (!reg_val0) 4236 return I40E_ERR_PARAM; 4237 4238 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4239 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4240 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4241 4242 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4243 4244 if (!status) { 4245 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4246 4247 if (reg_val1) 4248 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4249 } 4250 4251 return status; 4252 } 4253 4254 /** 4255 * i40e_aq_resume_port_tx 4256 * @hw: pointer to the hardware structure 4257 * @cmd_details: pointer to command details structure or NULL 4258 * 4259 * Resume port's Tx traffic 4260 **/ 4261 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4262 struct i40e_asq_cmd_details *cmd_details) 4263 { 4264 struct i40e_aq_desc desc; 4265 i40e_status status; 4266 4267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4268 4269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4270 4271 return status; 4272 } 4273 4274 /** 4275 * i40e_set_pci_config_data - store PCI bus info 4276 * @hw: pointer to hardware structure 4277 * @link_status: the link status word from PCI config space 4278 * 4279 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4280 **/ 4281 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4282 { 4283 hw->bus.type = i40e_bus_type_pci_express; 4284 4285 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4286 case PCI_EXP_LNKSTA_NLW_X1: 4287 hw->bus.width = i40e_bus_width_pcie_x1; 4288 break; 4289 case PCI_EXP_LNKSTA_NLW_X2: 4290 hw->bus.width = i40e_bus_width_pcie_x2; 4291 break; 4292 case PCI_EXP_LNKSTA_NLW_X4: 4293 hw->bus.width = i40e_bus_width_pcie_x4; 4294 break; 4295 case PCI_EXP_LNKSTA_NLW_X8: 4296 hw->bus.width = i40e_bus_width_pcie_x8; 4297 break; 4298 default: 4299 hw->bus.width = i40e_bus_width_unknown; 4300 break; 4301 } 4302 4303 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4304 case PCI_EXP_LNKSTA_CLS_2_5GB: 4305 hw->bus.speed = i40e_bus_speed_2500; 4306 break; 4307 case PCI_EXP_LNKSTA_CLS_5_0GB: 4308 hw->bus.speed = i40e_bus_speed_5000; 4309 break; 4310 case PCI_EXP_LNKSTA_CLS_8_0GB: 4311 hw->bus.speed = i40e_bus_speed_8000; 4312 break; 4313 default: 4314 hw->bus.speed = i40e_bus_speed_unknown; 4315 break; 4316 } 4317 } 4318 4319 /** 4320 * i40e_aq_debug_dump 4321 * @hw: pointer to the hardware structure 4322 * @cluster_id: specific cluster to dump 4323 * @table_id: table id within cluster 4324 * @start_index: index of line in the block to read 4325 * @buff_size: dump buffer size 4326 * @buff: dump buffer 4327 * @ret_buff_size: actual buffer size returned 4328 * @ret_next_table: next block to read 4329 * @ret_next_index: next index to read 4330 * 4331 * Dump internal FW/HW data for debug purposes. 4332 * 4333 **/ 4334 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4335 u8 table_id, u32 start_index, u16 buff_size, 4336 void *buff, u16 *ret_buff_size, 4337 u8 *ret_next_table, u32 *ret_next_index, 4338 struct i40e_asq_cmd_details *cmd_details) 4339 { 4340 struct i40e_aq_desc desc; 4341 struct i40e_aqc_debug_dump_internals *cmd = 4342 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4343 struct i40e_aqc_debug_dump_internals *resp = 4344 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4345 i40e_status status; 4346 4347 if (buff_size == 0 || !buff) 4348 return I40E_ERR_PARAM; 4349 4350 i40e_fill_default_direct_cmd_desc(&desc, 4351 i40e_aqc_opc_debug_dump_internals); 4352 /* Indirect Command */ 4353 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4354 if (buff_size > I40E_AQ_LARGE_BUF) 4355 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4356 4357 cmd->cluster_id = cluster_id; 4358 cmd->table_id = table_id; 4359 cmd->idx = cpu_to_le32(start_index); 4360 4361 desc.datalen = cpu_to_le16(buff_size); 4362 4363 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4364 if (!status) { 4365 if (ret_buff_size) 4366 *ret_buff_size = le16_to_cpu(desc.datalen); 4367 if (ret_next_table) 4368 *ret_next_table = resp->table_id; 4369 if (ret_next_index) 4370 *ret_next_index = le32_to_cpu(resp->idx); 4371 } 4372 4373 return status; 4374 } 4375 4376 /** 4377 * i40e_read_bw_from_alt_ram 4378 * @hw: pointer to the hardware structure 4379 * @max_bw: pointer for max_bw read 4380 * @min_bw: pointer for min_bw read 4381 * @min_valid: pointer for bool that is true if min_bw is a valid value 4382 * @max_valid: pointer for bool that is true if max_bw is a valid value 4383 * 4384 * Read bw from the alternate ram for the given pf 4385 **/ 4386 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4387 u32 *max_bw, u32 *min_bw, 4388 bool *min_valid, bool *max_valid) 4389 { 4390 i40e_status status; 4391 u32 max_bw_addr, min_bw_addr; 4392 4393 /* Calculate the address of the min/max bw registers */ 4394 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4395 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4396 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4397 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4398 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4399 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4400 4401 /* Read the bandwidths from alt ram */ 4402 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4403 min_bw_addr, min_bw); 4404 4405 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4406 *min_valid = true; 4407 else 4408 *min_valid = false; 4409 4410 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4411 *max_valid = true; 4412 else 4413 *max_valid = false; 4414 4415 return status; 4416 } 4417 4418 /** 4419 * i40e_aq_configure_partition_bw 4420 * @hw: pointer to the hardware structure 4421 * @bw_data: Buffer holding valid pfs and bw limits 4422 * @cmd_details: pointer to command details 4423 * 4424 * Configure partitions guaranteed/max bw 4425 **/ 4426 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4427 struct i40e_aqc_configure_partition_bw_data *bw_data, 4428 struct i40e_asq_cmd_details *cmd_details) 4429 { 4430 i40e_status status; 4431 struct i40e_aq_desc desc; 4432 u16 bwd_size = sizeof(*bw_data); 4433 4434 i40e_fill_default_direct_cmd_desc(&desc, 4435 i40e_aqc_opc_configure_partition_bw); 4436 4437 /* Indirect command */ 4438 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4439 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4440 4441 if (bwd_size > I40E_AQ_LARGE_BUF) 4442 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4443 4444 desc.datalen = cpu_to_le16(bwd_size); 4445 4446 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4447 cmd_details); 4448 4449 return status; 4450 } 4451 4452 /** 4453 * i40e_read_phy_register_clause22 4454 * @hw: pointer to the HW structure 4455 * @reg: register address in the page 4456 * @phy_adr: PHY address on MDIO interface 4457 * @value: PHY register value 4458 * 4459 * Reads specified PHY register value 4460 **/ 4461 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4462 u16 reg, u8 phy_addr, u16 *value) 4463 { 4464 i40e_status status = I40E_ERR_TIMEOUT; 4465 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4466 u32 command = 0; 4467 u16 retry = 1000; 4468 4469 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4470 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4471 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4472 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4473 (I40E_GLGEN_MSCA_MDICMD_MASK); 4474 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4475 do { 4476 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4477 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4478 status = 0; 4479 break; 4480 } 4481 udelay(10); 4482 retry--; 4483 } while (retry); 4484 4485 if (status) { 4486 i40e_debug(hw, I40E_DEBUG_PHY, 4487 "PHY: Can't write command to external PHY.\n"); 4488 } else { 4489 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4490 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4491 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4492 } 4493 4494 return status; 4495 } 4496 4497 /** 4498 * i40e_write_phy_register_clause22 4499 * @hw: pointer to the HW structure 4500 * @reg: register address in the page 4501 * @phy_adr: PHY address on MDIO interface 4502 * @value: PHY register value 4503 * 4504 * Writes specified PHY register value 4505 **/ 4506 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4507 u16 reg, u8 phy_addr, u16 value) 4508 { 4509 i40e_status status = I40E_ERR_TIMEOUT; 4510 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4511 u32 command = 0; 4512 u16 retry = 1000; 4513 4514 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4515 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4516 4517 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4518 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4519 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4520 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4521 (I40E_GLGEN_MSCA_MDICMD_MASK); 4522 4523 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4524 do { 4525 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4526 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4527 status = 0; 4528 break; 4529 } 4530 udelay(10); 4531 retry--; 4532 } while (retry); 4533 4534 return status; 4535 } 4536 4537 /** 4538 * i40e_read_phy_register_clause45 4539 * @hw: pointer to the HW structure 4540 * @page: registers page number 4541 * @reg: register address in the page 4542 * @phy_adr: PHY address on MDIO interface 4543 * @value: PHY register value 4544 * 4545 * Reads specified PHY register value 4546 **/ 4547 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4548 u8 page, u16 reg, u8 phy_addr, u16 *value) 4549 { 4550 i40e_status status = I40E_ERR_TIMEOUT; 4551 u32 command = 0; 4552 u16 retry = 1000; 4553 u8 port_num = hw->func_caps.mdio_port_num; 4554 4555 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4556 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4557 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4558 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4559 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4560 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4561 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4562 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4563 do { 4564 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4565 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4566 status = 0; 4567 break; 4568 } 4569 usleep_range(10, 20); 4570 retry--; 4571 } while (retry); 4572 4573 if (status) { 4574 i40e_debug(hw, I40E_DEBUG_PHY, 4575 "PHY: Can't write command to external PHY.\n"); 4576 goto phy_read_end; 4577 } 4578 4579 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4580 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4581 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4582 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4583 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4584 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4585 status = I40E_ERR_TIMEOUT; 4586 retry = 1000; 4587 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4588 do { 4589 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4590 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4591 status = 0; 4592 break; 4593 } 4594 usleep_range(10, 20); 4595 retry--; 4596 } while (retry); 4597 4598 if (!status) { 4599 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4600 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4601 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4602 } else { 4603 i40e_debug(hw, I40E_DEBUG_PHY, 4604 "PHY: Can't read register value from external PHY.\n"); 4605 } 4606 4607 phy_read_end: 4608 return status; 4609 } 4610 4611 /** 4612 * i40e_write_phy_register_clause45 4613 * @hw: pointer to the HW structure 4614 * @page: registers page number 4615 * @reg: register address in the page 4616 * @phy_adr: PHY address on MDIO interface 4617 * @value: PHY register value 4618 * 4619 * Writes value to specified PHY register 4620 **/ 4621 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4622 u8 page, u16 reg, u8 phy_addr, u16 value) 4623 { 4624 i40e_status status = I40E_ERR_TIMEOUT; 4625 u32 command = 0; 4626 u16 retry = 1000; 4627 u8 port_num = hw->func_caps.mdio_port_num; 4628 4629 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4630 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4631 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4632 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4633 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4634 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4635 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4636 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4637 do { 4638 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4639 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4640 status = 0; 4641 break; 4642 } 4643 usleep_range(10, 20); 4644 retry--; 4645 } while (retry); 4646 if (status) { 4647 i40e_debug(hw, I40E_DEBUG_PHY, 4648 "PHY: Can't write command to external PHY.\n"); 4649 goto phy_write_end; 4650 } 4651 4652 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4653 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4654 4655 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4656 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4657 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4658 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4659 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4660 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4661 status = I40E_ERR_TIMEOUT; 4662 retry = 1000; 4663 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4664 do { 4665 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4666 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4667 status = 0; 4668 break; 4669 } 4670 usleep_range(10, 20); 4671 retry--; 4672 } while (retry); 4673 4674 phy_write_end: 4675 return status; 4676 } 4677 4678 /** 4679 * i40e_write_phy_register 4680 * @hw: pointer to the HW structure 4681 * @page: registers page number 4682 * @reg: register address in the page 4683 * @phy_adr: PHY address on MDIO interface 4684 * @value: PHY register value 4685 * 4686 * Writes value to specified PHY register 4687 **/ 4688 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4689 u8 page, u16 reg, u8 phy_addr, u16 value) 4690 { 4691 i40e_status status; 4692 4693 switch (hw->device_id) { 4694 case I40E_DEV_ID_1G_BASE_T_X722: 4695 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4696 value); 4697 break; 4698 case I40E_DEV_ID_10G_BASE_T: 4699 case I40E_DEV_ID_10G_BASE_T4: 4700 case I40E_DEV_ID_10G_BASE_T_X722: 4701 case I40E_DEV_ID_25G_B: 4702 case I40E_DEV_ID_25G_SFP28: 4703 status = i40e_write_phy_register_clause45(hw, page, reg, 4704 phy_addr, value); 4705 break; 4706 default: 4707 status = I40E_ERR_UNKNOWN_PHY; 4708 break; 4709 } 4710 4711 return status; 4712 } 4713 4714 /** 4715 * i40e_read_phy_register 4716 * @hw: pointer to the HW structure 4717 * @page: registers page number 4718 * @reg: register address in the page 4719 * @phy_adr: PHY address on MDIO interface 4720 * @value: PHY register value 4721 * 4722 * Reads specified PHY register value 4723 **/ 4724 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4725 u8 page, u16 reg, u8 phy_addr, u16 *value) 4726 { 4727 i40e_status status; 4728 4729 switch (hw->device_id) { 4730 case I40E_DEV_ID_1G_BASE_T_X722: 4731 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4732 value); 4733 break; 4734 case I40E_DEV_ID_10G_BASE_T: 4735 case I40E_DEV_ID_10G_BASE_T4: 4736 case I40E_DEV_ID_10G_BASE_T_X722: 4737 case I40E_DEV_ID_25G_B: 4738 case I40E_DEV_ID_25G_SFP28: 4739 status = i40e_read_phy_register_clause45(hw, page, reg, 4740 phy_addr, value); 4741 break; 4742 default: 4743 status = I40E_ERR_UNKNOWN_PHY; 4744 break; 4745 } 4746 4747 return status; 4748 } 4749 4750 /** 4751 * i40e_get_phy_address 4752 * @hw: pointer to the HW structure 4753 * @dev_num: PHY port num that address we want 4754 * @phy_addr: Returned PHY address 4755 * 4756 * Gets PHY address for current port 4757 **/ 4758 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4759 { 4760 u8 port_num = hw->func_caps.mdio_port_num; 4761 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4762 4763 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4764 } 4765 4766 /** 4767 * i40e_blink_phy_led 4768 * @hw: pointer to the HW structure 4769 * @time: time how long led will blinks in secs 4770 * @interval: gap between LED on and off in msecs 4771 * 4772 * Blinks PHY link LED 4773 **/ 4774 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4775 u32 time, u32 interval) 4776 { 4777 i40e_status status = 0; 4778 u32 i; 4779 u16 led_ctl; 4780 u16 gpio_led_port; 4781 u16 led_reg; 4782 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4783 u8 phy_addr = 0; 4784 u8 port_num; 4785 4786 i = rd32(hw, I40E_PFGEN_PORTNUM); 4787 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4788 phy_addr = i40e_get_phy_address(hw, port_num); 4789 4790 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4791 led_addr++) { 4792 status = i40e_read_phy_register_clause45(hw, 4793 I40E_PHY_COM_REG_PAGE, 4794 led_addr, phy_addr, 4795 &led_reg); 4796 if (status) 4797 goto phy_blinking_end; 4798 led_ctl = led_reg; 4799 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4800 led_reg = 0; 4801 status = i40e_write_phy_register_clause45(hw, 4802 I40E_PHY_COM_REG_PAGE, 4803 led_addr, phy_addr, 4804 led_reg); 4805 if (status) 4806 goto phy_blinking_end; 4807 break; 4808 } 4809 } 4810 4811 if (time > 0 && interval > 0) { 4812 for (i = 0; i < time * 1000; i += interval) { 4813 status = i40e_read_phy_register_clause45(hw, 4814 I40E_PHY_COM_REG_PAGE, 4815 led_addr, phy_addr, &led_reg); 4816 if (status) 4817 goto restore_config; 4818 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4819 led_reg = 0; 4820 else 4821 led_reg = I40E_PHY_LED_MANUAL_ON; 4822 status = i40e_write_phy_register_clause45(hw, 4823 I40E_PHY_COM_REG_PAGE, 4824 led_addr, phy_addr, led_reg); 4825 if (status) 4826 goto restore_config; 4827 msleep(interval); 4828 } 4829 } 4830 4831 restore_config: 4832 status = i40e_write_phy_register_clause45(hw, 4833 I40E_PHY_COM_REG_PAGE, 4834 led_addr, phy_addr, led_ctl); 4835 4836 phy_blinking_end: 4837 return status; 4838 } 4839 4840 /** 4841 * i40e_led_get_phy - return current on/off mode 4842 * @hw: pointer to the hw struct 4843 * @led_addr: address of led register to use 4844 * @val: original value of register to use 4845 * 4846 **/ 4847 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4848 u16 *val) 4849 { 4850 i40e_status status = 0; 4851 u16 gpio_led_port; 4852 u8 phy_addr = 0; 4853 u16 reg_val; 4854 u16 temp_addr; 4855 u8 port_num; 4856 u32 i; 4857 4858 temp_addr = I40E_PHY_LED_PROV_REG_1; 4859 i = rd32(hw, I40E_PFGEN_PORTNUM); 4860 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4861 phy_addr = i40e_get_phy_address(hw, port_num); 4862 4863 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4864 temp_addr++) { 4865 status = i40e_read_phy_register_clause45(hw, 4866 I40E_PHY_COM_REG_PAGE, 4867 temp_addr, phy_addr, 4868 ®_val); 4869 if (status) 4870 return status; 4871 *val = reg_val; 4872 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4873 *led_addr = temp_addr; 4874 break; 4875 } 4876 } 4877 return status; 4878 } 4879 4880 /** 4881 * i40e_led_set_phy 4882 * @hw: pointer to the HW structure 4883 * @on: true or false 4884 * @mode: original val plus bit for set or ignore 4885 * Set led's on or off when controlled by the PHY 4886 * 4887 **/ 4888 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4889 u16 led_addr, u32 mode) 4890 { 4891 i40e_status status = 0; 4892 u16 led_ctl = 0; 4893 u16 led_reg = 0; 4894 u8 phy_addr = 0; 4895 u8 port_num; 4896 u32 i; 4897 4898 i = rd32(hw, I40E_PFGEN_PORTNUM); 4899 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4900 phy_addr = i40e_get_phy_address(hw, port_num); 4901 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4902 led_addr, phy_addr, &led_reg); 4903 if (status) 4904 return status; 4905 led_ctl = led_reg; 4906 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4907 led_reg = 0; 4908 status = i40e_write_phy_register_clause45(hw, 4909 I40E_PHY_COM_REG_PAGE, 4910 led_addr, phy_addr, 4911 led_reg); 4912 if (status) 4913 return status; 4914 } 4915 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4916 led_addr, phy_addr, &led_reg); 4917 if (status) 4918 goto restore_config; 4919 if (on) 4920 led_reg = I40E_PHY_LED_MANUAL_ON; 4921 else 4922 led_reg = 0; 4923 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4924 led_addr, phy_addr, led_reg); 4925 if (status) 4926 goto restore_config; 4927 if (mode & I40E_PHY_LED_MODE_ORIG) { 4928 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4929 status = i40e_write_phy_register_clause45(hw, 4930 I40E_PHY_COM_REG_PAGE, 4931 led_addr, phy_addr, led_ctl); 4932 } 4933 return status; 4934 restore_config: 4935 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4936 led_addr, phy_addr, led_ctl); 4937 return status; 4938 } 4939 4940 /** 4941 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4942 * @hw: pointer to the hw struct 4943 * @reg_addr: register address 4944 * @reg_val: ptr to register value 4945 * @cmd_details: pointer to command details structure or NULL 4946 * 4947 * Use the firmware to read the Rx control register, 4948 * especially useful if the Rx unit is under heavy pressure 4949 **/ 4950 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4951 u32 reg_addr, u32 *reg_val, 4952 struct i40e_asq_cmd_details *cmd_details) 4953 { 4954 struct i40e_aq_desc desc; 4955 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4956 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4957 i40e_status status; 4958 4959 if (!reg_val) 4960 return I40E_ERR_PARAM; 4961 4962 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4963 4964 cmd_resp->address = cpu_to_le32(reg_addr); 4965 4966 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4967 4968 if (status == 0) 4969 *reg_val = le32_to_cpu(cmd_resp->value); 4970 4971 return status; 4972 } 4973 4974 /** 4975 * i40e_read_rx_ctl - read from an Rx control register 4976 * @hw: pointer to the hw struct 4977 * @reg_addr: register address 4978 **/ 4979 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4980 { 4981 i40e_status status = 0; 4982 bool use_register; 4983 int retry = 5; 4984 u32 val = 0; 4985 4986 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 4987 if (!use_register) { 4988 do_retry: 4989 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4990 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4991 usleep_range(1000, 2000); 4992 retry--; 4993 goto do_retry; 4994 } 4995 } 4996 4997 /* if the AQ access failed, try the old-fashioned way */ 4998 if (status || use_register) 4999 val = rd32(hw, reg_addr); 5000 5001 return val; 5002 } 5003 5004 /** 5005 * i40e_aq_rx_ctl_write_register 5006 * @hw: pointer to the hw struct 5007 * @reg_addr: register address 5008 * @reg_val: register value 5009 * @cmd_details: pointer to command details structure or NULL 5010 * 5011 * Use the firmware to write to an Rx control register, 5012 * especially useful if the Rx unit is under heavy pressure 5013 **/ 5014 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5015 u32 reg_addr, u32 reg_val, 5016 struct i40e_asq_cmd_details *cmd_details) 5017 { 5018 struct i40e_aq_desc desc; 5019 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5020 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5021 i40e_status status; 5022 5023 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5024 5025 cmd->address = cpu_to_le32(reg_addr); 5026 cmd->value = cpu_to_le32(reg_val); 5027 5028 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5029 5030 return status; 5031 } 5032 5033 /** 5034 * i40e_write_rx_ctl - write to an Rx control register 5035 * @hw: pointer to the hw struct 5036 * @reg_addr: register address 5037 * @reg_val: register value 5038 **/ 5039 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5040 { 5041 i40e_status status = 0; 5042 bool use_register; 5043 int retry = 5; 5044 5045 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 5046 if (!use_register) { 5047 do_retry: 5048 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5049 reg_val, NULL); 5050 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5051 usleep_range(1000, 2000); 5052 retry--; 5053 goto do_retry; 5054 } 5055 } 5056 5057 /* if the AQ access failed, try the old-fashioned way */ 5058 if (status || use_register) 5059 wr32(hw, reg_addr, reg_val); 5060 } 5061