1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include <linux/avf/virtchnl.h> 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 304 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 305 return; 306 307 len = le16_to_cpu(aq_desc->datalen); 308 309 i40e_debug(hw, mask, 310 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 311 le16_to_cpu(aq_desc->opcode), 312 le16_to_cpu(aq_desc->flags), 313 le16_to_cpu(aq_desc->datalen), 314 le16_to_cpu(aq_desc->retval)); 315 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 316 le32_to_cpu(aq_desc->cookie_high), 317 le32_to_cpu(aq_desc->cookie_low)); 318 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->params.internal.param0), 320 le32_to_cpu(aq_desc->params.internal.param1)); 321 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.external.addr_high), 323 le32_to_cpu(aq_desc->params.external.addr_low)); 324 325 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 326 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 327 if (buf_len < len) 328 len = buf_len; 329 /* write the full 16-byte chunks */ 330 if (hw->debug_mask & mask) { 331 char prefix[27]; 332 333 snprintf(prefix, sizeof(prefix), 334 "i40e %02x:%02x.%x: \t0x", 335 hw->bus.bus_id, 336 hw->bus.device, 337 hw->bus.func); 338 339 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 340 16, 1, buf, len, false); 341 } 342 } 343 } 344 345 /** 346 * i40e_check_asq_alive 347 * @hw: pointer to the hw struct 348 * 349 * Returns true if Queue is enabled else false. 350 **/ 351 bool i40e_check_asq_alive(struct i40e_hw *hw) 352 { 353 if (hw->aq.asq.len) 354 return !!(rd32(hw, hw->aq.asq.len) & 355 I40E_PF_ATQLEN_ATQENABLE_MASK); 356 else 357 return false; 358 } 359 360 /** 361 * i40e_aq_queue_shutdown 362 * @hw: pointer to the hw struct 363 * @unloading: is the driver unloading itself 364 * 365 * Tell the Firmware that we're shutting down the AdminQ and whether 366 * or not the driver is unloading as well. 367 **/ 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 369 bool unloading) 370 { 371 struct i40e_aq_desc desc; 372 struct i40e_aqc_queue_shutdown *cmd = 373 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 374 i40e_status status; 375 376 i40e_fill_default_direct_cmd_desc(&desc, 377 i40e_aqc_opc_queue_shutdown); 378 379 if (unloading) 380 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 381 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 382 383 return status; 384 } 385 386 /** 387 * i40e_aq_get_set_rss_lut 388 * @hw: pointer to the hardware structure 389 * @vsi_id: vsi fw index 390 * @pf_lut: for PF table set true, for VSI table set false 391 * @lut: pointer to the lut buffer provided by the caller 392 * @lut_size: size of the lut buffer 393 * @set: set true to set the table, false to get the table 394 * 395 * Internal function to get or set RSS look up table 396 **/ 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 398 u16 vsi_id, bool pf_lut, 399 u8 *lut, u16 lut_size, 400 bool set) 401 { 402 i40e_status status; 403 struct i40e_aq_desc desc; 404 struct i40e_aqc_get_set_rss_lut *cmd_resp = 405 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 406 407 if (set) 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_set_rss_lut); 410 else 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_get_rss_lut); 413 414 /* Indirect command */ 415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 417 418 cmd_resp->vsi_id = 419 cpu_to_le16((u16)((vsi_id << 420 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 422 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 423 424 if (pf_lut) 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 else 430 cmd_resp->flags |= cpu_to_le16((u16) 431 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 433 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 434 435 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 436 437 return status; 438 } 439 440 /** 441 * i40e_aq_get_rss_lut 442 * @hw: pointer to the hardware structure 443 * @vsi_id: vsi fw index 444 * @pf_lut: for PF table set true, for VSI table set false 445 * @lut: pointer to the lut buffer provided by the caller 446 * @lut_size: size of the lut buffer 447 * 448 * get the RSS lookup table, PF or VSI type 449 **/ 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 451 bool pf_lut, u8 *lut, u16 lut_size) 452 { 453 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 454 false); 455 } 456 457 /** 458 * i40e_aq_set_rss_lut 459 * @hw: pointer to the hardware structure 460 * @vsi_id: vsi fw index 461 * @pf_lut: for PF table set true, for VSI table set false 462 * @lut: pointer to the lut buffer provided by the caller 463 * @lut_size: size of the lut buffer 464 * 465 * set the RSS lookup table, PF or VSI type 466 **/ 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 468 bool pf_lut, u8 *lut, u16 lut_size) 469 { 470 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 471 } 472 473 /** 474 * i40e_aq_get_set_rss_key 475 * @hw: pointer to the hw struct 476 * @vsi_id: vsi fw index 477 * @key: pointer to key info struct 478 * @set: set true to set the key, false to get the key 479 * 480 * get the RSS key per VSI 481 **/ 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 483 u16 vsi_id, 484 struct i40e_aqc_get_set_rss_key_data *key, 485 bool set) 486 { 487 i40e_status status; 488 struct i40e_aq_desc desc; 489 struct i40e_aqc_get_set_rss_key *cmd_resp = 490 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 491 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 492 493 if (set) 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_set_rss_key); 496 else 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_get_rss_key); 499 500 /* Indirect command */ 501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 503 504 cmd_resp->vsi_id = 505 cpu_to_le16((u16)((vsi_id << 506 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 507 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 508 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 509 510 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 511 512 return status; 513 } 514 515 /** 516 * i40e_aq_get_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 **/ 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key) 525 { 526 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 527 } 528 529 /** 530 * i40e_aq_set_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 * set the RSS key per VSI 536 **/ 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 538 u16 vsi_id, 539 struct i40e_aqc_get_set_rss_key_data *key) 540 { 541 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 542 } 543 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 545 * hardware to a bit-field that can be used by SW to more easily determine the 546 * packet type. 547 * 548 * Macros are used to shorten the table lines and make this table human 549 * readable. 550 * 551 * We store the PTYPE in the top byte of the bit field - this is just so that 552 * we can check that the table doesn't have a row missing, as the index into 553 * the table should be the PTYPE. 554 * 555 * Typical work flow: 556 * 557 * IF NOT i40e_ptype_lookup[ptype].known 558 * THEN 559 * Packet is unknown 560 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 561 * Use the rest of the fields to look at the tunnels, inner protocols, etc 562 * ELSE 563 * Use the enum i40e_rx_l2_ptype to decode the packet type 564 * ENDIF 565 */ 566 567 /* macro to make the table lines short */ 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 569 { PTYPE, \ 570 1, \ 571 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 572 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 573 I40E_RX_PTYPE_##OUTER_FRAG, \ 574 I40E_RX_PTYPE_TUNNEL_##T, \ 575 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 576 I40E_RX_PTYPE_##TEF, \ 577 I40E_RX_PTYPE_INNER_PROT_##I, \ 578 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 579 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 581 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 582 583 /* shorter macros makes the table fit but are terse */ 584 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 585 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 586 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 587 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 590 /* L2 Packet types */ 591 I40E_PTT_UNUSED_ENTRY(0), 592 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 594 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT_UNUSED_ENTRY(4), 596 I40E_PTT_UNUSED_ENTRY(5), 597 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT_UNUSED_ENTRY(8), 600 I40E_PTT_UNUSED_ENTRY(9), 601 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 603 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 614 /* Non Tunneled IPv4 */ 615 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 616 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 617 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(25), 619 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 620 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 621 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 622 623 /* IPv4 --> IPv4 */ 624 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 625 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 626 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(32), 628 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 629 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 630 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 631 632 /* IPv4 --> IPv6 */ 633 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 634 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 635 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 636 I40E_PTT_UNUSED_ENTRY(39), 637 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 638 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 639 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 640 641 /* IPv4 --> GRE/NAT */ 642 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 643 644 /* IPv4 --> GRE/NAT --> IPv4 */ 645 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(47), 649 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> GRE/NAT --> IPv6 */ 654 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(54), 658 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT --> MAC */ 663 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 666 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(62), 670 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 675 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(69), 679 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 684 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 687 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(77), 691 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 696 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(84), 700 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 703 704 /* Non Tunneled IPv6 */ 705 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 706 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 707 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 708 I40E_PTT_UNUSED_ENTRY(91), 709 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 710 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 711 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 712 713 /* IPv6 --> IPv4 */ 714 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 715 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 716 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 717 I40E_PTT_UNUSED_ENTRY(98), 718 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 719 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 720 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 721 722 /* IPv6 --> IPv6 */ 723 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 724 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 725 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(105), 727 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 728 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 729 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 730 731 /* IPv6 --> GRE/NAT */ 732 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 733 734 /* IPv6 --> GRE/NAT -> IPv4 */ 735 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(113), 739 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> GRE/NAT -> IPv6 */ 744 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(120), 748 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT -> MAC */ 753 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 756 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(128), 760 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 765 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(135), 769 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 774 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 777 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(143), 781 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 786 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(150), 790 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 793 794 /* unused entries */ 795 I40E_PTT_UNUSED_ENTRY(154), 796 I40E_PTT_UNUSED_ENTRY(155), 797 I40E_PTT_UNUSED_ENTRY(156), 798 I40E_PTT_UNUSED_ENTRY(157), 799 I40E_PTT_UNUSED_ENTRY(158), 800 I40E_PTT_UNUSED_ENTRY(159), 801 802 I40E_PTT_UNUSED_ENTRY(160), 803 I40E_PTT_UNUSED_ENTRY(161), 804 I40E_PTT_UNUSED_ENTRY(162), 805 I40E_PTT_UNUSED_ENTRY(163), 806 I40E_PTT_UNUSED_ENTRY(164), 807 I40E_PTT_UNUSED_ENTRY(165), 808 I40E_PTT_UNUSED_ENTRY(166), 809 I40E_PTT_UNUSED_ENTRY(167), 810 I40E_PTT_UNUSED_ENTRY(168), 811 I40E_PTT_UNUSED_ENTRY(169), 812 813 I40E_PTT_UNUSED_ENTRY(170), 814 I40E_PTT_UNUSED_ENTRY(171), 815 I40E_PTT_UNUSED_ENTRY(172), 816 I40E_PTT_UNUSED_ENTRY(173), 817 I40E_PTT_UNUSED_ENTRY(174), 818 I40E_PTT_UNUSED_ENTRY(175), 819 I40E_PTT_UNUSED_ENTRY(176), 820 I40E_PTT_UNUSED_ENTRY(177), 821 I40E_PTT_UNUSED_ENTRY(178), 822 I40E_PTT_UNUSED_ENTRY(179), 823 824 I40E_PTT_UNUSED_ENTRY(180), 825 I40E_PTT_UNUSED_ENTRY(181), 826 I40E_PTT_UNUSED_ENTRY(182), 827 I40E_PTT_UNUSED_ENTRY(183), 828 I40E_PTT_UNUSED_ENTRY(184), 829 I40E_PTT_UNUSED_ENTRY(185), 830 I40E_PTT_UNUSED_ENTRY(186), 831 I40E_PTT_UNUSED_ENTRY(187), 832 I40E_PTT_UNUSED_ENTRY(188), 833 I40E_PTT_UNUSED_ENTRY(189), 834 835 I40E_PTT_UNUSED_ENTRY(190), 836 I40E_PTT_UNUSED_ENTRY(191), 837 I40E_PTT_UNUSED_ENTRY(192), 838 I40E_PTT_UNUSED_ENTRY(193), 839 I40E_PTT_UNUSED_ENTRY(194), 840 I40E_PTT_UNUSED_ENTRY(195), 841 I40E_PTT_UNUSED_ENTRY(196), 842 I40E_PTT_UNUSED_ENTRY(197), 843 I40E_PTT_UNUSED_ENTRY(198), 844 I40E_PTT_UNUSED_ENTRY(199), 845 846 I40E_PTT_UNUSED_ENTRY(200), 847 I40E_PTT_UNUSED_ENTRY(201), 848 I40E_PTT_UNUSED_ENTRY(202), 849 I40E_PTT_UNUSED_ENTRY(203), 850 I40E_PTT_UNUSED_ENTRY(204), 851 I40E_PTT_UNUSED_ENTRY(205), 852 I40E_PTT_UNUSED_ENTRY(206), 853 I40E_PTT_UNUSED_ENTRY(207), 854 I40E_PTT_UNUSED_ENTRY(208), 855 I40E_PTT_UNUSED_ENTRY(209), 856 857 I40E_PTT_UNUSED_ENTRY(210), 858 I40E_PTT_UNUSED_ENTRY(211), 859 I40E_PTT_UNUSED_ENTRY(212), 860 I40E_PTT_UNUSED_ENTRY(213), 861 I40E_PTT_UNUSED_ENTRY(214), 862 I40E_PTT_UNUSED_ENTRY(215), 863 I40E_PTT_UNUSED_ENTRY(216), 864 I40E_PTT_UNUSED_ENTRY(217), 865 I40E_PTT_UNUSED_ENTRY(218), 866 I40E_PTT_UNUSED_ENTRY(219), 867 868 I40E_PTT_UNUSED_ENTRY(220), 869 I40E_PTT_UNUSED_ENTRY(221), 870 I40E_PTT_UNUSED_ENTRY(222), 871 I40E_PTT_UNUSED_ENTRY(223), 872 I40E_PTT_UNUSED_ENTRY(224), 873 I40E_PTT_UNUSED_ENTRY(225), 874 I40E_PTT_UNUSED_ENTRY(226), 875 I40E_PTT_UNUSED_ENTRY(227), 876 I40E_PTT_UNUSED_ENTRY(228), 877 I40E_PTT_UNUSED_ENTRY(229), 878 879 I40E_PTT_UNUSED_ENTRY(230), 880 I40E_PTT_UNUSED_ENTRY(231), 881 I40E_PTT_UNUSED_ENTRY(232), 882 I40E_PTT_UNUSED_ENTRY(233), 883 I40E_PTT_UNUSED_ENTRY(234), 884 I40E_PTT_UNUSED_ENTRY(235), 885 I40E_PTT_UNUSED_ENTRY(236), 886 I40E_PTT_UNUSED_ENTRY(237), 887 I40E_PTT_UNUSED_ENTRY(238), 888 I40E_PTT_UNUSED_ENTRY(239), 889 890 I40E_PTT_UNUSED_ENTRY(240), 891 I40E_PTT_UNUSED_ENTRY(241), 892 I40E_PTT_UNUSED_ENTRY(242), 893 I40E_PTT_UNUSED_ENTRY(243), 894 I40E_PTT_UNUSED_ENTRY(244), 895 I40E_PTT_UNUSED_ENTRY(245), 896 I40E_PTT_UNUSED_ENTRY(246), 897 I40E_PTT_UNUSED_ENTRY(247), 898 I40E_PTT_UNUSED_ENTRY(248), 899 I40E_PTT_UNUSED_ENTRY(249), 900 901 I40E_PTT_UNUSED_ENTRY(250), 902 I40E_PTT_UNUSED_ENTRY(251), 903 I40E_PTT_UNUSED_ENTRY(252), 904 I40E_PTT_UNUSED_ENTRY(253), 905 I40E_PTT_UNUSED_ENTRY(254), 906 I40E_PTT_UNUSED_ENTRY(255) 907 }; 908 909 /** 910 * i40e_init_shared_code - Initialize the shared code 911 * @hw: pointer to hardware structure 912 * 913 * This assigns the MAC type and PHY code and inits the NVM. 914 * Does not touch the hardware. This function must be called prior to any 915 * other function in the shared code. The i40e_hw structure should be 916 * memset to 0 prior to calling this function. The following fields in 917 * hw structure should be filled in prior to calling this function: 918 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 919 * subsystem_vendor_id, and revision_id 920 **/ 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 922 { 923 i40e_status status = 0; 924 u32 port, ari, func_rid; 925 926 i40e_set_mac_type(hw); 927 928 switch (hw->mac.type) { 929 case I40E_MAC_XL710: 930 case I40E_MAC_X722: 931 break; 932 default: 933 return I40E_ERR_DEVICE_NOT_SUPPORTED; 934 } 935 936 hw->phy.get_link_info = true; 937 938 /* Determine port number and PF number*/ 939 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 940 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 941 hw->port = (u8)port; 942 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 943 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 944 func_rid = rd32(hw, I40E_PF_FUNC_RID); 945 if (ari) 946 hw->pf_id = (u8)(func_rid & 0xff); 947 else 948 hw->pf_id = (u8)(func_rid & 0x7); 949 950 if (hw->mac.type == I40E_MAC_X722) 951 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 952 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 953 954 status = i40e_init_nvm(hw); 955 return status; 956 } 957 958 /** 959 * i40e_aq_mac_address_read - Retrieve the MAC addresses 960 * @hw: pointer to the hw struct 961 * @flags: a return indicator of what addresses were added to the addr store 962 * @addrs: the requestor's mac addr store 963 * @cmd_details: pointer to command details structure or NULL 964 **/ 965 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 966 u16 *flags, 967 struct i40e_aqc_mac_address_read_data *addrs, 968 struct i40e_asq_cmd_details *cmd_details) 969 { 970 struct i40e_aq_desc desc; 971 struct i40e_aqc_mac_address_read *cmd_data = 972 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 973 i40e_status status; 974 975 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 976 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 977 978 status = i40e_asq_send_command(hw, &desc, addrs, 979 sizeof(*addrs), cmd_details); 980 *flags = le16_to_cpu(cmd_data->command_flags); 981 982 return status; 983 } 984 985 /** 986 * i40e_aq_mac_address_write - Change the MAC addresses 987 * @hw: pointer to the hw struct 988 * @flags: indicates which MAC to be written 989 * @mac_addr: address to write 990 * @cmd_details: pointer to command details structure or NULL 991 **/ 992 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 993 u16 flags, u8 *mac_addr, 994 struct i40e_asq_cmd_details *cmd_details) 995 { 996 struct i40e_aq_desc desc; 997 struct i40e_aqc_mac_address_write *cmd_data = 998 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 999 i40e_status status; 1000 1001 i40e_fill_default_direct_cmd_desc(&desc, 1002 i40e_aqc_opc_mac_address_write); 1003 cmd_data->command_flags = cpu_to_le16(flags); 1004 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1005 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1006 ((u32)mac_addr[3] << 16) | 1007 ((u32)mac_addr[4] << 8) | 1008 mac_addr[5]); 1009 1010 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1011 1012 return status; 1013 } 1014 1015 /** 1016 * i40e_get_mac_addr - get MAC address 1017 * @hw: pointer to the HW structure 1018 * @mac_addr: pointer to MAC address 1019 * 1020 * Reads the adapter's MAC address from register 1021 **/ 1022 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1023 { 1024 struct i40e_aqc_mac_address_read_data addrs; 1025 i40e_status status; 1026 u16 flags = 0; 1027 1028 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1029 1030 if (flags & I40E_AQC_LAN_ADDR_VALID) 1031 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1032 1033 return status; 1034 } 1035 1036 /** 1037 * i40e_get_port_mac_addr - get Port MAC address 1038 * @hw: pointer to the HW structure 1039 * @mac_addr: pointer to Port MAC address 1040 * 1041 * Reads the adapter's Port MAC address 1042 **/ 1043 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1044 { 1045 struct i40e_aqc_mac_address_read_data addrs; 1046 i40e_status status; 1047 u16 flags = 0; 1048 1049 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1050 if (status) 1051 return status; 1052 1053 if (flags & I40E_AQC_PORT_ADDR_VALID) 1054 ether_addr_copy(mac_addr, addrs.port_mac); 1055 else 1056 status = I40E_ERR_INVALID_MAC_ADDR; 1057 1058 return status; 1059 } 1060 1061 /** 1062 * i40e_pre_tx_queue_cfg - pre tx queue configure 1063 * @hw: pointer to the HW structure 1064 * @queue: target PF queue index 1065 * @enable: state change request 1066 * 1067 * Handles hw requirement to indicate intention to enable 1068 * or disable target queue. 1069 **/ 1070 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1071 { 1072 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1073 u32 reg_block = 0; 1074 u32 reg_val; 1075 1076 if (abs_queue_idx >= 128) { 1077 reg_block = abs_queue_idx / 128; 1078 abs_queue_idx %= 128; 1079 } 1080 1081 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1082 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1083 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1084 1085 if (enable) 1086 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1087 else 1088 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1089 1090 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1091 } 1092 1093 /** 1094 * i40e_read_pba_string - Reads part number string from EEPROM 1095 * @hw: pointer to hardware structure 1096 * @pba_num: stores the part number string from the EEPROM 1097 * @pba_num_size: part number string buffer length 1098 * 1099 * Reads the part number string from the EEPROM. 1100 **/ 1101 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1102 u32 pba_num_size) 1103 { 1104 i40e_status status = 0; 1105 u16 pba_word = 0; 1106 u16 pba_size = 0; 1107 u16 pba_ptr = 0; 1108 u16 i = 0; 1109 1110 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1111 if (status || (pba_word != 0xFAFA)) { 1112 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1113 return status; 1114 } 1115 1116 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1117 if (status) { 1118 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1119 return status; 1120 } 1121 1122 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1123 if (status) { 1124 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1125 return status; 1126 } 1127 1128 /* Subtract one to get PBA word count (PBA Size word is included in 1129 * total size) 1130 */ 1131 pba_size--; 1132 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1133 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1134 return I40E_ERR_PARAM; 1135 } 1136 1137 for (i = 0; i < pba_size; i++) { 1138 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1139 if (status) { 1140 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1141 return status; 1142 } 1143 1144 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1145 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1146 } 1147 pba_num[(pba_size * 2)] = '\0'; 1148 1149 return status; 1150 } 1151 1152 /** 1153 * i40e_get_media_type - Gets media type 1154 * @hw: pointer to the hardware structure 1155 **/ 1156 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1157 { 1158 enum i40e_media_type media; 1159 1160 switch (hw->phy.link_info.phy_type) { 1161 case I40E_PHY_TYPE_10GBASE_SR: 1162 case I40E_PHY_TYPE_10GBASE_LR: 1163 case I40E_PHY_TYPE_1000BASE_SX: 1164 case I40E_PHY_TYPE_1000BASE_LX: 1165 case I40E_PHY_TYPE_40GBASE_SR4: 1166 case I40E_PHY_TYPE_40GBASE_LR4: 1167 case I40E_PHY_TYPE_25GBASE_LR: 1168 case I40E_PHY_TYPE_25GBASE_SR: 1169 media = I40E_MEDIA_TYPE_FIBER; 1170 break; 1171 case I40E_PHY_TYPE_100BASE_TX: 1172 case I40E_PHY_TYPE_1000BASE_T: 1173 case I40E_PHY_TYPE_10GBASE_T: 1174 media = I40E_MEDIA_TYPE_BASET; 1175 break; 1176 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1177 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1178 case I40E_PHY_TYPE_10GBASE_CR1: 1179 case I40E_PHY_TYPE_40GBASE_CR4: 1180 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1181 case I40E_PHY_TYPE_40GBASE_AOC: 1182 case I40E_PHY_TYPE_10GBASE_AOC: 1183 case I40E_PHY_TYPE_25GBASE_CR: 1184 case I40E_PHY_TYPE_25GBASE_AOC: 1185 case I40E_PHY_TYPE_25GBASE_ACC: 1186 media = I40E_MEDIA_TYPE_DA; 1187 break; 1188 case I40E_PHY_TYPE_1000BASE_KX: 1189 case I40E_PHY_TYPE_10GBASE_KX4: 1190 case I40E_PHY_TYPE_10GBASE_KR: 1191 case I40E_PHY_TYPE_40GBASE_KR4: 1192 case I40E_PHY_TYPE_20GBASE_KR2: 1193 case I40E_PHY_TYPE_25GBASE_KR: 1194 media = I40E_MEDIA_TYPE_BACKPLANE; 1195 break; 1196 case I40E_PHY_TYPE_SGMII: 1197 case I40E_PHY_TYPE_XAUI: 1198 case I40E_PHY_TYPE_XFI: 1199 case I40E_PHY_TYPE_XLAUI: 1200 case I40E_PHY_TYPE_XLPPI: 1201 default: 1202 media = I40E_MEDIA_TYPE_UNKNOWN; 1203 break; 1204 } 1205 1206 return media; 1207 } 1208 1209 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1210 #define I40E_PF_RESET_WAIT_COUNT 200 1211 /** 1212 * i40e_pf_reset - Reset the PF 1213 * @hw: pointer to the hardware structure 1214 * 1215 * Assuming someone else has triggered a global reset, 1216 * assure the global reset is complete and then reset the PF 1217 **/ 1218 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1219 { 1220 u32 cnt = 0; 1221 u32 cnt1 = 0; 1222 u32 reg = 0; 1223 u32 grst_del; 1224 1225 /* Poll for Global Reset steady state in case of recent GRST. 1226 * The grst delay value is in 100ms units, and we'll wait a 1227 * couple counts longer to be sure we don't just miss the end. 1228 */ 1229 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1230 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1231 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1232 1233 /* It can take upto 15 secs for GRST steady state. 1234 * Bump it to 16 secs max to be safe. 1235 */ 1236 grst_del = grst_del * 20; 1237 1238 for (cnt = 0; cnt < grst_del; cnt++) { 1239 reg = rd32(hw, I40E_GLGEN_RSTAT); 1240 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1241 break; 1242 msleep(100); 1243 } 1244 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1245 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1246 return I40E_ERR_RESET_FAILED; 1247 } 1248 1249 /* Now Wait for the FW to be ready */ 1250 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1251 reg = rd32(hw, I40E_GLNVM_ULD); 1252 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1253 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1254 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1255 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1256 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1257 break; 1258 } 1259 usleep_range(10000, 20000); 1260 } 1261 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1262 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1263 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1264 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1265 return I40E_ERR_RESET_FAILED; 1266 } 1267 1268 /* If there was a Global Reset in progress when we got here, 1269 * we don't need to do the PF Reset 1270 */ 1271 if (!cnt) { 1272 u32 reg2 = 0; 1273 if (hw->revision_id == 0) 1274 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1275 else 1276 cnt = I40E_PF_RESET_WAIT_COUNT; 1277 reg = rd32(hw, I40E_PFGEN_CTRL); 1278 wr32(hw, I40E_PFGEN_CTRL, 1279 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1280 for (; cnt; cnt--) { 1281 reg = rd32(hw, I40E_PFGEN_CTRL); 1282 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1283 break; 1284 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1285 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1286 hw_dbg(hw, "Core reset upcoming. Skipping PF reset request.\n"); 1287 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1288 return I40E_ERR_NOT_READY; 1289 } 1290 usleep_range(1000, 2000); 1291 } 1292 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1293 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1294 return I40E_ERR_RESET_FAILED; 1295 } 1296 } 1297 1298 i40e_clear_pxe_mode(hw); 1299 1300 return 0; 1301 } 1302 1303 /** 1304 * i40e_clear_hw - clear out any left over hw state 1305 * @hw: pointer to the hw struct 1306 * 1307 * Clear queues and interrupts, typically called at init time, 1308 * but after the capabilities have been found so we know how many 1309 * queues and msix vectors have been allocated. 1310 **/ 1311 void i40e_clear_hw(struct i40e_hw *hw) 1312 { 1313 u32 num_queues, base_queue; 1314 u32 num_pf_int; 1315 u32 num_vf_int; 1316 u32 num_vfs; 1317 u32 i, j; 1318 u32 val; 1319 u32 eol = 0x7ff; 1320 1321 /* get number of interrupts, queues, and VFs */ 1322 val = rd32(hw, I40E_GLPCI_CNF2); 1323 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1324 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1325 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1326 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1327 1328 val = rd32(hw, I40E_PFLAN_QALLOC); 1329 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1330 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1331 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1332 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1333 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1334 num_queues = (j - base_queue) + 1; 1335 else 1336 num_queues = 0; 1337 1338 val = rd32(hw, I40E_PF_VT_PFALLOC); 1339 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1340 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1341 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1342 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1343 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1344 num_vfs = (j - i) + 1; 1345 else 1346 num_vfs = 0; 1347 1348 /* stop all the interrupts */ 1349 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1350 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1351 for (i = 0; i < num_pf_int - 2; i++) 1352 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1353 1354 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1355 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1356 wr32(hw, I40E_PFINT_LNKLST0, val); 1357 for (i = 0; i < num_pf_int - 2; i++) 1358 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1359 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1360 for (i = 0; i < num_vfs; i++) 1361 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1362 for (i = 0; i < num_vf_int - 2; i++) 1363 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1364 1365 /* warn the HW of the coming Tx disables */ 1366 for (i = 0; i < num_queues; i++) { 1367 u32 abs_queue_idx = base_queue + i; 1368 u32 reg_block = 0; 1369 1370 if (abs_queue_idx >= 128) { 1371 reg_block = abs_queue_idx / 128; 1372 abs_queue_idx %= 128; 1373 } 1374 1375 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1376 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1377 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1378 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1379 1380 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1381 } 1382 udelay(400); 1383 1384 /* stop all the queues */ 1385 for (i = 0; i < num_queues; i++) { 1386 wr32(hw, I40E_QINT_TQCTL(i), 0); 1387 wr32(hw, I40E_QTX_ENA(i), 0); 1388 wr32(hw, I40E_QINT_RQCTL(i), 0); 1389 wr32(hw, I40E_QRX_ENA(i), 0); 1390 } 1391 1392 /* short wait for all queue disables to settle */ 1393 udelay(50); 1394 } 1395 1396 /** 1397 * i40e_clear_pxe_mode - clear pxe operations mode 1398 * @hw: pointer to the hw struct 1399 * 1400 * Make sure all PXE mode settings are cleared, including things 1401 * like descriptor fetch/write-back mode. 1402 **/ 1403 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1404 { 1405 u32 reg; 1406 1407 if (i40e_check_asq_alive(hw)) 1408 i40e_aq_clear_pxe_mode(hw, NULL); 1409 1410 /* Clear single descriptor fetch/write-back mode */ 1411 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1412 1413 if (hw->revision_id == 0) { 1414 /* As a work around clear PXE_MODE instead of setting it */ 1415 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1416 } else { 1417 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1418 } 1419 } 1420 1421 /** 1422 * i40e_led_is_mine - helper to find matching led 1423 * @hw: pointer to the hw struct 1424 * @idx: index into GPIO registers 1425 * 1426 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1427 */ 1428 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1429 { 1430 u32 gpio_val = 0; 1431 u32 port; 1432 1433 if (!hw->func_caps.led[idx]) 1434 return 0; 1435 1436 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1437 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1438 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1439 1440 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1441 * if it is not our port then ignore 1442 */ 1443 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1444 (port != hw->port)) 1445 return 0; 1446 1447 return gpio_val; 1448 } 1449 1450 #define I40E_COMBINED_ACTIVITY 0xA 1451 #define I40E_FILTER_ACTIVITY 0xE 1452 #define I40E_LINK_ACTIVITY 0xC 1453 #define I40E_MAC_ACTIVITY 0xD 1454 #define I40E_LED0 22 1455 1456 /** 1457 * i40e_led_get - return current on/off mode 1458 * @hw: pointer to the hw struct 1459 * 1460 * The value returned is the 'mode' field as defined in the 1461 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1462 * values are variations of possible behaviors relating to 1463 * blink, link, and wire. 1464 **/ 1465 u32 i40e_led_get(struct i40e_hw *hw) 1466 { 1467 u32 current_mode = 0; 1468 u32 mode = 0; 1469 int i; 1470 1471 /* as per the documentation GPIO 22-29 are the LED 1472 * GPIO pins named LED0..LED7 1473 */ 1474 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1475 u32 gpio_val = i40e_led_is_mine(hw, i); 1476 1477 if (!gpio_val) 1478 continue; 1479 1480 /* ignore gpio LED src mode entries related to the activity 1481 * LEDs 1482 */ 1483 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1484 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1485 switch (current_mode) { 1486 case I40E_COMBINED_ACTIVITY: 1487 case I40E_FILTER_ACTIVITY: 1488 case I40E_MAC_ACTIVITY: 1489 continue; 1490 default: 1491 break; 1492 } 1493 1494 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1495 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1496 break; 1497 } 1498 1499 return mode; 1500 } 1501 1502 /** 1503 * i40e_led_set - set new on/off mode 1504 * @hw: pointer to the hw struct 1505 * @mode: 0=off, 0xf=on (else see manual for mode details) 1506 * @blink: true if the LED should blink when on, false if steady 1507 * 1508 * if this function is used to turn on the blink it should 1509 * be used to disable the blink when restoring the original state. 1510 **/ 1511 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1512 { 1513 u32 current_mode = 0; 1514 int i; 1515 1516 if (mode & 0xfffffff0) 1517 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1518 1519 /* as per the documentation GPIO 22-29 are the LED 1520 * GPIO pins named LED0..LED7 1521 */ 1522 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1523 u32 gpio_val = i40e_led_is_mine(hw, i); 1524 1525 if (!gpio_val) 1526 continue; 1527 1528 /* ignore gpio LED src mode entries related to the activity 1529 * LEDs 1530 */ 1531 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1532 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1533 switch (current_mode) { 1534 case I40E_COMBINED_ACTIVITY: 1535 case I40E_FILTER_ACTIVITY: 1536 case I40E_MAC_ACTIVITY: 1537 continue; 1538 default: 1539 break; 1540 } 1541 1542 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1543 /* this & is a bit of paranoia, but serves as a range check */ 1544 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1545 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1546 1547 if (mode == I40E_LINK_ACTIVITY) 1548 blink = false; 1549 1550 if (blink) 1551 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1552 else 1553 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1554 1555 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1556 break; 1557 } 1558 } 1559 1560 /* Admin command wrappers */ 1561 1562 /** 1563 * i40e_aq_get_phy_capabilities 1564 * @hw: pointer to the hw struct 1565 * @abilities: structure for PHY capabilities to be filled 1566 * @qualified_modules: report Qualified Modules 1567 * @report_init: report init capabilities (active are default) 1568 * @cmd_details: pointer to command details structure or NULL 1569 * 1570 * Returns the various PHY abilities supported on the Port. 1571 **/ 1572 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1573 bool qualified_modules, bool report_init, 1574 struct i40e_aq_get_phy_abilities_resp *abilities, 1575 struct i40e_asq_cmd_details *cmd_details) 1576 { 1577 struct i40e_aq_desc desc; 1578 i40e_status status; 1579 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1580 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1581 1582 if (!abilities) 1583 return I40E_ERR_PARAM; 1584 1585 do { 1586 i40e_fill_default_direct_cmd_desc(&desc, 1587 i40e_aqc_opc_get_phy_abilities); 1588 1589 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1590 if (abilities_size > I40E_AQ_LARGE_BUF) 1591 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1592 1593 if (qualified_modules) 1594 desc.params.external.param0 |= 1595 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1596 1597 if (report_init) 1598 desc.params.external.param0 |= 1599 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1600 1601 status = i40e_asq_send_command(hw, &desc, abilities, 1602 abilities_size, cmd_details); 1603 1604 if (status) 1605 break; 1606 1607 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1608 status = I40E_ERR_UNKNOWN_PHY; 1609 break; 1610 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1611 usleep_range(1000, 2000); 1612 total_delay++; 1613 status = I40E_ERR_TIMEOUT; 1614 } 1615 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1616 (total_delay < max_delay)); 1617 1618 if (status) 1619 return status; 1620 1621 if (report_init) { 1622 if (hw->mac.type == I40E_MAC_XL710 && 1623 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1624 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1625 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1626 } else { 1627 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1628 hw->phy.phy_types |= 1629 ((u64)abilities->phy_type_ext << 32); 1630 } 1631 } 1632 1633 return status; 1634 } 1635 1636 /** 1637 * i40e_aq_set_phy_config 1638 * @hw: pointer to the hw struct 1639 * @config: structure with PHY configuration to be set 1640 * @cmd_details: pointer to command details structure or NULL 1641 * 1642 * Set the various PHY configuration parameters 1643 * supported on the Port.One or more of the Set PHY config parameters may be 1644 * ignored in an MFP mode as the PF may not have the privilege to set some 1645 * of the PHY Config parameters. This status will be indicated by the 1646 * command response. 1647 **/ 1648 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1649 struct i40e_aq_set_phy_config *config, 1650 struct i40e_asq_cmd_details *cmd_details) 1651 { 1652 struct i40e_aq_desc desc; 1653 struct i40e_aq_set_phy_config *cmd = 1654 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1655 enum i40e_status_code status; 1656 1657 if (!config) 1658 return I40E_ERR_PARAM; 1659 1660 i40e_fill_default_direct_cmd_desc(&desc, 1661 i40e_aqc_opc_set_phy_config); 1662 1663 *cmd = *config; 1664 1665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1666 1667 return status; 1668 } 1669 1670 /** 1671 * i40e_set_fc 1672 * @hw: pointer to the hw struct 1673 * 1674 * Set the requested flow control mode using set_phy_config. 1675 **/ 1676 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1677 bool atomic_restart) 1678 { 1679 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1680 struct i40e_aq_get_phy_abilities_resp abilities; 1681 struct i40e_aq_set_phy_config config; 1682 enum i40e_status_code status; 1683 u8 pause_mask = 0x0; 1684 1685 *aq_failures = 0x0; 1686 1687 switch (fc_mode) { 1688 case I40E_FC_FULL: 1689 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1690 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1691 break; 1692 case I40E_FC_RX_PAUSE: 1693 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1694 break; 1695 case I40E_FC_TX_PAUSE: 1696 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1697 break; 1698 default: 1699 break; 1700 } 1701 1702 /* Get the current phy config */ 1703 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1704 NULL); 1705 if (status) { 1706 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1707 return status; 1708 } 1709 1710 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1711 /* clear the old pause settings */ 1712 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1713 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1714 /* set the new abilities */ 1715 config.abilities |= pause_mask; 1716 /* If the abilities have changed, then set the new config */ 1717 if (config.abilities != abilities.abilities) { 1718 /* Auto restart link so settings take effect */ 1719 if (atomic_restart) 1720 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1721 /* Copy over all the old settings */ 1722 config.phy_type = abilities.phy_type; 1723 config.phy_type_ext = abilities.phy_type_ext; 1724 config.link_speed = abilities.link_speed; 1725 config.eee_capability = abilities.eee_capability; 1726 config.eeer = abilities.eeer_val; 1727 config.low_power_ctrl = abilities.d3_lpan; 1728 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1729 I40E_AQ_PHY_FEC_CONFIG_MASK; 1730 status = i40e_aq_set_phy_config(hw, &config, NULL); 1731 1732 if (status) 1733 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1734 } 1735 /* Update the link info */ 1736 status = i40e_update_link_info(hw); 1737 if (status) { 1738 /* Wait a little bit (on 40G cards it sometimes takes a really 1739 * long time for link to come back from the atomic reset) 1740 * and try once more 1741 */ 1742 msleep(1000); 1743 status = i40e_update_link_info(hw); 1744 } 1745 if (status) 1746 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1747 1748 return status; 1749 } 1750 1751 /** 1752 * i40e_aq_clear_pxe_mode 1753 * @hw: pointer to the hw struct 1754 * @cmd_details: pointer to command details structure or NULL 1755 * 1756 * Tell the firmware that the driver is taking over from PXE 1757 **/ 1758 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1759 struct i40e_asq_cmd_details *cmd_details) 1760 { 1761 i40e_status status; 1762 struct i40e_aq_desc desc; 1763 struct i40e_aqc_clear_pxe *cmd = 1764 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1765 1766 i40e_fill_default_direct_cmd_desc(&desc, 1767 i40e_aqc_opc_clear_pxe_mode); 1768 1769 cmd->rx_cnt = 0x2; 1770 1771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1772 1773 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1774 1775 return status; 1776 } 1777 1778 /** 1779 * i40e_aq_set_link_restart_an 1780 * @hw: pointer to the hw struct 1781 * @enable_link: if true: enable link, if false: disable link 1782 * @cmd_details: pointer to command details structure or NULL 1783 * 1784 * Sets up the link and restarts the Auto-Negotiation over the link. 1785 **/ 1786 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1787 bool enable_link, 1788 struct i40e_asq_cmd_details *cmd_details) 1789 { 1790 struct i40e_aq_desc desc; 1791 struct i40e_aqc_set_link_restart_an *cmd = 1792 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1793 i40e_status status; 1794 1795 i40e_fill_default_direct_cmd_desc(&desc, 1796 i40e_aqc_opc_set_link_restart_an); 1797 1798 cmd->command = I40E_AQ_PHY_RESTART_AN; 1799 if (enable_link) 1800 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1801 else 1802 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1803 1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1805 1806 return status; 1807 } 1808 1809 /** 1810 * i40e_aq_get_link_info 1811 * @hw: pointer to the hw struct 1812 * @enable_lse: enable/disable LinkStatusEvent reporting 1813 * @link: pointer to link status structure - optional 1814 * @cmd_details: pointer to command details structure or NULL 1815 * 1816 * Returns the link status of the adapter. 1817 **/ 1818 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1819 bool enable_lse, struct i40e_link_status *link, 1820 struct i40e_asq_cmd_details *cmd_details) 1821 { 1822 struct i40e_aq_desc desc; 1823 struct i40e_aqc_get_link_status *resp = 1824 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1825 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1826 i40e_status status; 1827 bool tx_pause, rx_pause; 1828 u16 command_flags; 1829 1830 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1831 1832 if (enable_lse) 1833 command_flags = I40E_AQ_LSE_ENABLE; 1834 else 1835 command_flags = I40E_AQ_LSE_DISABLE; 1836 resp->command_flags = cpu_to_le16(command_flags); 1837 1838 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1839 1840 if (status) 1841 goto aq_get_link_info_exit; 1842 1843 /* save off old link status information */ 1844 hw->phy.link_info_old = *hw_link_info; 1845 1846 /* update link status */ 1847 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1848 hw->phy.media_type = i40e_get_media_type(hw); 1849 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1850 hw_link_info->link_info = resp->link_info; 1851 hw_link_info->an_info = resp->an_info; 1852 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1853 I40E_AQ_CONFIG_FEC_RS_ENA); 1854 hw_link_info->ext_info = resp->ext_info; 1855 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1856 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1857 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1858 1859 /* update fc info */ 1860 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1861 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1862 if (tx_pause & rx_pause) 1863 hw->fc.current_mode = I40E_FC_FULL; 1864 else if (tx_pause) 1865 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1866 else if (rx_pause) 1867 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1868 else 1869 hw->fc.current_mode = I40E_FC_NONE; 1870 1871 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1872 hw_link_info->crc_enable = true; 1873 else 1874 hw_link_info->crc_enable = false; 1875 1876 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1877 hw_link_info->lse_enable = true; 1878 else 1879 hw_link_info->lse_enable = false; 1880 1881 if ((hw->mac.type == I40E_MAC_XL710) && 1882 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1883 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1884 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1885 1886 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1887 hw->aq.api_min_ver >= 7) { 1888 __le32 tmp; 1889 1890 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1891 hw->phy.phy_types = le32_to_cpu(tmp); 1892 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1893 } 1894 1895 /* save link status information */ 1896 if (link) 1897 *link = *hw_link_info; 1898 1899 /* flag cleared so helper functions don't call AQ again */ 1900 hw->phy.get_link_info = false; 1901 1902 aq_get_link_info_exit: 1903 return status; 1904 } 1905 1906 /** 1907 * i40e_aq_set_phy_int_mask 1908 * @hw: pointer to the hw struct 1909 * @mask: interrupt mask to be set 1910 * @cmd_details: pointer to command details structure or NULL 1911 * 1912 * Set link interrupt mask. 1913 **/ 1914 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1915 u16 mask, 1916 struct i40e_asq_cmd_details *cmd_details) 1917 { 1918 struct i40e_aq_desc desc; 1919 struct i40e_aqc_set_phy_int_mask *cmd = 1920 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1921 i40e_status status; 1922 1923 i40e_fill_default_direct_cmd_desc(&desc, 1924 i40e_aqc_opc_set_phy_int_mask); 1925 1926 cmd->event_mask = cpu_to_le16(mask); 1927 1928 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1929 1930 return status; 1931 } 1932 1933 /** 1934 * i40e_aq_set_phy_debug 1935 * @hw: pointer to the hw struct 1936 * @cmd_flags: debug command flags 1937 * @cmd_details: pointer to command details structure or NULL 1938 * 1939 * Reset the external PHY. 1940 **/ 1941 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1942 struct i40e_asq_cmd_details *cmd_details) 1943 { 1944 struct i40e_aq_desc desc; 1945 struct i40e_aqc_set_phy_debug *cmd = 1946 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1947 i40e_status status; 1948 1949 i40e_fill_default_direct_cmd_desc(&desc, 1950 i40e_aqc_opc_set_phy_debug); 1951 1952 cmd->command_flags = cmd_flags; 1953 1954 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1955 1956 return status; 1957 } 1958 1959 /** 1960 * i40e_aq_add_vsi 1961 * @hw: pointer to the hw struct 1962 * @vsi_ctx: pointer to a vsi context struct 1963 * @cmd_details: pointer to command details structure or NULL 1964 * 1965 * Add a VSI context to the hardware. 1966 **/ 1967 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1968 struct i40e_vsi_context *vsi_ctx, 1969 struct i40e_asq_cmd_details *cmd_details) 1970 { 1971 struct i40e_aq_desc desc; 1972 struct i40e_aqc_add_get_update_vsi *cmd = 1973 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1974 struct i40e_aqc_add_get_update_vsi_completion *resp = 1975 (struct i40e_aqc_add_get_update_vsi_completion *) 1976 &desc.params.raw; 1977 i40e_status status; 1978 1979 i40e_fill_default_direct_cmd_desc(&desc, 1980 i40e_aqc_opc_add_vsi); 1981 1982 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1983 cmd->connection_type = vsi_ctx->connection_type; 1984 cmd->vf_id = vsi_ctx->vf_num; 1985 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1986 1987 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1988 1989 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1990 sizeof(vsi_ctx->info), cmd_details); 1991 1992 if (status) 1993 goto aq_add_vsi_exit; 1994 1995 vsi_ctx->seid = le16_to_cpu(resp->seid); 1996 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1997 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1998 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1999 2000 aq_add_vsi_exit: 2001 return status; 2002 } 2003 2004 /** 2005 * i40e_aq_set_default_vsi 2006 * @hw: pointer to the hw struct 2007 * @seid: vsi number 2008 * @cmd_details: pointer to command details structure or NULL 2009 **/ 2010 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2011 u16 seid, 2012 struct i40e_asq_cmd_details *cmd_details) 2013 { 2014 struct i40e_aq_desc desc; 2015 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2016 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2017 &desc.params.raw; 2018 i40e_status status; 2019 2020 i40e_fill_default_direct_cmd_desc(&desc, 2021 i40e_aqc_opc_set_vsi_promiscuous_modes); 2022 2023 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2024 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2025 cmd->seid = cpu_to_le16(seid); 2026 2027 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2028 2029 return status; 2030 } 2031 2032 /** 2033 * i40e_aq_clear_default_vsi 2034 * @hw: pointer to the hw struct 2035 * @seid: vsi number 2036 * @cmd_details: pointer to command details structure or NULL 2037 **/ 2038 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2039 u16 seid, 2040 struct i40e_asq_cmd_details *cmd_details) 2041 { 2042 struct i40e_aq_desc desc; 2043 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2044 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2045 &desc.params.raw; 2046 i40e_status status; 2047 2048 i40e_fill_default_direct_cmd_desc(&desc, 2049 i40e_aqc_opc_set_vsi_promiscuous_modes); 2050 2051 cmd->promiscuous_flags = cpu_to_le16(0); 2052 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2053 cmd->seid = cpu_to_le16(seid); 2054 2055 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2056 2057 return status; 2058 } 2059 2060 /** 2061 * i40e_aq_set_vsi_unicast_promiscuous 2062 * @hw: pointer to the hw struct 2063 * @seid: vsi number 2064 * @set: set unicast promiscuous enable/disable 2065 * @cmd_details: pointer to command details structure or NULL 2066 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2067 **/ 2068 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2069 u16 seid, bool set, 2070 struct i40e_asq_cmd_details *cmd_details, 2071 bool rx_only_promisc) 2072 { 2073 struct i40e_aq_desc desc; 2074 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2075 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2076 i40e_status status; 2077 u16 flags = 0; 2078 2079 i40e_fill_default_direct_cmd_desc(&desc, 2080 i40e_aqc_opc_set_vsi_promiscuous_modes); 2081 2082 if (set) { 2083 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2084 if (rx_only_promisc && 2085 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2086 (hw->aq.api_maj_ver > 1))) 2087 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2088 } 2089 2090 cmd->promiscuous_flags = cpu_to_le16(flags); 2091 2092 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2093 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2094 (hw->aq.api_maj_ver > 1)) 2095 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2096 2097 cmd->seid = cpu_to_le16(seid); 2098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2099 2100 return status; 2101 } 2102 2103 /** 2104 * i40e_aq_set_vsi_multicast_promiscuous 2105 * @hw: pointer to the hw struct 2106 * @seid: vsi number 2107 * @set: set multicast promiscuous enable/disable 2108 * @cmd_details: pointer to command details structure or NULL 2109 **/ 2110 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2111 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2112 { 2113 struct i40e_aq_desc desc; 2114 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2115 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2116 i40e_status status; 2117 u16 flags = 0; 2118 2119 i40e_fill_default_direct_cmd_desc(&desc, 2120 i40e_aqc_opc_set_vsi_promiscuous_modes); 2121 2122 if (set) 2123 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2124 2125 cmd->promiscuous_flags = cpu_to_le16(flags); 2126 2127 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2128 2129 cmd->seid = cpu_to_le16(seid); 2130 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2131 2132 return status; 2133 } 2134 2135 /** 2136 * i40e_aq_set_vsi_mc_promisc_on_vlan 2137 * @hw: pointer to the hw struct 2138 * @seid: vsi number 2139 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2140 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2141 * @cmd_details: pointer to command details structure or NULL 2142 **/ 2143 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2144 u16 seid, bool enable, 2145 u16 vid, 2146 struct i40e_asq_cmd_details *cmd_details) 2147 { 2148 struct i40e_aq_desc desc; 2149 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2150 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2151 enum i40e_status_code status; 2152 u16 flags = 0; 2153 2154 i40e_fill_default_direct_cmd_desc(&desc, 2155 i40e_aqc_opc_set_vsi_promiscuous_modes); 2156 2157 if (enable) 2158 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2159 2160 cmd->promiscuous_flags = cpu_to_le16(flags); 2161 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2162 cmd->seid = cpu_to_le16(seid); 2163 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2164 2165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2166 2167 return status; 2168 } 2169 2170 /** 2171 * i40e_aq_set_vsi_uc_promisc_on_vlan 2172 * @hw: pointer to the hw struct 2173 * @seid: vsi number 2174 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2175 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2176 * @cmd_details: pointer to command details structure or NULL 2177 **/ 2178 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2179 u16 seid, bool enable, 2180 u16 vid, 2181 struct i40e_asq_cmd_details *cmd_details) 2182 { 2183 struct i40e_aq_desc desc; 2184 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2185 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2186 enum i40e_status_code status; 2187 u16 flags = 0; 2188 2189 i40e_fill_default_direct_cmd_desc(&desc, 2190 i40e_aqc_opc_set_vsi_promiscuous_modes); 2191 2192 if (enable) 2193 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2194 2195 cmd->promiscuous_flags = cpu_to_le16(flags); 2196 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2197 cmd->seid = cpu_to_le16(seid); 2198 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2199 2200 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2201 2202 return status; 2203 } 2204 2205 /** 2206 * i40e_aq_set_vsi_bc_promisc_on_vlan 2207 * @hw: pointer to the hw struct 2208 * @seid: vsi number 2209 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2210 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2211 * @cmd_details: pointer to command details structure or NULL 2212 **/ 2213 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2214 u16 seid, bool enable, u16 vid, 2215 struct i40e_asq_cmd_details *cmd_details) 2216 { 2217 struct i40e_aq_desc desc; 2218 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2219 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2220 i40e_status status; 2221 u16 flags = 0; 2222 2223 i40e_fill_default_direct_cmd_desc(&desc, 2224 i40e_aqc_opc_set_vsi_promiscuous_modes); 2225 2226 if (enable) 2227 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2228 2229 cmd->promiscuous_flags = cpu_to_le16(flags); 2230 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2231 cmd->seid = cpu_to_le16(seid); 2232 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2233 2234 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2235 2236 return status; 2237 } 2238 2239 /** 2240 * i40e_aq_set_vsi_broadcast 2241 * @hw: pointer to the hw struct 2242 * @seid: vsi number 2243 * @set_filter: true to set filter, false to clear filter 2244 * @cmd_details: pointer to command details structure or NULL 2245 * 2246 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2247 **/ 2248 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2249 u16 seid, bool set_filter, 2250 struct i40e_asq_cmd_details *cmd_details) 2251 { 2252 struct i40e_aq_desc desc; 2253 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2254 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2255 i40e_status status; 2256 2257 i40e_fill_default_direct_cmd_desc(&desc, 2258 i40e_aqc_opc_set_vsi_promiscuous_modes); 2259 2260 if (set_filter) 2261 cmd->promiscuous_flags 2262 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2263 else 2264 cmd->promiscuous_flags 2265 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2266 2267 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2268 cmd->seid = cpu_to_le16(seid); 2269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2270 2271 return status; 2272 } 2273 2274 /** 2275 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2276 * @hw: pointer to the hw struct 2277 * @seid: vsi number 2278 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2279 * @cmd_details: pointer to command details structure or NULL 2280 **/ 2281 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2282 u16 seid, bool enable, 2283 struct i40e_asq_cmd_details *cmd_details) 2284 { 2285 struct i40e_aq_desc desc; 2286 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2287 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2288 i40e_status status; 2289 u16 flags = 0; 2290 2291 i40e_fill_default_direct_cmd_desc(&desc, 2292 i40e_aqc_opc_set_vsi_promiscuous_modes); 2293 if (enable) 2294 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2295 2296 cmd->promiscuous_flags = cpu_to_le16(flags); 2297 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2298 cmd->seid = cpu_to_le16(seid); 2299 2300 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2301 2302 return status; 2303 } 2304 2305 /** 2306 * i40e_get_vsi_params - get VSI configuration info 2307 * @hw: pointer to the hw struct 2308 * @vsi_ctx: pointer to a vsi context struct 2309 * @cmd_details: pointer to command details structure or NULL 2310 **/ 2311 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2312 struct i40e_vsi_context *vsi_ctx, 2313 struct i40e_asq_cmd_details *cmd_details) 2314 { 2315 struct i40e_aq_desc desc; 2316 struct i40e_aqc_add_get_update_vsi *cmd = 2317 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2318 struct i40e_aqc_add_get_update_vsi_completion *resp = 2319 (struct i40e_aqc_add_get_update_vsi_completion *) 2320 &desc.params.raw; 2321 i40e_status status; 2322 2323 i40e_fill_default_direct_cmd_desc(&desc, 2324 i40e_aqc_opc_get_vsi_parameters); 2325 2326 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2327 2328 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2329 2330 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2331 sizeof(vsi_ctx->info), NULL); 2332 2333 if (status) 2334 goto aq_get_vsi_params_exit; 2335 2336 vsi_ctx->seid = le16_to_cpu(resp->seid); 2337 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2338 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2339 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2340 2341 aq_get_vsi_params_exit: 2342 return status; 2343 } 2344 2345 /** 2346 * i40e_aq_update_vsi_params 2347 * @hw: pointer to the hw struct 2348 * @vsi_ctx: pointer to a vsi context struct 2349 * @cmd_details: pointer to command details structure or NULL 2350 * 2351 * Update a VSI context. 2352 **/ 2353 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2354 struct i40e_vsi_context *vsi_ctx, 2355 struct i40e_asq_cmd_details *cmd_details) 2356 { 2357 struct i40e_aq_desc desc; 2358 struct i40e_aqc_add_get_update_vsi *cmd = 2359 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2360 struct i40e_aqc_add_get_update_vsi_completion *resp = 2361 (struct i40e_aqc_add_get_update_vsi_completion *) 2362 &desc.params.raw; 2363 i40e_status status; 2364 2365 i40e_fill_default_direct_cmd_desc(&desc, 2366 i40e_aqc_opc_update_vsi_parameters); 2367 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2368 2369 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2370 2371 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2372 sizeof(vsi_ctx->info), cmd_details); 2373 2374 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2375 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2376 2377 return status; 2378 } 2379 2380 /** 2381 * i40e_aq_get_switch_config 2382 * @hw: pointer to the hardware structure 2383 * @buf: pointer to the result buffer 2384 * @buf_size: length of input buffer 2385 * @start_seid: seid to start for the report, 0 == beginning 2386 * @cmd_details: pointer to command details structure or NULL 2387 * 2388 * Fill the buf with switch configuration returned from AdminQ command 2389 **/ 2390 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2391 struct i40e_aqc_get_switch_config_resp *buf, 2392 u16 buf_size, u16 *start_seid, 2393 struct i40e_asq_cmd_details *cmd_details) 2394 { 2395 struct i40e_aq_desc desc; 2396 struct i40e_aqc_switch_seid *scfg = 2397 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2398 i40e_status status; 2399 2400 i40e_fill_default_direct_cmd_desc(&desc, 2401 i40e_aqc_opc_get_switch_config); 2402 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2403 if (buf_size > I40E_AQ_LARGE_BUF) 2404 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2405 scfg->seid = cpu_to_le16(*start_seid); 2406 2407 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2408 *start_seid = le16_to_cpu(scfg->seid); 2409 2410 return status; 2411 } 2412 2413 /** 2414 * i40e_aq_set_switch_config 2415 * @hw: pointer to the hardware structure 2416 * @flags: bit flag values to set 2417 * @valid_flags: which bit flags to set 2418 * @mode: cloud filter mode 2419 * @cmd_details: pointer to command details structure or NULL 2420 * 2421 * Set switch configuration bits 2422 **/ 2423 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2424 u16 flags, 2425 u16 valid_flags, u8 mode, 2426 struct i40e_asq_cmd_details *cmd_details) 2427 { 2428 struct i40e_aq_desc desc; 2429 struct i40e_aqc_set_switch_config *scfg = 2430 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2431 enum i40e_status_code status; 2432 2433 i40e_fill_default_direct_cmd_desc(&desc, 2434 i40e_aqc_opc_set_switch_config); 2435 scfg->flags = cpu_to_le16(flags); 2436 scfg->valid_flags = cpu_to_le16(valid_flags); 2437 scfg->mode = mode; 2438 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2439 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2440 scfg->first_tag = cpu_to_le16(hw->first_tag); 2441 scfg->second_tag = cpu_to_le16(hw->second_tag); 2442 } 2443 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2444 2445 return status; 2446 } 2447 2448 /** 2449 * i40e_aq_get_firmware_version 2450 * @hw: pointer to the hw struct 2451 * @fw_major_version: firmware major version 2452 * @fw_minor_version: firmware minor version 2453 * @fw_build: firmware build number 2454 * @api_major_version: major queue version 2455 * @api_minor_version: minor queue version 2456 * @cmd_details: pointer to command details structure or NULL 2457 * 2458 * Get the firmware version from the admin queue commands 2459 **/ 2460 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2461 u16 *fw_major_version, u16 *fw_minor_version, 2462 u32 *fw_build, 2463 u16 *api_major_version, u16 *api_minor_version, 2464 struct i40e_asq_cmd_details *cmd_details) 2465 { 2466 struct i40e_aq_desc desc; 2467 struct i40e_aqc_get_version *resp = 2468 (struct i40e_aqc_get_version *)&desc.params.raw; 2469 i40e_status status; 2470 2471 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2472 2473 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2474 2475 if (!status) { 2476 if (fw_major_version) 2477 *fw_major_version = le16_to_cpu(resp->fw_major); 2478 if (fw_minor_version) 2479 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2480 if (fw_build) 2481 *fw_build = le32_to_cpu(resp->fw_build); 2482 if (api_major_version) 2483 *api_major_version = le16_to_cpu(resp->api_major); 2484 if (api_minor_version) 2485 *api_minor_version = le16_to_cpu(resp->api_minor); 2486 } 2487 2488 return status; 2489 } 2490 2491 /** 2492 * i40e_aq_send_driver_version 2493 * @hw: pointer to the hw struct 2494 * @dv: driver's major, minor version 2495 * @cmd_details: pointer to command details structure or NULL 2496 * 2497 * Send the driver version to the firmware 2498 **/ 2499 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2500 struct i40e_driver_version *dv, 2501 struct i40e_asq_cmd_details *cmd_details) 2502 { 2503 struct i40e_aq_desc desc; 2504 struct i40e_aqc_driver_version *cmd = 2505 (struct i40e_aqc_driver_version *)&desc.params.raw; 2506 i40e_status status; 2507 u16 len; 2508 2509 if (dv == NULL) 2510 return I40E_ERR_PARAM; 2511 2512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2513 2514 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2515 cmd->driver_major_ver = dv->major_version; 2516 cmd->driver_minor_ver = dv->minor_version; 2517 cmd->driver_build_ver = dv->build_version; 2518 cmd->driver_subbuild_ver = dv->subbuild_version; 2519 2520 len = 0; 2521 while (len < sizeof(dv->driver_string) && 2522 (dv->driver_string[len] < 0x80) && 2523 dv->driver_string[len]) 2524 len++; 2525 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2526 len, cmd_details); 2527 2528 return status; 2529 } 2530 2531 /** 2532 * i40e_get_link_status - get status of the HW network link 2533 * @hw: pointer to the hw struct 2534 * @link_up: pointer to bool (true/false = linkup/linkdown) 2535 * 2536 * Variable link_up true if link is up, false if link is down. 2537 * The variable link_up is invalid if returned value of status != 0 2538 * 2539 * Side effect: LinkStatusEvent reporting becomes enabled 2540 **/ 2541 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2542 { 2543 i40e_status status = 0; 2544 2545 if (hw->phy.get_link_info) { 2546 status = i40e_update_link_info(hw); 2547 2548 if (status) 2549 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2550 status); 2551 } 2552 2553 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2554 2555 return status; 2556 } 2557 2558 /** 2559 * i40e_updatelink_status - update status of the HW network link 2560 * @hw: pointer to the hw struct 2561 **/ 2562 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2563 { 2564 struct i40e_aq_get_phy_abilities_resp abilities; 2565 i40e_status status = 0; 2566 2567 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2568 if (status) 2569 return status; 2570 2571 /* extra checking needed to ensure link info to user is timely */ 2572 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2573 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2574 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2575 status = i40e_aq_get_phy_capabilities(hw, false, false, 2576 &abilities, NULL); 2577 if (status) 2578 return status; 2579 2580 hw->phy.link_info.req_fec_info = 2581 abilities.fec_cfg_curr_mod_ext_info & 2582 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2583 2584 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2585 sizeof(hw->phy.link_info.module_type)); 2586 } 2587 2588 return status; 2589 } 2590 2591 /** 2592 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2593 * @hw: pointer to the hw struct 2594 * @uplink_seid: the MAC or other gizmo SEID 2595 * @downlink_seid: the VSI SEID 2596 * @enabled_tc: bitmap of TCs to be enabled 2597 * @default_port: true for default port VSI, false for control port 2598 * @veb_seid: pointer to where to put the resulting VEB SEID 2599 * @enable_stats: true to turn on VEB stats 2600 * @cmd_details: pointer to command details structure or NULL 2601 * 2602 * This asks the FW to add a VEB between the uplink and downlink 2603 * elements. If the uplink SEID is 0, this will be a floating VEB. 2604 **/ 2605 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2606 u16 downlink_seid, u8 enabled_tc, 2607 bool default_port, u16 *veb_seid, 2608 bool enable_stats, 2609 struct i40e_asq_cmd_details *cmd_details) 2610 { 2611 struct i40e_aq_desc desc; 2612 struct i40e_aqc_add_veb *cmd = 2613 (struct i40e_aqc_add_veb *)&desc.params.raw; 2614 struct i40e_aqc_add_veb_completion *resp = 2615 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2616 i40e_status status; 2617 u16 veb_flags = 0; 2618 2619 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2620 if (!!uplink_seid != !!downlink_seid) 2621 return I40E_ERR_PARAM; 2622 2623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2624 2625 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2626 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2627 cmd->enable_tcs = enabled_tc; 2628 if (!uplink_seid) 2629 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2630 if (default_port) 2631 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2632 else 2633 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2634 2635 /* reverse logic here: set the bitflag to disable the stats */ 2636 if (!enable_stats) 2637 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2638 2639 cmd->veb_flags = cpu_to_le16(veb_flags); 2640 2641 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2642 2643 if (!status && veb_seid) 2644 *veb_seid = le16_to_cpu(resp->veb_seid); 2645 2646 return status; 2647 } 2648 2649 /** 2650 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2651 * @hw: pointer to the hw struct 2652 * @veb_seid: the SEID of the VEB to query 2653 * @switch_id: the uplink switch id 2654 * @floating: set to true if the VEB is floating 2655 * @statistic_index: index of the stats counter block for this VEB 2656 * @vebs_used: number of VEB's used by function 2657 * @vebs_free: total VEB's not reserved by any function 2658 * @cmd_details: pointer to command details structure or NULL 2659 * 2660 * This retrieves the parameters for a particular VEB, specified by 2661 * uplink_seid, and returns them to the caller. 2662 **/ 2663 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2664 u16 veb_seid, u16 *switch_id, 2665 bool *floating, u16 *statistic_index, 2666 u16 *vebs_used, u16 *vebs_free, 2667 struct i40e_asq_cmd_details *cmd_details) 2668 { 2669 struct i40e_aq_desc desc; 2670 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2671 (struct i40e_aqc_get_veb_parameters_completion *) 2672 &desc.params.raw; 2673 i40e_status status; 2674 2675 if (veb_seid == 0) 2676 return I40E_ERR_PARAM; 2677 2678 i40e_fill_default_direct_cmd_desc(&desc, 2679 i40e_aqc_opc_get_veb_parameters); 2680 cmd_resp->seid = cpu_to_le16(veb_seid); 2681 2682 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2683 if (status) 2684 goto get_veb_exit; 2685 2686 if (switch_id) 2687 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2688 if (statistic_index) 2689 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2690 if (vebs_used) 2691 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2692 if (vebs_free) 2693 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2694 if (floating) { 2695 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2696 2697 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2698 *floating = true; 2699 else 2700 *floating = false; 2701 } 2702 2703 get_veb_exit: 2704 return status; 2705 } 2706 2707 /** 2708 * i40e_aq_add_macvlan 2709 * @hw: pointer to the hw struct 2710 * @seid: VSI for the mac address 2711 * @mv_list: list of macvlans to be added 2712 * @count: length of the list 2713 * @cmd_details: pointer to command details structure or NULL 2714 * 2715 * Add MAC/VLAN addresses to the HW filtering 2716 **/ 2717 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2718 struct i40e_aqc_add_macvlan_element_data *mv_list, 2719 u16 count, struct i40e_asq_cmd_details *cmd_details) 2720 { 2721 struct i40e_aq_desc desc; 2722 struct i40e_aqc_macvlan *cmd = 2723 (struct i40e_aqc_macvlan *)&desc.params.raw; 2724 i40e_status status; 2725 u16 buf_size; 2726 int i; 2727 2728 if (count == 0 || !mv_list || !hw) 2729 return I40E_ERR_PARAM; 2730 2731 buf_size = count * sizeof(*mv_list); 2732 2733 /* prep the rest of the request */ 2734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2735 cmd->num_addresses = cpu_to_le16(count); 2736 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2737 cmd->seid[1] = 0; 2738 cmd->seid[2] = 0; 2739 2740 for (i = 0; i < count; i++) 2741 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2742 mv_list[i].flags |= 2743 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2744 2745 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2746 if (buf_size > I40E_AQ_LARGE_BUF) 2747 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2748 2749 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2750 cmd_details); 2751 2752 return status; 2753 } 2754 2755 /** 2756 * i40e_aq_remove_macvlan 2757 * @hw: pointer to the hw struct 2758 * @seid: VSI for the mac address 2759 * @mv_list: list of macvlans to be removed 2760 * @count: length of the list 2761 * @cmd_details: pointer to command details structure or NULL 2762 * 2763 * Remove MAC/VLAN addresses from the HW filtering 2764 **/ 2765 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2766 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2767 u16 count, struct i40e_asq_cmd_details *cmd_details) 2768 { 2769 struct i40e_aq_desc desc; 2770 struct i40e_aqc_macvlan *cmd = 2771 (struct i40e_aqc_macvlan *)&desc.params.raw; 2772 i40e_status status; 2773 u16 buf_size; 2774 2775 if (count == 0 || !mv_list || !hw) 2776 return I40E_ERR_PARAM; 2777 2778 buf_size = count * sizeof(*mv_list); 2779 2780 /* prep the rest of the request */ 2781 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2782 cmd->num_addresses = cpu_to_le16(count); 2783 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2784 cmd->seid[1] = 0; 2785 cmd->seid[2] = 0; 2786 2787 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2788 if (buf_size > I40E_AQ_LARGE_BUF) 2789 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2790 2791 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2792 cmd_details); 2793 2794 return status; 2795 } 2796 2797 /** 2798 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2799 * @hw: pointer to the hw struct 2800 * @opcode: AQ opcode for add or delete mirror rule 2801 * @sw_seid: Switch SEID (to which rule refers) 2802 * @rule_type: Rule Type (ingress/egress/VLAN) 2803 * @id: Destination VSI SEID or Rule ID 2804 * @count: length of the list 2805 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2806 * @cmd_details: pointer to command details structure or NULL 2807 * @rule_id: Rule ID returned from FW 2808 * @rule_used: Number of rules used in internal switch 2809 * @rule_free: Number of rules free in internal switch 2810 * 2811 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2812 * VEBs/VEPA elements only 2813 **/ 2814 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2815 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2816 u16 count, __le16 *mr_list, 2817 struct i40e_asq_cmd_details *cmd_details, 2818 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2819 { 2820 struct i40e_aq_desc desc; 2821 struct i40e_aqc_add_delete_mirror_rule *cmd = 2822 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2823 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2824 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2825 i40e_status status; 2826 u16 buf_size; 2827 2828 buf_size = count * sizeof(*mr_list); 2829 2830 /* prep the rest of the request */ 2831 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2832 cmd->seid = cpu_to_le16(sw_seid); 2833 cmd->rule_type = cpu_to_le16(rule_type & 2834 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2835 cmd->num_entries = cpu_to_le16(count); 2836 /* Dest VSI for add, rule_id for delete */ 2837 cmd->destination = cpu_to_le16(id); 2838 if (mr_list) { 2839 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2840 I40E_AQ_FLAG_RD)); 2841 if (buf_size > I40E_AQ_LARGE_BUF) 2842 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2843 } 2844 2845 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2846 cmd_details); 2847 if (!status || 2848 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2849 if (rule_id) 2850 *rule_id = le16_to_cpu(resp->rule_id); 2851 if (rules_used) 2852 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2853 if (rules_free) 2854 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2855 } 2856 return status; 2857 } 2858 2859 /** 2860 * i40e_aq_add_mirrorrule - add a mirror rule 2861 * @hw: pointer to the hw struct 2862 * @sw_seid: Switch SEID (to which rule refers) 2863 * @rule_type: Rule Type (ingress/egress/VLAN) 2864 * @dest_vsi: SEID of VSI to which packets will be mirrored 2865 * @count: length of the list 2866 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2867 * @cmd_details: pointer to command details structure or NULL 2868 * @rule_id: Rule ID returned from FW 2869 * @rule_used: Number of rules used in internal switch 2870 * @rule_free: Number of rules free in internal switch 2871 * 2872 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2873 **/ 2874 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2875 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2876 struct i40e_asq_cmd_details *cmd_details, 2877 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2878 { 2879 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2880 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2881 if (count == 0 || !mr_list) 2882 return I40E_ERR_PARAM; 2883 } 2884 2885 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2886 rule_type, dest_vsi, count, mr_list, 2887 cmd_details, rule_id, rules_used, rules_free); 2888 } 2889 2890 /** 2891 * i40e_aq_delete_mirrorrule - delete a mirror rule 2892 * @hw: pointer to the hw struct 2893 * @sw_seid: Switch SEID (to which rule refers) 2894 * @rule_type: Rule Type (ingress/egress/VLAN) 2895 * @count: length of the list 2896 * @rule_id: Rule ID that is returned in the receive desc as part of 2897 * add_mirrorrule. 2898 * @mr_list: list of mirrored VLAN IDs to be removed 2899 * @cmd_details: pointer to command details structure or NULL 2900 * @rule_used: Number of rules used in internal switch 2901 * @rule_free: Number of rules free in internal switch 2902 * 2903 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2904 **/ 2905 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2906 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2907 struct i40e_asq_cmd_details *cmd_details, 2908 u16 *rules_used, u16 *rules_free) 2909 { 2910 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2911 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2912 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2913 * mirroring. For other rule_type, count and rule_type should 2914 * not matter. 2915 */ 2916 if (count == 0 || !mr_list) 2917 return I40E_ERR_PARAM; 2918 } 2919 2920 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2921 rule_type, rule_id, count, mr_list, 2922 cmd_details, NULL, rules_used, rules_free); 2923 } 2924 2925 /** 2926 * i40e_aq_send_msg_to_vf 2927 * @hw: pointer to the hardware structure 2928 * @vfid: VF id to send msg 2929 * @v_opcode: opcodes for VF-PF communication 2930 * @v_retval: return error code 2931 * @msg: pointer to the msg buffer 2932 * @msglen: msg length 2933 * @cmd_details: pointer to command details 2934 * 2935 * send msg to vf 2936 **/ 2937 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2938 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2939 struct i40e_asq_cmd_details *cmd_details) 2940 { 2941 struct i40e_aq_desc desc; 2942 struct i40e_aqc_pf_vf_message *cmd = 2943 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2944 i40e_status status; 2945 2946 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2947 cmd->id = cpu_to_le32(vfid); 2948 desc.cookie_high = cpu_to_le32(v_opcode); 2949 desc.cookie_low = cpu_to_le32(v_retval); 2950 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2951 if (msglen) { 2952 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2953 I40E_AQ_FLAG_RD)); 2954 if (msglen > I40E_AQ_LARGE_BUF) 2955 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2956 desc.datalen = cpu_to_le16(msglen); 2957 } 2958 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2959 2960 return status; 2961 } 2962 2963 /** 2964 * i40e_aq_debug_read_register 2965 * @hw: pointer to the hw struct 2966 * @reg_addr: register address 2967 * @reg_val: register value 2968 * @cmd_details: pointer to command details structure or NULL 2969 * 2970 * Read the register using the admin queue commands 2971 **/ 2972 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2973 u32 reg_addr, u64 *reg_val, 2974 struct i40e_asq_cmd_details *cmd_details) 2975 { 2976 struct i40e_aq_desc desc; 2977 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2978 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2979 i40e_status status; 2980 2981 if (reg_val == NULL) 2982 return I40E_ERR_PARAM; 2983 2984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2985 2986 cmd_resp->address = cpu_to_le32(reg_addr); 2987 2988 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2989 2990 if (!status) { 2991 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2992 (u64)le32_to_cpu(cmd_resp->value_low); 2993 } 2994 2995 return status; 2996 } 2997 2998 /** 2999 * i40e_aq_debug_write_register 3000 * @hw: pointer to the hw struct 3001 * @reg_addr: register address 3002 * @reg_val: register value 3003 * @cmd_details: pointer to command details structure or NULL 3004 * 3005 * Write to a register using the admin queue commands 3006 **/ 3007 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 3008 u32 reg_addr, u64 reg_val, 3009 struct i40e_asq_cmd_details *cmd_details) 3010 { 3011 struct i40e_aq_desc desc; 3012 struct i40e_aqc_debug_reg_read_write *cmd = 3013 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3014 i40e_status status; 3015 3016 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3017 3018 cmd->address = cpu_to_le32(reg_addr); 3019 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3020 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3021 3022 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3023 3024 return status; 3025 } 3026 3027 /** 3028 * i40e_aq_request_resource 3029 * @hw: pointer to the hw struct 3030 * @resource: resource id 3031 * @access: access type 3032 * @sdp_number: resource number 3033 * @timeout: the maximum time in ms that the driver may hold the resource 3034 * @cmd_details: pointer to command details structure or NULL 3035 * 3036 * requests common resource using the admin queue commands 3037 **/ 3038 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3039 enum i40e_aq_resources_ids resource, 3040 enum i40e_aq_resource_access_type access, 3041 u8 sdp_number, u64 *timeout, 3042 struct i40e_asq_cmd_details *cmd_details) 3043 { 3044 struct i40e_aq_desc desc; 3045 struct i40e_aqc_request_resource *cmd_resp = 3046 (struct i40e_aqc_request_resource *)&desc.params.raw; 3047 i40e_status status; 3048 3049 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3050 3051 cmd_resp->resource_id = cpu_to_le16(resource); 3052 cmd_resp->access_type = cpu_to_le16(access); 3053 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3054 3055 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3056 /* The completion specifies the maximum time in ms that the driver 3057 * may hold the resource in the Timeout field. 3058 * If the resource is held by someone else, the command completes with 3059 * busy return value and the timeout field indicates the maximum time 3060 * the current owner of the resource has to free it. 3061 */ 3062 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3063 *timeout = le32_to_cpu(cmd_resp->timeout); 3064 3065 return status; 3066 } 3067 3068 /** 3069 * i40e_aq_release_resource 3070 * @hw: pointer to the hw struct 3071 * @resource: resource id 3072 * @sdp_number: resource number 3073 * @cmd_details: pointer to command details structure or NULL 3074 * 3075 * release common resource using the admin queue commands 3076 **/ 3077 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3078 enum i40e_aq_resources_ids resource, 3079 u8 sdp_number, 3080 struct i40e_asq_cmd_details *cmd_details) 3081 { 3082 struct i40e_aq_desc desc; 3083 struct i40e_aqc_request_resource *cmd = 3084 (struct i40e_aqc_request_resource *)&desc.params.raw; 3085 i40e_status status; 3086 3087 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3088 3089 cmd->resource_id = cpu_to_le16(resource); 3090 cmd->resource_number = cpu_to_le32(sdp_number); 3091 3092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3093 3094 return status; 3095 } 3096 3097 /** 3098 * i40e_aq_read_nvm 3099 * @hw: pointer to the hw struct 3100 * @module_pointer: module pointer location in words from the NVM beginning 3101 * @offset: byte offset from the module beginning 3102 * @length: length of the section to be read (in bytes from the offset) 3103 * @data: command buffer (size [bytes] = length) 3104 * @last_command: tells if this is the last command in a series 3105 * @cmd_details: pointer to command details structure or NULL 3106 * 3107 * Read the NVM using the admin queue commands 3108 **/ 3109 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3110 u32 offset, u16 length, void *data, 3111 bool last_command, 3112 struct i40e_asq_cmd_details *cmd_details) 3113 { 3114 struct i40e_aq_desc desc; 3115 struct i40e_aqc_nvm_update *cmd = 3116 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3117 i40e_status status; 3118 3119 /* In offset the highest byte must be zeroed. */ 3120 if (offset & 0xFF000000) { 3121 status = I40E_ERR_PARAM; 3122 goto i40e_aq_read_nvm_exit; 3123 } 3124 3125 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3126 3127 /* If this is the last command in a series, set the proper flag. */ 3128 if (last_command) 3129 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3130 cmd->module_pointer = module_pointer; 3131 cmd->offset = cpu_to_le32(offset); 3132 cmd->length = cpu_to_le16(length); 3133 3134 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3135 if (length > I40E_AQ_LARGE_BUF) 3136 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3137 3138 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3139 3140 i40e_aq_read_nvm_exit: 3141 return status; 3142 } 3143 3144 /** 3145 * i40e_aq_erase_nvm 3146 * @hw: pointer to the hw struct 3147 * @module_pointer: module pointer location in words from the NVM beginning 3148 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3149 * @length: length of the section to be erased (expressed in 4 KB) 3150 * @last_command: tells if this is the last command in a series 3151 * @cmd_details: pointer to command details structure or NULL 3152 * 3153 * Erase the NVM sector using the admin queue commands 3154 **/ 3155 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3156 u32 offset, u16 length, bool last_command, 3157 struct i40e_asq_cmd_details *cmd_details) 3158 { 3159 struct i40e_aq_desc desc; 3160 struct i40e_aqc_nvm_update *cmd = 3161 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3162 i40e_status status; 3163 3164 /* In offset the highest byte must be zeroed. */ 3165 if (offset & 0xFF000000) { 3166 status = I40E_ERR_PARAM; 3167 goto i40e_aq_erase_nvm_exit; 3168 } 3169 3170 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3171 3172 /* If this is the last command in a series, set the proper flag. */ 3173 if (last_command) 3174 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3175 cmd->module_pointer = module_pointer; 3176 cmd->offset = cpu_to_le32(offset); 3177 cmd->length = cpu_to_le16(length); 3178 3179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3180 3181 i40e_aq_erase_nvm_exit: 3182 return status; 3183 } 3184 3185 /** 3186 * i40e_parse_discover_capabilities 3187 * @hw: pointer to the hw struct 3188 * @buff: pointer to a buffer containing device/function capability records 3189 * @cap_count: number of capability records in the list 3190 * @list_type_opc: type of capabilities list to parse 3191 * 3192 * Parse the device/function capabilities list. 3193 **/ 3194 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3195 u32 cap_count, 3196 enum i40e_admin_queue_opc list_type_opc) 3197 { 3198 struct i40e_aqc_list_capabilities_element_resp *cap; 3199 u32 valid_functions, num_functions; 3200 u32 number, logical_id, phys_id; 3201 struct i40e_hw_capabilities *p; 3202 u8 major_rev; 3203 u32 i = 0; 3204 u16 id; 3205 3206 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3207 3208 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3209 p = &hw->dev_caps; 3210 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3211 p = &hw->func_caps; 3212 else 3213 return; 3214 3215 for (i = 0; i < cap_count; i++, cap++) { 3216 id = le16_to_cpu(cap->id); 3217 number = le32_to_cpu(cap->number); 3218 logical_id = le32_to_cpu(cap->logical_id); 3219 phys_id = le32_to_cpu(cap->phys_id); 3220 major_rev = cap->major_rev; 3221 3222 switch (id) { 3223 case I40E_AQ_CAP_ID_SWITCH_MODE: 3224 p->switch_mode = number; 3225 break; 3226 case I40E_AQ_CAP_ID_MNG_MODE: 3227 p->management_mode = number; 3228 if (major_rev > 1) { 3229 p->mng_protocols_over_mctp = logical_id; 3230 i40e_debug(hw, I40E_DEBUG_INIT, 3231 "HW Capability: Protocols over MCTP = %d\n", 3232 p->mng_protocols_over_mctp); 3233 } else { 3234 p->mng_protocols_over_mctp = 0; 3235 } 3236 break; 3237 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3238 p->npar_enable = number; 3239 break; 3240 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3241 p->os2bmc = number; 3242 break; 3243 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3244 p->valid_functions = number; 3245 break; 3246 case I40E_AQ_CAP_ID_SRIOV: 3247 if (number == 1) 3248 p->sr_iov_1_1 = true; 3249 break; 3250 case I40E_AQ_CAP_ID_VF: 3251 p->num_vfs = number; 3252 p->vf_base_id = logical_id; 3253 break; 3254 case I40E_AQ_CAP_ID_VMDQ: 3255 if (number == 1) 3256 p->vmdq = true; 3257 break; 3258 case I40E_AQ_CAP_ID_8021QBG: 3259 if (number == 1) 3260 p->evb_802_1_qbg = true; 3261 break; 3262 case I40E_AQ_CAP_ID_8021QBR: 3263 if (number == 1) 3264 p->evb_802_1_qbh = true; 3265 break; 3266 case I40E_AQ_CAP_ID_VSI: 3267 p->num_vsis = number; 3268 break; 3269 case I40E_AQ_CAP_ID_DCB: 3270 if (number == 1) { 3271 p->dcb = true; 3272 p->enabled_tcmap = logical_id; 3273 p->maxtc = phys_id; 3274 } 3275 break; 3276 case I40E_AQ_CAP_ID_FCOE: 3277 if (number == 1) 3278 p->fcoe = true; 3279 break; 3280 case I40E_AQ_CAP_ID_ISCSI: 3281 if (number == 1) 3282 p->iscsi = true; 3283 break; 3284 case I40E_AQ_CAP_ID_RSS: 3285 p->rss = true; 3286 p->rss_table_size = number; 3287 p->rss_table_entry_width = logical_id; 3288 break; 3289 case I40E_AQ_CAP_ID_RXQ: 3290 p->num_rx_qp = number; 3291 p->base_queue = phys_id; 3292 break; 3293 case I40E_AQ_CAP_ID_TXQ: 3294 p->num_tx_qp = number; 3295 p->base_queue = phys_id; 3296 break; 3297 case I40E_AQ_CAP_ID_MSIX: 3298 p->num_msix_vectors = number; 3299 i40e_debug(hw, I40E_DEBUG_INIT, 3300 "HW Capability: MSIX vector count = %d\n", 3301 p->num_msix_vectors); 3302 break; 3303 case I40E_AQ_CAP_ID_VF_MSIX: 3304 p->num_msix_vectors_vf = number; 3305 break; 3306 case I40E_AQ_CAP_ID_FLEX10: 3307 if (major_rev == 1) { 3308 if (number == 1) { 3309 p->flex10_enable = true; 3310 p->flex10_capable = true; 3311 } 3312 } else { 3313 /* Capability revision >= 2 */ 3314 if (number & 1) 3315 p->flex10_enable = true; 3316 if (number & 2) 3317 p->flex10_capable = true; 3318 } 3319 p->flex10_mode = logical_id; 3320 p->flex10_status = phys_id; 3321 break; 3322 case I40E_AQ_CAP_ID_CEM: 3323 if (number == 1) 3324 p->mgmt_cem = true; 3325 break; 3326 case I40E_AQ_CAP_ID_IWARP: 3327 if (number == 1) 3328 p->iwarp = true; 3329 break; 3330 case I40E_AQ_CAP_ID_LED: 3331 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3332 p->led[phys_id] = true; 3333 break; 3334 case I40E_AQ_CAP_ID_SDP: 3335 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3336 p->sdp[phys_id] = true; 3337 break; 3338 case I40E_AQ_CAP_ID_MDIO: 3339 if (number == 1) { 3340 p->mdio_port_num = phys_id; 3341 p->mdio_port_mode = logical_id; 3342 } 3343 break; 3344 case I40E_AQ_CAP_ID_1588: 3345 if (number == 1) 3346 p->ieee_1588 = true; 3347 break; 3348 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3349 p->fd = true; 3350 p->fd_filters_guaranteed = number; 3351 p->fd_filters_best_effort = logical_id; 3352 break; 3353 case I40E_AQ_CAP_ID_WSR_PROT: 3354 p->wr_csr_prot = (u64)number; 3355 p->wr_csr_prot |= (u64)logical_id << 32; 3356 break; 3357 case I40E_AQ_CAP_ID_NVM_MGMT: 3358 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3359 p->sec_rev_disabled = true; 3360 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3361 p->update_disabled = true; 3362 break; 3363 default: 3364 break; 3365 } 3366 } 3367 3368 if (p->fcoe) 3369 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3370 3371 /* Software override ensuring FCoE is disabled if npar or mfp 3372 * mode because it is not supported in these modes. 3373 */ 3374 if (p->npar_enable || p->flex10_enable) 3375 p->fcoe = false; 3376 3377 /* count the enabled ports (aka the "not disabled" ports) */ 3378 hw->num_ports = 0; 3379 for (i = 0; i < 4; i++) { 3380 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3381 u64 port_cfg = 0; 3382 3383 /* use AQ read to get the physical register offset instead 3384 * of the port relative offset 3385 */ 3386 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3387 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3388 hw->num_ports++; 3389 } 3390 3391 valid_functions = p->valid_functions; 3392 num_functions = 0; 3393 while (valid_functions) { 3394 if (valid_functions & 1) 3395 num_functions++; 3396 valid_functions >>= 1; 3397 } 3398 3399 /* partition id is 1-based, and functions are evenly spread 3400 * across the ports as partitions 3401 */ 3402 if (hw->num_ports != 0) { 3403 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3404 hw->num_partitions = num_functions / hw->num_ports; 3405 } 3406 3407 /* additional HW specific goodies that might 3408 * someday be HW version specific 3409 */ 3410 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3411 } 3412 3413 /** 3414 * i40e_aq_discover_capabilities 3415 * @hw: pointer to the hw struct 3416 * @buff: a virtual buffer to hold the capabilities 3417 * @buff_size: Size of the virtual buffer 3418 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3419 * @list_type_opc: capabilities type to discover - pass in the command opcode 3420 * @cmd_details: pointer to command details structure or NULL 3421 * 3422 * Get the device capabilities descriptions from the firmware 3423 **/ 3424 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3425 void *buff, u16 buff_size, u16 *data_size, 3426 enum i40e_admin_queue_opc list_type_opc, 3427 struct i40e_asq_cmd_details *cmd_details) 3428 { 3429 struct i40e_aqc_list_capabilites *cmd; 3430 struct i40e_aq_desc desc; 3431 i40e_status status = 0; 3432 3433 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3434 3435 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3436 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3437 status = I40E_ERR_PARAM; 3438 goto exit; 3439 } 3440 3441 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3442 3443 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3444 if (buff_size > I40E_AQ_LARGE_BUF) 3445 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3446 3447 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3448 *data_size = le16_to_cpu(desc.datalen); 3449 3450 if (status) 3451 goto exit; 3452 3453 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3454 list_type_opc); 3455 3456 exit: 3457 return status; 3458 } 3459 3460 /** 3461 * i40e_aq_update_nvm 3462 * @hw: pointer to the hw struct 3463 * @module_pointer: module pointer location in words from the NVM beginning 3464 * @offset: byte offset from the module beginning 3465 * @length: length of the section to be written (in bytes from the offset) 3466 * @data: command buffer (size [bytes] = length) 3467 * @last_command: tells if this is the last command in a series 3468 * @cmd_details: pointer to command details structure or NULL 3469 * 3470 * Update the NVM using the admin queue commands 3471 **/ 3472 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3473 u32 offset, u16 length, void *data, 3474 bool last_command, 3475 struct i40e_asq_cmd_details *cmd_details) 3476 { 3477 struct i40e_aq_desc desc; 3478 struct i40e_aqc_nvm_update *cmd = 3479 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3480 i40e_status status; 3481 3482 /* In offset the highest byte must be zeroed. */ 3483 if (offset & 0xFF000000) { 3484 status = I40E_ERR_PARAM; 3485 goto i40e_aq_update_nvm_exit; 3486 } 3487 3488 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3489 3490 /* If this is the last command in a series, set the proper flag. */ 3491 if (last_command) 3492 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3493 cmd->module_pointer = module_pointer; 3494 cmd->offset = cpu_to_le32(offset); 3495 cmd->length = cpu_to_le16(length); 3496 3497 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3498 if (length > I40E_AQ_LARGE_BUF) 3499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3500 3501 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3502 3503 i40e_aq_update_nvm_exit: 3504 return status; 3505 } 3506 3507 /** 3508 * i40e_aq_get_lldp_mib 3509 * @hw: pointer to the hw struct 3510 * @bridge_type: type of bridge requested 3511 * @mib_type: Local, Remote or both Local and Remote MIBs 3512 * @buff: pointer to a user supplied buffer to store the MIB block 3513 * @buff_size: size of the buffer (in bytes) 3514 * @local_len : length of the returned Local LLDP MIB 3515 * @remote_len: length of the returned Remote LLDP MIB 3516 * @cmd_details: pointer to command details structure or NULL 3517 * 3518 * Requests the complete LLDP MIB (entire packet). 3519 **/ 3520 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3521 u8 mib_type, void *buff, u16 buff_size, 3522 u16 *local_len, u16 *remote_len, 3523 struct i40e_asq_cmd_details *cmd_details) 3524 { 3525 struct i40e_aq_desc desc; 3526 struct i40e_aqc_lldp_get_mib *cmd = 3527 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3528 struct i40e_aqc_lldp_get_mib *resp = 3529 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3530 i40e_status status; 3531 3532 if (buff_size == 0 || !buff) 3533 return I40E_ERR_PARAM; 3534 3535 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3536 /* Indirect Command */ 3537 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3538 3539 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3540 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3541 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3542 3543 desc.datalen = cpu_to_le16(buff_size); 3544 3545 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3546 if (buff_size > I40E_AQ_LARGE_BUF) 3547 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3548 3549 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3550 if (!status) { 3551 if (local_len != NULL) 3552 *local_len = le16_to_cpu(resp->local_len); 3553 if (remote_len != NULL) 3554 *remote_len = le16_to_cpu(resp->remote_len); 3555 } 3556 3557 return status; 3558 } 3559 3560 /** 3561 * i40e_aq_cfg_lldp_mib_change_event 3562 * @hw: pointer to the hw struct 3563 * @enable_update: Enable or Disable event posting 3564 * @cmd_details: pointer to command details structure or NULL 3565 * 3566 * Enable or Disable posting of an event on ARQ when LLDP MIB 3567 * associated with the interface changes 3568 **/ 3569 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3570 bool enable_update, 3571 struct i40e_asq_cmd_details *cmd_details) 3572 { 3573 struct i40e_aq_desc desc; 3574 struct i40e_aqc_lldp_update_mib *cmd = 3575 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3576 i40e_status status; 3577 3578 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3579 3580 if (!enable_update) 3581 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3582 3583 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3584 3585 return status; 3586 } 3587 3588 /** 3589 * i40e_aq_stop_lldp 3590 * @hw: pointer to the hw struct 3591 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3592 * @cmd_details: pointer to command details structure or NULL 3593 * 3594 * Stop or Shutdown the embedded LLDP Agent 3595 **/ 3596 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3597 struct i40e_asq_cmd_details *cmd_details) 3598 { 3599 struct i40e_aq_desc desc; 3600 struct i40e_aqc_lldp_stop *cmd = 3601 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3602 i40e_status status; 3603 3604 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3605 3606 if (shutdown_agent) 3607 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3608 3609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3610 3611 return status; 3612 } 3613 3614 /** 3615 * i40e_aq_start_lldp 3616 * @hw: pointer to the hw struct 3617 * @cmd_details: pointer to command details structure or NULL 3618 * 3619 * Start the embedded LLDP Agent on all ports. 3620 **/ 3621 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3622 struct i40e_asq_cmd_details *cmd_details) 3623 { 3624 struct i40e_aq_desc desc; 3625 struct i40e_aqc_lldp_start *cmd = 3626 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3627 i40e_status status; 3628 3629 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3630 3631 cmd->command = I40E_AQ_LLDP_AGENT_START; 3632 3633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3634 3635 return status; 3636 } 3637 3638 /** 3639 * i40e_aq_get_cee_dcb_config 3640 * @hw: pointer to the hw struct 3641 * @buff: response buffer that stores CEE operational configuration 3642 * @buff_size: size of the buffer passed 3643 * @cmd_details: pointer to command details structure or NULL 3644 * 3645 * Get CEE DCBX mode operational configuration from firmware 3646 **/ 3647 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3648 void *buff, u16 buff_size, 3649 struct i40e_asq_cmd_details *cmd_details) 3650 { 3651 struct i40e_aq_desc desc; 3652 i40e_status status; 3653 3654 if (buff_size == 0 || !buff) 3655 return I40E_ERR_PARAM; 3656 3657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3658 3659 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3660 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3661 cmd_details); 3662 3663 return status; 3664 } 3665 3666 /** 3667 * i40e_aq_add_udp_tunnel 3668 * @hw: pointer to the hw struct 3669 * @udp_port: the UDP port to add in Host byte order 3670 * @header_len: length of the tunneling header length in DWords 3671 * @protocol_index: protocol index type 3672 * @filter_index: pointer to filter index 3673 * @cmd_details: pointer to command details structure or NULL 3674 * 3675 * Note: Firmware expects the udp_port value to be in Little Endian format, 3676 * and this function will call cpu_to_le16 to convert from Host byte order to 3677 * Little Endian order. 3678 **/ 3679 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3680 u16 udp_port, u8 protocol_index, 3681 u8 *filter_index, 3682 struct i40e_asq_cmd_details *cmd_details) 3683 { 3684 struct i40e_aq_desc desc; 3685 struct i40e_aqc_add_udp_tunnel *cmd = 3686 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3687 struct i40e_aqc_del_udp_tunnel_completion *resp = 3688 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3689 i40e_status status; 3690 3691 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3692 3693 cmd->udp_port = cpu_to_le16(udp_port); 3694 cmd->protocol_type = protocol_index; 3695 3696 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3697 3698 if (!status && filter_index) 3699 *filter_index = resp->index; 3700 3701 return status; 3702 } 3703 3704 /** 3705 * i40e_aq_del_udp_tunnel 3706 * @hw: pointer to the hw struct 3707 * @index: filter index 3708 * @cmd_details: pointer to command details structure or NULL 3709 **/ 3710 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3711 struct i40e_asq_cmd_details *cmd_details) 3712 { 3713 struct i40e_aq_desc desc; 3714 struct i40e_aqc_remove_udp_tunnel *cmd = 3715 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3716 i40e_status status; 3717 3718 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3719 3720 cmd->index = index; 3721 3722 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3723 3724 return status; 3725 } 3726 3727 /** 3728 * i40e_aq_delete_element - Delete switch element 3729 * @hw: pointer to the hw struct 3730 * @seid: the SEID to delete from the switch 3731 * @cmd_details: pointer to command details structure or NULL 3732 * 3733 * This deletes a switch element from the switch. 3734 **/ 3735 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3736 struct i40e_asq_cmd_details *cmd_details) 3737 { 3738 struct i40e_aq_desc desc; 3739 struct i40e_aqc_switch_seid *cmd = 3740 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3741 i40e_status status; 3742 3743 if (seid == 0) 3744 return I40E_ERR_PARAM; 3745 3746 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3747 3748 cmd->seid = cpu_to_le16(seid); 3749 3750 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3751 3752 return status; 3753 } 3754 3755 /** 3756 * i40e_aq_dcb_updated - DCB Updated Command 3757 * @hw: pointer to the hw struct 3758 * @cmd_details: pointer to command details structure or NULL 3759 * 3760 * EMP will return when the shared RPB settings have been 3761 * recomputed and modified. The retval field in the descriptor 3762 * will be set to 0 when RPB is modified. 3763 **/ 3764 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3765 struct i40e_asq_cmd_details *cmd_details) 3766 { 3767 struct i40e_aq_desc desc; 3768 i40e_status status; 3769 3770 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3771 3772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3773 3774 return status; 3775 } 3776 3777 /** 3778 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3779 * @hw: pointer to the hw struct 3780 * @seid: seid for the physical port/switching component/vsi 3781 * @buff: Indirect buffer to hold data parameters and response 3782 * @buff_size: Indirect buffer size 3783 * @opcode: Tx scheduler AQ command opcode 3784 * @cmd_details: pointer to command details structure or NULL 3785 * 3786 * Generic command handler for Tx scheduler AQ commands 3787 **/ 3788 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3789 void *buff, u16 buff_size, 3790 enum i40e_admin_queue_opc opcode, 3791 struct i40e_asq_cmd_details *cmd_details) 3792 { 3793 struct i40e_aq_desc desc; 3794 struct i40e_aqc_tx_sched_ind *cmd = 3795 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3796 i40e_status status; 3797 bool cmd_param_flag = false; 3798 3799 switch (opcode) { 3800 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3801 case i40e_aqc_opc_configure_vsi_tc_bw: 3802 case i40e_aqc_opc_enable_switching_comp_ets: 3803 case i40e_aqc_opc_modify_switching_comp_ets: 3804 case i40e_aqc_opc_disable_switching_comp_ets: 3805 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3806 case i40e_aqc_opc_configure_switching_comp_bw_config: 3807 cmd_param_flag = true; 3808 break; 3809 case i40e_aqc_opc_query_vsi_bw_config: 3810 case i40e_aqc_opc_query_vsi_ets_sla_config: 3811 case i40e_aqc_opc_query_switching_comp_ets_config: 3812 case i40e_aqc_opc_query_port_ets_config: 3813 case i40e_aqc_opc_query_switching_comp_bw_config: 3814 cmd_param_flag = false; 3815 break; 3816 default: 3817 return I40E_ERR_PARAM; 3818 } 3819 3820 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3821 3822 /* Indirect command */ 3823 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3824 if (cmd_param_flag) 3825 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3826 if (buff_size > I40E_AQ_LARGE_BUF) 3827 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3828 3829 desc.datalen = cpu_to_le16(buff_size); 3830 3831 cmd->vsi_seid = cpu_to_le16(seid); 3832 3833 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3834 3835 return status; 3836 } 3837 3838 /** 3839 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3840 * @hw: pointer to the hw struct 3841 * @seid: VSI seid 3842 * @credit: BW limit credits (0 = disabled) 3843 * @max_credit: Max BW limit credits 3844 * @cmd_details: pointer to command details structure or NULL 3845 **/ 3846 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3847 u16 seid, u16 credit, u8 max_credit, 3848 struct i40e_asq_cmd_details *cmd_details) 3849 { 3850 struct i40e_aq_desc desc; 3851 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3852 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3853 i40e_status status; 3854 3855 i40e_fill_default_direct_cmd_desc(&desc, 3856 i40e_aqc_opc_configure_vsi_bw_limit); 3857 3858 cmd->vsi_seid = cpu_to_le16(seid); 3859 cmd->credit = cpu_to_le16(credit); 3860 cmd->max_credit = max_credit; 3861 3862 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3863 3864 return status; 3865 } 3866 3867 /** 3868 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3869 * @hw: pointer to the hw struct 3870 * @seid: VSI seid 3871 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3872 * @cmd_details: pointer to command details structure or NULL 3873 **/ 3874 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3875 u16 seid, 3876 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3877 struct i40e_asq_cmd_details *cmd_details) 3878 { 3879 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3880 i40e_aqc_opc_configure_vsi_tc_bw, 3881 cmd_details); 3882 } 3883 3884 /** 3885 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3886 * @hw: pointer to the hw struct 3887 * @seid: seid of the switching component connected to Physical Port 3888 * @ets_data: Buffer holding ETS parameters 3889 * @cmd_details: pointer to command details structure or NULL 3890 **/ 3891 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3892 u16 seid, 3893 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3894 enum i40e_admin_queue_opc opcode, 3895 struct i40e_asq_cmd_details *cmd_details) 3896 { 3897 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3898 sizeof(*ets_data), opcode, cmd_details); 3899 } 3900 3901 /** 3902 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3903 * @hw: pointer to the hw struct 3904 * @seid: seid of the switching component 3905 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3906 * @cmd_details: pointer to command details structure or NULL 3907 **/ 3908 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3909 u16 seid, 3910 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3911 struct i40e_asq_cmd_details *cmd_details) 3912 { 3913 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3914 i40e_aqc_opc_configure_switching_comp_bw_config, 3915 cmd_details); 3916 } 3917 3918 /** 3919 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3920 * @hw: pointer to the hw struct 3921 * @seid: seid of the VSI 3922 * @bw_data: Buffer to hold VSI BW configuration 3923 * @cmd_details: pointer to command details structure or NULL 3924 **/ 3925 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3926 u16 seid, 3927 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3928 struct i40e_asq_cmd_details *cmd_details) 3929 { 3930 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3931 i40e_aqc_opc_query_vsi_bw_config, 3932 cmd_details); 3933 } 3934 3935 /** 3936 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3937 * @hw: pointer to the hw struct 3938 * @seid: seid of the VSI 3939 * @bw_data: Buffer to hold VSI BW configuration per TC 3940 * @cmd_details: pointer to command details structure or NULL 3941 **/ 3942 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3943 u16 seid, 3944 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3945 struct i40e_asq_cmd_details *cmd_details) 3946 { 3947 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3948 i40e_aqc_opc_query_vsi_ets_sla_config, 3949 cmd_details); 3950 } 3951 3952 /** 3953 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3954 * @hw: pointer to the hw struct 3955 * @seid: seid of the switching component 3956 * @bw_data: Buffer to hold switching component's per TC BW config 3957 * @cmd_details: pointer to command details structure or NULL 3958 **/ 3959 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3960 u16 seid, 3961 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3962 struct i40e_asq_cmd_details *cmd_details) 3963 { 3964 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3965 i40e_aqc_opc_query_switching_comp_ets_config, 3966 cmd_details); 3967 } 3968 3969 /** 3970 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3971 * @hw: pointer to the hw struct 3972 * @seid: seid of the VSI or switching component connected to Physical Port 3973 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3974 * @cmd_details: pointer to command details structure or NULL 3975 **/ 3976 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3977 u16 seid, 3978 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3979 struct i40e_asq_cmd_details *cmd_details) 3980 { 3981 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3982 i40e_aqc_opc_query_port_ets_config, 3983 cmd_details); 3984 } 3985 3986 /** 3987 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3988 * @hw: pointer to the hw struct 3989 * @seid: seid of the switching component 3990 * @bw_data: Buffer to hold switching component's BW configuration 3991 * @cmd_details: pointer to command details structure or NULL 3992 **/ 3993 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3994 u16 seid, 3995 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3996 struct i40e_asq_cmd_details *cmd_details) 3997 { 3998 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3999 i40e_aqc_opc_query_switching_comp_bw_config, 4000 cmd_details); 4001 } 4002 4003 /** 4004 * i40e_validate_filter_settings 4005 * @hw: pointer to the hardware structure 4006 * @settings: Filter control settings 4007 * 4008 * Check and validate the filter control settings passed. 4009 * The function checks for the valid filter/context sizes being 4010 * passed for FCoE and PE. 4011 * 4012 * Returns 0 if the values passed are valid and within 4013 * range else returns an error. 4014 **/ 4015 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4016 struct i40e_filter_control_settings *settings) 4017 { 4018 u32 fcoe_cntx_size, fcoe_filt_size; 4019 u32 pe_cntx_size, pe_filt_size; 4020 u32 fcoe_fmax; 4021 u32 val; 4022 4023 /* Validate FCoE settings passed */ 4024 switch (settings->fcoe_filt_num) { 4025 case I40E_HASH_FILTER_SIZE_1K: 4026 case I40E_HASH_FILTER_SIZE_2K: 4027 case I40E_HASH_FILTER_SIZE_4K: 4028 case I40E_HASH_FILTER_SIZE_8K: 4029 case I40E_HASH_FILTER_SIZE_16K: 4030 case I40E_HASH_FILTER_SIZE_32K: 4031 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4032 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4033 break; 4034 default: 4035 return I40E_ERR_PARAM; 4036 } 4037 4038 switch (settings->fcoe_cntx_num) { 4039 case I40E_DMA_CNTX_SIZE_512: 4040 case I40E_DMA_CNTX_SIZE_1K: 4041 case I40E_DMA_CNTX_SIZE_2K: 4042 case I40E_DMA_CNTX_SIZE_4K: 4043 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4044 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4045 break; 4046 default: 4047 return I40E_ERR_PARAM; 4048 } 4049 4050 /* Validate PE settings passed */ 4051 switch (settings->pe_filt_num) { 4052 case I40E_HASH_FILTER_SIZE_1K: 4053 case I40E_HASH_FILTER_SIZE_2K: 4054 case I40E_HASH_FILTER_SIZE_4K: 4055 case I40E_HASH_FILTER_SIZE_8K: 4056 case I40E_HASH_FILTER_SIZE_16K: 4057 case I40E_HASH_FILTER_SIZE_32K: 4058 case I40E_HASH_FILTER_SIZE_64K: 4059 case I40E_HASH_FILTER_SIZE_128K: 4060 case I40E_HASH_FILTER_SIZE_256K: 4061 case I40E_HASH_FILTER_SIZE_512K: 4062 case I40E_HASH_FILTER_SIZE_1M: 4063 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4064 pe_filt_size <<= (u32)settings->pe_filt_num; 4065 break; 4066 default: 4067 return I40E_ERR_PARAM; 4068 } 4069 4070 switch (settings->pe_cntx_num) { 4071 case I40E_DMA_CNTX_SIZE_512: 4072 case I40E_DMA_CNTX_SIZE_1K: 4073 case I40E_DMA_CNTX_SIZE_2K: 4074 case I40E_DMA_CNTX_SIZE_4K: 4075 case I40E_DMA_CNTX_SIZE_8K: 4076 case I40E_DMA_CNTX_SIZE_16K: 4077 case I40E_DMA_CNTX_SIZE_32K: 4078 case I40E_DMA_CNTX_SIZE_64K: 4079 case I40E_DMA_CNTX_SIZE_128K: 4080 case I40E_DMA_CNTX_SIZE_256K: 4081 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4082 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4083 break; 4084 default: 4085 return I40E_ERR_PARAM; 4086 } 4087 4088 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4089 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4090 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4091 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4092 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4093 return I40E_ERR_INVALID_SIZE; 4094 4095 return 0; 4096 } 4097 4098 /** 4099 * i40e_set_filter_control 4100 * @hw: pointer to the hardware structure 4101 * @settings: Filter control settings 4102 * 4103 * Set the Queue Filters for PE/FCoE and enable filters required 4104 * for a single PF. It is expected that these settings are programmed 4105 * at the driver initialization time. 4106 **/ 4107 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4108 struct i40e_filter_control_settings *settings) 4109 { 4110 i40e_status ret = 0; 4111 u32 hash_lut_size = 0; 4112 u32 val; 4113 4114 if (!settings) 4115 return I40E_ERR_PARAM; 4116 4117 /* Validate the input settings */ 4118 ret = i40e_validate_filter_settings(hw, settings); 4119 if (ret) 4120 return ret; 4121 4122 /* Read the PF Queue Filter control register */ 4123 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4124 4125 /* Program required PE hash buckets for the PF */ 4126 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4127 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4128 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4129 /* Program required PE contexts for the PF */ 4130 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4131 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4132 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4133 4134 /* Program required FCoE hash buckets for the PF */ 4135 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4136 val |= ((u32)settings->fcoe_filt_num << 4137 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4138 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4139 /* Program required FCoE DDP contexts for the PF */ 4140 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4141 val |= ((u32)settings->fcoe_cntx_num << 4142 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4143 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4144 4145 /* Program Hash LUT size for the PF */ 4146 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4147 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4148 hash_lut_size = 1; 4149 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4150 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4151 4152 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4153 if (settings->enable_fdir) 4154 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4155 if (settings->enable_ethtype) 4156 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4157 if (settings->enable_macvlan) 4158 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4159 4160 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4161 4162 return 0; 4163 } 4164 4165 /** 4166 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4167 * @hw: pointer to the hw struct 4168 * @mac_addr: MAC address to use in the filter 4169 * @ethtype: Ethertype to use in the filter 4170 * @flags: Flags that needs to be applied to the filter 4171 * @vsi_seid: seid of the control VSI 4172 * @queue: VSI queue number to send the packet to 4173 * @is_add: Add control packet filter if True else remove 4174 * @stats: Structure to hold information on control filter counts 4175 * @cmd_details: pointer to command details structure or NULL 4176 * 4177 * This command will Add or Remove control packet filter for a control VSI. 4178 * In return it will update the total number of perfect filter count in 4179 * the stats member. 4180 **/ 4181 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4182 u8 *mac_addr, u16 ethtype, u16 flags, 4183 u16 vsi_seid, u16 queue, bool is_add, 4184 struct i40e_control_filter_stats *stats, 4185 struct i40e_asq_cmd_details *cmd_details) 4186 { 4187 struct i40e_aq_desc desc; 4188 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4189 (struct i40e_aqc_add_remove_control_packet_filter *) 4190 &desc.params.raw; 4191 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4192 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4193 &desc.params.raw; 4194 i40e_status status; 4195 4196 if (vsi_seid == 0) 4197 return I40E_ERR_PARAM; 4198 4199 if (is_add) { 4200 i40e_fill_default_direct_cmd_desc(&desc, 4201 i40e_aqc_opc_add_control_packet_filter); 4202 cmd->queue = cpu_to_le16(queue); 4203 } else { 4204 i40e_fill_default_direct_cmd_desc(&desc, 4205 i40e_aqc_opc_remove_control_packet_filter); 4206 } 4207 4208 if (mac_addr) 4209 ether_addr_copy(cmd->mac, mac_addr); 4210 4211 cmd->etype = cpu_to_le16(ethtype); 4212 cmd->flags = cpu_to_le16(flags); 4213 cmd->seid = cpu_to_le16(vsi_seid); 4214 4215 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4216 4217 if (!status && stats) { 4218 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4219 stats->etype_used = le16_to_cpu(resp->etype_used); 4220 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4221 stats->etype_free = le16_to_cpu(resp->etype_free); 4222 } 4223 4224 return status; 4225 } 4226 4227 /** 4228 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4229 * @hw: pointer to the hw struct 4230 * @seid: VSI seid to add ethertype filter from 4231 **/ 4232 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4233 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4234 u16 seid) 4235 { 4236 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4237 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4238 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4239 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4240 i40e_status status; 4241 4242 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4243 seid, 0, true, NULL, 4244 NULL); 4245 if (status) 4246 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4247 } 4248 4249 /** 4250 * i40e_aq_alternate_read 4251 * @hw: pointer to the hardware structure 4252 * @reg_addr0: address of first dword to be read 4253 * @reg_val0: pointer for data read from 'reg_addr0' 4254 * @reg_addr1: address of second dword to be read 4255 * @reg_val1: pointer for data read from 'reg_addr1' 4256 * 4257 * Read one or two dwords from alternate structure. Fields are indicated 4258 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4259 * is not passed then only register at 'reg_addr0' is read. 4260 * 4261 **/ 4262 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4263 u32 reg_addr0, u32 *reg_val0, 4264 u32 reg_addr1, u32 *reg_val1) 4265 { 4266 struct i40e_aq_desc desc; 4267 struct i40e_aqc_alternate_write *cmd_resp = 4268 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4269 i40e_status status; 4270 4271 if (!reg_val0) 4272 return I40E_ERR_PARAM; 4273 4274 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4275 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4276 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4277 4278 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4279 4280 if (!status) { 4281 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4282 4283 if (reg_val1) 4284 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4285 } 4286 4287 return status; 4288 } 4289 4290 /** 4291 * i40e_aq_resume_port_tx 4292 * @hw: pointer to the hardware structure 4293 * @cmd_details: pointer to command details structure or NULL 4294 * 4295 * Resume port's Tx traffic 4296 **/ 4297 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4298 struct i40e_asq_cmd_details *cmd_details) 4299 { 4300 struct i40e_aq_desc desc; 4301 i40e_status status; 4302 4303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4304 4305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4306 4307 return status; 4308 } 4309 4310 /** 4311 * i40e_set_pci_config_data - store PCI bus info 4312 * @hw: pointer to hardware structure 4313 * @link_status: the link status word from PCI config space 4314 * 4315 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4316 **/ 4317 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4318 { 4319 hw->bus.type = i40e_bus_type_pci_express; 4320 4321 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4322 case PCI_EXP_LNKSTA_NLW_X1: 4323 hw->bus.width = i40e_bus_width_pcie_x1; 4324 break; 4325 case PCI_EXP_LNKSTA_NLW_X2: 4326 hw->bus.width = i40e_bus_width_pcie_x2; 4327 break; 4328 case PCI_EXP_LNKSTA_NLW_X4: 4329 hw->bus.width = i40e_bus_width_pcie_x4; 4330 break; 4331 case PCI_EXP_LNKSTA_NLW_X8: 4332 hw->bus.width = i40e_bus_width_pcie_x8; 4333 break; 4334 default: 4335 hw->bus.width = i40e_bus_width_unknown; 4336 break; 4337 } 4338 4339 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4340 case PCI_EXP_LNKSTA_CLS_2_5GB: 4341 hw->bus.speed = i40e_bus_speed_2500; 4342 break; 4343 case PCI_EXP_LNKSTA_CLS_5_0GB: 4344 hw->bus.speed = i40e_bus_speed_5000; 4345 break; 4346 case PCI_EXP_LNKSTA_CLS_8_0GB: 4347 hw->bus.speed = i40e_bus_speed_8000; 4348 break; 4349 default: 4350 hw->bus.speed = i40e_bus_speed_unknown; 4351 break; 4352 } 4353 } 4354 4355 /** 4356 * i40e_aq_debug_dump 4357 * @hw: pointer to the hardware structure 4358 * @cluster_id: specific cluster to dump 4359 * @table_id: table id within cluster 4360 * @start_index: index of line in the block to read 4361 * @buff_size: dump buffer size 4362 * @buff: dump buffer 4363 * @ret_buff_size: actual buffer size returned 4364 * @ret_next_table: next block to read 4365 * @ret_next_index: next index to read 4366 * 4367 * Dump internal FW/HW data for debug purposes. 4368 * 4369 **/ 4370 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4371 u8 table_id, u32 start_index, u16 buff_size, 4372 void *buff, u16 *ret_buff_size, 4373 u8 *ret_next_table, u32 *ret_next_index, 4374 struct i40e_asq_cmd_details *cmd_details) 4375 { 4376 struct i40e_aq_desc desc; 4377 struct i40e_aqc_debug_dump_internals *cmd = 4378 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4379 struct i40e_aqc_debug_dump_internals *resp = 4380 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4381 i40e_status status; 4382 4383 if (buff_size == 0 || !buff) 4384 return I40E_ERR_PARAM; 4385 4386 i40e_fill_default_direct_cmd_desc(&desc, 4387 i40e_aqc_opc_debug_dump_internals); 4388 /* Indirect Command */ 4389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4390 if (buff_size > I40E_AQ_LARGE_BUF) 4391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4392 4393 cmd->cluster_id = cluster_id; 4394 cmd->table_id = table_id; 4395 cmd->idx = cpu_to_le32(start_index); 4396 4397 desc.datalen = cpu_to_le16(buff_size); 4398 4399 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4400 if (!status) { 4401 if (ret_buff_size) 4402 *ret_buff_size = le16_to_cpu(desc.datalen); 4403 if (ret_next_table) 4404 *ret_next_table = resp->table_id; 4405 if (ret_next_index) 4406 *ret_next_index = le32_to_cpu(resp->idx); 4407 } 4408 4409 return status; 4410 } 4411 4412 /** 4413 * i40e_read_bw_from_alt_ram 4414 * @hw: pointer to the hardware structure 4415 * @max_bw: pointer for max_bw read 4416 * @min_bw: pointer for min_bw read 4417 * @min_valid: pointer for bool that is true if min_bw is a valid value 4418 * @max_valid: pointer for bool that is true if max_bw is a valid value 4419 * 4420 * Read bw from the alternate ram for the given pf 4421 **/ 4422 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4423 u32 *max_bw, u32 *min_bw, 4424 bool *min_valid, bool *max_valid) 4425 { 4426 i40e_status status; 4427 u32 max_bw_addr, min_bw_addr; 4428 4429 /* Calculate the address of the min/max bw registers */ 4430 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4431 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4432 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4433 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4434 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4435 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4436 4437 /* Read the bandwidths from alt ram */ 4438 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4439 min_bw_addr, min_bw); 4440 4441 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4442 *min_valid = true; 4443 else 4444 *min_valid = false; 4445 4446 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4447 *max_valid = true; 4448 else 4449 *max_valid = false; 4450 4451 return status; 4452 } 4453 4454 /** 4455 * i40e_aq_configure_partition_bw 4456 * @hw: pointer to the hardware structure 4457 * @bw_data: Buffer holding valid pfs and bw limits 4458 * @cmd_details: pointer to command details 4459 * 4460 * Configure partitions guaranteed/max bw 4461 **/ 4462 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4463 struct i40e_aqc_configure_partition_bw_data *bw_data, 4464 struct i40e_asq_cmd_details *cmd_details) 4465 { 4466 i40e_status status; 4467 struct i40e_aq_desc desc; 4468 u16 bwd_size = sizeof(*bw_data); 4469 4470 i40e_fill_default_direct_cmd_desc(&desc, 4471 i40e_aqc_opc_configure_partition_bw); 4472 4473 /* Indirect command */ 4474 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4475 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4476 4477 if (bwd_size > I40E_AQ_LARGE_BUF) 4478 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4479 4480 desc.datalen = cpu_to_le16(bwd_size); 4481 4482 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4483 cmd_details); 4484 4485 return status; 4486 } 4487 4488 /** 4489 * i40e_read_phy_register_clause22 4490 * @hw: pointer to the HW structure 4491 * @reg: register address in the page 4492 * @phy_adr: PHY address on MDIO interface 4493 * @value: PHY register value 4494 * 4495 * Reads specified PHY register value 4496 **/ 4497 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4498 u16 reg, u8 phy_addr, u16 *value) 4499 { 4500 i40e_status status = I40E_ERR_TIMEOUT; 4501 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4502 u32 command = 0; 4503 u16 retry = 1000; 4504 4505 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4506 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4507 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4508 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4509 (I40E_GLGEN_MSCA_MDICMD_MASK); 4510 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4511 do { 4512 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4513 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4514 status = 0; 4515 break; 4516 } 4517 udelay(10); 4518 retry--; 4519 } while (retry); 4520 4521 if (status) { 4522 i40e_debug(hw, I40E_DEBUG_PHY, 4523 "PHY: Can't write command to external PHY.\n"); 4524 } else { 4525 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4526 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4527 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4528 } 4529 4530 return status; 4531 } 4532 4533 /** 4534 * i40e_write_phy_register_clause22 4535 * @hw: pointer to the HW structure 4536 * @reg: register address in the page 4537 * @phy_adr: PHY address on MDIO interface 4538 * @value: PHY register value 4539 * 4540 * Writes specified PHY register value 4541 **/ 4542 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4543 u16 reg, u8 phy_addr, u16 value) 4544 { 4545 i40e_status status = I40E_ERR_TIMEOUT; 4546 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4547 u32 command = 0; 4548 u16 retry = 1000; 4549 4550 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4551 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4552 4553 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4554 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4555 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4556 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4557 (I40E_GLGEN_MSCA_MDICMD_MASK); 4558 4559 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4560 do { 4561 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4562 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4563 status = 0; 4564 break; 4565 } 4566 udelay(10); 4567 retry--; 4568 } while (retry); 4569 4570 return status; 4571 } 4572 4573 /** 4574 * i40e_read_phy_register_clause45 4575 * @hw: pointer to the HW structure 4576 * @page: registers page number 4577 * @reg: register address in the page 4578 * @phy_adr: PHY address on MDIO interface 4579 * @value: PHY register value 4580 * 4581 * Reads specified PHY register value 4582 **/ 4583 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4584 u8 page, u16 reg, u8 phy_addr, u16 *value) 4585 { 4586 i40e_status status = I40E_ERR_TIMEOUT; 4587 u32 command = 0; 4588 u16 retry = 1000; 4589 u8 port_num = hw->func_caps.mdio_port_num; 4590 4591 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4592 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4593 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4594 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4595 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4596 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4597 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4598 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4599 do { 4600 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4601 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4602 status = 0; 4603 break; 4604 } 4605 usleep_range(10, 20); 4606 retry--; 4607 } while (retry); 4608 4609 if (status) { 4610 i40e_debug(hw, I40E_DEBUG_PHY, 4611 "PHY: Can't write command to external PHY.\n"); 4612 goto phy_read_end; 4613 } 4614 4615 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4616 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4617 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4618 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4619 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4620 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4621 status = I40E_ERR_TIMEOUT; 4622 retry = 1000; 4623 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4624 do { 4625 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4626 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4627 status = 0; 4628 break; 4629 } 4630 usleep_range(10, 20); 4631 retry--; 4632 } while (retry); 4633 4634 if (!status) { 4635 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4636 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4637 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4638 } else { 4639 i40e_debug(hw, I40E_DEBUG_PHY, 4640 "PHY: Can't read register value from external PHY.\n"); 4641 } 4642 4643 phy_read_end: 4644 return status; 4645 } 4646 4647 /** 4648 * i40e_write_phy_register_clause45 4649 * @hw: pointer to the HW structure 4650 * @page: registers page number 4651 * @reg: register address in the page 4652 * @phy_adr: PHY address on MDIO interface 4653 * @value: PHY register value 4654 * 4655 * Writes value to specified PHY register 4656 **/ 4657 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4658 u8 page, u16 reg, u8 phy_addr, u16 value) 4659 { 4660 i40e_status status = I40E_ERR_TIMEOUT; 4661 u32 command = 0; 4662 u16 retry = 1000; 4663 u8 port_num = hw->func_caps.mdio_port_num; 4664 4665 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4666 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4667 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4668 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4669 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4670 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4671 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4672 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4673 do { 4674 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4675 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4676 status = 0; 4677 break; 4678 } 4679 usleep_range(10, 20); 4680 retry--; 4681 } while (retry); 4682 if (status) { 4683 i40e_debug(hw, I40E_DEBUG_PHY, 4684 "PHY: Can't write command to external PHY.\n"); 4685 goto phy_write_end; 4686 } 4687 4688 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4689 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4690 4691 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4692 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4693 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4694 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4695 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4696 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4697 status = I40E_ERR_TIMEOUT; 4698 retry = 1000; 4699 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4700 do { 4701 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4702 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4703 status = 0; 4704 break; 4705 } 4706 usleep_range(10, 20); 4707 retry--; 4708 } while (retry); 4709 4710 phy_write_end: 4711 return status; 4712 } 4713 4714 /** 4715 * i40e_write_phy_register 4716 * @hw: pointer to the HW structure 4717 * @page: registers page number 4718 * @reg: register address in the page 4719 * @phy_adr: PHY address on MDIO interface 4720 * @value: PHY register value 4721 * 4722 * Writes value to specified PHY register 4723 **/ 4724 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4725 u8 page, u16 reg, u8 phy_addr, u16 value) 4726 { 4727 i40e_status status; 4728 4729 switch (hw->device_id) { 4730 case I40E_DEV_ID_1G_BASE_T_X722: 4731 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4732 value); 4733 break; 4734 case I40E_DEV_ID_10G_BASE_T: 4735 case I40E_DEV_ID_10G_BASE_T4: 4736 case I40E_DEV_ID_10G_BASE_T_X722: 4737 case I40E_DEV_ID_25G_B: 4738 case I40E_DEV_ID_25G_SFP28: 4739 status = i40e_write_phy_register_clause45(hw, page, reg, 4740 phy_addr, value); 4741 break; 4742 default: 4743 status = I40E_ERR_UNKNOWN_PHY; 4744 break; 4745 } 4746 4747 return status; 4748 } 4749 4750 /** 4751 * i40e_read_phy_register 4752 * @hw: pointer to the HW structure 4753 * @page: registers page number 4754 * @reg: register address in the page 4755 * @phy_adr: PHY address on MDIO interface 4756 * @value: PHY register value 4757 * 4758 * Reads specified PHY register value 4759 **/ 4760 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4761 u8 page, u16 reg, u8 phy_addr, u16 *value) 4762 { 4763 i40e_status status; 4764 4765 switch (hw->device_id) { 4766 case I40E_DEV_ID_1G_BASE_T_X722: 4767 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4768 value); 4769 break; 4770 case I40E_DEV_ID_10G_BASE_T: 4771 case I40E_DEV_ID_10G_BASE_T4: 4772 case I40E_DEV_ID_10G_BASE_T_X722: 4773 case I40E_DEV_ID_25G_B: 4774 case I40E_DEV_ID_25G_SFP28: 4775 status = i40e_read_phy_register_clause45(hw, page, reg, 4776 phy_addr, value); 4777 break; 4778 default: 4779 status = I40E_ERR_UNKNOWN_PHY; 4780 break; 4781 } 4782 4783 return status; 4784 } 4785 4786 /** 4787 * i40e_get_phy_address 4788 * @hw: pointer to the HW structure 4789 * @dev_num: PHY port num that address we want 4790 * @phy_addr: Returned PHY address 4791 * 4792 * Gets PHY address for current port 4793 **/ 4794 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4795 { 4796 u8 port_num = hw->func_caps.mdio_port_num; 4797 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4798 4799 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4800 } 4801 4802 /** 4803 * i40e_blink_phy_led 4804 * @hw: pointer to the HW structure 4805 * @time: time how long led will blinks in secs 4806 * @interval: gap between LED on and off in msecs 4807 * 4808 * Blinks PHY link LED 4809 **/ 4810 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4811 u32 time, u32 interval) 4812 { 4813 i40e_status status = 0; 4814 u32 i; 4815 u16 led_ctl; 4816 u16 gpio_led_port; 4817 u16 led_reg; 4818 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4819 u8 phy_addr = 0; 4820 u8 port_num; 4821 4822 i = rd32(hw, I40E_PFGEN_PORTNUM); 4823 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4824 phy_addr = i40e_get_phy_address(hw, port_num); 4825 4826 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4827 led_addr++) { 4828 status = i40e_read_phy_register_clause45(hw, 4829 I40E_PHY_COM_REG_PAGE, 4830 led_addr, phy_addr, 4831 &led_reg); 4832 if (status) 4833 goto phy_blinking_end; 4834 led_ctl = led_reg; 4835 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4836 led_reg = 0; 4837 status = i40e_write_phy_register_clause45(hw, 4838 I40E_PHY_COM_REG_PAGE, 4839 led_addr, phy_addr, 4840 led_reg); 4841 if (status) 4842 goto phy_blinking_end; 4843 break; 4844 } 4845 } 4846 4847 if (time > 0 && interval > 0) { 4848 for (i = 0; i < time * 1000; i += interval) { 4849 status = i40e_read_phy_register_clause45(hw, 4850 I40E_PHY_COM_REG_PAGE, 4851 led_addr, phy_addr, &led_reg); 4852 if (status) 4853 goto restore_config; 4854 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4855 led_reg = 0; 4856 else 4857 led_reg = I40E_PHY_LED_MANUAL_ON; 4858 status = i40e_write_phy_register_clause45(hw, 4859 I40E_PHY_COM_REG_PAGE, 4860 led_addr, phy_addr, led_reg); 4861 if (status) 4862 goto restore_config; 4863 msleep(interval); 4864 } 4865 } 4866 4867 restore_config: 4868 status = i40e_write_phy_register_clause45(hw, 4869 I40E_PHY_COM_REG_PAGE, 4870 led_addr, phy_addr, led_ctl); 4871 4872 phy_blinking_end: 4873 return status; 4874 } 4875 4876 /** 4877 * i40e_led_get_reg - read LED register 4878 * @hw: pointer to the HW structure 4879 * @led_addr: LED register address 4880 * @reg_val: read register value 4881 **/ 4882 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4883 u32 *reg_val) 4884 { 4885 enum i40e_status_code status; 4886 u8 phy_addr = 0; 4887 u8 port_num; 4888 u32 i; 4889 4890 *reg_val = 0; 4891 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4892 status = 4893 i40e_aq_get_phy_register(hw, 4894 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4895 I40E_PHY_COM_REG_PAGE, 4896 I40E_PHY_LED_PROV_REG_1, 4897 reg_val, NULL); 4898 } else { 4899 i = rd32(hw, I40E_PFGEN_PORTNUM); 4900 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4901 phy_addr = i40e_get_phy_address(hw, port_num); 4902 status = i40e_read_phy_register_clause45(hw, 4903 I40E_PHY_COM_REG_PAGE, 4904 led_addr, phy_addr, 4905 (u16 *)reg_val); 4906 } 4907 return status; 4908 } 4909 4910 /** 4911 * i40e_led_set_reg - write LED register 4912 * @hw: pointer to the HW structure 4913 * @led_addr: LED register address 4914 * @reg_val: register value to write 4915 **/ 4916 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4917 u32 reg_val) 4918 { 4919 enum i40e_status_code status; 4920 u8 phy_addr = 0; 4921 u8 port_num; 4922 u32 i; 4923 4924 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4925 status = 4926 i40e_aq_set_phy_register(hw, 4927 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4928 I40E_PHY_COM_REG_PAGE, 4929 I40E_PHY_LED_PROV_REG_1, 4930 reg_val, NULL); 4931 } else { 4932 i = rd32(hw, I40E_PFGEN_PORTNUM); 4933 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4934 phy_addr = i40e_get_phy_address(hw, port_num); 4935 status = i40e_write_phy_register_clause45(hw, 4936 I40E_PHY_COM_REG_PAGE, 4937 led_addr, phy_addr, 4938 (u16)reg_val); 4939 } 4940 4941 return status; 4942 } 4943 4944 /** 4945 * i40e_led_get_phy - return current on/off mode 4946 * @hw: pointer to the hw struct 4947 * @led_addr: address of led register to use 4948 * @val: original value of register to use 4949 * 4950 **/ 4951 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4952 u16 *val) 4953 { 4954 i40e_status status = 0; 4955 u16 gpio_led_port; 4956 u8 phy_addr = 0; 4957 u16 reg_val; 4958 u16 temp_addr; 4959 u8 port_num; 4960 u32 i; 4961 u32 reg_val_aq; 4962 4963 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4964 status = 4965 i40e_aq_get_phy_register(hw, 4966 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4967 I40E_PHY_COM_REG_PAGE, 4968 I40E_PHY_LED_PROV_REG_1, 4969 ®_val_aq, NULL); 4970 if (status == I40E_SUCCESS) 4971 *val = (u16)reg_val_aq; 4972 return status; 4973 } 4974 temp_addr = I40E_PHY_LED_PROV_REG_1; 4975 i = rd32(hw, I40E_PFGEN_PORTNUM); 4976 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4977 phy_addr = i40e_get_phy_address(hw, port_num); 4978 4979 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4980 temp_addr++) { 4981 status = i40e_read_phy_register_clause45(hw, 4982 I40E_PHY_COM_REG_PAGE, 4983 temp_addr, phy_addr, 4984 ®_val); 4985 if (status) 4986 return status; 4987 *val = reg_val; 4988 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4989 *led_addr = temp_addr; 4990 break; 4991 } 4992 } 4993 return status; 4994 } 4995 4996 /** 4997 * i40e_led_set_phy 4998 * @hw: pointer to the HW structure 4999 * @on: true or false 5000 * @mode: original val plus bit for set or ignore 5001 * Set led's on or off when controlled by the PHY 5002 * 5003 **/ 5004 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 5005 u16 led_addr, u32 mode) 5006 { 5007 i40e_status status = 0; 5008 u32 led_ctl = 0; 5009 u32 led_reg = 0; 5010 5011 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5012 if (status) 5013 return status; 5014 led_ctl = led_reg; 5015 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5016 led_reg = 0; 5017 status = i40e_led_set_reg(hw, led_addr, led_reg); 5018 if (status) 5019 return status; 5020 } 5021 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5022 if (status) 5023 goto restore_config; 5024 if (on) 5025 led_reg = I40E_PHY_LED_MANUAL_ON; 5026 else 5027 led_reg = 0; 5028 5029 status = i40e_led_set_reg(hw, led_addr, led_reg); 5030 if (status) 5031 goto restore_config; 5032 if (mode & I40E_PHY_LED_MODE_ORIG) { 5033 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5034 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5035 } 5036 return status; 5037 5038 restore_config: 5039 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5040 return status; 5041 } 5042 5043 /** 5044 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5045 * @hw: pointer to the hw struct 5046 * @reg_addr: register address 5047 * @reg_val: ptr to register value 5048 * @cmd_details: pointer to command details structure or NULL 5049 * 5050 * Use the firmware to read the Rx control register, 5051 * especially useful if the Rx unit is under heavy pressure 5052 **/ 5053 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5054 u32 reg_addr, u32 *reg_val, 5055 struct i40e_asq_cmd_details *cmd_details) 5056 { 5057 struct i40e_aq_desc desc; 5058 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5059 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5060 i40e_status status; 5061 5062 if (!reg_val) 5063 return I40E_ERR_PARAM; 5064 5065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5066 5067 cmd_resp->address = cpu_to_le32(reg_addr); 5068 5069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5070 5071 if (status == 0) 5072 *reg_val = le32_to_cpu(cmd_resp->value); 5073 5074 return status; 5075 } 5076 5077 /** 5078 * i40e_read_rx_ctl - read from an Rx control register 5079 * @hw: pointer to the hw struct 5080 * @reg_addr: register address 5081 **/ 5082 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5083 { 5084 i40e_status status = 0; 5085 bool use_register; 5086 int retry = 5; 5087 u32 val = 0; 5088 5089 use_register = (((hw->aq.api_maj_ver == 1) && 5090 (hw->aq.api_min_ver < 5)) || 5091 (hw->mac.type == I40E_MAC_X722)); 5092 if (!use_register) { 5093 do_retry: 5094 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5095 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5096 usleep_range(1000, 2000); 5097 retry--; 5098 goto do_retry; 5099 } 5100 } 5101 5102 /* if the AQ access failed, try the old-fashioned way */ 5103 if (status || use_register) 5104 val = rd32(hw, reg_addr); 5105 5106 return val; 5107 } 5108 5109 /** 5110 * i40e_aq_rx_ctl_write_register 5111 * @hw: pointer to the hw struct 5112 * @reg_addr: register address 5113 * @reg_val: register value 5114 * @cmd_details: pointer to command details structure or NULL 5115 * 5116 * Use the firmware to write to an Rx control register, 5117 * especially useful if the Rx unit is under heavy pressure 5118 **/ 5119 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5120 u32 reg_addr, u32 reg_val, 5121 struct i40e_asq_cmd_details *cmd_details) 5122 { 5123 struct i40e_aq_desc desc; 5124 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5125 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5126 i40e_status status; 5127 5128 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5129 5130 cmd->address = cpu_to_le32(reg_addr); 5131 cmd->value = cpu_to_le32(reg_val); 5132 5133 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5134 5135 return status; 5136 } 5137 5138 /** 5139 * i40e_write_rx_ctl - write to an Rx control register 5140 * @hw: pointer to the hw struct 5141 * @reg_addr: register address 5142 * @reg_val: register value 5143 **/ 5144 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5145 { 5146 i40e_status status = 0; 5147 bool use_register; 5148 int retry = 5; 5149 5150 use_register = (((hw->aq.api_maj_ver == 1) && 5151 (hw->aq.api_min_ver < 5)) || 5152 (hw->mac.type == I40E_MAC_X722)); 5153 if (!use_register) { 5154 do_retry: 5155 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5156 reg_val, NULL); 5157 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5158 usleep_range(1000, 2000); 5159 retry--; 5160 goto do_retry; 5161 } 5162 } 5163 5164 /* if the AQ access failed, try the old-fashioned way */ 5165 if (status || use_register) 5166 wr32(hw, reg_addr, reg_val); 5167 } 5168 5169 /** 5170 * i40e_aq_set_phy_register 5171 * @hw: pointer to the hw struct 5172 * @phy_select: select which phy should be accessed 5173 * @dev_addr: PHY device address 5174 * @reg_addr: PHY register address 5175 * @reg_val: new register value 5176 * @cmd_details: pointer to command details structure or NULL 5177 * 5178 * Write the external PHY register. 5179 **/ 5180 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5181 u8 phy_select, u8 dev_addr, 5182 u32 reg_addr, u32 reg_val, 5183 struct i40e_asq_cmd_details *cmd_details) 5184 { 5185 struct i40e_aq_desc desc; 5186 struct i40e_aqc_phy_register_access *cmd = 5187 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5188 i40e_status status; 5189 5190 i40e_fill_default_direct_cmd_desc(&desc, 5191 i40e_aqc_opc_set_phy_register); 5192 5193 cmd->phy_interface = phy_select; 5194 cmd->dev_address = dev_addr; 5195 cmd->reg_address = cpu_to_le32(reg_addr); 5196 cmd->reg_value = cpu_to_le32(reg_val); 5197 5198 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5199 5200 return status; 5201 } 5202 5203 /** 5204 * i40e_aq_get_phy_register 5205 * @hw: pointer to the hw struct 5206 * @phy_select: select which phy should be accessed 5207 * @dev_addr: PHY device address 5208 * @reg_addr: PHY register address 5209 * @reg_val: read register value 5210 * @cmd_details: pointer to command details structure or NULL 5211 * 5212 * Read the external PHY register. 5213 **/ 5214 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5215 u8 phy_select, u8 dev_addr, 5216 u32 reg_addr, u32 *reg_val, 5217 struct i40e_asq_cmd_details *cmd_details) 5218 { 5219 struct i40e_aq_desc desc; 5220 struct i40e_aqc_phy_register_access *cmd = 5221 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5222 i40e_status status; 5223 5224 i40e_fill_default_direct_cmd_desc(&desc, 5225 i40e_aqc_opc_get_phy_register); 5226 5227 cmd->phy_interface = phy_select; 5228 cmd->dev_address = dev_addr; 5229 cmd->reg_address = cpu_to_le32(reg_addr); 5230 5231 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5232 if (!status) 5233 *reg_val = le32_to_cpu(cmd->reg_value); 5234 5235 return status; 5236 } 5237 5238 /** 5239 * i40e_aq_write_ppp - Write pipeline personalization profile (ppp) 5240 * @hw: pointer to the hw struct 5241 * @buff: command buffer (size in bytes = buff_size) 5242 * @buff_size: buffer size in bytes 5243 * @track_id: package tracking id 5244 * @error_offset: returns error offset 5245 * @error_info: returns error information 5246 * @cmd_details: pointer to command details structure or NULL 5247 **/ 5248 enum 5249 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff, 5250 u16 buff_size, u32 track_id, 5251 u32 *error_offset, u32 *error_info, 5252 struct i40e_asq_cmd_details *cmd_details) 5253 { 5254 struct i40e_aq_desc desc; 5255 struct i40e_aqc_write_personalization_profile *cmd = 5256 (struct i40e_aqc_write_personalization_profile *) 5257 &desc.params.raw; 5258 struct i40e_aqc_write_ppp_resp *resp; 5259 i40e_status status; 5260 5261 i40e_fill_default_direct_cmd_desc(&desc, 5262 i40e_aqc_opc_write_personalization_profile); 5263 5264 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5265 if (buff_size > I40E_AQ_LARGE_BUF) 5266 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5267 5268 desc.datalen = cpu_to_le16(buff_size); 5269 5270 cmd->profile_track_id = cpu_to_le32(track_id); 5271 5272 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5273 if (!status) { 5274 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw; 5275 if (error_offset) 5276 *error_offset = le32_to_cpu(resp->error_offset); 5277 if (error_info) 5278 *error_info = le32_to_cpu(resp->error_info); 5279 } 5280 5281 return status; 5282 } 5283 5284 /** 5285 * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp) 5286 * @hw: pointer to the hw struct 5287 * @buff: command buffer (size in bytes = buff_size) 5288 * @buff_size: buffer size in bytes 5289 * @cmd_details: pointer to command details structure or NULL 5290 **/ 5291 enum 5292 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff, 5293 u16 buff_size, u8 flags, 5294 struct i40e_asq_cmd_details *cmd_details) 5295 { 5296 struct i40e_aq_desc desc; 5297 struct i40e_aqc_get_applied_profiles *cmd = 5298 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5299 i40e_status status; 5300 5301 i40e_fill_default_direct_cmd_desc(&desc, 5302 i40e_aqc_opc_get_personalization_profile_list); 5303 5304 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5305 if (buff_size > I40E_AQ_LARGE_BUF) 5306 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5307 desc.datalen = cpu_to_le16(buff_size); 5308 5309 cmd->flags = flags; 5310 5311 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5312 5313 return status; 5314 } 5315 5316 /** 5317 * i40e_find_segment_in_package 5318 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5319 * @pkg_hdr: pointer to the package header to be searched 5320 * 5321 * This function searches a package file for a particular segment type. On 5322 * success it returns a pointer to the segment header, otherwise it will 5323 * return NULL. 5324 **/ 5325 struct i40e_generic_seg_header * 5326 i40e_find_segment_in_package(u32 segment_type, 5327 struct i40e_package_header *pkg_hdr) 5328 { 5329 struct i40e_generic_seg_header *segment; 5330 u32 i; 5331 5332 /* Search all package segments for the requested segment type */ 5333 for (i = 0; i < pkg_hdr->segment_count; i++) { 5334 segment = 5335 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5336 pkg_hdr->segment_offset[i]); 5337 5338 if (segment->type == segment_type) 5339 return segment; 5340 } 5341 5342 return NULL; 5343 } 5344 5345 /** 5346 * i40e_write_profile 5347 * @hw: pointer to the hardware structure 5348 * @profile: pointer to the profile segment of the package to be downloaded 5349 * @track_id: package tracking id 5350 * 5351 * Handles the download of a complete package. 5352 */ 5353 enum i40e_status_code 5354 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5355 u32 track_id) 5356 { 5357 i40e_status status = 0; 5358 struct i40e_section_table *sec_tbl; 5359 struct i40e_profile_section_header *sec = NULL; 5360 u32 dev_cnt; 5361 u32 vendor_dev_id; 5362 u32 *nvm; 5363 u32 section_size = 0; 5364 u32 offset = 0, info = 0; 5365 u32 i; 5366 5367 if (!track_id) { 5368 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0."); 5369 return I40E_NOT_SUPPORTED; 5370 } 5371 5372 dev_cnt = profile->device_table_count; 5373 5374 for (i = 0; i < dev_cnt; i++) { 5375 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5376 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5377 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5378 break; 5379 } 5380 if (i == dev_cnt) { 5381 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP"); 5382 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5383 } 5384 5385 nvm = (u32 *)&profile->device_table[dev_cnt]; 5386 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5387 5388 for (i = 0; i < sec_tbl->section_count; i++) { 5389 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5390 sec_tbl->section_offset[i]); 5391 5392 /* Skip 'AQ', 'note' and 'name' sections */ 5393 if (sec->section.type != SECTION_TYPE_MMIO) 5394 continue; 5395 5396 section_size = sec->section.size + 5397 sizeof(struct i40e_profile_section_header); 5398 5399 /* Write profile */ 5400 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size, 5401 track_id, &offset, &info, NULL); 5402 if (status) { 5403 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5404 "Failed to write profile: offset %d, info %d", 5405 offset, info); 5406 break; 5407 } 5408 } 5409 return status; 5410 } 5411 5412 /** 5413 * i40e_add_pinfo_to_list 5414 * @hw: pointer to the hardware structure 5415 * @profile: pointer to the profile segment of the package 5416 * @profile_info_sec: buffer for information section 5417 * @track_id: package tracking id 5418 * 5419 * Register a profile to the list of loaded profiles. 5420 */ 5421 enum i40e_status_code 5422 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5423 struct i40e_profile_segment *profile, 5424 u8 *profile_info_sec, u32 track_id) 5425 { 5426 i40e_status status = 0; 5427 struct i40e_profile_section_header *sec = NULL; 5428 struct i40e_profile_info *pinfo; 5429 u32 offset = 0, info = 0; 5430 5431 sec = (struct i40e_profile_section_header *)profile_info_sec; 5432 sec->tbl_size = 1; 5433 sec->data_end = sizeof(struct i40e_profile_section_header) + 5434 sizeof(struct i40e_profile_info); 5435 sec->section.type = SECTION_TYPE_INFO; 5436 sec->section.offset = sizeof(struct i40e_profile_section_header); 5437 sec->section.size = sizeof(struct i40e_profile_info); 5438 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5439 sec->section.offset); 5440 pinfo->track_id = track_id; 5441 pinfo->version = profile->version; 5442 pinfo->op = I40E_PPP_ADD_TRACKID; 5443 memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE); 5444 5445 status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end, 5446 track_id, &offset, &info, NULL); 5447 5448 return status; 5449 } 5450 5451 /** 5452 * i40e_aq_add_cloud_filters 5453 * @hw: pointer to the hardware structure 5454 * @seid: VSI seid to add cloud filters from 5455 * @filters: Buffer which contains the filters to be added 5456 * @filter_count: number of filters contained in the buffer 5457 * 5458 * Set the cloud filters for a given VSI. The contents of the 5459 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5460 * of the function. 5461 * 5462 **/ 5463 enum i40e_status_code 5464 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5465 struct i40e_aqc_cloud_filters_element_data *filters, 5466 u8 filter_count) 5467 { 5468 struct i40e_aq_desc desc; 5469 struct i40e_aqc_add_remove_cloud_filters *cmd = 5470 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5471 enum i40e_status_code status; 5472 u16 buff_len; 5473 5474 i40e_fill_default_direct_cmd_desc(&desc, 5475 i40e_aqc_opc_add_cloud_filters); 5476 5477 buff_len = filter_count * sizeof(*filters); 5478 desc.datalen = cpu_to_le16(buff_len); 5479 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5480 cmd->num_filters = filter_count; 5481 cmd->seid = cpu_to_le16(seid); 5482 5483 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5484 5485 return status; 5486 } 5487 5488 /** 5489 * i40e_aq_add_cloud_filters_bb 5490 * @hw: pointer to the hardware structure 5491 * @seid: VSI seid to add cloud filters from 5492 * @filters: Buffer which contains the filters in big buffer to be added 5493 * @filter_count: number of filters contained in the buffer 5494 * 5495 * Set the big buffer cloud filters for a given VSI. The contents of the 5496 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5497 * function. 5498 * 5499 **/ 5500 i40e_status 5501 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5502 struct i40e_aqc_cloud_filters_element_bb *filters, 5503 u8 filter_count) 5504 { 5505 struct i40e_aq_desc desc; 5506 struct i40e_aqc_add_remove_cloud_filters *cmd = 5507 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5508 i40e_status status; 5509 u16 buff_len; 5510 int i; 5511 5512 i40e_fill_default_direct_cmd_desc(&desc, 5513 i40e_aqc_opc_add_cloud_filters); 5514 5515 buff_len = filter_count * sizeof(*filters); 5516 desc.datalen = cpu_to_le16(buff_len); 5517 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5518 cmd->num_filters = filter_count; 5519 cmd->seid = cpu_to_le16(seid); 5520 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5521 5522 for (i = 0; i < filter_count; i++) { 5523 u16 tnl_type; 5524 u32 ti; 5525 5526 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5527 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5528 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5529 5530 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5531 * one more byte further than normally used for Tenant ID in 5532 * other tunnel types. 5533 */ 5534 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5535 ti = le32_to_cpu(filters[i].element.tenant_id); 5536 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5537 } 5538 } 5539 5540 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5541 5542 return status; 5543 } 5544 5545 /** 5546 * i40e_aq_rem_cloud_filters 5547 * @hw: pointer to the hardware structure 5548 * @seid: VSI seid to remove cloud filters from 5549 * @filters: Buffer which contains the filters to be removed 5550 * @filter_count: number of filters contained in the buffer 5551 * 5552 * Remove the cloud filters for a given VSI. The contents of the 5553 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5554 * of the function. 5555 * 5556 **/ 5557 enum i40e_status_code 5558 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5559 struct i40e_aqc_cloud_filters_element_data *filters, 5560 u8 filter_count) 5561 { 5562 struct i40e_aq_desc desc; 5563 struct i40e_aqc_add_remove_cloud_filters *cmd = 5564 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5565 enum i40e_status_code status; 5566 u16 buff_len; 5567 5568 i40e_fill_default_direct_cmd_desc(&desc, 5569 i40e_aqc_opc_remove_cloud_filters); 5570 5571 buff_len = filter_count * sizeof(*filters); 5572 desc.datalen = cpu_to_le16(buff_len); 5573 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5574 cmd->num_filters = filter_count; 5575 cmd->seid = cpu_to_le16(seid); 5576 5577 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5578 5579 return status; 5580 } 5581 5582 /** 5583 * i40e_aq_rem_cloud_filters_bb 5584 * @hw: pointer to the hardware structure 5585 * @seid: VSI seid to remove cloud filters from 5586 * @filters: Buffer which contains the filters in big buffer to be removed 5587 * @filter_count: number of filters contained in the buffer 5588 * 5589 * Remove the big buffer cloud filters for a given VSI. The contents of the 5590 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5591 * function. 5592 * 5593 **/ 5594 i40e_status 5595 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5596 struct i40e_aqc_cloud_filters_element_bb *filters, 5597 u8 filter_count) 5598 { 5599 struct i40e_aq_desc desc; 5600 struct i40e_aqc_add_remove_cloud_filters *cmd = 5601 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5602 i40e_status status; 5603 u16 buff_len; 5604 int i; 5605 5606 i40e_fill_default_direct_cmd_desc(&desc, 5607 i40e_aqc_opc_remove_cloud_filters); 5608 5609 buff_len = filter_count * sizeof(*filters); 5610 desc.datalen = cpu_to_le16(buff_len); 5611 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5612 cmd->num_filters = filter_count; 5613 cmd->seid = cpu_to_le16(seid); 5614 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5615 5616 for (i = 0; i < filter_count; i++) { 5617 u16 tnl_type; 5618 u32 ti; 5619 5620 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5621 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5622 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5623 5624 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5625 * one more byte further than normally used for Tenant ID in 5626 * other tunnel types. 5627 */ 5628 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5629 ti = le32_to_cpu(filters[i].element.tenant_id); 5630 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5631 } 5632 } 5633 5634 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5635 5636 return status; 5637 } 5638