1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include <linux/avf/virtchnl.h> 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 304 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 305 return; 306 307 len = le16_to_cpu(aq_desc->datalen); 308 309 i40e_debug(hw, mask, 310 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 311 le16_to_cpu(aq_desc->opcode), 312 le16_to_cpu(aq_desc->flags), 313 le16_to_cpu(aq_desc->datalen), 314 le16_to_cpu(aq_desc->retval)); 315 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 316 le32_to_cpu(aq_desc->cookie_high), 317 le32_to_cpu(aq_desc->cookie_low)); 318 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->params.internal.param0), 320 le32_to_cpu(aq_desc->params.internal.param1)); 321 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.external.addr_high), 323 le32_to_cpu(aq_desc->params.external.addr_low)); 324 325 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 326 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 327 if (buf_len < len) 328 len = buf_len; 329 /* write the full 16-byte chunks */ 330 if (hw->debug_mask & mask) { 331 char prefix[27]; 332 333 snprintf(prefix, sizeof(prefix), 334 "i40e %02x:%02x.%x: \t0x", 335 hw->bus.bus_id, 336 hw->bus.device, 337 hw->bus.func); 338 339 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 340 16, 1, buf, len, false); 341 } 342 } 343 } 344 345 /** 346 * i40e_check_asq_alive 347 * @hw: pointer to the hw struct 348 * 349 * Returns true if Queue is enabled else false. 350 **/ 351 bool i40e_check_asq_alive(struct i40e_hw *hw) 352 { 353 if (hw->aq.asq.len) 354 return !!(rd32(hw, hw->aq.asq.len) & 355 I40E_PF_ATQLEN_ATQENABLE_MASK); 356 else 357 return false; 358 } 359 360 /** 361 * i40e_aq_queue_shutdown 362 * @hw: pointer to the hw struct 363 * @unloading: is the driver unloading itself 364 * 365 * Tell the Firmware that we're shutting down the AdminQ and whether 366 * or not the driver is unloading as well. 367 **/ 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 369 bool unloading) 370 { 371 struct i40e_aq_desc desc; 372 struct i40e_aqc_queue_shutdown *cmd = 373 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 374 i40e_status status; 375 376 i40e_fill_default_direct_cmd_desc(&desc, 377 i40e_aqc_opc_queue_shutdown); 378 379 if (unloading) 380 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 381 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 382 383 return status; 384 } 385 386 /** 387 * i40e_aq_get_set_rss_lut 388 * @hw: pointer to the hardware structure 389 * @vsi_id: vsi fw index 390 * @pf_lut: for PF table set true, for VSI table set false 391 * @lut: pointer to the lut buffer provided by the caller 392 * @lut_size: size of the lut buffer 393 * @set: set true to set the table, false to get the table 394 * 395 * Internal function to get or set RSS look up table 396 **/ 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 398 u16 vsi_id, bool pf_lut, 399 u8 *lut, u16 lut_size, 400 bool set) 401 { 402 i40e_status status; 403 struct i40e_aq_desc desc; 404 struct i40e_aqc_get_set_rss_lut *cmd_resp = 405 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 406 407 if (set) 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_set_rss_lut); 410 else 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_get_rss_lut); 413 414 /* Indirect command */ 415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 417 418 cmd_resp->vsi_id = 419 cpu_to_le16((u16)((vsi_id << 420 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 422 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 423 424 if (pf_lut) 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 else 430 cmd_resp->flags |= cpu_to_le16((u16) 431 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 433 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 434 435 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 436 437 return status; 438 } 439 440 /** 441 * i40e_aq_get_rss_lut 442 * @hw: pointer to the hardware structure 443 * @vsi_id: vsi fw index 444 * @pf_lut: for PF table set true, for VSI table set false 445 * @lut: pointer to the lut buffer provided by the caller 446 * @lut_size: size of the lut buffer 447 * 448 * get the RSS lookup table, PF or VSI type 449 **/ 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 451 bool pf_lut, u8 *lut, u16 lut_size) 452 { 453 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 454 false); 455 } 456 457 /** 458 * i40e_aq_set_rss_lut 459 * @hw: pointer to the hardware structure 460 * @vsi_id: vsi fw index 461 * @pf_lut: for PF table set true, for VSI table set false 462 * @lut: pointer to the lut buffer provided by the caller 463 * @lut_size: size of the lut buffer 464 * 465 * set the RSS lookup table, PF or VSI type 466 **/ 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 468 bool pf_lut, u8 *lut, u16 lut_size) 469 { 470 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 471 } 472 473 /** 474 * i40e_aq_get_set_rss_key 475 * @hw: pointer to the hw struct 476 * @vsi_id: vsi fw index 477 * @key: pointer to key info struct 478 * @set: set true to set the key, false to get the key 479 * 480 * get the RSS key per VSI 481 **/ 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 483 u16 vsi_id, 484 struct i40e_aqc_get_set_rss_key_data *key, 485 bool set) 486 { 487 i40e_status status; 488 struct i40e_aq_desc desc; 489 struct i40e_aqc_get_set_rss_key *cmd_resp = 490 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 491 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 492 493 if (set) 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_set_rss_key); 496 else 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_get_rss_key); 499 500 /* Indirect command */ 501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 503 504 cmd_resp->vsi_id = 505 cpu_to_le16((u16)((vsi_id << 506 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 507 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 508 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 509 510 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 511 512 return status; 513 } 514 515 /** 516 * i40e_aq_get_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 **/ 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key) 525 { 526 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 527 } 528 529 /** 530 * i40e_aq_set_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 * set the RSS key per VSI 536 **/ 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 538 u16 vsi_id, 539 struct i40e_aqc_get_set_rss_key_data *key) 540 { 541 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 542 } 543 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 545 * hardware to a bit-field that can be used by SW to more easily determine the 546 * packet type. 547 * 548 * Macros are used to shorten the table lines and make this table human 549 * readable. 550 * 551 * We store the PTYPE in the top byte of the bit field - this is just so that 552 * we can check that the table doesn't have a row missing, as the index into 553 * the table should be the PTYPE. 554 * 555 * Typical work flow: 556 * 557 * IF NOT i40e_ptype_lookup[ptype].known 558 * THEN 559 * Packet is unknown 560 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 561 * Use the rest of the fields to look at the tunnels, inner protocols, etc 562 * ELSE 563 * Use the enum i40e_rx_l2_ptype to decode the packet type 564 * ENDIF 565 */ 566 567 /* macro to make the table lines short */ 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 569 { PTYPE, \ 570 1, \ 571 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 572 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 573 I40E_RX_PTYPE_##OUTER_FRAG, \ 574 I40E_RX_PTYPE_TUNNEL_##T, \ 575 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 576 I40E_RX_PTYPE_##TEF, \ 577 I40E_RX_PTYPE_INNER_PROT_##I, \ 578 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 579 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 581 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 582 583 /* shorter macros makes the table fit but are terse */ 584 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 585 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 586 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 587 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 590 /* L2 Packet types */ 591 I40E_PTT_UNUSED_ENTRY(0), 592 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 594 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT_UNUSED_ENTRY(4), 596 I40E_PTT_UNUSED_ENTRY(5), 597 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT_UNUSED_ENTRY(8), 600 I40E_PTT_UNUSED_ENTRY(9), 601 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 603 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 614 /* Non Tunneled IPv4 */ 615 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 616 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 617 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(25), 619 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 620 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 621 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 622 623 /* IPv4 --> IPv4 */ 624 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 625 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 626 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(32), 628 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 629 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 630 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 631 632 /* IPv4 --> IPv6 */ 633 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 634 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 635 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 636 I40E_PTT_UNUSED_ENTRY(39), 637 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 638 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 639 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 640 641 /* IPv4 --> GRE/NAT */ 642 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 643 644 /* IPv4 --> GRE/NAT --> IPv4 */ 645 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(47), 649 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> GRE/NAT --> IPv6 */ 654 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(54), 658 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT --> MAC */ 663 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 666 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(62), 670 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 675 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(69), 679 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 684 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 687 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(77), 691 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 696 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(84), 700 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 703 704 /* Non Tunneled IPv6 */ 705 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 706 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 707 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 708 I40E_PTT_UNUSED_ENTRY(91), 709 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 710 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 711 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 712 713 /* IPv6 --> IPv4 */ 714 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 715 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 716 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 717 I40E_PTT_UNUSED_ENTRY(98), 718 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 719 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 720 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 721 722 /* IPv6 --> IPv6 */ 723 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 724 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 725 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(105), 727 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 728 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 729 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 730 731 /* IPv6 --> GRE/NAT */ 732 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 733 734 /* IPv6 --> GRE/NAT -> IPv4 */ 735 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(113), 739 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> GRE/NAT -> IPv6 */ 744 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(120), 748 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT -> MAC */ 753 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 756 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(128), 760 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 765 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(135), 769 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 774 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 777 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(143), 781 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 786 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(150), 790 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 793 794 /* unused entries */ 795 I40E_PTT_UNUSED_ENTRY(154), 796 I40E_PTT_UNUSED_ENTRY(155), 797 I40E_PTT_UNUSED_ENTRY(156), 798 I40E_PTT_UNUSED_ENTRY(157), 799 I40E_PTT_UNUSED_ENTRY(158), 800 I40E_PTT_UNUSED_ENTRY(159), 801 802 I40E_PTT_UNUSED_ENTRY(160), 803 I40E_PTT_UNUSED_ENTRY(161), 804 I40E_PTT_UNUSED_ENTRY(162), 805 I40E_PTT_UNUSED_ENTRY(163), 806 I40E_PTT_UNUSED_ENTRY(164), 807 I40E_PTT_UNUSED_ENTRY(165), 808 I40E_PTT_UNUSED_ENTRY(166), 809 I40E_PTT_UNUSED_ENTRY(167), 810 I40E_PTT_UNUSED_ENTRY(168), 811 I40E_PTT_UNUSED_ENTRY(169), 812 813 I40E_PTT_UNUSED_ENTRY(170), 814 I40E_PTT_UNUSED_ENTRY(171), 815 I40E_PTT_UNUSED_ENTRY(172), 816 I40E_PTT_UNUSED_ENTRY(173), 817 I40E_PTT_UNUSED_ENTRY(174), 818 I40E_PTT_UNUSED_ENTRY(175), 819 I40E_PTT_UNUSED_ENTRY(176), 820 I40E_PTT_UNUSED_ENTRY(177), 821 I40E_PTT_UNUSED_ENTRY(178), 822 I40E_PTT_UNUSED_ENTRY(179), 823 824 I40E_PTT_UNUSED_ENTRY(180), 825 I40E_PTT_UNUSED_ENTRY(181), 826 I40E_PTT_UNUSED_ENTRY(182), 827 I40E_PTT_UNUSED_ENTRY(183), 828 I40E_PTT_UNUSED_ENTRY(184), 829 I40E_PTT_UNUSED_ENTRY(185), 830 I40E_PTT_UNUSED_ENTRY(186), 831 I40E_PTT_UNUSED_ENTRY(187), 832 I40E_PTT_UNUSED_ENTRY(188), 833 I40E_PTT_UNUSED_ENTRY(189), 834 835 I40E_PTT_UNUSED_ENTRY(190), 836 I40E_PTT_UNUSED_ENTRY(191), 837 I40E_PTT_UNUSED_ENTRY(192), 838 I40E_PTT_UNUSED_ENTRY(193), 839 I40E_PTT_UNUSED_ENTRY(194), 840 I40E_PTT_UNUSED_ENTRY(195), 841 I40E_PTT_UNUSED_ENTRY(196), 842 I40E_PTT_UNUSED_ENTRY(197), 843 I40E_PTT_UNUSED_ENTRY(198), 844 I40E_PTT_UNUSED_ENTRY(199), 845 846 I40E_PTT_UNUSED_ENTRY(200), 847 I40E_PTT_UNUSED_ENTRY(201), 848 I40E_PTT_UNUSED_ENTRY(202), 849 I40E_PTT_UNUSED_ENTRY(203), 850 I40E_PTT_UNUSED_ENTRY(204), 851 I40E_PTT_UNUSED_ENTRY(205), 852 I40E_PTT_UNUSED_ENTRY(206), 853 I40E_PTT_UNUSED_ENTRY(207), 854 I40E_PTT_UNUSED_ENTRY(208), 855 I40E_PTT_UNUSED_ENTRY(209), 856 857 I40E_PTT_UNUSED_ENTRY(210), 858 I40E_PTT_UNUSED_ENTRY(211), 859 I40E_PTT_UNUSED_ENTRY(212), 860 I40E_PTT_UNUSED_ENTRY(213), 861 I40E_PTT_UNUSED_ENTRY(214), 862 I40E_PTT_UNUSED_ENTRY(215), 863 I40E_PTT_UNUSED_ENTRY(216), 864 I40E_PTT_UNUSED_ENTRY(217), 865 I40E_PTT_UNUSED_ENTRY(218), 866 I40E_PTT_UNUSED_ENTRY(219), 867 868 I40E_PTT_UNUSED_ENTRY(220), 869 I40E_PTT_UNUSED_ENTRY(221), 870 I40E_PTT_UNUSED_ENTRY(222), 871 I40E_PTT_UNUSED_ENTRY(223), 872 I40E_PTT_UNUSED_ENTRY(224), 873 I40E_PTT_UNUSED_ENTRY(225), 874 I40E_PTT_UNUSED_ENTRY(226), 875 I40E_PTT_UNUSED_ENTRY(227), 876 I40E_PTT_UNUSED_ENTRY(228), 877 I40E_PTT_UNUSED_ENTRY(229), 878 879 I40E_PTT_UNUSED_ENTRY(230), 880 I40E_PTT_UNUSED_ENTRY(231), 881 I40E_PTT_UNUSED_ENTRY(232), 882 I40E_PTT_UNUSED_ENTRY(233), 883 I40E_PTT_UNUSED_ENTRY(234), 884 I40E_PTT_UNUSED_ENTRY(235), 885 I40E_PTT_UNUSED_ENTRY(236), 886 I40E_PTT_UNUSED_ENTRY(237), 887 I40E_PTT_UNUSED_ENTRY(238), 888 I40E_PTT_UNUSED_ENTRY(239), 889 890 I40E_PTT_UNUSED_ENTRY(240), 891 I40E_PTT_UNUSED_ENTRY(241), 892 I40E_PTT_UNUSED_ENTRY(242), 893 I40E_PTT_UNUSED_ENTRY(243), 894 I40E_PTT_UNUSED_ENTRY(244), 895 I40E_PTT_UNUSED_ENTRY(245), 896 I40E_PTT_UNUSED_ENTRY(246), 897 I40E_PTT_UNUSED_ENTRY(247), 898 I40E_PTT_UNUSED_ENTRY(248), 899 I40E_PTT_UNUSED_ENTRY(249), 900 901 I40E_PTT_UNUSED_ENTRY(250), 902 I40E_PTT_UNUSED_ENTRY(251), 903 I40E_PTT_UNUSED_ENTRY(252), 904 I40E_PTT_UNUSED_ENTRY(253), 905 I40E_PTT_UNUSED_ENTRY(254), 906 I40E_PTT_UNUSED_ENTRY(255) 907 }; 908 909 /** 910 * i40e_init_shared_code - Initialize the shared code 911 * @hw: pointer to hardware structure 912 * 913 * This assigns the MAC type and PHY code and inits the NVM. 914 * Does not touch the hardware. This function must be called prior to any 915 * other function in the shared code. The i40e_hw structure should be 916 * memset to 0 prior to calling this function. The following fields in 917 * hw structure should be filled in prior to calling this function: 918 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 919 * subsystem_vendor_id, and revision_id 920 **/ 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 922 { 923 i40e_status status = 0; 924 u32 port, ari, func_rid; 925 926 i40e_set_mac_type(hw); 927 928 switch (hw->mac.type) { 929 case I40E_MAC_XL710: 930 case I40E_MAC_X722: 931 break; 932 default: 933 return I40E_ERR_DEVICE_NOT_SUPPORTED; 934 } 935 936 hw->phy.get_link_info = true; 937 938 /* Determine port number and PF number*/ 939 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 940 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 941 hw->port = (u8)port; 942 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 943 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 944 func_rid = rd32(hw, I40E_PF_FUNC_RID); 945 if (ari) 946 hw->pf_id = (u8)(func_rid & 0xff); 947 else 948 hw->pf_id = (u8)(func_rid & 0x7); 949 950 if (hw->mac.type == I40E_MAC_X722) 951 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 952 953 status = i40e_init_nvm(hw); 954 return status; 955 } 956 957 /** 958 * i40e_aq_mac_address_read - Retrieve the MAC addresses 959 * @hw: pointer to the hw struct 960 * @flags: a return indicator of what addresses were added to the addr store 961 * @addrs: the requestor's mac addr store 962 * @cmd_details: pointer to command details structure or NULL 963 **/ 964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 965 u16 *flags, 966 struct i40e_aqc_mac_address_read_data *addrs, 967 struct i40e_asq_cmd_details *cmd_details) 968 { 969 struct i40e_aq_desc desc; 970 struct i40e_aqc_mac_address_read *cmd_data = 971 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 972 i40e_status status; 973 974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 975 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 976 977 status = i40e_asq_send_command(hw, &desc, addrs, 978 sizeof(*addrs), cmd_details); 979 *flags = le16_to_cpu(cmd_data->command_flags); 980 981 return status; 982 } 983 984 /** 985 * i40e_aq_mac_address_write - Change the MAC addresses 986 * @hw: pointer to the hw struct 987 * @flags: indicates which MAC to be written 988 * @mac_addr: address to write 989 * @cmd_details: pointer to command details structure or NULL 990 **/ 991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 992 u16 flags, u8 *mac_addr, 993 struct i40e_asq_cmd_details *cmd_details) 994 { 995 struct i40e_aq_desc desc; 996 struct i40e_aqc_mac_address_write *cmd_data = 997 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 998 i40e_status status; 999 1000 i40e_fill_default_direct_cmd_desc(&desc, 1001 i40e_aqc_opc_mac_address_write); 1002 cmd_data->command_flags = cpu_to_le16(flags); 1003 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1004 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1005 ((u32)mac_addr[3] << 16) | 1006 ((u32)mac_addr[4] << 8) | 1007 mac_addr[5]); 1008 1009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1010 1011 return status; 1012 } 1013 1014 /** 1015 * i40e_get_mac_addr - get MAC address 1016 * @hw: pointer to the HW structure 1017 * @mac_addr: pointer to MAC address 1018 * 1019 * Reads the adapter's MAC address from register 1020 **/ 1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1022 { 1023 struct i40e_aqc_mac_address_read_data addrs; 1024 i40e_status status; 1025 u16 flags = 0; 1026 1027 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1028 1029 if (flags & I40E_AQC_LAN_ADDR_VALID) 1030 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1031 1032 return status; 1033 } 1034 1035 /** 1036 * i40e_get_port_mac_addr - get Port MAC address 1037 * @hw: pointer to the HW structure 1038 * @mac_addr: pointer to Port MAC address 1039 * 1040 * Reads the adapter's Port MAC address 1041 **/ 1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1043 { 1044 struct i40e_aqc_mac_address_read_data addrs; 1045 i40e_status status; 1046 u16 flags = 0; 1047 1048 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1049 if (status) 1050 return status; 1051 1052 if (flags & I40E_AQC_PORT_ADDR_VALID) 1053 ether_addr_copy(mac_addr, addrs.port_mac); 1054 else 1055 status = I40E_ERR_INVALID_MAC_ADDR; 1056 1057 return status; 1058 } 1059 1060 /** 1061 * i40e_pre_tx_queue_cfg - pre tx queue configure 1062 * @hw: pointer to the HW structure 1063 * @queue: target PF queue index 1064 * @enable: state change request 1065 * 1066 * Handles hw requirement to indicate intention to enable 1067 * or disable target queue. 1068 **/ 1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1070 { 1071 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1072 u32 reg_block = 0; 1073 u32 reg_val; 1074 1075 if (abs_queue_idx >= 128) { 1076 reg_block = abs_queue_idx / 128; 1077 abs_queue_idx %= 128; 1078 } 1079 1080 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1081 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1082 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1083 1084 if (enable) 1085 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1086 else 1087 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1088 1089 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1090 } 1091 1092 /** 1093 * i40e_read_pba_string - Reads part number string from EEPROM 1094 * @hw: pointer to hardware structure 1095 * @pba_num: stores the part number string from the EEPROM 1096 * @pba_num_size: part number string buffer length 1097 * 1098 * Reads the part number string from the EEPROM. 1099 **/ 1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1101 u32 pba_num_size) 1102 { 1103 i40e_status status = 0; 1104 u16 pba_word = 0; 1105 u16 pba_size = 0; 1106 u16 pba_ptr = 0; 1107 u16 i = 0; 1108 1109 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1110 if (status || (pba_word != 0xFAFA)) { 1111 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1112 return status; 1113 } 1114 1115 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1116 if (status) { 1117 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1118 return status; 1119 } 1120 1121 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1122 if (status) { 1123 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1124 return status; 1125 } 1126 1127 /* Subtract one to get PBA word count (PBA Size word is included in 1128 * total size) 1129 */ 1130 pba_size--; 1131 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1132 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1133 return I40E_ERR_PARAM; 1134 } 1135 1136 for (i = 0; i < pba_size; i++) { 1137 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1138 if (status) { 1139 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1140 return status; 1141 } 1142 1143 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1144 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1145 } 1146 pba_num[(pba_size * 2)] = '\0'; 1147 1148 return status; 1149 } 1150 1151 /** 1152 * i40e_get_media_type - Gets media type 1153 * @hw: pointer to the hardware structure 1154 **/ 1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1156 { 1157 enum i40e_media_type media; 1158 1159 switch (hw->phy.link_info.phy_type) { 1160 case I40E_PHY_TYPE_10GBASE_SR: 1161 case I40E_PHY_TYPE_10GBASE_LR: 1162 case I40E_PHY_TYPE_1000BASE_SX: 1163 case I40E_PHY_TYPE_1000BASE_LX: 1164 case I40E_PHY_TYPE_40GBASE_SR4: 1165 case I40E_PHY_TYPE_40GBASE_LR4: 1166 case I40E_PHY_TYPE_25GBASE_LR: 1167 case I40E_PHY_TYPE_25GBASE_SR: 1168 media = I40E_MEDIA_TYPE_FIBER; 1169 break; 1170 case I40E_PHY_TYPE_100BASE_TX: 1171 case I40E_PHY_TYPE_1000BASE_T: 1172 case I40E_PHY_TYPE_10GBASE_T: 1173 media = I40E_MEDIA_TYPE_BASET; 1174 break; 1175 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1176 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1177 case I40E_PHY_TYPE_10GBASE_CR1: 1178 case I40E_PHY_TYPE_40GBASE_CR4: 1179 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1180 case I40E_PHY_TYPE_40GBASE_AOC: 1181 case I40E_PHY_TYPE_10GBASE_AOC: 1182 case I40E_PHY_TYPE_25GBASE_CR: 1183 media = I40E_MEDIA_TYPE_DA; 1184 break; 1185 case I40E_PHY_TYPE_1000BASE_KX: 1186 case I40E_PHY_TYPE_10GBASE_KX4: 1187 case I40E_PHY_TYPE_10GBASE_KR: 1188 case I40E_PHY_TYPE_40GBASE_KR4: 1189 case I40E_PHY_TYPE_20GBASE_KR2: 1190 case I40E_PHY_TYPE_25GBASE_KR: 1191 media = I40E_MEDIA_TYPE_BACKPLANE; 1192 break; 1193 case I40E_PHY_TYPE_SGMII: 1194 case I40E_PHY_TYPE_XAUI: 1195 case I40E_PHY_TYPE_XFI: 1196 case I40E_PHY_TYPE_XLAUI: 1197 case I40E_PHY_TYPE_XLPPI: 1198 default: 1199 media = I40E_MEDIA_TYPE_UNKNOWN; 1200 break; 1201 } 1202 1203 return media; 1204 } 1205 1206 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1207 #define I40E_PF_RESET_WAIT_COUNT 200 1208 /** 1209 * i40e_pf_reset - Reset the PF 1210 * @hw: pointer to the hardware structure 1211 * 1212 * Assuming someone else has triggered a global reset, 1213 * assure the global reset is complete and then reset the PF 1214 **/ 1215 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1216 { 1217 u32 cnt = 0; 1218 u32 cnt1 = 0; 1219 u32 reg = 0; 1220 u32 grst_del; 1221 1222 /* Poll for Global Reset steady state in case of recent GRST. 1223 * The grst delay value is in 100ms units, and we'll wait a 1224 * couple counts longer to be sure we don't just miss the end. 1225 */ 1226 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1227 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1228 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1229 1230 /* It can take upto 15 secs for GRST steady state. 1231 * Bump it to 16 secs max to be safe. 1232 */ 1233 grst_del = grst_del * 20; 1234 1235 for (cnt = 0; cnt < grst_del; cnt++) { 1236 reg = rd32(hw, I40E_GLGEN_RSTAT); 1237 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1238 break; 1239 msleep(100); 1240 } 1241 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1242 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1243 return I40E_ERR_RESET_FAILED; 1244 } 1245 1246 /* Now Wait for the FW to be ready */ 1247 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1248 reg = rd32(hw, I40E_GLNVM_ULD); 1249 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1250 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1251 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1252 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1253 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1254 break; 1255 } 1256 usleep_range(10000, 20000); 1257 } 1258 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1260 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1261 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1262 return I40E_ERR_RESET_FAILED; 1263 } 1264 1265 /* If there was a Global Reset in progress when we got here, 1266 * we don't need to do the PF Reset 1267 */ 1268 if (!cnt) { 1269 if (hw->revision_id == 0) 1270 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1271 else 1272 cnt = I40E_PF_RESET_WAIT_COUNT; 1273 reg = rd32(hw, I40E_PFGEN_CTRL); 1274 wr32(hw, I40E_PFGEN_CTRL, 1275 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1276 for (; cnt; cnt--) { 1277 reg = rd32(hw, I40E_PFGEN_CTRL); 1278 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1279 break; 1280 usleep_range(1000, 2000); 1281 } 1282 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1283 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1284 return I40E_ERR_RESET_FAILED; 1285 } 1286 } 1287 1288 i40e_clear_pxe_mode(hw); 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * i40e_clear_hw - clear out any left over hw state 1295 * @hw: pointer to the hw struct 1296 * 1297 * Clear queues and interrupts, typically called at init time, 1298 * but after the capabilities have been found so we know how many 1299 * queues and msix vectors have been allocated. 1300 **/ 1301 void i40e_clear_hw(struct i40e_hw *hw) 1302 { 1303 u32 num_queues, base_queue; 1304 u32 num_pf_int; 1305 u32 num_vf_int; 1306 u32 num_vfs; 1307 u32 i, j; 1308 u32 val; 1309 u32 eol = 0x7ff; 1310 1311 /* get number of interrupts, queues, and VFs */ 1312 val = rd32(hw, I40E_GLPCI_CNF2); 1313 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1314 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1315 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1316 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1317 1318 val = rd32(hw, I40E_PFLAN_QALLOC); 1319 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1320 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1321 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1322 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1323 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1324 num_queues = (j - base_queue) + 1; 1325 else 1326 num_queues = 0; 1327 1328 val = rd32(hw, I40E_PF_VT_PFALLOC); 1329 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1330 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1331 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1332 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1333 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1334 num_vfs = (j - i) + 1; 1335 else 1336 num_vfs = 0; 1337 1338 /* stop all the interrupts */ 1339 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1340 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1341 for (i = 0; i < num_pf_int - 2; i++) 1342 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1343 1344 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1345 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1346 wr32(hw, I40E_PFINT_LNKLST0, val); 1347 for (i = 0; i < num_pf_int - 2; i++) 1348 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1349 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1350 for (i = 0; i < num_vfs; i++) 1351 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1352 for (i = 0; i < num_vf_int - 2; i++) 1353 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1354 1355 /* warn the HW of the coming Tx disables */ 1356 for (i = 0; i < num_queues; i++) { 1357 u32 abs_queue_idx = base_queue + i; 1358 u32 reg_block = 0; 1359 1360 if (abs_queue_idx >= 128) { 1361 reg_block = abs_queue_idx / 128; 1362 abs_queue_idx %= 128; 1363 } 1364 1365 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1366 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1367 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1368 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1369 1370 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1371 } 1372 udelay(400); 1373 1374 /* stop all the queues */ 1375 for (i = 0; i < num_queues; i++) { 1376 wr32(hw, I40E_QINT_TQCTL(i), 0); 1377 wr32(hw, I40E_QTX_ENA(i), 0); 1378 wr32(hw, I40E_QINT_RQCTL(i), 0); 1379 wr32(hw, I40E_QRX_ENA(i), 0); 1380 } 1381 1382 /* short wait for all queue disables to settle */ 1383 udelay(50); 1384 } 1385 1386 /** 1387 * i40e_clear_pxe_mode - clear pxe operations mode 1388 * @hw: pointer to the hw struct 1389 * 1390 * Make sure all PXE mode settings are cleared, including things 1391 * like descriptor fetch/write-back mode. 1392 **/ 1393 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1394 { 1395 u32 reg; 1396 1397 if (i40e_check_asq_alive(hw)) 1398 i40e_aq_clear_pxe_mode(hw, NULL); 1399 1400 /* Clear single descriptor fetch/write-back mode */ 1401 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1402 1403 if (hw->revision_id == 0) { 1404 /* As a work around clear PXE_MODE instead of setting it */ 1405 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1406 } else { 1407 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1408 } 1409 } 1410 1411 /** 1412 * i40e_led_is_mine - helper to find matching led 1413 * @hw: pointer to the hw struct 1414 * @idx: index into GPIO registers 1415 * 1416 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1417 */ 1418 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1419 { 1420 u32 gpio_val = 0; 1421 u32 port; 1422 1423 if (!hw->func_caps.led[idx]) 1424 return 0; 1425 1426 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1427 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1428 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1429 1430 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1431 * if it is not our port then ignore 1432 */ 1433 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1434 (port != hw->port)) 1435 return 0; 1436 1437 return gpio_val; 1438 } 1439 1440 #define I40E_COMBINED_ACTIVITY 0xA 1441 #define I40E_FILTER_ACTIVITY 0xE 1442 #define I40E_LINK_ACTIVITY 0xC 1443 #define I40E_MAC_ACTIVITY 0xD 1444 #define I40E_LED0 22 1445 1446 /** 1447 * i40e_led_get - return current on/off mode 1448 * @hw: pointer to the hw struct 1449 * 1450 * The value returned is the 'mode' field as defined in the 1451 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1452 * values are variations of possible behaviors relating to 1453 * blink, link, and wire. 1454 **/ 1455 u32 i40e_led_get(struct i40e_hw *hw) 1456 { 1457 u32 current_mode = 0; 1458 u32 mode = 0; 1459 int i; 1460 1461 /* as per the documentation GPIO 22-29 are the LED 1462 * GPIO pins named LED0..LED7 1463 */ 1464 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1465 u32 gpio_val = i40e_led_is_mine(hw, i); 1466 1467 if (!gpio_val) 1468 continue; 1469 1470 /* ignore gpio LED src mode entries related to the activity 1471 * LEDs 1472 */ 1473 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1474 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1475 switch (current_mode) { 1476 case I40E_COMBINED_ACTIVITY: 1477 case I40E_FILTER_ACTIVITY: 1478 case I40E_MAC_ACTIVITY: 1479 continue; 1480 default: 1481 break; 1482 } 1483 1484 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1485 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1486 break; 1487 } 1488 1489 return mode; 1490 } 1491 1492 /** 1493 * i40e_led_set - set new on/off mode 1494 * @hw: pointer to the hw struct 1495 * @mode: 0=off, 0xf=on (else see manual for mode details) 1496 * @blink: true if the LED should blink when on, false if steady 1497 * 1498 * if this function is used to turn on the blink it should 1499 * be used to disable the blink when restoring the original state. 1500 **/ 1501 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1502 { 1503 u32 current_mode = 0; 1504 int i; 1505 1506 if (mode & 0xfffffff0) 1507 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1508 1509 /* as per the documentation GPIO 22-29 are the LED 1510 * GPIO pins named LED0..LED7 1511 */ 1512 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1513 u32 gpio_val = i40e_led_is_mine(hw, i); 1514 1515 if (!gpio_val) 1516 continue; 1517 1518 /* ignore gpio LED src mode entries related to the activity 1519 * LEDs 1520 */ 1521 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1522 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1523 switch (current_mode) { 1524 case I40E_COMBINED_ACTIVITY: 1525 case I40E_FILTER_ACTIVITY: 1526 case I40E_MAC_ACTIVITY: 1527 continue; 1528 default: 1529 break; 1530 } 1531 1532 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1533 /* this & is a bit of paranoia, but serves as a range check */ 1534 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1535 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1536 1537 if (mode == I40E_LINK_ACTIVITY) 1538 blink = false; 1539 1540 if (blink) 1541 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1542 else 1543 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1544 1545 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1546 break; 1547 } 1548 } 1549 1550 /* Admin command wrappers */ 1551 1552 /** 1553 * i40e_aq_get_phy_capabilities 1554 * @hw: pointer to the hw struct 1555 * @abilities: structure for PHY capabilities to be filled 1556 * @qualified_modules: report Qualified Modules 1557 * @report_init: report init capabilities (active are default) 1558 * @cmd_details: pointer to command details structure or NULL 1559 * 1560 * Returns the various PHY abilities supported on the Port. 1561 **/ 1562 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1563 bool qualified_modules, bool report_init, 1564 struct i40e_aq_get_phy_abilities_resp *abilities, 1565 struct i40e_asq_cmd_details *cmd_details) 1566 { 1567 struct i40e_aq_desc desc; 1568 i40e_status status; 1569 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1570 1571 if (!abilities) 1572 return I40E_ERR_PARAM; 1573 1574 i40e_fill_default_direct_cmd_desc(&desc, 1575 i40e_aqc_opc_get_phy_abilities); 1576 1577 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1578 if (abilities_size > I40E_AQ_LARGE_BUF) 1579 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1580 1581 if (qualified_modules) 1582 desc.params.external.param0 |= 1583 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1584 1585 if (report_init) 1586 desc.params.external.param0 |= 1587 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1588 1589 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1590 cmd_details); 1591 1592 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1593 status = I40E_ERR_UNKNOWN_PHY; 1594 1595 if (report_init) { 1596 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1597 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); 1598 } 1599 1600 return status; 1601 } 1602 1603 /** 1604 * i40e_aq_set_phy_config 1605 * @hw: pointer to the hw struct 1606 * @config: structure with PHY configuration to be set 1607 * @cmd_details: pointer to command details structure or NULL 1608 * 1609 * Set the various PHY configuration parameters 1610 * supported on the Port.One or more of the Set PHY config parameters may be 1611 * ignored in an MFP mode as the PF may not have the privilege to set some 1612 * of the PHY Config parameters. This status will be indicated by the 1613 * command response. 1614 **/ 1615 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1616 struct i40e_aq_set_phy_config *config, 1617 struct i40e_asq_cmd_details *cmd_details) 1618 { 1619 struct i40e_aq_desc desc; 1620 struct i40e_aq_set_phy_config *cmd = 1621 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1622 enum i40e_status_code status; 1623 1624 if (!config) 1625 return I40E_ERR_PARAM; 1626 1627 i40e_fill_default_direct_cmd_desc(&desc, 1628 i40e_aqc_opc_set_phy_config); 1629 1630 *cmd = *config; 1631 1632 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1633 1634 return status; 1635 } 1636 1637 /** 1638 * i40e_set_fc 1639 * @hw: pointer to the hw struct 1640 * 1641 * Set the requested flow control mode using set_phy_config. 1642 **/ 1643 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1644 bool atomic_restart) 1645 { 1646 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1647 struct i40e_aq_get_phy_abilities_resp abilities; 1648 struct i40e_aq_set_phy_config config; 1649 enum i40e_status_code status; 1650 u8 pause_mask = 0x0; 1651 1652 *aq_failures = 0x0; 1653 1654 switch (fc_mode) { 1655 case I40E_FC_FULL: 1656 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1657 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1658 break; 1659 case I40E_FC_RX_PAUSE: 1660 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1661 break; 1662 case I40E_FC_TX_PAUSE: 1663 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1664 break; 1665 default: 1666 break; 1667 } 1668 1669 /* Get the current phy config */ 1670 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1671 NULL); 1672 if (status) { 1673 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1674 return status; 1675 } 1676 1677 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1678 /* clear the old pause settings */ 1679 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1680 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1681 /* set the new abilities */ 1682 config.abilities |= pause_mask; 1683 /* If the abilities have changed, then set the new config */ 1684 if (config.abilities != abilities.abilities) { 1685 /* Auto restart link so settings take effect */ 1686 if (atomic_restart) 1687 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1688 /* Copy over all the old settings */ 1689 config.phy_type = abilities.phy_type; 1690 config.phy_type_ext = abilities.phy_type_ext; 1691 config.link_speed = abilities.link_speed; 1692 config.eee_capability = abilities.eee_capability; 1693 config.eeer = abilities.eeer_val; 1694 config.low_power_ctrl = abilities.d3_lpan; 1695 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1696 I40E_AQ_PHY_FEC_CONFIG_MASK; 1697 status = i40e_aq_set_phy_config(hw, &config, NULL); 1698 1699 if (status) 1700 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1701 } 1702 /* Update the link info */ 1703 status = i40e_update_link_info(hw); 1704 if (status) { 1705 /* Wait a little bit (on 40G cards it sometimes takes a really 1706 * long time for link to come back from the atomic reset) 1707 * and try once more 1708 */ 1709 msleep(1000); 1710 status = i40e_update_link_info(hw); 1711 } 1712 if (status) 1713 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1714 1715 return status; 1716 } 1717 1718 /** 1719 * i40e_aq_clear_pxe_mode 1720 * @hw: pointer to the hw struct 1721 * @cmd_details: pointer to command details structure or NULL 1722 * 1723 * Tell the firmware that the driver is taking over from PXE 1724 **/ 1725 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1726 struct i40e_asq_cmd_details *cmd_details) 1727 { 1728 i40e_status status; 1729 struct i40e_aq_desc desc; 1730 struct i40e_aqc_clear_pxe *cmd = 1731 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1732 1733 i40e_fill_default_direct_cmd_desc(&desc, 1734 i40e_aqc_opc_clear_pxe_mode); 1735 1736 cmd->rx_cnt = 0x2; 1737 1738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1739 1740 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1741 1742 return status; 1743 } 1744 1745 /** 1746 * i40e_aq_set_link_restart_an 1747 * @hw: pointer to the hw struct 1748 * @enable_link: if true: enable link, if false: disable link 1749 * @cmd_details: pointer to command details structure or NULL 1750 * 1751 * Sets up the link and restarts the Auto-Negotiation over the link. 1752 **/ 1753 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1754 bool enable_link, 1755 struct i40e_asq_cmd_details *cmd_details) 1756 { 1757 struct i40e_aq_desc desc; 1758 struct i40e_aqc_set_link_restart_an *cmd = 1759 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1760 i40e_status status; 1761 1762 i40e_fill_default_direct_cmd_desc(&desc, 1763 i40e_aqc_opc_set_link_restart_an); 1764 1765 cmd->command = I40E_AQ_PHY_RESTART_AN; 1766 if (enable_link) 1767 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1768 else 1769 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1770 1771 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1772 1773 return status; 1774 } 1775 1776 /** 1777 * i40e_aq_get_link_info 1778 * @hw: pointer to the hw struct 1779 * @enable_lse: enable/disable LinkStatusEvent reporting 1780 * @link: pointer to link status structure - optional 1781 * @cmd_details: pointer to command details structure or NULL 1782 * 1783 * Returns the link status of the adapter. 1784 **/ 1785 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1786 bool enable_lse, struct i40e_link_status *link, 1787 struct i40e_asq_cmd_details *cmd_details) 1788 { 1789 struct i40e_aq_desc desc; 1790 struct i40e_aqc_get_link_status *resp = 1791 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1792 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1793 i40e_status status; 1794 bool tx_pause, rx_pause; 1795 u16 command_flags; 1796 1797 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1798 1799 if (enable_lse) 1800 command_flags = I40E_AQ_LSE_ENABLE; 1801 else 1802 command_flags = I40E_AQ_LSE_DISABLE; 1803 resp->command_flags = cpu_to_le16(command_flags); 1804 1805 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1806 1807 if (status) 1808 goto aq_get_link_info_exit; 1809 1810 /* save off old link status information */ 1811 hw->phy.link_info_old = *hw_link_info; 1812 1813 /* update link status */ 1814 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1815 hw->phy.media_type = i40e_get_media_type(hw); 1816 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1817 hw_link_info->link_info = resp->link_info; 1818 hw_link_info->an_info = resp->an_info; 1819 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1820 I40E_AQ_CONFIG_FEC_RS_ENA); 1821 hw_link_info->ext_info = resp->ext_info; 1822 hw_link_info->loopback = resp->loopback; 1823 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1824 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1825 1826 /* update fc info */ 1827 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1828 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1829 if (tx_pause & rx_pause) 1830 hw->fc.current_mode = I40E_FC_FULL; 1831 else if (tx_pause) 1832 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1833 else if (rx_pause) 1834 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1835 else 1836 hw->fc.current_mode = I40E_FC_NONE; 1837 1838 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1839 hw_link_info->crc_enable = true; 1840 else 1841 hw_link_info->crc_enable = false; 1842 1843 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1844 hw_link_info->lse_enable = true; 1845 else 1846 hw_link_info->lse_enable = false; 1847 1848 if ((hw->mac.type == I40E_MAC_XL710) && 1849 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1850 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1851 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1852 1853 /* save link status information */ 1854 if (link) 1855 *link = *hw_link_info; 1856 1857 /* flag cleared so helper functions don't call AQ again */ 1858 hw->phy.get_link_info = false; 1859 1860 aq_get_link_info_exit: 1861 return status; 1862 } 1863 1864 /** 1865 * i40e_aq_set_phy_int_mask 1866 * @hw: pointer to the hw struct 1867 * @mask: interrupt mask to be set 1868 * @cmd_details: pointer to command details structure or NULL 1869 * 1870 * Set link interrupt mask. 1871 **/ 1872 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1873 u16 mask, 1874 struct i40e_asq_cmd_details *cmd_details) 1875 { 1876 struct i40e_aq_desc desc; 1877 struct i40e_aqc_set_phy_int_mask *cmd = 1878 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1879 i40e_status status; 1880 1881 i40e_fill_default_direct_cmd_desc(&desc, 1882 i40e_aqc_opc_set_phy_int_mask); 1883 1884 cmd->event_mask = cpu_to_le16(mask); 1885 1886 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1887 1888 return status; 1889 } 1890 1891 /** 1892 * i40e_aq_set_phy_debug 1893 * @hw: pointer to the hw struct 1894 * @cmd_flags: debug command flags 1895 * @cmd_details: pointer to command details structure or NULL 1896 * 1897 * Reset the external PHY. 1898 **/ 1899 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1900 struct i40e_asq_cmd_details *cmd_details) 1901 { 1902 struct i40e_aq_desc desc; 1903 struct i40e_aqc_set_phy_debug *cmd = 1904 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1905 i40e_status status; 1906 1907 i40e_fill_default_direct_cmd_desc(&desc, 1908 i40e_aqc_opc_set_phy_debug); 1909 1910 cmd->command_flags = cmd_flags; 1911 1912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1913 1914 return status; 1915 } 1916 1917 /** 1918 * i40e_aq_add_vsi 1919 * @hw: pointer to the hw struct 1920 * @vsi_ctx: pointer to a vsi context struct 1921 * @cmd_details: pointer to command details structure or NULL 1922 * 1923 * Add a VSI context to the hardware. 1924 **/ 1925 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1926 struct i40e_vsi_context *vsi_ctx, 1927 struct i40e_asq_cmd_details *cmd_details) 1928 { 1929 struct i40e_aq_desc desc; 1930 struct i40e_aqc_add_get_update_vsi *cmd = 1931 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1932 struct i40e_aqc_add_get_update_vsi_completion *resp = 1933 (struct i40e_aqc_add_get_update_vsi_completion *) 1934 &desc.params.raw; 1935 i40e_status status; 1936 1937 i40e_fill_default_direct_cmd_desc(&desc, 1938 i40e_aqc_opc_add_vsi); 1939 1940 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1941 cmd->connection_type = vsi_ctx->connection_type; 1942 cmd->vf_id = vsi_ctx->vf_num; 1943 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1944 1945 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1946 1947 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1948 sizeof(vsi_ctx->info), cmd_details); 1949 1950 if (status) 1951 goto aq_add_vsi_exit; 1952 1953 vsi_ctx->seid = le16_to_cpu(resp->seid); 1954 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1955 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1956 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1957 1958 aq_add_vsi_exit: 1959 return status; 1960 } 1961 1962 /** 1963 * i40e_aq_set_default_vsi 1964 * @hw: pointer to the hw struct 1965 * @seid: vsi number 1966 * @cmd_details: pointer to command details structure or NULL 1967 **/ 1968 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 1969 u16 seid, 1970 struct i40e_asq_cmd_details *cmd_details) 1971 { 1972 struct i40e_aq_desc desc; 1973 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1974 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1975 &desc.params.raw; 1976 i40e_status status; 1977 1978 i40e_fill_default_direct_cmd_desc(&desc, 1979 i40e_aqc_opc_set_vsi_promiscuous_modes); 1980 1981 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1982 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1983 cmd->seid = cpu_to_le16(seid); 1984 1985 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1986 1987 return status; 1988 } 1989 1990 /** 1991 * i40e_aq_clear_default_vsi 1992 * @hw: pointer to the hw struct 1993 * @seid: vsi number 1994 * @cmd_details: pointer to command details structure or NULL 1995 **/ 1996 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 1997 u16 seid, 1998 struct i40e_asq_cmd_details *cmd_details) 1999 { 2000 struct i40e_aq_desc desc; 2001 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2002 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2003 &desc.params.raw; 2004 i40e_status status; 2005 2006 i40e_fill_default_direct_cmd_desc(&desc, 2007 i40e_aqc_opc_set_vsi_promiscuous_modes); 2008 2009 cmd->promiscuous_flags = cpu_to_le16(0); 2010 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2011 cmd->seid = cpu_to_le16(seid); 2012 2013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2014 2015 return status; 2016 } 2017 2018 /** 2019 * i40e_aq_set_vsi_unicast_promiscuous 2020 * @hw: pointer to the hw struct 2021 * @seid: vsi number 2022 * @set: set unicast promiscuous enable/disable 2023 * @cmd_details: pointer to command details structure or NULL 2024 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2025 **/ 2026 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2027 u16 seid, bool set, 2028 struct i40e_asq_cmd_details *cmd_details, 2029 bool rx_only_promisc) 2030 { 2031 struct i40e_aq_desc desc; 2032 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2033 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2034 i40e_status status; 2035 u16 flags = 0; 2036 2037 i40e_fill_default_direct_cmd_desc(&desc, 2038 i40e_aqc_opc_set_vsi_promiscuous_modes); 2039 2040 if (set) { 2041 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2042 if (rx_only_promisc && 2043 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2044 (hw->aq.api_maj_ver > 1))) 2045 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2046 } 2047 2048 cmd->promiscuous_flags = cpu_to_le16(flags); 2049 2050 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2051 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2052 (hw->aq.api_maj_ver > 1)) 2053 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2054 2055 cmd->seid = cpu_to_le16(seid); 2056 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2057 2058 return status; 2059 } 2060 2061 /** 2062 * i40e_aq_set_vsi_multicast_promiscuous 2063 * @hw: pointer to the hw struct 2064 * @seid: vsi number 2065 * @set: set multicast promiscuous enable/disable 2066 * @cmd_details: pointer to command details structure or NULL 2067 **/ 2068 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2069 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2070 { 2071 struct i40e_aq_desc desc; 2072 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2073 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2074 i40e_status status; 2075 u16 flags = 0; 2076 2077 i40e_fill_default_direct_cmd_desc(&desc, 2078 i40e_aqc_opc_set_vsi_promiscuous_modes); 2079 2080 if (set) 2081 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2082 2083 cmd->promiscuous_flags = cpu_to_le16(flags); 2084 2085 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2086 2087 cmd->seid = cpu_to_le16(seid); 2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089 2090 return status; 2091 } 2092 2093 /** 2094 * i40e_aq_set_vsi_mc_promisc_on_vlan 2095 * @hw: pointer to the hw struct 2096 * @seid: vsi number 2097 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2098 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2099 * @cmd_details: pointer to command details structure or NULL 2100 **/ 2101 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2102 u16 seid, bool enable, 2103 u16 vid, 2104 struct i40e_asq_cmd_details *cmd_details) 2105 { 2106 struct i40e_aq_desc desc; 2107 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2108 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2109 enum i40e_status_code status; 2110 u16 flags = 0; 2111 2112 i40e_fill_default_direct_cmd_desc(&desc, 2113 i40e_aqc_opc_set_vsi_promiscuous_modes); 2114 2115 if (enable) 2116 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2117 2118 cmd->promiscuous_flags = cpu_to_le16(flags); 2119 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2120 cmd->seid = cpu_to_le16(seid); 2121 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2122 2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2124 2125 return status; 2126 } 2127 2128 /** 2129 * i40e_aq_set_vsi_uc_promisc_on_vlan 2130 * @hw: pointer to the hw struct 2131 * @seid: vsi number 2132 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2133 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2134 * @cmd_details: pointer to command details structure or NULL 2135 **/ 2136 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2137 u16 seid, bool enable, 2138 u16 vid, 2139 struct i40e_asq_cmd_details *cmd_details) 2140 { 2141 struct i40e_aq_desc desc; 2142 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2143 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2144 enum i40e_status_code status; 2145 u16 flags = 0; 2146 2147 i40e_fill_default_direct_cmd_desc(&desc, 2148 i40e_aqc_opc_set_vsi_promiscuous_modes); 2149 2150 if (enable) 2151 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2152 2153 cmd->promiscuous_flags = cpu_to_le16(flags); 2154 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2155 cmd->seid = cpu_to_le16(seid); 2156 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2157 2158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2159 2160 return status; 2161 } 2162 2163 /** 2164 * i40e_aq_set_vsi_bc_promisc_on_vlan 2165 * @hw: pointer to the hw struct 2166 * @seid: vsi number 2167 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2168 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2169 * @cmd_details: pointer to command details structure or NULL 2170 **/ 2171 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2172 u16 seid, bool enable, u16 vid, 2173 struct i40e_asq_cmd_details *cmd_details) 2174 { 2175 struct i40e_aq_desc desc; 2176 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2177 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2178 i40e_status status; 2179 u16 flags = 0; 2180 2181 i40e_fill_default_direct_cmd_desc(&desc, 2182 i40e_aqc_opc_set_vsi_promiscuous_modes); 2183 2184 if (enable) 2185 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2186 2187 cmd->promiscuous_flags = cpu_to_le16(flags); 2188 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2189 cmd->seid = cpu_to_le16(seid); 2190 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2191 2192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2193 2194 return status; 2195 } 2196 2197 /** 2198 * i40e_aq_set_vsi_broadcast 2199 * @hw: pointer to the hw struct 2200 * @seid: vsi number 2201 * @set_filter: true to set filter, false to clear filter 2202 * @cmd_details: pointer to command details structure or NULL 2203 * 2204 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2205 **/ 2206 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2207 u16 seid, bool set_filter, 2208 struct i40e_asq_cmd_details *cmd_details) 2209 { 2210 struct i40e_aq_desc desc; 2211 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2212 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2213 i40e_status status; 2214 2215 i40e_fill_default_direct_cmd_desc(&desc, 2216 i40e_aqc_opc_set_vsi_promiscuous_modes); 2217 2218 if (set_filter) 2219 cmd->promiscuous_flags 2220 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2221 else 2222 cmd->promiscuous_flags 2223 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2224 2225 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2226 cmd->seid = cpu_to_le16(seid); 2227 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2228 2229 return status; 2230 } 2231 2232 /** 2233 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2234 * @hw: pointer to the hw struct 2235 * @seid: vsi number 2236 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2237 * @cmd_details: pointer to command details structure or NULL 2238 **/ 2239 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2240 u16 seid, bool enable, 2241 struct i40e_asq_cmd_details *cmd_details) 2242 { 2243 struct i40e_aq_desc desc; 2244 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2245 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2246 i40e_status status; 2247 u16 flags = 0; 2248 2249 i40e_fill_default_direct_cmd_desc(&desc, 2250 i40e_aqc_opc_set_vsi_promiscuous_modes); 2251 if (enable) 2252 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2253 2254 cmd->promiscuous_flags = cpu_to_le16(flags); 2255 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2256 cmd->seid = cpu_to_le16(seid); 2257 2258 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2259 2260 return status; 2261 } 2262 2263 /** 2264 * i40e_get_vsi_params - get VSI configuration info 2265 * @hw: pointer to the hw struct 2266 * @vsi_ctx: pointer to a vsi context struct 2267 * @cmd_details: pointer to command details structure or NULL 2268 **/ 2269 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2270 struct i40e_vsi_context *vsi_ctx, 2271 struct i40e_asq_cmd_details *cmd_details) 2272 { 2273 struct i40e_aq_desc desc; 2274 struct i40e_aqc_add_get_update_vsi *cmd = 2275 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2276 struct i40e_aqc_add_get_update_vsi_completion *resp = 2277 (struct i40e_aqc_add_get_update_vsi_completion *) 2278 &desc.params.raw; 2279 i40e_status status; 2280 2281 i40e_fill_default_direct_cmd_desc(&desc, 2282 i40e_aqc_opc_get_vsi_parameters); 2283 2284 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2285 2286 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2287 2288 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2289 sizeof(vsi_ctx->info), NULL); 2290 2291 if (status) 2292 goto aq_get_vsi_params_exit; 2293 2294 vsi_ctx->seid = le16_to_cpu(resp->seid); 2295 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2296 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2297 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2298 2299 aq_get_vsi_params_exit: 2300 return status; 2301 } 2302 2303 /** 2304 * i40e_aq_update_vsi_params 2305 * @hw: pointer to the hw struct 2306 * @vsi_ctx: pointer to a vsi context struct 2307 * @cmd_details: pointer to command details structure or NULL 2308 * 2309 * Update a VSI context. 2310 **/ 2311 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2312 struct i40e_vsi_context *vsi_ctx, 2313 struct i40e_asq_cmd_details *cmd_details) 2314 { 2315 struct i40e_aq_desc desc; 2316 struct i40e_aqc_add_get_update_vsi *cmd = 2317 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2318 struct i40e_aqc_add_get_update_vsi_completion *resp = 2319 (struct i40e_aqc_add_get_update_vsi_completion *) 2320 &desc.params.raw; 2321 i40e_status status; 2322 2323 i40e_fill_default_direct_cmd_desc(&desc, 2324 i40e_aqc_opc_update_vsi_parameters); 2325 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2326 2327 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2328 2329 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2330 sizeof(vsi_ctx->info), cmd_details); 2331 2332 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2333 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2334 2335 return status; 2336 } 2337 2338 /** 2339 * i40e_aq_get_switch_config 2340 * @hw: pointer to the hardware structure 2341 * @buf: pointer to the result buffer 2342 * @buf_size: length of input buffer 2343 * @start_seid: seid to start for the report, 0 == beginning 2344 * @cmd_details: pointer to command details structure or NULL 2345 * 2346 * Fill the buf with switch configuration returned from AdminQ command 2347 **/ 2348 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2349 struct i40e_aqc_get_switch_config_resp *buf, 2350 u16 buf_size, u16 *start_seid, 2351 struct i40e_asq_cmd_details *cmd_details) 2352 { 2353 struct i40e_aq_desc desc; 2354 struct i40e_aqc_switch_seid *scfg = 2355 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2356 i40e_status status; 2357 2358 i40e_fill_default_direct_cmd_desc(&desc, 2359 i40e_aqc_opc_get_switch_config); 2360 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2361 if (buf_size > I40E_AQ_LARGE_BUF) 2362 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2363 scfg->seid = cpu_to_le16(*start_seid); 2364 2365 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2366 *start_seid = le16_to_cpu(scfg->seid); 2367 2368 return status; 2369 } 2370 2371 /** 2372 * i40e_aq_set_switch_config 2373 * @hw: pointer to the hardware structure 2374 * @flags: bit flag values to set 2375 * @valid_flags: which bit flags to set 2376 * @cmd_details: pointer to command details structure or NULL 2377 * 2378 * Set switch configuration bits 2379 **/ 2380 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2381 u16 flags, 2382 u16 valid_flags, 2383 struct i40e_asq_cmd_details *cmd_details) 2384 { 2385 struct i40e_aq_desc desc; 2386 struct i40e_aqc_set_switch_config *scfg = 2387 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2388 enum i40e_status_code status; 2389 2390 i40e_fill_default_direct_cmd_desc(&desc, 2391 i40e_aqc_opc_set_switch_config); 2392 scfg->flags = cpu_to_le16(flags); 2393 scfg->valid_flags = cpu_to_le16(valid_flags); 2394 2395 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2396 2397 return status; 2398 } 2399 2400 /** 2401 * i40e_aq_get_firmware_version 2402 * @hw: pointer to the hw struct 2403 * @fw_major_version: firmware major version 2404 * @fw_minor_version: firmware minor version 2405 * @fw_build: firmware build number 2406 * @api_major_version: major queue version 2407 * @api_minor_version: minor queue version 2408 * @cmd_details: pointer to command details structure or NULL 2409 * 2410 * Get the firmware version from the admin queue commands 2411 **/ 2412 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2413 u16 *fw_major_version, u16 *fw_minor_version, 2414 u32 *fw_build, 2415 u16 *api_major_version, u16 *api_minor_version, 2416 struct i40e_asq_cmd_details *cmd_details) 2417 { 2418 struct i40e_aq_desc desc; 2419 struct i40e_aqc_get_version *resp = 2420 (struct i40e_aqc_get_version *)&desc.params.raw; 2421 i40e_status status; 2422 2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2424 2425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2426 2427 if (!status) { 2428 if (fw_major_version) 2429 *fw_major_version = le16_to_cpu(resp->fw_major); 2430 if (fw_minor_version) 2431 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2432 if (fw_build) 2433 *fw_build = le32_to_cpu(resp->fw_build); 2434 if (api_major_version) 2435 *api_major_version = le16_to_cpu(resp->api_major); 2436 if (api_minor_version) 2437 *api_minor_version = le16_to_cpu(resp->api_minor); 2438 } 2439 2440 return status; 2441 } 2442 2443 /** 2444 * i40e_aq_send_driver_version 2445 * @hw: pointer to the hw struct 2446 * @dv: driver's major, minor version 2447 * @cmd_details: pointer to command details structure or NULL 2448 * 2449 * Send the driver version to the firmware 2450 **/ 2451 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2452 struct i40e_driver_version *dv, 2453 struct i40e_asq_cmd_details *cmd_details) 2454 { 2455 struct i40e_aq_desc desc; 2456 struct i40e_aqc_driver_version *cmd = 2457 (struct i40e_aqc_driver_version *)&desc.params.raw; 2458 i40e_status status; 2459 u16 len; 2460 2461 if (dv == NULL) 2462 return I40E_ERR_PARAM; 2463 2464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2465 2466 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2467 cmd->driver_major_ver = dv->major_version; 2468 cmd->driver_minor_ver = dv->minor_version; 2469 cmd->driver_build_ver = dv->build_version; 2470 cmd->driver_subbuild_ver = dv->subbuild_version; 2471 2472 len = 0; 2473 while (len < sizeof(dv->driver_string) && 2474 (dv->driver_string[len] < 0x80) && 2475 dv->driver_string[len]) 2476 len++; 2477 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2478 len, cmd_details); 2479 2480 return status; 2481 } 2482 2483 /** 2484 * i40e_get_link_status - get status of the HW network link 2485 * @hw: pointer to the hw struct 2486 * @link_up: pointer to bool (true/false = linkup/linkdown) 2487 * 2488 * Variable link_up true if link is up, false if link is down. 2489 * The variable link_up is invalid if returned value of status != 0 2490 * 2491 * Side effect: LinkStatusEvent reporting becomes enabled 2492 **/ 2493 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2494 { 2495 i40e_status status = 0; 2496 2497 if (hw->phy.get_link_info) { 2498 status = i40e_update_link_info(hw); 2499 2500 if (status) 2501 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2502 status); 2503 } 2504 2505 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2506 2507 return status; 2508 } 2509 2510 /** 2511 * i40e_updatelink_status - update status of the HW network link 2512 * @hw: pointer to the hw struct 2513 **/ 2514 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2515 { 2516 struct i40e_aq_get_phy_abilities_resp abilities; 2517 i40e_status status = 0; 2518 2519 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2520 if (status) 2521 return status; 2522 2523 /* extra checking needed to ensure link info to user is timely */ 2524 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2525 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2526 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2527 status = i40e_aq_get_phy_capabilities(hw, false, false, 2528 &abilities, NULL); 2529 if (status) 2530 return status; 2531 2532 hw->phy.link_info.req_fec_info = 2533 abilities.fec_cfg_curr_mod_ext_info & 2534 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2535 2536 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2537 sizeof(hw->phy.link_info.module_type)); 2538 } 2539 2540 return status; 2541 } 2542 2543 /** 2544 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2545 * @hw: pointer to the hw struct 2546 * @uplink_seid: the MAC or other gizmo SEID 2547 * @downlink_seid: the VSI SEID 2548 * @enabled_tc: bitmap of TCs to be enabled 2549 * @default_port: true for default port VSI, false for control port 2550 * @veb_seid: pointer to where to put the resulting VEB SEID 2551 * @enable_stats: true to turn on VEB stats 2552 * @cmd_details: pointer to command details structure or NULL 2553 * 2554 * This asks the FW to add a VEB between the uplink and downlink 2555 * elements. If the uplink SEID is 0, this will be a floating VEB. 2556 **/ 2557 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2558 u16 downlink_seid, u8 enabled_tc, 2559 bool default_port, u16 *veb_seid, 2560 bool enable_stats, 2561 struct i40e_asq_cmd_details *cmd_details) 2562 { 2563 struct i40e_aq_desc desc; 2564 struct i40e_aqc_add_veb *cmd = 2565 (struct i40e_aqc_add_veb *)&desc.params.raw; 2566 struct i40e_aqc_add_veb_completion *resp = 2567 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2568 i40e_status status; 2569 u16 veb_flags = 0; 2570 2571 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2572 if (!!uplink_seid != !!downlink_seid) 2573 return I40E_ERR_PARAM; 2574 2575 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2576 2577 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2578 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2579 cmd->enable_tcs = enabled_tc; 2580 if (!uplink_seid) 2581 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2582 if (default_port) 2583 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2584 else 2585 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2586 2587 /* reverse logic here: set the bitflag to disable the stats */ 2588 if (!enable_stats) 2589 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2590 2591 cmd->veb_flags = cpu_to_le16(veb_flags); 2592 2593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2594 2595 if (!status && veb_seid) 2596 *veb_seid = le16_to_cpu(resp->veb_seid); 2597 2598 return status; 2599 } 2600 2601 /** 2602 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2603 * @hw: pointer to the hw struct 2604 * @veb_seid: the SEID of the VEB to query 2605 * @switch_id: the uplink switch id 2606 * @floating: set to true if the VEB is floating 2607 * @statistic_index: index of the stats counter block for this VEB 2608 * @vebs_used: number of VEB's used by function 2609 * @vebs_free: total VEB's not reserved by any function 2610 * @cmd_details: pointer to command details structure or NULL 2611 * 2612 * This retrieves the parameters for a particular VEB, specified by 2613 * uplink_seid, and returns them to the caller. 2614 **/ 2615 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2616 u16 veb_seid, u16 *switch_id, 2617 bool *floating, u16 *statistic_index, 2618 u16 *vebs_used, u16 *vebs_free, 2619 struct i40e_asq_cmd_details *cmd_details) 2620 { 2621 struct i40e_aq_desc desc; 2622 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2623 (struct i40e_aqc_get_veb_parameters_completion *) 2624 &desc.params.raw; 2625 i40e_status status; 2626 2627 if (veb_seid == 0) 2628 return I40E_ERR_PARAM; 2629 2630 i40e_fill_default_direct_cmd_desc(&desc, 2631 i40e_aqc_opc_get_veb_parameters); 2632 cmd_resp->seid = cpu_to_le16(veb_seid); 2633 2634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2635 if (status) 2636 goto get_veb_exit; 2637 2638 if (switch_id) 2639 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2640 if (statistic_index) 2641 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2642 if (vebs_used) 2643 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2644 if (vebs_free) 2645 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2646 if (floating) { 2647 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2648 2649 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2650 *floating = true; 2651 else 2652 *floating = false; 2653 } 2654 2655 get_veb_exit: 2656 return status; 2657 } 2658 2659 /** 2660 * i40e_aq_add_macvlan 2661 * @hw: pointer to the hw struct 2662 * @seid: VSI for the mac address 2663 * @mv_list: list of macvlans to be added 2664 * @count: length of the list 2665 * @cmd_details: pointer to command details structure or NULL 2666 * 2667 * Add MAC/VLAN addresses to the HW filtering 2668 **/ 2669 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2670 struct i40e_aqc_add_macvlan_element_data *mv_list, 2671 u16 count, struct i40e_asq_cmd_details *cmd_details) 2672 { 2673 struct i40e_aq_desc desc; 2674 struct i40e_aqc_macvlan *cmd = 2675 (struct i40e_aqc_macvlan *)&desc.params.raw; 2676 i40e_status status; 2677 u16 buf_size; 2678 int i; 2679 2680 if (count == 0 || !mv_list || !hw) 2681 return I40E_ERR_PARAM; 2682 2683 buf_size = count * sizeof(*mv_list); 2684 2685 /* prep the rest of the request */ 2686 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2687 cmd->num_addresses = cpu_to_le16(count); 2688 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2689 cmd->seid[1] = 0; 2690 cmd->seid[2] = 0; 2691 2692 for (i = 0; i < count; i++) 2693 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2694 mv_list[i].flags |= 2695 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2696 2697 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2698 if (buf_size > I40E_AQ_LARGE_BUF) 2699 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2700 2701 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2702 cmd_details); 2703 2704 return status; 2705 } 2706 2707 /** 2708 * i40e_aq_remove_macvlan 2709 * @hw: pointer to the hw struct 2710 * @seid: VSI for the mac address 2711 * @mv_list: list of macvlans to be removed 2712 * @count: length of the list 2713 * @cmd_details: pointer to command details structure or NULL 2714 * 2715 * Remove MAC/VLAN addresses from the HW filtering 2716 **/ 2717 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2718 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2719 u16 count, struct i40e_asq_cmd_details *cmd_details) 2720 { 2721 struct i40e_aq_desc desc; 2722 struct i40e_aqc_macvlan *cmd = 2723 (struct i40e_aqc_macvlan *)&desc.params.raw; 2724 i40e_status status; 2725 u16 buf_size; 2726 2727 if (count == 0 || !mv_list || !hw) 2728 return I40E_ERR_PARAM; 2729 2730 buf_size = count * sizeof(*mv_list); 2731 2732 /* prep the rest of the request */ 2733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2734 cmd->num_addresses = cpu_to_le16(count); 2735 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2736 cmd->seid[1] = 0; 2737 cmd->seid[2] = 0; 2738 2739 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2740 if (buf_size > I40E_AQ_LARGE_BUF) 2741 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2742 2743 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2744 cmd_details); 2745 2746 return status; 2747 } 2748 2749 /** 2750 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2751 * @hw: pointer to the hw struct 2752 * @opcode: AQ opcode for add or delete mirror rule 2753 * @sw_seid: Switch SEID (to which rule refers) 2754 * @rule_type: Rule Type (ingress/egress/VLAN) 2755 * @id: Destination VSI SEID or Rule ID 2756 * @count: length of the list 2757 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2758 * @cmd_details: pointer to command details structure or NULL 2759 * @rule_id: Rule ID returned from FW 2760 * @rule_used: Number of rules used in internal switch 2761 * @rule_free: Number of rules free in internal switch 2762 * 2763 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2764 * VEBs/VEPA elements only 2765 **/ 2766 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2767 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2768 u16 count, __le16 *mr_list, 2769 struct i40e_asq_cmd_details *cmd_details, 2770 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2771 { 2772 struct i40e_aq_desc desc; 2773 struct i40e_aqc_add_delete_mirror_rule *cmd = 2774 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2775 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2776 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2777 i40e_status status; 2778 u16 buf_size; 2779 2780 buf_size = count * sizeof(*mr_list); 2781 2782 /* prep the rest of the request */ 2783 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2784 cmd->seid = cpu_to_le16(sw_seid); 2785 cmd->rule_type = cpu_to_le16(rule_type & 2786 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2787 cmd->num_entries = cpu_to_le16(count); 2788 /* Dest VSI for add, rule_id for delete */ 2789 cmd->destination = cpu_to_le16(id); 2790 if (mr_list) { 2791 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2792 I40E_AQ_FLAG_RD)); 2793 if (buf_size > I40E_AQ_LARGE_BUF) 2794 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2795 } 2796 2797 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2798 cmd_details); 2799 if (!status || 2800 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2801 if (rule_id) 2802 *rule_id = le16_to_cpu(resp->rule_id); 2803 if (rules_used) 2804 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2805 if (rules_free) 2806 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2807 } 2808 return status; 2809 } 2810 2811 /** 2812 * i40e_aq_add_mirrorrule - add a mirror rule 2813 * @hw: pointer to the hw struct 2814 * @sw_seid: Switch SEID (to which rule refers) 2815 * @rule_type: Rule Type (ingress/egress/VLAN) 2816 * @dest_vsi: SEID of VSI to which packets will be mirrored 2817 * @count: length of the list 2818 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2819 * @cmd_details: pointer to command details structure or NULL 2820 * @rule_id: Rule ID returned from FW 2821 * @rule_used: Number of rules used in internal switch 2822 * @rule_free: Number of rules free in internal switch 2823 * 2824 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2825 **/ 2826 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2827 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2828 struct i40e_asq_cmd_details *cmd_details, 2829 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2830 { 2831 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2832 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2833 if (count == 0 || !mr_list) 2834 return I40E_ERR_PARAM; 2835 } 2836 2837 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2838 rule_type, dest_vsi, count, mr_list, 2839 cmd_details, rule_id, rules_used, rules_free); 2840 } 2841 2842 /** 2843 * i40e_aq_delete_mirrorrule - delete a mirror rule 2844 * @hw: pointer to the hw struct 2845 * @sw_seid: Switch SEID (to which rule refers) 2846 * @rule_type: Rule Type (ingress/egress/VLAN) 2847 * @count: length of the list 2848 * @rule_id: Rule ID that is returned in the receive desc as part of 2849 * add_mirrorrule. 2850 * @mr_list: list of mirrored VLAN IDs to be removed 2851 * @cmd_details: pointer to command details structure or NULL 2852 * @rule_used: Number of rules used in internal switch 2853 * @rule_free: Number of rules free in internal switch 2854 * 2855 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2856 **/ 2857 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2858 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2859 struct i40e_asq_cmd_details *cmd_details, 2860 u16 *rules_used, u16 *rules_free) 2861 { 2862 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2863 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2864 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2865 * mirroring. For other rule_type, count and rule_type should 2866 * not matter. 2867 */ 2868 if (count == 0 || !mr_list) 2869 return I40E_ERR_PARAM; 2870 } 2871 2872 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2873 rule_type, rule_id, count, mr_list, 2874 cmd_details, NULL, rules_used, rules_free); 2875 } 2876 2877 /** 2878 * i40e_aq_send_msg_to_vf 2879 * @hw: pointer to the hardware structure 2880 * @vfid: VF id to send msg 2881 * @v_opcode: opcodes for VF-PF communication 2882 * @v_retval: return error code 2883 * @msg: pointer to the msg buffer 2884 * @msglen: msg length 2885 * @cmd_details: pointer to command details 2886 * 2887 * send msg to vf 2888 **/ 2889 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2890 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2891 struct i40e_asq_cmd_details *cmd_details) 2892 { 2893 struct i40e_aq_desc desc; 2894 struct i40e_aqc_pf_vf_message *cmd = 2895 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2896 i40e_status status; 2897 2898 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2899 cmd->id = cpu_to_le32(vfid); 2900 desc.cookie_high = cpu_to_le32(v_opcode); 2901 desc.cookie_low = cpu_to_le32(v_retval); 2902 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2903 if (msglen) { 2904 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2905 I40E_AQ_FLAG_RD)); 2906 if (msglen > I40E_AQ_LARGE_BUF) 2907 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2908 desc.datalen = cpu_to_le16(msglen); 2909 } 2910 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2911 2912 return status; 2913 } 2914 2915 /** 2916 * i40e_aq_debug_read_register 2917 * @hw: pointer to the hw struct 2918 * @reg_addr: register address 2919 * @reg_val: register value 2920 * @cmd_details: pointer to command details structure or NULL 2921 * 2922 * Read the register using the admin queue commands 2923 **/ 2924 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2925 u32 reg_addr, u64 *reg_val, 2926 struct i40e_asq_cmd_details *cmd_details) 2927 { 2928 struct i40e_aq_desc desc; 2929 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2930 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2931 i40e_status status; 2932 2933 if (reg_val == NULL) 2934 return I40E_ERR_PARAM; 2935 2936 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2937 2938 cmd_resp->address = cpu_to_le32(reg_addr); 2939 2940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2941 2942 if (!status) { 2943 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2944 (u64)le32_to_cpu(cmd_resp->value_low); 2945 } 2946 2947 return status; 2948 } 2949 2950 /** 2951 * i40e_aq_debug_write_register 2952 * @hw: pointer to the hw struct 2953 * @reg_addr: register address 2954 * @reg_val: register value 2955 * @cmd_details: pointer to command details structure or NULL 2956 * 2957 * Write to a register using the admin queue commands 2958 **/ 2959 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2960 u32 reg_addr, u64 reg_val, 2961 struct i40e_asq_cmd_details *cmd_details) 2962 { 2963 struct i40e_aq_desc desc; 2964 struct i40e_aqc_debug_reg_read_write *cmd = 2965 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2966 i40e_status status; 2967 2968 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2969 2970 cmd->address = cpu_to_le32(reg_addr); 2971 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2972 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2973 2974 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2975 2976 return status; 2977 } 2978 2979 /** 2980 * i40e_aq_request_resource 2981 * @hw: pointer to the hw struct 2982 * @resource: resource id 2983 * @access: access type 2984 * @sdp_number: resource number 2985 * @timeout: the maximum time in ms that the driver may hold the resource 2986 * @cmd_details: pointer to command details structure or NULL 2987 * 2988 * requests common resource using the admin queue commands 2989 **/ 2990 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2991 enum i40e_aq_resources_ids resource, 2992 enum i40e_aq_resource_access_type access, 2993 u8 sdp_number, u64 *timeout, 2994 struct i40e_asq_cmd_details *cmd_details) 2995 { 2996 struct i40e_aq_desc desc; 2997 struct i40e_aqc_request_resource *cmd_resp = 2998 (struct i40e_aqc_request_resource *)&desc.params.raw; 2999 i40e_status status; 3000 3001 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3002 3003 cmd_resp->resource_id = cpu_to_le16(resource); 3004 cmd_resp->access_type = cpu_to_le16(access); 3005 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3006 3007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3008 /* The completion specifies the maximum time in ms that the driver 3009 * may hold the resource in the Timeout field. 3010 * If the resource is held by someone else, the command completes with 3011 * busy return value and the timeout field indicates the maximum time 3012 * the current owner of the resource has to free it. 3013 */ 3014 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3015 *timeout = le32_to_cpu(cmd_resp->timeout); 3016 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_aq_release_resource 3022 * @hw: pointer to the hw struct 3023 * @resource: resource id 3024 * @sdp_number: resource number 3025 * @cmd_details: pointer to command details structure or NULL 3026 * 3027 * release common resource using the admin queue commands 3028 **/ 3029 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3030 enum i40e_aq_resources_ids resource, 3031 u8 sdp_number, 3032 struct i40e_asq_cmd_details *cmd_details) 3033 { 3034 struct i40e_aq_desc desc; 3035 struct i40e_aqc_request_resource *cmd = 3036 (struct i40e_aqc_request_resource *)&desc.params.raw; 3037 i40e_status status; 3038 3039 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3040 3041 cmd->resource_id = cpu_to_le16(resource); 3042 cmd->resource_number = cpu_to_le32(sdp_number); 3043 3044 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3045 3046 return status; 3047 } 3048 3049 /** 3050 * i40e_aq_read_nvm 3051 * @hw: pointer to the hw struct 3052 * @module_pointer: module pointer location in words from the NVM beginning 3053 * @offset: byte offset from the module beginning 3054 * @length: length of the section to be read (in bytes from the offset) 3055 * @data: command buffer (size [bytes] = length) 3056 * @last_command: tells if this is the last command in a series 3057 * @cmd_details: pointer to command details structure or NULL 3058 * 3059 * Read the NVM using the admin queue commands 3060 **/ 3061 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3062 u32 offset, u16 length, void *data, 3063 bool last_command, 3064 struct i40e_asq_cmd_details *cmd_details) 3065 { 3066 struct i40e_aq_desc desc; 3067 struct i40e_aqc_nvm_update *cmd = 3068 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3069 i40e_status status; 3070 3071 /* In offset the highest byte must be zeroed. */ 3072 if (offset & 0xFF000000) { 3073 status = I40E_ERR_PARAM; 3074 goto i40e_aq_read_nvm_exit; 3075 } 3076 3077 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3078 3079 /* If this is the last command in a series, set the proper flag. */ 3080 if (last_command) 3081 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3082 cmd->module_pointer = module_pointer; 3083 cmd->offset = cpu_to_le32(offset); 3084 cmd->length = cpu_to_le16(length); 3085 3086 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3087 if (length > I40E_AQ_LARGE_BUF) 3088 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3089 3090 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3091 3092 i40e_aq_read_nvm_exit: 3093 return status; 3094 } 3095 3096 /** 3097 * i40e_aq_erase_nvm 3098 * @hw: pointer to the hw struct 3099 * @module_pointer: module pointer location in words from the NVM beginning 3100 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3101 * @length: length of the section to be erased (expressed in 4 KB) 3102 * @last_command: tells if this is the last command in a series 3103 * @cmd_details: pointer to command details structure or NULL 3104 * 3105 * Erase the NVM sector using the admin queue commands 3106 **/ 3107 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3108 u32 offset, u16 length, bool last_command, 3109 struct i40e_asq_cmd_details *cmd_details) 3110 { 3111 struct i40e_aq_desc desc; 3112 struct i40e_aqc_nvm_update *cmd = 3113 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3114 i40e_status status; 3115 3116 /* In offset the highest byte must be zeroed. */ 3117 if (offset & 0xFF000000) { 3118 status = I40E_ERR_PARAM; 3119 goto i40e_aq_erase_nvm_exit; 3120 } 3121 3122 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3123 3124 /* If this is the last command in a series, set the proper flag. */ 3125 if (last_command) 3126 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3127 cmd->module_pointer = module_pointer; 3128 cmd->offset = cpu_to_le32(offset); 3129 cmd->length = cpu_to_le16(length); 3130 3131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3132 3133 i40e_aq_erase_nvm_exit: 3134 return status; 3135 } 3136 3137 /** 3138 * i40e_parse_discover_capabilities 3139 * @hw: pointer to the hw struct 3140 * @buff: pointer to a buffer containing device/function capability records 3141 * @cap_count: number of capability records in the list 3142 * @list_type_opc: type of capabilities list to parse 3143 * 3144 * Parse the device/function capabilities list. 3145 **/ 3146 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3147 u32 cap_count, 3148 enum i40e_admin_queue_opc list_type_opc) 3149 { 3150 struct i40e_aqc_list_capabilities_element_resp *cap; 3151 u32 valid_functions, num_functions; 3152 u32 number, logical_id, phys_id; 3153 struct i40e_hw_capabilities *p; 3154 u8 major_rev; 3155 u32 i = 0; 3156 u16 id; 3157 3158 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3159 3160 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3161 p = &hw->dev_caps; 3162 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3163 p = &hw->func_caps; 3164 else 3165 return; 3166 3167 for (i = 0; i < cap_count; i++, cap++) { 3168 id = le16_to_cpu(cap->id); 3169 number = le32_to_cpu(cap->number); 3170 logical_id = le32_to_cpu(cap->logical_id); 3171 phys_id = le32_to_cpu(cap->phys_id); 3172 major_rev = cap->major_rev; 3173 3174 switch (id) { 3175 case I40E_AQ_CAP_ID_SWITCH_MODE: 3176 p->switch_mode = number; 3177 break; 3178 case I40E_AQ_CAP_ID_MNG_MODE: 3179 p->management_mode = number; 3180 if (major_rev > 1) { 3181 p->mng_protocols_over_mctp = logical_id; 3182 i40e_debug(hw, I40E_DEBUG_INIT, 3183 "HW Capability: Protocols over MCTP = %d\n", 3184 p->mng_protocols_over_mctp); 3185 } else { 3186 p->mng_protocols_over_mctp = 0; 3187 } 3188 break; 3189 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3190 p->npar_enable = number; 3191 break; 3192 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3193 p->os2bmc = number; 3194 break; 3195 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3196 p->valid_functions = number; 3197 break; 3198 case I40E_AQ_CAP_ID_SRIOV: 3199 if (number == 1) 3200 p->sr_iov_1_1 = true; 3201 break; 3202 case I40E_AQ_CAP_ID_VF: 3203 p->num_vfs = number; 3204 p->vf_base_id = logical_id; 3205 break; 3206 case I40E_AQ_CAP_ID_VMDQ: 3207 if (number == 1) 3208 p->vmdq = true; 3209 break; 3210 case I40E_AQ_CAP_ID_8021QBG: 3211 if (number == 1) 3212 p->evb_802_1_qbg = true; 3213 break; 3214 case I40E_AQ_CAP_ID_8021QBR: 3215 if (number == 1) 3216 p->evb_802_1_qbh = true; 3217 break; 3218 case I40E_AQ_CAP_ID_VSI: 3219 p->num_vsis = number; 3220 break; 3221 case I40E_AQ_CAP_ID_DCB: 3222 if (number == 1) { 3223 p->dcb = true; 3224 p->enabled_tcmap = logical_id; 3225 p->maxtc = phys_id; 3226 } 3227 break; 3228 case I40E_AQ_CAP_ID_FCOE: 3229 if (number == 1) 3230 p->fcoe = true; 3231 break; 3232 case I40E_AQ_CAP_ID_ISCSI: 3233 if (number == 1) 3234 p->iscsi = true; 3235 break; 3236 case I40E_AQ_CAP_ID_RSS: 3237 p->rss = true; 3238 p->rss_table_size = number; 3239 p->rss_table_entry_width = logical_id; 3240 break; 3241 case I40E_AQ_CAP_ID_RXQ: 3242 p->num_rx_qp = number; 3243 p->base_queue = phys_id; 3244 break; 3245 case I40E_AQ_CAP_ID_TXQ: 3246 p->num_tx_qp = number; 3247 p->base_queue = phys_id; 3248 break; 3249 case I40E_AQ_CAP_ID_MSIX: 3250 p->num_msix_vectors = number; 3251 i40e_debug(hw, I40E_DEBUG_INIT, 3252 "HW Capability: MSIX vector count = %d\n", 3253 p->num_msix_vectors); 3254 break; 3255 case I40E_AQ_CAP_ID_VF_MSIX: 3256 p->num_msix_vectors_vf = number; 3257 break; 3258 case I40E_AQ_CAP_ID_FLEX10: 3259 if (major_rev == 1) { 3260 if (number == 1) { 3261 p->flex10_enable = true; 3262 p->flex10_capable = true; 3263 } 3264 } else { 3265 /* Capability revision >= 2 */ 3266 if (number & 1) 3267 p->flex10_enable = true; 3268 if (number & 2) 3269 p->flex10_capable = true; 3270 } 3271 p->flex10_mode = logical_id; 3272 p->flex10_status = phys_id; 3273 break; 3274 case I40E_AQ_CAP_ID_CEM: 3275 if (number == 1) 3276 p->mgmt_cem = true; 3277 break; 3278 case I40E_AQ_CAP_ID_IWARP: 3279 if (number == 1) 3280 p->iwarp = true; 3281 break; 3282 case I40E_AQ_CAP_ID_LED: 3283 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3284 p->led[phys_id] = true; 3285 break; 3286 case I40E_AQ_CAP_ID_SDP: 3287 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3288 p->sdp[phys_id] = true; 3289 break; 3290 case I40E_AQ_CAP_ID_MDIO: 3291 if (number == 1) { 3292 p->mdio_port_num = phys_id; 3293 p->mdio_port_mode = logical_id; 3294 } 3295 break; 3296 case I40E_AQ_CAP_ID_1588: 3297 if (number == 1) 3298 p->ieee_1588 = true; 3299 break; 3300 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3301 p->fd = true; 3302 p->fd_filters_guaranteed = number; 3303 p->fd_filters_best_effort = logical_id; 3304 break; 3305 case I40E_AQ_CAP_ID_WSR_PROT: 3306 p->wr_csr_prot = (u64)number; 3307 p->wr_csr_prot |= (u64)logical_id << 32; 3308 break; 3309 case I40E_AQ_CAP_ID_NVM_MGMT: 3310 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3311 p->sec_rev_disabled = true; 3312 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3313 p->update_disabled = true; 3314 break; 3315 default: 3316 break; 3317 } 3318 } 3319 3320 if (p->fcoe) 3321 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3322 3323 /* Software override ensuring FCoE is disabled if npar or mfp 3324 * mode because it is not supported in these modes. 3325 */ 3326 if (p->npar_enable || p->flex10_enable) 3327 p->fcoe = false; 3328 3329 /* count the enabled ports (aka the "not disabled" ports) */ 3330 hw->num_ports = 0; 3331 for (i = 0; i < 4; i++) { 3332 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3333 u64 port_cfg = 0; 3334 3335 /* use AQ read to get the physical register offset instead 3336 * of the port relative offset 3337 */ 3338 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3339 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3340 hw->num_ports++; 3341 } 3342 3343 valid_functions = p->valid_functions; 3344 num_functions = 0; 3345 while (valid_functions) { 3346 if (valid_functions & 1) 3347 num_functions++; 3348 valid_functions >>= 1; 3349 } 3350 3351 /* partition id is 1-based, and functions are evenly spread 3352 * across the ports as partitions 3353 */ 3354 if (hw->num_ports != 0) { 3355 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3356 hw->num_partitions = num_functions / hw->num_ports; 3357 } 3358 3359 /* additional HW specific goodies that might 3360 * someday be HW version specific 3361 */ 3362 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3363 } 3364 3365 /** 3366 * i40e_aq_discover_capabilities 3367 * @hw: pointer to the hw struct 3368 * @buff: a virtual buffer to hold the capabilities 3369 * @buff_size: Size of the virtual buffer 3370 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3371 * @list_type_opc: capabilities type to discover - pass in the command opcode 3372 * @cmd_details: pointer to command details structure or NULL 3373 * 3374 * Get the device capabilities descriptions from the firmware 3375 **/ 3376 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3377 void *buff, u16 buff_size, u16 *data_size, 3378 enum i40e_admin_queue_opc list_type_opc, 3379 struct i40e_asq_cmd_details *cmd_details) 3380 { 3381 struct i40e_aqc_list_capabilites *cmd; 3382 struct i40e_aq_desc desc; 3383 i40e_status status = 0; 3384 3385 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3386 3387 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3388 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3389 status = I40E_ERR_PARAM; 3390 goto exit; 3391 } 3392 3393 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3394 3395 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3396 if (buff_size > I40E_AQ_LARGE_BUF) 3397 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3398 3399 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3400 *data_size = le16_to_cpu(desc.datalen); 3401 3402 if (status) 3403 goto exit; 3404 3405 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3406 list_type_opc); 3407 3408 exit: 3409 return status; 3410 } 3411 3412 /** 3413 * i40e_aq_update_nvm 3414 * @hw: pointer to the hw struct 3415 * @module_pointer: module pointer location in words from the NVM beginning 3416 * @offset: byte offset from the module beginning 3417 * @length: length of the section to be written (in bytes from the offset) 3418 * @data: command buffer (size [bytes] = length) 3419 * @last_command: tells if this is the last command in a series 3420 * @cmd_details: pointer to command details structure or NULL 3421 * 3422 * Update the NVM using the admin queue commands 3423 **/ 3424 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3425 u32 offset, u16 length, void *data, 3426 bool last_command, 3427 struct i40e_asq_cmd_details *cmd_details) 3428 { 3429 struct i40e_aq_desc desc; 3430 struct i40e_aqc_nvm_update *cmd = 3431 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3432 i40e_status status; 3433 3434 /* In offset the highest byte must be zeroed. */ 3435 if (offset & 0xFF000000) { 3436 status = I40E_ERR_PARAM; 3437 goto i40e_aq_update_nvm_exit; 3438 } 3439 3440 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3441 3442 /* If this is the last command in a series, set the proper flag. */ 3443 if (last_command) 3444 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3445 cmd->module_pointer = module_pointer; 3446 cmd->offset = cpu_to_le32(offset); 3447 cmd->length = cpu_to_le16(length); 3448 3449 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3450 if (length > I40E_AQ_LARGE_BUF) 3451 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3452 3453 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3454 3455 i40e_aq_update_nvm_exit: 3456 return status; 3457 } 3458 3459 /** 3460 * i40e_aq_get_lldp_mib 3461 * @hw: pointer to the hw struct 3462 * @bridge_type: type of bridge requested 3463 * @mib_type: Local, Remote or both Local and Remote MIBs 3464 * @buff: pointer to a user supplied buffer to store the MIB block 3465 * @buff_size: size of the buffer (in bytes) 3466 * @local_len : length of the returned Local LLDP MIB 3467 * @remote_len: length of the returned Remote LLDP MIB 3468 * @cmd_details: pointer to command details structure or NULL 3469 * 3470 * Requests the complete LLDP MIB (entire packet). 3471 **/ 3472 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3473 u8 mib_type, void *buff, u16 buff_size, 3474 u16 *local_len, u16 *remote_len, 3475 struct i40e_asq_cmd_details *cmd_details) 3476 { 3477 struct i40e_aq_desc desc; 3478 struct i40e_aqc_lldp_get_mib *cmd = 3479 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3480 struct i40e_aqc_lldp_get_mib *resp = 3481 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3482 i40e_status status; 3483 3484 if (buff_size == 0 || !buff) 3485 return I40E_ERR_PARAM; 3486 3487 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3488 /* Indirect Command */ 3489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3490 3491 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3492 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3493 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3494 3495 desc.datalen = cpu_to_le16(buff_size); 3496 3497 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3498 if (buff_size > I40E_AQ_LARGE_BUF) 3499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3500 3501 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3502 if (!status) { 3503 if (local_len != NULL) 3504 *local_len = le16_to_cpu(resp->local_len); 3505 if (remote_len != NULL) 3506 *remote_len = le16_to_cpu(resp->remote_len); 3507 } 3508 3509 return status; 3510 } 3511 3512 /** 3513 * i40e_aq_cfg_lldp_mib_change_event 3514 * @hw: pointer to the hw struct 3515 * @enable_update: Enable or Disable event posting 3516 * @cmd_details: pointer to command details structure or NULL 3517 * 3518 * Enable or Disable posting of an event on ARQ when LLDP MIB 3519 * associated with the interface changes 3520 **/ 3521 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3522 bool enable_update, 3523 struct i40e_asq_cmd_details *cmd_details) 3524 { 3525 struct i40e_aq_desc desc; 3526 struct i40e_aqc_lldp_update_mib *cmd = 3527 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3528 i40e_status status; 3529 3530 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3531 3532 if (!enable_update) 3533 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3534 3535 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3536 3537 return status; 3538 } 3539 3540 /** 3541 * i40e_aq_stop_lldp 3542 * @hw: pointer to the hw struct 3543 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3544 * @cmd_details: pointer to command details structure or NULL 3545 * 3546 * Stop or Shutdown the embedded LLDP Agent 3547 **/ 3548 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3549 struct i40e_asq_cmd_details *cmd_details) 3550 { 3551 struct i40e_aq_desc desc; 3552 struct i40e_aqc_lldp_stop *cmd = 3553 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3554 i40e_status status; 3555 3556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3557 3558 if (shutdown_agent) 3559 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3560 3561 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3562 3563 return status; 3564 } 3565 3566 /** 3567 * i40e_aq_start_lldp 3568 * @hw: pointer to the hw struct 3569 * @cmd_details: pointer to command details structure or NULL 3570 * 3571 * Start the embedded LLDP Agent on all ports. 3572 **/ 3573 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3574 struct i40e_asq_cmd_details *cmd_details) 3575 { 3576 struct i40e_aq_desc desc; 3577 struct i40e_aqc_lldp_start *cmd = 3578 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3579 i40e_status status; 3580 3581 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3582 3583 cmd->command = I40E_AQ_LLDP_AGENT_START; 3584 3585 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3586 3587 return status; 3588 } 3589 3590 /** 3591 * i40e_aq_get_cee_dcb_config 3592 * @hw: pointer to the hw struct 3593 * @buff: response buffer that stores CEE operational configuration 3594 * @buff_size: size of the buffer passed 3595 * @cmd_details: pointer to command details structure or NULL 3596 * 3597 * Get CEE DCBX mode operational configuration from firmware 3598 **/ 3599 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3600 void *buff, u16 buff_size, 3601 struct i40e_asq_cmd_details *cmd_details) 3602 { 3603 struct i40e_aq_desc desc; 3604 i40e_status status; 3605 3606 if (buff_size == 0 || !buff) 3607 return I40E_ERR_PARAM; 3608 3609 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3610 3611 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3612 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3613 cmd_details); 3614 3615 return status; 3616 } 3617 3618 /** 3619 * i40e_aq_add_udp_tunnel 3620 * @hw: pointer to the hw struct 3621 * @udp_port: the UDP port to add in Host byte order 3622 * @header_len: length of the tunneling header length in DWords 3623 * @protocol_index: protocol index type 3624 * @filter_index: pointer to filter index 3625 * @cmd_details: pointer to command details structure or NULL 3626 * 3627 * Note: Firmware expects the udp_port value to be in Little Endian format, 3628 * and this function will call cpu_to_le16 to convert from Host byte order to 3629 * Little Endian order. 3630 **/ 3631 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3632 u16 udp_port, u8 protocol_index, 3633 u8 *filter_index, 3634 struct i40e_asq_cmd_details *cmd_details) 3635 { 3636 struct i40e_aq_desc desc; 3637 struct i40e_aqc_add_udp_tunnel *cmd = 3638 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3639 struct i40e_aqc_del_udp_tunnel_completion *resp = 3640 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3641 i40e_status status; 3642 3643 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3644 3645 cmd->udp_port = cpu_to_le16(udp_port); 3646 cmd->protocol_type = protocol_index; 3647 3648 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3649 3650 if (!status && filter_index) 3651 *filter_index = resp->index; 3652 3653 return status; 3654 } 3655 3656 /** 3657 * i40e_aq_del_udp_tunnel 3658 * @hw: pointer to the hw struct 3659 * @index: filter index 3660 * @cmd_details: pointer to command details structure or NULL 3661 **/ 3662 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3663 struct i40e_asq_cmd_details *cmd_details) 3664 { 3665 struct i40e_aq_desc desc; 3666 struct i40e_aqc_remove_udp_tunnel *cmd = 3667 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3668 i40e_status status; 3669 3670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3671 3672 cmd->index = index; 3673 3674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3675 3676 return status; 3677 } 3678 3679 /** 3680 * i40e_aq_delete_element - Delete switch element 3681 * @hw: pointer to the hw struct 3682 * @seid: the SEID to delete from the switch 3683 * @cmd_details: pointer to command details structure or NULL 3684 * 3685 * This deletes a switch element from the switch. 3686 **/ 3687 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3688 struct i40e_asq_cmd_details *cmd_details) 3689 { 3690 struct i40e_aq_desc desc; 3691 struct i40e_aqc_switch_seid *cmd = 3692 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3693 i40e_status status; 3694 3695 if (seid == 0) 3696 return I40E_ERR_PARAM; 3697 3698 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3699 3700 cmd->seid = cpu_to_le16(seid); 3701 3702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3703 3704 return status; 3705 } 3706 3707 /** 3708 * i40e_aq_dcb_updated - DCB Updated Command 3709 * @hw: pointer to the hw struct 3710 * @cmd_details: pointer to command details structure or NULL 3711 * 3712 * EMP will return when the shared RPB settings have been 3713 * recomputed and modified. The retval field in the descriptor 3714 * will be set to 0 when RPB is modified. 3715 **/ 3716 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3717 struct i40e_asq_cmd_details *cmd_details) 3718 { 3719 struct i40e_aq_desc desc; 3720 i40e_status status; 3721 3722 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3723 3724 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3725 3726 return status; 3727 } 3728 3729 /** 3730 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3731 * @hw: pointer to the hw struct 3732 * @seid: seid for the physical port/switching component/vsi 3733 * @buff: Indirect buffer to hold data parameters and response 3734 * @buff_size: Indirect buffer size 3735 * @opcode: Tx scheduler AQ command opcode 3736 * @cmd_details: pointer to command details structure or NULL 3737 * 3738 * Generic command handler for Tx scheduler AQ commands 3739 **/ 3740 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3741 void *buff, u16 buff_size, 3742 enum i40e_admin_queue_opc opcode, 3743 struct i40e_asq_cmd_details *cmd_details) 3744 { 3745 struct i40e_aq_desc desc; 3746 struct i40e_aqc_tx_sched_ind *cmd = 3747 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3748 i40e_status status; 3749 bool cmd_param_flag = false; 3750 3751 switch (opcode) { 3752 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3753 case i40e_aqc_opc_configure_vsi_tc_bw: 3754 case i40e_aqc_opc_enable_switching_comp_ets: 3755 case i40e_aqc_opc_modify_switching_comp_ets: 3756 case i40e_aqc_opc_disable_switching_comp_ets: 3757 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3758 case i40e_aqc_opc_configure_switching_comp_bw_config: 3759 cmd_param_flag = true; 3760 break; 3761 case i40e_aqc_opc_query_vsi_bw_config: 3762 case i40e_aqc_opc_query_vsi_ets_sla_config: 3763 case i40e_aqc_opc_query_switching_comp_ets_config: 3764 case i40e_aqc_opc_query_port_ets_config: 3765 case i40e_aqc_opc_query_switching_comp_bw_config: 3766 cmd_param_flag = false; 3767 break; 3768 default: 3769 return I40E_ERR_PARAM; 3770 } 3771 3772 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3773 3774 /* Indirect command */ 3775 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3776 if (cmd_param_flag) 3777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3778 if (buff_size > I40E_AQ_LARGE_BUF) 3779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3780 3781 desc.datalen = cpu_to_le16(buff_size); 3782 3783 cmd->vsi_seid = cpu_to_le16(seid); 3784 3785 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3786 3787 return status; 3788 } 3789 3790 /** 3791 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3792 * @hw: pointer to the hw struct 3793 * @seid: VSI seid 3794 * @credit: BW limit credits (0 = disabled) 3795 * @max_credit: Max BW limit credits 3796 * @cmd_details: pointer to command details structure or NULL 3797 **/ 3798 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3799 u16 seid, u16 credit, u8 max_credit, 3800 struct i40e_asq_cmd_details *cmd_details) 3801 { 3802 struct i40e_aq_desc desc; 3803 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3804 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3805 i40e_status status; 3806 3807 i40e_fill_default_direct_cmd_desc(&desc, 3808 i40e_aqc_opc_configure_vsi_bw_limit); 3809 3810 cmd->vsi_seid = cpu_to_le16(seid); 3811 cmd->credit = cpu_to_le16(credit); 3812 cmd->max_credit = max_credit; 3813 3814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3815 3816 return status; 3817 } 3818 3819 /** 3820 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3821 * @hw: pointer to the hw struct 3822 * @seid: VSI seid 3823 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3824 * @cmd_details: pointer to command details structure or NULL 3825 **/ 3826 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3827 u16 seid, 3828 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3829 struct i40e_asq_cmd_details *cmd_details) 3830 { 3831 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3832 i40e_aqc_opc_configure_vsi_tc_bw, 3833 cmd_details); 3834 } 3835 3836 /** 3837 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3838 * @hw: pointer to the hw struct 3839 * @seid: seid of the switching component connected to Physical Port 3840 * @ets_data: Buffer holding ETS parameters 3841 * @cmd_details: pointer to command details structure or NULL 3842 **/ 3843 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3844 u16 seid, 3845 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3846 enum i40e_admin_queue_opc opcode, 3847 struct i40e_asq_cmd_details *cmd_details) 3848 { 3849 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3850 sizeof(*ets_data), opcode, cmd_details); 3851 } 3852 3853 /** 3854 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3855 * @hw: pointer to the hw struct 3856 * @seid: seid of the switching component 3857 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3858 * @cmd_details: pointer to command details structure or NULL 3859 **/ 3860 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3861 u16 seid, 3862 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3863 struct i40e_asq_cmd_details *cmd_details) 3864 { 3865 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3866 i40e_aqc_opc_configure_switching_comp_bw_config, 3867 cmd_details); 3868 } 3869 3870 /** 3871 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3872 * @hw: pointer to the hw struct 3873 * @seid: seid of the VSI 3874 * @bw_data: Buffer to hold VSI BW configuration 3875 * @cmd_details: pointer to command details structure or NULL 3876 **/ 3877 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3878 u16 seid, 3879 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3880 struct i40e_asq_cmd_details *cmd_details) 3881 { 3882 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3883 i40e_aqc_opc_query_vsi_bw_config, 3884 cmd_details); 3885 } 3886 3887 /** 3888 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3889 * @hw: pointer to the hw struct 3890 * @seid: seid of the VSI 3891 * @bw_data: Buffer to hold VSI BW configuration per TC 3892 * @cmd_details: pointer to command details structure or NULL 3893 **/ 3894 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3895 u16 seid, 3896 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3897 struct i40e_asq_cmd_details *cmd_details) 3898 { 3899 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3900 i40e_aqc_opc_query_vsi_ets_sla_config, 3901 cmd_details); 3902 } 3903 3904 /** 3905 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3906 * @hw: pointer to the hw struct 3907 * @seid: seid of the switching component 3908 * @bw_data: Buffer to hold switching component's per TC BW config 3909 * @cmd_details: pointer to command details structure or NULL 3910 **/ 3911 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3912 u16 seid, 3913 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3914 struct i40e_asq_cmd_details *cmd_details) 3915 { 3916 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3917 i40e_aqc_opc_query_switching_comp_ets_config, 3918 cmd_details); 3919 } 3920 3921 /** 3922 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3923 * @hw: pointer to the hw struct 3924 * @seid: seid of the VSI or switching component connected to Physical Port 3925 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3926 * @cmd_details: pointer to command details structure or NULL 3927 **/ 3928 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3929 u16 seid, 3930 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3931 struct i40e_asq_cmd_details *cmd_details) 3932 { 3933 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3934 i40e_aqc_opc_query_port_ets_config, 3935 cmd_details); 3936 } 3937 3938 /** 3939 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3940 * @hw: pointer to the hw struct 3941 * @seid: seid of the switching component 3942 * @bw_data: Buffer to hold switching component's BW configuration 3943 * @cmd_details: pointer to command details structure or NULL 3944 **/ 3945 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3946 u16 seid, 3947 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3948 struct i40e_asq_cmd_details *cmd_details) 3949 { 3950 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3951 i40e_aqc_opc_query_switching_comp_bw_config, 3952 cmd_details); 3953 } 3954 3955 /** 3956 * i40e_validate_filter_settings 3957 * @hw: pointer to the hardware structure 3958 * @settings: Filter control settings 3959 * 3960 * Check and validate the filter control settings passed. 3961 * The function checks for the valid filter/context sizes being 3962 * passed for FCoE and PE. 3963 * 3964 * Returns 0 if the values passed are valid and within 3965 * range else returns an error. 3966 **/ 3967 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3968 struct i40e_filter_control_settings *settings) 3969 { 3970 u32 fcoe_cntx_size, fcoe_filt_size; 3971 u32 pe_cntx_size, pe_filt_size; 3972 u32 fcoe_fmax; 3973 u32 val; 3974 3975 /* Validate FCoE settings passed */ 3976 switch (settings->fcoe_filt_num) { 3977 case I40E_HASH_FILTER_SIZE_1K: 3978 case I40E_HASH_FILTER_SIZE_2K: 3979 case I40E_HASH_FILTER_SIZE_4K: 3980 case I40E_HASH_FILTER_SIZE_8K: 3981 case I40E_HASH_FILTER_SIZE_16K: 3982 case I40E_HASH_FILTER_SIZE_32K: 3983 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3984 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3985 break; 3986 default: 3987 return I40E_ERR_PARAM; 3988 } 3989 3990 switch (settings->fcoe_cntx_num) { 3991 case I40E_DMA_CNTX_SIZE_512: 3992 case I40E_DMA_CNTX_SIZE_1K: 3993 case I40E_DMA_CNTX_SIZE_2K: 3994 case I40E_DMA_CNTX_SIZE_4K: 3995 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3996 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3997 break; 3998 default: 3999 return I40E_ERR_PARAM; 4000 } 4001 4002 /* Validate PE settings passed */ 4003 switch (settings->pe_filt_num) { 4004 case I40E_HASH_FILTER_SIZE_1K: 4005 case I40E_HASH_FILTER_SIZE_2K: 4006 case I40E_HASH_FILTER_SIZE_4K: 4007 case I40E_HASH_FILTER_SIZE_8K: 4008 case I40E_HASH_FILTER_SIZE_16K: 4009 case I40E_HASH_FILTER_SIZE_32K: 4010 case I40E_HASH_FILTER_SIZE_64K: 4011 case I40E_HASH_FILTER_SIZE_128K: 4012 case I40E_HASH_FILTER_SIZE_256K: 4013 case I40E_HASH_FILTER_SIZE_512K: 4014 case I40E_HASH_FILTER_SIZE_1M: 4015 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4016 pe_filt_size <<= (u32)settings->pe_filt_num; 4017 break; 4018 default: 4019 return I40E_ERR_PARAM; 4020 } 4021 4022 switch (settings->pe_cntx_num) { 4023 case I40E_DMA_CNTX_SIZE_512: 4024 case I40E_DMA_CNTX_SIZE_1K: 4025 case I40E_DMA_CNTX_SIZE_2K: 4026 case I40E_DMA_CNTX_SIZE_4K: 4027 case I40E_DMA_CNTX_SIZE_8K: 4028 case I40E_DMA_CNTX_SIZE_16K: 4029 case I40E_DMA_CNTX_SIZE_32K: 4030 case I40E_DMA_CNTX_SIZE_64K: 4031 case I40E_DMA_CNTX_SIZE_128K: 4032 case I40E_DMA_CNTX_SIZE_256K: 4033 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4034 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4035 break; 4036 default: 4037 return I40E_ERR_PARAM; 4038 } 4039 4040 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4041 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4042 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4043 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4044 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4045 return I40E_ERR_INVALID_SIZE; 4046 4047 return 0; 4048 } 4049 4050 /** 4051 * i40e_set_filter_control 4052 * @hw: pointer to the hardware structure 4053 * @settings: Filter control settings 4054 * 4055 * Set the Queue Filters for PE/FCoE and enable filters required 4056 * for a single PF. It is expected that these settings are programmed 4057 * at the driver initialization time. 4058 **/ 4059 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4060 struct i40e_filter_control_settings *settings) 4061 { 4062 i40e_status ret = 0; 4063 u32 hash_lut_size = 0; 4064 u32 val; 4065 4066 if (!settings) 4067 return I40E_ERR_PARAM; 4068 4069 /* Validate the input settings */ 4070 ret = i40e_validate_filter_settings(hw, settings); 4071 if (ret) 4072 return ret; 4073 4074 /* Read the PF Queue Filter control register */ 4075 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4076 4077 /* Program required PE hash buckets for the PF */ 4078 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4079 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4080 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4081 /* Program required PE contexts for the PF */ 4082 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4083 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4084 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4085 4086 /* Program required FCoE hash buckets for the PF */ 4087 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4088 val |= ((u32)settings->fcoe_filt_num << 4089 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4090 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4091 /* Program required FCoE DDP contexts for the PF */ 4092 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4093 val |= ((u32)settings->fcoe_cntx_num << 4094 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4095 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4096 4097 /* Program Hash LUT size for the PF */ 4098 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4099 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4100 hash_lut_size = 1; 4101 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4102 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4103 4104 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4105 if (settings->enable_fdir) 4106 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4107 if (settings->enable_ethtype) 4108 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4109 if (settings->enable_macvlan) 4110 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4111 4112 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4113 4114 return 0; 4115 } 4116 4117 /** 4118 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4119 * @hw: pointer to the hw struct 4120 * @mac_addr: MAC address to use in the filter 4121 * @ethtype: Ethertype to use in the filter 4122 * @flags: Flags that needs to be applied to the filter 4123 * @vsi_seid: seid of the control VSI 4124 * @queue: VSI queue number to send the packet to 4125 * @is_add: Add control packet filter if True else remove 4126 * @stats: Structure to hold information on control filter counts 4127 * @cmd_details: pointer to command details structure or NULL 4128 * 4129 * This command will Add or Remove control packet filter for a control VSI. 4130 * In return it will update the total number of perfect filter count in 4131 * the stats member. 4132 **/ 4133 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4134 u8 *mac_addr, u16 ethtype, u16 flags, 4135 u16 vsi_seid, u16 queue, bool is_add, 4136 struct i40e_control_filter_stats *stats, 4137 struct i40e_asq_cmd_details *cmd_details) 4138 { 4139 struct i40e_aq_desc desc; 4140 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4141 (struct i40e_aqc_add_remove_control_packet_filter *) 4142 &desc.params.raw; 4143 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4144 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4145 &desc.params.raw; 4146 i40e_status status; 4147 4148 if (vsi_seid == 0) 4149 return I40E_ERR_PARAM; 4150 4151 if (is_add) { 4152 i40e_fill_default_direct_cmd_desc(&desc, 4153 i40e_aqc_opc_add_control_packet_filter); 4154 cmd->queue = cpu_to_le16(queue); 4155 } else { 4156 i40e_fill_default_direct_cmd_desc(&desc, 4157 i40e_aqc_opc_remove_control_packet_filter); 4158 } 4159 4160 if (mac_addr) 4161 ether_addr_copy(cmd->mac, mac_addr); 4162 4163 cmd->etype = cpu_to_le16(ethtype); 4164 cmd->flags = cpu_to_le16(flags); 4165 cmd->seid = cpu_to_le16(vsi_seid); 4166 4167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4168 4169 if (!status && stats) { 4170 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4171 stats->etype_used = le16_to_cpu(resp->etype_used); 4172 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4173 stats->etype_free = le16_to_cpu(resp->etype_free); 4174 } 4175 4176 return status; 4177 } 4178 4179 /** 4180 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4181 * @hw: pointer to the hw struct 4182 * @seid: VSI seid to add ethertype filter from 4183 **/ 4184 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4185 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4186 u16 seid) 4187 { 4188 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4189 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4190 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4191 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4192 i40e_status status; 4193 4194 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4195 seid, 0, true, NULL, 4196 NULL); 4197 if (status) 4198 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4199 } 4200 4201 /** 4202 * i40e_aq_alternate_read 4203 * @hw: pointer to the hardware structure 4204 * @reg_addr0: address of first dword to be read 4205 * @reg_val0: pointer for data read from 'reg_addr0' 4206 * @reg_addr1: address of second dword to be read 4207 * @reg_val1: pointer for data read from 'reg_addr1' 4208 * 4209 * Read one or two dwords from alternate structure. Fields are indicated 4210 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4211 * is not passed then only register at 'reg_addr0' is read. 4212 * 4213 **/ 4214 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4215 u32 reg_addr0, u32 *reg_val0, 4216 u32 reg_addr1, u32 *reg_val1) 4217 { 4218 struct i40e_aq_desc desc; 4219 struct i40e_aqc_alternate_write *cmd_resp = 4220 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4221 i40e_status status; 4222 4223 if (!reg_val0) 4224 return I40E_ERR_PARAM; 4225 4226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4227 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4228 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4229 4230 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4231 4232 if (!status) { 4233 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4234 4235 if (reg_val1) 4236 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4237 } 4238 4239 return status; 4240 } 4241 4242 /** 4243 * i40e_aq_resume_port_tx 4244 * @hw: pointer to the hardware structure 4245 * @cmd_details: pointer to command details structure or NULL 4246 * 4247 * Resume port's Tx traffic 4248 **/ 4249 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4250 struct i40e_asq_cmd_details *cmd_details) 4251 { 4252 struct i40e_aq_desc desc; 4253 i40e_status status; 4254 4255 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4256 4257 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4258 4259 return status; 4260 } 4261 4262 /** 4263 * i40e_set_pci_config_data - store PCI bus info 4264 * @hw: pointer to hardware structure 4265 * @link_status: the link status word from PCI config space 4266 * 4267 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4268 **/ 4269 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4270 { 4271 hw->bus.type = i40e_bus_type_pci_express; 4272 4273 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4274 case PCI_EXP_LNKSTA_NLW_X1: 4275 hw->bus.width = i40e_bus_width_pcie_x1; 4276 break; 4277 case PCI_EXP_LNKSTA_NLW_X2: 4278 hw->bus.width = i40e_bus_width_pcie_x2; 4279 break; 4280 case PCI_EXP_LNKSTA_NLW_X4: 4281 hw->bus.width = i40e_bus_width_pcie_x4; 4282 break; 4283 case PCI_EXP_LNKSTA_NLW_X8: 4284 hw->bus.width = i40e_bus_width_pcie_x8; 4285 break; 4286 default: 4287 hw->bus.width = i40e_bus_width_unknown; 4288 break; 4289 } 4290 4291 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4292 case PCI_EXP_LNKSTA_CLS_2_5GB: 4293 hw->bus.speed = i40e_bus_speed_2500; 4294 break; 4295 case PCI_EXP_LNKSTA_CLS_5_0GB: 4296 hw->bus.speed = i40e_bus_speed_5000; 4297 break; 4298 case PCI_EXP_LNKSTA_CLS_8_0GB: 4299 hw->bus.speed = i40e_bus_speed_8000; 4300 break; 4301 default: 4302 hw->bus.speed = i40e_bus_speed_unknown; 4303 break; 4304 } 4305 } 4306 4307 /** 4308 * i40e_aq_debug_dump 4309 * @hw: pointer to the hardware structure 4310 * @cluster_id: specific cluster to dump 4311 * @table_id: table id within cluster 4312 * @start_index: index of line in the block to read 4313 * @buff_size: dump buffer size 4314 * @buff: dump buffer 4315 * @ret_buff_size: actual buffer size returned 4316 * @ret_next_table: next block to read 4317 * @ret_next_index: next index to read 4318 * 4319 * Dump internal FW/HW data for debug purposes. 4320 * 4321 **/ 4322 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4323 u8 table_id, u32 start_index, u16 buff_size, 4324 void *buff, u16 *ret_buff_size, 4325 u8 *ret_next_table, u32 *ret_next_index, 4326 struct i40e_asq_cmd_details *cmd_details) 4327 { 4328 struct i40e_aq_desc desc; 4329 struct i40e_aqc_debug_dump_internals *cmd = 4330 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4331 struct i40e_aqc_debug_dump_internals *resp = 4332 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4333 i40e_status status; 4334 4335 if (buff_size == 0 || !buff) 4336 return I40E_ERR_PARAM; 4337 4338 i40e_fill_default_direct_cmd_desc(&desc, 4339 i40e_aqc_opc_debug_dump_internals); 4340 /* Indirect Command */ 4341 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4342 if (buff_size > I40E_AQ_LARGE_BUF) 4343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4344 4345 cmd->cluster_id = cluster_id; 4346 cmd->table_id = table_id; 4347 cmd->idx = cpu_to_le32(start_index); 4348 4349 desc.datalen = cpu_to_le16(buff_size); 4350 4351 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4352 if (!status) { 4353 if (ret_buff_size) 4354 *ret_buff_size = le16_to_cpu(desc.datalen); 4355 if (ret_next_table) 4356 *ret_next_table = resp->table_id; 4357 if (ret_next_index) 4358 *ret_next_index = le32_to_cpu(resp->idx); 4359 } 4360 4361 return status; 4362 } 4363 4364 /** 4365 * i40e_read_bw_from_alt_ram 4366 * @hw: pointer to the hardware structure 4367 * @max_bw: pointer for max_bw read 4368 * @min_bw: pointer for min_bw read 4369 * @min_valid: pointer for bool that is true if min_bw is a valid value 4370 * @max_valid: pointer for bool that is true if max_bw is a valid value 4371 * 4372 * Read bw from the alternate ram for the given pf 4373 **/ 4374 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4375 u32 *max_bw, u32 *min_bw, 4376 bool *min_valid, bool *max_valid) 4377 { 4378 i40e_status status; 4379 u32 max_bw_addr, min_bw_addr; 4380 4381 /* Calculate the address of the min/max bw registers */ 4382 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4383 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4384 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4385 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4386 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4387 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4388 4389 /* Read the bandwidths from alt ram */ 4390 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4391 min_bw_addr, min_bw); 4392 4393 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4394 *min_valid = true; 4395 else 4396 *min_valid = false; 4397 4398 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4399 *max_valid = true; 4400 else 4401 *max_valid = false; 4402 4403 return status; 4404 } 4405 4406 /** 4407 * i40e_aq_configure_partition_bw 4408 * @hw: pointer to the hardware structure 4409 * @bw_data: Buffer holding valid pfs and bw limits 4410 * @cmd_details: pointer to command details 4411 * 4412 * Configure partitions guaranteed/max bw 4413 **/ 4414 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4415 struct i40e_aqc_configure_partition_bw_data *bw_data, 4416 struct i40e_asq_cmd_details *cmd_details) 4417 { 4418 i40e_status status; 4419 struct i40e_aq_desc desc; 4420 u16 bwd_size = sizeof(*bw_data); 4421 4422 i40e_fill_default_direct_cmd_desc(&desc, 4423 i40e_aqc_opc_configure_partition_bw); 4424 4425 /* Indirect command */ 4426 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4428 4429 if (bwd_size > I40E_AQ_LARGE_BUF) 4430 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4431 4432 desc.datalen = cpu_to_le16(bwd_size); 4433 4434 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4435 cmd_details); 4436 4437 return status; 4438 } 4439 4440 /** 4441 * i40e_read_phy_register_clause22 4442 * @hw: pointer to the HW structure 4443 * @reg: register address in the page 4444 * @phy_adr: PHY address on MDIO interface 4445 * @value: PHY register value 4446 * 4447 * Reads specified PHY register value 4448 **/ 4449 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4450 u16 reg, u8 phy_addr, u16 *value) 4451 { 4452 i40e_status status = I40E_ERR_TIMEOUT; 4453 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4454 u32 command = 0; 4455 u16 retry = 1000; 4456 4457 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4458 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4459 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4460 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4461 (I40E_GLGEN_MSCA_MDICMD_MASK); 4462 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4463 do { 4464 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4465 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4466 status = 0; 4467 break; 4468 } 4469 udelay(10); 4470 retry--; 4471 } while (retry); 4472 4473 if (status) { 4474 i40e_debug(hw, I40E_DEBUG_PHY, 4475 "PHY: Can't write command to external PHY.\n"); 4476 } else { 4477 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4478 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4479 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4480 } 4481 4482 return status; 4483 } 4484 4485 /** 4486 * i40e_write_phy_register_clause22 4487 * @hw: pointer to the HW structure 4488 * @reg: register address in the page 4489 * @phy_adr: PHY address on MDIO interface 4490 * @value: PHY register value 4491 * 4492 * Writes specified PHY register value 4493 **/ 4494 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4495 u16 reg, u8 phy_addr, u16 value) 4496 { 4497 i40e_status status = I40E_ERR_TIMEOUT; 4498 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4499 u32 command = 0; 4500 u16 retry = 1000; 4501 4502 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4503 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4504 4505 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4506 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4507 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4508 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4509 (I40E_GLGEN_MSCA_MDICMD_MASK); 4510 4511 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4512 do { 4513 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4514 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4515 status = 0; 4516 break; 4517 } 4518 udelay(10); 4519 retry--; 4520 } while (retry); 4521 4522 return status; 4523 } 4524 4525 /** 4526 * i40e_read_phy_register_clause45 4527 * @hw: pointer to the HW structure 4528 * @page: registers page number 4529 * @reg: register address in the page 4530 * @phy_adr: PHY address on MDIO interface 4531 * @value: PHY register value 4532 * 4533 * Reads specified PHY register value 4534 **/ 4535 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4536 u8 page, u16 reg, u8 phy_addr, u16 *value) 4537 { 4538 i40e_status status = I40E_ERR_TIMEOUT; 4539 u32 command = 0; 4540 u16 retry = 1000; 4541 u8 port_num = hw->func_caps.mdio_port_num; 4542 4543 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4544 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4545 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4546 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4547 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4548 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4549 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4550 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4551 do { 4552 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4553 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4554 status = 0; 4555 break; 4556 } 4557 usleep_range(10, 20); 4558 retry--; 4559 } while (retry); 4560 4561 if (status) { 4562 i40e_debug(hw, I40E_DEBUG_PHY, 4563 "PHY: Can't write command to external PHY.\n"); 4564 goto phy_read_end; 4565 } 4566 4567 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4568 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4569 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4570 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4571 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4572 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4573 status = I40E_ERR_TIMEOUT; 4574 retry = 1000; 4575 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4576 do { 4577 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4578 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4579 status = 0; 4580 break; 4581 } 4582 usleep_range(10, 20); 4583 retry--; 4584 } while (retry); 4585 4586 if (!status) { 4587 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4588 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4589 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4590 } else { 4591 i40e_debug(hw, I40E_DEBUG_PHY, 4592 "PHY: Can't read register value from external PHY.\n"); 4593 } 4594 4595 phy_read_end: 4596 return status; 4597 } 4598 4599 /** 4600 * i40e_write_phy_register_clause45 4601 * @hw: pointer to the HW structure 4602 * @page: registers page number 4603 * @reg: register address in the page 4604 * @phy_adr: PHY address on MDIO interface 4605 * @value: PHY register value 4606 * 4607 * Writes value to specified PHY register 4608 **/ 4609 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4610 u8 page, u16 reg, u8 phy_addr, u16 value) 4611 { 4612 i40e_status status = I40E_ERR_TIMEOUT; 4613 u32 command = 0; 4614 u16 retry = 1000; 4615 u8 port_num = hw->func_caps.mdio_port_num; 4616 4617 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4618 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4619 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4620 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4621 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4622 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4623 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4624 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4625 do { 4626 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4627 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4628 status = 0; 4629 break; 4630 } 4631 usleep_range(10, 20); 4632 retry--; 4633 } while (retry); 4634 if (status) { 4635 i40e_debug(hw, I40E_DEBUG_PHY, 4636 "PHY: Can't write command to external PHY.\n"); 4637 goto phy_write_end; 4638 } 4639 4640 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4641 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4642 4643 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4644 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4645 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4646 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4647 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4648 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4649 status = I40E_ERR_TIMEOUT; 4650 retry = 1000; 4651 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4652 do { 4653 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4654 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4655 status = 0; 4656 break; 4657 } 4658 usleep_range(10, 20); 4659 retry--; 4660 } while (retry); 4661 4662 phy_write_end: 4663 return status; 4664 } 4665 4666 /** 4667 * i40e_write_phy_register 4668 * @hw: pointer to the HW structure 4669 * @page: registers page number 4670 * @reg: register address in the page 4671 * @phy_adr: PHY address on MDIO interface 4672 * @value: PHY register value 4673 * 4674 * Writes value to specified PHY register 4675 **/ 4676 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4677 u8 page, u16 reg, u8 phy_addr, u16 value) 4678 { 4679 i40e_status status; 4680 4681 switch (hw->device_id) { 4682 case I40E_DEV_ID_1G_BASE_T_X722: 4683 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4684 value); 4685 break; 4686 case I40E_DEV_ID_10G_BASE_T: 4687 case I40E_DEV_ID_10G_BASE_T4: 4688 case I40E_DEV_ID_10G_BASE_T_X722: 4689 case I40E_DEV_ID_25G_B: 4690 case I40E_DEV_ID_25G_SFP28: 4691 status = i40e_write_phy_register_clause45(hw, page, reg, 4692 phy_addr, value); 4693 break; 4694 default: 4695 status = I40E_ERR_UNKNOWN_PHY; 4696 break; 4697 } 4698 4699 return status; 4700 } 4701 4702 /** 4703 * i40e_read_phy_register 4704 * @hw: pointer to the HW structure 4705 * @page: registers page number 4706 * @reg: register address in the page 4707 * @phy_adr: PHY address on MDIO interface 4708 * @value: PHY register value 4709 * 4710 * Reads specified PHY register value 4711 **/ 4712 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4713 u8 page, u16 reg, u8 phy_addr, u16 *value) 4714 { 4715 i40e_status status; 4716 4717 switch (hw->device_id) { 4718 case I40E_DEV_ID_1G_BASE_T_X722: 4719 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4720 value); 4721 break; 4722 case I40E_DEV_ID_10G_BASE_T: 4723 case I40E_DEV_ID_10G_BASE_T4: 4724 case I40E_DEV_ID_10G_BASE_T_X722: 4725 case I40E_DEV_ID_25G_B: 4726 case I40E_DEV_ID_25G_SFP28: 4727 status = i40e_read_phy_register_clause45(hw, page, reg, 4728 phy_addr, value); 4729 break; 4730 default: 4731 status = I40E_ERR_UNKNOWN_PHY; 4732 break; 4733 } 4734 4735 return status; 4736 } 4737 4738 /** 4739 * i40e_get_phy_address 4740 * @hw: pointer to the HW structure 4741 * @dev_num: PHY port num that address we want 4742 * @phy_addr: Returned PHY address 4743 * 4744 * Gets PHY address for current port 4745 **/ 4746 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4747 { 4748 u8 port_num = hw->func_caps.mdio_port_num; 4749 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4750 4751 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4752 } 4753 4754 /** 4755 * i40e_blink_phy_led 4756 * @hw: pointer to the HW structure 4757 * @time: time how long led will blinks in secs 4758 * @interval: gap between LED on and off in msecs 4759 * 4760 * Blinks PHY link LED 4761 **/ 4762 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4763 u32 time, u32 interval) 4764 { 4765 i40e_status status = 0; 4766 u32 i; 4767 u16 led_ctl; 4768 u16 gpio_led_port; 4769 u16 led_reg; 4770 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4771 u8 phy_addr = 0; 4772 u8 port_num; 4773 4774 i = rd32(hw, I40E_PFGEN_PORTNUM); 4775 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4776 phy_addr = i40e_get_phy_address(hw, port_num); 4777 4778 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4779 led_addr++) { 4780 status = i40e_read_phy_register_clause45(hw, 4781 I40E_PHY_COM_REG_PAGE, 4782 led_addr, phy_addr, 4783 &led_reg); 4784 if (status) 4785 goto phy_blinking_end; 4786 led_ctl = led_reg; 4787 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4788 led_reg = 0; 4789 status = i40e_write_phy_register_clause45(hw, 4790 I40E_PHY_COM_REG_PAGE, 4791 led_addr, phy_addr, 4792 led_reg); 4793 if (status) 4794 goto phy_blinking_end; 4795 break; 4796 } 4797 } 4798 4799 if (time > 0 && interval > 0) { 4800 for (i = 0; i < time * 1000; i += interval) { 4801 status = i40e_read_phy_register_clause45(hw, 4802 I40E_PHY_COM_REG_PAGE, 4803 led_addr, phy_addr, &led_reg); 4804 if (status) 4805 goto restore_config; 4806 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4807 led_reg = 0; 4808 else 4809 led_reg = I40E_PHY_LED_MANUAL_ON; 4810 status = i40e_write_phy_register_clause45(hw, 4811 I40E_PHY_COM_REG_PAGE, 4812 led_addr, phy_addr, led_reg); 4813 if (status) 4814 goto restore_config; 4815 msleep(interval); 4816 } 4817 } 4818 4819 restore_config: 4820 status = i40e_write_phy_register_clause45(hw, 4821 I40E_PHY_COM_REG_PAGE, 4822 led_addr, phy_addr, led_ctl); 4823 4824 phy_blinking_end: 4825 return status; 4826 } 4827 4828 /** 4829 * i40e_led_get_phy - return current on/off mode 4830 * @hw: pointer to the hw struct 4831 * @led_addr: address of led register to use 4832 * @val: original value of register to use 4833 * 4834 **/ 4835 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4836 u16 *val) 4837 { 4838 i40e_status status = 0; 4839 u16 gpio_led_port; 4840 u8 phy_addr = 0; 4841 u16 reg_val; 4842 u16 temp_addr; 4843 u8 port_num; 4844 u32 i; 4845 4846 temp_addr = I40E_PHY_LED_PROV_REG_1; 4847 i = rd32(hw, I40E_PFGEN_PORTNUM); 4848 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4849 phy_addr = i40e_get_phy_address(hw, port_num); 4850 4851 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4852 temp_addr++) { 4853 status = i40e_read_phy_register_clause45(hw, 4854 I40E_PHY_COM_REG_PAGE, 4855 temp_addr, phy_addr, 4856 ®_val); 4857 if (status) 4858 return status; 4859 *val = reg_val; 4860 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4861 *led_addr = temp_addr; 4862 break; 4863 } 4864 } 4865 return status; 4866 } 4867 4868 /** 4869 * i40e_led_set_phy 4870 * @hw: pointer to the HW structure 4871 * @on: true or false 4872 * @mode: original val plus bit for set or ignore 4873 * Set led's on or off when controlled by the PHY 4874 * 4875 **/ 4876 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4877 u16 led_addr, u32 mode) 4878 { 4879 i40e_status status = 0; 4880 u16 led_ctl = 0; 4881 u16 led_reg = 0; 4882 u8 phy_addr = 0; 4883 u8 port_num; 4884 u32 i; 4885 4886 i = rd32(hw, I40E_PFGEN_PORTNUM); 4887 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4888 phy_addr = i40e_get_phy_address(hw, port_num); 4889 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4890 led_addr, phy_addr, &led_reg); 4891 if (status) 4892 return status; 4893 led_ctl = led_reg; 4894 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4895 led_reg = 0; 4896 status = i40e_write_phy_register_clause45(hw, 4897 I40E_PHY_COM_REG_PAGE, 4898 led_addr, phy_addr, 4899 led_reg); 4900 if (status) 4901 return status; 4902 } 4903 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4904 led_addr, phy_addr, &led_reg); 4905 if (status) 4906 goto restore_config; 4907 if (on) 4908 led_reg = I40E_PHY_LED_MANUAL_ON; 4909 else 4910 led_reg = 0; 4911 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4912 led_addr, phy_addr, led_reg); 4913 if (status) 4914 goto restore_config; 4915 if (mode & I40E_PHY_LED_MODE_ORIG) { 4916 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4917 status = i40e_write_phy_register_clause45(hw, 4918 I40E_PHY_COM_REG_PAGE, 4919 led_addr, phy_addr, led_ctl); 4920 } 4921 return status; 4922 restore_config: 4923 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 4924 led_addr, phy_addr, led_ctl); 4925 return status; 4926 } 4927 4928 /** 4929 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4930 * @hw: pointer to the hw struct 4931 * @reg_addr: register address 4932 * @reg_val: ptr to register value 4933 * @cmd_details: pointer to command details structure or NULL 4934 * 4935 * Use the firmware to read the Rx control register, 4936 * especially useful if the Rx unit is under heavy pressure 4937 **/ 4938 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4939 u32 reg_addr, u32 *reg_val, 4940 struct i40e_asq_cmd_details *cmd_details) 4941 { 4942 struct i40e_aq_desc desc; 4943 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4944 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4945 i40e_status status; 4946 4947 if (!reg_val) 4948 return I40E_ERR_PARAM; 4949 4950 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4951 4952 cmd_resp->address = cpu_to_le32(reg_addr); 4953 4954 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4955 4956 if (status == 0) 4957 *reg_val = le32_to_cpu(cmd_resp->value); 4958 4959 return status; 4960 } 4961 4962 /** 4963 * i40e_read_rx_ctl - read from an Rx control register 4964 * @hw: pointer to the hw struct 4965 * @reg_addr: register address 4966 **/ 4967 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4968 { 4969 i40e_status status = 0; 4970 bool use_register; 4971 int retry = 5; 4972 u32 val = 0; 4973 4974 use_register = (((hw->aq.api_maj_ver == 1) && 4975 (hw->aq.api_min_ver < 5)) || 4976 (hw->mac.type == I40E_MAC_X722)); 4977 if (!use_register) { 4978 do_retry: 4979 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4980 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4981 usleep_range(1000, 2000); 4982 retry--; 4983 goto do_retry; 4984 } 4985 } 4986 4987 /* if the AQ access failed, try the old-fashioned way */ 4988 if (status || use_register) 4989 val = rd32(hw, reg_addr); 4990 4991 return val; 4992 } 4993 4994 /** 4995 * i40e_aq_rx_ctl_write_register 4996 * @hw: pointer to the hw struct 4997 * @reg_addr: register address 4998 * @reg_val: register value 4999 * @cmd_details: pointer to command details structure or NULL 5000 * 5001 * Use the firmware to write to an Rx control register, 5002 * especially useful if the Rx unit is under heavy pressure 5003 **/ 5004 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5005 u32 reg_addr, u32 reg_val, 5006 struct i40e_asq_cmd_details *cmd_details) 5007 { 5008 struct i40e_aq_desc desc; 5009 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5010 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5011 i40e_status status; 5012 5013 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5014 5015 cmd->address = cpu_to_le32(reg_addr); 5016 cmd->value = cpu_to_le32(reg_val); 5017 5018 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5019 5020 return status; 5021 } 5022 5023 /** 5024 * i40e_write_rx_ctl - write to an Rx control register 5025 * @hw: pointer to the hw struct 5026 * @reg_addr: register address 5027 * @reg_val: register value 5028 **/ 5029 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5030 { 5031 i40e_status status = 0; 5032 bool use_register; 5033 int retry = 5; 5034 5035 use_register = (((hw->aq.api_maj_ver == 1) && 5036 (hw->aq.api_min_ver < 5)) || 5037 (hw->mac.type == I40E_MAC_X722)); 5038 if (!use_register) { 5039 do_retry: 5040 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5041 reg_val, NULL); 5042 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5043 usleep_range(1000, 2000); 5044 retry--; 5045 goto do_retry; 5046 } 5047 } 5048 5049 /* if the AQ access failed, try the old-fashioned way */ 5050 if (status || use_register) 5051 wr32(hw, reg_addr, reg_val); 5052 } 5053 5054 /** 5055 * i40e_aq_write_ppp - Write pipeline personalization profile (ppp) 5056 * @hw: pointer to the hw struct 5057 * @buff: command buffer (size in bytes = buff_size) 5058 * @buff_size: buffer size in bytes 5059 * @track_id: package tracking id 5060 * @error_offset: returns error offset 5061 * @error_info: returns error information 5062 * @cmd_details: pointer to command details structure or NULL 5063 **/ 5064 enum 5065 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff, 5066 u16 buff_size, u32 track_id, 5067 u32 *error_offset, u32 *error_info, 5068 struct i40e_asq_cmd_details *cmd_details) 5069 { 5070 struct i40e_aq_desc desc; 5071 struct i40e_aqc_write_personalization_profile *cmd = 5072 (struct i40e_aqc_write_personalization_profile *) 5073 &desc.params.raw; 5074 struct i40e_aqc_write_ppp_resp *resp; 5075 i40e_status status; 5076 5077 i40e_fill_default_direct_cmd_desc(&desc, 5078 i40e_aqc_opc_write_personalization_profile); 5079 5080 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5081 if (buff_size > I40E_AQ_LARGE_BUF) 5082 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5083 5084 desc.datalen = cpu_to_le16(buff_size); 5085 5086 cmd->profile_track_id = cpu_to_le32(track_id); 5087 5088 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5089 if (!status) { 5090 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw; 5091 if (error_offset) 5092 *error_offset = le32_to_cpu(resp->error_offset); 5093 if (error_info) 5094 *error_info = le32_to_cpu(resp->error_info); 5095 } 5096 5097 return status; 5098 } 5099 5100 /** 5101 * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp) 5102 * @hw: pointer to the hw struct 5103 * @buff: command buffer (size in bytes = buff_size) 5104 * @buff_size: buffer size in bytes 5105 * @cmd_details: pointer to command details structure or NULL 5106 **/ 5107 enum 5108 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff, 5109 u16 buff_size, u8 flags, 5110 struct i40e_asq_cmd_details *cmd_details) 5111 { 5112 struct i40e_aq_desc desc; 5113 struct i40e_aqc_get_applied_profiles *cmd = 5114 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5115 i40e_status status; 5116 5117 i40e_fill_default_direct_cmd_desc(&desc, 5118 i40e_aqc_opc_get_personalization_profile_list); 5119 5120 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5121 if (buff_size > I40E_AQ_LARGE_BUF) 5122 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5123 desc.datalen = cpu_to_le16(buff_size); 5124 5125 cmd->flags = flags; 5126 5127 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5128 5129 return status; 5130 } 5131 5132 /** 5133 * i40e_find_segment_in_package 5134 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5135 * @pkg_hdr: pointer to the package header to be searched 5136 * 5137 * This function searches a package file for a particular segment type. On 5138 * success it returns a pointer to the segment header, otherwise it will 5139 * return NULL. 5140 **/ 5141 struct i40e_generic_seg_header * 5142 i40e_find_segment_in_package(u32 segment_type, 5143 struct i40e_package_header *pkg_hdr) 5144 { 5145 struct i40e_generic_seg_header *segment; 5146 u32 i; 5147 5148 /* Search all package segments for the requested segment type */ 5149 for (i = 0; i < pkg_hdr->segment_count; i++) { 5150 segment = 5151 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5152 pkg_hdr->segment_offset[i]); 5153 5154 if (segment->type == segment_type) 5155 return segment; 5156 } 5157 5158 return NULL; 5159 } 5160 5161 /** 5162 * i40e_write_profile 5163 * @hw: pointer to the hardware structure 5164 * @profile: pointer to the profile segment of the package to be downloaded 5165 * @track_id: package tracking id 5166 * 5167 * Handles the download of a complete package. 5168 */ 5169 enum i40e_status_code 5170 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5171 u32 track_id) 5172 { 5173 i40e_status status = 0; 5174 struct i40e_section_table *sec_tbl; 5175 struct i40e_profile_section_header *sec = NULL; 5176 u32 dev_cnt; 5177 u32 vendor_dev_id; 5178 u32 *nvm; 5179 u32 section_size = 0; 5180 u32 offset = 0, info = 0; 5181 u32 i; 5182 5183 if (!track_id) { 5184 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0."); 5185 return I40E_NOT_SUPPORTED; 5186 } 5187 5188 dev_cnt = profile->device_table_count; 5189 5190 for (i = 0; i < dev_cnt; i++) { 5191 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5192 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5193 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5194 break; 5195 } 5196 if (i == dev_cnt) { 5197 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP"); 5198 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5199 } 5200 5201 nvm = (u32 *)&profile->device_table[dev_cnt]; 5202 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5203 5204 for (i = 0; i < sec_tbl->section_count; i++) { 5205 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5206 sec_tbl->section_offset[i]); 5207 5208 /* Skip 'AQ', 'note' and 'name' sections */ 5209 if (sec->section.type != SECTION_TYPE_MMIO) 5210 continue; 5211 5212 section_size = sec->section.size + 5213 sizeof(struct i40e_profile_section_header); 5214 5215 /* Write profile */ 5216 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size, 5217 track_id, &offset, &info, NULL); 5218 if (status) { 5219 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5220 "Failed to write profile: offset %d, info %d", 5221 offset, info); 5222 break; 5223 } 5224 } 5225 return status; 5226 } 5227 5228 /** 5229 * i40e_add_pinfo_to_list 5230 * @hw: pointer to the hardware structure 5231 * @profile: pointer to the profile segment of the package 5232 * @profile_info_sec: buffer for information section 5233 * @track_id: package tracking id 5234 * 5235 * Register a profile to the list of loaded profiles. 5236 */ 5237 enum i40e_status_code 5238 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5239 struct i40e_profile_segment *profile, 5240 u8 *profile_info_sec, u32 track_id) 5241 { 5242 i40e_status status = 0; 5243 struct i40e_profile_section_header *sec = NULL; 5244 struct i40e_profile_info *pinfo; 5245 u32 offset = 0, info = 0; 5246 5247 sec = (struct i40e_profile_section_header *)profile_info_sec; 5248 sec->tbl_size = 1; 5249 sec->data_end = sizeof(struct i40e_profile_section_header) + 5250 sizeof(struct i40e_profile_info); 5251 sec->section.type = SECTION_TYPE_INFO; 5252 sec->section.offset = sizeof(struct i40e_profile_section_header); 5253 sec->section.size = sizeof(struct i40e_profile_info); 5254 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5255 sec->section.offset); 5256 pinfo->track_id = track_id; 5257 pinfo->version = profile->version; 5258 pinfo->op = I40E_PPP_ADD_TRACKID; 5259 memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE); 5260 5261 status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end, 5262 track_id, &offset, &info, NULL); 5263 return status; 5264 } 5265