1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Driver
4  * Copyright(c) 2013 - 2016 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26 
27 #include "i40e_type.h"
28 #include "i40e_adminq.h"
29 #include "i40e_prototype.h"
30 #include <linux/avf/virtchnl.h>
31 
32 /**
33  * i40e_set_mac_type - Sets MAC type
34  * @hw: pointer to the HW structure
35  *
36  * This function sets the mac type of the adapter based on the
37  * vendor ID and device ID stored in the hw structure.
38  **/
39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40 {
41 	i40e_status status = 0;
42 
43 	if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 		switch (hw->device_id) {
45 		case I40E_DEV_ID_SFP_XL710:
46 		case I40E_DEV_ID_QEMU:
47 		case I40E_DEV_ID_KX_B:
48 		case I40E_DEV_ID_KX_C:
49 		case I40E_DEV_ID_QSFP_A:
50 		case I40E_DEV_ID_QSFP_B:
51 		case I40E_DEV_ID_QSFP_C:
52 		case I40E_DEV_ID_10G_BASE_T:
53 		case I40E_DEV_ID_10G_BASE_T4:
54 		case I40E_DEV_ID_20G_KR2:
55 		case I40E_DEV_ID_20G_KR2_A:
56 		case I40E_DEV_ID_25G_B:
57 		case I40E_DEV_ID_25G_SFP28:
58 			hw->mac.type = I40E_MAC_XL710;
59 			break;
60 		case I40E_DEV_ID_KX_X722:
61 		case I40E_DEV_ID_QSFP_X722:
62 		case I40E_DEV_ID_SFP_X722:
63 		case I40E_DEV_ID_1G_BASE_T_X722:
64 		case I40E_DEV_ID_10G_BASE_T_X722:
65 		case I40E_DEV_ID_SFP_I_X722:
66 			hw->mac.type = I40E_MAC_X722;
67 			break;
68 		default:
69 			hw->mac.type = I40E_MAC_GENERIC;
70 			break;
71 		}
72 	} else {
73 		status = I40E_ERR_DEVICE_NOT_SUPPORTED;
74 	}
75 
76 	hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
77 		  hw->mac.type, status);
78 	return status;
79 }
80 
81 /**
82  * i40e_aq_str - convert AQ err code to a string
83  * @hw: pointer to the HW structure
84  * @aq_err: the AQ error code to convert
85  **/
86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
87 {
88 	switch (aq_err) {
89 	case I40E_AQ_RC_OK:
90 		return "OK";
91 	case I40E_AQ_RC_EPERM:
92 		return "I40E_AQ_RC_EPERM";
93 	case I40E_AQ_RC_ENOENT:
94 		return "I40E_AQ_RC_ENOENT";
95 	case I40E_AQ_RC_ESRCH:
96 		return "I40E_AQ_RC_ESRCH";
97 	case I40E_AQ_RC_EINTR:
98 		return "I40E_AQ_RC_EINTR";
99 	case I40E_AQ_RC_EIO:
100 		return "I40E_AQ_RC_EIO";
101 	case I40E_AQ_RC_ENXIO:
102 		return "I40E_AQ_RC_ENXIO";
103 	case I40E_AQ_RC_E2BIG:
104 		return "I40E_AQ_RC_E2BIG";
105 	case I40E_AQ_RC_EAGAIN:
106 		return "I40E_AQ_RC_EAGAIN";
107 	case I40E_AQ_RC_ENOMEM:
108 		return "I40E_AQ_RC_ENOMEM";
109 	case I40E_AQ_RC_EACCES:
110 		return "I40E_AQ_RC_EACCES";
111 	case I40E_AQ_RC_EFAULT:
112 		return "I40E_AQ_RC_EFAULT";
113 	case I40E_AQ_RC_EBUSY:
114 		return "I40E_AQ_RC_EBUSY";
115 	case I40E_AQ_RC_EEXIST:
116 		return "I40E_AQ_RC_EEXIST";
117 	case I40E_AQ_RC_EINVAL:
118 		return "I40E_AQ_RC_EINVAL";
119 	case I40E_AQ_RC_ENOTTY:
120 		return "I40E_AQ_RC_ENOTTY";
121 	case I40E_AQ_RC_ENOSPC:
122 		return "I40E_AQ_RC_ENOSPC";
123 	case I40E_AQ_RC_ENOSYS:
124 		return "I40E_AQ_RC_ENOSYS";
125 	case I40E_AQ_RC_ERANGE:
126 		return "I40E_AQ_RC_ERANGE";
127 	case I40E_AQ_RC_EFLUSHED:
128 		return "I40E_AQ_RC_EFLUSHED";
129 	case I40E_AQ_RC_BAD_ADDR:
130 		return "I40E_AQ_RC_BAD_ADDR";
131 	case I40E_AQ_RC_EMODE:
132 		return "I40E_AQ_RC_EMODE";
133 	case I40E_AQ_RC_EFBIG:
134 		return "I40E_AQ_RC_EFBIG";
135 	}
136 
137 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
138 	return hw->err_str;
139 }
140 
141 /**
142  * i40e_stat_str - convert status err code to a string
143  * @hw: pointer to the HW structure
144  * @stat_err: the status error code to convert
145  **/
146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
147 {
148 	switch (stat_err) {
149 	case 0:
150 		return "OK";
151 	case I40E_ERR_NVM:
152 		return "I40E_ERR_NVM";
153 	case I40E_ERR_NVM_CHECKSUM:
154 		return "I40E_ERR_NVM_CHECKSUM";
155 	case I40E_ERR_PHY:
156 		return "I40E_ERR_PHY";
157 	case I40E_ERR_CONFIG:
158 		return "I40E_ERR_CONFIG";
159 	case I40E_ERR_PARAM:
160 		return "I40E_ERR_PARAM";
161 	case I40E_ERR_MAC_TYPE:
162 		return "I40E_ERR_MAC_TYPE";
163 	case I40E_ERR_UNKNOWN_PHY:
164 		return "I40E_ERR_UNKNOWN_PHY";
165 	case I40E_ERR_LINK_SETUP:
166 		return "I40E_ERR_LINK_SETUP";
167 	case I40E_ERR_ADAPTER_STOPPED:
168 		return "I40E_ERR_ADAPTER_STOPPED";
169 	case I40E_ERR_INVALID_MAC_ADDR:
170 		return "I40E_ERR_INVALID_MAC_ADDR";
171 	case I40E_ERR_DEVICE_NOT_SUPPORTED:
172 		return "I40E_ERR_DEVICE_NOT_SUPPORTED";
173 	case I40E_ERR_MASTER_REQUESTS_PENDING:
174 		return "I40E_ERR_MASTER_REQUESTS_PENDING";
175 	case I40E_ERR_INVALID_LINK_SETTINGS:
176 		return "I40E_ERR_INVALID_LINK_SETTINGS";
177 	case I40E_ERR_AUTONEG_NOT_COMPLETE:
178 		return "I40E_ERR_AUTONEG_NOT_COMPLETE";
179 	case I40E_ERR_RESET_FAILED:
180 		return "I40E_ERR_RESET_FAILED";
181 	case I40E_ERR_SWFW_SYNC:
182 		return "I40E_ERR_SWFW_SYNC";
183 	case I40E_ERR_NO_AVAILABLE_VSI:
184 		return "I40E_ERR_NO_AVAILABLE_VSI";
185 	case I40E_ERR_NO_MEMORY:
186 		return "I40E_ERR_NO_MEMORY";
187 	case I40E_ERR_BAD_PTR:
188 		return "I40E_ERR_BAD_PTR";
189 	case I40E_ERR_RING_FULL:
190 		return "I40E_ERR_RING_FULL";
191 	case I40E_ERR_INVALID_PD_ID:
192 		return "I40E_ERR_INVALID_PD_ID";
193 	case I40E_ERR_INVALID_QP_ID:
194 		return "I40E_ERR_INVALID_QP_ID";
195 	case I40E_ERR_INVALID_CQ_ID:
196 		return "I40E_ERR_INVALID_CQ_ID";
197 	case I40E_ERR_INVALID_CEQ_ID:
198 		return "I40E_ERR_INVALID_CEQ_ID";
199 	case I40E_ERR_INVALID_AEQ_ID:
200 		return "I40E_ERR_INVALID_AEQ_ID";
201 	case I40E_ERR_INVALID_SIZE:
202 		return "I40E_ERR_INVALID_SIZE";
203 	case I40E_ERR_INVALID_ARP_INDEX:
204 		return "I40E_ERR_INVALID_ARP_INDEX";
205 	case I40E_ERR_INVALID_FPM_FUNC_ID:
206 		return "I40E_ERR_INVALID_FPM_FUNC_ID";
207 	case I40E_ERR_QP_INVALID_MSG_SIZE:
208 		return "I40E_ERR_QP_INVALID_MSG_SIZE";
209 	case I40E_ERR_QP_TOOMANY_WRS_POSTED:
210 		return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
211 	case I40E_ERR_INVALID_FRAG_COUNT:
212 		return "I40E_ERR_INVALID_FRAG_COUNT";
213 	case I40E_ERR_QUEUE_EMPTY:
214 		return "I40E_ERR_QUEUE_EMPTY";
215 	case I40E_ERR_INVALID_ALIGNMENT:
216 		return "I40E_ERR_INVALID_ALIGNMENT";
217 	case I40E_ERR_FLUSHED_QUEUE:
218 		return "I40E_ERR_FLUSHED_QUEUE";
219 	case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
220 		return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
221 	case I40E_ERR_INVALID_IMM_DATA_SIZE:
222 		return "I40E_ERR_INVALID_IMM_DATA_SIZE";
223 	case I40E_ERR_TIMEOUT:
224 		return "I40E_ERR_TIMEOUT";
225 	case I40E_ERR_OPCODE_MISMATCH:
226 		return "I40E_ERR_OPCODE_MISMATCH";
227 	case I40E_ERR_CQP_COMPL_ERROR:
228 		return "I40E_ERR_CQP_COMPL_ERROR";
229 	case I40E_ERR_INVALID_VF_ID:
230 		return "I40E_ERR_INVALID_VF_ID";
231 	case I40E_ERR_INVALID_HMCFN_ID:
232 		return "I40E_ERR_INVALID_HMCFN_ID";
233 	case I40E_ERR_BACKING_PAGE_ERROR:
234 		return "I40E_ERR_BACKING_PAGE_ERROR";
235 	case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
236 		return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
237 	case I40E_ERR_INVALID_PBLE_INDEX:
238 		return "I40E_ERR_INVALID_PBLE_INDEX";
239 	case I40E_ERR_INVALID_SD_INDEX:
240 		return "I40E_ERR_INVALID_SD_INDEX";
241 	case I40E_ERR_INVALID_PAGE_DESC_INDEX:
242 		return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
243 	case I40E_ERR_INVALID_SD_TYPE:
244 		return "I40E_ERR_INVALID_SD_TYPE";
245 	case I40E_ERR_MEMCPY_FAILED:
246 		return "I40E_ERR_MEMCPY_FAILED";
247 	case I40E_ERR_INVALID_HMC_OBJ_INDEX:
248 		return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
249 	case I40E_ERR_INVALID_HMC_OBJ_COUNT:
250 		return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
251 	case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
252 		return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
253 	case I40E_ERR_SRQ_ENABLED:
254 		return "I40E_ERR_SRQ_ENABLED";
255 	case I40E_ERR_ADMIN_QUEUE_ERROR:
256 		return "I40E_ERR_ADMIN_QUEUE_ERROR";
257 	case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
258 		return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
259 	case I40E_ERR_BUF_TOO_SHORT:
260 		return "I40E_ERR_BUF_TOO_SHORT";
261 	case I40E_ERR_ADMIN_QUEUE_FULL:
262 		return "I40E_ERR_ADMIN_QUEUE_FULL";
263 	case I40E_ERR_ADMIN_QUEUE_NO_WORK:
264 		return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
265 	case I40E_ERR_BAD_IWARP_CQE:
266 		return "I40E_ERR_BAD_IWARP_CQE";
267 	case I40E_ERR_NVM_BLANK_MODE:
268 		return "I40E_ERR_NVM_BLANK_MODE";
269 	case I40E_ERR_NOT_IMPLEMENTED:
270 		return "I40E_ERR_NOT_IMPLEMENTED";
271 	case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
272 		return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
273 	case I40E_ERR_DIAG_TEST_FAILED:
274 		return "I40E_ERR_DIAG_TEST_FAILED";
275 	case I40E_ERR_NOT_READY:
276 		return "I40E_ERR_NOT_READY";
277 	case I40E_NOT_SUPPORTED:
278 		return "I40E_NOT_SUPPORTED";
279 	case I40E_ERR_FIRMWARE_API_VERSION:
280 		return "I40E_ERR_FIRMWARE_API_VERSION";
281 	}
282 
283 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
284 	return hw->err_str;
285 }
286 
287 /**
288  * i40e_debug_aq
289  * @hw: debug mask related to admin queue
290  * @mask: debug mask
291  * @desc: pointer to admin queue descriptor
292  * @buffer: pointer to command buffer
293  * @buf_len: max length of buffer
294  *
295  * Dumps debug log about adminq command with descriptor contents.
296  **/
297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
298 		   void *buffer, u16 buf_len)
299 {
300 	struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
301 	u16 len;
302 	u8 *buf = (u8 *)buffer;
303 
304 	if ((!(mask & hw->debug_mask)) || (desc == NULL))
305 		return;
306 
307 	len = le16_to_cpu(aq_desc->datalen);
308 
309 	i40e_debug(hw, mask,
310 		   "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
311 		   le16_to_cpu(aq_desc->opcode),
312 		   le16_to_cpu(aq_desc->flags),
313 		   le16_to_cpu(aq_desc->datalen),
314 		   le16_to_cpu(aq_desc->retval));
315 	i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
316 		   le32_to_cpu(aq_desc->cookie_high),
317 		   le32_to_cpu(aq_desc->cookie_low));
318 	i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
319 		   le32_to_cpu(aq_desc->params.internal.param0),
320 		   le32_to_cpu(aq_desc->params.internal.param1));
321 	i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
322 		   le32_to_cpu(aq_desc->params.external.addr_high),
323 		   le32_to_cpu(aq_desc->params.external.addr_low));
324 
325 	if ((buffer != NULL) && (aq_desc->datalen != 0)) {
326 		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
327 		if (buf_len < len)
328 			len = buf_len;
329 		/* write the full 16-byte chunks */
330 		if (hw->debug_mask & mask) {
331 			char prefix[20];
332 
333 			snprintf(prefix, 20,
334 				 "i40e %02x:%02x.%x: \t0x",
335 				 hw->bus.bus_id,
336 				 hw->bus.device,
337 				 hw->bus.func);
338 
339 			print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
340 				       16, 1, buf, len, false);
341 		}
342 	}
343 }
344 
345 /**
346  * i40e_check_asq_alive
347  * @hw: pointer to the hw struct
348  *
349  * Returns true if Queue is enabled else false.
350  **/
351 bool i40e_check_asq_alive(struct i40e_hw *hw)
352 {
353 	if (hw->aq.asq.len)
354 		return !!(rd32(hw, hw->aq.asq.len) &
355 			  I40E_PF_ATQLEN_ATQENABLE_MASK);
356 	else
357 		return false;
358 }
359 
360 /**
361  * i40e_aq_queue_shutdown
362  * @hw: pointer to the hw struct
363  * @unloading: is the driver unloading itself
364  *
365  * Tell the Firmware that we're shutting down the AdminQ and whether
366  * or not the driver is unloading as well.
367  **/
368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
369 					     bool unloading)
370 {
371 	struct i40e_aq_desc desc;
372 	struct i40e_aqc_queue_shutdown *cmd =
373 		(struct i40e_aqc_queue_shutdown *)&desc.params.raw;
374 	i40e_status status;
375 
376 	i40e_fill_default_direct_cmd_desc(&desc,
377 					  i40e_aqc_opc_queue_shutdown);
378 
379 	if (unloading)
380 		cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
381 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
382 
383 	return status;
384 }
385 
386 /**
387  * i40e_aq_get_set_rss_lut
388  * @hw: pointer to the hardware structure
389  * @vsi_id: vsi fw index
390  * @pf_lut: for PF table set true, for VSI table set false
391  * @lut: pointer to the lut buffer provided by the caller
392  * @lut_size: size of the lut buffer
393  * @set: set true to set the table, false to get the table
394  *
395  * Internal function to get or set RSS look up table
396  **/
397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
398 					   u16 vsi_id, bool pf_lut,
399 					   u8 *lut, u16 lut_size,
400 					   bool set)
401 {
402 	i40e_status status;
403 	struct i40e_aq_desc desc;
404 	struct i40e_aqc_get_set_rss_lut *cmd_resp =
405 		   (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
406 
407 	if (set)
408 		i40e_fill_default_direct_cmd_desc(&desc,
409 						  i40e_aqc_opc_set_rss_lut);
410 	else
411 		i40e_fill_default_direct_cmd_desc(&desc,
412 						  i40e_aqc_opc_get_rss_lut);
413 
414 	/* Indirect command */
415 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
416 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
417 
418 	cmd_resp->vsi_id =
419 			cpu_to_le16((u16)((vsi_id <<
420 					  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
421 					  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
422 	cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
423 
424 	if (pf_lut)
425 		cmd_resp->flags |= cpu_to_le16((u16)
426 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
427 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
428 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
429 	else
430 		cmd_resp->flags |= cpu_to_le16((u16)
431 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
432 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
433 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
434 
435 	status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
436 
437 	return status;
438 }
439 
440 /**
441  * i40e_aq_get_rss_lut
442  * @hw: pointer to the hardware structure
443  * @vsi_id: vsi fw index
444  * @pf_lut: for PF table set true, for VSI table set false
445  * @lut: pointer to the lut buffer provided by the caller
446  * @lut_size: size of the lut buffer
447  *
448  * get the RSS lookup table, PF or VSI type
449  **/
450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
451 				bool pf_lut, u8 *lut, u16 lut_size)
452 {
453 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
454 				       false);
455 }
456 
457 /**
458  * i40e_aq_set_rss_lut
459  * @hw: pointer to the hardware structure
460  * @vsi_id: vsi fw index
461  * @pf_lut: for PF table set true, for VSI table set false
462  * @lut: pointer to the lut buffer provided by the caller
463  * @lut_size: size of the lut buffer
464  *
465  * set the RSS lookup table, PF or VSI type
466  **/
467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
468 				bool pf_lut, u8 *lut, u16 lut_size)
469 {
470 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
471 }
472 
473 /**
474  * i40e_aq_get_set_rss_key
475  * @hw: pointer to the hw struct
476  * @vsi_id: vsi fw index
477  * @key: pointer to key info struct
478  * @set: set true to set the key, false to get the key
479  *
480  * get the RSS key per VSI
481  **/
482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
483 				      u16 vsi_id,
484 				      struct i40e_aqc_get_set_rss_key_data *key,
485 				      bool set)
486 {
487 	i40e_status status;
488 	struct i40e_aq_desc desc;
489 	struct i40e_aqc_get_set_rss_key *cmd_resp =
490 			(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
491 	u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
492 
493 	if (set)
494 		i40e_fill_default_direct_cmd_desc(&desc,
495 						  i40e_aqc_opc_set_rss_key);
496 	else
497 		i40e_fill_default_direct_cmd_desc(&desc,
498 						  i40e_aqc_opc_get_rss_key);
499 
500 	/* Indirect command */
501 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
502 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
503 
504 	cmd_resp->vsi_id =
505 			cpu_to_le16((u16)((vsi_id <<
506 					  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
507 					  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
508 	cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
509 
510 	status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
511 
512 	return status;
513 }
514 
515 /**
516  * i40e_aq_get_rss_key
517  * @hw: pointer to the hw struct
518  * @vsi_id: vsi fw index
519  * @key: pointer to key info struct
520  *
521  **/
522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
523 				u16 vsi_id,
524 				struct i40e_aqc_get_set_rss_key_data *key)
525 {
526 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
527 }
528 
529 /**
530  * i40e_aq_set_rss_key
531  * @hw: pointer to the hw struct
532  * @vsi_id: vsi fw index
533  * @key: pointer to key info struct
534  *
535  * set the RSS key per VSI
536  **/
537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
538 				u16 vsi_id,
539 				struct i40e_aqc_get_set_rss_key_data *key)
540 {
541 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
542 }
543 
544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
545  * hardware to a bit-field that can be used by SW to more easily determine the
546  * packet type.
547  *
548  * Macros are used to shorten the table lines and make this table human
549  * readable.
550  *
551  * We store the PTYPE in the top byte of the bit field - this is just so that
552  * we can check that the table doesn't have a row missing, as the index into
553  * the table should be the PTYPE.
554  *
555  * Typical work flow:
556  *
557  * IF NOT i40e_ptype_lookup[ptype].known
558  * THEN
559  *      Packet is unknown
560  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
561  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
562  * ELSE
563  *      Use the enum i40e_rx_l2_ptype to decode the packet type
564  * ENDIF
565  */
566 
567 /* macro to make the table lines short */
568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
569 	{	PTYPE, \
570 		1, \
571 		I40E_RX_PTYPE_OUTER_##OUTER_IP, \
572 		I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
573 		I40E_RX_PTYPE_##OUTER_FRAG, \
574 		I40E_RX_PTYPE_TUNNEL_##T, \
575 		I40E_RX_PTYPE_TUNNEL_END_##TE, \
576 		I40E_RX_PTYPE_##TEF, \
577 		I40E_RX_PTYPE_INNER_PROT_##I, \
578 		I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
579 
580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
581 		{ PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
582 
583 /* shorter macros makes the table fit but are terse */
584 #define I40E_RX_PTYPE_NOF		I40E_RX_PTYPE_NOT_FRAG
585 #define I40E_RX_PTYPE_FRG		I40E_RX_PTYPE_FRAG
586 #define I40E_RX_PTYPE_INNER_PROT_TS	I40E_RX_PTYPE_INNER_PROT_TIMESYNC
587 
588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
590 	/* L2 Packet types */
591 	I40E_PTT_UNUSED_ENTRY(0),
592 	I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
593 	I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
594 	I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
595 	I40E_PTT_UNUSED_ENTRY(4),
596 	I40E_PTT_UNUSED_ENTRY(5),
597 	I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
598 	I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
599 	I40E_PTT_UNUSED_ENTRY(8),
600 	I40E_PTT_UNUSED_ENTRY(9),
601 	I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
602 	I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
603 	I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
604 	I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
605 	I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
606 	I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
607 	I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
608 	I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
609 	I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
610 	I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
611 	I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
612 	I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
613 
614 	/* Non Tunneled IPv4 */
615 	I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
616 	I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
617 	I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
618 	I40E_PTT_UNUSED_ENTRY(25),
619 	I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
620 	I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
621 	I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
622 
623 	/* IPv4 --> IPv4 */
624 	I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
625 	I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
626 	I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
627 	I40E_PTT_UNUSED_ENTRY(32),
628 	I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
629 	I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
630 	I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
631 
632 	/* IPv4 --> IPv6 */
633 	I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
634 	I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
635 	I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
636 	I40E_PTT_UNUSED_ENTRY(39),
637 	I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
638 	I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
639 	I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
640 
641 	/* IPv4 --> GRE/NAT */
642 	I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
643 
644 	/* IPv4 --> GRE/NAT --> IPv4 */
645 	I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
646 	I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
647 	I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
648 	I40E_PTT_UNUSED_ENTRY(47),
649 	I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
650 	I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
651 	I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
652 
653 	/* IPv4 --> GRE/NAT --> IPv6 */
654 	I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
655 	I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
656 	I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
657 	I40E_PTT_UNUSED_ENTRY(54),
658 	I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
659 	I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
660 	I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
661 
662 	/* IPv4 --> GRE/NAT --> MAC */
663 	I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
664 
665 	/* IPv4 --> GRE/NAT --> MAC --> IPv4 */
666 	I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
667 	I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
668 	I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
669 	I40E_PTT_UNUSED_ENTRY(62),
670 	I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
671 	I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
672 	I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
673 
674 	/* IPv4 --> GRE/NAT -> MAC --> IPv6 */
675 	I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
676 	I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
677 	I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
678 	I40E_PTT_UNUSED_ENTRY(69),
679 	I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
680 	I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
681 	I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
682 
683 	/* IPv4 --> GRE/NAT --> MAC/VLAN */
684 	I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
685 
686 	/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
687 	I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
688 	I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
689 	I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
690 	I40E_PTT_UNUSED_ENTRY(77),
691 	I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
692 	I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
693 	I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
694 
695 	/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
696 	I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
697 	I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
698 	I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
699 	I40E_PTT_UNUSED_ENTRY(84),
700 	I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
701 	I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
702 	I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
703 
704 	/* Non Tunneled IPv6 */
705 	I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
706 	I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
707 	I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
708 	I40E_PTT_UNUSED_ENTRY(91),
709 	I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
710 	I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
711 	I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
712 
713 	/* IPv6 --> IPv4 */
714 	I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
715 	I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
716 	I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
717 	I40E_PTT_UNUSED_ENTRY(98),
718 	I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
719 	I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
720 	I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
721 
722 	/* IPv6 --> IPv6 */
723 	I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
724 	I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
725 	I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
726 	I40E_PTT_UNUSED_ENTRY(105),
727 	I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
728 	I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
729 	I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
730 
731 	/* IPv6 --> GRE/NAT */
732 	I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
733 
734 	/* IPv6 --> GRE/NAT -> IPv4 */
735 	I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
736 	I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
737 	I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
738 	I40E_PTT_UNUSED_ENTRY(113),
739 	I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
740 	I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
741 	I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
742 
743 	/* IPv6 --> GRE/NAT -> IPv6 */
744 	I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
745 	I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
746 	I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
747 	I40E_PTT_UNUSED_ENTRY(120),
748 	I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
749 	I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
750 	I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
751 
752 	/* IPv6 --> GRE/NAT -> MAC */
753 	I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
754 
755 	/* IPv6 --> GRE/NAT -> MAC -> IPv4 */
756 	I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
757 	I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
758 	I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
759 	I40E_PTT_UNUSED_ENTRY(128),
760 	I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
761 	I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
762 	I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
763 
764 	/* IPv6 --> GRE/NAT -> MAC -> IPv6 */
765 	I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
766 	I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
767 	I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
768 	I40E_PTT_UNUSED_ENTRY(135),
769 	I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
770 	I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
771 	I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
772 
773 	/* IPv6 --> GRE/NAT -> MAC/VLAN */
774 	I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
775 
776 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
777 	I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
778 	I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
779 	I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
780 	I40E_PTT_UNUSED_ENTRY(143),
781 	I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
782 	I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
783 	I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
784 
785 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
786 	I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
787 	I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
788 	I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
789 	I40E_PTT_UNUSED_ENTRY(150),
790 	I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
791 	I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
792 	I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
793 
794 	/* unused entries */
795 	I40E_PTT_UNUSED_ENTRY(154),
796 	I40E_PTT_UNUSED_ENTRY(155),
797 	I40E_PTT_UNUSED_ENTRY(156),
798 	I40E_PTT_UNUSED_ENTRY(157),
799 	I40E_PTT_UNUSED_ENTRY(158),
800 	I40E_PTT_UNUSED_ENTRY(159),
801 
802 	I40E_PTT_UNUSED_ENTRY(160),
803 	I40E_PTT_UNUSED_ENTRY(161),
804 	I40E_PTT_UNUSED_ENTRY(162),
805 	I40E_PTT_UNUSED_ENTRY(163),
806 	I40E_PTT_UNUSED_ENTRY(164),
807 	I40E_PTT_UNUSED_ENTRY(165),
808 	I40E_PTT_UNUSED_ENTRY(166),
809 	I40E_PTT_UNUSED_ENTRY(167),
810 	I40E_PTT_UNUSED_ENTRY(168),
811 	I40E_PTT_UNUSED_ENTRY(169),
812 
813 	I40E_PTT_UNUSED_ENTRY(170),
814 	I40E_PTT_UNUSED_ENTRY(171),
815 	I40E_PTT_UNUSED_ENTRY(172),
816 	I40E_PTT_UNUSED_ENTRY(173),
817 	I40E_PTT_UNUSED_ENTRY(174),
818 	I40E_PTT_UNUSED_ENTRY(175),
819 	I40E_PTT_UNUSED_ENTRY(176),
820 	I40E_PTT_UNUSED_ENTRY(177),
821 	I40E_PTT_UNUSED_ENTRY(178),
822 	I40E_PTT_UNUSED_ENTRY(179),
823 
824 	I40E_PTT_UNUSED_ENTRY(180),
825 	I40E_PTT_UNUSED_ENTRY(181),
826 	I40E_PTT_UNUSED_ENTRY(182),
827 	I40E_PTT_UNUSED_ENTRY(183),
828 	I40E_PTT_UNUSED_ENTRY(184),
829 	I40E_PTT_UNUSED_ENTRY(185),
830 	I40E_PTT_UNUSED_ENTRY(186),
831 	I40E_PTT_UNUSED_ENTRY(187),
832 	I40E_PTT_UNUSED_ENTRY(188),
833 	I40E_PTT_UNUSED_ENTRY(189),
834 
835 	I40E_PTT_UNUSED_ENTRY(190),
836 	I40E_PTT_UNUSED_ENTRY(191),
837 	I40E_PTT_UNUSED_ENTRY(192),
838 	I40E_PTT_UNUSED_ENTRY(193),
839 	I40E_PTT_UNUSED_ENTRY(194),
840 	I40E_PTT_UNUSED_ENTRY(195),
841 	I40E_PTT_UNUSED_ENTRY(196),
842 	I40E_PTT_UNUSED_ENTRY(197),
843 	I40E_PTT_UNUSED_ENTRY(198),
844 	I40E_PTT_UNUSED_ENTRY(199),
845 
846 	I40E_PTT_UNUSED_ENTRY(200),
847 	I40E_PTT_UNUSED_ENTRY(201),
848 	I40E_PTT_UNUSED_ENTRY(202),
849 	I40E_PTT_UNUSED_ENTRY(203),
850 	I40E_PTT_UNUSED_ENTRY(204),
851 	I40E_PTT_UNUSED_ENTRY(205),
852 	I40E_PTT_UNUSED_ENTRY(206),
853 	I40E_PTT_UNUSED_ENTRY(207),
854 	I40E_PTT_UNUSED_ENTRY(208),
855 	I40E_PTT_UNUSED_ENTRY(209),
856 
857 	I40E_PTT_UNUSED_ENTRY(210),
858 	I40E_PTT_UNUSED_ENTRY(211),
859 	I40E_PTT_UNUSED_ENTRY(212),
860 	I40E_PTT_UNUSED_ENTRY(213),
861 	I40E_PTT_UNUSED_ENTRY(214),
862 	I40E_PTT_UNUSED_ENTRY(215),
863 	I40E_PTT_UNUSED_ENTRY(216),
864 	I40E_PTT_UNUSED_ENTRY(217),
865 	I40E_PTT_UNUSED_ENTRY(218),
866 	I40E_PTT_UNUSED_ENTRY(219),
867 
868 	I40E_PTT_UNUSED_ENTRY(220),
869 	I40E_PTT_UNUSED_ENTRY(221),
870 	I40E_PTT_UNUSED_ENTRY(222),
871 	I40E_PTT_UNUSED_ENTRY(223),
872 	I40E_PTT_UNUSED_ENTRY(224),
873 	I40E_PTT_UNUSED_ENTRY(225),
874 	I40E_PTT_UNUSED_ENTRY(226),
875 	I40E_PTT_UNUSED_ENTRY(227),
876 	I40E_PTT_UNUSED_ENTRY(228),
877 	I40E_PTT_UNUSED_ENTRY(229),
878 
879 	I40E_PTT_UNUSED_ENTRY(230),
880 	I40E_PTT_UNUSED_ENTRY(231),
881 	I40E_PTT_UNUSED_ENTRY(232),
882 	I40E_PTT_UNUSED_ENTRY(233),
883 	I40E_PTT_UNUSED_ENTRY(234),
884 	I40E_PTT_UNUSED_ENTRY(235),
885 	I40E_PTT_UNUSED_ENTRY(236),
886 	I40E_PTT_UNUSED_ENTRY(237),
887 	I40E_PTT_UNUSED_ENTRY(238),
888 	I40E_PTT_UNUSED_ENTRY(239),
889 
890 	I40E_PTT_UNUSED_ENTRY(240),
891 	I40E_PTT_UNUSED_ENTRY(241),
892 	I40E_PTT_UNUSED_ENTRY(242),
893 	I40E_PTT_UNUSED_ENTRY(243),
894 	I40E_PTT_UNUSED_ENTRY(244),
895 	I40E_PTT_UNUSED_ENTRY(245),
896 	I40E_PTT_UNUSED_ENTRY(246),
897 	I40E_PTT_UNUSED_ENTRY(247),
898 	I40E_PTT_UNUSED_ENTRY(248),
899 	I40E_PTT_UNUSED_ENTRY(249),
900 
901 	I40E_PTT_UNUSED_ENTRY(250),
902 	I40E_PTT_UNUSED_ENTRY(251),
903 	I40E_PTT_UNUSED_ENTRY(252),
904 	I40E_PTT_UNUSED_ENTRY(253),
905 	I40E_PTT_UNUSED_ENTRY(254),
906 	I40E_PTT_UNUSED_ENTRY(255)
907 };
908 
909 /**
910  * i40e_init_shared_code - Initialize the shared code
911  * @hw: pointer to hardware structure
912  *
913  * This assigns the MAC type and PHY code and inits the NVM.
914  * Does not touch the hardware. This function must be called prior to any
915  * other function in the shared code. The i40e_hw structure should be
916  * memset to 0 prior to calling this function.  The following fields in
917  * hw structure should be filled in prior to calling this function:
918  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
919  * subsystem_vendor_id, and revision_id
920  **/
921 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
922 {
923 	i40e_status status = 0;
924 	u32 port, ari, func_rid;
925 
926 	i40e_set_mac_type(hw);
927 
928 	switch (hw->mac.type) {
929 	case I40E_MAC_XL710:
930 	case I40E_MAC_X722:
931 		break;
932 	default:
933 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
934 	}
935 
936 	hw->phy.get_link_info = true;
937 
938 	/* Determine port number and PF number*/
939 	port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
940 					   >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
941 	hw->port = (u8)port;
942 	ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
943 						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
944 	func_rid = rd32(hw, I40E_PF_FUNC_RID);
945 	if (ari)
946 		hw->pf_id = (u8)(func_rid & 0xff);
947 	else
948 		hw->pf_id = (u8)(func_rid & 0x7);
949 
950 	if (hw->mac.type == I40E_MAC_X722)
951 		hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
952 
953 	status = i40e_init_nvm(hw);
954 	return status;
955 }
956 
957 /**
958  * i40e_aq_mac_address_read - Retrieve the MAC addresses
959  * @hw: pointer to the hw struct
960  * @flags: a return indicator of what addresses were added to the addr store
961  * @addrs: the requestor's mac addr store
962  * @cmd_details: pointer to command details structure or NULL
963  **/
964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
965 				   u16 *flags,
966 				   struct i40e_aqc_mac_address_read_data *addrs,
967 				   struct i40e_asq_cmd_details *cmd_details)
968 {
969 	struct i40e_aq_desc desc;
970 	struct i40e_aqc_mac_address_read *cmd_data =
971 		(struct i40e_aqc_mac_address_read *)&desc.params.raw;
972 	i40e_status status;
973 
974 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
975 	desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
976 
977 	status = i40e_asq_send_command(hw, &desc, addrs,
978 				       sizeof(*addrs), cmd_details);
979 	*flags = le16_to_cpu(cmd_data->command_flags);
980 
981 	return status;
982 }
983 
984 /**
985  * i40e_aq_mac_address_write - Change the MAC addresses
986  * @hw: pointer to the hw struct
987  * @flags: indicates which MAC to be written
988  * @mac_addr: address to write
989  * @cmd_details: pointer to command details structure or NULL
990  **/
991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
992 				    u16 flags, u8 *mac_addr,
993 				    struct i40e_asq_cmd_details *cmd_details)
994 {
995 	struct i40e_aq_desc desc;
996 	struct i40e_aqc_mac_address_write *cmd_data =
997 		(struct i40e_aqc_mac_address_write *)&desc.params.raw;
998 	i40e_status status;
999 
1000 	i40e_fill_default_direct_cmd_desc(&desc,
1001 					  i40e_aqc_opc_mac_address_write);
1002 	cmd_data->command_flags = cpu_to_le16(flags);
1003 	cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1004 	cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1005 					((u32)mac_addr[3] << 16) |
1006 					((u32)mac_addr[4] << 8) |
1007 					mac_addr[5]);
1008 
1009 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1010 
1011 	return status;
1012 }
1013 
1014 /**
1015  * i40e_get_mac_addr - get MAC address
1016  * @hw: pointer to the HW structure
1017  * @mac_addr: pointer to MAC address
1018  *
1019  * Reads the adapter's MAC address from register
1020  **/
1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1022 {
1023 	struct i40e_aqc_mac_address_read_data addrs;
1024 	i40e_status status;
1025 	u16 flags = 0;
1026 
1027 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1028 
1029 	if (flags & I40E_AQC_LAN_ADDR_VALID)
1030 		ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1031 
1032 	return status;
1033 }
1034 
1035 /**
1036  * i40e_get_port_mac_addr - get Port MAC address
1037  * @hw: pointer to the HW structure
1038  * @mac_addr: pointer to Port MAC address
1039  *
1040  * Reads the adapter's Port MAC address
1041  **/
1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1043 {
1044 	struct i40e_aqc_mac_address_read_data addrs;
1045 	i40e_status status;
1046 	u16 flags = 0;
1047 
1048 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1049 	if (status)
1050 		return status;
1051 
1052 	if (flags & I40E_AQC_PORT_ADDR_VALID)
1053 		ether_addr_copy(mac_addr, addrs.port_mac);
1054 	else
1055 		status = I40E_ERR_INVALID_MAC_ADDR;
1056 
1057 	return status;
1058 }
1059 
1060 /**
1061  * i40e_pre_tx_queue_cfg - pre tx queue configure
1062  * @hw: pointer to the HW structure
1063  * @queue: target PF queue index
1064  * @enable: state change request
1065  *
1066  * Handles hw requirement to indicate intention to enable
1067  * or disable target queue.
1068  **/
1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1070 {
1071 	u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1072 	u32 reg_block = 0;
1073 	u32 reg_val;
1074 
1075 	if (abs_queue_idx >= 128) {
1076 		reg_block = abs_queue_idx / 128;
1077 		abs_queue_idx %= 128;
1078 	}
1079 
1080 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1081 	reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1082 	reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1083 
1084 	if (enable)
1085 		reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1086 	else
1087 		reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1088 
1089 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1090 }
1091 
1092 /**
1093  *  i40e_read_pba_string - Reads part number string from EEPROM
1094  *  @hw: pointer to hardware structure
1095  *  @pba_num: stores the part number string from the EEPROM
1096  *  @pba_num_size: part number string buffer length
1097  *
1098  *  Reads the part number string from the EEPROM.
1099  **/
1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1101 				 u32 pba_num_size)
1102 {
1103 	i40e_status status = 0;
1104 	u16 pba_word = 0;
1105 	u16 pba_size = 0;
1106 	u16 pba_ptr = 0;
1107 	u16 i = 0;
1108 
1109 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1110 	if (status || (pba_word != 0xFAFA)) {
1111 		hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1112 		return status;
1113 	}
1114 
1115 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1116 	if (status) {
1117 		hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1118 		return status;
1119 	}
1120 
1121 	status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1122 	if (status) {
1123 		hw_dbg(hw, "Failed to read PBA Block size.\n");
1124 		return status;
1125 	}
1126 
1127 	/* Subtract one to get PBA word count (PBA Size word is included in
1128 	 * total size)
1129 	 */
1130 	pba_size--;
1131 	if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1132 		hw_dbg(hw, "Buffer to small for PBA data.\n");
1133 		return I40E_ERR_PARAM;
1134 	}
1135 
1136 	for (i = 0; i < pba_size; i++) {
1137 		status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1138 		if (status) {
1139 			hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1140 			return status;
1141 		}
1142 
1143 		pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1144 		pba_num[(i * 2) + 1] = pba_word & 0xFF;
1145 	}
1146 	pba_num[(pba_size * 2)] = '\0';
1147 
1148 	return status;
1149 }
1150 
1151 /**
1152  * i40e_get_media_type - Gets media type
1153  * @hw: pointer to the hardware structure
1154  **/
1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1156 {
1157 	enum i40e_media_type media;
1158 
1159 	switch (hw->phy.link_info.phy_type) {
1160 	case I40E_PHY_TYPE_10GBASE_SR:
1161 	case I40E_PHY_TYPE_10GBASE_LR:
1162 	case I40E_PHY_TYPE_1000BASE_SX:
1163 	case I40E_PHY_TYPE_1000BASE_LX:
1164 	case I40E_PHY_TYPE_40GBASE_SR4:
1165 	case I40E_PHY_TYPE_40GBASE_LR4:
1166 	case I40E_PHY_TYPE_25GBASE_LR:
1167 	case I40E_PHY_TYPE_25GBASE_SR:
1168 		media = I40E_MEDIA_TYPE_FIBER;
1169 		break;
1170 	case I40E_PHY_TYPE_100BASE_TX:
1171 	case I40E_PHY_TYPE_1000BASE_T:
1172 	case I40E_PHY_TYPE_10GBASE_T:
1173 		media = I40E_MEDIA_TYPE_BASET;
1174 		break;
1175 	case I40E_PHY_TYPE_10GBASE_CR1_CU:
1176 	case I40E_PHY_TYPE_40GBASE_CR4_CU:
1177 	case I40E_PHY_TYPE_10GBASE_CR1:
1178 	case I40E_PHY_TYPE_40GBASE_CR4:
1179 	case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1180 	case I40E_PHY_TYPE_40GBASE_AOC:
1181 	case I40E_PHY_TYPE_10GBASE_AOC:
1182 	case I40E_PHY_TYPE_25GBASE_CR:
1183 		media = I40E_MEDIA_TYPE_DA;
1184 		break;
1185 	case I40E_PHY_TYPE_1000BASE_KX:
1186 	case I40E_PHY_TYPE_10GBASE_KX4:
1187 	case I40E_PHY_TYPE_10GBASE_KR:
1188 	case I40E_PHY_TYPE_40GBASE_KR4:
1189 	case I40E_PHY_TYPE_20GBASE_KR2:
1190 	case I40E_PHY_TYPE_25GBASE_KR:
1191 		media = I40E_MEDIA_TYPE_BACKPLANE;
1192 		break;
1193 	case I40E_PHY_TYPE_SGMII:
1194 	case I40E_PHY_TYPE_XAUI:
1195 	case I40E_PHY_TYPE_XFI:
1196 	case I40E_PHY_TYPE_XLAUI:
1197 	case I40E_PHY_TYPE_XLPPI:
1198 	default:
1199 		media = I40E_MEDIA_TYPE_UNKNOWN;
1200 		break;
1201 	}
1202 
1203 	return media;
1204 }
1205 
1206 #define I40E_PF_RESET_WAIT_COUNT_A0	200
1207 #define I40E_PF_RESET_WAIT_COUNT	200
1208 /**
1209  * i40e_pf_reset - Reset the PF
1210  * @hw: pointer to the hardware structure
1211  *
1212  * Assuming someone else has triggered a global reset,
1213  * assure the global reset is complete and then reset the PF
1214  **/
1215 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1216 {
1217 	u32 cnt = 0;
1218 	u32 cnt1 = 0;
1219 	u32 reg = 0;
1220 	u32 grst_del;
1221 
1222 	/* Poll for Global Reset steady state in case of recent GRST.
1223 	 * The grst delay value is in 100ms units, and we'll wait a
1224 	 * couple counts longer to be sure we don't just miss the end.
1225 	 */
1226 	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1227 		    I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1228 		    I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1229 
1230 	/* It can take upto 15 secs for GRST steady state.
1231 	 * Bump it to 16 secs max to be safe.
1232 	 */
1233 	grst_del = grst_del * 20;
1234 
1235 	for (cnt = 0; cnt < grst_del; cnt++) {
1236 		reg = rd32(hw, I40E_GLGEN_RSTAT);
1237 		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1238 			break;
1239 		msleep(100);
1240 	}
1241 	if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1242 		hw_dbg(hw, "Global reset polling failed to complete.\n");
1243 		return I40E_ERR_RESET_FAILED;
1244 	}
1245 
1246 	/* Now Wait for the FW to be ready */
1247 	for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1248 		reg = rd32(hw, I40E_GLNVM_ULD);
1249 		reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1250 			I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1251 		if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1252 			    I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1253 			hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1254 			break;
1255 		}
1256 		usleep_range(10000, 20000);
1257 	}
1258 	if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1259 		     I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1260 		hw_dbg(hw, "wait for FW Reset complete timedout\n");
1261 		hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1262 		return I40E_ERR_RESET_FAILED;
1263 	}
1264 
1265 	/* If there was a Global Reset in progress when we got here,
1266 	 * we don't need to do the PF Reset
1267 	 */
1268 	if (!cnt) {
1269 		if (hw->revision_id == 0)
1270 			cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1271 		else
1272 			cnt = I40E_PF_RESET_WAIT_COUNT;
1273 		reg = rd32(hw, I40E_PFGEN_CTRL);
1274 		wr32(hw, I40E_PFGEN_CTRL,
1275 		     (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1276 		for (; cnt; cnt--) {
1277 			reg = rd32(hw, I40E_PFGEN_CTRL);
1278 			if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1279 				break;
1280 			usleep_range(1000, 2000);
1281 		}
1282 		if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1283 			hw_dbg(hw, "PF reset polling failed to complete.\n");
1284 			return I40E_ERR_RESET_FAILED;
1285 		}
1286 	}
1287 
1288 	i40e_clear_pxe_mode(hw);
1289 
1290 	return 0;
1291 }
1292 
1293 /**
1294  * i40e_clear_hw - clear out any left over hw state
1295  * @hw: pointer to the hw struct
1296  *
1297  * Clear queues and interrupts, typically called at init time,
1298  * but after the capabilities have been found so we know how many
1299  * queues and msix vectors have been allocated.
1300  **/
1301 void i40e_clear_hw(struct i40e_hw *hw)
1302 {
1303 	u32 num_queues, base_queue;
1304 	u32 num_pf_int;
1305 	u32 num_vf_int;
1306 	u32 num_vfs;
1307 	u32 i, j;
1308 	u32 val;
1309 	u32 eol = 0x7ff;
1310 
1311 	/* get number of interrupts, queues, and VFs */
1312 	val = rd32(hw, I40E_GLPCI_CNF2);
1313 	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1314 		     I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1315 	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1316 		     I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1317 
1318 	val = rd32(hw, I40E_PFLAN_QALLOC);
1319 	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1320 		     I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1321 	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1322 	    I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1323 	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1324 		num_queues = (j - base_queue) + 1;
1325 	else
1326 		num_queues = 0;
1327 
1328 	val = rd32(hw, I40E_PF_VT_PFALLOC);
1329 	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1330 	    I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1331 	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1332 	    I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1333 	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1334 		num_vfs = (j - i) + 1;
1335 	else
1336 		num_vfs = 0;
1337 
1338 	/* stop all the interrupts */
1339 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1340 	val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1341 	for (i = 0; i < num_pf_int - 2; i++)
1342 		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1343 
1344 	/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1345 	val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1346 	wr32(hw, I40E_PFINT_LNKLST0, val);
1347 	for (i = 0; i < num_pf_int - 2; i++)
1348 		wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1349 	val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1350 	for (i = 0; i < num_vfs; i++)
1351 		wr32(hw, I40E_VPINT_LNKLST0(i), val);
1352 	for (i = 0; i < num_vf_int - 2; i++)
1353 		wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1354 
1355 	/* warn the HW of the coming Tx disables */
1356 	for (i = 0; i < num_queues; i++) {
1357 		u32 abs_queue_idx = base_queue + i;
1358 		u32 reg_block = 0;
1359 
1360 		if (abs_queue_idx >= 128) {
1361 			reg_block = abs_queue_idx / 128;
1362 			abs_queue_idx %= 128;
1363 		}
1364 
1365 		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1366 		val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1367 		val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1368 		val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1369 
1370 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1371 	}
1372 	udelay(400);
1373 
1374 	/* stop all the queues */
1375 	for (i = 0; i < num_queues; i++) {
1376 		wr32(hw, I40E_QINT_TQCTL(i), 0);
1377 		wr32(hw, I40E_QTX_ENA(i), 0);
1378 		wr32(hw, I40E_QINT_RQCTL(i), 0);
1379 		wr32(hw, I40E_QRX_ENA(i), 0);
1380 	}
1381 
1382 	/* short wait for all queue disables to settle */
1383 	udelay(50);
1384 }
1385 
1386 /**
1387  * i40e_clear_pxe_mode - clear pxe operations mode
1388  * @hw: pointer to the hw struct
1389  *
1390  * Make sure all PXE mode settings are cleared, including things
1391  * like descriptor fetch/write-back mode.
1392  **/
1393 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1394 {
1395 	u32 reg;
1396 
1397 	if (i40e_check_asq_alive(hw))
1398 		i40e_aq_clear_pxe_mode(hw, NULL);
1399 
1400 	/* Clear single descriptor fetch/write-back mode */
1401 	reg = rd32(hw, I40E_GLLAN_RCTL_0);
1402 
1403 	if (hw->revision_id == 0) {
1404 		/* As a work around clear PXE_MODE instead of setting it */
1405 		wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1406 	} else {
1407 		wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1408 	}
1409 }
1410 
1411 /**
1412  * i40e_led_is_mine - helper to find matching led
1413  * @hw: pointer to the hw struct
1414  * @idx: index into GPIO registers
1415  *
1416  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1417  */
1418 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1419 {
1420 	u32 gpio_val = 0;
1421 	u32 port;
1422 
1423 	if (!hw->func_caps.led[idx])
1424 		return 0;
1425 
1426 	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1427 	port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1428 		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1429 
1430 	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1431 	 * if it is not our port then ignore
1432 	 */
1433 	if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1434 	    (port != hw->port))
1435 		return 0;
1436 
1437 	return gpio_val;
1438 }
1439 
1440 #define I40E_COMBINED_ACTIVITY 0xA
1441 #define I40E_FILTER_ACTIVITY 0xE
1442 #define I40E_LINK_ACTIVITY 0xC
1443 #define I40E_MAC_ACTIVITY 0xD
1444 #define I40E_LED0 22
1445 
1446 /**
1447  * i40e_led_get - return current on/off mode
1448  * @hw: pointer to the hw struct
1449  *
1450  * The value returned is the 'mode' field as defined in the
1451  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1452  * values are variations of possible behaviors relating to
1453  * blink, link, and wire.
1454  **/
1455 u32 i40e_led_get(struct i40e_hw *hw)
1456 {
1457 	u32 current_mode = 0;
1458 	u32 mode = 0;
1459 	int i;
1460 
1461 	/* as per the documentation GPIO 22-29 are the LED
1462 	 * GPIO pins named LED0..LED7
1463 	 */
1464 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1465 		u32 gpio_val = i40e_led_is_mine(hw, i);
1466 
1467 		if (!gpio_val)
1468 			continue;
1469 
1470 		/* ignore gpio LED src mode entries related to the activity
1471 		 * LEDs
1472 		 */
1473 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1474 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1475 		switch (current_mode) {
1476 		case I40E_COMBINED_ACTIVITY:
1477 		case I40E_FILTER_ACTIVITY:
1478 		case I40E_MAC_ACTIVITY:
1479 			continue;
1480 		default:
1481 			break;
1482 		}
1483 
1484 		mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1485 			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1486 		break;
1487 	}
1488 
1489 	return mode;
1490 }
1491 
1492 /**
1493  * i40e_led_set - set new on/off mode
1494  * @hw: pointer to the hw struct
1495  * @mode: 0=off, 0xf=on (else see manual for mode details)
1496  * @blink: true if the LED should blink when on, false if steady
1497  *
1498  * if this function is used to turn on the blink it should
1499  * be used to disable the blink when restoring the original state.
1500  **/
1501 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1502 {
1503 	u32 current_mode = 0;
1504 	int i;
1505 
1506 	if (mode & 0xfffffff0)
1507 		hw_dbg(hw, "invalid mode passed in %X\n", mode);
1508 
1509 	/* as per the documentation GPIO 22-29 are the LED
1510 	 * GPIO pins named LED0..LED7
1511 	 */
1512 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1513 		u32 gpio_val = i40e_led_is_mine(hw, i);
1514 
1515 		if (!gpio_val)
1516 			continue;
1517 
1518 		/* ignore gpio LED src mode entries related to the activity
1519 		 * LEDs
1520 		 */
1521 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1522 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1523 		switch (current_mode) {
1524 		case I40E_COMBINED_ACTIVITY:
1525 		case I40E_FILTER_ACTIVITY:
1526 		case I40E_MAC_ACTIVITY:
1527 			continue;
1528 		default:
1529 			break;
1530 		}
1531 
1532 		gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1533 		/* this & is a bit of paranoia, but serves as a range check */
1534 		gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1535 			     I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1536 
1537 		if (mode == I40E_LINK_ACTIVITY)
1538 			blink = false;
1539 
1540 		if (blink)
1541 			gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1542 		else
1543 			gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1544 
1545 		wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1546 		break;
1547 	}
1548 }
1549 
1550 /* Admin command wrappers */
1551 
1552 /**
1553  * i40e_aq_get_phy_capabilities
1554  * @hw: pointer to the hw struct
1555  * @abilities: structure for PHY capabilities to be filled
1556  * @qualified_modules: report Qualified Modules
1557  * @report_init: report init capabilities (active are default)
1558  * @cmd_details: pointer to command details structure or NULL
1559  *
1560  * Returns the various PHY abilities supported on the Port.
1561  **/
1562 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1563 			bool qualified_modules, bool report_init,
1564 			struct i40e_aq_get_phy_abilities_resp *abilities,
1565 			struct i40e_asq_cmd_details *cmd_details)
1566 {
1567 	struct i40e_aq_desc desc;
1568 	i40e_status status;
1569 	u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1570 
1571 	if (!abilities)
1572 		return I40E_ERR_PARAM;
1573 
1574 	i40e_fill_default_direct_cmd_desc(&desc,
1575 					  i40e_aqc_opc_get_phy_abilities);
1576 
1577 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1578 	if (abilities_size > I40E_AQ_LARGE_BUF)
1579 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1580 
1581 	if (qualified_modules)
1582 		desc.params.external.param0 |=
1583 			cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1584 
1585 	if (report_init)
1586 		desc.params.external.param0 |=
1587 			cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1588 
1589 	status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1590 				       cmd_details);
1591 
1592 	if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1593 		status = I40E_ERR_UNKNOWN_PHY;
1594 
1595 	if (report_init) {
1596 		hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1597 		hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1598 	}
1599 
1600 	return status;
1601 }
1602 
1603 /**
1604  * i40e_aq_set_phy_config
1605  * @hw: pointer to the hw struct
1606  * @config: structure with PHY configuration to be set
1607  * @cmd_details: pointer to command details structure or NULL
1608  *
1609  * Set the various PHY configuration parameters
1610  * supported on the Port.One or more of the Set PHY config parameters may be
1611  * ignored in an MFP mode as the PF may not have the privilege to set some
1612  * of the PHY Config parameters. This status will be indicated by the
1613  * command response.
1614  **/
1615 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1616 				struct i40e_aq_set_phy_config *config,
1617 				struct i40e_asq_cmd_details *cmd_details)
1618 {
1619 	struct i40e_aq_desc desc;
1620 	struct i40e_aq_set_phy_config *cmd =
1621 			(struct i40e_aq_set_phy_config *)&desc.params.raw;
1622 	enum i40e_status_code status;
1623 
1624 	if (!config)
1625 		return I40E_ERR_PARAM;
1626 
1627 	i40e_fill_default_direct_cmd_desc(&desc,
1628 					  i40e_aqc_opc_set_phy_config);
1629 
1630 	*cmd = *config;
1631 
1632 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1633 
1634 	return status;
1635 }
1636 
1637 /**
1638  * i40e_set_fc
1639  * @hw: pointer to the hw struct
1640  *
1641  * Set the requested flow control mode using set_phy_config.
1642  **/
1643 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1644 				  bool atomic_restart)
1645 {
1646 	enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1647 	struct i40e_aq_get_phy_abilities_resp abilities;
1648 	struct i40e_aq_set_phy_config config;
1649 	enum i40e_status_code status;
1650 	u8 pause_mask = 0x0;
1651 
1652 	*aq_failures = 0x0;
1653 
1654 	switch (fc_mode) {
1655 	case I40E_FC_FULL:
1656 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1657 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1658 		break;
1659 	case I40E_FC_RX_PAUSE:
1660 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1661 		break;
1662 	case I40E_FC_TX_PAUSE:
1663 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1664 		break;
1665 	default:
1666 		break;
1667 	}
1668 
1669 	/* Get the current phy config */
1670 	status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1671 					      NULL);
1672 	if (status) {
1673 		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1674 		return status;
1675 	}
1676 
1677 	memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1678 	/* clear the old pause settings */
1679 	config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1680 			   ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1681 	/* set the new abilities */
1682 	config.abilities |= pause_mask;
1683 	/* If the abilities have changed, then set the new config */
1684 	if (config.abilities != abilities.abilities) {
1685 		/* Auto restart link so settings take effect */
1686 		if (atomic_restart)
1687 			config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1688 		/* Copy over all the old settings */
1689 		config.phy_type = abilities.phy_type;
1690 		config.phy_type_ext = abilities.phy_type_ext;
1691 		config.link_speed = abilities.link_speed;
1692 		config.eee_capability = abilities.eee_capability;
1693 		config.eeer = abilities.eeer_val;
1694 		config.low_power_ctrl = abilities.d3_lpan;
1695 		config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1696 				    I40E_AQ_PHY_FEC_CONFIG_MASK;
1697 		status = i40e_aq_set_phy_config(hw, &config, NULL);
1698 
1699 		if (status)
1700 			*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1701 	}
1702 	/* Update the link info */
1703 	status = i40e_update_link_info(hw);
1704 	if (status) {
1705 		/* Wait a little bit (on 40G cards it sometimes takes a really
1706 		 * long time for link to come back from the atomic reset)
1707 		 * and try once more
1708 		 */
1709 		msleep(1000);
1710 		status = i40e_update_link_info(hw);
1711 	}
1712 	if (status)
1713 		*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1714 
1715 	return status;
1716 }
1717 
1718 /**
1719  * i40e_aq_clear_pxe_mode
1720  * @hw: pointer to the hw struct
1721  * @cmd_details: pointer to command details structure or NULL
1722  *
1723  * Tell the firmware that the driver is taking over from PXE
1724  **/
1725 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1726 				struct i40e_asq_cmd_details *cmd_details)
1727 {
1728 	i40e_status status;
1729 	struct i40e_aq_desc desc;
1730 	struct i40e_aqc_clear_pxe *cmd =
1731 		(struct i40e_aqc_clear_pxe *)&desc.params.raw;
1732 
1733 	i40e_fill_default_direct_cmd_desc(&desc,
1734 					  i40e_aqc_opc_clear_pxe_mode);
1735 
1736 	cmd->rx_cnt = 0x2;
1737 
1738 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1739 
1740 	wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1741 
1742 	return status;
1743 }
1744 
1745 /**
1746  * i40e_aq_set_link_restart_an
1747  * @hw: pointer to the hw struct
1748  * @enable_link: if true: enable link, if false: disable link
1749  * @cmd_details: pointer to command details structure or NULL
1750  *
1751  * Sets up the link and restarts the Auto-Negotiation over the link.
1752  **/
1753 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1754 					bool enable_link,
1755 					struct i40e_asq_cmd_details *cmd_details)
1756 {
1757 	struct i40e_aq_desc desc;
1758 	struct i40e_aqc_set_link_restart_an *cmd =
1759 		(struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1760 	i40e_status status;
1761 
1762 	i40e_fill_default_direct_cmd_desc(&desc,
1763 					  i40e_aqc_opc_set_link_restart_an);
1764 
1765 	cmd->command = I40E_AQ_PHY_RESTART_AN;
1766 	if (enable_link)
1767 		cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1768 	else
1769 		cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1770 
1771 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1772 
1773 	return status;
1774 }
1775 
1776 /**
1777  * i40e_aq_get_link_info
1778  * @hw: pointer to the hw struct
1779  * @enable_lse: enable/disable LinkStatusEvent reporting
1780  * @link: pointer to link status structure - optional
1781  * @cmd_details: pointer to command details structure or NULL
1782  *
1783  * Returns the link status of the adapter.
1784  **/
1785 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1786 				bool enable_lse, struct i40e_link_status *link,
1787 				struct i40e_asq_cmd_details *cmd_details)
1788 {
1789 	struct i40e_aq_desc desc;
1790 	struct i40e_aqc_get_link_status *resp =
1791 		(struct i40e_aqc_get_link_status *)&desc.params.raw;
1792 	struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1793 	i40e_status status;
1794 	bool tx_pause, rx_pause;
1795 	u16 command_flags;
1796 
1797 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1798 
1799 	if (enable_lse)
1800 		command_flags = I40E_AQ_LSE_ENABLE;
1801 	else
1802 		command_flags = I40E_AQ_LSE_DISABLE;
1803 	resp->command_flags = cpu_to_le16(command_flags);
1804 
1805 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1806 
1807 	if (status)
1808 		goto aq_get_link_info_exit;
1809 
1810 	/* save off old link status information */
1811 	hw->phy.link_info_old = *hw_link_info;
1812 
1813 	/* update link status */
1814 	hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1815 	hw->phy.media_type = i40e_get_media_type(hw);
1816 	hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1817 	hw_link_info->link_info = resp->link_info;
1818 	hw_link_info->an_info = resp->an_info;
1819 	hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1820 						 I40E_AQ_CONFIG_FEC_RS_ENA);
1821 	hw_link_info->ext_info = resp->ext_info;
1822 	hw_link_info->loopback = resp->loopback;
1823 	hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1824 	hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1825 
1826 	/* update fc info */
1827 	tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1828 	rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1829 	if (tx_pause & rx_pause)
1830 		hw->fc.current_mode = I40E_FC_FULL;
1831 	else if (tx_pause)
1832 		hw->fc.current_mode = I40E_FC_TX_PAUSE;
1833 	else if (rx_pause)
1834 		hw->fc.current_mode = I40E_FC_RX_PAUSE;
1835 	else
1836 		hw->fc.current_mode = I40E_FC_NONE;
1837 
1838 	if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1839 		hw_link_info->crc_enable = true;
1840 	else
1841 		hw_link_info->crc_enable = false;
1842 
1843 	if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1844 		hw_link_info->lse_enable = true;
1845 	else
1846 		hw_link_info->lse_enable = false;
1847 
1848 	if ((hw->mac.type == I40E_MAC_XL710) &&
1849 	    (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1850 	     hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1851 		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1852 
1853 	/* save link status information */
1854 	if (link)
1855 		*link = *hw_link_info;
1856 
1857 	/* flag cleared so helper functions don't call AQ again */
1858 	hw->phy.get_link_info = false;
1859 
1860 aq_get_link_info_exit:
1861 	return status;
1862 }
1863 
1864 /**
1865  * i40e_aq_set_phy_int_mask
1866  * @hw: pointer to the hw struct
1867  * @mask: interrupt mask to be set
1868  * @cmd_details: pointer to command details structure or NULL
1869  *
1870  * Set link interrupt mask.
1871  **/
1872 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1873 				     u16 mask,
1874 				     struct i40e_asq_cmd_details *cmd_details)
1875 {
1876 	struct i40e_aq_desc desc;
1877 	struct i40e_aqc_set_phy_int_mask *cmd =
1878 		(struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1879 	i40e_status status;
1880 
1881 	i40e_fill_default_direct_cmd_desc(&desc,
1882 					  i40e_aqc_opc_set_phy_int_mask);
1883 
1884 	cmd->event_mask = cpu_to_le16(mask);
1885 
1886 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1887 
1888 	return status;
1889 }
1890 
1891 /**
1892  * i40e_aq_set_phy_debug
1893  * @hw: pointer to the hw struct
1894  * @cmd_flags: debug command flags
1895  * @cmd_details: pointer to command details structure or NULL
1896  *
1897  * Reset the external PHY.
1898  **/
1899 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1900 				  struct i40e_asq_cmd_details *cmd_details)
1901 {
1902 	struct i40e_aq_desc desc;
1903 	struct i40e_aqc_set_phy_debug *cmd =
1904 		(struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1905 	i40e_status status;
1906 
1907 	i40e_fill_default_direct_cmd_desc(&desc,
1908 					  i40e_aqc_opc_set_phy_debug);
1909 
1910 	cmd->command_flags = cmd_flags;
1911 
1912 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913 
1914 	return status;
1915 }
1916 
1917 /**
1918  * i40e_aq_add_vsi
1919  * @hw: pointer to the hw struct
1920  * @vsi_ctx: pointer to a vsi context struct
1921  * @cmd_details: pointer to command details structure or NULL
1922  *
1923  * Add a VSI context to the hardware.
1924 **/
1925 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1926 				struct i40e_vsi_context *vsi_ctx,
1927 				struct i40e_asq_cmd_details *cmd_details)
1928 {
1929 	struct i40e_aq_desc desc;
1930 	struct i40e_aqc_add_get_update_vsi *cmd =
1931 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1932 	struct i40e_aqc_add_get_update_vsi_completion *resp =
1933 		(struct i40e_aqc_add_get_update_vsi_completion *)
1934 		&desc.params.raw;
1935 	i40e_status status;
1936 
1937 	i40e_fill_default_direct_cmd_desc(&desc,
1938 					  i40e_aqc_opc_add_vsi);
1939 
1940 	cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1941 	cmd->connection_type = vsi_ctx->connection_type;
1942 	cmd->vf_id = vsi_ctx->vf_num;
1943 	cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1944 
1945 	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1946 
1947 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1948 				    sizeof(vsi_ctx->info), cmd_details);
1949 
1950 	if (status)
1951 		goto aq_add_vsi_exit;
1952 
1953 	vsi_ctx->seid = le16_to_cpu(resp->seid);
1954 	vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1955 	vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1956 	vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1957 
1958 aq_add_vsi_exit:
1959 	return status;
1960 }
1961 
1962 /**
1963  * i40e_aq_set_default_vsi
1964  * @hw: pointer to the hw struct
1965  * @seid: vsi number
1966  * @cmd_details: pointer to command details structure or NULL
1967  **/
1968 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1969 				    u16 seid,
1970 				    struct i40e_asq_cmd_details *cmd_details)
1971 {
1972 	struct i40e_aq_desc desc;
1973 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1974 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
1975 		&desc.params.raw;
1976 	i40e_status status;
1977 
1978 	i40e_fill_default_direct_cmd_desc(&desc,
1979 					  i40e_aqc_opc_set_vsi_promiscuous_modes);
1980 
1981 	cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1982 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1983 	cmd->seid = cpu_to_le16(seid);
1984 
1985 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1986 
1987 	return status;
1988 }
1989 
1990 /**
1991  * i40e_aq_clear_default_vsi
1992  * @hw: pointer to the hw struct
1993  * @seid: vsi number
1994  * @cmd_details: pointer to command details structure or NULL
1995  **/
1996 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1997 				      u16 seid,
1998 				      struct i40e_asq_cmd_details *cmd_details)
1999 {
2000 	struct i40e_aq_desc desc;
2001 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2002 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2003 		&desc.params.raw;
2004 	i40e_status status;
2005 
2006 	i40e_fill_default_direct_cmd_desc(&desc,
2007 					  i40e_aqc_opc_set_vsi_promiscuous_modes);
2008 
2009 	cmd->promiscuous_flags = cpu_to_le16(0);
2010 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2011 	cmd->seid = cpu_to_le16(seid);
2012 
2013 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2014 
2015 	return status;
2016 }
2017 
2018 /**
2019  * i40e_aq_set_vsi_unicast_promiscuous
2020  * @hw: pointer to the hw struct
2021  * @seid: vsi number
2022  * @set: set unicast promiscuous enable/disable
2023  * @cmd_details: pointer to command details structure or NULL
2024  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2025  **/
2026 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2027 				u16 seid, bool set,
2028 				struct i40e_asq_cmd_details *cmd_details,
2029 				bool rx_only_promisc)
2030 {
2031 	struct i40e_aq_desc desc;
2032 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2033 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2034 	i40e_status status;
2035 	u16 flags = 0;
2036 
2037 	i40e_fill_default_direct_cmd_desc(&desc,
2038 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2039 
2040 	if (set) {
2041 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2042 		if (rx_only_promisc &&
2043 		    (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2044 		     (hw->aq.api_maj_ver > 1)))
2045 			flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2046 	}
2047 
2048 	cmd->promiscuous_flags = cpu_to_le16(flags);
2049 
2050 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2051 	if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2052 	    (hw->aq.api_maj_ver > 1))
2053 		cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2054 
2055 	cmd->seid = cpu_to_le16(seid);
2056 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2057 
2058 	return status;
2059 }
2060 
2061 /**
2062  * i40e_aq_set_vsi_multicast_promiscuous
2063  * @hw: pointer to the hw struct
2064  * @seid: vsi number
2065  * @set: set multicast promiscuous enable/disable
2066  * @cmd_details: pointer to command details structure or NULL
2067  **/
2068 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2069 				u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2070 {
2071 	struct i40e_aq_desc desc;
2072 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2073 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2074 	i40e_status status;
2075 	u16 flags = 0;
2076 
2077 	i40e_fill_default_direct_cmd_desc(&desc,
2078 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2079 
2080 	if (set)
2081 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2082 
2083 	cmd->promiscuous_flags = cpu_to_le16(flags);
2084 
2085 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2086 
2087 	cmd->seid = cpu_to_le16(seid);
2088 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089 
2090 	return status;
2091 }
2092 
2093 /**
2094  * i40e_aq_set_vsi_mc_promisc_on_vlan
2095  * @hw: pointer to the hw struct
2096  * @seid: vsi number
2097  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2098  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2099  * @cmd_details: pointer to command details structure or NULL
2100  **/
2101 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2102 							 u16 seid, bool enable,
2103 							 u16 vid,
2104 				struct i40e_asq_cmd_details *cmd_details)
2105 {
2106 	struct i40e_aq_desc desc;
2107 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2108 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2109 	enum i40e_status_code status;
2110 	u16 flags = 0;
2111 
2112 	i40e_fill_default_direct_cmd_desc(&desc,
2113 					  i40e_aqc_opc_set_vsi_promiscuous_modes);
2114 
2115 	if (enable)
2116 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2117 
2118 	cmd->promiscuous_flags = cpu_to_le16(flags);
2119 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2120 	cmd->seid = cpu_to_le16(seid);
2121 	cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2122 
2123 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124 
2125 	return status;
2126 }
2127 
2128 /**
2129  * i40e_aq_set_vsi_uc_promisc_on_vlan
2130  * @hw: pointer to the hw struct
2131  * @seid: vsi number
2132  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2133  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2134  * @cmd_details: pointer to command details structure or NULL
2135  **/
2136 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2137 							 u16 seid, bool enable,
2138 							 u16 vid,
2139 				struct i40e_asq_cmd_details *cmd_details)
2140 {
2141 	struct i40e_aq_desc desc;
2142 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2143 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2144 	enum i40e_status_code status;
2145 	u16 flags = 0;
2146 
2147 	i40e_fill_default_direct_cmd_desc(&desc,
2148 					  i40e_aqc_opc_set_vsi_promiscuous_modes);
2149 
2150 	if (enable)
2151 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2152 
2153 	cmd->promiscuous_flags = cpu_to_le16(flags);
2154 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2155 	cmd->seid = cpu_to_le16(seid);
2156 	cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2157 
2158 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2159 
2160 	return status;
2161 }
2162 
2163 /**
2164  * i40e_aq_set_vsi_bc_promisc_on_vlan
2165  * @hw: pointer to the hw struct
2166  * @seid: vsi number
2167  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2168  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2169  * @cmd_details: pointer to command details structure or NULL
2170  **/
2171 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2172 				u16 seid, bool enable, u16 vid,
2173 				struct i40e_asq_cmd_details *cmd_details)
2174 {
2175 	struct i40e_aq_desc desc;
2176 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2177 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2178 	i40e_status status;
2179 	u16 flags = 0;
2180 
2181 	i40e_fill_default_direct_cmd_desc(&desc,
2182 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2183 
2184 	if (enable)
2185 		flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2186 
2187 	cmd->promiscuous_flags = cpu_to_le16(flags);
2188 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2189 	cmd->seid = cpu_to_le16(seid);
2190 	cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2191 
2192 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2193 
2194 	return status;
2195 }
2196 
2197 /**
2198  * i40e_aq_set_vsi_broadcast
2199  * @hw: pointer to the hw struct
2200  * @seid: vsi number
2201  * @set_filter: true to set filter, false to clear filter
2202  * @cmd_details: pointer to command details structure or NULL
2203  *
2204  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2205  **/
2206 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2207 				u16 seid, bool set_filter,
2208 				struct i40e_asq_cmd_details *cmd_details)
2209 {
2210 	struct i40e_aq_desc desc;
2211 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2212 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2213 	i40e_status status;
2214 
2215 	i40e_fill_default_direct_cmd_desc(&desc,
2216 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2217 
2218 	if (set_filter)
2219 		cmd->promiscuous_flags
2220 			    |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2221 	else
2222 		cmd->promiscuous_flags
2223 			    &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2224 
2225 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2226 	cmd->seid = cpu_to_le16(seid);
2227 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2228 
2229 	return status;
2230 }
2231 
2232 /**
2233  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2234  * @hw: pointer to the hw struct
2235  * @seid: vsi number
2236  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2237  * @cmd_details: pointer to command details structure or NULL
2238  **/
2239 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2240 				       u16 seid, bool enable,
2241 				       struct i40e_asq_cmd_details *cmd_details)
2242 {
2243 	struct i40e_aq_desc desc;
2244 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2245 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2246 	i40e_status status;
2247 	u16 flags = 0;
2248 
2249 	i40e_fill_default_direct_cmd_desc(&desc,
2250 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2251 	if (enable)
2252 		flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2253 
2254 	cmd->promiscuous_flags = cpu_to_le16(flags);
2255 	cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2256 	cmd->seid = cpu_to_le16(seid);
2257 
2258 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2259 
2260 	return status;
2261 }
2262 
2263 /**
2264  * i40e_get_vsi_params - get VSI configuration info
2265  * @hw: pointer to the hw struct
2266  * @vsi_ctx: pointer to a vsi context struct
2267  * @cmd_details: pointer to command details structure or NULL
2268  **/
2269 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2270 				struct i40e_vsi_context *vsi_ctx,
2271 				struct i40e_asq_cmd_details *cmd_details)
2272 {
2273 	struct i40e_aq_desc desc;
2274 	struct i40e_aqc_add_get_update_vsi *cmd =
2275 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2276 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2277 		(struct i40e_aqc_add_get_update_vsi_completion *)
2278 		&desc.params.raw;
2279 	i40e_status status;
2280 
2281 	i40e_fill_default_direct_cmd_desc(&desc,
2282 					  i40e_aqc_opc_get_vsi_parameters);
2283 
2284 	cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2285 
2286 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2287 
2288 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2289 				    sizeof(vsi_ctx->info), NULL);
2290 
2291 	if (status)
2292 		goto aq_get_vsi_params_exit;
2293 
2294 	vsi_ctx->seid = le16_to_cpu(resp->seid);
2295 	vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2296 	vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2297 	vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2298 
2299 aq_get_vsi_params_exit:
2300 	return status;
2301 }
2302 
2303 /**
2304  * i40e_aq_update_vsi_params
2305  * @hw: pointer to the hw struct
2306  * @vsi_ctx: pointer to a vsi context struct
2307  * @cmd_details: pointer to command details structure or NULL
2308  *
2309  * Update a VSI context.
2310  **/
2311 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2312 				struct i40e_vsi_context *vsi_ctx,
2313 				struct i40e_asq_cmd_details *cmd_details)
2314 {
2315 	struct i40e_aq_desc desc;
2316 	struct i40e_aqc_add_get_update_vsi *cmd =
2317 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2318 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2319 		(struct i40e_aqc_add_get_update_vsi_completion *)
2320 		&desc.params.raw;
2321 	i40e_status status;
2322 
2323 	i40e_fill_default_direct_cmd_desc(&desc,
2324 					  i40e_aqc_opc_update_vsi_parameters);
2325 	cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2326 
2327 	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2328 
2329 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2330 				    sizeof(vsi_ctx->info), cmd_details);
2331 
2332 	vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2333 	vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2334 
2335 	return status;
2336 }
2337 
2338 /**
2339  * i40e_aq_get_switch_config
2340  * @hw: pointer to the hardware structure
2341  * @buf: pointer to the result buffer
2342  * @buf_size: length of input buffer
2343  * @start_seid: seid to start for the report, 0 == beginning
2344  * @cmd_details: pointer to command details structure or NULL
2345  *
2346  * Fill the buf with switch configuration returned from AdminQ command
2347  **/
2348 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2349 				struct i40e_aqc_get_switch_config_resp *buf,
2350 				u16 buf_size, u16 *start_seid,
2351 				struct i40e_asq_cmd_details *cmd_details)
2352 {
2353 	struct i40e_aq_desc desc;
2354 	struct i40e_aqc_switch_seid *scfg =
2355 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
2356 	i40e_status status;
2357 
2358 	i40e_fill_default_direct_cmd_desc(&desc,
2359 					  i40e_aqc_opc_get_switch_config);
2360 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2361 	if (buf_size > I40E_AQ_LARGE_BUF)
2362 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2363 	scfg->seid = cpu_to_le16(*start_seid);
2364 
2365 	status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2366 	*start_seid = le16_to_cpu(scfg->seid);
2367 
2368 	return status;
2369 }
2370 
2371 /**
2372  * i40e_aq_set_switch_config
2373  * @hw: pointer to the hardware structure
2374  * @flags: bit flag values to set
2375  * @valid_flags: which bit flags to set
2376  * @cmd_details: pointer to command details structure or NULL
2377  *
2378  * Set switch configuration bits
2379  **/
2380 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2381 						u16 flags,
2382 						u16 valid_flags,
2383 				struct i40e_asq_cmd_details *cmd_details)
2384 {
2385 	struct i40e_aq_desc desc;
2386 	struct i40e_aqc_set_switch_config *scfg =
2387 		(struct i40e_aqc_set_switch_config *)&desc.params.raw;
2388 	enum i40e_status_code status;
2389 
2390 	i40e_fill_default_direct_cmd_desc(&desc,
2391 					  i40e_aqc_opc_set_switch_config);
2392 	scfg->flags = cpu_to_le16(flags);
2393 	scfg->valid_flags = cpu_to_le16(valid_flags);
2394 
2395 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2396 
2397 	return status;
2398 }
2399 
2400 /**
2401  * i40e_aq_get_firmware_version
2402  * @hw: pointer to the hw struct
2403  * @fw_major_version: firmware major version
2404  * @fw_minor_version: firmware minor version
2405  * @fw_build: firmware build number
2406  * @api_major_version: major queue version
2407  * @api_minor_version: minor queue version
2408  * @cmd_details: pointer to command details structure or NULL
2409  *
2410  * Get the firmware version from the admin queue commands
2411  **/
2412 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2413 				u16 *fw_major_version, u16 *fw_minor_version,
2414 				u32 *fw_build,
2415 				u16 *api_major_version, u16 *api_minor_version,
2416 				struct i40e_asq_cmd_details *cmd_details)
2417 {
2418 	struct i40e_aq_desc desc;
2419 	struct i40e_aqc_get_version *resp =
2420 		(struct i40e_aqc_get_version *)&desc.params.raw;
2421 	i40e_status status;
2422 
2423 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2424 
2425 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2426 
2427 	if (!status) {
2428 		if (fw_major_version)
2429 			*fw_major_version = le16_to_cpu(resp->fw_major);
2430 		if (fw_minor_version)
2431 			*fw_minor_version = le16_to_cpu(resp->fw_minor);
2432 		if (fw_build)
2433 			*fw_build = le32_to_cpu(resp->fw_build);
2434 		if (api_major_version)
2435 			*api_major_version = le16_to_cpu(resp->api_major);
2436 		if (api_minor_version)
2437 			*api_minor_version = le16_to_cpu(resp->api_minor);
2438 	}
2439 
2440 	return status;
2441 }
2442 
2443 /**
2444  * i40e_aq_send_driver_version
2445  * @hw: pointer to the hw struct
2446  * @dv: driver's major, minor version
2447  * @cmd_details: pointer to command details structure or NULL
2448  *
2449  * Send the driver version to the firmware
2450  **/
2451 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2452 				struct i40e_driver_version *dv,
2453 				struct i40e_asq_cmd_details *cmd_details)
2454 {
2455 	struct i40e_aq_desc desc;
2456 	struct i40e_aqc_driver_version *cmd =
2457 		(struct i40e_aqc_driver_version *)&desc.params.raw;
2458 	i40e_status status;
2459 	u16 len;
2460 
2461 	if (dv == NULL)
2462 		return I40E_ERR_PARAM;
2463 
2464 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2465 
2466 	desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2467 	cmd->driver_major_ver = dv->major_version;
2468 	cmd->driver_minor_ver = dv->minor_version;
2469 	cmd->driver_build_ver = dv->build_version;
2470 	cmd->driver_subbuild_ver = dv->subbuild_version;
2471 
2472 	len = 0;
2473 	while (len < sizeof(dv->driver_string) &&
2474 	       (dv->driver_string[len] < 0x80) &&
2475 	       dv->driver_string[len])
2476 		len++;
2477 	status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2478 				       len, cmd_details);
2479 
2480 	return status;
2481 }
2482 
2483 /**
2484  * i40e_get_link_status - get status of the HW network link
2485  * @hw: pointer to the hw struct
2486  * @link_up: pointer to bool (true/false = linkup/linkdown)
2487  *
2488  * Variable link_up true if link is up, false if link is down.
2489  * The variable link_up is invalid if returned value of status != 0
2490  *
2491  * Side effect: LinkStatusEvent reporting becomes enabled
2492  **/
2493 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2494 {
2495 	i40e_status status = 0;
2496 
2497 	if (hw->phy.get_link_info) {
2498 		status = i40e_update_link_info(hw);
2499 
2500 		if (status)
2501 			i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2502 				   status);
2503 	}
2504 
2505 	*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2506 
2507 	return status;
2508 }
2509 
2510 /**
2511  * i40e_updatelink_status - update status of the HW network link
2512  * @hw: pointer to the hw struct
2513  **/
2514 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2515 {
2516 	struct i40e_aq_get_phy_abilities_resp abilities;
2517 	i40e_status status = 0;
2518 
2519 	status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2520 	if (status)
2521 		return status;
2522 
2523 	/* extra checking needed to ensure link info to user is timely */
2524 	if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2525 	    ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2526 	     !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2527 		status = i40e_aq_get_phy_capabilities(hw, false, false,
2528 						      &abilities, NULL);
2529 		if (status)
2530 			return status;
2531 
2532 		memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2533 		       sizeof(hw->phy.link_info.module_type));
2534 	}
2535 
2536 	return status;
2537 }
2538 
2539 /**
2540  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2541  * @hw: pointer to the hw struct
2542  * @uplink_seid: the MAC or other gizmo SEID
2543  * @downlink_seid: the VSI SEID
2544  * @enabled_tc: bitmap of TCs to be enabled
2545  * @default_port: true for default port VSI, false for control port
2546  * @veb_seid: pointer to where to put the resulting VEB SEID
2547  * @enable_stats: true to turn on VEB stats
2548  * @cmd_details: pointer to command details structure or NULL
2549  *
2550  * This asks the FW to add a VEB between the uplink and downlink
2551  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2552  **/
2553 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2554 				u16 downlink_seid, u8 enabled_tc,
2555 				bool default_port, u16 *veb_seid,
2556 				bool enable_stats,
2557 				struct i40e_asq_cmd_details *cmd_details)
2558 {
2559 	struct i40e_aq_desc desc;
2560 	struct i40e_aqc_add_veb *cmd =
2561 		(struct i40e_aqc_add_veb *)&desc.params.raw;
2562 	struct i40e_aqc_add_veb_completion *resp =
2563 		(struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2564 	i40e_status status;
2565 	u16 veb_flags = 0;
2566 
2567 	/* SEIDs need to either both be set or both be 0 for floating VEB */
2568 	if (!!uplink_seid != !!downlink_seid)
2569 		return I40E_ERR_PARAM;
2570 
2571 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2572 
2573 	cmd->uplink_seid = cpu_to_le16(uplink_seid);
2574 	cmd->downlink_seid = cpu_to_le16(downlink_seid);
2575 	cmd->enable_tcs = enabled_tc;
2576 	if (!uplink_seid)
2577 		veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2578 	if (default_port)
2579 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2580 	else
2581 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2582 
2583 	/* reverse logic here: set the bitflag to disable the stats */
2584 	if (!enable_stats)
2585 		veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2586 
2587 	cmd->veb_flags = cpu_to_le16(veb_flags);
2588 
2589 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2590 
2591 	if (!status && veb_seid)
2592 		*veb_seid = le16_to_cpu(resp->veb_seid);
2593 
2594 	return status;
2595 }
2596 
2597 /**
2598  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2599  * @hw: pointer to the hw struct
2600  * @veb_seid: the SEID of the VEB to query
2601  * @switch_id: the uplink switch id
2602  * @floating: set to true if the VEB is floating
2603  * @statistic_index: index of the stats counter block for this VEB
2604  * @vebs_used: number of VEB's used by function
2605  * @vebs_free: total VEB's not reserved by any function
2606  * @cmd_details: pointer to command details structure or NULL
2607  *
2608  * This retrieves the parameters for a particular VEB, specified by
2609  * uplink_seid, and returns them to the caller.
2610  **/
2611 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2612 				u16 veb_seid, u16 *switch_id,
2613 				bool *floating, u16 *statistic_index,
2614 				u16 *vebs_used, u16 *vebs_free,
2615 				struct i40e_asq_cmd_details *cmd_details)
2616 {
2617 	struct i40e_aq_desc desc;
2618 	struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2619 		(struct i40e_aqc_get_veb_parameters_completion *)
2620 		&desc.params.raw;
2621 	i40e_status status;
2622 
2623 	if (veb_seid == 0)
2624 		return I40E_ERR_PARAM;
2625 
2626 	i40e_fill_default_direct_cmd_desc(&desc,
2627 					  i40e_aqc_opc_get_veb_parameters);
2628 	cmd_resp->seid = cpu_to_le16(veb_seid);
2629 
2630 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2631 	if (status)
2632 		goto get_veb_exit;
2633 
2634 	if (switch_id)
2635 		*switch_id = le16_to_cpu(cmd_resp->switch_id);
2636 	if (statistic_index)
2637 		*statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2638 	if (vebs_used)
2639 		*vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2640 	if (vebs_free)
2641 		*vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2642 	if (floating) {
2643 		u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2644 
2645 		if (flags & I40E_AQC_ADD_VEB_FLOATING)
2646 			*floating = true;
2647 		else
2648 			*floating = false;
2649 	}
2650 
2651 get_veb_exit:
2652 	return status;
2653 }
2654 
2655 /**
2656  * i40e_aq_add_macvlan
2657  * @hw: pointer to the hw struct
2658  * @seid: VSI for the mac address
2659  * @mv_list: list of macvlans to be added
2660  * @count: length of the list
2661  * @cmd_details: pointer to command details structure or NULL
2662  *
2663  * Add MAC/VLAN addresses to the HW filtering
2664  **/
2665 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2666 			struct i40e_aqc_add_macvlan_element_data *mv_list,
2667 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2668 {
2669 	struct i40e_aq_desc desc;
2670 	struct i40e_aqc_macvlan *cmd =
2671 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2672 	i40e_status status;
2673 	u16 buf_size;
2674 	int i;
2675 
2676 	if (count == 0 || !mv_list || !hw)
2677 		return I40E_ERR_PARAM;
2678 
2679 	buf_size = count * sizeof(*mv_list);
2680 
2681 	/* prep the rest of the request */
2682 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2683 	cmd->num_addresses = cpu_to_le16(count);
2684 	cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2685 	cmd->seid[1] = 0;
2686 	cmd->seid[2] = 0;
2687 
2688 	for (i = 0; i < count; i++)
2689 		if (is_multicast_ether_addr(mv_list[i].mac_addr))
2690 			mv_list[i].flags |=
2691 			       cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2692 
2693 	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2694 	if (buf_size > I40E_AQ_LARGE_BUF)
2695 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2696 
2697 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2698 				       cmd_details);
2699 
2700 	return status;
2701 }
2702 
2703 /**
2704  * i40e_aq_remove_macvlan
2705  * @hw: pointer to the hw struct
2706  * @seid: VSI for the mac address
2707  * @mv_list: list of macvlans to be removed
2708  * @count: length of the list
2709  * @cmd_details: pointer to command details structure or NULL
2710  *
2711  * Remove MAC/VLAN addresses from the HW filtering
2712  **/
2713 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2714 			struct i40e_aqc_remove_macvlan_element_data *mv_list,
2715 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2716 {
2717 	struct i40e_aq_desc desc;
2718 	struct i40e_aqc_macvlan *cmd =
2719 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2720 	i40e_status status;
2721 	u16 buf_size;
2722 
2723 	if (count == 0 || !mv_list || !hw)
2724 		return I40E_ERR_PARAM;
2725 
2726 	buf_size = count * sizeof(*mv_list);
2727 
2728 	/* prep the rest of the request */
2729 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2730 	cmd->num_addresses = cpu_to_le16(count);
2731 	cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2732 	cmd->seid[1] = 0;
2733 	cmd->seid[2] = 0;
2734 
2735 	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2736 	if (buf_size > I40E_AQ_LARGE_BUF)
2737 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2738 
2739 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2740 				       cmd_details);
2741 
2742 	return status;
2743 }
2744 
2745 /**
2746  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2747  * @hw: pointer to the hw struct
2748  * @opcode: AQ opcode for add or delete mirror rule
2749  * @sw_seid: Switch SEID (to which rule refers)
2750  * @rule_type: Rule Type (ingress/egress/VLAN)
2751  * @id: Destination VSI SEID or Rule ID
2752  * @count: length of the list
2753  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2754  * @cmd_details: pointer to command details structure or NULL
2755  * @rule_id: Rule ID returned from FW
2756  * @rule_used: Number of rules used in internal switch
2757  * @rule_free: Number of rules free in internal switch
2758  *
2759  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2760  * VEBs/VEPA elements only
2761  **/
2762 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2763 				u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2764 				u16 count, __le16 *mr_list,
2765 				struct i40e_asq_cmd_details *cmd_details,
2766 				u16 *rule_id, u16 *rules_used, u16 *rules_free)
2767 {
2768 	struct i40e_aq_desc desc;
2769 	struct i40e_aqc_add_delete_mirror_rule *cmd =
2770 		(struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2771 	struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2772 	(struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2773 	i40e_status status;
2774 	u16 buf_size;
2775 
2776 	buf_size = count * sizeof(*mr_list);
2777 
2778 	/* prep the rest of the request */
2779 	i40e_fill_default_direct_cmd_desc(&desc, opcode);
2780 	cmd->seid = cpu_to_le16(sw_seid);
2781 	cmd->rule_type = cpu_to_le16(rule_type &
2782 				     I40E_AQC_MIRROR_RULE_TYPE_MASK);
2783 	cmd->num_entries = cpu_to_le16(count);
2784 	/* Dest VSI for add, rule_id for delete */
2785 	cmd->destination = cpu_to_le16(id);
2786 	if (mr_list) {
2787 		desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2788 						I40E_AQ_FLAG_RD));
2789 		if (buf_size > I40E_AQ_LARGE_BUF)
2790 			desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2791 	}
2792 
2793 	status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2794 				       cmd_details);
2795 	if (!status ||
2796 	    hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2797 		if (rule_id)
2798 			*rule_id = le16_to_cpu(resp->rule_id);
2799 		if (rules_used)
2800 			*rules_used = le16_to_cpu(resp->mirror_rules_used);
2801 		if (rules_free)
2802 			*rules_free = le16_to_cpu(resp->mirror_rules_free);
2803 	}
2804 	return status;
2805 }
2806 
2807 /**
2808  * i40e_aq_add_mirrorrule - add a mirror rule
2809  * @hw: pointer to the hw struct
2810  * @sw_seid: Switch SEID (to which rule refers)
2811  * @rule_type: Rule Type (ingress/egress/VLAN)
2812  * @dest_vsi: SEID of VSI to which packets will be mirrored
2813  * @count: length of the list
2814  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2815  * @cmd_details: pointer to command details structure or NULL
2816  * @rule_id: Rule ID returned from FW
2817  * @rule_used: Number of rules used in internal switch
2818  * @rule_free: Number of rules free in internal switch
2819  *
2820  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2821  **/
2822 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2823 			u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2824 			struct i40e_asq_cmd_details *cmd_details,
2825 			u16 *rule_id, u16 *rules_used, u16 *rules_free)
2826 {
2827 	if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2828 	    rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2829 		if (count == 0 || !mr_list)
2830 			return I40E_ERR_PARAM;
2831 	}
2832 
2833 	return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2834 				  rule_type, dest_vsi, count, mr_list,
2835 				  cmd_details, rule_id, rules_used, rules_free);
2836 }
2837 
2838 /**
2839  * i40e_aq_delete_mirrorrule - delete a mirror rule
2840  * @hw: pointer to the hw struct
2841  * @sw_seid: Switch SEID (to which rule refers)
2842  * @rule_type: Rule Type (ingress/egress/VLAN)
2843  * @count: length of the list
2844  * @rule_id: Rule ID that is returned in the receive desc as part of
2845  *		add_mirrorrule.
2846  * @mr_list: list of mirrored VLAN IDs to be removed
2847  * @cmd_details: pointer to command details structure or NULL
2848  * @rule_used: Number of rules used in internal switch
2849  * @rule_free: Number of rules free in internal switch
2850  *
2851  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2852  **/
2853 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2854 			u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2855 			struct i40e_asq_cmd_details *cmd_details,
2856 			u16 *rules_used, u16 *rules_free)
2857 {
2858 	/* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2859 	if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2860 		/* count and mr_list shall be valid for rule_type INGRESS VLAN
2861 		 * mirroring. For other rule_type, count and rule_type should
2862 		 * not matter.
2863 		 */
2864 		if (count == 0 || !mr_list)
2865 			return I40E_ERR_PARAM;
2866 	}
2867 
2868 	return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2869 				  rule_type, rule_id, count, mr_list,
2870 				  cmd_details, NULL, rules_used, rules_free);
2871 }
2872 
2873 /**
2874  * i40e_aq_send_msg_to_vf
2875  * @hw: pointer to the hardware structure
2876  * @vfid: VF id to send msg
2877  * @v_opcode: opcodes for VF-PF communication
2878  * @v_retval: return error code
2879  * @msg: pointer to the msg buffer
2880  * @msglen: msg length
2881  * @cmd_details: pointer to command details
2882  *
2883  * send msg to vf
2884  **/
2885 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2886 				u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2887 				struct i40e_asq_cmd_details *cmd_details)
2888 {
2889 	struct i40e_aq_desc desc;
2890 	struct i40e_aqc_pf_vf_message *cmd =
2891 		(struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2892 	i40e_status status;
2893 
2894 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2895 	cmd->id = cpu_to_le32(vfid);
2896 	desc.cookie_high = cpu_to_le32(v_opcode);
2897 	desc.cookie_low = cpu_to_le32(v_retval);
2898 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2899 	if (msglen) {
2900 		desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2901 						I40E_AQ_FLAG_RD));
2902 		if (msglen > I40E_AQ_LARGE_BUF)
2903 			desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2904 		desc.datalen = cpu_to_le16(msglen);
2905 	}
2906 	status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2907 
2908 	return status;
2909 }
2910 
2911 /**
2912  * i40e_aq_debug_read_register
2913  * @hw: pointer to the hw struct
2914  * @reg_addr: register address
2915  * @reg_val: register value
2916  * @cmd_details: pointer to command details structure or NULL
2917  *
2918  * Read the register using the admin queue commands
2919  **/
2920 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2921 				u32 reg_addr, u64 *reg_val,
2922 				struct i40e_asq_cmd_details *cmd_details)
2923 {
2924 	struct i40e_aq_desc desc;
2925 	struct i40e_aqc_debug_reg_read_write *cmd_resp =
2926 		(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2927 	i40e_status status;
2928 
2929 	if (reg_val == NULL)
2930 		return I40E_ERR_PARAM;
2931 
2932 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2933 
2934 	cmd_resp->address = cpu_to_le32(reg_addr);
2935 
2936 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2937 
2938 	if (!status) {
2939 		*reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2940 			   (u64)le32_to_cpu(cmd_resp->value_low);
2941 	}
2942 
2943 	return status;
2944 }
2945 
2946 /**
2947  * i40e_aq_debug_write_register
2948  * @hw: pointer to the hw struct
2949  * @reg_addr: register address
2950  * @reg_val: register value
2951  * @cmd_details: pointer to command details structure or NULL
2952  *
2953  * Write to a register using the admin queue commands
2954  **/
2955 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2956 					u32 reg_addr, u64 reg_val,
2957 					struct i40e_asq_cmd_details *cmd_details)
2958 {
2959 	struct i40e_aq_desc desc;
2960 	struct i40e_aqc_debug_reg_read_write *cmd =
2961 		(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2962 	i40e_status status;
2963 
2964 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2965 
2966 	cmd->address = cpu_to_le32(reg_addr);
2967 	cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2968 	cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2969 
2970 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2971 
2972 	return status;
2973 }
2974 
2975 /**
2976  * i40e_aq_request_resource
2977  * @hw: pointer to the hw struct
2978  * @resource: resource id
2979  * @access: access type
2980  * @sdp_number: resource number
2981  * @timeout: the maximum time in ms that the driver may hold the resource
2982  * @cmd_details: pointer to command details structure or NULL
2983  *
2984  * requests common resource using the admin queue commands
2985  **/
2986 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2987 				enum i40e_aq_resources_ids resource,
2988 				enum i40e_aq_resource_access_type access,
2989 				u8 sdp_number, u64 *timeout,
2990 				struct i40e_asq_cmd_details *cmd_details)
2991 {
2992 	struct i40e_aq_desc desc;
2993 	struct i40e_aqc_request_resource *cmd_resp =
2994 		(struct i40e_aqc_request_resource *)&desc.params.raw;
2995 	i40e_status status;
2996 
2997 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2998 
2999 	cmd_resp->resource_id = cpu_to_le16(resource);
3000 	cmd_resp->access_type = cpu_to_le16(access);
3001 	cmd_resp->resource_number = cpu_to_le32(sdp_number);
3002 
3003 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3004 	/* The completion specifies the maximum time in ms that the driver
3005 	 * may hold the resource in the Timeout field.
3006 	 * If the resource is held by someone else, the command completes with
3007 	 * busy return value and the timeout field indicates the maximum time
3008 	 * the current owner of the resource has to free it.
3009 	 */
3010 	if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3011 		*timeout = le32_to_cpu(cmd_resp->timeout);
3012 
3013 	return status;
3014 }
3015 
3016 /**
3017  * i40e_aq_release_resource
3018  * @hw: pointer to the hw struct
3019  * @resource: resource id
3020  * @sdp_number: resource number
3021  * @cmd_details: pointer to command details structure or NULL
3022  *
3023  * release common resource using the admin queue commands
3024  **/
3025 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3026 				enum i40e_aq_resources_ids resource,
3027 				u8 sdp_number,
3028 				struct i40e_asq_cmd_details *cmd_details)
3029 {
3030 	struct i40e_aq_desc desc;
3031 	struct i40e_aqc_request_resource *cmd =
3032 		(struct i40e_aqc_request_resource *)&desc.params.raw;
3033 	i40e_status status;
3034 
3035 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3036 
3037 	cmd->resource_id = cpu_to_le16(resource);
3038 	cmd->resource_number = cpu_to_le32(sdp_number);
3039 
3040 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3041 
3042 	return status;
3043 }
3044 
3045 /**
3046  * i40e_aq_read_nvm
3047  * @hw: pointer to the hw struct
3048  * @module_pointer: module pointer location in words from the NVM beginning
3049  * @offset: byte offset from the module beginning
3050  * @length: length of the section to be read (in bytes from the offset)
3051  * @data: command buffer (size [bytes] = length)
3052  * @last_command: tells if this is the last command in a series
3053  * @cmd_details: pointer to command details structure or NULL
3054  *
3055  * Read the NVM using the admin queue commands
3056  **/
3057 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3058 				u32 offset, u16 length, void *data,
3059 				bool last_command,
3060 				struct i40e_asq_cmd_details *cmd_details)
3061 {
3062 	struct i40e_aq_desc desc;
3063 	struct i40e_aqc_nvm_update *cmd =
3064 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3065 	i40e_status status;
3066 
3067 	/* In offset the highest byte must be zeroed. */
3068 	if (offset & 0xFF000000) {
3069 		status = I40E_ERR_PARAM;
3070 		goto i40e_aq_read_nvm_exit;
3071 	}
3072 
3073 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3074 
3075 	/* If this is the last command in a series, set the proper flag. */
3076 	if (last_command)
3077 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3078 	cmd->module_pointer = module_pointer;
3079 	cmd->offset = cpu_to_le32(offset);
3080 	cmd->length = cpu_to_le16(length);
3081 
3082 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3083 	if (length > I40E_AQ_LARGE_BUF)
3084 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3085 
3086 	status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3087 
3088 i40e_aq_read_nvm_exit:
3089 	return status;
3090 }
3091 
3092 /**
3093  * i40e_aq_erase_nvm
3094  * @hw: pointer to the hw struct
3095  * @module_pointer: module pointer location in words from the NVM beginning
3096  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3097  * @length: length of the section to be erased (expressed in 4 KB)
3098  * @last_command: tells if this is the last command in a series
3099  * @cmd_details: pointer to command details structure or NULL
3100  *
3101  * Erase the NVM sector using the admin queue commands
3102  **/
3103 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3104 			      u32 offset, u16 length, bool last_command,
3105 			      struct i40e_asq_cmd_details *cmd_details)
3106 {
3107 	struct i40e_aq_desc desc;
3108 	struct i40e_aqc_nvm_update *cmd =
3109 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3110 	i40e_status status;
3111 
3112 	/* In offset the highest byte must be zeroed. */
3113 	if (offset & 0xFF000000) {
3114 		status = I40E_ERR_PARAM;
3115 		goto i40e_aq_erase_nvm_exit;
3116 	}
3117 
3118 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3119 
3120 	/* If this is the last command in a series, set the proper flag. */
3121 	if (last_command)
3122 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3123 	cmd->module_pointer = module_pointer;
3124 	cmd->offset = cpu_to_le32(offset);
3125 	cmd->length = cpu_to_le16(length);
3126 
3127 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3128 
3129 i40e_aq_erase_nvm_exit:
3130 	return status;
3131 }
3132 
3133 /**
3134  * i40e_parse_discover_capabilities
3135  * @hw: pointer to the hw struct
3136  * @buff: pointer to a buffer containing device/function capability records
3137  * @cap_count: number of capability records in the list
3138  * @list_type_opc: type of capabilities list to parse
3139  *
3140  * Parse the device/function capabilities list.
3141  **/
3142 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3143 				     u32 cap_count,
3144 				     enum i40e_admin_queue_opc list_type_opc)
3145 {
3146 	struct i40e_aqc_list_capabilities_element_resp *cap;
3147 	u32 valid_functions, num_functions;
3148 	u32 number, logical_id, phys_id;
3149 	struct i40e_hw_capabilities *p;
3150 	u8 major_rev;
3151 	u32 i = 0;
3152 	u16 id;
3153 
3154 	cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3155 
3156 	if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3157 		p = &hw->dev_caps;
3158 	else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3159 		p = &hw->func_caps;
3160 	else
3161 		return;
3162 
3163 	for (i = 0; i < cap_count; i++, cap++) {
3164 		id = le16_to_cpu(cap->id);
3165 		number = le32_to_cpu(cap->number);
3166 		logical_id = le32_to_cpu(cap->logical_id);
3167 		phys_id = le32_to_cpu(cap->phys_id);
3168 		major_rev = cap->major_rev;
3169 
3170 		switch (id) {
3171 		case I40E_AQ_CAP_ID_SWITCH_MODE:
3172 			p->switch_mode = number;
3173 			break;
3174 		case I40E_AQ_CAP_ID_MNG_MODE:
3175 			p->management_mode = number;
3176 			if (major_rev > 1) {
3177 				p->mng_protocols_over_mctp = logical_id;
3178 				i40e_debug(hw, I40E_DEBUG_INIT,
3179 					   "HW Capability: Protocols over MCTP = %d\n",
3180 					   p->mng_protocols_over_mctp);
3181 			} else {
3182 				p->mng_protocols_over_mctp = 0;
3183 			}
3184 			break;
3185 		case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3186 			p->npar_enable = number;
3187 			break;
3188 		case I40E_AQ_CAP_ID_OS2BMC_CAP:
3189 			p->os2bmc = number;
3190 			break;
3191 		case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3192 			p->valid_functions = number;
3193 			break;
3194 		case I40E_AQ_CAP_ID_SRIOV:
3195 			if (number == 1)
3196 				p->sr_iov_1_1 = true;
3197 			break;
3198 		case I40E_AQ_CAP_ID_VF:
3199 			p->num_vfs = number;
3200 			p->vf_base_id = logical_id;
3201 			break;
3202 		case I40E_AQ_CAP_ID_VMDQ:
3203 			if (number == 1)
3204 				p->vmdq = true;
3205 			break;
3206 		case I40E_AQ_CAP_ID_8021QBG:
3207 			if (number == 1)
3208 				p->evb_802_1_qbg = true;
3209 			break;
3210 		case I40E_AQ_CAP_ID_8021QBR:
3211 			if (number == 1)
3212 				p->evb_802_1_qbh = true;
3213 			break;
3214 		case I40E_AQ_CAP_ID_VSI:
3215 			p->num_vsis = number;
3216 			break;
3217 		case I40E_AQ_CAP_ID_DCB:
3218 			if (number == 1) {
3219 				p->dcb = true;
3220 				p->enabled_tcmap = logical_id;
3221 				p->maxtc = phys_id;
3222 			}
3223 			break;
3224 		case I40E_AQ_CAP_ID_FCOE:
3225 			if (number == 1)
3226 				p->fcoe = true;
3227 			break;
3228 		case I40E_AQ_CAP_ID_ISCSI:
3229 			if (number == 1)
3230 				p->iscsi = true;
3231 			break;
3232 		case I40E_AQ_CAP_ID_RSS:
3233 			p->rss = true;
3234 			p->rss_table_size = number;
3235 			p->rss_table_entry_width = logical_id;
3236 			break;
3237 		case I40E_AQ_CAP_ID_RXQ:
3238 			p->num_rx_qp = number;
3239 			p->base_queue = phys_id;
3240 			break;
3241 		case I40E_AQ_CAP_ID_TXQ:
3242 			p->num_tx_qp = number;
3243 			p->base_queue = phys_id;
3244 			break;
3245 		case I40E_AQ_CAP_ID_MSIX:
3246 			p->num_msix_vectors = number;
3247 			i40e_debug(hw, I40E_DEBUG_INIT,
3248 				   "HW Capability: MSIX vector count = %d\n",
3249 				   p->num_msix_vectors);
3250 			break;
3251 		case I40E_AQ_CAP_ID_VF_MSIX:
3252 			p->num_msix_vectors_vf = number;
3253 			break;
3254 		case I40E_AQ_CAP_ID_FLEX10:
3255 			if (major_rev == 1) {
3256 				if (number == 1) {
3257 					p->flex10_enable = true;
3258 					p->flex10_capable = true;
3259 				}
3260 			} else {
3261 				/* Capability revision >= 2 */
3262 				if (number & 1)
3263 					p->flex10_enable = true;
3264 				if (number & 2)
3265 					p->flex10_capable = true;
3266 			}
3267 			p->flex10_mode = logical_id;
3268 			p->flex10_status = phys_id;
3269 			break;
3270 		case I40E_AQ_CAP_ID_CEM:
3271 			if (number == 1)
3272 				p->mgmt_cem = true;
3273 			break;
3274 		case I40E_AQ_CAP_ID_IWARP:
3275 			if (number == 1)
3276 				p->iwarp = true;
3277 			break;
3278 		case I40E_AQ_CAP_ID_LED:
3279 			if (phys_id < I40E_HW_CAP_MAX_GPIO)
3280 				p->led[phys_id] = true;
3281 			break;
3282 		case I40E_AQ_CAP_ID_SDP:
3283 			if (phys_id < I40E_HW_CAP_MAX_GPIO)
3284 				p->sdp[phys_id] = true;
3285 			break;
3286 		case I40E_AQ_CAP_ID_MDIO:
3287 			if (number == 1) {
3288 				p->mdio_port_num = phys_id;
3289 				p->mdio_port_mode = logical_id;
3290 			}
3291 			break;
3292 		case I40E_AQ_CAP_ID_1588:
3293 			if (number == 1)
3294 				p->ieee_1588 = true;
3295 			break;
3296 		case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3297 			p->fd = true;
3298 			p->fd_filters_guaranteed = number;
3299 			p->fd_filters_best_effort = logical_id;
3300 			break;
3301 		case I40E_AQ_CAP_ID_WSR_PROT:
3302 			p->wr_csr_prot = (u64)number;
3303 			p->wr_csr_prot |= (u64)logical_id << 32;
3304 			break;
3305 		case I40E_AQ_CAP_ID_NVM_MGMT:
3306 			if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3307 				p->sec_rev_disabled = true;
3308 			if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3309 				p->update_disabled = true;
3310 			break;
3311 		default:
3312 			break;
3313 		}
3314 	}
3315 
3316 	if (p->fcoe)
3317 		i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3318 
3319 	/* Software override ensuring FCoE is disabled if npar or mfp
3320 	 * mode because it is not supported in these modes.
3321 	 */
3322 	if (p->npar_enable || p->flex10_enable)
3323 		p->fcoe = false;
3324 
3325 	/* count the enabled ports (aka the "not disabled" ports) */
3326 	hw->num_ports = 0;
3327 	for (i = 0; i < 4; i++) {
3328 		u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3329 		u64 port_cfg = 0;
3330 
3331 		/* use AQ read to get the physical register offset instead
3332 		 * of the port relative offset
3333 		 */
3334 		i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3335 		if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3336 			hw->num_ports++;
3337 	}
3338 
3339 	valid_functions = p->valid_functions;
3340 	num_functions = 0;
3341 	while (valid_functions) {
3342 		if (valid_functions & 1)
3343 			num_functions++;
3344 		valid_functions >>= 1;
3345 	}
3346 
3347 	/* partition id is 1-based, and functions are evenly spread
3348 	 * across the ports as partitions
3349 	 */
3350 	if (hw->num_ports != 0) {
3351 		hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3352 		hw->num_partitions = num_functions / hw->num_ports;
3353 	}
3354 
3355 	/* additional HW specific goodies that might
3356 	 * someday be HW version specific
3357 	 */
3358 	p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3359 }
3360 
3361 /**
3362  * i40e_aq_discover_capabilities
3363  * @hw: pointer to the hw struct
3364  * @buff: a virtual buffer to hold the capabilities
3365  * @buff_size: Size of the virtual buffer
3366  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3367  * @list_type_opc: capabilities type to discover - pass in the command opcode
3368  * @cmd_details: pointer to command details structure or NULL
3369  *
3370  * Get the device capabilities descriptions from the firmware
3371  **/
3372 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3373 				void *buff, u16 buff_size, u16 *data_size,
3374 				enum i40e_admin_queue_opc list_type_opc,
3375 				struct i40e_asq_cmd_details *cmd_details)
3376 {
3377 	struct i40e_aqc_list_capabilites *cmd;
3378 	struct i40e_aq_desc desc;
3379 	i40e_status status = 0;
3380 
3381 	cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3382 
3383 	if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3384 		list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3385 		status = I40E_ERR_PARAM;
3386 		goto exit;
3387 	}
3388 
3389 	i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3390 
3391 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3392 	if (buff_size > I40E_AQ_LARGE_BUF)
3393 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3394 
3395 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3396 	*data_size = le16_to_cpu(desc.datalen);
3397 
3398 	if (status)
3399 		goto exit;
3400 
3401 	i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3402 					 list_type_opc);
3403 
3404 exit:
3405 	return status;
3406 }
3407 
3408 /**
3409  * i40e_aq_update_nvm
3410  * @hw: pointer to the hw struct
3411  * @module_pointer: module pointer location in words from the NVM beginning
3412  * @offset: byte offset from the module beginning
3413  * @length: length of the section to be written (in bytes from the offset)
3414  * @data: command buffer (size [bytes] = length)
3415  * @last_command: tells if this is the last command in a series
3416  * @cmd_details: pointer to command details structure or NULL
3417  *
3418  * Update the NVM using the admin queue commands
3419  **/
3420 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3421 			       u32 offset, u16 length, void *data,
3422 			       bool last_command,
3423 			       struct i40e_asq_cmd_details *cmd_details)
3424 {
3425 	struct i40e_aq_desc desc;
3426 	struct i40e_aqc_nvm_update *cmd =
3427 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3428 	i40e_status status;
3429 
3430 	/* In offset the highest byte must be zeroed. */
3431 	if (offset & 0xFF000000) {
3432 		status = I40E_ERR_PARAM;
3433 		goto i40e_aq_update_nvm_exit;
3434 	}
3435 
3436 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3437 
3438 	/* If this is the last command in a series, set the proper flag. */
3439 	if (last_command)
3440 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3441 	cmd->module_pointer = module_pointer;
3442 	cmd->offset = cpu_to_le32(offset);
3443 	cmd->length = cpu_to_le16(length);
3444 
3445 	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3446 	if (length > I40E_AQ_LARGE_BUF)
3447 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3448 
3449 	status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3450 
3451 i40e_aq_update_nvm_exit:
3452 	return status;
3453 }
3454 
3455 /**
3456  * i40e_aq_get_lldp_mib
3457  * @hw: pointer to the hw struct
3458  * @bridge_type: type of bridge requested
3459  * @mib_type: Local, Remote or both Local and Remote MIBs
3460  * @buff: pointer to a user supplied buffer to store the MIB block
3461  * @buff_size: size of the buffer (in bytes)
3462  * @local_len : length of the returned Local LLDP MIB
3463  * @remote_len: length of the returned Remote LLDP MIB
3464  * @cmd_details: pointer to command details structure or NULL
3465  *
3466  * Requests the complete LLDP MIB (entire packet).
3467  **/
3468 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3469 				u8 mib_type, void *buff, u16 buff_size,
3470 				u16 *local_len, u16 *remote_len,
3471 				struct i40e_asq_cmd_details *cmd_details)
3472 {
3473 	struct i40e_aq_desc desc;
3474 	struct i40e_aqc_lldp_get_mib *cmd =
3475 		(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3476 	struct i40e_aqc_lldp_get_mib *resp =
3477 		(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3478 	i40e_status status;
3479 
3480 	if (buff_size == 0 || !buff)
3481 		return I40E_ERR_PARAM;
3482 
3483 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3484 	/* Indirect Command */
3485 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3486 
3487 	cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3488 	cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3489 		       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3490 
3491 	desc.datalen = cpu_to_le16(buff_size);
3492 
3493 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3494 	if (buff_size > I40E_AQ_LARGE_BUF)
3495 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3496 
3497 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3498 	if (!status) {
3499 		if (local_len != NULL)
3500 			*local_len = le16_to_cpu(resp->local_len);
3501 		if (remote_len != NULL)
3502 			*remote_len = le16_to_cpu(resp->remote_len);
3503 	}
3504 
3505 	return status;
3506 }
3507 
3508 /**
3509  * i40e_aq_cfg_lldp_mib_change_event
3510  * @hw: pointer to the hw struct
3511  * @enable_update: Enable or Disable event posting
3512  * @cmd_details: pointer to command details structure or NULL
3513  *
3514  * Enable or Disable posting of an event on ARQ when LLDP MIB
3515  * associated with the interface changes
3516  **/
3517 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3518 				bool enable_update,
3519 				struct i40e_asq_cmd_details *cmd_details)
3520 {
3521 	struct i40e_aq_desc desc;
3522 	struct i40e_aqc_lldp_update_mib *cmd =
3523 		(struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3524 	i40e_status status;
3525 
3526 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3527 
3528 	if (!enable_update)
3529 		cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3530 
3531 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3532 
3533 	return status;
3534 }
3535 
3536 /**
3537  * i40e_aq_stop_lldp
3538  * @hw: pointer to the hw struct
3539  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3540  * @cmd_details: pointer to command details structure or NULL
3541  *
3542  * Stop or Shutdown the embedded LLDP Agent
3543  **/
3544 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3545 				struct i40e_asq_cmd_details *cmd_details)
3546 {
3547 	struct i40e_aq_desc desc;
3548 	struct i40e_aqc_lldp_stop *cmd =
3549 		(struct i40e_aqc_lldp_stop *)&desc.params.raw;
3550 	i40e_status status;
3551 
3552 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3553 
3554 	if (shutdown_agent)
3555 		cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3556 
3557 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3558 
3559 	return status;
3560 }
3561 
3562 /**
3563  * i40e_aq_start_lldp
3564  * @hw: pointer to the hw struct
3565  * @cmd_details: pointer to command details structure or NULL
3566  *
3567  * Start the embedded LLDP Agent on all ports.
3568  **/
3569 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3570 				struct i40e_asq_cmd_details *cmd_details)
3571 {
3572 	struct i40e_aq_desc desc;
3573 	struct i40e_aqc_lldp_start *cmd =
3574 		(struct i40e_aqc_lldp_start *)&desc.params.raw;
3575 	i40e_status status;
3576 
3577 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3578 
3579 	cmd->command = I40E_AQ_LLDP_AGENT_START;
3580 
3581 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3582 
3583 	return status;
3584 }
3585 
3586 /**
3587  * i40e_aq_get_cee_dcb_config
3588  * @hw: pointer to the hw struct
3589  * @buff: response buffer that stores CEE operational configuration
3590  * @buff_size: size of the buffer passed
3591  * @cmd_details: pointer to command details structure or NULL
3592  *
3593  * Get CEE DCBX mode operational configuration from firmware
3594  **/
3595 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3596 				       void *buff, u16 buff_size,
3597 				       struct i40e_asq_cmd_details *cmd_details)
3598 {
3599 	struct i40e_aq_desc desc;
3600 	i40e_status status;
3601 
3602 	if (buff_size == 0 || !buff)
3603 		return I40E_ERR_PARAM;
3604 
3605 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3606 
3607 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3608 	status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3609 				       cmd_details);
3610 
3611 	return status;
3612 }
3613 
3614 /**
3615  * i40e_aq_add_udp_tunnel
3616  * @hw: pointer to the hw struct
3617  * @udp_port: the UDP port to add in Host byte order
3618  * @header_len: length of the tunneling header length in DWords
3619  * @protocol_index: protocol index type
3620  * @filter_index: pointer to filter index
3621  * @cmd_details: pointer to command details structure or NULL
3622  *
3623  * Note: Firmware expects the udp_port value to be in Little Endian format,
3624  * and this function will call cpu_to_le16 to convert from Host byte order to
3625  * Little Endian order.
3626  **/
3627 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3628 				u16 udp_port, u8 protocol_index,
3629 				u8 *filter_index,
3630 				struct i40e_asq_cmd_details *cmd_details)
3631 {
3632 	struct i40e_aq_desc desc;
3633 	struct i40e_aqc_add_udp_tunnel *cmd =
3634 		(struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3635 	struct i40e_aqc_del_udp_tunnel_completion *resp =
3636 		(struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3637 	i40e_status status;
3638 
3639 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3640 
3641 	cmd->udp_port = cpu_to_le16(udp_port);
3642 	cmd->protocol_type = protocol_index;
3643 
3644 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3645 
3646 	if (!status && filter_index)
3647 		*filter_index = resp->index;
3648 
3649 	return status;
3650 }
3651 
3652 /**
3653  * i40e_aq_del_udp_tunnel
3654  * @hw: pointer to the hw struct
3655  * @index: filter index
3656  * @cmd_details: pointer to command details structure or NULL
3657  **/
3658 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3659 				struct i40e_asq_cmd_details *cmd_details)
3660 {
3661 	struct i40e_aq_desc desc;
3662 	struct i40e_aqc_remove_udp_tunnel *cmd =
3663 		(struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3664 	i40e_status status;
3665 
3666 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3667 
3668 	cmd->index = index;
3669 
3670 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3671 
3672 	return status;
3673 }
3674 
3675 /**
3676  * i40e_aq_delete_element - Delete switch element
3677  * @hw: pointer to the hw struct
3678  * @seid: the SEID to delete from the switch
3679  * @cmd_details: pointer to command details structure or NULL
3680  *
3681  * This deletes a switch element from the switch.
3682  **/
3683 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3684 				struct i40e_asq_cmd_details *cmd_details)
3685 {
3686 	struct i40e_aq_desc desc;
3687 	struct i40e_aqc_switch_seid *cmd =
3688 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
3689 	i40e_status status;
3690 
3691 	if (seid == 0)
3692 		return I40E_ERR_PARAM;
3693 
3694 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3695 
3696 	cmd->seid = cpu_to_le16(seid);
3697 
3698 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3699 
3700 	return status;
3701 }
3702 
3703 /**
3704  * i40e_aq_dcb_updated - DCB Updated Command
3705  * @hw: pointer to the hw struct
3706  * @cmd_details: pointer to command details structure or NULL
3707  *
3708  * EMP will return when the shared RPB settings have been
3709  * recomputed and modified. The retval field in the descriptor
3710  * will be set to 0 when RPB is modified.
3711  **/
3712 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3713 				struct i40e_asq_cmd_details *cmd_details)
3714 {
3715 	struct i40e_aq_desc desc;
3716 	i40e_status status;
3717 
3718 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3719 
3720 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3721 
3722 	return status;
3723 }
3724 
3725 /**
3726  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3727  * @hw: pointer to the hw struct
3728  * @seid: seid for the physical port/switching component/vsi
3729  * @buff: Indirect buffer to hold data parameters and response
3730  * @buff_size: Indirect buffer size
3731  * @opcode: Tx scheduler AQ command opcode
3732  * @cmd_details: pointer to command details structure or NULL
3733  *
3734  * Generic command handler for Tx scheduler AQ commands
3735  **/
3736 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3737 				void *buff, u16 buff_size,
3738 				 enum i40e_admin_queue_opc opcode,
3739 				struct i40e_asq_cmd_details *cmd_details)
3740 {
3741 	struct i40e_aq_desc desc;
3742 	struct i40e_aqc_tx_sched_ind *cmd =
3743 		(struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3744 	i40e_status status;
3745 	bool cmd_param_flag = false;
3746 
3747 	switch (opcode) {
3748 	case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3749 	case i40e_aqc_opc_configure_vsi_tc_bw:
3750 	case i40e_aqc_opc_enable_switching_comp_ets:
3751 	case i40e_aqc_opc_modify_switching_comp_ets:
3752 	case i40e_aqc_opc_disable_switching_comp_ets:
3753 	case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3754 	case i40e_aqc_opc_configure_switching_comp_bw_config:
3755 		cmd_param_flag = true;
3756 		break;
3757 	case i40e_aqc_opc_query_vsi_bw_config:
3758 	case i40e_aqc_opc_query_vsi_ets_sla_config:
3759 	case i40e_aqc_opc_query_switching_comp_ets_config:
3760 	case i40e_aqc_opc_query_port_ets_config:
3761 	case i40e_aqc_opc_query_switching_comp_bw_config:
3762 		cmd_param_flag = false;
3763 		break;
3764 	default:
3765 		return I40E_ERR_PARAM;
3766 	}
3767 
3768 	i40e_fill_default_direct_cmd_desc(&desc, opcode);
3769 
3770 	/* Indirect command */
3771 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3772 	if (cmd_param_flag)
3773 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3774 	if (buff_size > I40E_AQ_LARGE_BUF)
3775 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3776 
3777 	desc.datalen = cpu_to_le16(buff_size);
3778 
3779 	cmd->vsi_seid = cpu_to_le16(seid);
3780 
3781 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3782 
3783 	return status;
3784 }
3785 
3786 /**
3787  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3788  * @hw: pointer to the hw struct
3789  * @seid: VSI seid
3790  * @credit: BW limit credits (0 = disabled)
3791  * @max_credit: Max BW limit credits
3792  * @cmd_details: pointer to command details structure or NULL
3793  **/
3794 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3795 				u16 seid, u16 credit, u8 max_credit,
3796 				struct i40e_asq_cmd_details *cmd_details)
3797 {
3798 	struct i40e_aq_desc desc;
3799 	struct i40e_aqc_configure_vsi_bw_limit *cmd =
3800 		(struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3801 	i40e_status status;
3802 
3803 	i40e_fill_default_direct_cmd_desc(&desc,
3804 					  i40e_aqc_opc_configure_vsi_bw_limit);
3805 
3806 	cmd->vsi_seid = cpu_to_le16(seid);
3807 	cmd->credit = cpu_to_le16(credit);
3808 	cmd->max_credit = max_credit;
3809 
3810 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3811 
3812 	return status;
3813 }
3814 
3815 /**
3816  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3817  * @hw: pointer to the hw struct
3818  * @seid: VSI seid
3819  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3820  * @cmd_details: pointer to command details structure or NULL
3821  **/
3822 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3823 			u16 seid,
3824 			struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3825 			struct i40e_asq_cmd_details *cmd_details)
3826 {
3827 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3828 				    i40e_aqc_opc_configure_vsi_tc_bw,
3829 				    cmd_details);
3830 }
3831 
3832 /**
3833  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3834  * @hw: pointer to the hw struct
3835  * @seid: seid of the switching component connected to Physical Port
3836  * @ets_data: Buffer holding ETS parameters
3837  * @cmd_details: pointer to command details structure or NULL
3838  **/
3839 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3840 		u16 seid,
3841 		struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3842 		enum i40e_admin_queue_opc opcode,
3843 		struct i40e_asq_cmd_details *cmd_details)
3844 {
3845 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3846 				    sizeof(*ets_data), opcode, cmd_details);
3847 }
3848 
3849 /**
3850  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3851  * @hw: pointer to the hw struct
3852  * @seid: seid of the switching component
3853  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3854  * @cmd_details: pointer to command details structure or NULL
3855  **/
3856 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3857 	u16 seid,
3858 	struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3859 	struct i40e_asq_cmd_details *cmd_details)
3860 {
3861 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3862 			    i40e_aqc_opc_configure_switching_comp_bw_config,
3863 			    cmd_details);
3864 }
3865 
3866 /**
3867  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3868  * @hw: pointer to the hw struct
3869  * @seid: seid of the VSI
3870  * @bw_data: Buffer to hold VSI BW configuration
3871  * @cmd_details: pointer to command details structure or NULL
3872  **/
3873 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3874 			u16 seid,
3875 			struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3876 			struct i40e_asq_cmd_details *cmd_details)
3877 {
3878 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3879 				    i40e_aqc_opc_query_vsi_bw_config,
3880 				    cmd_details);
3881 }
3882 
3883 /**
3884  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3885  * @hw: pointer to the hw struct
3886  * @seid: seid of the VSI
3887  * @bw_data: Buffer to hold VSI BW configuration per TC
3888  * @cmd_details: pointer to command details structure or NULL
3889  **/
3890 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3891 			u16 seid,
3892 			struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3893 			struct i40e_asq_cmd_details *cmd_details)
3894 {
3895 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3896 				    i40e_aqc_opc_query_vsi_ets_sla_config,
3897 				    cmd_details);
3898 }
3899 
3900 /**
3901  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3902  * @hw: pointer to the hw struct
3903  * @seid: seid of the switching component
3904  * @bw_data: Buffer to hold switching component's per TC BW config
3905  * @cmd_details: pointer to command details structure or NULL
3906  **/
3907 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3908 		u16 seid,
3909 		struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3910 		struct i40e_asq_cmd_details *cmd_details)
3911 {
3912 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3913 				   i40e_aqc_opc_query_switching_comp_ets_config,
3914 				   cmd_details);
3915 }
3916 
3917 /**
3918  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3919  * @hw: pointer to the hw struct
3920  * @seid: seid of the VSI or switching component connected to Physical Port
3921  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3922  * @cmd_details: pointer to command details structure or NULL
3923  **/
3924 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3925 			u16 seid,
3926 			struct i40e_aqc_query_port_ets_config_resp *bw_data,
3927 			struct i40e_asq_cmd_details *cmd_details)
3928 {
3929 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3930 				    i40e_aqc_opc_query_port_ets_config,
3931 				    cmd_details);
3932 }
3933 
3934 /**
3935  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3936  * @hw: pointer to the hw struct
3937  * @seid: seid of the switching component
3938  * @bw_data: Buffer to hold switching component's BW configuration
3939  * @cmd_details: pointer to command details structure or NULL
3940  **/
3941 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3942 		u16 seid,
3943 		struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3944 		struct i40e_asq_cmd_details *cmd_details)
3945 {
3946 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3947 				    i40e_aqc_opc_query_switching_comp_bw_config,
3948 				    cmd_details);
3949 }
3950 
3951 /**
3952  * i40e_validate_filter_settings
3953  * @hw: pointer to the hardware structure
3954  * @settings: Filter control settings
3955  *
3956  * Check and validate the filter control settings passed.
3957  * The function checks for the valid filter/context sizes being
3958  * passed for FCoE and PE.
3959  *
3960  * Returns 0 if the values passed are valid and within
3961  * range else returns an error.
3962  **/
3963 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3964 				struct i40e_filter_control_settings *settings)
3965 {
3966 	u32 fcoe_cntx_size, fcoe_filt_size;
3967 	u32 pe_cntx_size, pe_filt_size;
3968 	u32 fcoe_fmax;
3969 	u32 val;
3970 
3971 	/* Validate FCoE settings passed */
3972 	switch (settings->fcoe_filt_num) {
3973 	case I40E_HASH_FILTER_SIZE_1K:
3974 	case I40E_HASH_FILTER_SIZE_2K:
3975 	case I40E_HASH_FILTER_SIZE_4K:
3976 	case I40E_HASH_FILTER_SIZE_8K:
3977 	case I40E_HASH_FILTER_SIZE_16K:
3978 	case I40E_HASH_FILTER_SIZE_32K:
3979 		fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3980 		fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3981 		break;
3982 	default:
3983 		return I40E_ERR_PARAM;
3984 	}
3985 
3986 	switch (settings->fcoe_cntx_num) {
3987 	case I40E_DMA_CNTX_SIZE_512:
3988 	case I40E_DMA_CNTX_SIZE_1K:
3989 	case I40E_DMA_CNTX_SIZE_2K:
3990 	case I40E_DMA_CNTX_SIZE_4K:
3991 		fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3992 		fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3993 		break;
3994 	default:
3995 		return I40E_ERR_PARAM;
3996 	}
3997 
3998 	/* Validate PE settings passed */
3999 	switch (settings->pe_filt_num) {
4000 	case I40E_HASH_FILTER_SIZE_1K:
4001 	case I40E_HASH_FILTER_SIZE_2K:
4002 	case I40E_HASH_FILTER_SIZE_4K:
4003 	case I40E_HASH_FILTER_SIZE_8K:
4004 	case I40E_HASH_FILTER_SIZE_16K:
4005 	case I40E_HASH_FILTER_SIZE_32K:
4006 	case I40E_HASH_FILTER_SIZE_64K:
4007 	case I40E_HASH_FILTER_SIZE_128K:
4008 	case I40E_HASH_FILTER_SIZE_256K:
4009 	case I40E_HASH_FILTER_SIZE_512K:
4010 	case I40E_HASH_FILTER_SIZE_1M:
4011 		pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4012 		pe_filt_size <<= (u32)settings->pe_filt_num;
4013 		break;
4014 	default:
4015 		return I40E_ERR_PARAM;
4016 	}
4017 
4018 	switch (settings->pe_cntx_num) {
4019 	case I40E_DMA_CNTX_SIZE_512:
4020 	case I40E_DMA_CNTX_SIZE_1K:
4021 	case I40E_DMA_CNTX_SIZE_2K:
4022 	case I40E_DMA_CNTX_SIZE_4K:
4023 	case I40E_DMA_CNTX_SIZE_8K:
4024 	case I40E_DMA_CNTX_SIZE_16K:
4025 	case I40E_DMA_CNTX_SIZE_32K:
4026 	case I40E_DMA_CNTX_SIZE_64K:
4027 	case I40E_DMA_CNTX_SIZE_128K:
4028 	case I40E_DMA_CNTX_SIZE_256K:
4029 		pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4030 		pe_cntx_size <<= (u32)settings->pe_cntx_num;
4031 		break;
4032 	default:
4033 		return I40E_ERR_PARAM;
4034 	}
4035 
4036 	/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4037 	val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4038 	fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4039 		     >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4040 	if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4041 		return I40E_ERR_INVALID_SIZE;
4042 
4043 	return 0;
4044 }
4045 
4046 /**
4047  * i40e_set_filter_control
4048  * @hw: pointer to the hardware structure
4049  * @settings: Filter control settings
4050  *
4051  * Set the Queue Filters for PE/FCoE and enable filters required
4052  * for a single PF. It is expected that these settings are programmed
4053  * at the driver initialization time.
4054  **/
4055 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4056 				struct i40e_filter_control_settings *settings)
4057 {
4058 	i40e_status ret = 0;
4059 	u32 hash_lut_size = 0;
4060 	u32 val;
4061 
4062 	if (!settings)
4063 		return I40E_ERR_PARAM;
4064 
4065 	/* Validate the input settings */
4066 	ret = i40e_validate_filter_settings(hw, settings);
4067 	if (ret)
4068 		return ret;
4069 
4070 	/* Read the PF Queue Filter control register */
4071 	val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4072 
4073 	/* Program required PE hash buckets for the PF */
4074 	val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4075 	val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4076 		I40E_PFQF_CTL_0_PEHSIZE_MASK;
4077 	/* Program required PE contexts for the PF */
4078 	val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4079 	val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4080 		I40E_PFQF_CTL_0_PEDSIZE_MASK;
4081 
4082 	/* Program required FCoE hash buckets for the PF */
4083 	val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4084 	val |= ((u32)settings->fcoe_filt_num <<
4085 			I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4086 		I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4087 	/* Program required FCoE DDP contexts for the PF */
4088 	val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4089 	val |= ((u32)settings->fcoe_cntx_num <<
4090 			I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4091 		I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4092 
4093 	/* Program Hash LUT size for the PF */
4094 	val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4095 	if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4096 		hash_lut_size = 1;
4097 	val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4098 		I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4099 
4100 	/* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4101 	if (settings->enable_fdir)
4102 		val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4103 	if (settings->enable_ethtype)
4104 		val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4105 	if (settings->enable_macvlan)
4106 		val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4107 
4108 	i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4109 
4110 	return 0;
4111 }
4112 
4113 /**
4114  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4115  * @hw: pointer to the hw struct
4116  * @mac_addr: MAC address to use in the filter
4117  * @ethtype: Ethertype to use in the filter
4118  * @flags: Flags that needs to be applied to the filter
4119  * @vsi_seid: seid of the control VSI
4120  * @queue: VSI queue number to send the packet to
4121  * @is_add: Add control packet filter if True else remove
4122  * @stats: Structure to hold information on control filter counts
4123  * @cmd_details: pointer to command details structure or NULL
4124  *
4125  * This command will Add or Remove control packet filter for a control VSI.
4126  * In return it will update the total number of perfect filter count in
4127  * the stats member.
4128  **/
4129 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4130 				u8 *mac_addr, u16 ethtype, u16 flags,
4131 				u16 vsi_seid, u16 queue, bool is_add,
4132 				struct i40e_control_filter_stats *stats,
4133 				struct i40e_asq_cmd_details *cmd_details)
4134 {
4135 	struct i40e_aq_desc desc;
4136 	struct i40e_aqc_add_remove_control_packet_filter *cmd =
4137 		(struct i40e_aqc_add_remove_control_packet_filter *)
4138 		&desc.params.raw;
4139 	struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4140 		(struct i40e_aqc_add_remove_control_packet_filter_completion *)
4141 		&desc.params.raw;
4142 	i40e_status status;
4143 
4144 	if (vsi_seid == 0)
4145 		return I40E_ERR_PARAM;
4146 
4147 	if (is_add) {
4148 		i40e_fill_default_direct_cmd_desc(&desc,
4149 				i40e_aqc_opc_add_control_packet_filter);
4150 		cmd->queue = cpu_to_le16(queue);
4151 	} else {
4152 		i40e_fill_default_direct_cmd_desc(&desc,
4153 				i40e_aqc_opc_remove_control_packet_filter);
4154 	}
4155 
4156 	if (mac_addr)
4157 		ether_addr_copy(cmd->mac, mac_addr);
4158 
4159 	cmd->etype = cpu_to_le16(ethtype);
4160 	cmd->flags = cpu_to_le16(flags);
4161 	cmd->seid = cpu_to_le16(vsi_seid);
4162 
4163 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4164 
4165 	if (!status && stats) {
4166 		stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4167 		stats->etype_used = le16_to_cpu(resp->etype_used);
4168 		stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4169 		stats->etype_free = le16_to_cpu(resp->etype_free);
4170 	}
4171 
4172 	return status;
4173 }
4174 
4175 /**
4176  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4177  * @hw: pointer to the hw struct
4178  * @seid: VSI seid to add ethertype filter from
4179  **/
4180 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4181 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4182 						    u16 seid)
4183 {
4184 	u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4185 		   I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4186 		   I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4187 	u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4188 	i40e_status status;
4189 
4190 	status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4191 						       seid, 0, true, NULL,
4192 						       NULL);
4193 	if (status)
4194 		hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4195 }
4196 
4197 /**
4198  * i40e_aq_alternate_read
4199  * @hw: pointer to the hardware structure
4200  * @reg_addr0: address of first dword to be read
4201  * @reg_val0: pointer for data read from 'reg_addr0'
4202  * @reg_addr1: address of second dword to be read
4203  * @reg_val1: pointer for data read from 'reg_addr1'
4204  *
4205  * Read one or two dwords from alternate structure. Fields are indicated
4206  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4207  * is not passed then only register at 'reg_addr0' is read.
4208  *
4209  **/
4210 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4211 					  u32 reg_addr0, u32 *reg_val0,
4212 					  u32 reg_addr1, u32 *reg_val1)
4213 {
4214 	struct i40e_aq_desc desc;
4215 	struct i40e_aqc_alternate_write *cmd_resp =
4216 		(struct i40e_aqc_alternate_write *)&desc.params.raw;
4217 	i40e_status status;
4218 
4219 	if (!reg_val0)
4220 		return I40E_ERR_PARAM;
4221 
4222 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4223 	cmd_resp->address0 = cpu_to_le32(reg_addr0);
4224 	cmd_resp->address1 = cpu_to_le32(reg_addr1);
4225 
4226 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4227 
4228 	if (!status) {
4229 		*reg_val0 = le32_to_cpu(cmd_resp->data0);
4230 
4231 		if (reg_val1)
4232 			*reg_val1 = le32_to_cpu(cmd_resp->data1);
4233 	}
4234 
4235 	return status;
4236 }
4237 
4238 /**
4239  * i40e_aq_resume_port_tx
4240  * @hw: pointer to the hardware structure
4241  * @cmd_details: pointer to command details structure or NULL
4242  *
4243  * Resume port's Tx traffic
4244  **/
4245 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4246 				   struct i40e_asq_cmd_details *cmd_details)
4247 {
4248 	struct i40e_aq_desc desc;
4249 	i40e_status status;
4250 
4251 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4252 
4253 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4254 
4255 	return status;
4256 }
4257 
4258 /**
4259  * i40e_set_pci_config_data - store PCI bus info
4260  * @hw: pointer to hardware structure
4261  * @link_status: the link status word from PCI config space
4262  *
4263  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4264  **/
4265 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4266 {
4267 	hw->bus.type = i40e_bus_type_pci_express;
4268 
4269 	switch (link_status & PCI_EXP_LNKSTA_NLW) {
4270 	case PCI_EXP_LNKSTA_NLW_X1:
4271 		hw->bus.width = i40e_bus_width_pcie_x1;
4272 		break;
4273 	case PCI_EXP_LNKSTA_NLW_X2:
4274 		hw->bus.width = i40e_bus_width_pcie_x2;
4275 		break;
4276 	case PCI_EXP_LNKSTA_NLW_X4:
4277 		hw->bus.width = i40e_bus_width_pcie_x4;
4278 		break;
4279 	case PCI_EXP_LNKSTA_NLW_X8:
4280 		hw->bus.width = i40e_bus_width_pcie_x8;
4281 		break;
4282 	default:
4283 		hw->bus.width = i40e_bus_width_unknown;
4284 		break;
4285 	}
4286 
4287 	switch (link_status & PCI_EXP_LNKSTA_CLS) {
4288 	case PCI_EXP_LNKSTA_CLS_2_5GB:
4289 		hw->bus.speed = i40e_bus_speed_2500;
4290 		break;
4291 	case PCI_EXP_LNKSTA_CLS_5_0GB:
4292 		hw->bus.speed = i40e_bus_speed_5000;
4293 		break;
4294 	case PCI_EXP_LNKSTA_CLS_8_0GB:
4295 		hw->bus.speed = i40e_bus_speed_8000;
4296 		break;
4297 	default:
4298 		hw->bus.speed = i40e_bus_speed_unknown;
4299 		break;
4300 	}
4301 }
4302 
4303 /**
4304  * i40e_aq_debug_dump
4305  * @hw: pointer to the hardware structure
4306  * @cluster_id: specific cluster to dump
4307  * @table_id: table id within cluster
4308  * @start_index: index of line in the block to read
4309  * @buff_size: dump buffer size
4310  * @buff: dump buffer
4311  * @ret_buff_size: actual buffer size returned
4312  * @ret_next_table: next block to read
4313  * @ret_next_index: next index to read
4314  *
4315  * Dump internal FW/HW data for debug purposes.
4316  *
4317  **/
4318 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4319 			       u8 table_id, u32 start_index, u16 buff_size,
4320 			       void *buff, u16 *ret_buff_size,
4321 			       u8 *ret_next_table, u32 *ret_next_index,
4322 			       struct i40e_asq_cmd_details *cmd_details)
4323 {
4324 	struct i40e_aq_desc desc;
4325 	struct i40e_aqc_debug_dump_internals *cmd =
4326 		(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4327 	struct i40e_aqc_debug_dump_internals *resp =
4328 		(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4329 	i40e_status status;
4330 
4331 	if (buff_size == 0 || !buff)
4332 		return I40E_ERR_PARAM;
4333 
4334 	i40e_fill_default_direct_cmd_desc(&desc,
4335 					  i40e_aqc_opc_debug_dump_internals);
4336 	/* Indirect Command */
4337 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4338 	if (buff_size > I40E_AQ_LARGE_BUF)
4339 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4340 
4341 	cmd->cluster_id = cluster_id;
4342 	cmd->table_id = table_id;
4343 	cmd->idx = cpu_to_le32(start_index);
4344 
4345 	desc.datalen = cpu_to_le16(buff_size);
4346 
4347 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4348 	if (!status) {
4349 		if (ret_buff_size)
4350 			*ret_buff_size = le16_to_cpu(desc.datalen);
4351 		if (ret_next_table)
4352 			*ret_next_table = resp->table_id;
4353 		if (ret_next_index)
4354 			*ret_next_index = le32_to_cpu(resp->idx);
4355 	}
4356 
4357 	return status;
4358 }
4359 
4360 /**
4361  * i40e_read_bw_from_alt_ram
4362  * @hw: pointer to the hardware structure
4363  * @max_bw: pointer for max_bw read
4364  * @min_bw: pointer for min_bw read
4365  * @min_valid: pointer for bool that is true if min_bw is a valid value
4366  * @max_valid: pointer for bool that is true if max_bw is a valid value
4367  *
4368  * Read bw from the alternate ram for the given pf
4369  **/
4370 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4371 				      u32 *max_bw, u32 *min_bw,
4372 				      bool *min_valid, bool *max_valid)
4373 {
4374 	i40e_status status;
4375 	u32 max_bw_addr, min_bw_addr;
4376 
4377 	/* Calculate the address of the min/max bw registers */
4378 	max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4379 		      I40E_ALT_STRUCT_MAX_BW_OFFSET +
4380 		      (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4381 	min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4382 		      I40E_ALT_STRUCT_MIN_BW_OFFSET +
4383 		      (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4384 
4385 	/* Read the bandwidths from alt ram */
4386 	status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4387 					min_bw_addr, min_bw);
4388 
4389 	if (*min_bw & I40E_ALT_BW_VALID_MASK)
4390 		*min_valid = true;
4391 	else
4392 		*min_valid = false;
4393 
4394 	if (*max_bw & I40E_ALT_BW_VALID_MASK)
4395 		*max_valid = true;
4396 	else
4397 		*max_valid = false;
4398 
4399 	return status;
4400 }
4401 
4402 /**
4403  * i40e_aq_configure_partition_bw
4404  * @hw: pointer to the hardware structure
4405  * @bw_data: Buffer holding valid pfs and bw limits
4406  * @cmd_details: pointer to command details
4407  *
4408  * Configure partitions guaranteed/max bw
4409  **/
4410 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4411 			struct i40e_aqc_configure_partition_bw_data *bw_data,
4412 			struct i40e_asq_cmd_details *cmd_details)
4413 {
4414 	i40e_status status;
4415 	struct i40e_aq_desc desc;
4416 	u16 bwd_size = sizeof(*bw_data);
4417 
4418 	i40e_fill_default_direct_cmd_desc(&desc,
4419 					  i40e_aqc_opc_configure_partition_bw);
4420 
4421 	/* Indirect command */
4422 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4423 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4424 
4425 	if (bwd_size > I40E_AQ_LARGE_BUF)
4426 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4427 
4428 	desc.datalen = cpu_to_le16(bwd_size);
4429 
4430 	status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4431 				       cmd_details);
4432 
4433 	return status;
4434 }
4435 
4436 /**
4437  * i40e_read_phy_register_clause22
4438  * @hw: pointer to the HW structure
4439  * @reg: register address in the page
4440  * @phy_adr: PHY address on MDIO interface
4441  * @value: PHY register value
4442  *
4443  * Reads specified PHY register value
4444  **/
4445 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4446 					    u16 reg, u8 phy_addr, u16 *value)
4447 {
4448 	i40e_status status = I40E_ERR_TIMEOUT;
4449 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
4450 	u32 command = 0;
4451 	u16 retry = 1000;
4452 
4453 	command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4454 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4455 		  (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4456 		  (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4457 		  (I40E_GLGEN_MSCA_MDICMD_MASK);
4458 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4459 	do {
4460 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4461 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4462 			status = 0;
4463 			break;
4464 		}
4465 		udelay(10);
4466 		retry--;
4467 	} while (retry);
4468 
4469 	if (status) {
4470 		i40e_debug(hw, I40E_DEBUG_PHY,
4471 			   "PHY: Can't write command to external PHY.\n");
4472 	} else {
4473 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4474 		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4475 			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4476 	}
4477 
4478 	return status;
4479 }
4480 
4481 /**
4482  * i40e_write_phy_register_clause22
4483  * @hw: pointer to the HW structure
4484  * @reg: register address in the page
4485  * @phy_adr: PHY address on MDIO interface
4486  * @value: PHY register value
4487  *
4488  * Writes specified PHY register value
4489  **/
4490 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4491 					     u16 reg, u8 phy_addr, u16 value)
4492 {
4493 	i40e_status status = I40E_ERR_TIMEOUT;
4494 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
4495 	u32 command  = 0;
4496 	u16 retry = 1000;
4497 
4498 	command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4499 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4500 
4501 	command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4502 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4503 		  (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4504 		  (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4505 		  (I40E_GLGEN_MSCA_MDICMD_MASK);
4506 
4507 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4508 	do {
4509 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4510 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4511 			status = 0;
4512 			break;
4513 		}
4514 		udelay(10);
4515 		retry--;
4516 	} while (retry);
4517 
4518 	return status;
4519 }
4520 
4521 /**
4522  * i40e_read_phy_register_clause45
4523  * @hw: pointer to the HW structure
4524  * @page: registers page number
4525  * @reg: register address in the page
4526  * @phy_adr: PHY address on MDIO interface
4527  * @value: PHY register value
4528  *
4529  * Reads specified PHY register value
4530  **/
4531 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4532 				u8 page, u16 reg, u8 phy_addr, u16 *value)
4533 {
4534 	i40e_status status = I40E_ERR_TIMEOUT;
4535 	u32 command = 0;
4536 	u16 retry = 1000;
4537 	u8 port_num = hw->func_caps.mdio_port_num;
4538 
4539 	command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4540 		  (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4541 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4542 		  (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4543 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4544 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
4545 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4546 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4547 	do {
4548 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4549 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4550 			status = 0;
4551 			break;
4552 		}
4553 		usleep_range(10, 20);
4554 		retry--;
4555 	} while (retry);
4556 
4557 	if (status) {
4558 		i40e_debug(hw, I40E_DEBUG_PHY,
4559 			   "PHY: Can't write command to external PHY.\n");
4560 		goto phy_read_end;
4561 	}
4562 
4563 	command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4564 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4565 		  (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4566 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4567 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
4568 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4569 	status = I40E_ERR_TIMEOUT;
4570 	retry = 1000;
4571 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4572 	do {
4573 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4574 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4575 			status = 0;
4576 			break;
4577 		}
4578 		usleep_range(10, 20);
4579 		retry--;
4580 	} while (retry);
4581 
4582 	if (!status) {
4583 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4584 		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4585 			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4586 	} else {
4587 		i40e_debug(hw, I40E_DEBUG_PHY,
4588 			   "PHY: Can't read register value from external PHY.\n");
4589 	}
4590 
4591 phy_read_end:
4592 	return status;
4593 }
4594 
4595 /**
4596  * i40e_write_phy_register_clause45
4597  * @hw: pointer to the HW structure
4598  * @page: registers page number
4599  * @reg: register address in the page
4600  * @phy_adr: PHY address on MDIO interface
4601  * @value: PHY register value
4602  *
4603  * Writes value to specified PHY register
4604  **/
4605 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4606 				u8 page, u16 reg, u8 phy_addr, u16 value)
4607 {
4608 	i40e_status status = I40E_ERR_TIMEOUT;
4609 	u32 command = 0;
4610 	u16 retry = 1000;
4611 	u8 port_num = hw->func_caps.mdio_port_num;
4612 
4613 	command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4614 		  (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4615 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4616 		  (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4617 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4618 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
4619 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4620 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4621 	do {
4622 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4623 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4624 			status = 0;
4625 			break;
4626 		}
4627 		usleep_range(10, 20);
4628 		retry--;
4629 	} while (retry);
4630 	if (status) {
4631 		i40e_debug(hw, I40E_DEBUG_PHY,
4632 			   "PHY: Can't write command to external PHY.\n");
4633 		goto phy_write_end;
4634 	}
4635 
4636 	command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4637 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4638 
4639 	command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4640 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4641 		  (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4642 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4643 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
4644 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4645 	status = I40E_ERR_TIMEOUT;
4646 	retry = 1000;
4647 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4648 	do {
4649 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4650 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4651 			status = 0;
4652 			break;
4653 		}
4654 		usleep_range(10, 20);
4655 		retry--;
4656 	} while (retry);
4657 
4658 phy_write_end:
4659 	return status;
4660 }
4661 
4662 /**
4663  * i40e_write_phy_register
4664  * @hw: pointer to the HW structure
4665  * @page: registers page number
4666  * @reg: register address in the page
4667  * @phy_adr: PHY address on MDIO interface
4668  * @value: PHY register value
4669  *
4670  * Writes value to specified PHY register
4671  **/
4672 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4673 				    u8 page, u16 reg, u8 phy_addr, u16 value)
4674 {
4675 	i40e_status status;
4676 
4677 	switch (hw->device_id) {
4678 	case I40E_DEV_ID_1G_BASE_T_X722:
4679 		status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4680 							  value);
4681 		break;
4682 	case I40E_DEV_ID_10G_BASE_T:
4683 	case I40E_DEV_ID_10G_BASE_T4:
4684 	case I40E_DEV_ID_10G_BASE_T_X722:
4685 	case I40E_DEV_ID_25G_B:
4686 	case I40E_DEV_ID_25G_SFP28:
4687 		status = i40e_write_phy_register_clause45(hw, page, reg,
4688 							  phy_addr, value);
4689 		break;
4690 	default:
4691 		status = I40E_ERR_UNKNOWN_PHY;
4692 		break;
4693 	}
4694 
4695 	return status;
4696 }
4697 
4698 /**
4699  * i40e_read_phy_register
4700  * @hw: pointer to the HW structure
4701  * @page: registers page number
4702  * @reg: register address in the page
4703  * @phy_adr: PHY address on MDIO interface
4704  * @value: PHY register value
4705  *
4706  * Reads specified PHY register value
4707  **/
4708 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4709 				   u8 page, u16 reg, u8 phy_addr, u16 *value)
4710 {
4711 	i40e_status status;
4712 
4713 	switch (hw->device_id) {
4714 	case I40E_DEV_ID_1G_BASE_T_X722:
4715 		status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4716 							 value);
4717 		break;
4718 	case I40E_DEV_ID_10G_BASE_T:
4719 	case I40E_DEV_ID_10G_BASE_T4:
4720 	case I40E_DEV_ID_10G_BASE_T_X722:
4721 	case I40E_DEV_ID_25G_B:
4722 	case I40E_DEV_ID_25G_SFP28:
4723 		status = i40e_read_phy_register_clause45(hw, page, reg,
4724 							 phy_addr, value);
4725 		break;
4726 	default:
4727 		status = I40E_ERR_UNKNOWN_PHY;
4728 		break;
4729 	}
4730 
4731 	return status;
4732 }
4733 
4734 /**
4735  * i40e_get_phy_address
4736  * @hw: pointer to the HW structure
4737  * @dev_num: PHY port num that address we want
4738  * @phy_addr: Returned PHY address
4739  *
4740  * Gets PHY address for current port
4741  **/
4742 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4743 {
4744 	u8 port_num = hw->func_caps.mdio_port_num;
4745 	u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4746 
4747 	return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4748 }
4749 
4750 /**
4751  * i40e_blink_phy_led
4752  * @hw: pointer to the HW structure
4753  * @time: time how long led will blinks in secs
4754  * @interval: gap between LED on and off in msecs
4755  *
4756  * Blinks PHY link LED
4757  **/
4758 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4759 				    u32 time, u32 interval)
4760 {
4761 	i40e_status status = 0;
4762 	u32 i;
4763 	u16 led_ctl;
4764 	u16 gpio_led_port;
4765 	u16 led_reg;
4766 	u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4767 	u8 phy_addr = 0;
4768 	u8 port_num;
4769 
4770 	i = rd32(hw, I40E_PFGEN_PORTNUM);
4771 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4772 	phy_addr = i40e_get_phy_address(hw, port_num);
4773 
4774 	for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4775 	     led_addr++) {
4776 		status = i40e_read_phy_register_clause45(hw,
4777 							 I40E_PHY_COM_REG_PAGE,
4778 							 led_addr, phy_addr,
4779 							 &led_reg);
4780 		if (status)
4781 			goto phy_blinking_end;
4782 		led_ctl = led_reg;
4783 		if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4784 			led_reg = 0;
4785 			status = i40e_write_phy_register_clause45(hw,
4786 							 I40E_PHY_COM_REG_PAGE,
4787 							 led_addr, phy_addr,
4788 							 led_reg);
4789 			if (status)
4790 				goto phy_blinking_end;
4791 			break;
4792 		}
4793 	}
4794 
4795 	if (time > 0 && interval > 0) {
4796 		for (i = 0; i < time * 1000; i += interval) {
4797 			status = i40e_read_phy_register_clause45(hw,
4798 						I40E_PHY_COM_REG_PAGE,
4799 						led_addr, phy_addr, &led_reg);
4800 			if (status)
4801 				goto restore_config;
4802 			if (led_reg & I40E_PHY_LED_MANUAL_ON)
4803 				led_reg = 0;
4804 			else
4805 				led_reg = I40E_PHY_LED_MANUAL_ON;
4806 			status = i40e_write_phy_register_clause45(hw,
4807 						I40E_PHY_COM_REG_PAGE,
4808 						led_addr, phy_addr, led_reg);
4809 			if (status)
4810 				goto restore_config;
4811 			msleep(interval);
4812 		}
4813 	}
4814 
4815 restore_config:
4816 	status = i40e_write_phy_register_clause45(hw,
4817 						  I40E_PHY_COM_REG_PAGE,
4818 						  led_addr, phy_addr, led_ctl);
4819 
4820 phy_blinking_end:
4821 	return status;
4822 }
4823 
4824 /**
4825  * i40e_led_get_phy - return current on/off mode
4826  * @hw: pointer to the hw struct
4827  * @led_addr: address of led register to use
4828  * @val: original value of register to use
4829  *
4830  **/
4831 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4832 			     u16 *val)
4833 {
4834 	i40e_status status = 0;
4835 	u16 gpio_led_port;
4836 	u8 phy_addr = 0;
4837 	u16 reg_val;
4838 	u16 temp_addr;
4839 	u8 port_num;
4840 	u32 i;
4841 
4842 	temp_addr = I40E_PHY_LED_PROV_REG_1;
4843 	i = rd32(hw, I40E_PFGEN_PORTNUM);
4844 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4845 	phy_addr = i40e_get_phy_address(hw, port_num);
4846 
4847 	for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4848 	     temp_addr++) {
4849 		status = i40e_read_phy_register_clause45(hw,
4850 							 I40E_PHY_COM_REG_PAGE,
4851 							 temp_addr, phy_addr,
4852 							 &reg_val);
4853 		if (status)
4854 			return status;
4855 		*val = reg_val;
4856 		if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4857 			*led_addr = temp_addr;
4858 			break;
4859 		}
4860 	}
4861 	return status;
4862 }
4863 
4864 /**
4865  * i40e_led_set_phy
4866  * @hw: pointer to the HW structure
4867  * @on: true or false
4868  * @mode: original val plus bit for set or ignore
4869  * Set led's on or off when controlled by the PHY
4870  *
4871  **/
4872 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4873 			     u16 led_addr, u32 mode)
4874 {
4875 	i40e_status status = 0;
4876 	u16 led_ctl = 0;
4877 	u16 led_reg = 0;
4878 	u8 phy_addr = 0;
4879 	u8 port_num;
4880 	u32 i;
4881 
4882 	i = rd32(hw, I40E_PFGEN_PORTNUM);
4883 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4884 	phy_addr = i40e_get_phy_address(hw, port_num);
4885 	status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4886 						 led_addr, phy_addr, &led_reg);
4887 	if (status)
4888 		return status;
4889 	led_ctl = led_reg;
4890 	if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4891 		led_reg = 0;
4892 		status = i40e_write_phy_register_clause45(hw,
4893 							  I40E_PHY_COM_REG_PAGE,
4894 							  led_addr, phy_addr,
4895 							  led_reg);
4896 		if (status)
4897 			return status;
4898 	}
4899 	status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4900 						 led_addr, phy_addr, &led_reg);
4901 	if (status)
4902 		goto restore_config;
4903 	if (on)
4904 		led_reg = I40E_PHY_LED_MANUAL_ON;
4905 	else
4906 		led_reg = 0;
4907 	status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4908 						  led_addr, phy_addr, led_reg);
4909 	if (status)
4910 		goto restore_config;
4911 	if (mode & I40E_PHY_LED_MODE_ORIG) {
4912 		led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4913 		status = i40e_write_phy_register_clause45(hw,
4914 						 I40E_PHY_COM_REG_PAGE,
4915 						 led_addr, phy_addr, led_ctl);
4916 	}
4917 	return status;
4918 restore_config:
4919 	status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4920 						  led_addr, phy_addr, led_ctl);
4921 	return status;
4922 }
4923 
4924 /**
4925  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4926  * @hw: pointer to the hw struct
4927  * @reg_addr: register address
4928  * @reg_val: ptr to register value
4929  * @cmd_details: pointer to command details structure or NULL
4930  *
4931  * Use the firmware to read the Rx control register,
4932  * especially useful if the Rx unit is under heavy pressure
4933  **/
4934 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4935 				u32 reg_addr, u32 *reg_val,
4936 				struct i40e_asq_cmd_details *cmd_details)
4937 {
4938 	struct i40e_aq_desc desc;
4939 	struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4940 		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4941 	i40e_status status;
4942 
4943 	if (!reg_val)
4944 		return I40E_ERR_PARAM;
4945 
4946 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4947 
4948 	cmd_resp->address = cpu_to_le32(reg_addr);
4949 
4950 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4951 
4952 	if (status == 0)
4953 		*reg_val = le32_to_cpu(cmd_resp->value);
4954 
4955 	return status;
4956 }
4957 
4958 /**
4959  * i40e_read_rx_ctl - read from an Rx control register
4960  * @hw: pointer to the hw struct
4961  * @reg_addr: register address
4962  **/
4963 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4964 {
4965 	i40e_status status = 0;
4966 	bool use_register;
4967 	int retry = 5;
4968 	u32 val = 0;
4969 
4970 	use_register = (((hw->aq.api_maj_ver == 1) &&
4971 			(hw->aq.api_min_ver < 5)) ||
4972 			(hw->mac.type == I40E_MAC_X722));
4973 	if (!use_register) {
4974 do_retry:
4975 		status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4976 		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4977 			usleep_range(1000, 2000);
4978 			retry--;
4979 			goto do_retry;
4980 		}
4981 	}
4982 
4983 	/* if the AQ access failed, try the old-fashioned way */
4984 	if (status || use_register)
4985 		val = rd32(hw, reg_addr);
4986 
4987 	return val;
4988 }
4989 
4990 /**
4991  * i40e_aq_rx_ctl_write_register
4992  * @hw: pointer to the hw struct
4993  * @reg_addr: register address
4994  * @reg_val: register value
4995  * @cmd_details: pointer to command details structure or NULL
4996  *
4997  * Use the firmware to write to an Rx control register,
4998  * especially useful if the Rx unit is under heavy pressure
4999  **/
5000 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5001 				u32 reg_addr, u32 reg_val,
5002 				struct i40e_asq_cmd_details *cmd_details)
5003 {
5004 	struct i40e_aq_desc desc;
5005 	struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5006 		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5007 	i40e_status status;
5008 
5009 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5010 
5011 	cmd->address = cpu_to_le32(reg_addr);
5012 	cmd->value = cpu_to_le32(reg_val);
5013 
5014 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5015 
5016 	return status;
5017 }
5018 
5019 /**
5020  * i40e_write_rx_ctl - write to an Rx control register
5021  * @hw: pointer to the hw struct
5022  * @reg_addr: register address
5023  * @reg_val: register value
5024  **/
5025 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5026 {
5027 	i40e_status status = 0;
5028 	bool use_register;
5029 	int retry = 5;
5030 
5031 	use_register = (((hw->aq.api_maj_ver == 1) &&
5032 			(hw->aq.api_min_ver < 5)) ||
5033 			(hw->mac.type == I40E_MAC_X722));
5034 	if (!use_register) {
5035 do_retry:
5036 		status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5037 						       reg_val, NULL);
5038 		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5039 			usleep_range(1000, 2000);
5040 			retry--;
5041 			goto do_retry;
5042 		}
5043 	}
5044 
5045 	/* if the AQ access failed, try the old-fashioned way */
5046 	if (status || use_register)
5047 		wr32(hw, reg_addr, reg_val);
5048 }
5049 
5050 /**
5051  * i40e_aq_write_ppp - Write pipeline personalization profile (ppp)
5052  * @hw: pointer to the hw struct
5053  * @buff: command buffer (size in bytes = buff_size)
5054  * @buff_size: buffer size in bytes
5055  * @track_id: package tracking id
5056  * @error_offset: returns error offset
5057  * @error_info: returns error information
5058  * @cmd_details: pointer to command details structure or NULL
5059  **/
5060 enum
5061 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff,
5062 				   u16 buff_size, u32 track_id,
5063 				   u32 *error_offset, u32 *error_info,
5064 				   struct i40e_asq_cmd_details *cmd_details)
5065 {
5066 	struct i40e_aq_desc desc;
5067 	struct i40e_aqc_write_personalization_profile *cmd =
5068 		(struct i40e_aqc_write_personalization_profile *)
5069 		&desc.params.raw;
5070 	struct i40e_aqc_write_ppp_resp *resp;
5071 	i40e_status status;
5072 
5073 	i40e_fill_default_direct_cmd_desc(&desc,
5074 					  i40e_aqc_opc_write_personalization_profile);
5075 
5076 	desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5077 	if (buff_size > I40E_AQ_LARGE_BUF)
5078 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5079 
5080 	desc.datalen = cpu_to_le16(buff_size);
5081 
5082 	cmd->profile_track_id = cpu_to_le32(track_id);
5083 
5084 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5085 	if (!status) {
5086 		resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw;
5087 		if (error_offset)
5088 			*error_offset = le32_to_cpu(resp->error_offset);
5089 		if (error_info)
5090 			*error_info = le32_to_cpu(resp->error_info);
5091 	}
5092 
5093 	return status;
5094 }
5095 
5096 /**
5097  * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp)
5098  * @hw: pointer to the hw struct
5099  * @buff: command buffer (size in bytes = buff_size)
5100  * @buff_size: buffer size in bytes
5101  * @cmd_details: pointer to command details structure or NULL
5102  **/
5103 enum
5104 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff,
5105 				      u16 buff_size, u8 flags,
5106 				      struct i40e_asq_cmd_details *cmd_details)
5107 {
5108 	struct i40e_aq_desc desc;
5109 	struct i40e_aqc_get_applied_profiles *cmd =
5110 		(struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5111 	i40e_status status;
5112 
5113 	i40e_fill_default_direct_cmd_desc(&desc,
5114 					  i40e_aqc_opc_get_personalization_profile_list);
5115 
5116 	desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5117 	if (buff_size > I40E_AQ_LARGE_BUF)
5118 		desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5119 	desc.datalen = cpu_to_le16(buff_size);
5120 
5121 	cmd->flags = flags;
5122 
5123 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5124 
5125 	return status;
5126 }
5127 
5128 /**
5129  * i40e_find_segment_in_package
5130  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5131  * @pkg_hdr: pointer to the package header to be searched
5132  *
5133  * This function searches a package file for a particular segment type. On
5134  * success it returns a pointer to the segment header, otherwise it will
5135  * return NULL.
5136  **/
5137 struct i40e_generic_seg_header *
5138 i40e_find_segment_in_package(u32 segment_type,
5139 			     struct i40e_package_header *pkg_hdr)
5140 {
5141 	struct i40e_generic_seg_header *segment;
5142 	u32 i;
5143 
5144 	/* Search all package segments for the requested segment type */
5145 	for (i = 0; i < pkg_hdr->segment_count; i++) {
5146 		segment =
5147 			(struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5148 			 pkg_hdr->segment_offset[i]);
5149 
5150 		if (segment->type == segment_type)
5151 			return segment;
5152 	}
5153 
5154 	return NULL;
5155 }
5156 
5157 /**
5158  * i40e_write_profile
5159  * @hw: pointer to the hardware structure
5160  * @profile: pointer to the profile segment of the package to be downloaded
5161  * @track_id: package tracking id
5162  *
5163  * Handles the download of a complete package.
5164  */
5165 enum i40e_status_code
5166 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5167 		   u32 track_id)
5168 {
5169 	i40e_status status = 0;
5170 	struct i40e_section_table *sec_tbl;
5171 	struct i40e_profile_section_header *sec = NULL;
5172 	u32 dev_cnt;
5173 	u32 vendor_dev_id;
5174 	u32 *nvm;
5175 	u32 section_size = 0;
5176 	u32 offset = 0, info = 0;
5177 	u32 i;
5178 
5179 	if (!track_id) {
5180 		i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
5181 		return I40E_NOT_SUPPORTED;
5182 	}
5183 
5184 	dev_cnt = profile->device_table_count;
5185 
5186 	for (i = 0; i < dev_cnt; i++) {
5187 		vendor_dev_id = profile->device_table[i].vendor_dev_id;
5188 		if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
5189 			if (hw->device_id == (vendor_dev_id & 0xFFFF))
5190 				break;
5191 	}
5192 	if (i == dev_cnt) {
5193 		i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP");
5194 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
5195 	}
5196 
5197 	nvm = (u32 *)&profile->device_table[dev_cnt];
5198 	sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
5199 
5200 	for (i = 0; i < sec_tbl->section_count; i++) {
5201 		sec = (struct i40e_profile_section_header *)((u8 *)profile +
5202 					     sec_tbl->section_offset[i]);
5203 
5204 		/* Skip 'AQ', 'note' and 'name' sections */
5205 		if (sec->section.type != SECTION_TYPE_MMIO)
5206 			continue;
5207 
5208 		section_size = sec->section.size +
5209 			sizeof(struct i40e_profile_section_header);
5210 
5211 		/* Write profile */
5212 		status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size,
5213 					   track_id, &offset, &info, NULL);
5214 		if (status) {
5215 			i40e_debug(hw, I40E_DEBUG_PACKAGE,
5216 				   "Failed to write profile: offset %d, info %d",
5217 				   offset, info);
5218 			break;
5219 		}
5220 	}
5221 	return status;
5222 }
5223 
5224 /**
5225  * i40e_add_pinfo_to_list
5226  * @hw: pointer to the hardware structure
5227  * @profile: pointer to the profile segment of the package
5228  * @profile_info_sec: buffer for information section
5229  * @track_id: package tracking id
5230  *
5231  * Register a profile to the list of loaded profiles.
5232  */
5233 enum i40e_status_code
5234 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5235 		       struct i40e_profile_segment *profile,
5236 		       u8 *profile_info_sec, u32 track_id)
5237 {
5238 	i40e_status status = 0;
5239 	struct i40e_profile_section_header *sec = NULL;
5240 	struct i40e_profile_info *pinfo;
5241 	u32 offset = 0, info = 0;
5242 
5243 	sec = (struct i40e_profile_section_header *)profile_info_sec;
5244 	sec->tbl_size = 1;
5245 	sec->data_end = sizeof(struct i40e_profile_section_header) +
5246 			sizeof(struct i40e_profile_info);
5247 	sec->section.type = SECTION_TYPE_INFO;
5248 	sec->section.offset = sizeof(struct i40e_profile_section_header);
5249 	sec->section.size = sizeof(struct i40e_profile_info);
5250 	pinfo = (struct i40e_profile_info *)(profile_info_sec +
5251 					     sec->section.offset);
5252 	pinfo->track_id = track_id;
5253 	pinfo->version = profile->version;
5254 	pinfo->op = I40E_PPP_ADD_TRACKID;
5255 	memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE);
5256 
5257 	status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end,
5258 				   track_id, &offset, &info, NULL);
5259 	return status;
5260 }
5261