1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include <linux/avf/virtchnl.h> 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 304 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 305 return; 306 307 len = le16_to_cpu(aq_desc->datalen); 308 309 i40e_debug(hw, mask, 310 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 311 le16_to_cpu(aq_desc->opcode), 312 le16_to_cpu(aq_desc->flags), 313 le16_to_cpu(aq_desc->datalen), 314 le16_to_cpu(aq_desc->retval)); 315 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 316 le32_to_cpu(aq_desc->cookie_high), 317 le32_to_cpu(aq_desc->cookie_low)); 318 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->params.internal.param0), 320 le32_to_cpu(aq_desc->params.internal.param1)); 321 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.external.addr_high), 323 le32_to_cpu(aq_desc->params.external.addr_low)); 324 325 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 326 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 327 if (buf_len < len) 328 len = buf_len; 329 /* write the full 16-byte chunks */ 330 if (hw->debug_mask & mask) { 331 char prefix[27]; 332 333 snprintf(prefix, sizeof(prefix), 334 "i40e %02x:%02x.%x: \t0x", 335 hw->bus.bus_id, 336 hw->bus.device, 337 hw->bus.func); 338 339 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 340 16, 1, buf, len, false); 341 } 342 } 343 } 344 345 /** 346 * i40e_check_asq_alive 347 * @hw: pointer to the hw struct 348 * 349 * Returns true if Queue is enabled else false. 350 **/ 351 bool i40e_check_asq_alive(struct i40e_hw *hw) 352 { 353 if (hw->aq.asq.len) 354 return !!(rd32(hw, hw->aq.asq.len) & 355 I40E_PF_ATQLEN_ATQENABLE_MASK); 356 else 357 return false; 358 } 359 360 /** 361 * i40e_aq_queue_shutdown 362 * @hw: pointer to the hw struct 363 * @unloading: is the driver unloading itself 364 * 365 * Tell the Firmware that we're shutting down the AdminQ and whether 366 * or not the driver is unloading as well. 367 **/ 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 369 bool unloading) 370 { 371 struct i40e_aq_desc desc; 372 struct i40e_aqc_queue_shutdown *cmd = 373 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 374 i40e_status status; 375 376 i40e_fill_default_direct_cmd_desc(&desc, 377 i40e_aqc_opc_queue_shutdown); 378 379 if (unloading) 380 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 381 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 382 383 return status; 384 } 385 386 /** 387 * i40e_aq_get_set_rss_lut 388 * @hw: pointer to the hardware structure 389 * @vsi_id: vsi fw index 390 * @pf_lut: for PF table set true, for VSI table set false 391 * @lut: pointer to the lut buffer provided by the caller 392 * @lut_size: size of the lut buffer 393 * @set: set true to set the table, false to get the table 394 * 395 * Internal function to get or set RSS look up table 396 **/ 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 398 u16 vsi_id, bool pf_lut, 399 u8 *lut, u16 lut_size, 400 bool set) 401 { 402 i40e_status status; 403 struct i40e_aq_desc desc; 404 struct i40e_aqc_get_set_rss_lut *cmd_resp = 405 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 406 407 if (set) 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_set_rss_lut); 410 else 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_get_rss_lut); 413 414 /* Indirect command */ 415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 417 418 cmd_resp->vsi_id = 419 cpu_to_le16((u16)((vsi_id << 420 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 422 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 423 424 if (pf_lut) 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 else 430 cmd_resp->flags |= cpu_to_le16((u16) 431 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 433 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 434 435 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 436 437 return status; 438 } 439 440 /** 441 * i40e_aq_get_rss_lut 442 * @hw: pointer to the hardware structure 443 * @vsi_id: vsi fw index 444 * @pf_lut: for PF table set true, for VSI table set false 445 * @lut: pointer to the lut buffer provided by the caller 446 * @lut_size: size of the lut buffer 447 * 448 * get the RSS lookup table, PF or VSI type 449 **/ 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 451 bool pf_lut, u8 *lut, u16 lut_size) 452 { 453 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 454 false); 455 } 456 457 /** 458 * i40e_aq_set_rss_lut 459 * @hw: pointer to the hardware structure 460 * @vsi_id: vsi fw index 461 * @pf_lut: for PF table set true, for VSI table set false 462 * @lut: pointer to the lut buffer provided by the caller 463 * @lut_size: size of the lut buffer 464 * 465 * set the RSS lookup table, PF or VSI type 466 **/ 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 468 bool pf_lut, u8 *lut, u16 lut_size) 469 { 470 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 471 } 472 473 /** 474 * i40e_aq_get_set_rss_key 475 * @hw: pointer to the hw struct 476 * @vsi_id: vsi fw index 477 * @key: pointer to key info struct 478 * @set: set true to set the key, false to get the key 479 * 480 * get the RSS key per VSI 481 **/ 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 483 u16 vsi_id, 484 struct i40e_aqc_get_set_rss_key_data *key, 485 bool set) 486 { 487 i40e_status status; 488 struct i40e_aq_desc desc; 489 struct i40e_aqc_get_set_rss_key *cmd_resp = 490 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 491 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 492 493 if (set) 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_set_rss_key); 496 else 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_get_rss_key); 499 500 /* Indirect command */ 501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 503 504 cmd_resp->vsi_id = 505 cpu_to_le16((u16)((vsi_id << 506 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 507 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 508 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 509 510 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 511 512 return status; 513 } 514 515 /** 516 * i40e_aq_get_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 **/ 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key) 525 { 526 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 527 } 528 529 /** 530 * i40e_aq_set_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 * set the RSS key per VSI 536 **/ 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 538 u16 vsi_id, 539 struct i40e_aqc_get_set_rss_key_data *key) 540 { 541 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 542 } 543 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 545 * hardware to a bit-field that can be used by SW to more easily determine the 546 * packet type. 547 * 548 * Macros are used to shorten the table lines and make this table human 549 * readable. 550 * 551 * We store the PTYPE in the top byte of the bit field - this is just so that 552 * we can check that the table doesn't have a row missing, as the index into 553 * the table should be the PTYPE. 554 * 555 * Typical work flow: 556 * 557 * IF NOT i40e_ptype_lookup[ptype].known 558 * THEN 559 * Packet is unknown 560 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 561 * Use the rest of the fields to look at the tunnels, inner protocols, etc 562 * ELSE 563 * Use the enum i40e_rx_l2_ptype to decode the packet type 564 * ENDIF 565 */ 566 567 /* macro to make the table lines short */ 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 569 { PTYPE, \ 570 1, \ 571 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 572 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 573 I40E_RX_PTYPE_##OUTER_FRAG, \ 574 I40E_RX_PTYPE_TUNNEL_##T, \ 575 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 576 I40E_RX_PTYPE_##TEF, \ 577 I40E_RX_PTYPE_INNER_PROT_##I, \ 578 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 579 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 581 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 582 583 /* shorter macros makes the table fit but are terse */ 584 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 585 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 586 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 587 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 590 /* L2 Packet types */ 591 I40E_PTT_UNUSED_ENTRY(0), 592 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 594 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT_UNUSED_ENTRY(4), 596 I40E_PTT_UNUSED_ENTRY(5), 597 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT_UNUSED_ENTRY(8), 600 I40E_PTT_UNUSED_ENTRY(9), 601 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 603 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 614 /* Non Tunneled IPv4 */ 615 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 616 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 617 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(25), 619 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 620 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 621 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 622 623 /* IPv4 --> IPv4 */ 624 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 625 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 626 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(32), 628 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 629 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 630 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 631 632 /* IPv4 --> IPv6 */ 633 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 634 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 635 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 636 I40E_PTT_UNUSED_ENTRY(39), 637 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 638 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 639 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 640 641 /* IPv4 --> GRE/NAT */ 642 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 643 644 /* IPv4 --> GRE/NAT --> IPv4 */ 645 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(47), 649 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> GRE/NAT --> IPv6 */ 654 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(54), 658 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT --> MAC */ 663 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 666 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(62), 670 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 675 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(69), 679 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 684 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 687 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(77), 691 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 696 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(84), 700 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 703 704 /* Non Tunneled IPv6 */ 705 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 706 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 707 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 708 I40E_PTT_UNUSED_ENTRY(91), 709 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 710 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 711 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 712 713 /* IPv6 --> IPv4 */ 714 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 715 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 716 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 717 I40E_PTT_UNUSED_ENTRY(98), 718 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 719 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 720 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 721 722 /* IPv6 --> IPv6 */ 723 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 724 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 725 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(105), 727 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 728 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 729 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 730 731 /* IPv6 --> GRE/NAT */ 732 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 733 734 /* IPv6 --> GRE/NAT -> IPv4 */ 735 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(113), 739 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> GRE/NAT -> IPv6 */ 744 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(120), 748 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT -> MAC */ 753 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 756 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(128), 760 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 765 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(135), 769 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 774 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 777 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(143), 781 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 786 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(150), 790 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 793 794 /* unused entries */ 795 I40E_PTT_UNUSED_ENTRY(154), 796 I40E_PTT_UNUSED_ENTRY(155), 797 I40E_PTT_UNUSED_ENTRY(156), 798 I40E_PTT_UNUSED_ENTRY(157), 799 I40E_PTT_UNUSED_ENTRY(158), 800 I40E_PTT_UNUSED_ENTRY(159), 801 802 I40E_PTT_UNUSED_ENTRY(160), 803 I40E_PTT_UNUSED_ENTRY(161), 804 I40E_PTT_UNUSED_ENTRY(162), 805 I40E_PTT_UNUSED_ENTRY(163), 806 I40E_PTT_UNUSED_ENTRY(164), 807 I40E_PTT_UNUSED_ENTRY(165), 808 I40E_PTT_UNUSED_ENTRY(166), 809 I40E_PTT_UNUSED_ENTRY(167), 810 I40E_PTT_UNUSED_ENTRY(168), 811 I40E_PTT_UNUSED_ENTRY(169), 812 813 I40E_PTT_UNUSED_ENTRY(170), 814 I40E_PTT_UNUSED_ENTRY(171), 815 I40E_PTT_UNUSED_ENTRY(172), 816 I40E_PTT_UNUSED_ENTRY(173), 817 I40E_PTT_UNUSED_ENTRY(174), 818 I40E_PTT_UNUSED_ENTRY(175), 819 I40E_PTT_UNUSED_ENTRY(176), 820 I40E_PTT_UNUSED_ENTRY(177), 821 I40E_PTT_UNUSED_ENTRY(178), 822 I40E_PTT_UNUSED_ENTRY(179), 823 824 I40E_PTT_UNUSED_ENTRY(180), 825 I40E_PTT_UNUSED_ENTRY(181), 826 I40E_PTT_UNUSED_ENTRY(182), 827 I40E_PTT_UNUSED_ENTRY(183), 828 I40E_PTT_UNUSED_ENTRY(184), 829 I40E_PTT_UNUSED_ENTRY(185), 830 I40E_PTT_UNUSED_ENTRY(186), 831 I40E_PTT_UNUSED_ENTRY(187), 832 I40E_PTT_UNUSED_ENTRY(188), 833 I40E_PTT_UNUSED_ENTRY(189), 834 835 I40E_PTT_UNUSED_ENTRY(190), 836 I40E_PTT_UNUSED_ENTRY(191), 837 I40E_PTT_UNUSED_ENTRY(192), 838 I40E_PTT_UNUSED_ENTRY(193), 839 I40E_PTT_UNUSED_ENTRY(194), 840 I40E_PTT_UNUSED_ENTRY(195), 841 I40E_PTT_UNUSED_ENTRY(196), 842 I40E_PTT_UNUSED_ENTRY(197), 843 I40E_PTT_UNUSED_ENTRY(198), 844 I40E_PTT_UNUSED_ENTRY(199), 845 846 I40E_PTT_UNUSED_ENTRY(200), 847 I40E_PTT_UNUSED_ENTRY(201), 848 I40E_PTT_UNUSED_ENTRY(202), 849 I40E_PTT_UNUSED_ENTRY(203), 850 I40E_PTT_UNUSED_ENTRY(204), 851 I40E_PTT_UNUSED_ENTRY(205), 852 I40E_PTT_UNUSED_ENTRY(206), 853 I40E_PTT_UNUSED_ENTRY(207), 854 I40E_PTT_UNUSED_ENTRY(208), 855 I40E_PTT_UNUSED_ENTRY(209), 856 857 I40E_PTT_UNUSED_ENTRY(210), 858 I40E_PTT_UNUSED_ENTRY(211), 859 I40E_PTT_UNUSED_ENTRY(212), 860 I40E_PTT_UNUSED_ENTRY(213), 861 I40E_PTT_UNUSED_ENTRY(214), 862 I40E_PTT_UNUSED_ENTRY(215), 863 I40E_PTT_UNUSED_ENTRY(216), 864 I40E_PTT_UNUSED_ENTRY(217), 865 I40E_PTT_UNUSED_ENTRY(218), 866 I40E_PTT_UNUSED_ENTRY(219), 867 868 I40E_PTT_UNUSED_ENTRY(220), 869 I40E_PTT_UNUSED_ENTRY(221), 870 I40E_PTT_UNUSED_ENTRY(222), 871 I40E_PTT_UNUSED_ENTRY(223), 872 I40E_PTT_UNUSED_ENTRY(224), 873 I40E_PTT_UNUSED_ENTRY(225), 874 I40E_PTT_UNUSED_ENTRY(226), 875 I40E_PTT_UNUSED_ENTRY(227), 876 I40E_PTT_UNUSED_ENTRY(228), 877 I40E_PTT_UNUSED_ENTRY(229), 878 879 I40E_PTT_UNUSED_ENTRY(230), 880 I40E_PTT_UNUSED_ENTRY(231), 881 I40E_PTT_UNUSED_ENTRY(232), 882 I40E_PTT_UNUSED_ENTRY(233), 883 I40E_PTT_UNUSED_ENTRY(234), 884 I40E_PTT_UNUSED_ENTRY(235), 885 I40E_PTT_UNUSED_ENTRY(236), 886 I40E_PTT_UNUSED_ENTRY(237), 887 I40E_PTT_UNUSED_ENTRY(238), 888 I40E_PTT_UNUSED_ENTRY(239), 889 890 I40E_PTT_UNUSED_ENTRY(240), 891 I40E_PTT_UNUSED_ENTRY(241), 892 I40E_PTT_UNUSED_ENTRY(242), 893 I40E_PTT_UNUSED_ENTRY(243), 894 I40E_PTT_UNUSED_ENTRY(244), 895 I40E_PTT_UNUSED_ENTRY(245), 896 I40E_PTT_UNUSED_ENTRY(246), 897 I40E_PTT_UNUSED_ENTRY(247), 898 I40E_PTT_UNUSED_ENTRY(248), 899 I40E_PTT_UNUSED_ENTRY(249), 900 901 I40E_PTT_UNUSED_ENTRY(250), 902 I40E_PTT_UNUSED_ENTRY(251), 903 I40E_PTT_UNUSED_ENTRY(252), 904 I40E_PTT_UNUSED_ENTRY(253), 905 I40E_PTT_UNUSED_ENTRY(254), 906 I40E_PTT_UNUSED_ENTRY(255) 907 }; 908 909 /** 910 * i40e_init_shared_code - Initialize the shared code 911 * @hw: pointer to hardware structure 912 * 913 * This assigns the MAC type and PHY code and inits the NVM. 914 * Does not touch the hardware. This function must be called prior to any 915 * other function in the shared code. The i40e_hw structure should be 916 * memset to 0 prior to calling this function. The following fields in 917 * hw structure should be filled in prior to calling this function: 918 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 919 * subsystem_vendor_id, and revision_id 920 **/ 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 922 { 923 i40e_status status = 0; 924 u32 port, ari, func_rid; 925 926 i40e_set_mac_type(hw); 927 928 switch (hw->mac.type) { 929 case I40E_MAC_XL710: 930 case I40E_MAC_X722: 931 break; 932 default: 933 return I40E_ERR_DEVICE_NOT_SUPPORTED; 934 } 935 936 hw->phy.get_link_info = true; 937 938 /* Determine port number and PF number*/ 939 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 940 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 941 hw->port = (u8)port; 942 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 943 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 944 func_rid = rd32(hw, I40E_PF_FUNC_RID); 945 if (ari) 946 hw->pf_id = (u8)(func_rid & 0xff); 947 else 948 hw->pf_id = (u8)(func_rid & 0x7); 949 950 if (hw->mac.type == I40E_MAC_X722) 951 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 952 953 status = i40e_init_nvm(hw); 954 return status; 955 } 956 957 /** 958 * i40e_aq_mac_address_read - Retrieve the MAC addresses 959 * @hw: pointer to the hw struct 960 * @flags: a return indicator of what addresses were added to the addr store 961 * @addrs: the requestor's mac addr store 962 * @cmd_details: pointer to command details structure or NULL 963 **/ 964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 965 u16 *flags, 966 struct i40e_aqc_mac_address_read_data *addrs, 967 struct i40e_asq_cmd_details *cmd_details) 968 { 969 struct i40e_aq_desc desc; 970 struct i40e_aqc_mac_address_read *cmd_data = 971 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 972 i40e_status status; 973 974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 975 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 976 977 status = i40e_asq_send_command(hw, &desc, addrs, 978 sizeof(*addrs), cmd_details); 979 *flags = le16_to_cpu(cmd_data->command_flags); 980 981 return status; 982 } 983 984 /** 985 * i40e_aq_mac_address_write - Change the MAC addresses 986 * @hw: pointer to the hw struct 987 * @flags: indicates which MAC to be written 988 * @mac_addr: address to write 989 * @cmd_details: pointer to command details structure or NULL 990 **/ 991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 992 u16 flags, u8 *mac_addr, 993 struct i40e_asq_cmd_details *cmd_details) 994 { 995 struct i40e_aq_desc desc; 996 struct i40e_aqc_mac_address_write *cmd_data = 997 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 998 i40e_status status; 999 1000 i40e_fill_default_direct_cmd_desc(&desc, 1001 i40e_aqc_opc_mac_address_write); 1002 cmd_data->command_flags = cpu_to_le16(flags); 1003 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1004 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1005 ((u32)mac_addr[3] << 16) | 1006 ((u32)mac_addr[4] << 8) | 1007 mac_addr[5]); 1008 1009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1010 1011 return status; 1012 } 1013 1014 /** 1015 * i40e_get_mac_addr - get MAC address 1016 * @hw: pointer to the HW structure 1017 * @mac_addr: pointer to MAC address 1018 * 1019 * Reads the adapter's MAC address from register 1020 **/ 1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1022 { 1023 struct i40e_aqc_mac_address_read_data addrs; 1024 i40e_status status; 1025 u16 flags = 0; 1026 1027 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1028 1029 if (flags & I40E_AQC_LAN_ADDR_VALID) 1030 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1031 1032 return status; 1033 } 1034 1035 /** 1036 * i40e_get_port_mac_addr - get Port MAC address 1037 * @hw: pointer to the HW structure 1038 * @mac_addr: pointer to Port MAC address 1039 * 1040 * Reads the adapter's Port MAC address 1041 **/ 1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1043 { 1044 struct i40e_aqc_mac_address_read_data addrs; 1045 i40e_status status; 1046 u16 flags = 0; 1047 1048 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1049 if (status) 1050 return status; 1051 1052 if (flags & I40E_AQC_PORT_ADDR_VALID) 1053 ether_addr_copy(mac_addr, addrs.port_mac); 1054 else 1055 status = I40E_ERR_INVALID_MAC_ADDR; 1056 1057 return status; 1058 } 1059 1060 /** 1061 * i40e_pre_tx_queue_cfg - pre tx queue configure 1062 * @hw: pointer to the HW structure 1063 * @queue: target PF queue index 1064 * @enable: state change request 1065 * 1066 * Handles hw requirement to indicate intention to enable 1067 * or disable target queue. 1068 **/ 1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1070 { 1071 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1072 u32 reg_block = 0; 1073 u32 reg_val; 1074 1075 if (abs_queue_idx >= 128) { 1076 reg_block = abs_queue_idx / 128; 1077 abs_queue_idx %= 128; 1078 } 1079 1080 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1081 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1082 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1083 1084 if (enable) 1085 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1086 else 1087 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1088 1089 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1090 } 1091 1092 /** 1093 * i40e_read_pba_string - Reads part number string from EEPROM 1094 * @hw: pointer to hardware structure 1095 * @pba_num: stores the part number string from the EEPROM 1096 * @pba_num_size: part number string buffer length 1097 * 1098 * Reads the part number string from the EEPROM. 1099 **/ 1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1101 u32 pba_num_size) 1102 { 1103 i40e_status status = 0; 1104 u16 pba_word = 0; 1105 u16 pba_size = 0; 1106 u16 pba_ptr = 0; 1107 u16 i = 0; 1108 1109 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1110 if (status || (pba_word != 0xFAFA)) { 1111 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1112 return status; 1113 } 1114 1115 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1116 if (status) { 1117 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1118 return status; 1119 } 1120 1121 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1122 if (status) { 1123 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1124 return status; 1125 } 1126 1127 /* Subtract one to get PBA word count (PBA Size word is included in 1128 * total size) 1129 */ 1130 pba_size--; 1131 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1132 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1133 return I40E_ERR_PARAM; 1134 } 1135 1136 for (i = 0; i < pba_size; i++) { 1137 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1138 if (status) { 1139 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1140 return status; 1141 } 1142 1143 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1144 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1145 } 1146 pba_num[(pba_size * 2)] = '\0'; 1147 1148 return status; 1149 } 1150 1151 /** 1152 * i40e_get_media_type - Gets media type 1153 * @hw: pointer to the hardware structure 1154 **/ 1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1156 { 1157 enum i40e_media_type media; 1158 1159 switch (hw->phy.link_info.phy_type) { 1160 case I40E_PHY_TYPE_10GBASE_SR: 1161 case I40E_PHY_TYPE_10GBASE_LR: 1162 case I40E_PHY_TYPE_1000BASE_SX: 1163 case I40E_PHY_TYPE_1000BASE_LX: 1164 case I40E_PHY_TYPE_40GBASE_SR4: 1165 case I40E_PHY_TYPE_40GBASE_LR4: 1166 case I40E_PHY_TYPE_25GBASE_LR: 1167 case I40E_PHY_TYPE_25GBASE_SR: 1168 media = I40E_MEDIA_TYPE_FIBER; 1169 break; 1170 case I40E_PHY_TYPE_100BASE_TX: 1171 case I40E_PHY_TYPE_1000BASE_T: 1172 case I40E_PHY_TYPE_10GBASE_T: 1173 media = I40E_MEDIA_TYPE_BASET; 1174 break; 1175 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1176 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1177 case I40E_PHY_TYPE_10GBASE_CR1: 1178 case I40E_PHY_TYPE_40GBASE_CR4: 1179 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1180 case I40E_PHY_TYPE_40GBASE_AOC: 1181 case I40E_PHY_TYPE_10GBASE_AOC: 1182 case I40E_PHY_TYPE_25GBASE_CR: 1183 case I40E_PHY_TYPE_25GBASE_AOC: 1184 case I40E_PHY_TYPE_25GBASE_ACC: 1185 media = I40E_MEDIA_TYPE_DA; 1186 break; 1187 case I40E_PHY_TYPE_1000BASE_KX: 1188 case I40E_PHY_TYPE_10GBASE_KX4: 1189 case I40E_PHY_TYPE_10GBASE_KR: 1190 case I40E_PHY_TYPE_40GBASE_KR4: 1191 case I40E_PHY_TYPE_20GBASE_KR2: 1192 case I40E_PHY_TYPE_25GBASE_KR: 1193 media = I40E_MEDIA_TYPE_BACKPLANE; 1194 break; 1195 case I40E_PHY_TYPE_SGMII: 1196 case I40E_PHY_TYPE_XAUI: 1197 case I40E_PHY_TYPE_XFI: 1198 case I40E_PHY_TYPE_XLAUI: 1199 case I40E_PHY_TYPE_XLPPI: 1200 default: 1201 media = I40E_MEDIA_TYPE_UNKNOWN; 1202 break; 1203 } 1204 1205 return media; 1206 } 1207 1208 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1209 #define I40E_PF_RESET_WAIT_COUNT 200 1210 /** 1211 * i40e_pf_reset - Reset the PF 1212 * @hw: pointer to the hardware structure 1213 * 1214 * Assuming someone else has triggered a global reset, 1215 * assure the global reset is complete and then reset the PF 1216 **/ 1217 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1218 { 1219 u32 cnt = 0; 1220 u32 cnt1 = 0; 1221 u32 reg = 0; 1222 u32 grst_del; 1223 1224 /* Poll for Global Reset steady state in case of recent GRST. 1225 * The grst delay value is in 100ms units, and we'll wait a 1226 * couple counts longer to be sure we don't just miss the end. 1227 */ 1228 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1229 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1230 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1231 1232 /* It can take upto 15 secs for GRST steady state. 1233 * Bump it to 16 secs max to be safe. 1234 */ 1235 grst_del = grst_del * 20; 1236 1237 for (cnt = 0; cnt < grst_del; cnt++) { 1238 reg = rd32(hw, I40E_GLGEN_RSTAT); 1239 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1240 break; 1241 msleep(100); 1242 } 1243 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1244 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1245 return I40E_ERR_RESET_FAILED; 1246 } 1247 1248 /* Now Wait for the FW to be ready */ 1249 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1250 reg = rd32(hw, I40E_GLNVM_ULD); 1251 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1252 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1253 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1254 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1255 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1256 break; 1257 } 1258 usleep_range(10000, 20000); 1259 } 1260 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1261 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1262 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1263 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1264 return I40E_ERR_RESET_FAILED; 1265 } 1266 1267 /* If there was a Global Reset in progress when we got here, 1268 * we don't need to do the PF Reset 1269 */ 1270 if (!cnt) { 1271 if (hw->revision_id == 0) 1272 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1273 else 1274 cnt = I40E_PF_RESET_WAIT_COUNT; 1275 reg = rd32(hw, I40E_PFGEN_CTRL); 1276 wr32(hw, I40E_PFGEN_CTRL, 1277 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1278 for (; cnt; cnt--) { 1279 reg = rd32(hw, I40E_PFGEN_CTRL); 1280 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1281 break; 1282 usleep_range(1000, 2000); 1283 } 1284 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1285 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1286 return I40E_ERR_RESET_FAILED; 1287 } 1288 } 1289 1290 i40e_clear_pxe_mode(hw); 1291 1292 return 0; 1293 } 1294 1295 /** 1296 * i40e_clear_hw - clear out any left over hw state 1297 * @hw: pointer to the hw struct 1298 * 1299 * Clear queues and interrupts, typically called at init time, 1300 * but after the capabilities have been found so we know how many 1301 * queues and msix vectors have been allocated. 1302 **/ 1303 void i40e_clear_hw(struct i40e_hw *hw) 1304 { 1305 u32 num_queues, base_queue; 1306 u32 num_pf_int; 1307 u32 num_vf_int; 1308 u32 num_vfs; 1309 u32 i, j; 1310 u32 val; 1311 u32 eol = 0x7ff; 1312 1313 /* get number of interrupts, queues, and VFs */ 1314 val = rd32(hw, I40E_GLPCI_CNF2); 1315 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1316 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1317 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1318 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1319 1320 val = rd32(hw, I40E_PFLAN_QALLOC); 1321 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1322 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1323 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1324 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1325 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1326 num_queues = (j - base_queue) + 1; 1327 else 1328 num_queues = 0; 1329 1330 val = rd32(hw, I40E_PF_VT_PFALLOC); 1331 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1332 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1333 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1334 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1335 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1336 num_vfs = (j - i) + 1; 1337 else 1338 num_vfs = 0; 1339 1340 /* stop all the interrupts */ 1341 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1342 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1343 for (i = 0; i < num_pf_int - 2; i++) 1344 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1345 1346 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1347 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1348 wr32(hw, I40E_PFINT_LNKLST0, val); 1349 for (i = 0; i < num_pf_int - 2; i++) 1350 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1351 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1352 for (i = 0; i < num_vfs; i++) 1353 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1354 for (i = 0; i < num_vf_int - 2; i++) 1355 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1356 1357 /* warn the HW of the coming Tx disables */ 1358 for (i = 0; i < num_queues; i++) { 1359 u32 abs_queue_idx = base_queue + i; 1360 u32 reg_block = 0; 1361 1362 if (abs_queue_idx >= 128) { 1363 reg_block = abs_queue_idx / 128; 1364 abs_queue_idx %= 128; 1365 } 1366 1367 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1368 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1369 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1370 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1371 1372 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1373 } 1374 udelay(400); 1375 1376 /* stop all the queues */ 1377 for (i = 0; i < num_queues; i++) { 1378 wr32(hw, I40E_QINT_TQCTL(i), 0); 1379 wr32(hw, I40E_QTX_ENA(i), 0); 1380 wr32(hw, I40E_QINT_RQCTL(i), 0); 1381 wr32(hw, I40E_QRX_ENA(i), 0); 1382 } 1383 1384 /* short wait for all queue disables to settle */ 1385 udelay(50); 1386 } 1387 1388 /** 1389 * i40e_clear_pxe_mode - clear pxe operations mode 1390 * @hw: pointer to the hw struct 1391 * 1392 * Make sure all PXE mode settings are cleared, including things 1393 * like descriptor fetch/write-back mode. 1394 **/ 1395 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1396 { 1397 u32 reg; 1398 1399 if (i40e_check_asq_alive(hw)) 1400 i40e_aq_clear_pxe_mode(hw, NULL); 1401 1402 /* Clear single descriptor fetch/write-back mode */ 1403 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1404 1405 if (hw->revision_id == 0) { 1406 /* As a work around clear PXE_MODE instead of setting it */ 1407 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1408 } else { 1409 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1410 } 1411 } 1412 1413 /** 1414 * i40e_led_is_mine - helper to find matching led 1415 * @hw: pointer to the hw struct 1416 * @idx: index into GPIO registers 1417 * 1418 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1419 */ 1420 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1421 { 1422 u32 gpio_val = 0; 1423 u32 port; 1424 1425 if (!hw->func_caps.led[idx]) 1426 return 0; 1427 1428 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1429 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1430 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1431 1432 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1433 * if it is not our port then ignore 1434 */ 1435 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1436 (port != hw->port)) 1437 return 0; 1438 1439 return gpio_val; 1440 } 1441 1442 #define I40E_COMBINED_ACTIVITY 0xA 1443 #define I40E_FILTER_ACTIVITY 0xE 1444 #define I40E_LINK_ACTIVITY 0xC 1445 #define I40E_MAC_ACTIVITY 0xD 1446 #define I40E_LED0 22 1447 1448 /** 1449 * i40e_led_get - return current on/off mode 1450 * @hw: pointer to the hw struct 1451 * 1452 * The value returned is the 'mode' field as defined in the 1453 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1454 * values are variations of possible behaviors relating to 1455 * blink, link, and wire. 1456 **/ 1457 u32 i40e_led_get(struct i40e_hw *hw) 1458 { 1459 u32 current_mode = 0; 1460 u32 mode = 0; 1461 int i; 1462 1463 /* as per the documentation GPIO 22-29 are the LED 1464 * GPIO pins named LED0..LED7 1465 */ 1466 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1467 u32 gpio_val = i40e_led_is_mine(hw, i); 1468 1469 if (!gpio_val) 1470 continue; 1471 1472 /* ignore gpio LED src mode entries related to the activity 1473 * LEDs 1474 */ 1475 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1476 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1477 switch (current_mode) { 1478 case I40E_COMBINED_ACTIVITY: 1479 case I40E_FILTER_ACTIVITY: 1480 case I40E_MAC_ACTIVITY: 1481 continue; 1482 default: 1483 break; 1484 } 1485 1486 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1487 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1488 break; 1489 } 1490 1491 return mode; 1492 } 1493 1494 /** 1495 * i40e_led_set - set new on/off mode 1496 * @hw: pointer to the hw struct 1497 * @mode: 0=off, 0xf=on (else see manual for mode details) 1498 * @blink: true if the LED should blink when on, false if steady 1499 * 1500 * if this function is used to turn on the blink it should 1501 * be used to disable the blink when restoring the original state. 1502 **/ 1503 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1504 { 1505 u32 current_mode = 0; 1506 int i; 1507 1508 if (mode & 0xfffffff0) 1509 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1510 1511 /* as per the documentation GPIO 22-29 are the LED 1512 * GPIO pins named LED0..LED7 1513 */ 1514 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1515 u32 gpio_val = i40e_led_is_mine(hw, i); 1516 1517 if (!gpio_val) 1518 continue; 1519 1520 /* ignore gpio LED src mode entries related to the activity 1521 * LEDs 1522 */ 1523 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1524 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1525 switch (current_mode) { 1526 case I40E_COMBINED_ACTIVITY: 1527 case I40E_FILTER_ACTIVITY: 1528 case I40E_MAC_ACTIVITY: 1529 continue; 1530 default: 1531 break; 1532 } 1533 1534 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1535 /* this & is a bit of paranoia, but serves as a range check */ 1536 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1537 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1538 1539 if (mode == I40E_LINK_ACTIVITY) 1540 blink = false; 1541 1542 if (blink) 1543 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1544 else 1545 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1546 1547 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1548 break; 1549 } 1550 } 1551 1552 /* Admin command wrappers */ 1553 1554 /** 1555 * i40e_aq_get_phy_capabilities 1556 * @hw: pointer to the hw struct 1557 * @abilities: structure for PHY capabilities to be filled 1558 * @qualified_modules: report Qualified Modules 1559 * @report_init: report init capabilities (active are default) 1560 * @cmd_details: pointer to command details structure or NULL 1561 * 1562 * Returns the various PHY abilities supported on the Port. 1563 **/ 1564 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1565 bool qualified_modules, bool report_init, 1566 struct i40e_aq_get_phy_abilities_resp *abilities, 1567 struct i40e_asq_cmd_details *cmd_details) 1568 { 1569 struct i40e_aq_desc desc; 1570 i40e_status status; 1571 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1572 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1573 1574 if (!abilities) 1575 return I40E_ERR_PARAM; 1576 1577 do { 1578 i40e_fill_default_direct_cmd_desc(&desc, 1579 i40e_aqc_opc_get_phy_abilities); 1580 1581 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1582 if (abilities_size > I40E_AQ_LARGE_BUF) 1583 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1584 1585 if (qualified_modules) 1586 desc.params.external.param0 |= 1587 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1588 1589 if (report_init) 1590 desc.params.external.param0 |= 1591 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1592 1593 status = i40e_asq_send_command(hw, &desc, abilities, 1594 abilities_size, cmd_details); 1595 1596 if (status) 1597 break; 1598 1599 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1600 status = I40E_ERR_UNKNOWN_PHY; 1601 break; 1602 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1603 usleep_range(1000, 2000); 1604 total_delay++; 1605 status = I40E_ERR_TIMEOUT; 1606 } 1607 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1608 (total_delay < max_delay)); 1609 1610 if (status) 1611 return status; 1612 1613 if (report_init) { 1614 if (hw->mac.type == I40E_MAC_XL710 && 1615 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1616 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1617 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1618 } else { 1619 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1620 hw->phy.phy_types |= 1621 ((u64)abilities->phy_type_ext << 32); 1622 } 1623 } 1624 1625 return status; 1626 } 1627 1628 /** 1629 * i40e_aq_set_phy_config 1630 * @hw: pointer to the hw struct 1631 * @config: structure with PHY configuration to be set 1632 * @cmd_details: pointer to command details structure or NULL 1633 * 1634 * Set the various PHY configuration parameters 1635 * supported on the Port.One or more of the Set PHY config parameters may be 1636 * ignored in an MFP mode as the PF may not have the privilege to set some 1637 * of the PHY Config parameters. This status will be indicated by the 1638 * command response. 1639 **/ 1640 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1641 struct i40e_aq_set_phy_config *config, 1642 struct i40e_asq_cmd_details *cmd_details) 1643 { 1644 struct i40e_aq_desc desc; 1645 struct i40e_aq_set_phy_config *cmd = 1646 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1647 enum i40e_status_code status; 1648 1649 if (!config) 1650 return I40E_ERR_PARAM; 1651 1652 i40e_fill_default_direct_cmd_desc(&desc, 1653 i40e_aqc_opc_set_phy_config); 1654 1655 *cmd = *config; 1656 1657 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1658 1659 return status; 1660 } 1661 1662 /** 1663 * i40e_set_fc 1664 * @hw: pointer to the hw struct 1665 * 1666 * Set the requested flow control mode using set_phy_config. 1667 **/ 1668 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1669 bool atomic_restart) 1670 { 1671 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1672 struct i40e_aq_get_phy_abilities_resp abilities; 1673 struct i40e_aq_set_phy_config config; 1674 enum i40e_status_code status; 1675 u8 pause_mask = 0x0; 1676 1677 *aq_failures = 0x0; 1678 1679 switch (fc_mode) { 1680 case I40E_FC_FULL: 1681 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1683 break; 1684 case I40E_FC_RX_PAUSE: 1685 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1686 break; 1687 case I40E_FC_TX_PAUSE: 1688 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1689 break; 1690 default: 1691 break; 1692 } 1693 1694 /* Get the current phy config */ 1695 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1696 NULL); 1697 if (status) { 1698 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1699 return status; 1700 } 1701 1702 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1703 /* clear the old pause settings */ 1704 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1705 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1706 /* set the new abilities */ 1707 config.abilities |= pause_mask; 1708 /* If the abilities have changed, then set the new config */ 1709 if (config.abilities != abilities.abilities) { 1710 /* Auto restart link so settings take effect */ 1711 if (atomic_restart) 1712 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1713 /* Copy over all the old settings */ 1714 config.phy_type = abilities.phy_type; 1715 config.phy_type_ext = abilities.phy_type_ext; 1716 config.link_speed = abilities.link_speed; 1717 config.eee_capability = abilities.eee_capability; 1718 config.eeer = abilities.eeer_val; 1719 config.low_power_ctrl = abilities.d3_lpan; 1720 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1721 I40E_AQ_PHY_FEC_CONFIG_MASK; 1722 status = i40e_aq_set_phy_config(hw, &config, NULL); 1723 1724 if (status) 1725 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1726 } 1727 /* Update the link info */ 1728 status = i40e_update_link_info(hw); 1729 if (status) { 1730 /* Wait a little bit (on 40G cards it sometimes takes a really 1731 * long time for link to come back from the atomic reset) 1732 * and try once more 1733 */ 1734 msleep(1000); 1735 status = i40e_update_link_info(hw); 1736 } 1737 if (status) 1738 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1739 1740 return status; 1741 } 1742 1743 /** 1744 * i40e_aq_clear_pxe_mode 1745 * @hw: pointer to the hw struct 1746 * @cmd_details: pointer to command details structure or NULL 1747 * 1748 * Tell the firmware that the driver is taking over from PXE 1749 **/ 1750 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1751 struct i40e_asq_cmd_details *cmd_details) 1752 { 1753 i40e_status status; 1754 struct i40e_aq_desc desc; 1755 struct i40e_aqc_clear_pxe *cmd = 1756 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1757 1758 i40e_fill_default_direct_cmd_desc(&desc, 1759 i40e_aqc_opc_clear_pxe_mode); 1760 1761 cmd->rx_cnt = 0x2; 1762 1763 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1764 1765 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1766 1767 return status; 1768 } 1769 1770 /** 1771 * i40e_aq_set_link_restart_an 1772 * @hw: pointer to the hw struct 1773 * @enable_link: if true: enable link, if false: disable link 1774 * @cmd_details: pointer to command details structure or NULL 1775 * 1776 * Sets up the link and restarts the Auto-Negotiation over the link. 1777 **/ 1778 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1779 bool enable_link, 1780 struct i40e_asq_cmd_details *cmd_details) 1781 { 1782 struct i40e_aq_desc desc; 1783 struct i40e_aqc_set_link_restart_an *cmd = 1784 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1785 i40e_status status; 1786 1787 i40e_fill_default_direct_cmd_desc(&desc, 1788 i40e_aqc_opc_set_link_restart_an); 1789 1790 cmd->command = I40E_AQ_PHY_RESTART_AN; 1791 if (enable_link) 1792 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1793 else 1794 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1795 1796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1797 1798 return status; 1799 } 1800 1801 /** 1802 * i40e_aq_get_link_info 1803 * @hw: pointer to the hw struct 1804 * @enable_lse: enable/disable LinkStatusEvent reporting 1805 * @link: pointer to link status structure - optional 1806 * @cmd_details: pointer to command details structure or NULL 1807 * 1808 * Returns the link status of the adapter. 1809 **/ 1810 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1811 bool enable_lse, struct i40e_link_status *link, 1812 struct i40e_asq_cmd_details *cmd_details) 1813 { 1814 struct i40e_aq_desc desc; 1815 struct i40e_aqc_get_link_status *resp = 1816 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1817 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1818 i40e_status status; 1819 bool tx_pause, rx_pause; 1820 u16 command_flags; 1821 1822 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1823 1824 if (enable_lse) 1825 command_flags = I40E_AQ_LSE_ENABLE; 1826 else 1827 command_flags = I40E_AQ_LSE_DISABLE; 1828 resp->command_flags = cpu_to_le16(command_flags); 1829 1830 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1831 1832 if (status) 1833 goto aq_get_link_info_exit; 1834 1835 /* save off old link status information */ 1836 hw->phy.link_info_old = *hw_link_info; 1837 1838 /* update link status */ 1839 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1840 hw->phy.media_type = i40e_get_media_type(hw); 1841 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1842 hw_link_info->link_info = resp->link_info; 1843 hw_link_info->an_info = resp->an_info; 1844 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1845 I40E_AQ_CONFIG_FEC_RS_ENA); 1846 hw_link_info->ext_info = resp->ext_info; 1847 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1848 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1849 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1850 1851 /* update fc info */ 1852 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1853 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1854 if (tx_pause & rx_pause) 1855 hw->fc.current_mode = I40E_FC_FULL; 1856 else if (tx_pause) 1857 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1858 else if (rx_pause) 1859 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1860 else 1861 hw->fc.current_mode = I40E_FC_NONE; 1862 1863 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1864 hw_link_info->crc_enable = true; 1865 else 1866 hw_link_info->crc_enable = false; 1867 1868 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1869 hw_link_info->lse_enable = true; 1870 else 1871 hw_link_info->lse_enable = false; 1872 1873 if ((hw->mac.type == I40E_MAC_XL710) && 1874 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1875 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1876 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1877 1878 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1879 hw->aq.api_min_ver >= 7) { 1880 __le32 tmp; 1881 1882 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1883 hw->phy.phy_types = le32_to_cpu(tmp); 1884 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1885 } 1886 1887 /* save link status information */ 1888 if (link) 1889 *link = *hw_link_info; 1890 1891 /* flag cleared so helper functions don't call AQ again */ 1892 hw->phy.get_link_info = false; 1893 1894 aq_get_link_info_exit: 1895 return status; 1896 } 1897 1898 /** 1899 * i40e_aq_set_phy_int_mask 1900 * @hw: pointer to the hw struct 1901 * @mask: interrupt mask to be set 1902 * @cmd_details: pointer to command details structure or NULL 1903 * 1904 * Set link interrupt mask. 1905 **/ 1906 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1907 u16 mask, 1908 struct i40e_asq_cmd_details *cmd_details) 1909 { 1910 struct i40e_aq_desc desc; 1911 struct i40e_aqc_set_phy_int_mask *cmd = 1912 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1913 i40e_status status; 1914 1915 i40e_fill_default_direct_cmd_desc(&desc, 1916 i40e_aqc_opc_set_phy_int_mask); 1917 1918 cmd->event_mask = cpu_to_le16(mask); 1919 1920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1921 1922 return status; 1923 } 1924 1925 /** 1926 * i40e_aq_set_phy_debug 1927 * @hw: pointer to the hw struct 1928 * @cmd_flags: debug command flags 1929 * @cmd_details: pointer to command details structure or NULL 1930 * 1931 * Reset the external PHY. 1932 **/ 1933 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1934 struct i40e_asq_cmd_details *cmd_details) 1935 { 1936 struct i40e_aq_desc desc; 1937 struct i40e_aqc_set_phy_debug *cmd = 1938 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1939 i40e_status status; 1940 1941 i40e_fill_default_direct_cmd_desc(&desc, 1942 i40e_aqc_opc_set_phy_debug); 1943 1944 cmd->command_flags = cmd_flags; 1945 1946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1947 1948 return status; 1949 } 1950 1951 /** 1952 * i40e_aq_add_vsi 1953 * @hw: pointer to the hw struct 1954 * @vsi_ctx: pointer to a vsi context struct 1955 * @cmd_details: pointer to command details structure or NULL 1956 * 1957 * Add a VSI context to the hardware. 1958 **/ 1959 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1960 struct i40e_vsi_context *vsi_ctx, 1961 struct i40e_asq_cmd_details *cmd_details) 1962 { 1963 struct i40e_aq_desc desc; 1964 struct i40e_aqc_add_get_update_vsi *cmd = 1965 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1966 struct i40e_aqc_add_get_update_vsi_completion *resp = 1967 (struct i40e_aqc_add_get_update_vsi_completion *) 1968 &desc.params.raw; 1969 i40e_status status; 1970 1971 i40e_fill_default_direct_cmd_desc(&desc, 1972 i40e_aqc_opc_add_vsi); 1973 1974 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1975 cmd->connection_type = vsi_ctx->connection_type; 1976 cmd->vf_id = vsi_ctx->vf_num; 1977 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1978 1979 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1980 1981 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1982 sizeof(vsi_ctx->info), cmd_details); 1983 1984 if (status) 1985 goto aq_add_vsi_exit; 1986 1987 vsi_ctx->seid = le16_to_cpu(resp->seid); 1988 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1989 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1990 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1991 1992 aq_add_vsi_exit: 1993 return status; 1994 } 1995 1996 /** 1997 * i40e_aq_set_default_vsi 1998 * @hw: pointer to the hw struct 1999 * @seid: vsi number 2000 * @cmd_details: pointer to command details structure or NULL 2001 **/ 2002 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2003 u16 seid, 2004 struct i40e_asq_cmd_details *cmd_details) 2005 { 2006 struct i40e_aq_desc desc; 2007 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2008 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2009 &desc.params.raw; 2010 i40e_status status; 2011 2012 i40e_fill_default_direct_cmd_desc(&desc, 2013 i40e_aqc_opc_set_vsi_promiscuous_modes); 2014 2015 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2016 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2017 cmd->seid = cpu_to_le16(seid); 2018 2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2020 2021 return status; 2022 } 2023 2024 /** 2025 * i40e_aq_clear_default_vsi 2026 * @hw: pointer to the hw struct 2027 * @seid: vsi number 2028 * @cmd_details: pointer to command details structure or NULL 2029 **/ 2030 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2031 u16 seid, 2032 struct i40e_asq_cmd_details *cmd_details) 2033 { 2034 struct i40e_aq_desc desc; 2035 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2036 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2037 &desc.params.raw; 2038 i40e_status status; 2039 2040 i40e_fill_default_direct_cmd_desc(&desc, 2041 i40e_aqc_opc_set_vsi_promiscuous_modes); 2042 2043 cmd->promiscuous_flags = cpu_to_le16(0); 2044 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2045 cmd->seid = cpu_to_le16(seid); 2046 2047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2048 2049 return status; 2050 } 2051 2052 /** 2053 * i40e_aq_set_vsi_unicast_promiscuous 2054 * @hw: pointer to the hw struct 2055 * @seid: vsi number 2056 * @set: set unicast promiscuous enable/disable 2057 * @cmd_details: pointer to command details structure or NULL 2058 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2059 **/ 2060 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2061 u16 seid, bool set, 2062 struct i40e_asq_cmd_details *cmd_details, 2063 bool rx_only_promisc) 2064 { 2065 struct i40e_aq_desc desc; 2066 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2067 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2068 i40e_status status; 2069 u16 flags = 0; 2070 2071 i40e_fill_default_direct_cmd_desc(&desc, 2072 i40e_aqc_opc_set_vsi_promiscuous_modes); 2073 2074 if (set) { 2075 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2076 if (rx_only_promisc && 2077 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2078 (hw->aq.api_maj_ver > 1))) 2079 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2080 } 2081 2082 cmd->promiscuous_flags = cpu_to_le16(flags); 2083 2084 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2085 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2086 (hw->aq.api_maj_ver > 1)) 2087 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2088 2089 cmd->seid = cpu_to_le16(seid); 2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2091 2092 return status; 2093 } 2094 2095 /** 2096 * i40e_aq_set_vsi_multicast_promiscuous 2097 * @hw: pointer to the hw struct 2098 * @seid: vsi number 2099 * @set: set multicast promiscuous enable/disable 2100 * @cmd_details: pointer to command details structure or NULL 2101 **/ 2102 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2103 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2104 { 2105 struct i40e_aq_desc desc; 2106 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2107 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2108 i40e_status status; 2109 u16 flags = 0; 2110 2111 i40e_fill_default_direct_cmd_desc(&desc, 2112 i40e_aqc_opc_set_vsi_promiscuous_modes); 2113 2114 if (set) 2115 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2116 2117 cmd->promiscuous_flags = cpu_to_le16(flags); 2118 2119 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2120 2121 cmd->seid = cpu_to_le16(seid); 2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2123 2124 return status; 2125 } 2126 2127 /** 2128 * i40e_aq_set_vsi_mc_promisc_on_vlan 2129 * @hw: pointer to the hw struct 2130 * @seid: vsi number 2131 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2132 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2133 * @cmd_details: pointer to command details structure or NULL 2134 **/ 2135 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2136 u16 seid, bool enable, 2137 u16 vid, 2138 struct i40e_asq_cmd_details *cmd_details) 2139 { 2140 struct i40e_aq_desc desc; 2141 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2142 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2143 enum i40e_status_code status; 2144 u16 flags = 0; 2145 2146 i40e_fill_default_direct_cmd_desc(&desc, 2147 i40e_aqc_opc_set_vsi_promiscuous_modes); 2148 2149 if (enable) 2150 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2151 2152 cmd->promiscuous_flags = cpu_to_le16(flags); 2153 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2154 cmd->seid = cpu_to_le16(seid); 2155 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2156 2157 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2158 2159 return status; 2160 } 2161 2162 /** 2163 * i40e_aq_set_vsi_uc_promisc_on_vlan 2164 * @hw: pointer to the hw struct 2165 * @seid: vsi number 2166 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2167 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2168 * @cmd_details: pointer to command details structure or NULL 2169 **/ 2170 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2171 u16 seid, bool enable, 2172 u16 vid, 2173 struct i40e_asq_cmd_details *cmd_details) 2174 { 2175 struct i40e_aq_desc desc; 2176 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2177 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2178 enum i40e_status_code status; 2179 u16 flags = 0; 2180 2181 i40e_fill_default_direct_cmd_desc(&desc, 2182 i40e_aqc_opc_set_vsi_promiscuous_modes); 2183 2184 if (enable) 2185 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2186 2187 cmd->promiscuous_flags = cpu_to_le16(flags); 2188 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2189 cmd->seid = cpu_to_le16(seid); 2190 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2191 2192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2193 2194 return status; 2195 } 2196 2197 /** 2198 * i40e_aq_set_vsi_bc_promisc_on_vlan 2199 * @hw: pointer to the hw struct 2200 * @seid: vsi number 2201 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2202 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2203 * @cmd_details: pointer to command details structure or NULL 2204 **/ 2205 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2206 u16 seid, bool enable, u16 vid, 2207 struct i40e_asq_cmd_details *cmd_details) 2208 { 2209 struct i40e_aq_desc desc; 2210 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2211 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2212 i40e_status status; 2213 u16 flags = 0; 2214 2215 i40e_fill_default_direct_cmd_desc(&desc, 2216 i40e_aqc_opc_set_vsi_promiscuous_modes); 2217 2218 if (enable) 2219 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2220 2221 cmd->promiscuous_flags = cpu_to_le16(flags); 2222 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2223 cmd->seid = cpu_to_le16(seid); 2224 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2225 2226 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2227 2228 return status; 2229 } 2230 2231 /** 2232 * i40e_aq_set_vsi_broadcast 2233 * @hw: pointer to the hw struct 2234 * @seid: vsi number 2235 * @set_filter: true to set filter, false to clear filter 2236 * @cmd_details: pointer to command details structure or NULL 2237 * 2238 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2239 **/ 2240 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2241 u16 seid, bool set_filter, 2242 struct i40e_asq_cmd_details *cmd_details) 2243 { 2244 struct i40e_aq_desc desc; 2245 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2246 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2247 i40e_status status; 2248 2249 i40e_fill_default_direct_cmd_desc(&desc, 2250 i40e_aqc_opc_set_vsi_promiscuous_modes); 2251 2252 if (set_filter) 2253 cmd->promiscuous_flags 2254 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2255 else 2256 cmd->promiscuous_flags 2257 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2258 2259 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2260 cmd->seid = cpu_to_le16(seid); 2261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2262 2263 return status; 2264 } 2265 2266 /** 2267 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2268 * @hw: pointer to the hw struct 2269 * @seid: vsi number 2270 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2271 * @cmd_details: pointer to command details structure or NULL 2272 **/ 2273 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2274 u16 seid, bool enable, 2275 struct i40e_asq_cmd_details *cmd_details) 2276 { 2277 struct i40e_aq_desc desc; 2278 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2279 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2280 i40e_status status; 2281 u16 flags = 0; 2282 2283 i40e_fill_default_direct_cmd_desc(&desc, 2284 i40e_aqc_opc_set_vsi_promiscuous_modes); 2285 if (enable) 2286 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2287 2288 cmd->promiscuous_flags = cpu_to_le16(flags); 2289 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2290 cmd->seid = cpu_to_le16(seid); 2291 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_get_vsi_params - get VSI configuration info 2299 * @hw: pointer to the hw struct 2300 * @vsi_ctx: pointer to a vsi context struct 2301 * @cmd_details: pointer to command details structure or NULL 2302 **/ 2303 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2304 struct i40e_vsi_context *vsi_ctx, 2305 struct i40e_asq_cmd_details *cmd_details) 2306 { 2307 struct i40e_aq_desc desc; 2308 struct i40e_aqc_add_get_update_vsi *cmd = 2309 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2310 struct i40e_aqc_add_get_update_vsi_completion *resp = 2311 (struct i40e_aqc_add_get_update_vsi_completion *) 2312 &desc.params.raw; 2313 i40e_status status; 2314 2315 i40e_fill_default_direct_cmd_desc(&desc, 2316 i40e_aqc_opc_get_vsi_parameters); 2317 2318 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2319 2320 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2321 2322 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2323 sizeof(vsi_ctx->info), NULL); 2324 2325 if (status) 2326 goto aq_get_vsi_params_exit; 2327 2328 vsi_ctx->seid = le16_to_cpu(resp->seid); 2329 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2330 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2331 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2332 2333 aq_get_vsi_params_exit: 2334 return status; 2335 } 2336 2337 /** 2338 * i40e_aq_update_vsi_params 2339 * @hw: pointer to the hw struct 2340 * @vsi_ctx: pointer to a vsi context struct 2341 * @cmd_details: pointer to command details structure or NULL 2342 * 2343 * Update a VSI context. 2344 **/ 2345 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2346 struct i40e_vsi_context *vsi_ctx, 2347 struct i40e_asq_cmd_details *cmd_details) 2348 { 2349 struct i40e_aq_desc desc; 2350 struct i40e_aqc_add_get_update_vsi *cmd = 2351 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2352 struct i40e_aqc_add_get_update_vsi_completion *resp = 2353 (struct i40e_aqc_add_get_update_vsi_completion *) 2354 &desc.params.raw; 2355 i40e_status status; 2356 2357 i40e_fill_default_direct_cmd_desc(&desc, 2358 i40e_aqc_opc_update_vsi_parameters); 2359 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2360 2361 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2362 2363 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2364 sizeof(vsi_ctx->info), cmd_details); 2365 2366 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2367 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2368 2369 return status; 2370 } 2371 2372 /** 2373 * i40e_aq_get_switch_config 2374 * @hw: pointer to the hardware structure 2375 * @buf: pointer to the result buffer 2376 * @buf_size: length of input buffer 2377 * @start_seid: seid to start for the report, 0 == beginning 2378 * @cmd_details: pointer to command details structure or NULL 2379 * 2380 * Fill the buf with switch configuration returned from AdminQ command 2381 **/ 2382 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2383 struct i40e_aqc_get_switch_config_resp *buf, 2384 u16 buf_size, u16 *start_seid, 2385 struct i40e_asq_cmd_details *cmd_details) 2386 { 2387 struct i40e_aq_desc desc; 2388 struct i40e_aqc_switch_seid *scfg = 2389 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2390 i40e_status status; 2391 2392 i40e_fill_default_direct_cmd_desc(&desc, 2393 i40e_aqc_opc_get_switch_config); 2394 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2395 if (buf_size > I40E_AQ_LARGE_BUF) 2396 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2397 scfg->seid = cpu_to_le16(*start_seid); 2398 2399 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2400 *start_seid = le16_to_cpu(scfg->seid); 2401 2402 return status; 2403 } 2404 2405 /** 2406 * i40e_aq_set_switch_config 2407 * @hw: pointer to the hardware structure 2408 * @flags: bit flag values to set 2409 * @valid_flags: which bit flags to set 2410 * @mode: cloud filter mode 2411 * @cmd_details: pointer to command details structure or NULL 2412 * 2413 * Set switch configuration bits 2414 **/ 2415 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2416 u16 flags, 2417 u16 valid_flags, u8 mode, 2418 struct i40e_asq_cmd_details *cmd_details) 2419 { 2420 struct i40e_aq_desc desc; 2421 struct i40e_aqc_set_switch_config *scfg = 2422 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2423 enum i40e_status_code status; 2424 2425 i40e_fill_default_direct_cmd_desc(&desc, 2426 i40e_aqc_opc_set_switch_config); 2427 scfg->flags = cpu_to_le16(flags); 2428 scfg->valid_flags = cpu_to_le16(valid_flags); 2429 scfg->mode = mode; 2430 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2431 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2432 scfg->first_tag = cpu_to_le16(hw->first_tag); 2433 scfg->second_tag = cpu_to_le16(hw->second_tag); 2434 } 2435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2436 2437 return status; 2438 } 2439 2440 /** 2441 * i40e_aq_get_firmware_version 2442 * @hw: pointer to the hw struct 2443 * @fw_major_version: firmware major version 2444 * @fw_minor_version: firmware minor version 2445 * @fw_build: firmware build number 2446 * @api_major_version: major queue version 2447 * @api_minor_version: minor queue version 2448 * @cmd_details: pointer to command details structure or NULL 2449 * 2450 * Get the firmware version from the admin queue commands 2451 **/ 2452 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2453 u16 *fw_major_version, u16 *fw_minor_version, 2454 u32 *fw_build, 2455 u16 *api_major_version, u16 *api_minor_version, 2456 struct i40e_asq_cmd_details *cmd_details) 2457 { 2458 struct i40e_aq_desc desc; 2459 struct i40e_aqc_get_version *resp = 2460 (struct i40e_aqc_get_version *)&desc.params.raw; 2461 i40e_status status; 2462 2463 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2464 2465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2466 2467 if (!status) { 2468 if (fw_major_version) 2469 *fw_major_version = le16_to_cpu(resp->fw_major); 2470 if (fw_minor_version) 2471 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2472 if (fw_build) 2473 *fw_build = le32_to_cpu(resp->fw_build); 2474 if (api_major_version) 2475 *api_major_version = le16_to_cpu(resp->api_major); 2476 if (api_minor_version) 2477 *api_minor_version = le16_to_cpu(resp->api_minor); 2478 } 2479 2480 return status; 2481 } 2482 2483 /** 2484 * i40e_aq_send_driver_version 2485 * @hw: pointer to the hw struct 2486 * @dv: driver's major, minor version 2487 * @cmd_details: pointer to command details structure or NULL 2488 * 2489 * Send the driver version to the firmware 2490 **/ 2491 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2492 struct i40e_driver_version *dv, 2493 struct i40e_asq_cmd_details *cmd_details) 2494 { 2495 struct i40e_aq_desc desc; 2496 struct i40e_aqc_driver_version *cmd = 2497 (struct i40e_aqc_driver_version *)&desc.params.raw; 2498 i40e_status status; 2499 u16 len; 2500 2501 if (dv == NULL) 2502 return I40E_ERR_PARAM; 2503 2504 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2505 2506 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2507 cmd->driver_major_ver = dv->major_version; 2508 cmd->driver_minor_ver = dv->minor_version; 2509 cmd->driver_build_ver = dv->build_version; 2510 cmd->driver_subbuild_ver = dv->subbuild_version; 2511 2512 len = 0; 2513 while (len < sizeof(dv->driver_string) && 2514 (dv->driver_string[len] < 0x80) && 2515 dv->driver_string[len]) 2516 len++; 2517 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2518 len, cmd_details); 2519 2520 return status; 2521 } 2522 2523 /** 2524 * i40e_get_link_status - get status of the HW network link 2525 * @hw: pointer to the hw struct 2526 * @link_up: pointer to bool (true/false = linkup/linkdown) 2527 * 2528 * Variable link_up true if link is up, false if link is down. 2529 * The variable link_up is invalid if returned value of status != 0 2530 * 2531 * Side effect: LinkStatusEvent reporting becomes enabled 2532 **/ 2533 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2534 { 2535 i40e_status status = 0; 2536 2537 if (hw->phy.get_link_info) { 2538 status = i40e_update_link_info(hw); 2539 2540 if (status) 2541 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2542 status); 2543 } 2544 2545 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2546 2547 return status; 2548 } 2549 2550 /** 2551 * i40e_updatelink_status - update status of the HW network link 2552 * @hw: pointer to the hw struct 2553 **/ 2554 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2555 { 2556 struct i40e_aq_get_phy_abilities_resp abilities; 2557 i40e_status status = 0; 2558 2559 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2560 if (status) 2561 return status; 2562 2563 /* extra checking needed to ensure link info to user is timely */ 2564 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2565 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2566 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2567 status = i40e_aq_get_phy_capabilities(hw, false, false, 2568 &abilities, NULL); 2569 if (status) 2570 return status; 2571 2572 hw->phy.link_info.req_fec_info = 2573 abilities.fec_cfg_curr_mod_ext_info & 2574 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2575 2576 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2577 sizeof(hw->phy.link_info.module_type)); 2578 } 2579 2580 return status; 2581 } 2582 2583 /** 2584 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2585 * @hw: pointer to the hw struct 2586 * @uplink_seid: the MAC or other gizmo SEID 2587 * @downlink_seid: the VSI SEID 2588 * @enabled_tc: bitmap of TCs to be enabled 2589 * @default_port: true for default port VSI, false for control port 2590 * @veb_seid: pointer to where to put the resulting VEB SEID 2591 * @enable_stats: true to turn on VEB stats 2592 * @cmd_details: pointer to command details structure or NULL 2593 * 2594 * This asks the FW to add a VEB between the uplink and downlink 2595 * elements. If the uplink SEID is 0, this will be a floating VEB. 2596 **/ 2597 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2598 u16 downlink_seid, u8 enabled_tc, 2599 bool default_port, u16 *veb_seid, 2600 bool enable_stats, 2601 struct i40e_asq_cmd_details *cmd_details) 2602 { 2603 struct i40e_aq_desc desc; 2604 struct i40e_aqc_add_veb *cmd = 2605 (struct i40e_aqc_add_veb *)&desc.params.raw; 2606 struct i40e_aqc_add_veb_completion *resp = 2607 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2608 i40e_status status; 2609 u16 veb_flags = 0; 2610 2611 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2612 if (!!uplink_seid != !!downlink_seid) 2613 return I40E_ERR_PARAM; 2614 2615 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2616 2617 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2618 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2619 cmd->enable_tcs = enabled_tc; 2620 if (!uplink_seid) 2621 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2622 if (default_port) 2623 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2624 else 2625 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2626 2627 /* reverse logic here: set the bitflag to disable the stats */ 2628 if (!enable_stats) 2629 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2630 2631 cmd->veb_flags = cpu_to_le16(veb_flags); 2632 2633 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2634 2635 if (!status && veb_seid) 2636 *veb_seid = le16_to_cpu(resp->veb_seid); 2637 2638 return status; 2639 } 2640 2641 /** 2642 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2643 * @hw: pointer to the hw struct 2644 * @veb_seid: the SEID of the VEB to query 2645 * @switch_id: the uplink switch id 2646 * @floating: set to true if the VEB is floating 2647 * @statistic_index: index of the stats counter block for this VEB 2648 * @vebs_used: number of VEB's used by function 2649 * @vebs_free: total VEB's not reserved by any function 2650 * @cmd_details: pointer to command details structure or NULL 2651 * 2652 * This retrieves the parameters for a particular VEB, specified by 2653 * uplink_seid, and returns them to the caller. 2654 **/ 2655 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2656 u16 veb_seid, u16 *switch_id, 2657 bool *floating, u16 *statistic_index, 2658 u16 *vebs_used, u16 *vebs_free, 2659 struct i40e_asq_cmd_details *cmd_details) 2660 { 2661 struct i40e_aq_desc desc; 2662 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2663 (struct i40e_aqc_get_veb_parameters_completion *) 2664 &desc.params.raw; 2665 i40e_status status; 2666 2667 if (veb_seid == 0) 2668 return I40E_ERR_PARAM; 2669 2670 i40e_fill_default_direct_cmd_desc(&desc, 2671 i40e_aqc_opc_get_veb_parameters); 2672 cmd_resp->seid = cpu_to_le16(veb_seid); 2673 2674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2675 if (status) 2676 goto get_veb_exit; 2677 2678 if (switch_id) 2679 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2680 if (statistic_index) 2681 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2682 if (vebs_used) 2683 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2684 if (vebs_free) 2685 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2686 if (floating) { 2687 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2688 2689 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2690 *floating = true; 2691 else 2692 *floating = false; 2693 } 2694 2695 get_veb_exit: 2696 return status; 2697 } 2698 2699 /** 2700 * i40e_aq_add_macvlan 2701 * @hw: pointer to the hw struct 2702 * @seid: VSI for the mac address 2703 * @mv_list: list of macvlans to be added 2704 * @count: length of the list 2705 * @cmd_details: pointer to command details structure or NULL 2706 * 2707 * Add MAC/VLAN addresses to the HW filtering 2708 **/ 2709 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2710 struct i40e_aqc_add_macvlan_element_data *mv_list, 2711 u16 count, struct i40e_asq_cmd_details *cmd_details) 2712 { 2713 struct i40e_aq_desc desc; 2714 struct i40e_aqc_macvlan *cmd = 2715 (struct i40e_aqc_macvlan *)&desc.params.raw; 2716 i40e_status status; 2717 u16 buf_size; 2718 int i; 2719 2720 if (count == 0 || !mv_list || !hw) 2721 return I40E_ERR_PARAM; 2722 2723 buf_size = count * sizeof(*mv_list); 2724 2725 /* prep the rest of the request */ 2726 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2727 cmd->num_addresses = cpu_to_le16(count); 2728 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2729 cmd->seid[1] = 0; 2730 cmd->seid[2] = 0; 2731 2732 for (i = 0; i < count; i++) 2733 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2734 mv_list[i].flags |= 2735 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2736 2737 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2738 if (buf_size > I40E_AQ_LARGE_BUF) 2739 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2740 2741 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2742 cmd_details); 2743 2744 return status; 2745 } 2746 2747 /** 2748 * i40e_aq_remove_macvlan 2749 * @hw: pointer to the hw struct 2750 * @seid: VSI for the mac address 2751 * @mv_list: list of macvlans to be removed 2752 * @count: length of the list 2753 * @cmd_details: pointer to command details structure or NULL 2754 * 2755 * Remove MAC/VLAN addresses from the HW filtering 2756 **/ 2757 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2758 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2759 u16 count, struct i40e_asq_cmd_details *cmd_details) 2760 { 2761 struct i40e_aq_desc desc; 2762 struct i40e_aqc_macvlan *cmd = 2763 (struct i40e_aqc_macvlan *)&desc.params.raw; 2764 i40e_status status; 2765 u16 buf_size; 2766 2767 if (count == 0 || !mv_list || !hw) 2768 return I40E_ERR_PARAM; 2769 2770 buf_size = count * sizeof(*mv_list); 2771 2772 /* prep the rest of the request */ 2773 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2774 cmd->num_addresses = cpu_to_le16(count); 2775 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2776 cmd->seid[1] = 0; 2777 cmd->seid[2] = 0; 2778 2779 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2780 if (buf_size > I40E_AQ_LARGE_BUF) 2781 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2782 2783 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2784 cmd_details); 2785 2786 return status; 2787 } 2788 2789 /** 2790 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2791 * @hw: pointer to the hw struct 2792 * @opcode: AQ opcode for add or delete mirror rule 2793 * @sw_seid: Switch SEID (to which rule refers) 2794 * @rule_type: Rule Type (ingress/egress/VLAN) 2795 * @id: Destination VSI SEID or Rule ID 2796 * @count: length of the list 2797 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2798 * @cmd_details: pointer to command details structure or NULL 2799 * @rule_id: Rule ID returned from FW 2800 * @rule_used: Number of rules used in internal switch 2801 * @rule_free: Number of rules free in internal switch 2802 * 2803 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2804 * VEBs/VEPA elements only 2805 **/ 2806 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2807 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2808 u16 count, __le16 *mr_list, 2809 struct i40e_asq_cmd_details *cmd_details, 2810 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2811 { 2812 struct i40e_aq_desc desc; 2813 struct i40e_aqc_add_delete_mirror_rule *cmd = 2814 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2815 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2816 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2817 i40e_status status; 2818 u16 buf_size; 2819 2820 buf_size = count * sizeof(*mr_list); 2821 2822 /* prep the rest of the request */ 2823 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2824 cmd->seid = cpu_to_le16(sw_seid); 2825 cmd->rule_type = cpu_to_le16(rule_type & 2826 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2827 cmd->num_entries = cpu_to_le16(count); 2828 /* Dest VSI for add, rule_id for delete */ 2829 cmd->destination = cpu_to_le16(id); 2830 if (mr_list) { 2831 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2832 I40E_AQ_FLAG_RD)); 2833 if (buf_size > I40E_AQ_LARGE_BUF) 2834 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2835 } 2836 2837 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2838 cmd_details); 2839 if (!status || 2840 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2841 if (rule_id) 2842 *rule_id = le16_to_cpu(resp->rule_id); 2843 if (rules_used) 2844 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2845 if (rules_free) 2846 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2847 } 2848 return status; 2849 } 2850 2851 /** 2852 * i40e_aq_add_mirrorrule - add a mirror rule 2853 * @hw: pointer to the hw struct 2854 * @sw_seid: Switch SEID (to which rule refers) 2855 * @rule_type: Rule Type (ingress/egress/VLAN) 2856 * @dest_vsi: SEID of VSI to which packets will be mirrored 2857 * @count: length of the list 2858 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2859 * @cmd_details: pointer to command details structure or NULL 2860 * @rule_id: Rule ID returned from FW 2861 * @rule_used: Number of rules used in internal switch 2862 * @rule_free: Number of rules free in internal switch 2863 * 2864 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2865 **/ 2866 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2867 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2868 struct i40e_asq_cmd_details *cmd_details, 2869 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2870 { 2871 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2872 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2873 if (count == 0 || !mr_list) 2874 return I40E_ERR_PARAM; 2875 } 2876 2877 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2878 rule_type, dest_vsi, count, mr_list, 2879 cmd_details, rule_id, rules_used, rules_free); 2880 } 2881 2882 /** 2883 * i40e_aq_delete_mirrorrule - delete a mirror rule 2884 * @hw: pointer to the hw struct 2885 * @sw_seid: Switch SEID (to which rule refers) 2886 * @rule_type: Rule Type (ingress/egress/VLAN) 2887 * @count: length of the list 2888 * @rule_id: Rule ID that is returned in the receive desc as part of 2889 * add_mirrorrule. 2890 * @mr_list: list of mirrored VLAN IDs to be removed 2891 * @cmd_details: pointer to command details structure or NULL 2892 * @rule_used: Number of rules used in internal switch 2893 * @rule_free: Number of rules free in internal switch 2894 * 2895 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2896 **/ 2897 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2898 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2899 struct i40e_asq_cmd_details *cmd_details, 2900 u16 *rules_used, u16 *rules_free) 2901 { 2902 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2903 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2904 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2905 * mirroring. For other rule_type, count and rule_type should 2906 * not matter. 2907 */ 2908 if (count == 0 || !mr_list) 2909 return I40E_ERR_PARAM; 2910 } 2911 2912 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2913 rule_type, rule_id, count, mr_list, 2914 cmd_details, NULL, rules_used, rules_free); 2915 } 2916 2917 /** 2918 * i40e_aq_send_msg_to_vf 2919 * @hw: pointer to the hardware structure 2920 * @vfid: VF id to send msg 2921 * @v_opcode: opcodes for VF-PF communication 2922 * @v_retval: return error code 2923 * @msg: pointer to the msg buffer 2924 * @msglen: msg length 2925 * @cmd_details: pointer to command details 2926 * 2927 * send msg to vf 2928 **/ 2929 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2930 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2931 struct i40e_asq_cmd_details *cmd_details) 2932 { 2933 struct i40e_aq_desc desc; 2934 struct i40e_aqc_pf_vf_message *cmd = 2935 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2936 i40e_status status; 2937 2938 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2939 cmd->id = cpu_to_le32(vfid); 2940 desc.cookie_high = cpu_to_le32(v_opcode); 2941 desc.cookie_low = cpu_to_le32(v_retval); 2942 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2943 if (msglen) { 2944 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2945 I40E_AQ_FLAG_RD)); 2946 if (msglen > I40E_AQ_LARGE_BUF) 2947 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2948 desc.datalen = cpu_to_le16(msglen); 2949 } 2950 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2951 2952 return status; 2953 } 2954 2955 /** 2956 * i40e_aq_debug_read_register 2957 * @hw: pointer to the hw struct 2958 * @reg_addr: register address 2959 * @reg_val: register value 2960 * @cmd_details: pointer to command details structure or NULL 2961 * 2962 * Read the register using the admin queue commands 2963 **/ 2964 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2965 u32 reg_addr, u64 *reg_val, 2966 struct i40e_asq_cmd_details *cmd_details) 2967 { 2968 struct i40e_aq_desc desc; 2969 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2970 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2971 i40e_status status; 2972 2973 if (reg_val == NULL) 2974 return I40E_ERR_PARAM; 2975 2976 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2977 2978 cmd_resp->address = cpu_to_le32(reg_addr); 2979 2980 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2981 2982 if (!status) { 2983 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2984 (u64)le32_to_cpu(cmd_resp->value_low); 2985 } 2986 2987 return status; 2988 } 2989 2990 /** 2991 * i40e_aq_debug_write_register 2992 * @hw: pointer to the hw struct 2993 * @reg_addr: register address 2994 * @reg_val: register value 2995 * @cmd_details: pointer to command details structure or NULL 2996 * 2997 * Write to a register using the admin queue commands 2998 **/ 2999 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 3000 u32 reg_addr, u64 reg_val, 3001 struct i40e_asq_cmd_details *cmd_details) 3002 { 3003 struct i40e_aq_desc desc; 3004 struct i40e_aqc_debug_reg_read_write *cmd = 3005 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3006 i40e_status status; 3007 3008 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3009 3010 cmd->address = cpu_to_le32(reg_addr); 3011 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3012 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3013 3014 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3015 3016 return status; 3017 } 3018 3019 /** 3020 * i40e_aq_request_resource 3021 * @hw: pointer to the hw struct 3022 * @resource: resource id 3023 * @access: access type 3024 * @sdp_number: resource number 3025 * @timeout: the maximum time in ms that the driver may hold the resource 3026 * @cmd_details: pointer to command details structure or NULL 3027 * 3028 * requests common resource using the admin queue commands 3029 **/ 3030 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3031 enum i40e_aq_resources_ids resource, 3032 enum i40e_aq_resource_access_type access, 3033 u8 sdp_number, u64 *timeout, 3034 struct i40e_asq_cmd_details *cmd_details) 3035 { 3036 struct i40e_aq_desc desc; 3037 struct i40e_aqc_request_resource *cmd_resp = 3038 (struct i40e_aqc_request_resource *)&desc.params.raw; 3039 i40e_status status; 3040 3041 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3042 3043 cmd_resp->resource_id = cpu_to_le16(resource); 3044 cmd_resp->access_type = cpu_to_le16(access); 3045 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3046 3047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3048 /* The completion specifies the maximum time in ms that the driver 3049 * may hold the resource in the Timeout field. 3050 * If the resource is held by someone else, the command completes with 3051 * busy return value and the timeout field indicates the maximum time 3052 * the current owner of the resource has to free it. 3053 */ 3054 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3055 *timeout = le32_to_cpu(cmd_resp->timeout); 3056 3057 return status; 3058 } 3059 3060 /** 3061 * i40e_aq_release_resource 3062 * @hw: pointer to the hw struct 3063 * @resource: resource id 3064 * @sdp_number: resource number 3065 * @cmd_details: pointer to command details structure or NULL 3066 * 3067 * release common resource using the admin queue commands 3068 **/ 3069 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3070 enum i40e_aq_resources_ids resource, 3071 u8 sdp_number, 3072 struct i40e_asq_cmd_details *cmd_details) 3073 { 3074 struct i40e_aq_desc desc; 3075 struct i40e_aqc_request_resource *cmd = 3076 (struct i40e_aqc_request_resource *)&desc.params.raw; 3077 i40e_status status; 3078 3079 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3080 3081 cmd->resource_id = cpu_to_le16(resource); 3082 cmd->resource_number = cpu_to_le32(sdp_number); 3083 3084 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3085 3086 return status; 3087 } 3088 3089 /** 3090 * i40e_aq_read_nvm 3091 * @hw: pointer to the hw struct 3092 * @module_pointer: module pointer location in words from the NVM beginning 3093 * @offset: byte offset from the module beginning 3094 * @length: length of the section to be read (in bytes from the offset) 3095 * @data: command buffer (size [bytes] = length) 3096 * @last_command: tells if this is the last command in a series 3097 * @cmd_details: pointer to command details structure or NULL 3098 * 3099 * Read the NVM using the admin queue commands 3100 **/ 3101 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3102 u32 offset, u16 length, void *data, 3103 bool last_command, 3104 struct i40e_asq_cmd_details *cmd_details) 3105 { 3106 struct i40e_aq_desc desc; 3107 struct i40e_aqc_nvm_update *cmd = 3108 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3109 i40e_status status; 3110 3111 /* In offset the highest byte must be zeroed. */ 3112 if (offset & 0xFF000000) { 3113 status = I40E_ERR_PARAM; 3114 goto i40e_aq_read_nvm_exit; 3115 } 3116 3117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3118 3119 /* If this is the last command in a series, set the proper flag. */ 3120 if (last_command) 3121 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3122 cmd->module_pointer = module_pointer; 3123 cmd->offset = cpu_to_le32(offset); 3124 cmd->length = cpu_to_le16(length); 3125 3126 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3127 if (length > I40E_AQ_LARGE_BUF) 3128 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3129 3130 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3131 3132 i40e_aq_read_nvm_exit: 3133 return status; 3134 } 3135 3136 /** 3137 * i40e_aq_erase_nvm 3138 * @hw: pointer to the hw struct 3139 * @module_pointer: module pointer location in words from the NVM beginning 3140 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3141 * @length: length of the section to be erased (expressed in 4 KB) 3142 * @last_command: tells if this is the last command in a series 3143 * @cmd_details: pointer to command details structure or NULL 3144 * 3145 * Erase the NVM sector using the admin queue commands 3146 **/ 3147 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3148 u32 offset, u16 length, bool last_command, 3149 struct i40e_asq_cmd_details *cmd_details) 3150 { 3151 struct i40e_aq_desc desc; 3152 struct i40e_aqc_nvm_update *cmd = 3153 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3154 i40e_status status; 3155 3156 /* In offset the highest byte must be zeroed. */ 3157 if (offset & 0xFF000000) { 3158 status = I40E_ERR_PARAM; 3159 goto i40e_aq_erase_nvm_exit; 3160 } 3161 3162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3163 3164 /* If this is the last command in a series, set the proper flag. */ 3165 if (last_command) 3166 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3167 cmd->module_pointer = module_pointer; 3168 cmd->offset = cpu_to_le32(offset); 3169 cmd->length = cpu_to_le16(length); 3170 3171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3172 3173 i40e_aq_erase_nvm_exit: 3174 return status; 3175 } 3176 3177 /** 3178 * i40e_parse_discover_capabilities 3179 * @hw: pointer to the hw struct 3180 * @buff: pointer to a buffer containing device/function capability records 3181 * @cap_count: number of capability records in the list 3182 * @list_type_opc: type of capabilities list to parse 3183 * 3184 * Parse the device/function capabilities list. 3185 **/ 3186 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3187 u32 cap_count, 3188 enum i40e_admin_queue_opc list_type_opc) 3189 { 3190 struct i40e_aqc_list_capabilities_element_resp *cap; 3191 u32 valid_functions, num_functions; 3192 u32 number, logical_id, phys_id; 3193 struct i40e_hw_capabilities *p; 3194 u8 major_rev; 3195 u32 i = 0; 3196 u16 id; 3197 3198 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3199 3200 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3201 p = &hw->dev_caps; 3202 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3203 p = &hw->func_caps; 3204 else 3205 return; 3206 3207 for (i = 0; i < cap_count; i++, cap++) { 3208 id = le16_to_cpu(cap->id); 3209 number = le32_to_cpu(cap->number); 3210 logical_id = le32_to_cpu(cap->logical_id); 3211 phys_id = le32_to_cpu(cap->phys_id); 3212 major_rev = cap->major_rev; 3213 3214 switch (id) { 3215 case I40E_AQ_CAP_ID_SWITCH_MODE: 3216 p->switch_mode = number; 3217 break; 3218 case I40E_AQ_CAP_ID_MNG_MODE: 3219 p->management_mode = number; 3220 if (major_rev > 1) { 3221 p->mng_protocols_over_mctp = logical_id; 3222 i40e_debug(hw, I40E_DEBUG_INIT, 3223 "HW Capability: Protocols over MCTP = %d\n", 3224 p->mng_protocols_over_mctp); 3225 } else { 3226 p->mng_protocols_over_mctp = 0; 3227 } 3228 break; 3229 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3230 p->npar_enable = number; 3231 break; 3232 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3233 p->os2bmc = number; 3234 break; 3235 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3236 p->valid_functions = number; 3237 break; 3238 case I40E_AQ_CAP_ID_SRIOV: 3239 if (number == 1) 3240 p->sr_iov_1_1 = true; 3241 break; 3242 case I40E_AQ_CAP_ID_VF: 3243 p->num_vfs = number; 3244 p->vf_base_id = logical_id; 3245 break; 3246 case I40E_AQ_CAP_ID_VMDQ: 3247 if (number == 1) 3248 p->vmdq = true; 3249 break; 3250 case I40E_AQ_CAP_ID_8021QBG: 3251 if (number == 1) 3252 p->evb_802_1_qbg = true; 3253 break; 3254 case I40E_AQ_CAP_ID_8021QBR: 3255 if (number == 1) 3256 p->evb_802_1_qbh = true; 3257 break; 3258 case I40E_AQ_CAP_ID_VSI: 3259 p->num_vsis = number; 3260 break; 3261 case I40E_AQ_CAP_ID_DCB: 3262 if (number == 1) { 3263 p->dcb = true; 3264 p->enabled_tcmap = logical_id; 3265 p->maxtc = phys_id; 3266 } 3267 break; 3268 case I40E_AQ_CAP_ID_FCOE: 3269 if (number == 1) 3270 p->fcoe = true; 3271 break; 3272 case I40E_AQ_CAP_ID_ISCSI: 3273 if (number == 1) 3274 p->iscsi = true; 3275 break; 3276 case I40E_AQ_CAP_ID_RSS: 3277 p->rss = true; 3278 p->rss_table_size = number; 3279 p->rss_table_entry_width = logical_id; 3280 break; 3281 case I40E_AQ_CAP_ID_RXQ: 3282 p->num_rx_qp = number; 3283 p->base_queue = phys_id; 3284 break; 3285 case I40E_AQ_CAP_ID_TXQ: 3286 p->num_tx_qp = number; 3287 p->base_queue = phys_id; 3288 break; 3289 case I40E_AQ_CAP_ID_MSIX: 3290 p->num_msix_vectors = number; 3291 i40e_debug(hw, I40E_DEBUG_INIT, 3292 "HW Capability: MSIX vector count = %d\n", 3293 p->num_msix_vectors); 3294 break; 3295 case I40E_AQ_CAP_ID_VF_MSIX: 3296 p->num_msix_vectors_vf = number; 3297 break; 3298 case I40E_AQ_CAP_ID_FLEX10: 3299 if (major_rev == 1) { 3300 if (number == 1) { 3301 p->flex10_enable = true; 3302 p->flex10_capable = true; 3303 } 3304 } else { 3305 /* Capability revision >= 2 */ 3306 if (number & 1) 3307 p->flex10_enable = true; 3308 if (number & 2) 3309 p->flex10_capable = true; 3310 } 3311 p->flex10_mode = logical_id; 3312 p->flex10_status = phys_id; 3313 break; 3314 case I40E_AQ_CAP_ID_CEM: 3315 if (number == 1) 3316 p->mgmt_cem = true; 3317 break; 3318 case I40E_AQ_CAP_ID_IWARP: 3319 if (number == 1) 3320 p->iwarp = true; 3321 break; 3322 case I40E_AQ_CAP_ID_LED: 3323 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3324 p->led[phys_id] = true; 3325 break; 3326 case I40E_AQ_CAP_ID_SDP: 3327 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3328 p->sdp[phys_id] = true; 3329 break; 3330 case I40E_AQ_CAP_ID_MDIO: 3331 if (number == 1) { 3332 p->mdio_port_num = phys_id; 3333 p->mdio_port_mode = logical_id; 3334 } 3335 break; 3336 case I40E_AQ_CAP_ID_1588: 3337 if (number == 1) 3338 p->ieee_1588 = true; 3339 break; 3340 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3341 p->fd = true; 3342 p->fd_filters_guaranteed = number; 3343 p->fd_filters_best_effort = logical_id; 3344 break; 3345 case I40E_AQ_CAP_ID_WSR_PROT: 3346 p->wr_csr_prot = (u64)number; 3347 p->wr_csr_prot |= (u64)logical_id << 32; 3348 break; 3349 case I40E_AQ_CAP_ID_NVM_MGMT: 3350 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3351 p->sec_rev_disabled = true; 3352 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3353 p->update_disabled = true; 3354 break; 3355 default: 3356 break; 3357 } 3358 } 3359 3360 if (p->fcoe) 3361 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3362 3363 /* Software override ensuring FCoE is disabled if npar or mfp 3364 * mode because it is not supported in these modes. 3365 */ 3366 if (p->npar_enable || p->flex10_enable) 3367 p->fcoe = false; 3368 3369 /* count the enabled ports (aka the "not disabled" ports) */ 3370 hw->num_ports = 0; 3371 for (i = 0; i < 4; i++) { 3372 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3373 u64 port_cfg = 0; 3374 3375 /* use AQ read to get the physical register offset instead 3376 * of the port relative offset 3377 */ 3378 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3379 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3380 hw->num_ports++; 3381 } 3382 3383 valid_functions = p->valid_functions; 3384 num_functions = 0; 3385 while (valid_functions) { 3386 if (valid_functions & 1) 3387 num_functions++; 3388 valid_functions >>= 1; 3389 } 3390 3391 /* partition id is 1-based, and functions are evenly spread 3392 * across the ports as partitions 3393 */ 3394 if (hw->num_ports != 0) { 3395 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3396 hw->num_partitions = num_functions / hw->num_ports; 3397 } 3398 3399 /* additional HW specific goodies that might 3400 * someday be HW version specific 3401 */ 3402 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3403 } 3404 3405 /** 3406 * i40e_aq_discover_capabilities 3407 * @hw: pointer to the hw struct 3408 * @buff: a virtual buffer to hold the capabilities 3409 * @buff_size: Size of the virtual buffer 3410 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3411 * @list_type_opc: capabilities type to discover - pass in the command opcode 3412 * @cmd_details: pointer to command details structure or NULL 3413 * 3414 * Get the device capabilities descriptions from the firmware 3415 **/ 3416 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3417 void *buff, u16 buff_size, u16 *data_size, 3418 enum i40e_admin_queue_opc list_type_opc, 3419 struct i40e_asq_cmd_details *cmd_details) 3420 { 3421 struct i40e_aqc_list_capabilites *cmd; 3422 struct i40e_aq_desc desc; 3423 i40e_status status = 0; 3424 3425 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3426 3427 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3428 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3429 status = I40E_ERR_PARAM; 3430 goto exit; 3431 } 3432 3433 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3434 3435 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3436 if (buff_size > I40E_AQ_LARGE_BUF) 3437 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3438 3439 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3440 *data_size = le16_to_cpu(desc.datalen); 3441 3442 if (status) 3443 goto exit; 3444 3445 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3446 list_type_opc); 3447 3448 exit: 3449 return status; 3450 } 3451 3452 /** 3453 * i40e_aq_update_nvm 3454 * @hw: pointer to the hw struct 3455 * @module_pointer: module pointer location in words from the NVM beginning 3456 * @offset: byte offset from the module beginning 3457 * @length: length of the section to be written (in bytes from the offset) 3458 * @data: command buffer (size [bytes] = length) 3459 * @last_command: tells if this is the last command in a series 3460 * @cmd_details: pointer to command details structure or NULL 3461 * 3462 * Update the NVM using the admin queue commands 3463 **/ 3464 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3465 u32 offset, u16 length, void *data, 3466 bool last_command, 3467 struct i40e_asq_cmd_details *cmd_details) 3468 { 3469 struct i40e_aq_desc desc; 3470 struct i40e_aqc_nvm_update *cmd = 3471 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3472 i40e_status status; 3473 3474 /* In offset the highest byte must be zeroed. */ 3475 if (offset & 0xFF000000) { 3476 status = I40E_ERR_PARAM; 3477 goto i40e_aq_update_nvm_exit; 3478 } 3479 3480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3481 3482 /* If this is the last command in a series, set the proper flag. */ 3483 if (last_command) 3484 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3485 cmd->module_pointer = module_pointer; 3486 cmd->offset = cpu_to_le32(offset); 3487 cmd->length = cpu_to_le16(length); 3488 3489 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3490 if (length > I40E_AQ_LARGE_BUF) 3491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3492 3493 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3494 3495 i40e_aq_update_nvm_exit: 3496 return status; 3497 } 3498 3499 /** 3500 * i40e_aq_get_lldp_mib 3501 * @hw: pointer to the hw struct 3502 * @bridge_type: type of bridge requested 3503 * @mib_type: Local, Remote or both Local and Remote MIBs 3504 * @buff: pointer to a user supplied buffer to store the MIB block 3505 * @buff_size: size of the buffer (in bytes) 3506 * @local_len : length of the returned Local LLDP MIB 3507 * @remote_len: length of the returned Remote LLDP MIB 3508 * @cmd_details: pointer to command details structure or NULL 3509 * 3510 * Requests the complete LLDP MIB (entire packet). 3511 **/ 3512 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3513 u8 mib_type, void *buff, u16 buff_size, 3514 u16 *local_len, u16 *remote_len, 3515 struct i40e_asq_cmd_details *cmd_details) 3516 { 3517 struct i40e_aq_desc desc; 3518 struct i40e_aqc_lldp_get_mib *cmd = 3519 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3520 struct i40e_aqc_lldp_get_mib *resp = 3521 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3522 i40e_status status; 3523 3524 if (buff_size == 0 || !buff) 3525 return I40E_ERR_PARAM; 3526 3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3528 /* Indirect Command */ 3529 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3530 3531 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3532 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3533 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3534 3535 desc.datalen = cpu_to_le16(buff_size); 3536 3537 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3538 if (buff_size > I40E_AQ_LARGE_BUF) 3539 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3540 3541 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3542 if (!status) { 3543 if (local_len != NULL) 3544 *local_len = le16_to_cpu(resp->local_len); 3545 if (remote_len != NULL) 3546 *remote_len = le16_to_cpu(resp->remote_len); 3547 } 3548 3549 return status; 3550 } 3551 3552 /** 3553 * i40e_aq_cfg_lldp_mib_change_event 3554 * @hw: pointer to the hw struct 3555 * @enable_update: Enable or Disable event posting 3556 * @cmd_details: pointer to command details structure or NULL 3557 * 3558 * Enable or Disable posting of an event on ARQ when LLDP MIB 3559 * associated with the interface changes 3560 **/ 3561 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3562 bool enable_update, 3563 struct i40e_asq_cmd_details *cmd_details) 3564 { 3565 struct i40e_aq_desc desc; 3566 struct i40e_aqc_lldp_update_mib *cmd = 3567 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3568 i40e_status status; 3569 3570 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3571 3572 if (!enable_update) 3573 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3574 3575 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3576 3577 return status; 3578 } 3579 3580 /** 3581 * i40e_aq_stop_lldp 3582 * @hw: pointer to the hw struct 3583 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3584 * @cmd_details: pointer to command details structure or NULL 3585 * 3586 * Stop or Shutdown the embedded LLDP Agent 3587 **/ 3588 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3589 struct i40e_asq_cmd_details *cmd_details) 3590 { 3591 struct i40e_aq_desc desc; 3592 struct i40e_aqc_lldp_stop *cmd = 3593 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3594 i40e_status status; 3595 3596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3597 3598 if (shutdown_agent) 3599 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3600 3601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3602 3603 return status; 3604 } 3605 3606 /** 3607 * i40e_aq_start_lldp 3608 * @hw: pointer to the hw struct 3609 * @cmd_details: pointer to command details structure or NULL 3610 * 3611 * Start the embedded LLDP Agent on all ports. 3612 **/ 3613 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3614 struct i40e_asq_cmd_details *cmd_details) 3615 { 3616 struct i40e_aq_desc desc; 3617 struct i40e_aqc_lldp_start *cmd = 3618 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3619 i40e_status status; 3620 3621 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3622 3623 cmd->command = I40E_AQ_LLDP_AGENT_START; 3624 3625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3626 3627 return status; 3628 } 3629 3630 /** 3631 * i40e_aq_get_cee_dcb_config 3632 * @hw: pointer to the hw struct 3633 * @buff: response buffer that stores CEE operational configuration 3634 * @buff_size: size of the buffer passed 3635 * @cmd_details: pointer to command details structure or NULL 3636 * 3637 * Get CEE DCBX mode operational configuration from firmware 3638 **/ 3639 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3640 void *buff, u16 buff_size, 3641 struct i40e_asq_cmd_details *cmd_details) 3642 { 3643 struct i40e_aq_desc desc; 3644 i40e_status status; 3645 3646 if (buff_size == 0 || !buff) 3647 return I40E_ERR_PARAM; 3648 3649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3650 3651 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3652 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3653 cmd_details); 3654 3655 return status; 3656 } 3657 3658 /** 3659 * i40e_aq_add_udp_tunnel 3660 * @hw: pointer to the hw struct 3661 * @udp_port: the UDP port to add in Host byte order 3662 * @header_len: length of the tunneling header length in DWords 3663 * @protocol_index: protocol index type 3664 * @filter_index: pointer to filter index 3665 * @cmd_details: pointer to command details structure or NULL 3666 * 3667 * Note: Firmware expects the udp_port value to be in Little Endian format, 3668 * and this function will call cpu_to_le16 to convert from Host byte order to 3669 * Little Endian order. 3670 **/ 3671 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3672 u16 udp_port, u8 protocol_index, 3673 u8 *filter_index, 3674 struct i40e_asq_cmd_details *cmd_details) 3675 { 3676 struct i40e_aq_desc desc; 3677 struct i40e_aqc_add_udp_tunnel *cmd = 3678 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3679 struct i40e_aqc_del_udp_tunnel_completion *resp = 3680 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3681 i40e_status status; 3682 3683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3684 3685 cmd->udp_port = cpu_to_le16(udp_port); 3686 cmd->protocol_type = protocol_index; 3687 3688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3689 3690 if (!status && filter_index) 3691 *filter_index = resp->index; 3692 3693 return status; 3694 } 3695 3696 /** 3697 * i40e_aq_del_udp_tunnel 3698 * @hw: pointer to the hw struct 3699 * @index: filter index 3700 * @cmd_details: pointer to command details structure or NULL 3701 **/ 3702 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3703 struct i40e_asq_cmd_details *cmd_details) 3704 { 3705 struct i40e_aq_desc desc; 3706 struct i40e_aqc_remove_udp_tunnel *cmd = 3707 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3708 i40e_status status; 3709 3710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3711 3712 cmd->index = index; 3713 3714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3715 3716 return status; 3717 } 3718 3719 /** 3720 * i40e_aq_delete_element - Delete switch element 3721 * @hw: pointer to the hw struct 3722 * @seid: the SEID to delete from the switch 3723 * @cmd_details: pointer to command details structure or NULL 3724 * 3725 * This deletes a switch element from the switch. 3726 **/ 3727 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3728 struct i40e_asq_cmd_details *cmd_details) 3729 { 3730 struct i40e_aq_desc desc; 3731 struct i40e_aqc_switch_seid *cmd = 3732 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3733 i40e_status status; 3734 3735 if (seid == 0) 3736 return I40E_ERR_PARAM; 3737 3738 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3739 3740 cmd->seid = cpu_to_le16(seid); 3741 3742 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3743 3744 return status; 3745 } 3746 3747 /** 3748 * i40e_aq_dcb_updated - DCB Updated Command 3749 * @hw: pointer to the hw struct 3750 * @cmd_details: pointer to command details structure or NULL 3751 * 3752 * EMP will return when the shared RPB settings have been 3753 * recomputed and modified. The retval field in the descriptor 3754 * will be set to 0 when RPB is modified. 3755 **/ 3756 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3757 struct i40e_asq_cmd_details *cmd_details) 3758 { 3759 struct i40e_aq_desc desc; 3760 i40e_status status; 3761 3762 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3763 3764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3765 3766 return status; 3767 } 3768 3769 /** 3770 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3771 * @hw: pointer to the hw struct 3772 * @seid: seid for the physical port/switching component/vsi 3773 * @buff: Indirect buffer to hold data parameters and response 3774 * @buff_size: Indirect buffer size 3775 * @opcode: Tx scheduler AQ command opcode 3776 * @cmd_details: pointer to command details structure or NULL 3777 * 3778 * Generic command handler for Tx scheduler AQ commands 3779 **/ 3780 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3781 void *buff, u16 buff_size, 3782 enum i40e_admin_queue_opc opcode, 3783 struct i40e_asq_cmd_details *cmd_details) 3784 { 3785 struct i40e_aq_desc desc; 3786 struct i40e_aqc_tx_sched_ind *cmd = 3787 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3788 i40e_status status; 3789 bool cmd_param_flag = false; 3790 3791 switch (opcode) { 3792 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3793 case i40e_aqc_opc_configure_vsi_tc_bw: 3794 case i40e_aqc_opc_enable_switching_comp_ets: 3795 case i40e_aqc_opc_modify_switching_comp_ets: 3796 case i40e_aqc_opc_disable_switching_comp_ets: 3797 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3798 case i40e_aqc_opc_configure_switching_comp_bw_config: 3799 cmd_param_flag = true; 3800 break; 3801 case i40e_aqc_opc_query_vsi_bw_config: 3802 case i40e_aqc_opc_query_vsi_ets_sla_config: 3803 case i40e_aqc_opc_query_switching_comp_ets_config: 3804 case i40e_aqc_opc_query_port_ets_config: 3805 case i40e_aqc_opc_query_switching_comp_bw_config: 3806 cmd_param_flag = false; 3807 break; 3808 default: 3809 return I40E_ERR_PARAM; 3810 } 3811 3812 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3813 3814 /* Indirect command */ 3815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3816 if (cmd_param_flag) 3817 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3818 if (buff_size > I40E_AQ_LARGE_BUF) 3819 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3820 3821 desc.datalen = cpu_to_le16(buff_size); 3822 3823 cmd->vsi_seid = cpu_to_le16(seid); 3824 3825 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3826 3827 return status; 3828 } 3829 3830 /** 3831 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3832 * @hw: pointer to the hw struct 3833 * @seid: VSI seid 3834 * @credit: BW limit credits (0 = disabled) 3835 * @max_credit: Max BW limit credits 3836 * @cmd_details: pointer to command details structure or NULL 3837 **/ 3838 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3839 u16 seid, u16 credit, u8 max_credit, 3840 struct i40e_asq_cmd_details *cmd_details) 3841 { 3842 struct i40e_aq_desc desc; 3843 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3844 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3845 i40e_status status; 3846 3847 i40e_fill_default_direct_cmd_desc(&desc, 3848 i40e_aqc_opc_configure_vsi_bw_limit); 3849 3850 cmd->vsi_seid = cpu_to_le16(seid); 3851 cmd->credit = cpu_to_le16(credit); 3852 cmd->max_credit = max_credit; 3853 3854 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3855 3856 return status; 3857 } 3858 3859 /** 3860 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3861 * @hw: pointer to the hw struct 3862 * @seid: VSI seid 3863 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3864 * @cmd_details: pointer to command details structure or NULL 3865 **/ 3866 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3867 u16 seid, 3868 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3869 struct i40e_asq_cmd_details *cmd_details) 3870 { 3871 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3872 i40e_aqc_opc_configure_vsi_tc_bw, 3873 cmd_details); 3874 } 3875 3876 /** 3877 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3878 * @hw: pointer to the hw struct 3879 * @seid: seid of the switching component connected to Physical Port 3880 * @ets_data: Buffer holding ETS parameters 3881 * @cmd_details: pointer to command details structure or NULL 3882 **/ 3883 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3884 u16 seid, 3885 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3886 enum i40e_admin_queue_opc opcode, 3887 struct i40e_asq_cmd_details *cmd_details) 3888 { 3889 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3890 sizeof(*ets_data), opcode, cmd_details); 3891 } 3892 3893 /** 3894 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3895 * @hw: pointer to the hw struct 3896 * @seid: seid of the switching component 3897 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3898 * @cmd_details: pointer to command details structure or NULL 3899 **/ 3900 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3901 u16 seid, 3902 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3903 struct i40e_asq_cmd_details *cmd_details) 3904 { 3905 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3906 i40e_aqc_opc_configure_switching_comp_bw_config, 3907 cmd_details); 3908 } 3909 3910 /** 3911 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3912 * @hw: pointer to the hw struct 3913 * @seid: seid of the VSI 3914 * @bw_data: Buffer to hold VSI BW configuration 3915 * @cmd_details: pointer to command details structure or NULL 3916 **/ 3917 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3918 u16 seid, 3919 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3920 struct i40e_asq_cmd_details *cmd_details) 3921 { 3922 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3923 i40e_aqc_opc_query_vsi_bw_config, 3924 cmd_details); 3925 } 3926 3927 /** 3928 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3929 * @hw: pointer to the hw struct 3930 * @seid: seid of the VSI 3931 * @bw_data: Buffer to hold VSI BW configuration per TC 3932 * @cmd_details: pointer to command details structure or NULL 3933 **/ 3934 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3935 u16 seid, 3936 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3937 struct i40e_asq_cmd_details *cmd_details) 3938 { 3939 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3940 i40e_aqc_opc_query_vsi_ets_sla_config, 3941 cmd_details); 3942 } 3943 3944 /** 3945 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3946 * @hw: pointer to the hw struct 3947 * @seid: seid of the switching component 3948 * @bw_data: Buffer to hold switching component's per TC BW config 3949 * @cmd_details: pointer to command details structure or NULL 3950 **/ 3951 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3952 u16 seid, 3953 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3954 struct i40e_asq_cmd_details *cmd_details) 3955 { 3956 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3957 i40e_aqc_opc_query_switching_comp_ets_config, 3958 cmd_details); 3959 } 3960 3961 /** 3962 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3963 * @hw: pointer to the hw struct 3964 * @seid: seid of the VSI or switching component connected to Physical Port 3965 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3966 * @cmd_details: pointer to command details structure or NULL 3967 **/ 3968 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3969 u16 seid, 3970 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3971 struct i40e_asq_cmd_details *cmd_details) 3972 { 3973 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3974 i40e_aqc_opc_query_port_ets_config, 3975 cmd_details); 3976 } 3977 3978 /** 3979 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3980 * @hw: pointer to the hw struct 3981 * @seid: seid of the switching component 3982 * @bw_data: Buffer to hold switching component's BW configuration 3983 * @cmd_details: pointer to command details structure or NULL 3984 **/ 3985 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3986 u16 seid, 3987 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3988 struct i40e_asq_cmd_details *cmd_details) 3989 { 3990 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3991 i40e_aqc_opc_query_switching_comp_bw_config, 3992 cmd_details); 3993 } 3994 3995 /** 3996 * i40e_validate_filter_settings 3997 * @hw: pointer to the hardware structure 3998 * @settings: Filter control settings 3999 * 4000 * Check and validate the filter control settings passed. 4001 * The function checks for the valid filter/context sizes being 4002 * passed for FCoE and PE. 4003 * 4004 * Returns 0 if the values passed are valid and within 4005 * range else returns an error. 4006 **/ 4007 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4008 struct i40e_filter_control_settings *settings) 4009 { 4010 u32 fcoe_cntx_size, fcoe_filt_size; 4011 u32 pe_cntx_size, pe_filt_size; 4012 u32 fcoe_fmax; 4013 u32 val; 4014 4015 /* Validate FCoE settings passed */ 4016 switch (settings->fcoe_filt_num) { 4017 case I40E_HASH_FILTER_SIZE_1K: 4018 case I40E_HASH_FILTER_SIZE_2K: 4019 case I40E_HASH_FILTER_SIZE_4K: 4020 case I40E_HASH_FILTER_SIZE_8K: 4021 case I40E_HASH_FILTER_SIZE_16K: 4022 case I40E_HASH_FILTER_SIZE_32K: 4023 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4024 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4025 break; 4026 default: 4027 return I40E_ERR_PARAM; 4028 } 4029 4030 switch (settings->fcoe_cntx_num) { 4031 case I40E_DMA_CNTX_SIZE_512: 4032 case I40E_DMA_CNTX_SIZE_1K: 4033 case I40E_DMA_CNTX_SIZE_2K: 4034 case I40E_DMA_CNTX_SIZE_4K: 4035 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4036 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4037 break; 4038 default: 4039 return I40E_ERR_PARAM; 4040 } 4041 4042 /* Validate PE settings passed */ 4043 switch (settings->pe_filt_num) { 4044 case I40E_HASH_FILTER_SIZE_1K: 4045 case I40E_HASH_FILTER_SIZE_2K: 4046 case I40E_HASH_FILTER_SIZE_4K: 4047 case I40E_HASH_FILTER_SIZE_8K: 4048 case I40E_HASH_FILTER_SIZE_16K: 4049 case I40E_HASH_FILTER_SIZE_32K: 4050 case I40E_HASH_FILTER_SIZE_64K: 4051 case I40E_HASH_FILTER_SIZE_128K: 4052 case I40E_HASH_FILTER_SIZE_256K: 4053 case I40E_HASH_FILTER_SIZE_512K: 4054 case I40E_HASH_FILTER_SIZE_1M: 4055 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4056 pe_filt_size <<= (u32)settings->pe_filt_num; 4057 break; 4058 default: 4059 return I40E_ERR_PARAM; 4060 } 4061 4062 switch (settings->pe_cntx_num) { 4063 case I40E_DMA_CNTX_SIZE_512: 4064 case I40E_DMA_CNTX_SIZE_1K: 4065 case I40E_DMA_CNTX_SIZE_2K: 4066 case I40E_DMA_CNTX_SIZE_4K: 4067 case I40E_DMA_CNTX_SIZE_8K: 4068 case I40E_DMA_CNTX_SIZE_16K: 4069 case I40E_DMA_CNTX_SIZE_32K: 4070 case I40E_DMA_CNTX_SIZE_64K: 4071 case I40E_DMA_CNTX_SIZE_128K: 4072 case I40E_DMA_CNTX_SIZE_256K: 4073 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4074 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4075 break; 4076 default: 4077 return I40E_ERR_PARAM; 4078 } 4079 4080 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4081 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4082 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4083 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4084 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4085 return I40E_ERR_INVALID_SIZE; 4086 4087 return 0; 4088 } 4089 4090 /** 4091 * i40e_set_filter_control 4092 * @hw: pointer to the hardware structure 4093 * @settings: Filter control settings 4094 * 4095 * Set the Queue Filters for PE/FCoE and enable filters required 4096 * for a single PF. It is expected that these settings are programmed 4097 * at the driver initialization time. 4098 **/ 4099 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4100 struct i40e_filter_control_settings *settings) 4101 { 4102 i40e_status ret = 0; 4103 u32 hash_lut_size = 0; 4104 u32 val; 4105 4106 if (!settings) 4107 return I40E_ERR_PARAM; 4108 4109 /* Validate the input settings */ 4110 ret = i40e_validate_filter_settings(hw, settings); 4111 if (ret) 4112 return ret; 4113 4114 /* Read the PF Queue Filter control register */ 4115 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4116 4117 /* Program required PE hash buckets for the PF */ 4118 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4119 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4120 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4121 /* Program required PE contexts for the PF */ 4122 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4123 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4124 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4125 4126 /* Program required FCoE hash buckets for the PF */ 4127 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4128 val |= ((u32)settings->fcoe_filt_num << 4129 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4130 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4131 /* Program required FCoE DDP contexts for the PF */ 4132 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4133 val |= ((u32)settings->fcoe_cntx_num << 4134 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4135 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4136 4137 /* Program Hash LUT size for the PF */ 4138 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4139 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4140 hash_lut_size = 1; 4141 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4142 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4143 4144 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4145 if (settings->enable_fdir) 4146 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4147 if (settings->enable_ethtype) 4148 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4149 if (settings->enable_macvlan) 4150 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4151 4152 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4153 4154 return 0; 4155 } 4156 4157 /** 4158 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4159 * @hw: pointer to the hw struct 4160 * @mac_addr: MAC address to use in the filter 4161 * @ethtype: Ethertype to use in the filter 4162 * @flags: Flags that needs to be applied to the filter 4163 * @vsi_seid: seid of the control VSI 4164 * @queue: VSI queue number to send the packet to 4165 * @is_add: Add control packet filter if True else remove 4166 * @stats: Structure to hold information on control filter counts 4167 * @cmd_details: pointer to command details structure or NULL 4168 * 4169 * This command will Add or Remove control packet filter for a control VSI. 4170 * In return it will update the total number of perfect filter count in 4171 * the stats member. 4172 **/ 4173 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4174 u8 *mac_addr, u16 ethtype, u16 flags, 4175 u16 vsi_seid, u16 queue, bool is_add, 4176 struct i40e_control_filter_stats *stats, 4177 struct i40e_asq_cmd_details *cmd_details) 4178 { 4179 struct i40e_aq_desc desc; 4180 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4181 (struct i40e_aqc_add_remove_control_packet_filter *) 4182 &desc.params.raw; 4183 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4184 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4185 &desc.params.raw; 4186 i40e_status status; 4187 4188 if (vsi_seid == 0) 4189 return I40E_ERR_PARAM; 4190 4191 if (is_add) { 4192 i40e_fill_default_direct_cmd_desc(&desc, 4193 i40e_aqc_opc_add_control_packet_filter); 4194 cmd->queue = cpu_to_le16(queue); 4195 } else { 4196 i40e_fill_default_direct_cmd_desc(&desc, 4197 i40e_aqc_opc_remove_control_packet_filter); 4198 } 4199 4200 if (mac_addr) 4201 ether_addr_copy(cmd->mac, mac_addr); 4202 4203 cmd->etype = cpu_to_le16(ethtype); 4204 cmd->flags = cpu_to_le16(flags); 4205 cmd->seid = cpu_to_le16(vsi_seid); 4206 4207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4208 4209 if (!status && stats) { 4210 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4211 stats->etype_used = le16_to_cpu(resp->etype_used); 4212 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4213 stats->etype_free = le16_to_cpu(resp->etype_free); 4214 } 4215 4216 return status; 4217 } 4218 4219 /** 4220 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4221 * @hw: pointer to the hw struct 4222 * @seid: VSI seid to add ethertype filter from 4223 **/ 4224 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4225 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4226 u16 seid) 4227 { 4228 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4229 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4230 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4231 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4232 i40e_status status; 4233 4234 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4235 seid, 0, true, NULL, 4236 NULL); 4237 if (status) 4238 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4239 } 4240 4241 /** 4242 * i40e_aq_alternate_read 4243 * @hw: pointer to the hardware structure 4244 * @reg_addr0: address of first dword to be read 4245 * @reg_val0: pointer for data read from 'reg_addr0' 4246 * @reg_addr1: address of second dword to be read 4247 * @reg_val1: pointer for data read from 'reg_addr1' 4248 * 4249 * Read one or two dwords from alternate structure. Fields are indicated 4250 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4251 * is not passed then only register at 'reg_addr0' is read. 4252 * 4253 **/ 4254 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4255 u32 reg_addr0, u32 *reg_val0, 4256 u32 reg_addr1, u32 *reg_val1) 4257 { 4258 struct i40e_aq_desc desc; 4259 struct i40e_aqc_alternate_write *cmd_resp = 4260 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4261 i40e_status status; 4262 4263 if (!reg_val0) 4264 return I40E_ERR_PARAM; 4265 4266 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4267 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4268 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4269 4270 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4271 4272 if (!status) { 4273 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4274 4275 if (reg_val1) 4276 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4277 } 4278 4279 return status; 4280 } 4281 4282 /** 4283 * i40e_aq_resume_port_tx 4284 * @hw: pointer to the hardware structure 4285 * @cmd_details: pointer to command details structure or NULL 4286 * 4287 * Resume port's Tx traffic 4288 **/ 4289 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4290 struct i40e_asq_cmd_details *cmd_details) 4291 { 4292 struct i40e_aq_desc desc; 4293 i40e_status status; 4294 4295 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4296 4297 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4298 4299 return status; 4300 } 4301 4302 /** 4303 * i40e_set_pci_config_data - store PCI bus info 4304 * @hw: pointer to hardware structure 4305 * @link_status: the link status word from PCI config space 4306 * 4307 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4308 **/ 4309 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4310 { 4311 hw->bus.type = i40e_bus_type_pci_express; 4312 4313 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4314 case PCI_EXP_LNKSTA_NLW_X1: 4315 hw->bus.width = i40e_bus_width_pcie_x1; 4316 break; 4317 case PCI_EXP_LNKSTA_NLW_X2: 4318 hw->bus.width = i40e_bus_width_pcie_x2; 4319 break; 4320 case PCI_EXP_LNKSTA_NLW_X4: 4321 hw->bus.width = i40e_bus_width_pcie_x4; 4322 break; 4323 case PCI_EXP_LNKSTA_NLW_X8: 4324 hw->bus.width = i40e_bus_width_pcie_x8; 4325 break; 4326 default: 4327 hw->bus.width = i40e_bus_width_unknown; 4328 break; 4329 } 4330 4331 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4332 case PCI_EXP_LNKSTA_CLS_2_5GB: 4333 hw->bus.speed = i40e_bus_speed_2500; 4334 break; 4335 case PCI_EXP_LNKSTA_CLS_5_0GB: 4336 hw->bus.speed = i40e_bus_speed_5000; 4337 break; 4338 case PCI_EXP_LNKSTA_CLS_8_0GB: 4339 hw->bus.speed = i40e_bus_speed_8000; 4340 break; 4341 default: 4342 hw->bus.speed = i40e_bus_speed_unknown; 4343 break; 4344 } 4345 } 4346 4347 /** 4348 * i40e_aq_debug_dump 4349 * @hw: pointer to the hardware structure 4350 * @cluster_id: specific cluster to dump 4351 * @table_id: table id within cluster 4352 * @start_index: index of line in the block to read 4353 * @buff_size: dump buffer size 4354 * @buff: dump buffer 4355 * @ret_buff_size: actual buffer size returned 4356 * @ret_next_table: next block to read 4357 * @ret_next_index: next index to read 4358 * 4359 * Dump internal FW/HW data for debug purposes. 4360 * 4361 **/ 4362 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4363 u8 table_id, u32 start_index, u16 buff_size, 4364 void *buff, u16 *ret_buff_size, 4365 u8 *ret_next_table, u32 *ret_next_index, 4366 struct i40e_asq_cmd_details *cmd_details) 4367 { 4368 struct i40e_aq_desc desc; 4369 struct i40e_aqc_debug_dump_internals *cmd = 4370 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4371 struct i40e_aqc_debug_dump_internals *resp = 4372 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4373 i40e_status status; 4374 4375 if (buff_size == 0 || !buff) 4376 return I40E_ERR_PARAM; 4377 4378 i40e_fill_default_direct_cmd_desc(&desc, 4379 i40e_aqc_opc_debug_dump_internals); 4380 /* Indirect Command */ 4381 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4382 if (buff_size > I40E_AQ_LARGE_BUF) 4383 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4384 4385 cmd->cluster_id = cluster_id; 4386 cmd->table_id = table_id; 4387 cmd->idx = cpu_to_le32(start_index); 4388 4389 desc.datalen = cpu_to_le16(buff_size); 4390 4391 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4392 if (!status) { 4393 if (ret_buff_size) 4394 *ret_buff_size = le16_to_cpu(desc.datalen); 4395 if (ret_next_table) 4396 *ret_next_table = resp->table_id; 4397 if (ret_next_index) 4398 *ret_next_index = le32_to_cpu(resp->idx); 4399 } 4400 4401 return status; 4402 } 4403 4404 /** 4405 * i40e_read_bw_from_alt_ram 4406 * @hw: pointer to the hardware structure 4407 * @max_bw: pointer for max_bw read 4408 * @min_bw: pointer for min_bw read 4409 * @min_valid: pointer for bool that is true if min_bw is a valid value 4410 * @max_valid: pointer for bool that is true if max_bw is a valid value 4411 * 4412 * Read bw from the alternate ram for the given pf 4413 **/ 4414 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4415 u32 *max_bw, u32 *min_bw, 4416 bool *min_valid, bool *max_valid) 4417 { 4418 i40e_status status; 4419 u32 max_bw_addr, min_bw_addr; 4420 4421 /* Calculate the address of the min/max bw registers */ 4422 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4423 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4424 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4425 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4426 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4427 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4428 4429 /* Read the bandwidths from alt ram */ 4430 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4431 min_bw_addr, min_bw); 4432 4433 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4434 *min_valid = true; 4435 else 4436 *min_valid = false; 4437 4438 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4439 *max_valid = true; 4440 else 4441 *max_valid = false; 4442 4443 return status; 4444 } 4445 4446 /** 4447 * i40e_aq_configure_partition_bw 4448 * @hw: pointer to the hardware structure 4449 * @bw_data: Buffer holding valid pfs and bw limits 4450 * @cmd_details: pointer to command details 4451 * 4452 * Configure partitions guaranteed/max bw 4453 **/ 4454 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4455 struct i40e_aqc_configure_partition_bw_data *bw_data, 4456 struct i40e_asq_cmd_details *cmd_details) 4457 { 4458 i40e_status status; 4459 struct i40e_aq_desc desc; 4460 u16 bwd_size = sizeof(*bw_data); 4461 4462 i40e_fill_default_direct_cmd_desc(&desc, 4463 i40e_aqc_opc_configure_partition_bw); 4464 4465 /* Indirect command */ 4466 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4467 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4468 4469 if (bwd_size > I40E_AQ_LARGE_BUF) 4470 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4471 4472 desc.datalen = cpu_to_le16(bwd_size); 4473 4474 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4475 cmd_details); 4476 4477 return status; 4478 } 4479 4480 /** 4481 * i40e_read_phy_register_clause22 4482 * @hw: pointer to the HW structure 4483 * @reg: register address in the page 4484 * @phy_adr: PHY address on MDIO interface 4485 * @value: PHY register value 4486 * 4487 * Reads specified PHY register value 4488 **/ 4489 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4490 u16 reg, u8 phy_addr, u16 *value) 4491 { 4492 i40e_status status = I40E_ERR_TIMEOUT; 4493 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4494 u32 command = 0; 4495 u16 retry = 1000; 4496 4497 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4498 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4499 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4500 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4501 (I40E_GLGEN_MSCA_MDICMD_MASK); 4502 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4503 do { 4504 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4505 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4506 status = 0; 4507 break; 4508 } 4509 udelay(10); 4510 retry--; 4511 } while (retry); 4512 4513 if (status) { 4514 i40e_debug(hw, I40E_DEBUG_PHY, 4515 "PHY: Can't write command to external PHY.\n"); 4516 } else { 4517 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4518 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4519 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4520 } 4521 4522 return status; 4523 } 4524 4525 /** 4526 * i40e_write_phy_register_clause22 4527 * @hw: pointer to the HW structure 4528 * @reg: register address in the page 4529 * @phy_adr: PHY address on MDIO interface 4530 * @value: PHY register value 4531 * 4532 * Writes specified PHY register value 4533 **/ 4534 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4535 u16 reg, u8 phy_addr, u16 value) 4536 { 4537 i40e_status status = I40E_ERR_TIMEOUT; 4538 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4539 u32 command = 0; 4540 u16 retry = 1000; 4541 4542 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4543 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4544 4545 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4546 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4547 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4548 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4549 (I40E_GLGEN_MSCA_MDICMD_MASK); 4550 4551 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4552 do { 4553 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4554 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4555 status = 0; 4556 break; 4557 } 4558 udelay(10); 4559 retry--; 4560 } while (retry); 4561 4562 return status; 4563 } 4564 4565 /** 4566 * i40e_read_phy_register_clause45 4567 * @hw: pointer to the HW structure 4568 * @page: registers page number 4569 * @reg: register address in the page 4570 * @phy_adr: PHY address on MDIO interface 4571 * @value: PHY register value 4572 * 4573 * Reads specified PHY register value 4574 **/ 4575 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4576 u8 page, u16 reg, u8 phy_addr, u16 *value) 4577 { 4578 i40e_status status = I40E_ERR_TIMEOUT; 4579 u32 command = 0; 4580 u16 retry = 1000; 4581 u8 port_num = hw->func_caps.mdio_port_num; 4582 4583 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4584 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4585 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4586 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4587 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4588 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4589 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4590 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4591 do { 4592 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4593 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4594 status = 0; 4595 break; 4596 } 4597 usleep_range(10, 20); 4598 retry--; 4599 } while (retry); 4600 4601 if (status) { 4602 i40e_debug(hw, I40E_DEBUG_PHY, 4603 "PHY: Can't write command to external PHY.\n"); 4604 goto phy_read_end; 4605 } 4606 4607 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4608 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4609 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4610 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4611 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4612 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4613 status = I40E_ERR_TIMEOUT; 4614 retry = 1000; 4615 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4616 do { 4617 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4618 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4619 status = 0; 4620 break; 4621 } 4622 usleep_range(10, 20); 4623 retry--; 4624 } while (retry); 4625 4626 if (!status) { 4627 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4628 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4629 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4630 } else { 4631 i40e_debug(hw, I40E_DEBUG_PHY, 4632 "PHY: Can't read register value from external PHY.\n"); 4633 } 4634 4635 phy_read_end: 4636 return status; 4637 } 4638 4639 /** 4640 * i40e_write_phy_register_clause45 4641 * @hw: pointer to the HW structure 4642 * @page: registers page number 4643 * @reg: register address in the page 4644 * @phy_adr: PHY address on MDIO interface 4645 * @value: PHY register value 4646 * 4647 * Writes value to specified PHY register 4648 **/ 4649 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4650 u8 page, u16 reg, u8 phy_addr, u16 value) 4651 { 4652 i40e_status status = I40E_ERR_TIMEOUT; 4653 u32 command = 0; 4654 u16 retry = 1000; 4655 u8 port_num = hw->func_caps.mdio_port_num; 4656 4657 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4658 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4659 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4660 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4661 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4662 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4663 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4664 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4665 do { 4666 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4667 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4668 status = 0; 4669 break; 4670 } 4671 usleep_range(10, 20); 4672 retry--; 4673 } while (retry); 4674 if (status) { 4675 i40e_debug(hw, I40E_DEBUG_PHY, 4676 "PHY: Can't write command to external PHY.\n"); 4677 goto phy_write_end; 4678 } 4679 4680 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4681 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4682 4683 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4684 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4685 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4686 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4687 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4688 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4689 status = I40E_ERR_TIMEOUT; 4690 retry = 1000; 4691 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4692 do { 4693 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4694 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4695 status = 0; 4696 break; 4697 } 4698 usleep_range(10, 20); 4699 retry--; 4700 } while (retry); 4701 4702 phy_write_end: 4703 return status; 4704 } 4705 4706 /** 4707 * i40e_write_phy_register 4708 * @hw: pointer to the HW structure 4709 * @page: registers page number 4710 * @reg: register address in the page 4711 * @phy_adr: PHY address on MDIO interface 4712 * @value: PHY register value 4713 * 4714 * Writes value to specified PHY register 4715 **/ 4716 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4717 u8 page, u16 reg, u8 phy_addr, u16 value) 4718 { 4719 i40e_status status; 4720 4721 switch (hw->device_id) { 4722 case I40E_DEV_ID_1G_BASE_T_X722: 4723 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4724 value); 4725 break; 4726 case I40E_DEV_ID_10G_BASE_T: 4727 case I40E_DEV_ID_10G_BASE_T4: 4728 case I40E_DEV_ID_10G_BASE_T_X722: 4729 case I40E_DEV_ID_25G_B: 4730 case I40E_DEV_ID_25G_SFP28: 4731 status = i40e_write_phy_register_clause45(hw, page, reg, 4732 phy_addr, value); 4733 break; 4734 default: 4735 status = I40E_ERR_UNKNOWN_PHY; 4736 break; 4737 } 4738 4739 return status; 4740 } 4741 4742 /** 4743 * i40e_read_phy_register 4744 * @hw: pointer to the HW structure 4745 * @page: registers page number 4746 * @reg: register address in the page 4747 * @phy_adr: PHY address on MDIO interface 4748 * @value: PHY register value 4749 * 4750 * Reads specified PHY register value 4751 **/ 4752 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4753 u8 page, u16 reg, u8 phy_addr, u16 *value) 4754 { 4755 i40e_status status; 4756 4757 switch (hw->device_id) { 4758 case I40E_DEV_ID_1G_BASE_T_X722: 4759 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4760 value); 4761 break; 4762 case I40E_DEV_ID_10G_BASE_T: 4763 case I40E_DEV_ID_10G_BASE_T4: 4764 case I40E_DEV_ID_10G_BASE_T_X722: 4765 case I40E_DEV_ID_25G_B: 4766 case I40E_DEV_ID_25G_SFP28: 4767 status = i40e_read_phy_register_clause45(hw, page, reg, 4768 phy_addr, value); 4769 break; 4770 default: 4771 status = I40E_ERR_UNKNOWN_PHY; 4772 break; 4773 } 4774 4775 return status; 4776 } 4777 4778 /** 4779 * i40e_get_phy_address 4780 * @hw: pointer to the HW structure 4781 * @dev_num: PHY port num that address we want 4782 * @phy_addr: Returned PHY address 4783 * 4784 * Gets PHY address for current port 4785 **/ 4786 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4787 { 4788 u8 port_num = hw->func_caps.mdio_port_num; 4789 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4790 4791 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4792 } 4793 4794 /** 4795 * i40e_blink_phy_led 4796 * @hw: pointer to the HW structure 4797 * @time: time how long led will blinks in secs 4798 * @interval: gap between LED on and off in msecs 4799 * 4800 * Blinks PHY link LED 4801 **/ 4802 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4803 u32 time, u32 interval) 4804 { 4805 i40e_status status = 0; 4806 u32 i; 4807 u16 led_ctl; 4808 u16 gpio_led_port; 4809 u16 led_reg; 4810 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4811 u8 phy_addr = 0; 4812 u8 port_num; 4813 4814 i = rd32(hw, I40E_PFGEN_PORTNUM); 4815 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4816 phy_addr = i40e_get_phy_address(hw, port_num); 4817 4818 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4819 led_addr++) { 4820 status = i40e_read_phy_register_clause45(hw, 4821 I40E_PHY_COM_REG_PAGE, 4822 led_addr, phy_addr, 4823 &led_reg); 4824 if (status) 4825 goto phy_blinking_end; 4826 led_ctl = led_reg; 4827 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4828 led_reg = 0; 4829 status = i40e_write_phy_register_clause45(hw, 4830 I40E_PHY_COM_REG_PAGE, 4831 led_addr, phy_addr, 4832 led_reg); 4833 if (status) 4834 goto phy_blinking_end; 4835 break; 4836 } 4837 } 4838 4839 if (time > 0 && interval > 0) { 4840 for (i = 0; i < time * 1000; i += interval) { 4841 status = i40e_read_phy_register_clause45(hw, 4842 I40E_PHY_COM_REG_PAGE, 4843 led_addr, phy_addr, &led_reg); 4844 if (status) 4845 goto restore_config; 4846 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4847 led_reg = 0; 4848 else 4849 led_reg = I40E_PHY_LED_MANUAL_ON; 4850 status = i40e_write_phy_register_clause45(hw, 4851 I40E_PHY_COM_REG_PAGE, 4852 led_addr, phy_addr, led_reg); 4853 if (status) 4854 goto restore_config; 4855 msleep(interval); 4856 } 4857 } 4858 4859 restore_config: 4860 status = i40e_write_phy_register_clause45(hw, 4861 I40E_PHY_COM_REG_PAGE, 4862 led_addr, phy_addr, led_ctl); 4863 4864 phy_blinking_end: 4865 return status; 4866 } 4867 4868 /** 4869 * i40e_led_get_reg - read LED register 4870 * @hw: pointer to the HW structure 4871 * @led_addr: LED register address 4872 * @reg_val: read register value 4873 **/ 4874 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4875 u32 *reg_val) 4876 { 4877 enum i40e_status_code status; 4878 u8 phy_addr = 0; 4879 u8 port_num; 4880 u32 i; 4881 4882 *reg_val = 0; 4883 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4884 status = 4885 i40e_aq_get_phy_register(hw, 4886 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4887 I40E_PHY_COM_REG_PAGE, 4888 I40E_PHY_LED_PROV_REG_1, 4889 reg_val, NULL); 4890 } else { 4891 i = rd32(hw, I40E_PFGEN_PORTNUM); 4892 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4893 phy_addr = i40e_get_phy_address(hw, port_num); 4894 status = i40e_read_phy_register_clause45(hw, 4895 I40E_PHY_COM_REG_PAGE, 4896 led_addr, phy_addr, 4897 (u16 *)reg_val); 4898 } 4899 return status; 4900 } 4901 4902 /** 4903 * i40e_led_set_reg - write LED register 4904 * @hw: pointer to the HW structure 4905 * @led_addr: LED register address 4906 * @reg_val: register value to write 4907 **/ 4908 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4909 u32 reg_val) 4910 { 4911 enum i40e_status_code status; 4912 u8 phy_addr = 0; 4913 u8 port_num; 4914 u32 i; 4915 4916 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4917 status = 4918 i40e_aq_set_phy_register(hw, 4919 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4920 I40E_PHY_COM_REG_PAGE, 4921 I40E_PHY_LED_PROV_REG_1, 4922 reg_val, NULL); 4923 } else { 4924 i = rd32(hw, I40E_PFGEN_PORTNUM); 4925 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4926 phy_addr = i40e_get_phy_address(hw, port_num); 4927 status = i40e_write_phy_register_clause45(hw, 4928 I40E_PHY_COM_REG_PAGE, 4929 led_addr, phy_addr, 4930 (u16)reg_val); 4931 } 4932 4933 return status; 4934 } 4935 4936 /** 4937 * i40e_led_get_phy - return current on/off mode 4938 * @hw: pointer to the hw struct 4939 * @led_addr: address of led register to use 4940 * @val: original value of register to use 4941 * 4942 **/ 4943 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4944 u16 *val) 4945 { 4946 i40e_status status = 0; 4947 u16 gpio_led_port; 4948 u8 phy_addr = 0; 4949 u16 reg_val; 4950 u16 temp_addr; 4951 u8 port_num; 4952 u32 i; 4953 u32 reg_val_aq; 4954 4955 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4956 status = 4957 i40e_aq_get_phy_register(hw, 4958 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4959 I40E_PHY_COM_REG_PAGE, 4960 I40E_PHY_LED_PROV_REG_1, 4961 ®_val_aq, NULL); 4962 if (status == I40E_SUCCESS) 4963 *val = (u16)reg_val_aq; 4964 return status; 4965 } 4966 temp_addr = I40E_PHY_LED_PROV_REG_1; 4967 i = rd32(hw, I40E_PFGEN_PORTNUM); 4968 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4969 phy_addr = i40e_get_phy_address(hw, port_num); 4970 4971 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4972 temp_addr++) { 4973 status = i40e_read_phy_register_clause45(hw, 4974 I40E_PHY_COM_REG_PAGE, 4975 temp_addr, phy_addr, 4976 ®_val); 4977 if (status) 4978 return status; 4979 *val = reg_val; 4980 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4981 *led_addr = temp_addr; 4982 break; 4983 } 4984 } 4985 return status; 4986 } 4987 4988 /** 4989 * i40e_led_set_phy 4990 * @hw: pointer to the HW structure 4991 * @on: true or false 4992 * @mode: original val plus bit for set or ignore 4993 * Set led's on or off when controlled by the PHY 4994 * 4995 **/ 4996 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4997 u16 led_addr, u32 mode) 4998 { 4999 i40e_status status = 0; 5000 u32 led_ctl = 0; 5001 u32 led_reg = 0; 5002 5003 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5004 if (status) 5005 return status; 5006 led_ctl = led_reg; 5007 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5008 led_reg = 0; 5009 status = i40e_led_set_reg(hw, led_addr, led_reg); 5010 if (status) 5011 return status; 5012 } 5013 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5014 if (status) 5015 goto restore_config; 5016 if (on) 5017 led_reg = I40E_PHY_LED_MANUAL_ON; 5018 else 5019 led_reg = 0; 5020 5021 status = i40e_led_set_reg(hw, led_addr, led_reg); 5022 if (status) 5023 goto restore_config; 5024 if (mode & I40E_PHY_LED_MODE_ORIG) { 5025 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5026 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5027 } 5028 return status; 5029 5030 restore_config: 5031 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5032 return status; 5033 } 5034 5035 /** 5036 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5037 * @hw: pointer to the hw struct 5038 * @reg_addr: register address 5039 * @reg_val: ptr to register value 5040 * @cmd_details: pointer to command details structure or NULL 5041 * 5042 * Use the firmware to read the Rx control register, 5043 * especially useful if the Rx unit is under heavy pressure 5044 **/ 5045 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5046 u32 reg_addr, u32 *reg_val, 5047 struct i40e_asq_cmd_details *cmd_details) 5048 { 5049 struct i40e_aq_desc desc; 5050 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5051 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5052 i40e_status status; 5053 5054 if (!reg_val) 5055 return I40E_ERR_PARAM; 5056 5057 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5058 5059 cmd_resp->address = cpu_to_le32(reg_addr); 5060 5061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5062 5063 if (status == 0) 5064 *reg_val = le32_to_cpu(cmd_resp->value); 5065 5066 return status; 5067 } 5068 5069 /** 5070 * i40e_read_rx_ctl - read from an Rx control register 5071 * @hw: pointer to the hw struct 5072 * @reg_addr: register address 5073 **/ 5074 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5075 { 5076 i40e_status status = 0; 5077 bool use_register; 5078 int retry = 5; 5079 u32 val = 0; 5080 5081 use_register = (((hw->aq.api_maj_ver == 1) && 5082 (hw->aq.api_min_ver < 5)) || 5083 (hw->mac.type == I40E_MAC_X722)); 5084 if (!use_register) { 5085 do_retry: 5086 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5087 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5088 usleep_range(1000, 2000); 5089 retry--; 5090 goto do_retry; 5091 } 5092 } 5093 5094 /* if the AQ access failed, try the old-fashioned way */ 5095 if (status || use_register) 5096 val = rd32(hw, reg_addr); 5097 5098 return val; 5099 } 5100 5101 /** 5102 * i40e_aq_rx_ctl_write_register 5103 * @hw: pointer to the hw struct 5104 * @reg_addr: register address 5105 * @reg_val: register value 5106 * @cmd_details: pointer to command details structure or NULL 5107 * 5108 * Use the firmware to write to an Rx control register, 5109 * especially useful if the Rx unit is under heavy pressure 5110 **/ 5111 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5112 u32 reg_addr, u32 reg_val, 5113 struct i40e_asq_cmd_details *cmd_details) 5114 { 5115 struct i40e_aq_desc desc; 5116 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5117 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5118 i40e_status status; 5119 5120 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5121 5122 cmd->address = cpu_to_le32(reg_addr); 5123 cmd->value = cpu_to_le32(reg_val); 5124 5125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5126 5127 return status; 5128 } 5129 5130 /** 5131 * i40e_write_rx_ctl - write to an Rx control register 5132 * @hw: pointer to the hw struct 5133 * @reg_addr: register address 5134 * @reg_val: register value 5135 **/ 5136 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5137 { 5138 i40e_status status = 0; 5139 bool use_register; 5140 int retry = 5; 5141 5142 use_register = (((hw->aq.api_maj_ver == 1) && 5143 (hw->aq.api_min_ver < 5)) || 5144 (hw->mac.type == I40E_MAC_X722)); 5145 if (!use_register) { 5146 do_retry: 5147 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5148 reg_val, NULL); 5149 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5150 usleep_range(1000, 2000); 5151 retry--; 5152 goto do_retry; 5153 } 5154 } 5155 5156 /* if the AQ access failed, try the old-fashioned way */ 5157 if (status || use_register) 5158 wr32(hw, reg_addr, reg_val); 5159 } 5160 5161 /** 5162 * i40e_aq_set_phy_register 5163 * @hw: pointer to the hw struct 5164 * @phy_select: select which phy should be accessed 5165 * @dev_addr: PHY device address 5166 * @reg_addr: PHY register address 5167 * @reg_val: new register value 5168 * @cmd_details: pointer to command details structure or NULL 5169 * 5170 * Write the external PHY register. 5171 **/ 5172 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5173 u8 phy_select, u8 dev_addr, 5174 u32 reg_addr, u32 reg_val, 5175 struct i40e_asq_cmd_details *cmd_details) 5176 { 5177 struct i40e_aq_desc desc; 5178 struct i40e_aqc_phy_register_access *cmd = 5179 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5180 i40e_status status; 5181 5182 i40e_fill_default_direct_cmd_desc(&desc, 5183 i40e_aqc_opc_set_phy_register); 5184 5185 cmd->phy_interface = phy_select; 5186 cmd->dev_address = dev_addr; 5187 cmd->reg_address = cpu_to_le32(reg_addr); 5188 cmd->reg_value = cpu_to_le32(reg_val); 5189 5190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5191 5192 return status; 5193 } 5194 5195 /** 5196 * i40e_aq_get_phy_register 5197 * @hw: pointer to the hw struct 5198 * @phy_select: select which phy should be accessed 5199 * @dev_addr: PHY device address 5200 * @reg_addr: PHY register address 5201 * @reg_val: read register value 5202 * @cmd_details: pointer to command details structure or NULL 5203 * 5204 * Read the external PHY register. 5205 **/ 5206 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5207 u8 phy_select, u8 dev_addr, 5208 u32 reg_addr, u32 *reg_val, 5209 struct i40e_asq_cmd_details *cmd_details) 5210 { 5211 struct i40e_aq_desc desc; 5212 struct i40e_aqc_phy_register_access *cmd = 5213 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5214 i40e_status status; 5215 5216 i40e_fill_default_direct_cmd_desc(&desc, 5217 i40e_aqc_opc_get_phy_register); 5218 5219 cmd->phy_interface = phy_select; 5220 cmd->dev_address = dev_addr; 5221 cmd->reg_address = cpu_to_le32(reg_addr); 5222 5223 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5224 if (!status) 5225 *reg_val = le32_to_cpu(cmd->reg_value); 5226 5227 return status; 5228 } 5229 5230 /** 5231 * i40e_aq_write_ppp - Write pipeline personalization profile (ppp) 5232 * @hw: pointer to the hw struct 5233 * @buff: command buffer (size in bytes = buff_size) 5234 * @buff_size: buffer size in bytes 5235 * @track_id: package tracking id 5236 * @error_offset: returns error offset 5237 * @error_info: returns error information 5238 * @cmd_details: pointer to command details structure or NULL 5239 **/ 5240 enum 5241 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff, 5242 u16 buff_size, u32 track_id, 5243 u32 *error_offset, u32 *error_info, 5244 struct i40e_asq_cmd_details *cmd_details) 5245 { 5246 struct i40e_aq_desc desc; 5247 struct i40e_aqc_write_personalization_profile *cmd = 5248 (struct i40e_aqc_write_personalization_profile *) 5249 &desc.params.raw; 5250 struct i40e_aqc_write_ppp_resp *resp; 5251 i40e_status status; 5252 5253 i40e_fill_default_direct_cmd_desc(&desc, 5254 i40e_aqc_opc_write_personalization_profile); 5255 5256 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5257 if (buff_size > I40E_AQ_LARGE_BUF) 5258 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5259 5260 desc.datalen = cpu_to_le16(buff_size); 5261 5262 cmd->profile_track_id = cpu_to_le32(track_id); 5263 5264 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5265 if (!status) { 5266 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw; 5267 if (error_offset) 5268 *error_offset = le32_to_cpu(resp->error_offset); 5269 if (error_info) 5270 *error_info = le32_to_cpu(resp->error_info); 5271 } 5272 5273 return status; 5274 } 5275 5276 /** 5277 * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp) 5278 * @hw: pointer to the hw struct 5279 * @buff: command buffer (size in bytes = buff_size) 5280 * @buff_size: buffer size in bytes 5281 * @cmd_details: pointer to command details structure or NULL 5282 **/ 5283 enum 5284 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff, 5285 u16 buff_size, u8 flags, 5286 struct i40e_asq_cmd_details *cmd_details) 5287 { 5288 struct i40e_aq_desc desc; 5289 struct i40e_aqc_get_applied_profiles *cmd = 5290 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5291 i40e_status status; 5292 5293 i40e_fill_default_direct_cmd_desc(&desc, 5294 i40e_aqc_opc_get_personalization_profile_list); 5295 5296 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5297 if (buff_size > I40E_AQ_LARGE_BUF) 5298 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5299 desc.datalen = cpu_to_le16(buff_size); 5300 5301 cmd->flags = flags; 5302 5303 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5304 5305 return status; 5306 } 5307 5308 /** 5309 * i40e_find_segment_in_package 5310 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5311 * @pkg_hdr: pointer to the package header to be searched 5312 * 5313 * This function searches a package file for a particular segment type. On 5314 * success it returns a pointer to the segment header, otherwise it will 5315 * return NULL. 5316 **/ 5317 struct i40e_generic_seg_header * 5318 i40e_find_segment_in_package(u32 segment_type, 5319 struct i40e_package_header *pkg_hdr) 5320 { 5321 struct i40e_generic_seg_header *segment; 5322 u32 i; 5323 5324 /* Search all package segments for the requested segment type */ 5325 for (i = 0; i < pkg_hdr->segment_count; i++) { 5326 segment = 5327 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5328 pkg_hdr->segment_offset[i]); 5329 5330 if (segment->type == segment_type) 5331 return segment; 5332 } 5333 5334 return NULL; 5335 } 5336 5337 /** 5338 * i40e_write_profile 5339 * @hw: pointer to the hardware structure 5340 * @profile: pointer to the profile segment of the package to be downloaded 5341 * @track_id: package tracking id 5342 * 5343 * Handles the download of a complete package. 5344 */ 5345 enum i40e_status_code 5346 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5347 u32 track_id) 5348 { 5349 i40e_status status = 0; 5350 struct i40e_section_table *sec_tbl; 5351 struct i40e_profile_section_header *sec = NULL; 5352 u32 dev_cnt; 5353 u32 vendor_dev_id; 5354 u32 *nvm; 5355 u32 section_size = 0; 5356 u32 offset = 0, info = 0; 5357 u32 i; 5358 5359 if (!track_id) { 5360 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0."); 5361 return I40E_NOT_SUPPORTED; 5362 } 5363 5364 dev_cnt = profile->device_table_count; 5365 5366 for (i = 0; i < dev_cnt; i++) { 5367 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5368 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5369 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5370 break; 5371 } 5372 if (i == dev_cnt) { 5373 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP"); 5374 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5375 } 5376 5377 nvm = (u32 *)&profile->device_table[dev_cnt]; 5378 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5379 5380 for (i = 0; i < sec_tbl->section_count; i++) { 5381 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5382 sec_tbl->section_offset[i]); 5383 5384 /* Skip 'AQ', 'note' and 'name' sections */ 5385 if (sec->section.type != SECTION_TYPE_MMIO) 5386 continue; 5387 5388 section_size = sec->section.size + 5389 sizeof(struct i40e_profile_section_header); 5390 5391 /* Write profile */ 5392 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size, 5393 track_id, &offset, &info, NULL); 5394 if (status) { 5395 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5396 "Failed to write profile: offset %d, info %d", 5397 offset, info); 5398 break; 5399 } 5400 } 5401 return status; 5402 } 5403 5404 /** 5405 * i40e_add_pinfo_to_list 5406 * @hw: pointer to the hardware structure 5407 * @profile: pointer to the profile segment of the package 5408 * @profile_info_sec: buffer for information section 5409 * @track_id: package tracking id 5410 * 5411 * Register a profile to the list of loaded profiles. 5412 */ 5413 enum i40e_status_code 5414 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5415 struct i40e_profile_segment *profile, 5416 u8 *profile_info_sec, u32 track_id) 5417 { 5418 i40e_status status = 0; 5419 struct i40e_profile_section_header *sec = NULL; 5420 struct i40e_profile_info *pinfo; 5421 u32 offset = 0, info = 0; 5422 5423 sec = (struct i40e_profile_section_header *)profile_info_sec; 5424 sec->tbl_size = 1; 5425 sec->data_end = sizeof(struct i40e_profile_section_header) + 5426 sizeof(struct i40e_profile_info); 5427 sec->section.type = SECTION_TYPE_INFO; 5428 sec->section.offset = sizeof(struct i40e_profile_section_header); 5429 sec->section.size = sizeof(struct i40e_profile_info); 5430 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5431 sec->section.offset); 5432 pinfo->track_id = track_id; 5433 pinfo->version = profile->version; 5434 pinfo->op = I40E_PPP_ADD_TRACKID; 5435 memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE); 5436 5437 status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end, 5438 track_id, &offset, &info, NULL); 5439 5440 return status; 5441 } 5442 5443 /** 5444 * i40e_aq_add_cloud_filters 5445 * @hw: pointer to the hardware structure 5446 * @seid: VSI seid to add cloud filters from 5447 * @filters: Buffer which contains the filters to be added 5448 * @filter_count: number of filters contained in the buffer 5449 * 5450 * Set the cloud filters for a given VSI. The contents of the 5451 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5452 * of the function. 5453 * 5454 **/ 5455 enum i40e_status_code 5456 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5457 struct i40e_aqc_cloud_filters_element_data *filters, 5458 u8 filter_count) 5459 { 5460 struct i40e_aq_desc desc; 5461 struct i40e_aqc_add_remove_cloud_filters *cmd = 5462 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5463 enum i40e_status_code status; 5464 u16 buff_len; 5465 5466 i40e_fill_default_direct_cmd_desc(&desc, 5467 i40e_aqc_opc_add_cloud_filters); 5468 5469 buff_len = filter_count * sizeof(*filters); 5470 desc.datalen = cpu_to_le16(buff_len); 5471 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5472 cmd->num_filters = filter_count; 5473 cmd->seid = cpu_to_le16(seid); 5474 5475 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5476 5477 return status; 5478 } 5479 5480 /** 5481 * i40e_aq_add_cloud_filters_bb 5482 * @hw: pointer to the hardware structure 5483 * @seid: VSI seid to add cloud filters from 5484 * @filters: Buffer which contains the filters in big buffer to be added 5485 * @filter_count: number of filters contained in the buffer 5486 * 5487 * Set the big buffer cloud filters for a given VSI. The contents of the 5488 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5489 * function. 5490 * 5491 **/ 5492 i40e_status 5493 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5494 struct i40e_aqc_cloud_filters_element_bb *filters, 5495 u8 filter_count) 5496 { 5497 struct i40e_aq_desc desc; 5498 struct i40e_aqc_add_remove_cloud_filters *cmd = 5499 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5500 i40e_status status; 5501 u16 buff_len; 5502 int i; 5503 5504 i40e_fill_default_direct_cmd_desc(&desc, 5505 i40e_aqc_opc_add_cloud_filters); 5506 5507 buff_len = filter_count * sizeof(*filters); 5508 desc.datalen = cpu_to_le16(buff_len); 5509 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5510 cmd->num_filters = filter_count; 5511 cmd->seid = cpu_to_le16(seid); 5512 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5513 5514 for (i = 0; i < filter_count; i++) { 5515 u16 tnl_type; 5516 u32 ti; 5517 5518 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5519 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5520 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5521 5522 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5523 * one more byte further than normally used for Tenant ID in 5524 * other tunnel types. 5525 */ 5526 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5527 ti = le32_to_cpu(filters[i].element.tenant_id); 5528 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5529 } 5530 } 5531 5532 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5533 5534 return status; 5535 } 5536 5537 /** 5538 * i40e_aq_rem_cloud_filters 5539 * @hw: pointer to the hardware structure 5540 * @seid: VSI seid to remove cloud filters from 5541 * @filters: Buffer which contains the filters to be removed 5542 * @filter_count: number of filters contained in the buffer 5543 * 5544 * Remove the cloud filters for a given VSI. The contents of the 5545 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5546 * of the function. 5547 * 5548 **/ 5549 enum i40e_status_code 5550 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5551 struct i40e_aqc_cloud_filters_element_data *filters, 5552 u8 filter_count) 5553 { 5554 struct i40e_aq_desc desc; 5555 struct i40e_aqc_add_remove_cloud_filters *cmd = 5556 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5557 enum i40e_status_code status; 5558 u16 buff_len; 5559 5560 i40e_fill_default_direct_cmd_desc(&desc, 5561 i40e_aqc_opc_remove_cloud_filters); 5562 5563 buff_len = filter_count * sizeof(*filters); 5564 desc.datalen = cpu_to_le16(buff_len); 5565 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5566 cmd->num_filters = filter_count; 5567 cmd->seid = cpu_to_le16(seid); 5568 5569 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5570 5571 return status; 5572 } 5573 5574 /** 5575 * i40e_aq_rem_cloud_filters_bb 5576 * @hw: pointer to the hardware structure 5577 * @seid: VSI seid to remove cloud filters from 5578 * @filters: Buffer which contains the filters in big buffer to be removed 5579 * @filter_count: number of filters contained in the buffer 5580 * 5581 * Remove the big buffer cloud filters for a given VSI. The contents of the 5582 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5583 * function. 5584 * 5585 **/ 5586 i40e_status 5587 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5588 struct i40e_aqc_cloud_filters_element_bb *filters, 5589 u8 filter_count) 5590 { 5591 struct i40e_aq_desc desc; 5592 struct i40e_aqc_add_remove_cloud_filters *cmd = 5593 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5594 i40e_status status; 5595 u16 buff_len; 5596 int i; 5597 5598 i40e_fill_default_direct_cmd_desc(&desc, 5599 i40e_aqc_opc_remove_cloud_filters); 5600 5601 buff_len = filter_count * sizeof(*filters); 5602 desc.datalen = cpu_to_le16(buff_len); 5603 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5604 cmd->num_filters = filter_count; 5605 cmd->seid = cpu_to_le16(seid); 5606 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5607 5608 for (i = 0; i < filter_count; i++) { 5609 u16 tnl_type; 5610 u32 ti; 5611 5612 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5613 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5614 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5615 5616 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5617 * one more byte further than normally used for Tenant ID in 5618 * other tunnel types. 5619 */ 5620 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5621 ti = le32_to_cpu(filters[i].element.tenant_id); 5622 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5623 } 5624 } 5625 5626 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5627 5628 return status; 5629 } 5630