1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include "i40e_virtchnl.h" 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 hw->mac.type = I40E_MAC_XL710; 57 break; 58 case I40E_DEV_ID_KX_X722: 59 case I40E_DEV_ID_QSFP_X722: 60 case I40E_DEV_ID_SFP_X722: 61 case I40E_DEV_ID_1G_BASE_T_X722: 62 case I40E_DEV_ID_10G_BASE_T_X722: 63 case I40E_DEV_ID_SFP_I_X722: 64 hw->mac.type = I40E_MAC_X722; 65 break; 66 default: 67 hw->mac.type = I40E_MAC_GENERIC; 68 break; 69 } 70 } else { 71 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 72 } 73 74 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 75 hw->mac.type, status); 76 return status; 77 } 78 79 /** 80 * i40e_aq_str - convert AQ err code to a string 81 * @hw: pointer to the HW structure 82 * @aq_err: the AQ error code to convert 83 **/ 84 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 85 { 86 switch (aq_err) { 87 case I40E_AQ_RC_OK: 88 return "OK"; 89 case I40E_AQ_RC_EPERM: 90 return "I40E_AQ_RC_EPERM"; 91 case I40E_AQ_RC_ENOENT: 92 return "I40E_AQ_RC_ENOENT"; 93 case I40E_AQ_RC_ESRCH: 94 return "I40E_AQ_RC_ESRCH"; 95 case I40E_AQ_RC_EINTR: 96 return "I40E_AQ_RC_EINTR"; 97 case I40E_AQ_RC_EIO: 98 return "I40E_AQ_RC_EIO"; 99 case I40E_AQ_RC_ENXIO: 100 return "I40E_AQ_RC_ENXIO"; 101 case I40E_AQ_RC_E2BIG: 102 return "I40E_AQ_RC_E2BIG"; 103 case I40E_AQ_RC_EAGAIN: 104 return "I40E_AQ_RC_EAGAIN"; 105 case I40E_AQ_RC_ENOMEM: 106 return "I40E_AQ_RC_ENOMEM"; 107 case I40E_AQ_RC_EACCES: 108 return "I40E_AQ_RC_EACCES"; 109 case I40E_AQ_RC_EFAULT: 110 return "I40E_AQ_RC_EFAULT"; 111 case I40E_AQ_RC_EBUSY: 112 return "I40E_AQ_RC_EBUSY"; 113 case I40E_AQ_RC_EEXIST: 114 return "I40E_AQ_RC_EEXIST"; 115 case I40E_AQ_RC_EINVAL: 116 return "I40E_AQ_RC_EINVAL"; 117 case I40E_AQ_RC_ENOTTY: 118 return "I40E_AQ_RC_ENOTTY"; 119 case I40E_AQ_RC_ENOSPC: 120 return "I40E_AQ_RC_ENOSPC"; 121 case I40E_AQ_RC_ENOSYS: 122 return "I40E_AQ_RC_ENOSYS"; 123 case I40E_AQ_RC_ERANGE: 124 return "I40E_AQ_RC_ERANGE"; 125 case I40E_AQ_RC_EFLUSHED: 126 return "I40E_AQ_RC_EFLUSHED"; 127 case I40E_AQ_RC_BAD_ADDR: 128 return "I40E_AQ_RC_BAD_ADDR"; 129 case I40E_AQ_RC_EMODE: 130 return "I40E_AQ_RC_EMODE"; 131 case I40E_AQ_RC_EFBIG: 132 return "I40E_AQ_RC_EFBIG"; 133 } 134 135 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 136 return hw->err_str; 137 } 138 139 /** 140 * i40e_stat_str - convert status err code to a string 141 * @hw: pointer to the HW structure 142 * @stat_err: the status error code to convert 143 **/ 144 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 145 { 146 switch (stat_err) { 147 case 0: 148 return "OK"; 149 case I40E_ERR_NVM: 150 return "I40E_ERR_NVM"; 151 case I40E_ERR_NVM_CHECKSUM: 152 return "I40E_ERR_NVM_CHECKSUM"; 153 case I40E_ERR_PHY: 154 return "I40E_ERR_PHY"; 155 case I40E_ERR_CONFIG: 156 return "I40E_ERR_CONFIG"; 157 case I40E_ERR_PARAM: 158 return "I40E_ERR_PARAM"; 159 case I40E_ERR_MAC_TYPE: 160 return "I40E_ERR_MAC_TYPE"; 161 case I40E_ERR_UNKNOWN_PHY: 162 return "I40E_ERR_UNKNOWN_PHY"; 163 case I40E_ERR_LINK_SETUP: 164 return "I40E_ERR_LINK_SETUP"; 165 case I40E_ERR_ADAPTER_STOPPED: 166 return "I40E_ERR_ADAPTER_STOPPED"; 167 case I40E_ERR_INVALID_MAC_ADDR: 168 return "I40E_ERR_INVALID_MAC_ADDR"; 169 case I40E_ERR_DEVICE_NOT_SUPPORTED: 170 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 171 case I40E_ERR_MASTER_REQUESTS_PENDING: 172 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 173 case I40E_ERR_INVALID_LINK_SETTINGS: 174 return "I40E_ERR_INVALID_LINK_SETTINGS"; 175 case I40E_ERR_AUTONEG_NOT_COMPLETE: 176 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 177 case I40E_ERR_RESET_FAILED: 178 return "I40E_ERR_RESET_FAILED"; 179 case I40E_ERR_SWFW_SYNC: 180 return "I40E_ERR_SWFW_SYNC"; 181 case I40E_ERR_NO_AVAILABLE_VSI: 182 return "I40E_ERR_NO_AVAILABLE_VSI"; 183 case I40E_ERR_NO_MEMORY: 184 return "I40E_ERR_NO_MEMORY"; 185 case I40E_ERR_BAD_PTR: 186 return "I40E_ERR_BAD_PTR"; 187 case I40E_ERR_RING_FULL: 188 return "I40E_ERR_RING_FULL"; 189 case I40E_ERR_INVALID_PD_ID: 190 return "I40E_ERR_INVALID_PD_ID"; 191 case I40E_ERR_INVALID_QP_ID: 192 return "I40E_ERR_INVALID_QP_ID"; 193 case I40E_ERR_INVALID_CQ_ID: 194 return "I40E_ERR_INVALID_CQ_ID"; 195 case I40E_ERR_INVALID_CEQ_ID: 196 return "I40E_ERR_INVALID_CEQ_ID"; 197 case I40E_ERR_INVALID_AEQ_ID: 198 return "I40E_ERR_INVALID_AEQ_ID"; 199 case I40E_ERR_INVALID_SIZE: 200 return "I40E_ERR_INVALID_SIZE"; 201 case I40E_ERR_INVALID_ARP_INDEX: 202 return "I40E_ERR_INVALID_ARP_INDEX"; 203 case I40E_ERR_INVALID_FPM_FUNC_ID: 204 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 205 case I40E_ERR_QP_INVALID_MSG_SIZE: 206 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 207 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 208 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 209 case I40E_ERR_INVALID_FRAG_COUNT: 210 return "I40E_ERR_INVALID_FRAG_COUNT"; 211 case I40E_ERR_QUEUE_EMPTY: 212 return "I40E_ERR_QUEUE_EMPTY"; 213 case I40E_ERR_INVALID_ALIGNMENT: 214 return "I40E_ERR_INVALID_ALIGNMENT"; 215 case I40E_ERR_FLUSHED_QUEUE: 216 return "I40E_ERR_FLUSHED_QUEUE"; 217 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 218 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 219 case I40E_ERR_INVALID_IMM_DATA_SIZE: 220 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 221 case I40E_ERR_TIMEOUT: 222 return "I40E_ERR_TIMEOUT"; 223 case I40E_ERR_OPCODE_MISMATCH: 224 return "I40E_ERR_OPCODE_MISMATCH"; 225 case I40E_ERR_CQP_COMPL_ERROR: 226 return "I40E_ERR_CQP_COMPL_ERROR"; 227 case I40E_ERR_INVALID_VF_ID: 228 return "I40E_ERR_INVALID_VF_ID"; 229 case I40E_ERR_INVALID_HMCFN_ID: 230 return "I40E_ERR_INVALID_HMCFN_ID"; 231 case I40E_ERR_BACKING_PAGE_ERROR: 232 return "I40E_ERR_BACKING_PAGE_ERROR"; 233 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 234 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 235 case I40E_ERR_INVALID_PBLE_INDEX: 236 return "I40E_ERR_INVALID_PBLE_INDEX"; 237 case I40E_ERR_INVALID_SD_INDEX: 238 return "I40E_ERR_INVALID_SD_INDEX"; 239 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 240 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 241 case I40E_ERR_INVALID_SD_TYPE: 242 return "I40E_ERR_INVALID_SD_TYPE"; 243 case I40E_ERR_MEMCPY_FAILED: 244 return "I40E_ERR_MEMCPY_FAILED"; 245 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 246 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 247 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 248 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 249 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 250 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 251 case I40E_ERR_SRQ_ENABLED: 252 return "I40E_ERR_SRQ_ENABLED"; 253 case I40E_ERR_ADMIN_QUEUE_ERROR: 254 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 255 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 256 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 257 case I40E_ERR_BUF_TOO_SHORT: 258 return "I40E_ERR_BUF_TOO_SHORT"; 259 case I40E_ERR_ADMIN_QUEUE_FULL: 260 return "I40E_ERR_ADMIN_QUEUE_FULL"; 261 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 262 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 263 case I40E_ERR_BAD_IWARP_CQE: 264 return "I40E_ERR_BAD_IWARP_CQE"; 265 case I40E_ERR_NVM_BLANK_MODE: 266 return "I40E_ERR_NVM_BLANK_MODE"; 267 case I40E_ERR_NOT_IMPLEMENTED: 268 return "I40E_ERR_NOT_IMPLEMENTED"; 269 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 270 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 271 case I40E_ERR_DIAG_TEST_FAILED: 272 return "I40E_ERR_DIAG_TEST_FAILED"; 273 case I40E_ERR_NOT_READY: 274 return "I40E_ERR_NOT_READY"; 275 case I40E_NOT_SUPPORTED: 276 return "I40E_NOT_SUPPORTED"; 277 case I40E_ERR_FIRMWARE_API_VERSION: 278 return "I40E_ERR_FIRMWARE_API_VERSION"; 279 } 280 281 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 282 return hw->err_str; 283 } 284 285 /** 286 * i40e_debug_aq 287 * @hw: debug mask related to admin queue 288 * @mask: debug mask 289 * @desc: pointer to admin queue descriptor 290 * @buffer: pointer to command buffer 291 * @buf_len: max length of buffer 292 * 293 * Dumps debug log about adminq command with descriptor contents. 294 **/ 295 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 296 void *buffer, u16 buf_len) 297 { 298 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 299 u16 len; 300 u8 *buf = (u8 *)buffer; 301 u16 i = 0; 302 303 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 304 return; 305 306 len = le16_to_cpu(aq_desc->datalen); 307 308 i40e_debug(hw, mask, 309 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 310 le16_to_cpu(aq_desc->opcode), 311 le16_to_cpu(aq_desc->flags), 312 le16_to_cpu(aq_desc->datalen), 313 le16_to_cpu(aq_desc->retval)); 314 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 315 le32_to_cpu(aq_desc->cookie_high), 316 le32_to_cpu(aq_desc->cookie_low)); 317 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 318 le32_to_cpu(aq_desc->params.internal.param0), 319 le32_to_cpu(aq_desc->params.internal.param1)); 320 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 321 le32_to_cpu(aq_desc->params.external.addr_high), 322 le32_to_cpu(aq_desc->params.external.addr_low)); 323 324 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 325 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 326 if (buf_len < len) 327 len = buf_len; 328 /* write the full 16-byte chunks */ 329 for (i = 0; i < (len - 16); i += 16) 330 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i); 331 /* write whatever's left over without overrunning the buffer */ 332 if (i < len) 333 i40e_debug(hw, mask, "\t0x%04X %*ph\n", 334 i, len - i, buf + i); 335 } 336 } 337 338 /** 339 * i40e_check_asq_alive 340 * @hw: pointer to the hw struct 341 * 342 * Returns true if Queue is enabled else false. 343 **/ 344 bool i40e_check_asq_alive(struct i40e_hw *hw) 345 { 346 if (hw->aq.asq.len) 347 return !!(rd32(hw, hw->aq.asq.len) & 348 I40E_PF_ATQLEN_ATQENABLE_MASK); 349 else 350 return false; 351 } 352 353 /** 354 * i40e_aq_queue_shutdown 355 * @hw: pointer to the hw struct 356 * @unloading: is the driver unloading itself 357 * 358 * Tell the Firmware that we're shutting down the AdminQ and whether 359 * or not the driver is unloading as well. 360 **/ 361 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 362 bool unloading) 363 { 364 struct i40e_aq_desc desc; 365 struct i40e_aqc_queue_shutdown *cmd = 366 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 367 i40e_status status; 368 369 i40e_fill_default_direct_cmd_desc(&desc, 370 i40e_aqc_opc_queue_shutdown); 371 372 if (unloading) 373 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 374 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 375 376 return status; 377 } 378 379 /** 380 * i40e_aq_get_set_rss_lut 381 * @hw: pointer to the hardware structure 382 * @vsi_id: vsi fw index 383 * @pf_lut: for PF table set true, for VSI table set false 384 * @lut: pointer to the lut buffer provided by the caller 385 * @lut_size: size of the lut buffer 386 * @set: set true to set the table, false to get the table 387 * 388 * Internal function to get or set RSS look up table 389 **/ 390 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 391 u16 vsi_id, bool pf_lut, 392 u8 *lut, u16 lut_size, 393 bool set) 394 { 395 i40e_status status; 396 struct i40e_aq_desc desc; 397 struct i40e_aqc_get_set_rss_lut *cmd_resp = 398 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 399 400 if (set) 401 i40e_fill_default_direct_cmd_desc(&desc, 402 i40e_aqc_opc_set_rss_lut); 403 else 404 i40e_fill_default_direct_cmd_desc(&desc, 405 i40e_aqc_opc_get_rss_lut); 406 407 /* Indirect command */ 408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 409 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 410 411 cmd_resp->vsi_id = 412 cpu_to_le16((u16)((vsi_id << 413 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 414 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 415 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 416 417 if (pf_lut) 418 cmd_resp->flags |= cpu_to_le16((u16) 419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 422 else 423 cmd_resp->flags |= cpu_to_le16((u16) 424 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 425 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 426 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 427 428 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 429 430 return status; 431 } 432 433 /** 434 * i40e_aq_get_rss_lut 435 * @hw: pointer to the hardware structure 436 * @vsi_id: vsi fw index 437 * @pf_lut: for PF table set true, for VSI table set false 438 * @lut: pointer to the lut buffer provided by the caller 439 * @lut_size: size of the lut buffer 440 * 441 * get the RSS lookup table, PF or VSI type 442 **/ 443 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 444 bool pf_lut, u8 *lut, u16 lut_size) 445 { 446 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 447 false); 448 } 449 450 /** 451 * i40e_aq_set_rss_lut 452 * @hw: pointer to the hardware structure 453 * @vsi_id: vsi fw index 454 * @pf_lut: for PF table set true, for VSI table set false 455 * @lut: pointer to the lut buffer provided by the caller 456 * @lut_size: size of the lut buffer 457 * 458 * set the RSS lookup table, PF or VSI type 459 **/ 460 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 461 bool pf_lut, u8 *lut, u16 lut_size) 462 { 463 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 464 } 465 466 /** 467 * i40e_aq_get_set_rss_key 468 * @hw: pointer to the hw struct 469 * @vsi_id: vsi fw index 470 * @key: pointer to key info struct 471 * @set: set true to set the key, false to get the key 472 * 473 * get the RSS key per VSI 474 **/ 475 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 476 u16 vsi_id, 477 struct i40e_aqc_get_set_rss_key_data *key, 478 bool set) 479 { 480 i40e_status status; 481 struct i40e_aq_desc desc; 482 struct i40e_aqc_get_set_rss_key *cmd_resp = 483 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 484 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 485 486 if (set) 487 i40e_fill_default_direct_cmd_desc(&desc, 488 i40e_aqc_opc_set_rss_key); 489 else 490 i40e_fill_default_direct_cmd_desc(&desc, 491 i40e_aqc_opc_get_rss_key); 492 493 /* Indirect command */ 494 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 495 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 496 497 cmd_resp->vsi_id = 498 cpu_to_le16((u16)((vsi_id << 499 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 500 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 501 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 502 503 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 504 505 return status; 506 } 507 508 /** 509 * i40e_aq_get_rss_key 510 * @hw: pointer to the hw struct 511 * @vsi_id: vsi fw index 512 * @key: pointer to key info struct 513 * 514 **/ 515 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 516 u16 vsi_id, 517 struct i40e_aqc_get_set_rss_key_data *key) 518 { 519 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 520 } 521 522 /** 523 * i40e_aq_set_rss_key 524 * @hw: pointer to the hw struct 525 * @vsi_id: vsi fw index 526 * @key: pointer to key info struct 527 * 528 * set the RSS key per VSI 529 **/ 530 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 531 u16 vsi_id, 532 struct i40e_aqc_get_set_rss_key_data *key) 533 { 534 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 535 } 536 537 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 538 * hardware to a bit-field that can be used by SW to more easily determine the 539 * packet type. 540 * 541 * Macros are used to shorten the table lines and make this table human 542 * readable. 543 * 544 * We store the PTYPE in the top byte of the bit field - this is just so that 545 * we can check that the table doesn't have a row missing, as the index into 546 * the table should be the PTYPE. 547 * 548 * Typical work flow: 549 * 550 * IF NOT i40e_ptype_lookup[ptype].known 551 * THEN 552 * Packet is unknown 553 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 554 * Use the rest of the fields to look at the tunnels, inner protocols, etc 555 * ELSE 556 * Use the enum i40e_rx_l2_ptype to decode the packet type 557 * ENDIF 558 */ 559 560 /* macro to make the table lines short */ 561 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 562 { PTYPE, \ 563 1, \ 564 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 565 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 566 I40E_RX_PTYPE_##OUTER_FRAG, \ 567 I40E_RX_PTYPE_TUNNEL_##T, \ 568 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 569 I40E_RX_PTYPE_##TEF, \ 570 I40E_RX_PTYPE_INNER_PROT_##I, \ 571 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 572 573 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 574 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 575 576 /* shorter macros makes the table fit but are terse */ 577 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 578 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 579 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 580 581 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 582 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 583 /* L2 Packet types */ 584 I40E_PTT_UNUSED_ENTRY(0), 585 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 586 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 587 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 588 I40E_PTT_UNUSED_ENTRY(4), 589 I40E_PTT_UNUSED_ENTRY(5), 590 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 591 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 592 I40E_PTT_UNUSED_ENTRY(8), 593 I40E_PTT_UNUSED_ENTRY(9), 594 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 596 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 597 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 598 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 599 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 600 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 601 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 602 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 607 /* Non Tunneled IPv4 */ 608 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 611 I40E_PTT_UNUSED_ENTRY(25), 612 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 613 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 614 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 615 616 /* IPv4 --> IPv4 */ 617 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 618 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 619 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 620 I40E_PTT_UNUSED_ENTRY(32), 621 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 622 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 623 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 624 625 /* IPv4 --> IPv6 */ 626 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 627 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 628 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 629 I40E_PTT_UNUSED_ENTRY(39), 630 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 631 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 632 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 633 634 /* IPv4 --> GRE/NAT */ 635 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 636 637 /* IPv4 --> GRE/NAT --> IPv4 */ 638 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 639 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 640 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 641 I40E_PTT_UNUSED_ENTRY(47), 642 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 643 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 644 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 645 646 /* IPv4 --> GRE/NAT --> IPv6 */ 647 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 648 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 649 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 650 I40E_PTT_UNUSED_ENTRY(54), 651 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 652 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 653 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 654 655 /* IPv4 --> GRE/NAT --> MAC */ 656 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 657 658 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 659 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 660 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 661 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 662 I40E_PTT_UNUSED_ENTRY(62), 663 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 664 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 665 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 666 667 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 668 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 669 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 670 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 671 I40E_PTT_UNUSED_ENTRY(69), 672 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 673 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 674 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 675 676 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 677 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 678 679 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 680 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 681 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 682 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 683 I40E_PTT_UNUSED_ENTRY(77), 684 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 685 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 686 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 687 688 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 689 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 690 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 691 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 692 I40E_PTT_UNUSED_ENTRY(84), 693 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 694 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 695 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 696 697 /* Non Tunneled IPv6 */ 698 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 699 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 700 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 701 I40E_PTT_UNUSED_ENTRY(91), 702 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 703 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 704 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 705 706 /* IPv6 --> IPv4 */ 707 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 708 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 709 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 710 I40E_PTT_UNUSED_ENTRY(98), 711 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 712 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 713 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 714 715 /* IPv6 --> IPv6 */ 716 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 717 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 718 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 719 I40E_PTT_UNUSED_ENTRY(105), 720 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 721 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 722 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 723 724 /* IPv6 --> GRE/NAT */ 725 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 726 727 /* IPv6 --> GRE/NAT -> IPv4 */ 728 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 729 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 730 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 731 I40E_PTT_UNUSED_ENTRY(113), 732 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 733 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 734 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 735 736 /* IPv6 --> GRE/NAT -> IPv6 */ 737 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 738 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 739 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 740 I40E_PTT_UNUSED_ENTRY(120), 741 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 742 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 743 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 744 745 /* IPv6 --> GRE/NAT -> MAC */ 746 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 747 748 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 749 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 750 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 751 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 752 I40E_PTT_UNUSED_ENTRY(128), 753 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 754 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 755 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 756 757 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 758 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 759 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 760 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 761 I40E_PTT_UNUSED_ENTRY(135), 762 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 763 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 764 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 765 766 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 767 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 768 769 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 770 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 771 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 772 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 773 I40E_PTT_UNUSED_ENTRY(143), 774 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 775 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 776 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 777 778 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 779 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 780 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 781 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 782 I40E_PTT_UNUSED_ENTRY(150), 783 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 784 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 785 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 786 787 /* unused entries */ 788 I40E_PTT_UNUSED_ENTRY(154), 789 I40E_PTT_UNUSED_ENTRY(155), 790 I40E_PTT_UNUSED_ENTRY(156), 791 I40E_PTT_UNUSED_ENTRY(157), 792 I40E_PTT_UNUSED_ENTRY(158), 793 I40E_PTT_UNUSED_ENTRY(159), 794 795 I40E_PTT_UNUSED_ENTRY(160), 796 I40E_PTT_UNUSED_ENTRY(161), 797 I40E_PTT_UNUSED_ENTRY(162), 798 I40E_PTT_UNUSED_ENTRY(163), 799 I40E_PTT_UNUSED_ENTRY(164), 800 I40E_PTT_UNUSED_ENTRY(165), 801 I40E_PTT_UNUSED_ENTRY(166), 802 I40E_PTT_UNUSED_ENTRY(167), 803 I40E_PTT_UNUSED_ENTRY(168), 804 I40E_PTT_UNUSED_ENTRY(169), 805 806 I40E_PTT_UNUSED_ENTRY(170), 807 I40E_PTT_UNUSED_ENTRY(171), 808 I40E_PTT_UNUSED_ENTRY(172), 809 I40E_PTT_UNUSED_ENTRY(173), 810 I40E_PTT_UNUSED_ENTRY(174), 811 I40E_PTT_UNUSED_ENTRY(175), 812 I40E_PTT_UNUSED_ENTRY(176), 813 I40E_PTT_UNUSED_ENTRY(177), 814 I40E_PTT_UNUSED_ENTRY(178), 815 I40E_PTT_UNUSED_ENTRY(179), 816 817 I40E_PTT_UNUSED_ENTRY(180), 818 I40E_PTT_UNUSED_ENTRY(181), 819 I40E_PTT_UNUSED_ENTRY(182), 820 I40E_PTT_UNUSED_ENTRY(183), 821 I40E_PTT_UNUSED_ENTRY(184), 822 I40E_PTT_UNUSED_ENTRY(185), 823 I40E_PTT_UNUSED_ENTRY(186), 824 I40E_PTT_UNUSED_ENTRY(187), 825 I40E_PTT_UNUSED_ENTRY(188), 826 I40E_PTT_UNUSED_ENTRY(189), 827 828 I40E_PTT_UNUSED_ENTRY(190), 829 I40E_PTT_UNUSED_ENTRY(191), 830 I40E_PTT_UNUSED_ENTRY(192), 831 I40E_PTT_UNUSED_ENTRY(193), 832 I40E_PTT_UNUSED_ENTRY(194), 833 I40E_PTT_UNUSED_ENTRY(195), 834 I40E_PTT_UNUSED_ENTRY(196), 835 I40E_PTT_UNUSED_ENTRY(197), 836 I40E_PTT_UNUSED_ENTRY(198), 837 I40E_PTT_UNUSED_ENTRY(199), 838 839 I40E_PTT_UNUSED_ENTRY(200), 840 I40E_PTT_UNUSED_ENTRY(201), 841 I40E_PTT_UNUSED_ENTRY(202), 842 I40E_PTT_UNUSED_ENTRY(203), 843 I40E_PTT_UNUSED_ENTRY(204), 844 I40E_PTT_UNUSED_ENTRY(205), 845 I40E_PTT_UNUSED_ENTRY(206), 846 I40E_PTT_UNUSED_ENTRY(207), 847 I40E_PTT_UNUSED_ENTRY(208), 848 I40E_PTT_UNUSED_ENTRY(209), 849 850 I40E_PTT_UNUSED_ENTRY(210), 851 I40E_PTT_UNUSED_ENTRY(211), 852 I40E_PTT_UNUSED_ENTRY(212), 853 I40E_PTT_UNUSED_ENTRY(213), 854 I40E_PTT_UNUSED_ENTRY(214), 855 I40E_PTT_UNUSED_ENTRY(215), 856 I40E_PTT_UNUSED_ENTRY(216), 857 I40E_PTT_UNUSED_ENTRY(217), 858 I40E_PTT_UNUSED_ENTRY(218), 859 I40E_PTT_UNUSED_ENTRY(219), 860 861 I40E_PTT_UNUSED_ENTRY(220), 862 I40E_PTT_UNUSED_ENTRY(221), 863 I40E_PTT_UNUSED_ENTRY(222), 864 I40E_PTT_UNUSED_ENTRY(223), 865 I40E_PTT_UNUSED_ENTRY(224), 866 I40E_PTT_UNUSED_ENTRY(225), 867 I40E_PTT_UNUSED_ENTRY(226), 868 I40E_PTT_UNUSED_ENTRY(227), 869 I40E_PTT_UNUSED_ENTRY(228), 870 I40E_PTT_UNUSED_ENTRY(229), 871 872 I40E_PTT_UNUSED_ENTRY(230), 873 I40E_PTT_UNUSED_ENTRY(231), 874 I40E_PTT_UNUSED_ENTRY(232), 875 I40E_PTT_UNUSED_ENTRY(233), 876 I40E_PTT_UNUSED_ENTRY(234), 877 I40E_PTT_UNUSED_ENTRY(235), 878 I40E_PTT_UNUSED_ENTRY(236), 879 I40E_PTT_UNUSED_ENTRY(237), 880 I40E_PTT_UNUSED_ENTRY(238), 881 I40E_PTT_UNUSED_ENTRY(239), 882 883 I40E_PTT_UNUSED_ENTRY(240), 884 I40E_PTT_UNUSED_ENTRY(241), 885 I40E_PTT_UNUSED_ENTRY(242), 886 I40E_PTT_UNUSED_ENTRY(243), 887 I40E_PTT_UNUSED_ENTRY(244), 888 I40E_PTT_UNUSED_ENTRY(245), 889 I40E_PTT_UNUSED_ENTRY(246), 890 I40E_PTT_UNUSED_ENTRY(247), 891 I40E_PTT_UNUSED_ENTRY(248), 892 I40E_PTT_UNUSED_ENTRY(249), 893 894 I40E_PTT_UNUSED_ENTRY(250), 895 I40E_PTT_UNUSED_ENTRY(251), 896 I40E_PTT_UNUSED_ENTRY(252), 897 I40E_PTT_UNUSED_ENTRY(253), 898 I40E_PTT_UNUSED_ENTRY(254), 899 I40E_PTT_UNUSED_ENTRY(255) 900 }; 901 902 /** 903 * i40e_init_shared_code - Initialize the shared code 904 * @hw: pointer to hardware structure 905 * 906 * This assigns the MAC type and PHY code and inits the NVM. 907 * Does not touch the hardware. This function must be called prior to any 908 * other function in the shared code. The i40e_hw structure should be 909 * memset to 0 prior to calling this function. The following fields in 910 * hw structure should be filled in prior to calling this function: 911 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 912 * subsystem_vendor_id, and revision_id 913 **/ 914 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 915 { 916 i40e_status status = 0; 917 u32 port, ari, func_rid; 918 919 i40e_set_mac_type(hw); 920 921 switch (hw->mac.type) { 922 case I40E_MAC_XL710: 923 case I40E_MAC_X722: 924 break; 925 default: 926 return I40E_ERR_DEVICE_NOT_SUPPORTED; 927 } 928 929 hw->phy.get_link_info = true; 930 931 /* Determine port number and PF number*/ 932 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 933 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 934 hw->port = (u8)port; 935 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 936 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 937 func_rid = rd32(hw, I40E_PF_FUNC_RID); 938 if (ari) 939 hw->pf_id = (u8)(func_rid & 0xff); 940 else 941 hw->pf_id = (u8)(func_rid & 0x7); 942 943 if (hw->mac.type == I40E_MAC_X722) 944 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 945 946 status = i40e_init_nvm(hw); 947 return status; 948 } 949 950 /** 951 * i40e_aq_mac_address_read - Retrieve the MAC addresses 952 * @hw: pointer to the hw struct 953 * @flags: a return indicator of what addresses were added to the addr store 954 * @addrs: the requestor's mac addr store 955 * @cmd_details: pointer to command details structure or NULL 956 **/ 957 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 958 u16 *flags, 959 struct i40e_aqc_mac_address_read_data *addrs, 960 struct i40e_asq_cmd_details *cmd_details) 961 { 962 struct i40e_aq_desc desc; 963 struct i40e_aqc_mac_address_read *cmd_data = 964 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 965 i40e_status status; 966 967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 968 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 969 970 status = i40e_asq_send_command(hw, &desc, addrs, 971 sizeof(*addrs), cmd_details); 972 *flags = le16_to_cpu(cmd_data->command_flags); 973 974 return status; 975 } 976 977 /** 978 * i40e_aq_mac_address_write - Change the MAC addresses 979 * @hw: pointer to the hw struct 980 * @flags: indicates which MAC to be written 981 * @mac_addr: address to write 982 * @cmd_details: pointer to command details structure or NULL 983 **/ 984 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 985 u16 flags, u8 *mac_addr, 986 struct i40e_asq_cmd_details *cmd_details) 987 { 988 struct i40e_aq_desc desc; 989 struct i40e_aqc_mac_address_write *cmd_data = 990 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 991 i40e_status status; 992 993 i40e_fill_default_direct_cmd_desc(&desc, 994 i40e_aqc_opc_mac_address_write); 995 cmd_data->command_flags = cpu_to_le16(flags); 996 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 997 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 998 ((u32)mac_addr[3] << 16) | 999 ((u32)mac_addr[4] << 8) | 1000 mac_addr[5]); 1001 1002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1003 1004 return status; 1005 } 1006 1007 /** 1008 * i40e_get_mac_addr - get MAC address 1009 * @hw: pointer to the HW structure 1010 * @mac_addr: pointer to MAC address 1011 * 1012 * Reads the adapter's MAC address from register 1013 **/ 1014 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1015 { 1016 struct i40e_aqc_mac_address_read_data addrs; 1017 i40e_status status; 1018 u16 flags = 0; 1019 1020 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1021 1022 if (flags & I40E_AQC_LAN_ADDR_VALID) 1023 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1024 1025 return status; 1026 } 1027 1028 /** 1029 * i40e_get_port_mac_addr - get Port MAC address 1030 * @hw: pointer to the HW structure 1031 * @mac_addr: pointer to Port MAC address 1032 * 1033 * Reads the adapter's Port MAC address 1034 **/ 1035 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1036 { 1037 struct i40e_aqc_mac_address_read_data addrs; 1038 i40e_status status; 1039 u16 flags = 0; 1040 1041 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1042 if (status) 1043 return status; 1044 1045 if (flags & I40E_AQC_PORT_ADDR_VALID) 1046 ether_addr_copy(mac_addr, addrs.port_mac); 1047 else 1048 status = I40E_ERR_INVALID_MAC_ADDR; 1049 1050 return status; 1051 } 1052 1053 /** 1054 * i40e_pre_tx_queue_cfg - pre tx queue configure 1055 * @hw: pointer to the HW structure 1056 * @queue: target PF queue index 1057 * @enable: state change request 1058 * 1059 * Handles hw requirement to indicate intention to enable 1060 * or disable target queue. 1061 **/ 1062 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1063 { 1064 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1065 u32 reg_block = 0; 1066 u32 reg_val; 1067 1068 if (abs_queue_idx >= 128) { 1069 reg_block = abs_queue_idx / 128; 1070 abs_queue_idx %= 128; 1071 } 1072 1073 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1074 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1075 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1076 1077 if (enable) 1078 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1079 else 1080 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1081 1082 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1083 } 1084 #ifdef I40E_FCOE 1085 1086 /** 1087 * i40e_get_san_mac_addr - get SAN MAC address 1088 * @hw: pointer to the HW structure 1089 * @mac_addr: pointer to SAN MAC address 1090 * 1091 * Reads the adapter's SAN MAC address from NVM 1092 **/ 1093 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1094 { 1095 struct i40e_aqc_mac_address_read_data addrs; 1096 i40e_status status; 1097 u16 flags = 0; 1098 1099 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1100 if (status) 1101 return status; 1102 1103 if (flags & I40E_AQC_SAN_ADDR_VALID) 1104 ether_addr_copy(mac_addr, addrs.pf_san_mac); 1105 else 1106 status = I40E_ERR_INVALID_MAC_ADDR; 1107 1108 return status; 1109 } 1110 #endif 1111 1112 /** 1113 * i40e_read_pba_string - Reads part number string from EEPROM 1114 * @hw: pointer to hardware structure 1115 * @pba_num: stores the part number string from the EEPROM 1116 * @pba_num_size: part number string buffer length 1117 * 1118 * Reads the part number string from the EEPROM. 1119 **/ 1120 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1121 u32 pba_num_size) 1122 { 1123 i40e_status status = 0; 1124 u16 pba_word = 0; 1125 u16 pba_size = 0; 1126 u16 pba_ptr = 0; 1127 u16 i = 0; 1128 1129 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1130 if (status || (pba_word != 0xFAFA)) { 1131 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1132 return status; 1133 } 1134 1135 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1136 if (status) { 1137 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1138 return status; 1139 } 1140 1141 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1142 if (status) { 1143 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1144 return status; 1145 } 1146 1147 /* Subtract one to get PBA word count (PBA Size word is included in 1148 * total size) 1149 */ 1150 pba_size--; 1151 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1152 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1153 return I40E_ERR_PARAM; 1154 } 1155 1156 for (i = 0; i < pba_size; i++) { 1157 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1158 if (status) { 1159 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1160 return status; 1161 } 1162 1163 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1164 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1165 } 1166 pba_num[(pba_size * 2)] = '\0'; 1167 1168 return status; 1169 } 1170 1171 /** 1172 * i40e_get_media_type - Gets media type 1173 * @hw: pointer to the hardware structure 1174 **/ 1175 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1176 { 1177 enum i40e_media_type media; 1178 1179 switch (hw->phy.link_info.phy_type) { 1180 case I40E_PHY_TYPE_10GBASE_SR: 1181 case I40E_PHY_TYPE_10GBASE_LR: 1182 case I40E_PHY_TYPE_1000BASE_SX: 1183 case I40E_PHY_TYPE_1000BASE_LX: 1184 case I40E_PHY_TYPE_40GBASE_SR4: 1185 case I40E_PHY_TYPE_40GBASE_LR4: 1186 media = I40E_MEDIA_TYPE_FIBER; 1187 break; 1188 case I40E_PHY_TYPE_100BASE_TX: 1189 case I40E_PHY_TYPE_1000BASE_T: 1190 case I40E_PHY_TYPE_10GBASE_T: 1191 media = I40E_MEDIA_TYPE_BASET; 1192 break; 1193 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1194 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1195 case I40E_PHY_TYPE_10GBASE_CR1: 1196 case I40E_PHY_TYPE_40GBASE_CR4: 1197 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1198 case I40E_PHY_TYPE_40GBASE_AOC: 1199 case I40E_PHY_TYPE_10GBASE_AOC: 1200 media = I40E_MEDIA_TYPE_DA; 1201 break; 1202 case I40E_PHY_TYPE_1000BASE_KX: 1203 case I40E_PHY_TYPE_10GBASE_KX4: 1204 case I40E_PHY_TYPE_10GBASE_KR: 1205 case I40E_PHY_TYPE_40GBASE_KR4: 1206 case I40E_PHY_TYPE_20GBASE_KR2: 1207 media = I40E_MEDIA_TYPE_BACKPLANE; 1208 break; 1209 case I40E_PHY_TYPE_SGMII: 1210 case I40E_PHY_TYPE_XAUI: 1211 case I40E_PHY_TYPE_XFI: 1212 case I40E_PHY_TYPE_XLAUI: 1213 case I40E_PHY_TYPE_XLPPI: 1214 default: 1215 media = I40E_MEDIA_TYPE_UNKNOWN; 1216 break; 1217 } 1218 1219 return media; 1220 } 1221 1222 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1223 #define I40E_PF_RESET_WAIT_COUNT 200 1224 /** 1225 * i40e_pf_reset - Reset the PF 1226 * @hw: pointer to the hardware structure 1227 * 1228 * Assuming someone else has triggered a global reset, 1229 * assure the global reset is complete and then reset the PF 1230 **/ 1231 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1232 { 1233 u32 cnt = 0; 1234 u32 cnt1 = 0; 1235 u32 reg = 0; 1236 u32 grst_del; 1237 1238 /* Poll for Global Reset steady state in case of recent GRST. 1239 * The grst delay value is in 100ms units, and we'll wait a 1240 * couple counts longer to be sure we don't just miss the end. 1241 */ 1242 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1243 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1244 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1245 1246 /* It can take upto 15 secs for GRST steady state. 1247 * Bump it to 16 secs max to be safe. 1248 */ 1249 grst_del = grst_del * 20; 1250 1251 for (cnt = 0; cnt < grst_del; cnt++) { 1252 reg = rd32(hw, I40E_GLGEN_RSTAT); 1253 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1254 break; 1255 msleep(100); 1256 } 1257 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1258 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1259 return I40E_ERR_RESET_FAILED; 1260 } 1261 1262 /* Now Wait for the FW to be ready */ 1263 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1264 reg = rd32(hw, I40E_GLNVM_ULD); 1265 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1267 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1268 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1269 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1270 break; 1271 } 1272 usleep_range(10000, 20000); 1273 } 1274 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1275 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1276 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1277 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1278 return I40E_ERR_RESET_FAILED; 1279 } 1280 1281 /* If there was a Global Reset in progress when we got here, 1282 * we don't need to do the PF Reset 1283 */ 1284 if (!cnt) { 1285 if (hw->revision_id == 0) 1286 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1287 else 1288 cnt = I40E_PF_RESET_WAIT_COUNT; 1289 reg = rd32(hw, I40E_PFGEN_CTRL); 1290 wr32(hw, I40E_PFGEN_CTRL, 1291 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1292 for (; cnt; cnt--) { 1293 reg = rd32(hw, I40E_PFGEN_CTRL); 1294 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1295 break; 1296 usleep_range(1000, 2000); 1297 } 1298 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1299 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1300 return I40E_ERR_RESET_FAILED; 1301 } 1302 } 1303 1304 i40e_clear_pxe_mode(hw); 1305 1306 return 0; 1307 } 1308 1309 /** 1310 * i40e_clear_hw - clear out any left over hw state 1311 * @hw: pointer to the hw struct 1312 * 1313 * Clear queues and interrupts, typically called at init time, 1314 * but after the capabilities have been found so we know how many 1315 * queues and msix vectors have been allocated. 1316 **/ 1317 void i40e_clear_hw(struct i40e_hw *hw) 1318 { 1319 u32 num_queues, base_queue; 1320 u32 num_pf_int; 1321 u32 num_vf_int; 1322 u32 num_vfs; 1323 u32 i, j; 1324 u32 val; 1325 u32 eol = 0x7ff; 1326 1327 /* get number of interrupts, queues, and VFs */ 1328 val = rd32(hw, I40E_GLPCI_CNF2); 1329 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1330 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1331 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1332 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1333 1334 val = rd32(hw, I40E_PFLAN_QALLOC); 1335 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1336 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1337 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1338 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1339 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1340 num_queues = (j - base_queue) + 1; 1341 else 1342 num_queues = 0; 1343 1344 val = rd32(hw, I40E_PF_VT_PFALLOC); 1345 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1346 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1347 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1348 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1349 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1350 num_vfs = (j - i) + 1; 1351 else 1352 num_vfs = 0; 1353 1354 /* stop all the interrupts */ 1355 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1356 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1357 for (i = 0; i < num_pf_int - 2; i++) 1358 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1359 1360 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1361 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1362 wr32(hw, I40E_PFINT_LNKLST0, val); 1363 for (i = 0; i < num_pf_int - 2; i++) 1364 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1365 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1366 for (i = 0; i < num_vfs; i++) 1367 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1368 for (i = 0; i < num_vf_int - 2; i++) 1369 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1370 1371 /* warn the HW of the coming Tx disables */ 1372 for (i = 0; i < num_queues; i++) { 1373 u32 abs_queue_idx = base_queue + i; 1374 u32 reg_block = 0; 1375 1376 if (abs_queue_idx >= 128) { 1377 reg_block = abs_queue_idx / 128; 1378 abs_queue_idx %= 128; 1379 } 1380 1381 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1382 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1383 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1384 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1385 1386 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1387 } 1388 udelay(400); 1389 1390 /* stop all the queues */ 1391 for (i = 0; i < num_queues; i++) { 1392 wr32(hw, I40E_QINT_TQCTL(i), 0); 1393 wr32(hw, I40E_QTX_ENA(i), 0); 1394 wr32(hw, I40E_QINT_RQCTL(i), 0); 1395 wr32(hw, I40E_QRX_ENA(i), 0); 1396 } 1397 1398 /* short wait for all queue disables to settle */ 1399 udelay(50); 1400 } 1401 1402 /** 1403 * i40e_clear_pxe_mode - clear pxe operations mode 1404 * @hw: pointer to the hw struct 1405 * 1406 * Make sure all PXE mode settings are cleared, including things 1407 * like descriptor fetch/write-back mode. 1408 **/ 1409 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1410 { 1411 u32 reg; 1412 1413 if (i40e_check_asq_alive(hw)) 1414 i40e_aq_clear_pxe_mode(hw, NULL); 1415 1416 /* Clear single descriptor fetch/write-back mode */ 1417 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1418 1419 if (hw->revision_id == 0) { 1420 /* As a work around clear PXE_MODE instead of setting it */ 1421 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1422 } else { 1423 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1424 } 1425 } 1426 1427 /** 1428 * i40e_led_is_mine - helper to find matching led 1429 * @hw: pointer to the hw struct 1430 * @idx: index into GPIO registers 1431 * 1432 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1433 */ 1434 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1435 { 1436 u32 gpio_val = 0; 1437 u32 port; 1438 1439 if (!hw->func_caps.led[idx]) 1440 return 0; 1441 1442 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1443 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1444 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1445 1446 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1447 * if it is not our port then ignore 1448 */ 1449 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1450 (port != hw->port)) 1451 return 0; 1452 1453 return gpio_val; 1454 } 1455 1456 #define I40E_COMBINED_ACTIVITY 0xA 1457 #define I40E_FILTER_ACTIVITY 0xE 1458 #define I40E_LINK_ACTIVITY 0xC 1459 #define I40E_MAC_ACTIVITY 0xD 1460 #define I40E_LED0 22 1461 1462 /** 1463 * i40e_led_get - return current on/off mode 1464 * @hw: pointer to the hw struct 1465 * 1466 * The value returned is the 'mode' field as defined in the 1467 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1468 * values are variations of possible behaviors relating to 1469 * blink, link, and wire. 1470 **/ 1471 u32 i40e_led_get(struct i40e_hw *hw) 1472 { 1473 u32 current_mode = 0; 1474 u32 mode = 0; 1475 int i; 1476 1477 /* as per the documentation GPIO 22-29 are the LED 1478 * GPIO pins named LED0..LED7 1479 */ 1480 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1481 u32 gpio_val = i40e_led_is_mine(hw, i); 1482 1483 if (!gpio_val) 1484 continue; 1485 1486 /* ignore gpio LED src mode entries related to the activity 1487 * LEDs 1488 */ 1489 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1490 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1491 switch (current_mode) { 1492 case I40E_COMBINED_ACTIVITY: 1493 case I40E_FILTER_ACTIVITY: 1494 case I40E_MAC_ACTIVITY: 1495 continue; 1496 default: 1497 break; 1498 } 1499 1500 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1501 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1502 break; 1503 } 1504 1505 return mode; 1506 } 1507 1508 /** 1509 * i40e_led_set - set new on/off mode 1510 * @hw: pointer to the hw struct 1511 * @mode: 0=off, 0xf=on (else see manual for mode details) 1512 * @blink: true if the LED should blink when on, false if steady 1513 * 1514 * if this function is used to turn on the blink it should 1515 * be used to disable the blink when restoring the original state. 1516 **/ 1517 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1518 { 1519 u32 current_mode = 0; 1520 int i; 1521 1522 if (mode & 0xfffffff0) 1523 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1524 1525 /* as per the documentation GPIO 22-29 are the LED 1526 * GPIO pins named LED0..LED7 1527 */ 1528 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1529 u32 gpio_val = i40e_led_is_mine(hw, i); 1530 1531 if (!gpio_val) 1532 continue; 1533 1534 /* ignore gpio LED src mode entries related to the activity 1535 * LEDs 1536 */ 1537 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1538 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1539 switch (current_mode) { 1540 case I40E_COMBINED_ACTIVITY: 1541 case I40E_FILTER_ACTIVITY: 1542 case I40E_MAC_ACTIVITY: 1543 continue; 1544 default: 1545 break; 1546 } 1547 1548 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1549 /* this & is a bit of paranoia, but serves as a range check */ 1550 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1551 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1552 1553 if (mode == I40E_LINK_ACTIVITY) 1554 blink = false; 1555 1556 if (blink) 1557 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1558 else 1559 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1560 1561 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1562 break; 1563 } 1564 } 1565 1566 /* Admin command wrappers */ 1567 1568 /** 1569 * i40e_aq_get_phy_capabilities 1570 * @hw: pointer to the hw struct 1571 * @abilities: structure for PHY capabilities to be filled 1572 * @qualified_modules: report Qualified Modules 1573 * @report_init: report init capabilities (active are default) 1574 * @cmd_details: pointer to command details structure or NULL 1575 * 1576 * Returns the various PHY abilities supported on the Port. 1577 **/ 1578 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1579 bool qualified_modules, bool report_init, 1580 struct i40e_aq_get_phy_abilities_resp *abilities, 1581 struct i40e_asq_cmd_details *cmd_details) 1582 { 1583 struct i40e_aq_desc desc; 1584 i40e_status status; 1585 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1586 1587 if (!abilities) 1588 return I40E_ERR_PARAM; 1589 1590 i40e_fill_default_direct_cmd_desc(&desc, 1591 i40e_aqc_opc_get_phy_abilities); 1592 1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1594 if (abilities_size > I40E_AQ_LARGE_BUF) 1595 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1596 1597 if (qualified_modules) 1598 desc.params.external.param0 |= 1599 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1600 1601 if (report_init) 1602 desc.params.external.param0 |= 1603 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1604 1605 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1606 cmd_details); 1607 1608 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1609 status = I40E_ERR_UNKNOWN_PHY; 1610 1611 if (report_init) 1612 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1613 1614 return status; 1615 } 1616 1617 /** 1618 * i40e_aq_set_phy_config 1619 * @hw: pointer to the hw struct 1620 * @config: structure with PHY configuration to be set 1621 * @cmd_details: pointer to command details structure or NULL 1622 * 1623 * Set the various PHY configuration parameters 1624 * supported on the Port.One or more of the Set PHY config parameters may be 1625 * ignored in an MFP mode as the PF may not have the privilege to set some 1626 * of the PHY Config parameters. This status will be indicated by the 1627 * command response. 1628 **/ 1629 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1630 struct i40e_aq_set_phy_config *config, 1631 struct i40e_asq_cmd_details *cmd_details) 1632 { 1633 struct i40e_aq_desc desc; 1634 struct i40e_aq_set_phy_config *cmd = 1635 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1636 enum i40e_status_code status; 1637 1638 if (!config) 1639 return I40E_ERR_PARAM; 1640 1641 i40e_fill_default_direct_cmd_desc(&desc, 1642 i40e_aqc_opc_set_phy_config); 1643 1644 *cmd = *config; 1645 1646 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1647 1648 return status; 1649 } 1650 1651 /** 1652 * i40e_set_fc 1653 * @hw: pointer to the hw struct 1654 * 1655 * Set the requested flow control mode using set_phy_config. 1656 **/ 1657 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1658 bool atomic_restart) 1659 { 1660 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1661 struct i40e_aq_get_phy_abilities_resp abilities; 1662 struct i40e_aq_set_phy_config config; 1663 enum i40e_status_code status; 1664 u8 pause_mask = 0x0; 1665 1666 *aq_failures = 0x0; 1667 1668 switch (fc_mode) { 1669 case I40E_FC_FULL: 1670 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1672 break; 1673 case I40E_FC_RX_PAUSE: 1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1675 break; 1676 case I40E_FC_TX_PAUSE: 1677 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 /* Get the current phy config */ 1684 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1685 NULL); 1686 if (status) { 1687 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1688 return status; 1689 } 1690 1691 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1692 /* clear the old pause settings */ 1693 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1694 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1695 /* set the new abilities */ 1696 config.abilities |= pause_mask; 1697 /* If the abilities have changed, then set the new config */ 1698 if (config.abilities != abilities.abilities) { 1699 /* Auto restart link so settings take effect */ 1700 if (atomic_restart) 1701 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1702 /* Copy over all the old settings */ 1703 config.phy_type = abilities.phy_type; 1704 config.link_speed = abilities.link_speed; 1705 config.eee_capability = abilities.eee_capability; 1706 config.eeer = abilities.eeer_val; 1707 config.low_power_ctrl = abilities.d3_lpan; 1708 status = i40e_aq_set_phy_config(hw, &config, NULL); 1709 1710 if (status) 1711 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1712 } 1713 /* Update the link info */ 1714 status = i40e_update_link_info(hw); 1715 if (status) { 1716 /* Wait a little bit (on 40G cards it sometimes takes a really 1717 * long time for link to come back from the atomic reset) 1718 * and try once more 1719 */ 1720 msleep(1000); 1721 status = i40e_update_link_info(hw); 1722 } 1723 if (status) 1724 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1725 1726 return status; 1727 } 1728 1729 /** 1730 * i40e_aq_clear_pxe_mode 1731 * @hw: pointer to the hw struct 1732 * @cmd_details: pointer to command details structure or NULL 1733 * 1734 * Tell the firmware that the driver is taking over from PXE 1735 **/ 1736 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1737 struct i40e_asq_cmd_details *cmd_details) 1738 { 1739 i40e_status status; 1740 struct i40e_aq_desc desc; 1741 struct i40e_aqc_clear_pxe *cmd = 1742 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1743 1744 i40e_fill_default_direct_cmd_desc(&desc, 1745 i40e_aqc_opc_clear_pxe_mode); 1746 1747 cmd->rx_cnt = 0x2; 1748 1749 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1750 1751 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1752 1753 return status; 1754 } 1755 1756 /** 1757 * i40e_aq_set_link_restart_an 1758 * @hw: pointer to the hw struct 1759 * @enable_link: if true: enable link, if false: disable link 1760 * @cmd_details: pointer to command details structure or NULL 1761 * 1762 * Sets up the link and restarts the Auto-Negotiation over the link. 1763 **/ 1764 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1765 bool enable_link, 1766 struct i40e_asq_cmd_details *cmd_details) 1767 { 1768 struct i40e_aq_desc desc; 1769 struct i40e_aqc_set_link_restart_an *cmd = 1770 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1771 i40e_status status; 1772 1773 i40e_fill_default_direct_cmd_desc(&desc, 1774 i40e_aqc_opc_set_link_restart_an); 1775 1776 cmd->command = I40E_AQ_PHY_RESTART_AN; 1777 if (enable_link) 1778 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1779 else 1780 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1781 1782 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1783 1784 return status; 1785 } 1786 1787 /** 1788 * i40e_aq_get_link_info 1789 * @hw: pointer to the hw struct 1790 * @enable_lse: enable/disable LinkStatusEvent reporting 1791 * @link: pointer to link status structure - optional 1792 * @cmd_details: pointer to command details structure or NULL 1793 * 1794 * Returns the link status of the adapter. 1795 **/ 1796 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1797 bool enable_lse, struct i40e_link_status *link, 1798 struct i40e_asq_cmd_details *cmd_details) 1799 { 1800 struct i40e_aq_desc desc; 1801 struct i40e_aqc_get_link_status *resp = 1802 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1803 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1804 i40e_status status; 1805 bool tx_pause, rx_pause; 1806 u16 command_flags; 1807 1808 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1809 1810 if (enable_lse) 1811 command_flags = I40E_AQ_LSE_ENABLE; 1812 else 1813 command_flags = I40E_AQ_LSE_DISABLE; 1814 resp->command_flags = cpu_to_le16(command_flags); 1815 1816 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1817 1818 if (status) 1819 goto aq_get_link_info_exit; 1820 1821 /* save off old link status information */ 1822 hw->phy.link_info_old = *hw_link_info; 1823 1824 /* update link status */ 1825 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1826 hw->phy.media_type = i40e_get_media_type(hw); 1827 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1828 hw_link_info->link_info = resp->link_info; 1829 hw_link_info->an_info = resp->an_info; 1830 hw_link_info->ext_info = resp->ext_info; 1831 hw_link_info->loopback = resp->loopback; 1832 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1833 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1834 1835 /* update fc info */ 1836 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1837 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1838 if (tx_pause & rx_pause) 1839 hw->fc.current_mode = I40E_FC_FULL; 1840 else if (tx_pause) 1841 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1842 else if (rx_pause) 1843 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1844 else 1845 hw->fc.current_mode = I40E_FC_NONE; 1846 1847 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1848 hw_link_info->crc_enable = true; 1849 else 1850 hw_link_info->crc_enable = false; 1851 1852 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1853 hw_link_info->lse_enable = true; 1854 else 1855 hw_link_info->lse_enable = false; 1856 1857 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1858 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1859 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1860 1861 /* save link status information */ 1862 if (link) 1863 *link = *hw_link_info; 1864 1865 /* flag cleared so helper functions don't call AQ again */ 1866 hw->phy.get_link_info = false; 1867 1868 aq_get_link_info_exit: 1869 return status; 1870 } 1871 1872 /** 1873 * i40e_aq_set_phy_int_mask 1874 * @hw: pointer to the hw struct 1875 * @mask: interrupt mask to be set 1876 * @cmd_details: pointer to command details structure or NULL 1877 * 1878 * Set link interrupt mask. 1879 **/ 1880 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1881 u16 mask, 1882 struct i40e_asq_cmd_details *cmd_details) 1883 { 1884 struct i40e_aq_desc desc; 1885 struct i40e_aqc_set_phy_int_mask *cmd = 1886 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1887 i40e_status status; 1888 1889 i40e_fill_default_direct_cmd_desc(&desc, 1890 i40e_aqc_opc_set_phy_int_mask); 1891 1892 cmd->event_mask = cpu_to_le16(mask); 1893 1894 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1895 1896 return status; 1897 } 1898 1899 /** 1900 * i40e_aq_set_phy_debug 1901 * @hw: pointer to the hw struct 1902 * @cmd_flags: debug command flags 1903 * @cmd_details: pointer to command details structure or NULL 1904 * 1905 * Reset the external PHY. 1906 **/ 1907 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1908 struct i40e_asq_cmd_details *cmd_details) 1909 { 1910 struct i40e_aq_desc desc; 1911 struct i40e_aqc_set_phy_debug *cmd = 1912 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1913 i40e_status status; 1914 1915 i40e_fill_default_direct_cmd_desc(&desc, 1916 i40e_aqc_opc_set_phy_debug); 1917 1918 cmd->command_flags = cmd_flags; 1919 1920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1921 1922 return status; 1923 } 1924 1925 /** 1926 * i40e_aq_add_vsi 1927 * @hw: pointer to the hw struct 1928 * @vsi_ctx: pointer to a vsi context struct 1929 * @cmd_details: pointer to command details structure or NULL 1930 * 1931 * Add a VSI context to the hardware. 1932 **/ 1933 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1934 struct i40e_vsi_context *vsi_ctx, 1935 struct i40e_asq_cmd_details *cmd_details) 1936 { 1937 struct i40e_aq_desc desc; 1938 struct i40e_aqc_add_get_update_vsi *cmd = 1939 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1940 struct i40e_aqc_add_get_update_vsi_completion *resp = 1941 (struct i40e_aqc_add_get_update_vsi_completion *) 1942 &desc.params.raw; 1943 i40e_status status; 1944 1945 i40e_fill_default_direct_cmd_desc(&desc, 1946 i40e_aqc_opc_add_vsi); 1947 1948 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1949 cmd->connection_type = vsi_ctx->connection_type; 1950 cmd->vf_id = vsi_ctx->vf_num; 1951 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1952 1953 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1954 1955 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1956 sizeof(vsi_ctx->info), cmd_details); 1957 1958 if (status) 1959 goto aq_add_vsi_exit; 1960 1961 vsi_ctx->seid = le16_to_cpu(resp->seid); 1962 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1963 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1964 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1965 1966 aq_add_vsi_exit: 1967 return status; 1968 } 1969 1970 /** 1971 * i40e_aq_set_default_vsi 1972 * @hw: pointer to the hw struct 1973 * @seid: vsi number 1974 * @cmd_details: pointer to command details structure or NULL 1975 **/ 1976 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 1977 u16 seid, 1978 struct i40e_asq_cmd_details *cmd_details) 1979 { 1980 struct i40e_aq_desc desc; 1981 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1982 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1983 &desc.params.raw; 1984 i40e_status status; 1985 1986 i40e_fill_default_direct_cmd_desc(&desc, 1987 i40e_aqc_opc_set_vsi_promiscuous_modes); 1988 1989 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1990 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1991 cmd->seid = cpu_to_le16(seid); 1992 1993 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1994 1995 return status; 1996 } 1997 1998 /** 1999 * i40e_aq_clear_default_vsi 2000 * @hw: pointer to the hw struct 2001 * @seid: vsi number 2002 * @cmd_details: pointer to command details structure or NULL 2003 **/ 2004 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2005 u16 seid, 2006 struct i40e_asq_cmd_details *cmd_details) 2007 { 2008 struct i40e_aq_desc desc; 2009 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2010 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2011 &desc.params.raw; 2012 i40e_status status; 2013 2014 i40e_fill_default_direct_cmd_desc(&desc, 2015 i40e_aqc_opc_set_vsi_promiscuous_modes); 2016 2017 cmd->promiscuous_flags = cpu_to_le16(0); 2018 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2019 cmd->seid = cpu_to_le16(seid); 2020 2021 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2022 2023 return status; 2024 } 2025 2026 /** 2027 * i40e_aq_set_vsi_unicast_promiscuous 2028 * @hw: pointer to the hw struct 2029 * @seid: vsi number 2030 * @set: set unicast promiscuous enable/disable 2031 * @cmd_details: pointer to command details structure or NULL 2032 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2033 **/ 2034 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2035 u16 seid, bool set, 2036 struct i40e_asq_cmd_details *cmd_details, 2037 bool rx_only_promisc) 2038 { 2039 struct i40e_aq_desc desc; 2040 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2041 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2042 i40e_status status; 2043 u16 flags = 0; 2044 2045 i40e_fill_default_direct_cmd_desc(&desc, 2046 i40e_aqc_opc_set_vsi_promiscuous_modes); 2047 2048 if (set) { 2049 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2050 if (rx_only_promisc && 2051 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2052 (hw->aq.api_maj_ver > 1))) 2053 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2054 } 2055 2056 cmd->promiscuous_flags = cpu_to_le16(flags); 2057 2058 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2059 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2060 (hw->aq.api_maj_ver > 1)) 2061 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2062 2063 cmd->seid = cpu_to_le16(seid); 2064 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2065 2066 return status; 2067 } 2068 2069 /** 2070 * i40e_aq_set_vsi_multicast_promiscuous 2071 * @hw: pointer to the hw struct 2072 * @seid: vsi number 2073 * @set: set multicast promiscuous enable/disable 2074 * @cmd_details: pointer to command details structure or NULL 2075 **/ 2076 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2077 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2078 { 2079 struct i40e_aq_desc desc; 2080 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2081 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2082 i40e_status status; 2083 u16 flags = 0; 2084 2085 i40e_fill_default_direct_cmd_desc(&desc, 2086 i40e_aqc_opc_set_vsi_promiscuous_modes); 2087 2088 if (set) 2089 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2090 2091 cmd->promiscuous_flags = cpu_to_le16(flags); 2092 2093 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2094 2095 cmd->seid = cpu_to_le16(seid); 2096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2097 2098 return status; 2099 } 2100 2101 /** 2102 * i40e_aq_set_vsi_mc_promisc_on_vlan 2103 * @hw: pointer to the hw struct 2104 * @seid: vsi number 2105 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2106 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2107 * @cmd_details: pointer to command details structure or NULL 2108 **/ 2109 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2110 u16 seid, bool enable, 2111 u16 vid, 2112 struct i40e_asq_cmd_details *cmd_details) 2113 { 2114 struct i40e_aq_desc desc; 2115 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2116 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2117 enum i40e_status_code status; 2118 u16 flags = 0; 2119 2120 i40e_fill_default_direct_cmd_desc(&desc, 2121 i40e_aqc_opc_set_vsi_promiscuous_modes); 2122 2123 if (enable) 2124 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2125 2126 cmd->promiscuous_flags = cpu_to_le16(flags); 2127 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2128 cmd->seid = cpu_to_le16(seid); 2129 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2130 2131 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2132 2133 return status; 2134 } 2135 2136 /** 2137 * i40e_aq_set_vsi_uc_promisc_on_vlan 2138 * @hw: pointer to the hw struct 2139 * @seid: vsi number 2140 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2141 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2142 * @cmd_details: pointer to command details structure or NULL 2143 **/ 2144 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2145 u16 seid, bool enable, 2146 u16 vid, 2147 struct i40e_asq_cmd_details *cmd_details) 2148 { 2149 struct i40e_aq_desc desc; 2150 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2151 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2152 enum i40e_status_code status; 2153 u16 flags = 0; 2154 2155 i40e_fill_default_direct_cmd_desc(&desc, 2156 i40e_aqc_opc_set_vsi_promiscuous_modes); 2157 2158 if (enable) 2159 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2160 2161 cmd->promiscuous_flags = cpu_to_le16(flags); 2162 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2163 cmd->seid = cpu_to_le16(seid); 2164 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2165 2166 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2167 2168 return status; 2169 } 2170 2171 /** 2172 * i40e_aq_set_vsi_broadcast 2173 * @hw: pointer to the hw struct 2174 * @seid: vsi number 2175 * @set_filter: true to set filter, false to clear filter 2176 * @cmd_details: pointer to command details structure or NULL 2177 * 2178 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2179 **/ 2180 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2181 u16 seid, bool set_filter, 2182 struct i40e_asq_cmd_details *cmd_details) 2183 { 2184 struct i40e_aq_desc desc; 2185 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2186 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2187 i40e_status status; 2188 2189 i40e_fill_default_direct_cmd_desc(&desc, 2190 i40e_aqc_opc_set_vsi_promiscuous_modes); 2191 2192 if (set_filter) 2193 cmd->promiscuous_flags 2194 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2195 else 2196 cmd->promiscuous_flags 2197 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2198 2199 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2200 cmd->seid = cpu_to_le16(seid); 2201 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2202 2203 return status; 2204 } 2205 2206 /** 2207 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2208 * @hw: pointer to the hw struct 2209 * @seid: vsi number 2210 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2211 * @cmd_details: pointer to command details structure or NULL 2212 **/ 2213 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2214 u16 seid, bool enable, 2215 struct i40e_asq_cmd_details *cmd_details) 2216 { 2217 struct i40e_aq_desc desc; 2218 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2219 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2220 i40e_status status; 2221 u16 flags = 0; 2222 2223 i40e_fill_default_direct_cmd_desc(&desc, 2224 i40e_aqc_opc_set_vsi_promiscuous_modes); 2225 if (enable) 2226 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2227 2228 cmd->promiscuous_flags = cpu_to_le16(flags); 2229 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2230 cmd->seid = cpu_to_le16(seid); 2231 2232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2233 2234 return status; 2235 } 2236 2237 /** 2238 * i40e_get_vsi_params - get VSI configuration info 2239 * @hw: pointer to the hw struct 2240 * @vsi_ctx: pointer to a vsi context struct 2241 * @cmd_details: pointer to command details structure or NULL 2242 **/ 2243 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2244 struct i40e_vsi_context *vsi_ctx, 2245 struct i40e_asq_cmd_details *cmd_details) 2246 { 2247 struct i40e_aq_desc desc; 2248 struct i40e_aqc_add_get_update_vsi *cmd = 2249 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2250 struct i40e_aqc_add_get_update_vsi_completion *resp = 2251 (struct i40e_aqc_add_get_update_vsi_completion *) 2252 &desc.params.raw; 2253 i40e_status status; 2254 2255 i40e_fill_default_direct_cmd_desc(&desc, 2256 i40e_aqc_opc_get_vsi_parameters); 2257 2258 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2259 2260 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2261 2262 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2263 sizeof(vsi_ctx->info), NULL); 2264 2265 if (status) 2266 goto aq_get_vsi_params_exit; 2267 2268 vsi_ctx->seid = le16_to_cpu(resp->seid); 2269 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2270 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2271 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2272 2273 aq_get_vsi_params_exit: 2274 return status; 2275 } 2276 2277 /** 2278 * i40e_aq_update_vsi_params 2279 * @hw: pointer to the hw struct 2280 * @vsi_ctx: pointer to a vsi context struct 2281 * @cmd_details: pointer to command details structure or NULL 2282 * 2283 * Update a VSI context. 2284 **/ 2285 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2286 struct i40e_vsi_context *vsi_ctx, 2287 struct i40e_asq_cmd_details *cmd_details) 2288 { 2289 struct i40e_aq_desc desc; 2290 struct i40e_aqc_add_get_update_vsi *cmd = 2291 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2292 struct i40e_aqc_add_get_update_vsi_completion *resp = 2293 (struct i40e_aqc_add_get_update_vsi_completion *) 2294 &desc.params.raw; 2295 i40e_status status; 2296 2297 i40e_fill_default_direct_cmd_desc(&desc, 2298 i40e_aqc_opc_update_vsi_parameters); 2299 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2300 2301 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2302 2303 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2304 sizeof(vsi_ctx->info), cmd_details); 2305 2306 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2307 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2308 2309 return status; 2310 } 2311 2312 /** 2313 * i40e_aq_get_switch_config 2314 * @hw: pointer to the hardware structure 2315 * @buf: pointer to the result buffer 2316 * @buf_size: length of input buffer 2317 * @start_seid: seid to start for the report, 0 == beginning 2318 * @cmd_details: pointer to command details structure or NULL 2319 * 2320 * Fill the buf with switch configuration returned from AdminQ command 2321 **/ 2322 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2323 struct i40e_aqc_get_switch_config_resp *buf, 2324 u16 buf_size, u16 *start_seid, 2325 struct i40e_asq_cmd_details *cmd_details) 2326 { 2327 struct i40e_aq_desc desc; 2328 struct i40e_aqc_switch_seid *scfg = 2329 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2330 i40e_status status; 2331 2332 i40e_fill_default_direct_cmd_desc(&desc, 2333 i40e_aqc_opc_get_switch_config); 2334 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2335 if (buf_size > I40E_AQ_LARGE_BUF) 2336 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2337 scfg->seid = cpu_to_le16(*start_seid); 2338 2339 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2340 *start_seid = le16_to_cpu(scfg->seid); 2341 2342 return status; 2343 } 2344 2345 /** 2346 * i40e_aq_set_switch_config 2347 * @hw: pointer to the hardware structure 2348 * @flags: bit flag values to set 2349 * @valid_flags: which bit flags to set 2350 * @cmd_details: pointer to command details structure or NULL 2351 * 2352 * Set switch configuration bits 2353 **/ 2354 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2355 u16 flags, 2356 u16 valid_flags, 2357 struct i40e_asq_cmd_details *cmd_details) 2358 { 2359 struct i40e_aq_desc desc; 2360 struct i40e_aqc_set_switch_config *scfg = 2361 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2362 enum i40e_status_code status; 2363 2364 i40e_fill_default_direct_cmd_desc(&desc, 2365 i40e_aqc_opc_set_switch_config); 2366 scfg->flags = cpu_to_le16(flags); 2367 scfg->valid_flags = cpu_to_le16(valid_flags); 2368 2369 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2370 2371 return status; 2372 } 2373 2374 /** 2375 * i40e_aq_get_firmware_version 2376 * @hw: pointer to the hw struct 2377 * @fw_major_version: firmware major version 2378 * @fw_minor_version: firmware minor version 2379 * @fw_build: firmware build number 2380 * @api_major_version: major queue version 2381 * @api_minor_version: minor queue version 2382 * @cmd_details: pointer to command details structure or NULL 2383 * 2384 * Get the firmware version from the admin queue commands 2385 **/ 2386 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2387 u16 *fw_major_version, u16 *fw_minor_version, 2388 u32 *fw_build, 2389 u16 *api_major_version, u16 *api_minor_version, 2390 struct i40e_asq_cmd_details *cmd_details) 2391 { 2392 struct i40e_aq_desc desc; 2393 struct i40e_aqc_get_version *resp = 2394 (struct i40e_aqc_get_version *)&desc.params.raw; 2395 i40e_status status; 2396 2397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2398 2399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2400 2401 if (!status) { 2402 if (fw_major_version) 2403 *fw_major_version = le16_to_cpu(resp->fw_major); 2404 if (fw_minor_version) 2405 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2406 if (fw_build) 2407 *fw_build = le32_to_cpu(resp->fw_build); 2408 if (api_major_version) 2409 *api_major_version = le16_to_cpu(resp->api_major); 2410 if (api_minor_version) 2411 *api_minor_version = le16_to_cpu(resp->api_minor); 2412 } 2413 2414 return status; 2415 } 2416 2417 /** 2418 * i40e_aq_send_driver_version 2419 * @hw: pointer to the hw struct 2420 * @dv: driver's major, minor version 2421 * @cmd_details: pointer to command details structure or NULL 2422 * 2423 * Send the driver version to the firmware 2424 **/ 2425 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2426 struct i40e_driver_version *dv, 2427 struct i40e_asq_cmd_details *cmd_details) 2428 { 2429 struct i40e_aq_desc desc; 2430 struct i40e_aqc_driver_version *cmd = 2431 (struct i40e_aqc_driver_version *)&desc.params.raw; 2432 i40e_status status; 2433 u16 len; 2434 2435 if (dv == NULL) 2436 return I40E_ERR_PARAM; 2437 2438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2439 2440 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2441 cmd->driver_major_ver = dv->major_version; 2442 cmd->driver_minor_ver = dv->minor_version; 2443 cmd->driver_build_ver = dv->build_version; 2444 cmd->driver_subbuild_ver = dv->subbuild_version; 2445 2446 len = 0; 2447 while (len < sizeof(dv->driver_string) && 2448 (dv->driver_string[len] < 0x80) && 2449 dv->driver_string[len]) 2450 len++; 2451 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2452 len, cmd_details); 2453 2454 return status; 2455 } 2456 2457 /** 2458 * i40e_get_link_status - get status of the HW network link 2459 * @hw: pointer to the hw struct 2460 * @link_up: pointer to bool (true/false = linkup/linkdown) 2461 * 2462 * Variable link_up true if link is up, false if link is down. 2463 * The variable link_up is invalid if returned value of status != 0 2464 * 2465 * Side effect: LinkStatusEvent reporting becomes enabled 2466 **/ 2467 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2468 { 2469 i40e_status status = 0; 2470 2471 if (hw->phy.get_link_info) { 2472 status = i40e_update_link_info(hw); 2473 2474 if (status) 2475 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2476 status); 2477 } 2478 2479 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2480 2481 return status; 2482 } 2483 2484 /** 2485 * i40e_updatelink_status - update status of the HW network link 2486 * @hw: pointer to the hw struct 2487 **/ 2488 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2489 { 2490 struct i40e_aq_get_phy_abilities_resp abilities; 2491 i40e_status status = 0; 2492 2493 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2494 if (status) 2495 return status; 2496 2497 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) { 2498 status = i40e_aq_get_phy_capabilities(hw, false, false, 2499 &abilities, NULL); 2500 if (status) 2501 return status; 2502 2503 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2504 sizeof(hw->phy.link_info.module_type)); 2505 } 2506 2507 return status; 2508 } 2509 2510 /** 2511 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2512 * @hw: pointer to the hw struct 2513 * @uplink_seid: the MAC or other gizmo SEID 2514 * @downlink_seid: the VSI SEID 2515 * @enabled_tc: bitmap of TCs to be enabled 2516 * @default_port: true for default port VSI, false for control port 2517 * @veb_seid: pointer to where to put the resulting VEB SEID 2518 * @enable_stats: true to turn on VEB stats 2519 * @cmd_details: pointer to command details structure or NULL 2520 * 2521 * This asks the FW to add a VEB between the uplink and downlink 2522 * elements. If the uplink SEID is 0, this will be a floating VEB. 2523 **/ 2524 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2525 u16 downlink_seid, u8 enabled_tc, 2526 bool default_port, u16 *veb_seid, 2527 bool enable_stats, 2528 struct i40e_asq_cmd_details *cmd_details) 2529 { 2530 struct i40e_aq_desc desc; 2531 struct i40e_aqc_add_veb *cmd = 2532 (struct i40e_aqc_add_veb *)&desc.params.raw; 2533 struct i40e_aqc_add_veb_completion *resp = 2534 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2535 i40e_status status; 2536 u16 veb_flags = 0; 2537 2538 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2539 if (!!uplink_seid != !!downlink_seid) 2540 return I40E_ERR_PARAM; 2541 2542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2543 2544 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2545 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2546 cmd->enable_tcs = enabled_tc; 2547 if (!uplink_seid) 2548 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2549 if (default_port) 2550 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2551 else 2552 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2553 2554 /* reverse logic here: set the bitflag to disable the stats */ 2555 if (!enable_stats) 2556 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2557 2558 cmd->veb_flags = cpu_to_le16(veb_flags); 2559 2560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2561 2562 if (!status && veb_seid) 2563 *veb_seid = le16_to_cpu(resp->veb_seid); 2564 2565 return status; 2566 } 2567 2568 /** 2569 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2570 * @hw: pointer to the hw struct 2571 * @veb_seid: the SEID of the VEB to query 2572 * @switch_id: the uplink switch id 2573 * @floating: set to true if the VEB is floating 2574 * @statistic_index: index of the stats counter block for this VEB 2575 * @vebs_used: number of VEB's used by function 2576 * @vebs_free: total VEB's not reserved by any function 2577 * @cmd_details: pointer to command details structure or NULL 2578 * 2579 * This retrieves the parameters for a particular VEB, specified by 2580 * uplink_seid, and returns them to the caller. 2581 **/ 2582 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2583 u16 veb_seid, u16 *switch_id, 2584 bool *floating, u16 *statistic_index, 2585 u16 *vebs_used, u16 *vebs_free, 2586 struct i40e_asq_cmd_details *cmd_details) 2587 { 2588 struct i40e_aq_desc desc; 2589 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2590 (struct i40e_aqc_get_veb_parameters_completion *) 2591 &desc.params.raw; 2592 i40e_status status; 2593 2594 if (veb_seid == 0) 2595 return I40E_ERR_PARAM; 2596 2597 i40e_fill_default_direct_cmd_desc(&desc, 2598 i40e_aqc_opc_get_veb_parameters); 2599 cmd_resp->seid = cpu_to_le16(veb_seid); 2600 2601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2602 if (status) 2603 goto get_veb_exit; 2604 2605 if (switch_id) 2606 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2607 if (statistic_index) 2608 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2609 if (vebs_used) 2610 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2611 if (vebs_free) 2612 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2613 if (floating) { 2614 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2615 2616 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2617 *floating = true; 2618 else 2619 *floating = false; 2620 } 2621 2622 get_veb_exit: 2623 return status; 2624 } 2625 2626 /** 2627 * i40e_aq_add_macvlan 2628 * @hw: pointer to the hw struct 2629 * @seid: VSI for the mac address 2630 * @mv_list: list of macvlans to be added 2631 * @count: length of the list 2632 * @cmd_details: pointer to command details structure or NULL 2633 * 2634 * Add MAC/VLAN addresses to the HW filtering 2635 **/ 2636 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2637 struct i40e_aqc_add_macvlan_element_data *mv_list, 2638 u16 count, struct i40e_asq_cmd_details *cmd_details) 2639 { 2640 struct i40e_aq_desc desc; 2641 struct i40e_aqc_macvlan *cmd = 2642 (struct i40e_aqc_macvlan *)&desc.params.raw; 2643 i40e_status status; 2644 u16 buf_size; 2645 int i; 2646 2647 if (count == 0 || !mv_list || !hw) 2648 return I40E_ERR_PARAM; 2649 2650 buf_size = count * sizeof(*mv_list); 2651 2652 /* prep the rest of the request */ 2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2654 cmd->num_addresses = cpu_to_le16(count); 2655 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2656 cmd->seid[1] = 0; 2657 cmd->seid[2] = 0; 2658 2659 for (i = 0; i < count; i++) 2660 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2661 mv_list[i].flags |= 2662 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2663 2664 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2665 if (buf_size > I40E_AQ_LARGE_BUF) 2666 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2667 2668 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2669 cmd_details); 2670 2671 return status; 2672 } 2673 2674 /** 2675 * i40e_aq_remove_macvlan 2676 * @hw: pointer to the hw struct 2677 * @seid: VSI for the mac address 2678 * @mv_list: list of macvlans to be removed 2679 * @count: length of the list 2680 * @cmd_details: pointer to command details structure or NULL 2681 * 2682 * Remove MAC/VLAN addresses from the HW filtering 2683 **/ 2684 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2685 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2686 u16 count, struct i40e_asq_cmd_details *cmd_details) 2687 { 2688 struct i40e_aq_desc desc; 2689 struct i40e_aqc_macvlan *cmd = 2690 (struct i40e_aqc_macvlan *)&desc.params.raw; 2691 i40e_status status; 2692 u16 buf_size; 2693 2694 if (count == 0 || !mv_list || !hw) 2695 return I40E_ERR_PARAM; 2696 2697 buf_size = count * sizeof(*mv_list); 2698 2699 /* prep the rest of the request */ 2700 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2701 cmd->num_addresses = cpu_to_le16(count); 2702 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2703 cmd->seid[1] = 0; 2704 cmd->seid[2] = 0; 2705 2706 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2707 if (buf_size > I40E_AQ_LARGE_BUF) 2708 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2709 2710 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2711 cmd_details); 2712 2713 return status; 2714 } 2715 2716 /** 2717 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2718 * @hw: pointer to the hw struct 2719 * @opcode: AQ opcode for add or delete mirror rule 2720 * @sw_seid: Switch SEID (to which rule refers) 2721 * @rule_type: Rule Type (ingress/egress/VLAN) 2722 * @id: Destination VSI SEID or Rule ID 2723 * @count: length of the list 2724 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2725 * @cmd_details: pointer to command details structure or NULL 2726 * @rule_id: Rule ID returned from FW 2727 * @rule_used: Number of rules used in internal switch 2728 * @rule_free: Number of rules free in internal switch 2729 * 2730 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2731 * VEBs/VEPA elements only 2732 **/ 2733 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2734 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2735 u16 count, __le16 *mr_list, 2736 struct i40e_asq_cmd_details *cmd_details, 2737 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2738 { 2739 struct i40e_aq_desc desc; 2740 struct i40e_aqc_add_delete_mirror_rule *cmd = 2741 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2742 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2743 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2744 i40e_status status; 2745 u16 buf_size; 2746 2747 buf_size = count * sizeof(*mr_list); 2748 2749 /* prep the rest of the request */ 2750 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2751 cmd->seid = cpu_to_le16(sw_seid); 2752 cmd->rule_type = cpu_to_le16(rule_type & 2753 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2754 cmd->num_entries = cpu_to_le16(count); 2755 /* Dest VSI for add, rule_id for delete */ 2756 cmd->destination = cpu_to_le16(id); 2757 if (mr_list) { 2758 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2759 I40E_AQ_FLAG_RD)); 2760 if (buf_size > I40E_AQ_LARGE_BUF) 2761 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2762 } 2763 2764 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2765 cmd_details); 2766 if (!status || 2767 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2768 if (rule_id) 2769 *rule_id = le16_to_cpu(resp->rule_id); 2770 if (rules_used) 2771 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2772 if (rules_free) 2773 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2774 } 2775 return status; 2776 } 2777 2778 /** 2779 * i40e_aq_add_mirrorrule - add a mirror rule 2780 * @hw: pointer to the hw struct 2781 * @sw_seid: Switch SEID (to which rule refers) 2782 * @rule_type: Rule Type (ingress/egress/VLAN) 2783 * @dest_vsi: SEID of VSI to which packets will be mirrored 2784 * @count: length of the list 2785 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2786 * @cmd_details: pointer to command details structure or NULL 2787 * @rule_id: Rule ID returned from FW 2788 * @rule_used: Number of rules used in internal switch 2789 * @rule_free: Number of rules free in internal switch 2790 * 2791 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2792 **/ 2793 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2794 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2795 struct i40e_asq_cmd_details *cmd_details, 2796 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2797 { 2798 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2799 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2800 if (count == 0 || !mr_list) 2801 return I40E_ERR_PARAM; 2802 } 2803 2804 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2805 rule_type, dest_vsi, count, mr_list, 2806 cmd_details, rule_id, rules_used, rules_free); 2807 } 2808 2809 /** 2810 * i40e_aq_delete_mirrorrule - delete a mirror rule 2811 * @hw: pointer to the hw struct 2812 * @sw_seid: Switch SEID (to which rule refers) 2813 * @rule_type: Rule Type (ingress/egress/VLAN) 2814 * @count: length of the list 2815 * @rule_id: Rule ID that is returned in the receive desc as part of 2816 * add_mirrorrule. 2817 * @mr_list: list of mirrored VLAN IDs to be removed 2818 * @cmd_details: pointer to command details structure or NULL 2819 * @rule_used: Number of rules used in internal switch 2820 * @rule_free: Number of rules free in internal switch 2821 * 2822 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2823 **/ 2824 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2825 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2826 struct i40e_asq_cmd_details *cmd_details, 2827 u16 *rules_used, u16 *rules_free) 2828 { 2829 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2830 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2831 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2832 * mirroring. For other rule_type, count and rule_type should 2833 * not matter. 2834 */ 2835 if (count == 0 || !mr_list) 2836 return I40E_ERR_PARAM; 2837 } 2838 2839 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2840 rule_type, rule_id, count, mr_list, 2841 cmd_details, NULL, rules_used, rules_free); 2842 } 2843 2844 /** 2845 * i40e_aq_send_msg_to_vf 2846 * @hw: pointer to the hardware structure 2847 * @vfid: VF id to send msg 2848 * @v_opcode: opcodes for VF-PF communication 2849 * @v_retval: return error code 2850 * @msg: pointer to the msg buffer 2851 * @msglen: msg length 2852 * @cmd_details: pointer to command details 2853 * 2854 * send msg to vf 2855 **/ 2856 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2857 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2858 struct i40e_asq_cmd_details *cmd_details) 2859 { 2860 struct i40e_aq_desc desc; 2861 struct i40e_aqc_pf_vf_message *cmd = 2862 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2863 i40e_status status; 2864 2865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2866 cmd->id = cpu_to_le32(vfid); 2867 desc.cookie_high = cpu_to_le32(v_opcode); 2868 desc.cookie_low = cpu_to_le32(v_retval); 2869 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2870 if (msglen) { 2871 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2872 I40E_AQ_FLAG_RD)); 2873 if (msglen > I40E_AQ_LARGE_BUF) 2874 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2875 desc.datalen = cpu_to_le16(msglen); 2876 } 2877 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2878 2879 return status; 2880 } 2881 2882 /** 2883 * i40e_aq_debug_read_register 2884 * @hw: pointer to the hw struct 2885 * @reg_addr: register address 2886 * @reg_val: register value 2887 * @cmd_details: pointer to command details structure or NULL 2888 * 2889 * Read the register using the admin queue commands 2890 **/ 2891 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2892 u32 reg_addr, u64 *reg_val, 2893 struct i40e_asq_cmd_details *cmd_details) 2894 { 2895 struct i40e_aq_desc desc; 2896 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2897 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2898 i40e_status status; 2899 2900 if (reg_val == NULL) 2901 return I40E_ERR_PARAM; 2902 2903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2904 2905 cmd_resp->address = cpu_to_le32(reg_addr); 2906 2907 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2908 2909 if (!status) { 2910 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2911 (u64)le32_to_cpu(cmd_resp->value_low); 2912 } 2913 2914 return status; 2915 } 2916 2917 /** 2918 * i40e_aq_debug_write_register 2919 * @hw: pointer to the hw struct 2920 * @reg_addr: register address 2921 * @reg_val: register value 2922 * @cmd_details: pointer to command details structure or NULL 2923 * 2924 * Write to a register using the admin queue commands 2925 **/ 2926 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2927 u32 reg_addr, u64 reg_val, 2928 struct i40e_asq_cmd_details *cmd_details) 2929 { 2930 struct i40e_aq_desc desc; 2931 struct i40e_aqc_debug_reg_read_write *cmd = 2932 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2933 i40e_status status; 2934 2935 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2936 2937 cmd->address = cpu_to_le32(reg_addr); 2938 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2939 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2940 2941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2942 2943 return status; 2944 } 2945 2946 /** 2947 * i40e_aq_request_resource 2948 * @hw: pointer to the hw struct 2949 * @resource: resource id 2950 * @access: access type 2951 * @sdp_number: resource number 2952 * @timeout: the maximum time in ms that the driver may hold the resource 2953 * @cmd_details: pointer to command details structure or NULL 2954 * 2955 * requests common resource using the admin queue commands 2956 **/ 2957 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2958 enum i40e_aq_resources_ids resource, 2959 enum i40e_aq_resource_access_type access, 2960 u8 sdp_number, u64 *timeout, 2961 struct i40e_asq_cmd_details *cmd_details) 2962 { 2963 struct i40e_aq_desc desc; 2964 struct i40e_aqc_request_resource *cmd_resp = 2965 (struct i40e_aqc_request_resource *)&desc.params.raw; 2966 i40e_status status; 2967 2968 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2969 2970 cmd_resp->resource_id = cpu_to_le16(resource); 2971 cmd_resp->access_type = cpu_to_le16(access); 2972 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2973 2974 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2975 /* The completion specifies the maximum time in ms that the driver 2976 * may hold the resource in the Timeout field. 2977 * If the resource is held by someone else, the command completes with 2978 * busy return value and the timeout field indicates the maximum time 2979 * the current owner of the resource has to free it. 2980 */ 2981 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2982 *timeout = le32_to_cpu(cmd_resp->timeout); 2983 2984 return status; 2985 } 2986 2987 /** 2988 * i40e_aq_release_resource 2989 * @hw: pointer to the hw struct 2990 * @resource: resource id 2991 * @sdp_number: resource number 2992 * @cmd_details: pointer to command details structure or NULL 2993 * 2994 * release common resource using the admin queue commands 2995 **/ 2996 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2997 enum i40e_aq_resources_ids resource, 2998 u8 sdp_number, 2999 struct i40e_asq_cmd_details *cmd_details) 3000 { 3001 struct i40e_aq_desc desc; 3002 struct i40e_aqc_request_resource *cmd = 3003 (struct i40e_aqc_request_resource *)&desc.params.raw; 3004 i40e_status status; 3005 3006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3007 3008 cmd->resource_id = cpu_to_le16(resource); 3009 cmd->resource_number = cpu_to_le32(sdp_number); 3010 3011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3012 3013 return status; 3014 } 3015 3016 /** 3017 * i40e_aq_read_nvm 3018 * @hw: pointer to the hw struct 3019 * @module_pointer: module pointer location in words from the NVM beginning 3020 * @offset: byte offset from the module beginning 3021 * @length: length of the section to be read (in bytes from the offset) 3022 * @data: command buffer (size [bytes] = length) 3023 * @last_command: tells if this is the last command in a series 3024 * @cmd_details: pointer to command details structure or NULL 3025 * 3026 * Read the NVM using the admin queue commands 3027 **/ 3028 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3029 u32 offset, u16 length, void *data, 3030 bool last_command, 3031 struct i40e_asq_cmd_details *cmd_details) 3032 { 3033 struct i40e_aq_desc desc; 3034 struct i40e_aqc_nvm_update *cmd = 3035 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3036 i40e_status status; 3037 3038 /* In offset the highest byte must be zeroed. */ 3039 if (offset & 0xFF000000) { 3040 status = I40E_ERR_PARAM; 3041 goto i40e_aq_read_nvm_exit; 3042 } 3043 3044 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3045 3046 /* If this is the last command in a series, set the proper flag. */ 3047 if (last_command) 3048 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3049 cmd->module_pointer = module_pointer; 3050 cmd->offset = cpu_to_le32(offset); 3051 cmd->length = cpu_to_le16(length); 3052 3053 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3054 if (length > I40E_AQ_LARGE_BUF) 3055 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3056 3057 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3058 3059 i40e_aq_read_nvm_exit: 3060 return status; 3061 } 3062 3063 /** 3064 * i40e_aq_erase_nvm 3065 * @hw: pointer to the hw struct 3066 * @module_pointer: module pointer location in words from the NVM beginning 3067 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3068 * @length: length of the section to be erased (expressed in 4 KB) 3069 * @last_command: tells if this is the last command in a series 3070 * @cmd_details: pointer to command details structure or NULL 3071 * 3072 * Erase the NVM sector using the admin queue commands 3073 **/ 3074 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3075 u32 offset, u16 length, bool last_command, 3076 struct i40e_asq_cmd_details *cmd_details) 3077 { 3078 struct i40e_aq_desc desc; 3079 struct i40e_aqc_nvm_update *cmd = 3080 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3081 i40e_status status; 3082 3083 /* In offset the highest byte must be zeroed. */ 3084 if (offset & 0xFF000000) { 3085 status = I40E_ERR_PARAM; 3086 goto i40e_aq_erase_nvm_exit; 3087 } 3088 3089 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3090 3091 /* If this is the last command in a series, set the proper flag. */ 3092 if (last_command) 3093 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3094 cmd->module_pointer = module_pointer; 3095 cmd->offset = cpu_to_le32(offset); 3096 cmd->length = cpu_to_le16(length); 3097 3098 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3099 3100 i40e_aq_erase_nvm_exit: 3101 return status; 3102 } 3103 3104 /** 3105 * i40e_parse_discover_capabilities 3106 * @hw: pointer to the hw struct 3107 * @buff: pointer to a buffer containing device/function capability records 3108 * @cap_count: number of capability records in the list 3109 * @list_type_opc: type of capabilities list to parse 3110 * 3111 * Parse the device/function capabilities list. 3112 **/ 3113 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3114 u32 cap_count, 3115 enum i40e_admin_queue_opc list_type_opc) 3116 { 3117 struct i40e_aqc_list_capabilities_element_resp *cap; 3118 u32 valid_functions, num_functions; 3119 u32 number, logical_id, phys_id; 3120 struct i40e_hw_capabilities *p; 3121 u8 major_rev; 3122 u32 i = 0; 3123 u16 id; 3124 3125 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3126 3127 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3128 p = &hw->dev_caps; 3129 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3130 p = &hw->func_caps; 3131 else 3132 return; 3133 3134 for (i = 0; i < cap_count; i++, cap++) { 3135 id = le16_to_cpu(cap->id); 3136 number = le32_to_cpu(cap->number); 3137 logical_id = le32_to_cpu(cap->logical_id); 3138 phys_id = le32_to_cpu(cap->phys_id); 3139 major_rev = cap->major_rev; 3140 3141 switch (id) { 3142 case I40E_AQ_CAP_ID_SWITCH_MODE: 3143 p->switch_mode = number; 3144 break; 3145 case I40E_AQ_CAP_ID_MNG_MODE: 3146 p->management_mode = number; 3147 break; 3148 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3149 p->npar_enable = number; 3150 break; 3151 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3152 p->os2bmc = number; 3153 break; 3154 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3155 p->valid_functions = number; 3156 break; 3157 case I40E_AQ_CAP_ID_SRIOV: 3158 if (number == 1) 3159 p->sr_iov_1_1 = true; 3160 break; 3161 case I40E_AQ_CAP_ID_VF: 3162 p->num_vfs = number; 3163 p->vf_base_id = logical_id; 3164 break; 3165 case I40E_AQ_CAP_ID_VMDQ: 3166 if (number == 1) 3167 p->vmdq = true; 3168 break; 3169 case I40E_AQ_CAP_ID_8021QBG: 3170 if (number == 1) 3171 p->evb_802_1_qbg = true; 3172 break; 3173 case I40E_AQ_CAP_ID_8021QBR: 3174 if (number == 1) 3175 p->evb_802_1_qbh = true; 3176 break; 3177 case I40E_AQ_CAP_ID_VSI: 3178 p->num_vsis = number; 3179 break; 3180 case I40E_AQ_CAP_ID_DCB: 3181 if (number == 1) { 3182 p->dcb = true; 3183 p->enabled_tcmap = logical_id; 3184 p->maxtc = phys_id; 3185 } 3186 break; 3187 case I40E_AQ_CAP_ID_FCOE: 3188 if (number == 1) 3189 p->fcoe = true; 3190 break; 3191 case I40E_AQ_CAP_ID_ISCSI: 3192 if (number == 1) 3193 p->iscsi = true; 3194 break; 3195 case I40E_AQ_CAP_ID_RSS: 3196 p->rss = true; 3197 p->rss_table_size = number; 3198 p->rss_table_entry_width = logical_id; 3199 break; 3200 case I40E_AQ_CAP_ID_RXQ: 3201 p->num_rx_qp = number; 3202 p->base_queue = phys_id; 3203 break; 3204 case I40E_AQ_CAP_ID_TXQ: 3205 p->num_tx_qp = number; 3206 p->base_queue = phys_id; 3207 break; 3208 case I40E_AQ_CAP_ID_MSIX: 3209 p->num_msix_vectors = number; 3210 i40e_debug(hw, I40E_DEBUG_INIT, 3211 "HW Capability: MSIX vector count = %d\n", 3212 p->num_msix_vectors); 3213 break; 3214 case I40E_AQ_CAP_ID_VF_MSIX: 3215 p->num_msix_vectors_vf = number; 3216 break; 3217 case I40E_AQ_CAP_ID_FLEX10: 3218 if (major_rev == 1) { 3219 if (number == 1) { 3220 p->flex10_enable = true; 3221 p->flex10_capable = true; 3222 } 3223 } else { 3224 /* Capability revision >= 2 */ 3225 if (number & 1) 3226 p->flex10_enable = true; 3227 if (number & 2) 3228 p->flex10_capable = true; 3229 } 3230 p->flex10_mode = logical_id; 3231 p->flex10_status = phys_id; 3232 break; 3233 case I40E_AQ_CAP_ID_CEM: 3234 if (number == 1) 3235 p->mgmt_cem = true; 3236 break; 3237 case I40E_AQ_CAP_ID_IWARP: 3238 if (number == 1) 3239 p->iwarp = true; 3240 break; 3241 case I40E_AQ_CAP_ID_LED: 3242 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3243 p->led[phys_id] = true; 3244 break; 3245 case I40E_AQ_CAP_ID_SDP: 3246 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3247 p->sdp[phys_id] = true; 3248 break; 3249 case I40E_AQ_CAP_ID_MDIO: 3250 if (number == 1) { 3251 p->mdio_port_num = phys_id; 3252 p->mdio_port_mode = logical_id; 3253 } 3254 break; 3255 case I40E_AQ_CAP_ID_1588: 3256 if (number == 1) 3257 p->ieee_1588 = true; 3258 break; 3259 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3260 p->fd = true; 3261 p->fd_filters_guaranteed = number; 3262 p->fd_filters_best_effort = logical_id; 3263 break; 3264 case I40E_AQ_CAP_ID_WSR_PROT: 3265 p->wr_csr_prot = (u64)number; 3266 p->wr_csr_prot |= (u64)logical_id << 32; 3267 break; 3268 case I40E_AQ_CAP_ID_NVM_MGMT: 3269 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3270 p->sec_rev_disabled = true; 3271 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3272 p->update_disabled = true; 3273 break; 3274 default: 3275 break; 3276 } 3277 } 3278 3279 if (p->fcoe) 3280 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3281 3282 /* Software override ensuring FCoE is disabled if npar or mfp 3283 * mode because it is not supported in these modes. 3284 */ 3285 if (p->npar_enable || p->flex10_enable) 3286 p->fcoe = false; 3287 3288 /* count the enabled ports (aka the "not disabled" ports) */ 3289 hw->num_ports = 0; 3290 for (i = 0; i < 4; i++) { 3291 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3292 u64 port_cfg = 0; 3293 3294 /* use AQ read to get the physical register offset instead 3295 * of the port relative offset 3296 */ 3297 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3298 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3299 hw->num_ports++; 3300 } 3301 3302 valid_functions = p->valid_functions; 3303 num_functions = 0; 3304 while (valid_functions) { 3305 if (valid_functions & 1) 3306 num_functions++; 3307 valid_functions >>= 1; 3308 } 3309 3310 /* partition id is 1-based, and functions are evenly spread 3311 * across the ports as partitions 3312 */ 3313 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3314 hw->num_partitions = num_functions / hw->num_ports; 3315 3316 /* additional HW specific goodies that might 3317 * someday be HW version specific 3318 */ 3319 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3320 } 3321 3322 /** 3323 * i40e_aq_discover_capabilities 3324 * @hw: pointer to the hw struct 3325 * @buff: a virtual buffer to hold the capabilities 3326 * @buff_size: Size of the virtual buffer 3327 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3328 * @list_type_opc: capabilities type to discover - pass in the command opcode 3329 * @cmd_details: pointer to command details structure or NULL 3330 * 3331 * Get the device capabilities descriptions from the firmware 3332 **/ 3333 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3334 void *buff, u16 buff_size, u16 *data_size, 3335 enum i40e_admin_queue_opc list_type_opc, 3336 struct i40e_asq_cmd_details *cmd_details) 3337 { 3338 struct i40e_aqc_list_capabilites *cmd; 3339 struct i40e_aq_desc desc; 3340 i40e_status status = 0; 3341 3342 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3343 3344 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3345 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3346 status = I40E_ERR_PARAM; 3347 goto exit; 3348 } 3349 3350 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3351 3352 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3353 if (buff_size > I40E_AQ_LARGE_BUF) 3354 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3355 3356 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3357 *data_size = le16_to_cpu(desc.datalen); 3358 3359 if (status) 3360 goto exit; 3361 3362 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3363 list_type_opc); 3364 3365 exit: 3366 return status; 3367 } 3368 3369 /** 3370 * i40e_aq_update_nvm 3371 * @hw: pointer to the hw struct 3372 * @module_pointer: module pointer location in words from the NVM beginning 3373 * @offset: byte offset from the module beginning 3374 * @length: length of the section to be written (in bytes from the offset) 3375 * @data: command buffer (size [bytes] = length) 3376 * @last_command: tells if this is the last command in a series 3377 * @cmd_details: pointer to command details structure or NULL 3378 * 3379 * Update the NVM using the admin queue commands 3380 **/ 3381 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3382 u32 offset, u16 length, void *data, 3383 bool last_command, 3384 struct i40e_asq_cmd_details *cmd_details) 3385 { 3386 struct i40e_aq_desc desc; 3387 struct i40e_aqc_nvm_update *cmd = 3388 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3389 i40e_status status; 3390 3391 /* In offset the highest byte must be zeroed. */ 3392 if (offset & 0xFF000000) { 3393 status = I40E_ERR_PARAM; 3394 goto i40e_aq_update_nvm_exit; 3395 } 3396 3397 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3398 3399 /* If this is the last command in a series, set the proper flag. */ 3400 if (last_command) 3401 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3402 cmd->module_pointer = module_pointer; 3403 cmd->offset = cpu_to_le32(offset); 3404 cmd->length = cpu_to_le16(length); 3405 3406 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3407 if (length > I40E_AQ_LARGE_BUF) 3408 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3409 3410 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3411 3412 i40e_aq_update_nvm_exit: 3413 return status; 3414 } 3415 3416 /** 3417 * i40e_aq_get_lldp_mib 3418 * @hw: pointer to the hw struct 3419 * @bridge_type: type of bridge requested 3420 * @mib_type: Local, Remote or both Local and Remote MIBs 3421 * @buff: pointer to a user supplied buffer to store the MIB block 3422 * @buff_size: size of the buffer (in bytes) 3423 * @local_len : length of the returned Local LLDP MIB 3424 * @remote_len: length of the returned Remote LLDP MIB 3425 * @cmd_details: pointer to command details structure or NULL 3426 * 3427 * Requests the complete LLDP MIB (entire packet). 3428 **/ 3429 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3430 u8 mib_type, void *buff, u16 buff_size, 3431 u16 *local_len, u16 *remote_len, 3432 struct i40e_asq_cmd_details *cmd_details) 3433 { 3434 struct i40e_aq_desc desc; 3435 struct i40e_aqc_lldp_get_mib *cmd = 3436 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3437 struct i40e_aqc_lldp_get_mib *resp = 3438 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3439 i40e_status status; 3440 3441 if (buff_size == 0 || !buff) 3442 return I40E_ERR_PARAM; 3443 3444 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3445 /* Indirect Command */ 3446 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3447 3448 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3449 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3450 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3451 3452 desc.datalen = cpu_to_le16(buff_size); 3453 3454 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3455 if (buff_size > I40E_AQ_LARGE_BUF) 3456 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3457 3458 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3459 if (!status) { 3460 if (local_len != NULL) 3461 *local_len = le16_to_cpu(resp->local_len); 3462 if (remote_len != NULL) 3463 *remote_len = le16_to_cpu(resp->remote_len); 3464 } 3465 3466 return status; 3467 } 3468 3469 /** 3470 * i40e_aq_cfg_lldp_mib_change_event 3471 * @hw: pointer to the hw struct 3472 * @enable_update: Enable or Disable event posting 3473 * @cmd_details: pointer to command details structure or NULL 3474 * 3475 * Enable or Disable posting of an event on ARQ when LLDP MIB 3476 * associated with the interface changes 3477 **/ 3478 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3479 bool enable_update, 3480 struct i40e_asq_cmd_details *cmd_details) 3481 { 3482 struct i40e_aq_desc desc; 3483 struct i40e_aqc_lldp_update_mib *cmd = 3484 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3485 i40e_status status; 3486 3487 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3488 3489 if (!enable_update) 3490 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3491 3492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3493 3494 return status; 3495 } 3496 3497 /** 3498 * i40e_aq_stop_lldp 3499 * @hw: pointer to the hw struct 3500 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3501 * @cmd_details: pointer to command details structure or NULL 3502 * 3503 * Stop or Shutdown the embedded LLDP Agent 3504 **/ 3505 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3506 struct i40e_asq_cmd_details *cmd_details) 3507 { 3508 struct i40e_aq_desc desc; 3509 struct i40e_aqc_lldp_stop *cmd = 3510 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3511 i40e_status status; 3512 3513 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3514 3515 if (shutdown_agent) 3516 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3517 3518 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3519 3520 return status; 3521 } 3522 3523 /** 3524 * i40e_aq_start_lldp 3525 * @hw: pointer to the hw struct 3526 * @cmd_details: pointer to command details structure or NULL 3527 * 3528 * Start the embedded LLDP Agent on all ports. 3529 **/ 3530 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3531 struct i40e_asq_cmd_details *cmd_details) 3532 { 3533 struct i40e_aq_desc desc; 3534 struct i40e_aqc_lldp_start *cmd = 3535 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3536 i40e_status status; 3537 3538 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3539 3540 cmd->command = I40E_AQ_LLDP_AGENT_START; 3541 3542 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3543 3544 return status; 3545 } 3546 3547 /** 3548 * i40e_aq_get_cee_dcb_config 3549 * @hw: pointer to the hw struct 3550 * @buff: response buffer that stores CEE operational configuration 3551 * @buff_size: size of the buffer passed 3552 * @cmd_details: pointer to command details structure or NULL 3553 * 3554 * Get CEE DCBX mode operational configuration from firmware 3555 **/ 3556 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3557 void *buff, u16 buff_size, 3558 struct i40e_asq_cmd_details *cmd_details) 3559 { 3560 struct i40e_aq_desc desc; 3561 i40e_status status; 3562 3563 if (buff_size == 0 || !buff) 3564 return I40E_ERR_PARAM; 3565 3566 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3567 3568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3569 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3570 cmd_details); 3571 3572 return status; 3573 } 3574 3575 /** 3576 * i40e_aq_add_udp_tunnel 3577 * @hw: pointer to the hw struct 3578 * @udp_port: the UDP port to add 3579 * @header_len: length of the tunneling header length in DWords 3580 * @protocol_index: protocol index type 3581 * @filter_index: pointer to filter index 3582 * @cmd_details: pointer to command details structure or NULL 3583 **/ 3584 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3585 u16 udp_port, u8 protocol_index, 3586 u8 *filter_index, 3587 struct i40e_asq_cmd_details *cmd_details) 3588 { 3589 struct i40e_aq_desc desc; 3590 struct i40e_aqc_add_udp_tunnel *cmd = 3591 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3592 struct i40e_aqc_del_udp_tunnel_completion *resp = 3593 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3594 i40e_status status; 3595 3596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3597 3598 cmd->udp_port = cpu_to_le16(udp_port); 3599 cmd->protocol_type = protocol_index; 3600 3601 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3602 3603 if (!status && filter_index) 3604 *filter_index = resp->index; 3605 3606 return status; 3607 } 3608 3609 /** 3610 * i40e_aq_del_udp_tunnel 3611 * @hw: pointer to the hw struct 3612 * @index: filter index 3613 * @cmd_details: pointer to command details structure or NULL 3614 **/ 3615 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3616 struct i40e_asq_cmd_details *cmd_details) 3617 { 3618 struct i40e_aq_desc desc; 3619 struct i40e_aqc_remove_udp_tunnel *cmd = 3620 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3621 i40e_status status; 3622 3623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3624 3625 cmd->index = index; 3626 3627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3628 3629 return status; 3630 } 3631 3632 /** 3633 * i40e_aq_delete_element - Delete switch element 3634 * @hw: pointer to the hw struct 3635 * @seid: the SEID to delete from the switch 3636 * @cmd_details: pointer to command details structure or NULL 3637 * 3638 * This deletes a switch element from the switch. 3639 **/ 3640 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3641 struct i40e_asq_cmd_details *cmd_details) 3642 { 3643 struct i40e_aq_desc desc; 3644 struct i40e_aqc_switch_seid *cmd = 3645 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3646 i40e_status status; 3647 3648 if (seid == 0) 3649 return I40E_ERR_PARAM; 3650 3651 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3652 3653 cmd->seid = cpu_to_le16(seid); 3654 3655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3656 3657 return status; 3658 } 3659 3660 /** 3661 * i40e_aq_dcb_updated - DCB Updated Command 3662 * @hw: pointer to the hw struct 3663 * @cmd_details: pointer to command details structure or NULL 3664 * 3665 * EMP will return when the shared RPB settings have been 3666 * recomputed and modified. The retval field in the descriptor 3667 * will be set to 0 when RPB is modified. 3668 **/ 3669 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3670 struct i40e_asq_cmd_details *cmd_details) 3671 { 3672 struct i40e_aq_desc desc; 3673 i40e_status status; 3674 3675 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3676 3677 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3678 3679 return status; 3680 } 3681 3682 /** 3683 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3684 * @hw: pointer to the hw struct 3685 * @seid: seid for the physical port/switching component/vsi 3686 * @buff: Indirect buffer to hold data parameters and response 3687 * @buff_size: Indirect buffer size 3688 * @opcode: Tx scheduler AQ command opcode 3689 * @cmd_details: pointer to command details structure or NULL 3690 * 3691 * Generic command handler for Tx scheduler AQ commands 3692 **/ 3693 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3694 void *buff, u16 buff_size, 3695 enum i40e_admin_queue_opc opcode, 3696 struct i40e_asq_cmd_details *cmd_details) 3697 { 3698 struct i40e_aq_desc desc; 3699 struct i40e_aqc_tx_sched_ind *cmd = 3700 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3701 i40e_status status; 3702 bool cmd_param_flag = false; 3703 3704 switch (opcode) { 3705 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3706 case i40e_aqc_opc_configure_vsi_tc_bw: 3707 case i40e_aqc_opc_enable_switching_comp_ets: 3708 case i40e_aqc_opc_modify_switching_comp_ets: 3709 case i40e_aqc_opc_disable_switching_comp_ets: 3710 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3711 case i40e_aqc_opc_configure_switching_comp_bw_config: 3712 cmd_param_flag = true; 3713 break; 3714 case i40e_aqc_opc_query_vsi_bw_config: 3715 case i40e_aqc_opc_query_vsi_ets_sla_config: 3716 case i40e_aqc_opc_query_switching_comp_ets_config: 3717 case i40e_aqc_opc_query_port_ets_config: 3718 case i40e_aqc_opc_query_switching_comp_bw_config: 3719 cmd_param_flag = false; 3720 break; 3721 default: 3722 return I40E_ERR_PARAM; 3723 } 3724 3725 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3726 3727 /* Indirect command */ 3728 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3729 if (cmd_param_flag) 3730 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3731 if (buff_size > I40E_AQ_LARGE_BUF) 3732 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3733 3734 desc.datalen = cpu_to_le16(buff_size); 3735 3736 cmd->vsi_seid = cpu_to_le16(seid); 3737 3738 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3739 3740 return status; 3741 } 3742 3743 /** 3744 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3745 * @hw: pointer to the hw struct 3746 * @seid: VSI seid 3747 * @credit: BW limit credits (0 = disabled) 3748 * @max_credit: Max BW limit credits 3749 * @cmd_details: pointer to command details structure or NULL 3750 **/ 3751 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3752 u16 seid, u16 credit, u8 max_credit, 3753 struct i40e_asq_cmd_details *cmd_details) 3754 { 3755 struct i40e_aq_desc desc; 3756 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3757 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3758 i40e_status status; 3759 3760 i40e_fill_default_direct_cmd_desc(&desc, 3761 i40e_aqc_opc_configure_vsi_bw_limit); 3762 3763 cmd->vsi_seid = cpu_to_le16(seid); 3764 cmd->credit = cpu_to_le16(credit); 3765 cmd->max_credit = max_credit; 3766 3767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3768 3769 return status; 3770 } 3771 3772 /** 3773 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3774 * @hw: pointer to the hw struct 3775 * @seid: VSI seid 3776 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3777 * @cmd_details: pointer to command details structure or NULL 3778 **/ 3779 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3780 u16 seid, 3781 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3782 struct i40e_asq_cmd_details *cmd_details) 3783 { 3784 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3785 i40e_aqc_opc_configure_vsi_tc_bw, 3786 cmd_details); 3787 } 3788 3789 /** 3790 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3791 * @hw: pointer to the hw struct 3792 * @seid: seid of the switching component connected to Physical Port 3793 * @ets_data: Buffer holding ETS parameters 3794 * @cmd_details: pointer to command details structure or NULL 3795 **/ 3796 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3797 u16 seid, 3798 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3799 enum i40e_admin_queue_opc opcode, 3800 struct i40e_asq_cmd_details *cmd_details) 3801 { 3802 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3803 sizeof(*ets_data), opcode, cmd_details); 3804 } 3805 3806 /** 3807 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3808 * @hw: pointer to the hw struct 3809 * @seid: seid of the switching component 3810 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3811 * @cmd_details: pointer to command details structure or NULL 3812 **/ 3813 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3814 u16 seid, 3815 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3816 struct i40e_asq_cmd_details *cmd_details) 3817 { 3818 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3819 i40e_aqc_opc_configure_switching_comp_bw_config, 3820 cmd_details); 3821 } 3822 3823 /** 3824 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3825 * @hw: pointer to the hw struct 3826 * @seid: seid of the VSI 3827 * @bw_data: Buffer to hold VSI BW configuration 3828 * @cmd_details: pointer to command details structure or NULL 3829 **/ 3830 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3831 u16 seid, 3832 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3833 struct i40e_asq_cmd_details *cmd_details) 3834 { 3835 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3836 i40e_aqc_opc_query_vsi_bw_config, 3837 cmd_details); 3838 } 3839 3840 /** 3841 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3842 * @hw: pointer to the hw struct 3843 * @seid: seid of the VSI 3844 * @bw_data: Buffer to hold VSI BW configuration per TC 3845 * @cmd_details: pointer to command details structure or NULL 3846 **/ 3847 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3848 u16 seid, 3849 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3850 struct i40e_asq_cmd_details *cmd_details) 3851 { 3852 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3853 i40e_aqc_opc_query_vsi_ets_sla_config, 3854 cmd_details); 3855 } 3856 3857 /** 3858 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3859 * @hw: pointer to the hw struct 3860 * @seid: seid of the switching component 3861 * @bw_data: Buffer to hold switching component's per TC BW config 3862 * @cmd_details: pointer to command details structure or NULL 3863 **/ 3864 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3865 u16 seid, 3866 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3867 struct i40e_asq_cmd_details *cmd_details) 3868 { 3869 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3870 i40e_aqc_opc_query_switching_comp_ets_config, 3871 cmd_details); 3872 } 3873 3874 /** 3875 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3876 * @hw: pointer to the hw struct 3877 * @seid: seid of the VSI or switching component connected to Physical Port 3878 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3879 * @cmd_details: pointer to command details structure or NULL 3880 **/ 3881 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3882 u16 seid, 3883 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3884 struct i40e_asq_cmd_details *cmd_details) 3885 { 3886 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3887 i40e_aqc_opc_query_port_ets_config, 3888 cmd_details); 3889 } 3890 3891 /** 3892 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3893 * @hw: pointer to the hw struct 3894 * @seid: seid of the switching component 3895 * @bw_data: Buffer to hold switching component's BW configuration 3896 * @cmd_details: pointer to command details structure or NULL 3897 **/ 3898 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3899 u16 seid, 3900 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3901 struct i40e_asq_cmd_details *cmd_details) 3902 { 3903 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3904 i40e_aqc_opc_query_switching_comp_bw_config, 3905 cmd_details); 3906 } 3907 3908 /** 3909 * i40e_validate_filter_settings 3910 * @hw: pointer to the hardware structure 3911 * @settings: Filter control settings 3912 * 3913 * Check and validate the filter control settings passed. 3914 * The function checks for the valid filter/context sizes being 3915 * passed for FCoE and PE. 3916 * 3917 * Returns 0 if the values passed are valid and within 3918 * range else returns an error. 3919 **/ 3920 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3921 struct i40e_filter_control_settings *settings) 3922 { 3923 u32 fcoe_cntx_size, fcoe_filt_size; 3924 u32 pe_cntx_size, pe_filt_size; 3925 u32 fcoe_fmax; 3926 u32 val; 3927 3928 /* Validate FCoE settings passed */ 3929 switch (settings->fcoe_filt_num) { 3930 case I40E_HASH_FILTER_SIZE_1K: 3931 case I40E_HASH_FILTER_SIZE_2K: 3932 case I40E_HASH_FILTER_SIZE_4K: 3933 case I40E_HASH_FILTER_SIZE_8K: 3934 case I40E_HASH_FILTER_SIZE_16K: 3935 case I40E_HASH_FILTER_SIZE_32K: 3936 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3937 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 3938 break; 3939 default: 3940 return I40E_ERR_PARAM; 3941 } 3942 3943 switch (settings->fcoe_cntx_num) { 3944 case I40E_DMA_CNTX_SIZE_512: 3945 case I40E_DMA_CNTX_SIZE_1K: 3946 case I40E_DMA_CNTX_SIZE_2K: 3947 case I40E_DMA_CNTX_SIZE_4K: 3948 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3949 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3950 break; 3951 default: 3952 return I40E_ERR_PARAM; 3953 } 3954 3955 /* Validate PE settings passed */ 3956 switch (settings->pe_filt_num) { 3957 case I40E_HASH_FILTER_SIZE_1K: 3958 case I40E_HASH_FILTER_SIZE_2K: 3959 case I40E_HASH_FILTER_SIZE_4K: 3960 case I40E_HASH_FILTER_SIZE_8K: 3961 case I40E_HASH_FILTER_SIZE_16K: 3962 case I40E_HASH_FILTER_SIZE_32K: 3963 case I40E_HASH_FILTER_SIZE_64K: 3964 case I40E_HASH_FILTER_SIZE_128K: 3965 case I40E_HASH_FILTER_SIZE_256K: 3966 case I40E_HASH_FILTER_SIZE_512K: 3967 case I40E_HASH_FILTER_SIZE_1M: 3968 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3969 pe_filt_size <<= (u32)settings->pe_filt_num; 3970 break; 3971 default: 3972 return I40E_ERR_PARAM; 3973 } 3974 3975 switch (settings->pe_cntx_num) { 3976 case I40E_DMA_CNTX_SIZE_512: 3977 case I40E_DMA_CNTX_SIZE_1K: 3978 case I40E_DMA_CNTX_SIZE_2K: 3979 case I40E_DMA_CNTX_SIZE_4K: 3980 case I40E_DMA_CNTX_SIZE_8K: 3981 case I40E_DMA_CNTX_SIZE_16K: 3982 case I40E_DMA_CNTX_SIZE_32K: 3983 case I40E_DMA_CNTX_SIZE_64K: 3984 case I40E_DMA_CNTX_SIZE_128K: 3985 case I40E_DMA_CNTX_SIZE_256K: 3986 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3987 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3988 break; 3989 default: 3990 return I40E_ERR_PARAM; 3991 } 3992 3993 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3994 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3995 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3996 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3997 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3998 return I40E_ERR_INVALID_SIZE; 3999 4000 return 0; 4001 } 4002 4003 /** 4004 * i40e_set_filter_control 4005 * @hw: pointer to the hardware structure 4006 * @settings: Filter control settings 4007 * 4008 * Set the Queue Filters for PE/FCoE and enable filters required 4009 * for a single PF. It is expected that these settings are programmed 4010 * at the driver initialization time. 4011 **/ 4012 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4013 struct i40e_filter_control_settings *settings) 4014 { 4015 i40e_status ret = 0; 4016 u32 hash_lut_size = 0; 4017 u32 val; 4018 4019 if (!settings) 4020 return I40E_ERR_PARAM; 4021 4022 /* Validate the input settings */ 4023 ret = i40e_validate_filter_settings(hw, settings); 4024 if (ret) 4025 return ret; 4026 4027 /* Read the PF Queue Filter control register */ 4028 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4029 4030 /* Program required PE hash buckets for the PF */ 4031 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4032 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4033 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4034 /* Program required PE contexts for the PF */ 4035 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4036 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4037 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4038 4039 /* Program required FCoE hash buckets for the PF */ 4040 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4041 val |= ((u32)settings->fcoe_filt_num << 4042 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4043 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4044 /* Program required FCoE DDP contexts for the PF */ 4045 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4046 val |= ((u32)settings->fcoe_cntx_num << 4047 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4048 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4049 4050 /* Program Hash LUT size for the PF */ 4051 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4052 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4053 hash_lut_size = 1; 4054 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4055 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4056 4057 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4058 if (settings->enable_fdir) 4059 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4060 if (settings->enable_ethtype) 4061 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4062 if (settings->enable_macvlan) 4063 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4064 4065 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4066 4067 return 0; 4068 } 4069 4070 /** 4071 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4072 * @hw: pointer to the hw struct 4073 * @mac_addr: MAC address to use in the filter 4074 * @ethtype: Ethertype to use in the filter 4075 * @flags: Flags that needs to be applied to the filter 4076 * @vsi_seid: seid of the control VSI 4077 * @queue: VSI queue number to send the packet to 4078 * @is_add: Add control packet filter if True else remove 4079 * @stats: Structure to hold information on control filter counts 4080 * @cmd_details: pointer to command details structure or NULL 4081 * 4082 * This command will Add or Remove control packet filter for a control VSI. 4083 * In return it will update the total number of perfect filter count in 4084 * the stats member. 4085 **/ 4086 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4087 u8 *mac_addr, u16 ethtype, u16 flags, 4088 u16 vsi_seid, u16 queue, bool is_add, 4089 struct i40e_control_filter_stats *stats, 4090 struct i40e_asq_cmd_details *cmd_details) 4091 { 4092 struct i40e_aq_desc desc; 4093 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4094 (struct i40e_aqc_add_remove_control_packet_filter *) 4095 &desc.params.raw; 4096 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4097 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4098 &desc.params.raw; 4099 i40e_status status; 4100 4101 if (vsi_seid == 0) 4102 return I40E_ERR_PARAM; 4103 4104 if (is_add) { 4105 i40e_fill_default_direct_cmd_desc(&desc, 4106 i40e_aqc_opc_add_control_packet_filter); 4107 cmd->queue = cpu_to_le16(queue); 4108 } else { 4109 i40e_fill_default_direct_cmd_desc(&desc, 4110 i40e_aqc_opc_remove_control_packet_filter); 4111 } 4112 4113 if (mac_addr) 4114 ether_addr_copy(cmd->mac, mac_addr); 4115 4116 cmd->etype = cpu_to_le16(ethtype); 4117 cmd->flags = cpu_to_le16(flags); 4118 cmd->seid = cpu_to_le16(vsi_seid); 4119 4120 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4121 4122 if (!status && stats) { 4123 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4124 stats->etype_used = le16_to_cpu(resp->etype_used); 4125 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4126 stats->etype_free = le16_to_cpu(resp->etype_free); 4127 } 4128 4129 return status; 4130 } 4131 4132 /** 4133 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4134 * @hw: pointer to the hw struct 4135 * @seid: VSI seid to add ethertype filter from 4136 **/ 4137 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4138 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4139 u16 seid) 4140 { 4141 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4142 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4143 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4144 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4145 i40e_status status; 4146 4147 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4148 seid, 0, true, NULL, 4149 NULL); 4150 if (status) 4151 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4152 } 4153 4154 /** 4155 * i40e_aq_alternate_read 4156 * @hw: pointer to the hardware structure 4157 * @reg_addr0: address of first dword to be read 4158 * @reg_val0: pointer for data read from 'reg_addr0' 4159 * @reg_addr1: address of second dword to be read 4160 * @reg_val1: pointer for data read from 'reg_addr1' 4161 * 4162 * Read one or two dwords from alternate structure. Fields are indicated 4163 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4164 * is not passed then only register at 'reg_addr0' is read. 4165 * 4166 **/ 4167 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4168 u32 reg_addr0, u32 *reg_val0, 4169 u32 reg_addr1, u32 *reg_val1) 4170 { 4171 struct i40e_aq_desc desc; 4172 struct i40e_aqc_alternate_write *cmd_resp = 4173 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4174 i40e_status status; 4175 4176 if (!reg_val0) 4177 return I40E_ERR_PARAM; 4178 4179 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4180 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4181 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4182 4183 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4184 4185 if (!status) { 4186 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4187 4188 if (reg_val1) 4189 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4190 } 4191 4192 return status; 4193 } 4194 4195 /** 4196 * i40e_aq_resume_port_tx 4197 * @hw: pointer to the hardware structure 4198 * @cmd_details: pointer to command details structure or NULL 4199 * 4200 * Resume port's Tx traffic 4201 **/ 4202 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4203 struct i40e_asq_cmd_details *cmd_details) 4204 { 4205 struct i40e_aq_desc desc; 4206 i40e_status status; 4207 4208 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4209 4210 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4211 4212 return status; 4213 } 4214 4215 /** 4216 * i40e_set_pci_config_data - store PCI bus info 4217 * @hw: pointer to hardware structure 4218 * @link_status: the link status word from PCI config space 4219 * 4220 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4221 **/ 4222 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4223 { 4224 hw->bus.type = i40e_bus_type_pci_express; 4225 4226 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4227 case PCI_EXP_LNKSTA_NLW_X1: 4228 hw->bus.width = i40e_bus_width_pcie_x1; 4229 break; 4230 case PCI_EXP_LNKSTA_NLW_X2: 4231 hw->bus.width = i40e_bus_width_pcie_x2; 4232 break; 4233 case PCI_EXP_LNKSTA_NLW_X4: 4234 hw->bus.width = i40e_bus_width_pcie_x4; 4235 break; 4236 case PCI_EXP_LNKSTA_NLW_X8: 4237 hw->bus.width = i40e_bus_width_pcie_x8; 4238 break; 4239 default: 4240 hw->bus.width = i40e_bus_width_unknown; 4241 break; 4242 } 4243 4244 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4245 case PCI_EXP_LNKSTA_CLS_2_5GB: 4246 hw->bus.speed = i40e_bus_speed_2500; 4247 break; 4248 case PCI_EXP_LNKSTA_CLS_5_0GB: 4249 hw->bus.speed = i40e_bus_speed_5000; 4250 break; 4251 case PCI_EXP_LNKSTA_CLS_8_0GB: 4252 hw->bus.speed = i40e_bus_speed_8000; 4253 break; 4254 default: 4255 hw->bus.speed = i40e_bus_speed_unknown; 4256 break; 4257 } 4258 } 4259 4260 /** 4261 * i40e_aq_debug_dump 4262 * @hw: pointer to the hardware structure 4263 * @cluster_id: specific cluster to dump 4264 * @table_id: table id within cluster 4265 * @start_index: index of line in the block to read 4266 * @buff_size: dump buffer size 4267 * @buff: dump buffer 4268 * @ret_buff_size: actual buffer size returned 4269 * @ret_next_table: next block to read 4270 * @ret_next_index: next index to read 4271 * 4272 * Dump internal FW/HW data for debug purposes. 4273 * 4274 **/ 4275 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4276 u8 table_id, u32 start_index, u16 buff_size, 4277 void *buff, u16 *ret_buff_size, 4278 u8 *ret_next_table, u32 *ret_next_index, 4279 struct i40e_asq_cmd_details *cmd_details) 4280 { 4281 struct i40e_aq_desc desc; 4282 struct i40e_aqc_debug_dump_internals *cmd = 4283 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4284 struct i40e_aqc_debug_dump_internals *resp = 4285 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4286 i40e_status status; 4287 4288 if (buff_size == 0 || !buff) 4289 return I40E_ERR_PARAM; 4290 4291 i40e_fill_default_direct_cmd_desc(&desc, 4292 i40e_aqc_opc_debug_dump_internals); 4293 /* Indirect Command */ 4294 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4295 if (buff_size > I40E_AQ_LARGE_BUF) 4296 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4297 4298 cmd->cluster_id = cluster_id; 4299 cmd->table_id = table_id; 4300 cmd->idx = cpu_to_le32(start_index); 4301 4302 desc.datalen = cpu_to_le16(buff_size); 4303 4304 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4305 if (!status) { 4306 if (ret_buff_size) 4307 *ret_buff_size = le16_to_cpu(desc.datalen); 4308 if (ret_next_table) 4309 *ret_next_table = resp->table_id; 4310 if (ret_next_index) 4311 *ret_next_index = le32_to_cpu(resp->idx); 4312 } 4313 4314 return status; 4315 } 4316 4317 /** 4318 * i40e_read_bw_from_alt_ram 4319 * @hw: pointer to the hardware structure 4320 * @max_bw: pointer for max_bw read 4321 * @min_bw: pointer for min_bw read 4322 * @min_valid: pointer for bool that is true if min_bw is a valid value 4323 * @max_valid: pointer for bool that is true if max_bw is a valid value 4324 * 4325 * Read bw from the alternate ram for the given pf 4326 **/ 4327 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4328 u32 *max_bw, u32 *min_bw, 4329 bool *min_valid, bool *max_valid) 4330 { 4331 i40e_status status; 4332 u32 max_bw_addr, min_bw_addr; 4333 4334 /* Calculate the address of the min/max bw registers */ 4335 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4336 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4337 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4338 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4339 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4340 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4341 4342 /* Read the bandwidths from alt ram */ 4343 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4344 min_bw_addr, min_bw); 4345 4346 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4347 *min_valid = true; 4348 else 4349 *min_valid = false; 4350 4351 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4352 *max_valid = true; 4353 else 4354 *max_valid = false; 4355 4356 return status; 4357 } 4358 4359 /** 4360 * i40e_aq_configure_partition_bw 4361 * @hw: pointer to the hardware structure 4362 * @bw_data: Buffer holding valid pfs and bw limits 4363 * @cmd_details: pointer to command details 4364 * 4365 * Configure partitions guaranteed/max bw 4366 **/ 4367 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4368 struct i40e_aqc_configure_partition_bw_data *bw_data, 4369 struct i40e_asq_cmd_details *cmd_details) 4370 { 4371 i40e_status status; 4372 struct i40e_aq_desc desc; 4373 u16 bwd_size = sizeof(*bw_data); 4374 4375 i40e_fill_default_direct_cmd_desc(&desc, 4376 i40e_aqc_opc_configure_partition_bw); 4377 4378 /* Indirect command */ 4379 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4380 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4381 4382 if (bwd_size > I40E_AQ_LARGE_BUF) 4383 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4384 4385 desc.datalen = cpu_to_le16(bwd_size); 4386 4387 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4388 cmd_details); 4389 4390 return status; 4391 } 4392 4393 /** 4394 * i40e_read_phy_register 4395 * @hw: pointer to the HW structure 4396 * @page: registers page number 4397 * @reg: register address in the page 4398 * @phy_adr: PHY address on MDIO interface 4399 * @value: PHY register value 4400 * 4401 * Reads specified PHY register value 4402 **/ 4403 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4404 u8 page, u16 reg, u8 phy_addr, 4405 u16 *value) 4406 { 4407 i40e_status status = I40E_ERR_TIMEOUT; 4408 u32 command = 0; 4409 u16 retry = 1000; 4410 u8 port_num = hw->func_caps.mdio_port_num; 4411 4412 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4413 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4414 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4415 (I40E_MDIO_OPCODE_ADDRESS) | 4416 (I40E_MDIO_STCODE) | 4417 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4418 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4419 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4420 do { 4421 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4422 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4423 status = 0; 4424 break; 4425 } 4426 usleep_range(10, 20); 4427 retry--; 4428 } while (retry); 4429 4430 if (status) { 4431 i40e_debug(hw, I40E_DEBUG_PHY, 4432 "PHY: Can't write command to external PHY.\n"); 4433 goto phy_read_end; 4434 } 4435 4436 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4437 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4438 (I40E_MDIO_OPCODE_READ) | 4439 (I40E_MDIO_STCODE) | 4440 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4441 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4442 status = I40E_ERR_TIMEOUT; 4443 retry = 1000; 4444 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4445 do { 4446 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4447 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4448 status = 0; 4449 break; 4450 } 4451 usleep_range(10, 20); 4452 retry--; 4453 } while (retry); 4454 4455 if (!status) { 4456 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4457 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4458 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4459 } else { 4460 i40e_debug(hw, I40E_DEBUG_PHY, 4461 "PHY: Can't read register value from external PHY.\n"); 4462 } 4463 4464 phy_read_end: 4465 return status; 4466 } 4467 4468 /** 4469 * i40e_write_phy_register 4470 * @hw: pointer to the HW structure 4471 * @page: registers page number 4472 * @reg: register address in the page 4473 * @phy_adr: PHY address on MDIO interface 4474 * @value: PHY register value 4475 * 4476 * Writes value to specified PHY register 4477 **/ 4478 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4479 u8 page, u16 reg, u8 phy_addr, 4480 u16 value) 4481 { 4482 i40e_status status = I40E_ERR_TIMEOUT; 4483 u32 command = 0; 4484 u16 retry = 1000; 4485 u8 port_num = hw->func_caps.mdio_port_num; 4486 4487 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4488 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4489 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4490 (I40E_MDIO_OPCODE_ADDRESS) | 4491 (I40E_MDIO_STCODE) | 4492 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4493 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4494 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4495 do { 4496 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4497 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4498 status = 0; 4499 break; 4500 } 4501 usleep_range(10, 20); 4502 retry--; 4503 } while (retry); 4504 if (status) { 4505 i40e_debug(hw, I40E_DEBUG_PHY, 4506 "PHY: Can't write command to external PHY.\n"); 4507 goto phy_write_end; 4508 } 4509 4510 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4511 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4512 4513 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4514 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4515 (I40E_MDIO_OPCODE_WRITE) | 4516 (I40E_MDIO_STCODE) | 4517 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4518 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4519 status = I40E_ERR_TIMEOUT; 4520 retry = 1000; 4521 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4522 do { 4523 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4524 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4525 status = 0; 4526 break; 4527 } 4528 usleep_range(10, 20); 4529 retry--; 4530 } while (retry); 4531 4532 phy_write_end: 4533 return status; 4534 } 4535 4536 /** 4537 * i40e_get_phy_address 4538 * @hw: pointer to the HW structure 4539 * @dev_num: PHY port num that address we want 4540 * @phy_addr: Returned PHY address 4541 * 4542 * Gets PHY address for current port 4543 **/ 4544 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4545 { 4546 u8 port_num = hw->func_caps.mdio_port_num; 4547 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4548 4549 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4550 } 4551 4552 /** 4553 * i40e_blink_phy_led 4554 * @hw: pointer to the HW structure 4555 * @time: time how long led will blinks in secs 4556 * @interval: gap between LED on and off in msecs 4557 * 4558 * Blinks PHY link LED 4559 **/ 4560 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4561 u32 time, u32 interval) 4562 { 4563 i40e_status status = 0; 4564 u32 i; 4565 u16 led_ctl; 4566 u16 gpio_led_port; 4567 u16 led_reg; 4568 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4569 u8 phy_addr = 0; 4570 u8 port_num; 4571 4572 i = rd32(hw, I40E_PFGEN_PORTNUM); 4573 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4574 phy_addr = i40e_get_phy_address(hw, port_num); 4575 4576 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4577 led_addr++) { 4578 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 4579 led_addr, phy_addr, &led_reg); 4580 if (status) 4581 goto phy_blinking_end; 4582 led_ctl = led_reg; 4583 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4584 led_reg = 0; 4585 status = i40e_write_phy_register(hw, 4586 I40E_PHY_COM_REG_PAGE, 4587 led_addr, phy_addr, 4588 led_reg); 4589 if (status) 4590 goto phy_blinking_end; 4591 break; 4592 } 4593 } 4594 4595 if (time > 0 && interval > 0) { 4596 for (i = 0; i < time * 1000; i += interval) { 4597 status = i40e_read_phy_register(hw, 4598 I40E_PHY_COM_REG_PAGE, 4599 led_addr, phy_addr, 4600 &led_reg); 4601 if (status) 4602 goto restore_config; 4603 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4604 led_reg = 0; 4605 else 4606 led_reg = I40E_PHY_LED_MANUAL_ON; 4607 status = i40e_write_phy_register(hw, 4608 I40E_PHY_COM_REG_PAGE, 4609 led_addr, phy_addr, 4610 led_reg); 4611 if (status) 4612 goto restore_config; 4613 msleep(interval); 4614 } 4615 } 4616 4617 restore_config: 4618 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 4619 phy_addr, led_ctl); 4620 4621 phy_blinking_end: 4622 return status; 4623 } 4624 4625 /** 4626 * i40e_led_get_phy - return current on/off mode 4627 * @hw: pointer to the hw struct 4628 * @led_addr: address of led register to use 4629 * @val: original value of register to use 4630 * 4631 **/ 4632 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4633 u16 *val) 4634 { 4635 i40e_status status = 0; 4636 u16 gpio_led_port; 4637 u8 phy_addr = 0; 4638 u16 reg_val; 4639 u16 temp_addr; 4640 u8 port_num; 4641 u32 i; 4642 4643 temp_addr = I40E_PHY_LED_PROV_REG_1; 4644 i = rd32(hw, I40E_PFGEN_PORTNUM); 4645 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4646 phy_addr = i40e_get_phy_address(hw, port_num); 4647 4648 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4649 temp_addr++) { 4650 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 4651 temp_addr, phy_addr, ®_val); 4652 if (status) 4653 return status; 4654 *val = reg_val; 4655 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4656 *led_addr = temp_addr; 4657 break; 4658 } 4659 } 4660 return status; 4661 } 4662 4663 /** 4664 * i40e_led_set_phy 4665 * @hw: pointer to the HW structure 4666 * @on: true or false 4667 * @mode: original val plus bit for set or ignore 4668 * Set led's on or off when controlled by the PHY 4669 * 4670 **/ 4671 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4672 u16 led_addr, u32 mode) 4673 { 4674 i40e_status status = 0; 4675 u16 led_ctl = 0; 4676 u16 led_reg = 0; 4677 u8 phy_addr = 0; 4678 u8 port_num; 4679 u32 i; 4680 4681 i = rd32(hw, I40E_PFGEN_PORTNUM); 4682 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4683 phy_addr = i40e_get_phy_address(hw, port_num); 4684 4685 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 4686 phy_addr, &led_reg); 4687 if (status) 4688 return status; 4689 led_ctl = led_reg; 4690 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4691 led_reg = 0; 4692 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, 4693 led_addr, phy_addr, led_reg); 4694 if (status) 4695 return status; 4696 } 4697 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, 4698 led_addr, phy_addr, &led_reg); 4699 if (status) 4700 goto restore_config; 4701 if (on) 4702 led_reg = I40E_PHY_LED_MANUAL_ON; 4703 else 4704 led_reg = 0; 4705 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, 4706 led_addr, phy_addr, led_reg); 4707 if (status) 4708 goto restore_config; 4709 if (mode & I40E_PHY_LED_MODE_ORIG) { 4710 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 4711 status = i40e_write_phy_register(hw, 4712 I40E_PHY_COM_REG_PAGE, 4713 led_addr, phy_addr, led_ctl); 4714 } 4715 return status; 4716 restore_config: 4717 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr, 4718 phy_addr, led_ctl); 4719 return status; 4720 } 4721 4722 /** 4723 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 4724 * @hw: pointer to the hw struct 4725 * @reg_addr: register address 4726 * @reg_val: ptr to register value 4727 * @cmd_details: pointer to command details structure or NULL 4728 * 4729 * Use the firmware to read the Rx control register, 4730 * especially useful if the Rx unit is under heavy pressure 4731 **/ 4732 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 4733 u32 reg_addr, u32 *reg_val, 4734 struct i40e_asq_cmd_details *cmd_details) 4735 { 4736 struct i40e_aq_desc desc; 4737 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 4738 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4739 i40e_status status; 4740 4741 if (!reg_val) 4742 return I40E_ERR_PARAM; 4743 4744 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 4745 4746 cmd_resp->address = cpu_to_le32(reg_addr); 4747 4748 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4749 4750 if (status == 0) 4751 *reg_val = le32_to_cpu(cmd_resp->value); 4752 4753 return status; 4754 } 4755 4756 /** 4757 * i40e_read_rx_ctl - read from an Rx control register 4758 * @hw: pointer to the hw struct 4759 * @reg_addr: register address 4760 **/ 4761 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 4762 { 4763 i40e_status status = 0; 4764 bool use_register; 4765 int retry = 5; 4766 u32 val = 0; 4767 4768 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 4769 if (!use_register) { 4770 do_retry: 4771 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 4772 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4773 usleep_range(1000, 2000); 4774 retry--; 4775 goto do_retry; 4776 } 4777 } 4778 4779 /* if the AQ access failed, try the old-fashioned way */ 4780 if (status || use_register) 4781 val = rd32(hw, reg_addr); 4782 4783 return val; 4784 } 4785 4786 /** 4787 * i40e_aq_rx_ctl_write_register 4788 * @hw: pointer to the hw struct 4789 * @reg_addr: register address 4790 * @reg_val: register value 4791 * @cmd_details: pointer to command details structure or NULL 4792 * 4793 * Use the firmware to write to an Rx control register, 4794 * especially useful if the Rx unit is under heavy pressure 4795 **/ 4796 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 4797 u32 reg_addr, u32 reg_val, 4798 struct i40e_asq_cmd_details *cmd_details) 4799 { 4800 struct i40e_aq_desc desc; 4801 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 4802 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 4803 i40e_status status; 4804 4805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 4806 4807 cmd->address = cpu_to_le32(reg_addr); 4808 cmd->value = cpu_to_le32(reg_val); 4809 4810 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4811 4812 return status; 4813 } 4814 4815 /** 4816 * i40e_write_rx_ctl - write to an Rx control register 4817 * @hw: pointer to the hw struct 4818 * @reg_addr: register address 4819 * @reg_val: register value 4820 **/ 4821 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 4822 { 4823 i40e_status status = 0; 4824 bool use_register; 4825 int retry = 5; 4826 4827 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 4828 if (!use_register) { 4829 do_retry: 4830 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 4831 reg_val, NULL); 4832 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 4833 usleep_range(1000, 2000); 4834 retry--; 4835 goto do_retry; 4836 } 4837 } 4838 4839 /* if the AQ access failed, try the old-fashioned way */ 4840 if (status || use_register) 4841 wr32(hw, reg_addr, reg_val); 4842 } 4843