1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_type.h" 28 #include "i40e_adminq.h" 29 #include "i40e_prototype.h" 30 #include <linux/avf/virtchnl.h> 31 32 /** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40 { 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_B: 48 case I40E_DEV_ID_KX_C: 49 case I40E_DEV_ID_QSFP_A: 50 case I40E_DEV_ID_QSFP_B: 51 case I40E_DEV_ID_QSFP_C: 52 case I40E_DEV_ID_10G_BASE_T: 53 case I40E_DEV_ID_10G_BASE_T4: 54 case I40E_DEV_ID_20G_KR2: 55 case I40E_DEV_ID_20G_KR2_A: 56 case I40E_DEV_ID_25G_B: 57 case I40E_DEV_ID_25G_SFP28: 58 hw->mac.type = I40E_MAC_XL710; 59 break; 60 case I40E_DEV_ID_KX_X722: 61 case I40E_DEV_ID_QSFP_X722: 62 case I40E_DEV_ID_SFP_X722: 63 case I40E_DEV_ID_1G_BASE_T_X722: 64 case I40E_DEV_ID_10G_BASE_T_X722: 65 case I40E_DEV_ID_SFP_I_X722: 66 hw->mac.type = I40E_MAC_X722; 67 break; 68 default: 69 hw->mac.type = I40E_MAC_GENERIC; 70 break; 71 } 72 } else { 73 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 74 } 75 76 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 77 hw->mac.type, status); 78 return status; 79 } 80 81 /** 82 * i40e_aq_str - convert AQ err code to a string 83 * @hw: pointer to the HW structure 84 * @aq_err: the AQ error code to convert 85 **/ 86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 87 { 88 switch (aq_err) { 89 case I40E_AQ_RC_OK: 90 return "OK"; 91 case I40E_AQ_RC_EPERM: 92 return "I40E_AQ_RC_EPERM"; 93 case I40E_AQ_RC_ENOENT: 94 return "I40E_AQ_RC_ENOENT"; 95 case I40E_AQ_RC_ESRCH: 96 return "I40E_AQ_RC_ESRCH"; 97 case I40E_AQ_RC_EINTR: 98 return "I40E_AQ_RC_EINTR"; 99 case I40E_AQ_RC_EIO: 100 return "I40E_AQ_RC_EIO"; 101 case I40E_AQ_RC_ENXIO: 102 return "I40E_AQ_RC_ENXIO"; 103 case I40E_AQ_RC_E2BIG: 104 return "I40E_AQ_RC_E2BIG"; 105 case I40E_AQ_RC_EAGAIN: 106 return "I40E_AQ_RC_EAGAIN"; 107 case I40E_AQ_RC_ENOMEM: 108 return "I40E_AQ_RC_ENOMEM"; 109 case I40E_AQ_RC_EACCES: 110 return "I40E_AQ_RC_EACCES"; 111 case I40E_AQ_RC_EFAULT: 112 return "I40E_AQ_RC_EFAULT"; 113 case I40E_AQ_RC_EBUSY: 114 return "I40E_AQ_RC_EBUSY"; 115 case I40E_AQ_RC_EEXIST: 116 return "I40E_AQ_RC_EEXIST"; 117 case I40E_AQ_RC_EINVAL: 118 return "I40E_AQ_RC_EINVAL"; 119 case I40E_AQ_RC_ENOTTY: 120 return "I40E_AQ_RC_ENOTTY"; 121 case I40E_AQ_RC_ENOSPC: 122 return "I40E_AQ_RC_ENOSPC"; 123 case I40E_AQ_RC_ENOSYS: 124 return "I40E_AQ_RC_ENOSYS"; 125 case I40E_AQ_RC_ERANGE: 126 return "I40E_AQ_RC_ERANGE"; 127 case I40E_AQ_RC_EFLUSHED: 128 return "I40E_AQ_RC_EFLUSHED"; 129 case I40E_AQ_RC_BAD_ADDR: 130 return "I40E_AQ_RC_BAD_ADDR"; 131 case I40E_AQ_RC_EMODE: 132 return "I40E_AQ_RC_EMODE"; 133 case I40E_AQ_RC_EFBIG: 134 return "I40E_AQ_RC_EFBIG"; 135 } 136 137 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 138 return hw->err_str; 139 } 140 141 /** 142 * i40e_stat_str - convert status err code to a string 143 * @hw: pointer to the HW structure 144 * @stat_err: the status error code to convert 145 **/ 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 147 { 148 switch (stat_err) { 149 case 0: 150 return "OK"; 151 case I40E_ERR_NVM: 152 return "I40E_ERR_NVM"; 153 case I40E_ERR_NVM_CHECKSUM: 154 return "I40E_ERR_NVM_CHECKSUM"; 155 case I40E_ERR_PHY: 156 return "I40E_ERR_PHY"; 157 case I40E_ERR_CONFIG: 158 return "I40E_ERR_CONFIG"; 159 case I40E_ERR_PARAM: 160 return "I40E_ERR_PARAM"; 161 case I40E_ERR_MAC_TYPE: 162 return "I40E_ERR_MAC_TYPE"; 163 case I40E_ERR_UNKNOWN_PHY: 164 return "I40E_ERR_UNKNOWN_PHY"; 165 case I40E_ERR_LINK_SETUP: 166 return "I40E_ERR_LINK_SETUP"; 167 case I40E_ERR_ADAPTER_STOPPED: 168 return "I40E_ERR_ADAPTER_STOPPED"; 169 case I40E_ERR_INVALID_MAC_ADDR: 170 return "I40E_ERR_INVALID_MAC_ADDR"; 171 case I40E_ERR_DEVICE_NOT_SUPPORTED: 172 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 173 case I40E_ERR_MASTER_REQUESTS_PENDING: 174 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 175 case I40E_ERR_INVALID_LINK_SETTINGS: 176 return "I40E_ERR_INVALID_LINK_SETTINGS"; 177 case I40E_ERR_AUTONEG_NOT_COMPLETE: 178 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 179 case I40E_ERR_RESET_FAILED: 180 return "I40E_ERR_RESET_FAILED"; 181 case I40E_ERR_SWFW_SYNC: 182 return "I40E_ERR_SWFW_SYNC"; 183 case I40E_ERR_NO_AVAILABLE_VSI: 184 return "I40E_ERR_NO_AVAILABLE_VSI"; 185 case I40E_ERR_NO_MEMORY: 186 return "I40E_ERR_NO_MEMORY"; 187 case I40E_ERR_BAD_PTR: 188 return "I40E_ERR_BAD_PTR"; 189 case I40E_ERR_RING_FULL: 190 return "I40E_ERR_RING_FULL"; 191 case I40E_ERR_INVALID_PD_ID: 192 return "I40E_ERR_INVALID_PD_ID"; 193 case I40E_ERR_INVALID_QP_ID: 194 return "I40E_ERR_INVALID_QP_ID"; 195 case I40E_ERR_INVALID_CQ_ID: 196 return "I40E_ERR_INVALID_CQ_ID"; 197 case I40E_ERR_INVALID_CEQ_ID: 198 return "I40E_ERR_INVALID_CEQ_ID"; 199 case I40E_ERR_INVALID_AEQ_ID: 200 return "I40E_ERR_INVALID_AEQ_ID"; 201 case I40E_ERR_INVALID_SIZE: 202 return "I40E_ERR_INVALID_SIZE"; 203 case I40E_ERR_INVALID_ARP_INDEX: 204 return "I40E_ERR_INVALID_ARP_INDEX"; 205 case I40E_ERR_INVALID_FPM_FUNC_ID: 206 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 207 case I40E_ERR_QP_INVALID_MSG_SIZE: 208 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 209 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 210 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 211 case I40E_ERR_INVALID_FRAG_COUNT: 212 return "I40E_ERR_INVALID_FRAG_COUNT"; 213 case I40E_ERR_QUEUE_EMPTY: 214 return "I40E_ERR_QUEUE_EMPTY"; 215 case I40E_ERR_INVALID_ALIGNMENT: 216 return "I40E_ERR_INVALID_ALIGNMENT"; 217 case I40E_ERR_FLUSHED_QUEUE: 218 return "I40E_ERR_FLUSHED_QUEUE"; 219 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 220 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 221 case I40E_ERR_INVALID_IMM_DATA_SIZE: 222 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 223 case I40E_ERR_TIMEOUT: 224 return "I40E_ERR_TIMEOUT"; 225 case I40E_ERR_OPCODE_MISMATCH: 226 return "I40E_ERR_OPCODE_MISMATCH"; 227 case I40E_ERR_CQP_COMPL_ERROR: 228 return "I40E_ERR_CQP_COMPL_ERROR"; 229 case I40E_ERR_INVALID_VF_ID: 230 return "I40E_ERR_INVALID_VF_ID"; 231 case I40E_ERR_INVALID_HMCFN_ID: 232 return "I40E_ERR_INVALID_HMCFN_ID"; 233 case I40E_ERR_BACKING_PAGE_ERROR: 234 return "I40E_ERR_BACKING_PAGE_ERROR"; 235 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 236 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 237 case I40E_ERR_INVALID_PBLE_INDEX: 238 return "I40E_ERR_INVALID_PBLE_INDEX"; 239 case I40E_ERR_INVALID_SD_INDEX: 240 return "I40E_ERR_INVALID_SD_INDEX"; 241 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 242 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 243 case I40E_ERR_INVALID_SD_TYPE: 244 return "I40E_ERR_INVALID_SD_TYPE"; 245 case I40E_ERR_MEMCPY_FAILED: 246 return "I40E_ERR_MEMCPY_FAILED"; 247 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 248 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 249 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 250 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 251 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 252 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 253 case I40E_ERR_SRQ_ENABLED: 254 return "I40E_ERR_SRQ_ENABLED"; 255 case I40E_ERR_ADMIN_QUEUE_ERROR: 256 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 257 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 258 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 259 case I40E_ERR_BUF_TOO_SHORT: 260 return "I40E_ERR_BUF_TOO_SHORT"; 261 case I40E_ERR_ADMIN_QUEUE_FULL: 262 return "I40E_ERR_ADMIN_QUEUE_FULL"; 263 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 264 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 265 case I40E_ERR_BAD_IWARP_CQE: 266 return "I40E_ERR_BAD_IWARP_CQE"; 267 case I40E_ERR_NVM_BLANK_MODE: 268 return "I40E_ERR_NVM_BLANK_MODE"; 269 case I40E_ERR_NOT_IMPLEMENTED: 270 return "I40E_ERR_NOT_IMPLEMENTED"; 271 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 272 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 273 case I40E_ERR_DIAG_TEST_FAILED: 274 return "I40E_ERR_DIAG_TEST_FAILED"; 275 case I40E_ERR_NOT_READY: 276 return "I40E_ERR_NOT_READY"; 277 case I40E_NOT_SUPPORTED: 278 return "I40E_NOT_SUPPORTED"; 279 case I40E_ERR_FIRMWARE_API_VERSION: 280 return "I40E_ERR_FIRMWARE_API_VERSION"; 281 } 282 283 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 284 return hw->err_str; 285 } 286 287 /** 288 * i40e_debug_aq 289 * @hw: debug mask related to admin queue 290 * @mask: debug mask 291 * @desc: pointer to admin queue descriptor 292 * @buffer: pointer to command buffer 293 * @buf_len: max length of buffer 294 * 295 * Dumps debug log about adminq command with descriptor contents. 296 **/ 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 298 void *buffer, u16 buf_len) 299 { 300 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 301 u16 len; 302 u8 *buf = (u8 *)buffer; 303 304 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 305 return; 306 307 len = le16_to_cpu(aq_desc->datalen); 308 309 i40e_debug(hw, mask, 310 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 311 le16_to_cpu(aq_desc->opcode), 312 le16_to_cpu(aq_desc->flags), 313 le16_to_cpu(aq_desc->datalen), 314 le16_to_cpu(aq_desc->retval)); 315 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 316 le32_to_cpu(aq_desc->cookie_high), 317 le32_to_cpu(aq_desc->cookie_low)); 318 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 319 le32_to_cpu(aq_desc->params.internal.param0), 320 le32_to_cpu(aq_desc->params.internal.param1)); 321 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 322 le32_to_cpu(aq_desc->params.external.addr_high), 323 le32_to_cpu(aq_desc->params.external.addr_low)); 324 325 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 326 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 327 if (buf_len < len) 328 len = buf_len; 329 /* write the full 16-byte chunks */ 330 if (hw->debug_mask & mask) { 331 char prefix[27]; 332 333 snprintf(prefix, sizeof(prefix), 334 "i40e %02x:%02x.%x: \t0x", 335 hw->bus.bus_id, 336 hw->bus.device, 337 hw->bus.func); 338 339 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 340 16, 1, buf, len, false); 341 } 342 } 343 } 344 345 /** 346 * i40e_check_asq_alive 347 * @hw: pointer to the hw struct 348 * 349 * Returns true if Queue is enabled else false. 350 **/ 351 bool i40e_check_asq_alive(struct i40e_hw *hw) 352 { 353 if (hw->aq.asq.len) 354 return !!(rd32(hw, hw->aq.asq.len) & 355 I40E_PF_ATQLEN_ATQENABLE_MASK); 356 else 357 return false; 358 } 359 360 /** 361 * i40e_aq_queue_shutdown 362 * @hw: pointer to the hw struct 363 * @unloading: is the driver unloading itself 364 * 365 * Tell the Firmware that we're shutting down the AdminQ and whether 366 * or not the driver is unloading as well. 367 **/ 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 369 bool unloading) 370 { 371 struct i40e_aq_desc desc; 372 struct i40e_aqc_queue_shutdown *cmd = 373 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 374 i40e_status status; 375 376 i40e_fill_default_direct_cmd_desc(&desc, 377 i40e_aqc_opc_queue_shutdown); 378 379 if (unloading) 380 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 381 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 382 383 return status; 384 } 385 386 /** 387 * i40e_aq_get_set_rss_lut 388 * @hw: pointer to the hardware structure 389 * @vsi_id: vsi fw index 390 * @pf_lut: for PF table set true, for VSI table set false 391 * @lut: pointer to the lut buffer provided by the caller 392 * @lut_size: size of the lut buffer 393 * @set: set true to set the table, false to get the table 394 * 395 * Internal function to get or set RSS look up table 396 **/ 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 398 u16 vsi_id, bool pf_lut, 399 u8 *lut, u16 lut_size, 400 bool set) 401 { 402 i40e_status status; 403 struct i40e_aq_desc desc; 404 struct i40e_aqc_get_set_rss_lut *cmd_resp = 405 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 406 407 if (set) 408 i40e_fill_default_direct_cmd_desc(&desc, 409 i40e_aqc_opc_set_rss_lut); 410 else 411 i40e_fill_default_direct_cmd_desc(&desc, 412 i40e_aqc_opc_get_rss_lut); 413 414 /* Indirect command */ 415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 416 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 417 418 cmd_resp->vsi_id = 419 cpu_to_le16((u16)((vsi_id << 420 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 421 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 422 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 423 424 if (pf_lut) 425 cmd_resp->flags |= cpu_to_le16((u16) 426 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 428 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 429 else 430 cmd_resp->flags |= cpu_to_le16((u16) 431 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 432 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 433 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 434 435 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 436 437 return status; 438 } 439 440 /** 441 * i40e_aq_get_rss_lut 442 * @hw: pointer to the hardware structure 443 * @vsi_id: vsi fw index 444 * @pf_lut: for PF table set true, for VSI table set false 445 * @lut: pointer to the lut buffer provided by the caller 446 * @lut_size: size of the lut buffer 447 * 448 * get the RSS lookup table, PF or VSI type 449 **/ 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 451 bool pf_lut, u8 *lut, u16 lut_size) 452 { 453 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 454 false); 455 } 456 457 /** 458 * i40e_aq_set_rss_lut 459 * @hw: pointer to the hardware structure 460 * @vsi_id: vsi fw index 461 * @pf_lut: for PF table set true, for VSI table set false 462 * @lut: pointer to the lut buffer provided by the caller 463 * @lut_size: size of the lut buffer 464 * 465 * set the RSS lookup table, PF or VSI type 466 **/ 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 468 bool pf_lut, u8 *lut, u16 lut_size) 469 { 470 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 471 } 472 473 /** 474 * i40e_aq_get_set_rss_key 475 * @hw: pointer to the hw struct 476 * @vsi_id: vsi fw index 477 * @key: pointer to key info struct 478 * @set: set true to set the key, false to get the key 479 * 480 * get the RSS key per VSI 481 **/ 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 483 u16 vsi_id, 484 struct i40e_aqc_get_set_rss_key_data *key, 485 bool set) 486 { 487 i40e_status status; 488 struct i40e_aq_desc desc; 489 struct i40e_aqc_get_set_rss_key *cmd_resp = 490 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 491 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 492 493 if (set) 494 i40e_fill_default_direct_cmd_desc(&desc, 495 i40e_aqc_opc_set_rss_key); 496 else 497 i40e_fill_default_direct_cmd_desc(&desc, 498 i40e_aqc_opc_get_rss_key); 499 500 /* Indirect command */ 501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 503 504 cmd_resp->vsi_id = 505 cpu_to_le16((u16)((vsi_id << 506 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 507 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 508 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 509 510 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 511 512 return status; 513 } 514 515 /** 516 * i40e_aq_get_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 **/ 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 523 u16 vsi_id, 524 struct i40e_aqc_get_set_rss_key_data *key) 525 { 526 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 527 } 528 529 /** 530 * i40e_aq_set_rss_key 531 * @hw: pointer to the hw struct 532 * @vsi_id: vsi fw index 533 * @key: pointer to key info struct 534 * 535 * set the RSS key per VSI 536 **/ 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 538 u16 vsi_id, 539 struct i40e_aqc_get_set_rss_key_data *key) 540 { 541 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 542 } 543 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 545 * hardware to a bit-field that can be used by SW to more easily determine the 546 * packet type. 547 * 548 * Macros are used to shorten the table lines and make this table human 549 * readable. 550 * 551 * We store the PTYPE in the top byte of the bit field - this is just so that 552 * we can check that the table doesn't have a row missing, as the index into 553 * the table should be the PTYPE. 554 * 555 * Typical work flow: 556 * 557 * IF NOT i40e_ptype_lookup[ptype].known 558 * THEN 559 * Packet is unknown 560 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 561 * Use the rest of the fields to look at the tunnels, inner protocols, etc 562 * ELSE 563 * Use the enum i40e_rx_l2_ptype to decode the packet type 564 * ENDIF 565 */ 566 567 /* macro to make the table lines short */ 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 569 { PTYPE, \ 570 1, \ 571 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 572 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 573 I40E_RX_PTYPE_##OUTER_FRAG, \ 574 I40E_RX_PTYPE_TUNNEL_##T, \ 575 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 576 I40E_RX_PTYPE_##TEF, \ 577 I40E_RX_PTYPE_INNER_PROT_##I, \ 578 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 579 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 581 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 582 583 /* shorter macros makes the table fit but are terse */ 584 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 585 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 586 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 587 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 590 /* L2 Packet types */ 591 I40E_PTT_UNUSED_ENTRY(0), 592 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 593 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 594 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 595 I40E_PTT_UNUSED_ENTRY(4), 596 I40E_PTT_UNUSED_ENTRY(5), 597 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 598 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 599 I40E_PTT_UNUSED_ENTRY(8), 600 I40E_PTT_UNUSED_ENTRY(9), 601 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 602 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 603 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 604 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 605 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 606 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 607 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 608 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 609 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 610 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 611 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 612 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 613 614 /* Non Tunneled IPv4 */ 615 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 616 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 617 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 618 I40E_PTT_UNUSED_ENTRY(25), 619 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 620 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 621 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 622 623 /* IPv4 --> IPv4 */ 624 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 625 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 626 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 627 I40E_PTT_UNUSED_ENTRY(32), 628 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 629 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 630 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 631 632 /* IPv4 --> IPv6 */ 633 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 634 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 635 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 636 I40E_PTT_UNUSED_ENTRY(39), 637 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 638 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 639 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 640 641 /* IPv4 --> GRE/NAT */ 642 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 643 644 /* IPv4 --> GRE/NAT --> IPv4 */ 645 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(47), 649 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> GRE/NAT --> IPv6 */ 654 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(54), 658 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT --> MAC */ 663 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 666 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(62), 670 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 675 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(69), 679 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 684 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 687 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(77), 691 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 696 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(84), 700 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 703 704 /* Non Tunneled IPv6 */ 705 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 706 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 707 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 708 I40E_PTT_UNUSED_ENTRY(91), 709 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 710 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 711 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 712 713 /* IPv6 --> IPv4 */ 714 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 715 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 716 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 717 I40E_PTT_UNUSED_ENTRY(98), 718 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 719 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 720 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 721 722 /* IPv6 --> IPv6 */ 723 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 724 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 725 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 726 I40E_PTT_UNUSED_ENTRY(105), 727 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 728 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 729 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 730 731 /* IPv6 --> GRE/NAT */ 732 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 733 734 /* IPv6 --> GRE/NAT -> IPv4 */ 735 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(113), 739 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> GRE/NAT -> IPv6 */ 744 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(120), 748 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT -> MAC */ 753 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 756 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(128), 760 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 765 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(135), 769 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 774 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 777 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(143), 781 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 786 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(150), 790 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 793 794 /* unused entries */ 795 I40E_PTT_UNUSED_ENTRY(154), 796 I40E_PTT_UNUSED_ENTRY(155), 797 I40E_PTT_UNUSED_ENTRY(156), 798 I40E_PTT_UNUSED_ENTRY(157), 799 I40E_PTT_UNUSED_ENTRY(158), 800 I40E_PTT_UNUSED_ENTRY(159), 801 802 I40E_PTT_UNUSED_ENTRY(160), 803 I40E_PTT_UNUSED_ENTRY(161), 804 I40E_PTT_UNUSED_ENTRY(162), 805 I40E_PTT_UNUSED_ENTRY(163), 806 I40E_PTT_UNUSED_ENTRY(164), 807 I40E_PTT_UNUSED_ENTRY(165), 808 I40E_PTT_UNUSED_ENTRY(166), 809 I40E_PTT_UNUSED_ENTRY(167), 810 I40E_PTT_UNUSED_ENTRY(168), 811 I40E_PTT_UNUSED_ENTRY(169), 812 813 I40E_PTT_UNUSED_ENTRY(170), 814 I40E_PTT_UNUSED_ENTRY(171), 815 I40E_PTT_UNUSED_ENTRY(172), 816 I40E_PTT_UNUSED_ENTRY(173), 817 I40E_PTT_UNUSED_ENTRY(174), 818 I40E_PTT_UNUSED_ENTRY(175), 819 I40E_PTT_UNUSED_ENTRY(176), 820 I40E_PTT_UNUSED_ENTRY(177), 821 I40E_PTT_UNUSED_ENTRY(178), 822 I40E_PTT_UNUSED_ENTRY(179), 823 824 I40E_PTT_UNUSED_ENTRY(180), 825 I40E_PTT_UNUSED_ENTRY(181), 826 I40E_PTT_UNUSED_ENTRY(182), 827 I40E_PTT_UNUSED_ENTRY(183), 828 I40E_PTT_UNUSED_ENTRY(184), 829 I40E_PTT_UNUSED_ENTRY(185), 830 I40E_PTT_UNUSED_ENTRY(186), 831 I40E_PTT_UNUSED_ENTRY(187), 832 I40E_PTT_UNUSED_ENTRY(188), 833 I40E_PTT_UNUSED_ENTRY(189), 834 835 I40E_PTT_UNUSED_ENTRY(190), 836 I40E_PTT_UNUSED_ENTRY(191), 837 I40E_PTT_UNUSED_ENTRY(192), 838 I40E_PTT_UNUSED_ENTRY(193), 839 I40E_PTT_UNUSED_ENTRY(194), 840 I40E_PTT_UNUSED_ENTRY(195), 841 I40E_PTT_UNUSED_ENTRY(196), 842 I40E_PTT_UNUSED_ENTRY(197), 843 I40E_PTT_UNUSED_ENTRY(198), 844 I40E_PTT_UNUSED_ENTRY(199), 845 846 I40E_PTT_UNUSED_ENTRY(200), 847 I40E_PTT_UNUSED_ENTRY(201), 848 I40E_PTT_UNUSED_ENTRY(202), 849 I40E_PTT_UNUSED_ENTRY(203), 850 I40E_PTT_UNUSED_ENTRY(204), 851 I40E_PTT_UNUSED_ENTRY(205), 852 I40E_PTT_UNUSED_ENTRY(206), 853 I40E_PTT_UNUSED_ENTRY(207), 854 I40E_PTT_UNUSED_ENTRY(208), 855 I40E_PTT_UNUSED_ENTRY(209), 856 857 I40E_PTT_UNUSED_ENTRY(210), 858 I40E_PTT_UNUSED_ENTRY(211), 859 I40E_PTT_UNUSED_ENTRY(212), 860 I40E_PTT_UNUSED_ENTRY(213), 861 I40E_PTT_UNUSED_ENTRY(214), 862 I40E_PTT_UNUSED_ENTRY(215), 863 I40E_PTT_UNUSED_ENTRY(216), 864 I40E_PTT_UNUSED_ENTRY(217), 865 I40E_PTT_UNUSED_ENTRY(218), 866 I40E_PTT_UNUSED_ENTRY(219), 867 868 I40E_PTT_UNUSED_ENTRY(220), 869 I40E_PTT_UNUSED_ENTRY(221), 870 I40E_PTT_UNUSED_ENTRY(222), 871 I40E_PTT_UNUSED_ENTRY(223), 872 I40E_PTT_UNUSED_ENTRY(224), 873 I40E_PTT_UNUSED_ENTRY(225), 874 I40E_PTT_UNUSED_ENTRY(226), 875 I40E_PTT_UNUSED_ENTRY(227), 876 I40E_PTT_UNUSED_ENTRY(228), 877 I40E_PTT_UNUSED_ENTRY(229), 878 879 I40E_PTT_UNUSED_ENTRY(230), 880 I40E_PTT_UNUSED_ENTRY(231), 881 I40E_PTT_UNUSED_ENTRY(232), 882 I40E_PTT_UNUSED_ENTRY(233), 883 I40E_PTT_UNUSED_ENTRY(234), 884 I40E_PTT_UNUSED_ENTRY(235), 885 I40E_PTT_UNUSED_ENTRY(236), 886 I40E_PTT_UNUSED_ENTRY(237), 887 I40E_PTT_UNUSED_ENTRY(238), 888 I40E_PTT_UNUSED_ENTRY(239), 889 890 I40E_PTT_UNUSED_ENTRY(240), 891 I40E_PTT_UNUSED_ENTRY(241), 892 I40E_PTT_UNUSED_ENTRY(242), 893 I40E_PTT_UNUSED_ENTRY(243), 894 I40E_PTT_UNUSED_ENTRY(244), 895 I40E_PTT_UNUSED_ENTRY(245), 896 I40E_PTT_UNUSED_ENTRY(246), 897 I40E_PTT_UNUSED_ENTRY(247), 898 I40E_PTT_UNUSED_ENTRY(248), 899 I40E_PTT_UNUSED_ENTRY(249), 900 901 I40E_PTT_UNUSED_ENTRY(250), 902 I40E_PTT_UNUSED_ENTRY(251), 903 I40E_PTT_UNUSED_ENTRY(252), 904 I40E_PTT_UNUSED_ENTRY(253), 905 I40E_PTT_UNUSED_ENTRY(254), 906 I40E_PTT_UNUSED_ENTRY(255) 907 }; 908 909 /** 910 * i40e_init_shared_code - Initialize the shared code 911 * @hw: pointer to hardware structure 912 * 913 * This assigns the MAC type and PHY code and inits the NVM. 914 * Does not touch the hardware. This function must be called prior to any 915 * other function in the shared code. The i40e_hw structure should be 916 * memset to 0 prior to calling this function. The following fields in 917 * hw structure should be filled in prior to calling this function: 918 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 919 * subsystem_vendor_id, and revision_id 920 **/ 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 922 { 923 i40e_status status = 0; 924 u32 port, ari, func_rid; 925 926 i40e_set_mac_type(hw); 927 928 switch (hw->mac.type) { 929 case I40E_MAC_XL710: 930 case I40E_MAC_X722: 931 break; 932 default: 933 return I40E_ERR_DEVICE_NOT_SUPPORTED; 934 } 935 936 hw->phy.get_link_info = true; 937 938 /* Determine port number and PF number*/ 939 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 940 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 941 hw->port = (u8)port; 942 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 943 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 944 func_rid = rd32(hw, I40E_PF_FUNC_RID); 945 if (ari) 946 hw->pf_id = (u8)(func_rid & 0xff); 947 else 948 hw->pf_id = (u8)(func_rid & 0x7); 949 950 if (hw->mac.type == I40E_MAC_X722) 951 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 952 953 status = i40e_init_nvm(hw); 954 return status; 955 } 956 957 /** 958 * i40e_aq_mac_address_read - Retrieve the MAC addresses 959 * @hw: pointer to the hw struct 960 * @flags: a return indicator of what addresses were added to the addr store 961 * @addrs: the requestor's mac addr store 962 * @cmd_details: pointer to command details structure or NULL 963 **/ 964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 965 u16 *flags, 966 struct i40e_aqc_mac_address_read_data *addrs, 967 struct i40e_asq_cmd_details *cmd_details) 968 { 969 struct i40e_aq_desc desc; 970 struct i40e_aqc_mac_address_read *cmd_data = 971 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 972 i40e_status status; 973 974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 975 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 976 977 status = i40e_asq_send_command(hw, &desc, addrs, 978 sizeof(*addrs), cmd_details); 979 *flags = le16_to_cpu(cmd_data->command_flags); 980 981 return status; 982 } 983 984 /** 985 * i40e_aq_mac_address_write - Change the MAC addresses 986 * @hw: pointer to the hw struct 987 * @flags: indicates which MAC to be written 988 * @mac_addr: address to write 989 * @cmd_details: pointer to command details structure or NULL 990 **/ 991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 992 u16 flags, u8 *mac_addr, 993 struct i40e_asq_cmd_details *cmd_details) 994 { 995 struct i40e_aq_desc desc; 996 struct i40e_aqc_mac_address_write *cmd_data = 997 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 998 i40e_status status; 999 1000 i40e_fill_default_direct_cmd_desc(&desc, 1001 i40e_aqc_opc_mac_address_write); 1002 cmd_data->command_flags = cpu_to_le16(flags); 1003 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 1004 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 1005 ((u32)mac_addr[3] << 16) | 1006 ((u32)mac_addr[4] << 8) | 1007 mac_addr[5]); 1008 1009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1010 1011 return status; 1012 } 1013 1014 /** 1015 * i40e_get_mac_addr - get MAC address 1016 * @hw: pointer to the HW structure 1017 * @mac_addr: pointer to MAC address 1018 * 1019 * Reads the adapter's MAC address from register 1020 **/ 1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1022 { 1023 struct i40e_aqc_mac_address_read_data addrs; 1024 i40e_status status; 1025 u16 flags = 0; 1026 1027 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1028 1029 if (flags & I40E_AQC_LAN_ADDR_VALID) 1030 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1031 1032 return status; 1033 } 1034 1035 /** 1036 * i40e_get_port_mac_addr - get Port MAC address 1037 * @hw: pointer to the HW structure 1038 * @mac_addr: pointer to Port MAC address 1039 * 1040 * Reads the adapter's Port MAC address 1041 **/ 1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1043 { 1044 struct i40e_aqc_mac_address_read_data addrs; 1045 i40e_status status; 1046 u16 flags = 0; 1047 1048 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1049 if (status) 1050 return status; 1051 1052 if (flags & I40E_AQC_PORT_ADDR_VALID) 1053 ether_addr_copy(mac_addr, addrs.port_mac); 1054 else 1055 status = I40E_ERR_INVALID_MAC_ADDR; 1056 1057 return status; 1058 } 1059 1060 /** 1061 * i40e_pre_tx_queue_cfg - pre tx queue configure 1062 * @hw: pointer to the HW structure 1063 * @queue: target PF queue index 1064 * @enable: state change request 1065 * 1066 * Handles hw requirement to indicate intention to enable 1067 * or disable target queue. 1068 **/ 1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1070 { 1071 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1072 u32 reg_block = 0; 1073 u32 reg_val; 1074 1075 if (abs_queue_idx >= 128) { 1076 reg_block = abs_queue_idx / 128; 1077 abs_queue_idx %= 128; 1078 } 1079 1080 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1081 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1082 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1083 1084 if (enable) 1085 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1086 else 1087 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1088 1089 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1090 } 1091 1092 /** 1093 * i40e_read_pba_string - Reads part number string from EEPROM 1094 * @hw: pointer to hardware structure 1095 * @pba_num: stores the part number string from the EEPROM 1096 * @pba_num_size: part number string buffer length 1097 * 1098 * Reads the part number string from the EEPROM. 1099 **/ 1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1101 u32 pba_num_size) 1102 { 1103 i40e_status status = 0; 1104 u16 pba_word = 0; 1105 u16 pba_size = 0; 1106 u16 pba_ptr = 0; 1107 u16 i = 0; 1108 1109 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1110 if (status || (pba_word != 0xFAFA)) { 1111 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1112 return status; 1113 } 1114 1115 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1116 if (status) { 1117 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1118 return status; 1119 } 1120 1121 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1122 if (status) { 1123 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1124 return status; 1125 } 1126 1127 /* Subtract one to get PBA word count (PBA Size word is included in 1128 * total size) 1129 */ 1130 pba_size--; 1131 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1132 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1133 return I40E_ERR_PARAM; 1134 } 1135 1136 for (i = 0; i < pba_size; i++) { 1137 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1138 if (status) { 1139 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1140 return status; 1141 } 1142 1143 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1144 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1145 } 1146 pba_num[(pba_size * 2)] = '\0'; 1147 1148 return status; 1149 } 1150 1151 /** 1152 * i40e_get_media_type - Gets media type 1153 * @hw: pointer to the hardware structure 1154 **/ 1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1156 { 1157 enum i40e_media_type media; 1158 1159 switch (hw->phy.link_info.phy_type) { 1160 case I40E_PHY_TYPE_10GBASE_SR: 1161 case I40E_PHY_TYPE_10GBASE_LR: 1162 case I40E_PHY_TYPE_1000BASE_SX: 1163 case I40E_PHY_TYPE_1000BASE_LX: 1164 case I40E_PHY_TYPE_40GBASE_SR4: 1165 case I40E_PHY_TYPE_40GBASE_LR4: 1166 case I40E_PHY_TYPE_25GBASE_LR: 1167 case I40E_PHY_TYPE_25GBASE_SR: 1168 media = I40E_MEDIA_TYPE_FIBER; 1169 break; 1170 case I40E_PHY_TYPE_100BASE_TX: 1171 case I40E_PHY_TYPE_1000BASE_T: 1172 case I40E_PHY_TYPE_10GBASE_T: 1173 media = I40E_MEDIA_TYPE_BASET; 1174 break; 1175 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1176 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1177 case I40E_PHY_TYPE_10GBASE_CR1: 1178 case I40E_PHY_TYPE_40GBASE_CR4: 1179 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1180 case I40E_PHY_TYPE_40GBASE_AOC: 1181 case I40E_PHY_TYPE_10GBASE_AOC: 1182 case I40E_PHY_TYPE_25GBASE_CR: 1183 media = I40E_MEDIA_TYPE_DA; 1184 break; 1185 case I40E_PHY_TYPE_1000BASE_KX: 1186 case I40E_PHY_TYPE_10GBASE_KX4: 1187 case I40E_PHY_TYPE_10GBASE_KR: 1188 case I40E_PHY_TYPE_40GBASE_KR4: 1189 case I40E_PHY_TYPE_20GBASE_KR2: 1190 case I40E_PHY_TYPE_25GBASE_KR: 1191 media = I40E_MEDIA_TYPE_BACKPLANE; 1192 break; 1193 case I40E_PHY_TYPE_SGMII: 1194 case I40E_PHY_TYPE_XAUI: 1195 case I40E_PHY_TYPE_XFI: 1196 case I40E_PHY_TYPE_XLAUI: 1197 case I40E_PHY_TYPE_XLPPI: 1198 default: 1199 media = I40E_MEDIA_TYPE_UNKNOWN; 1200 break; 1201 } 1202 1203 return media; 1204 } 1205 1206 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1207 #define I40E_PF_RESET_WAIT_COUNT 200 1208 /** 1209 * i40e_pf_reset - Reset the PF 1210 * @hw: pointer to the hardware structure 1211 * 1212 * Assuming someone else has triggered a global reset, 1213 * assure the global reset is complete and then reset the PF 1214 **/ 1215 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1216 { 1217 u32 cnt = 0; 1218 u32 cnt1 = 0; 1219 u32 reg = 0; 1220 u32 grst_del; 1221 1222 /* Poll for Global Reset steady state in case of recent GRST. 1223 * The grst delay value is in 100ms units, and we'll wait a 1224 * couple counts longer to be sure we don't just miss the end. 1225 */ 1226 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1227 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1228 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1229 1230 /* It can take upto 15 secs for GRST steady state. 1231 * Bump it to 16 secs max to be safe. 1232 */ 1233 grst_del = grst_del * 20; 1234 1235 for (cnt = 0; cnt < grst_del; cnt++) { 1236 reg = rd32(hw, I40E_GLGEN_RSTAT); 1237 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1238 break; 1239 msleep(100); 1240 } 1241 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1242 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1243 return I40E_ERR_RESET_FAILED; 1244 } 1245 1246 /* Now Wait for the FW to be ready */ 1247 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1248 reg = rd32(hw, I40E_GLNVM_ULD); 1249 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1250 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1251 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1252 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1253 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1254 break; 1255 } 1256 usleep_range(10000, 20000); 1257 } 1258 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1259 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1260 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1261 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1262 return I40E_ERR_RESET_FAILED; 1263 } 1264 1265 /* If there was a Global Reset in progress when we got here, 1266 * we don't need to do the PF Reset 1267 */ 1268 if (!cnt) { 1269 if (hw->revision_id == 0) 1270 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1271 else 1272 cnt = I40E_PF_RESET_WAIT_COUNT; 1273 reg = rd32(hw, I40E_PFGEN_CTRL); 1274 wr32(hw, I40E_PFGEN_CTRL, 1275 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1276 for (; cnt; cnt--) { 1277 reg = rd32(hw, I40E_PFGEN_CTRL); 1278 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1279 break; 1280 usleep_range(1000, 2000); 1281 } 1282 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1283 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1284 return I40E_ERR_RESET_FAILED; 1285 } 1286 } 1287 1288 i40e_clear_pxe_mode(hw); 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * i40e_clear_hw - clear out any left over hw state 1295 * @hw: pointer to the hw struct 1296 * 1297 * Clear queues and interrupts, typically called at init time, 1298 * but after the capabilities have been found so we know how many 1299 * queues and msix vectors have been allocated. 1300 **/ 1301 void i40e_clear_hw(struct i40e_hw *hw) 1302 { 1303 u32 num_queues, base_queue; 1304 u32 num_pf_int; 1305 u32 num_vf_int; 1306 u32 num_vfs; 1307 u32 i, j; 1308 u32 val; 1309 u32 eol = 0x7ff; 1310 1311 /* get number of interrupts, queues, and VFs */ 1312 val = rd32(hw, I40E_GLPCI_CNF2); 1313 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1314 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1315 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1316 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1317 1318 val = rd32(hw, I40E_PFLAN_QALLOC); 1319 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1320 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1321 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1322 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1323 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1324 num_queues = (j - base_queue) + 1; 1325 else 1326 num_queues = 0; 1327 1328 val = rd32(hw, I40E_PF_VT_PFALLOC); 1329 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1330 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1331 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1332 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1333 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1334 num_vfs = (j - i) + 1; 1335 else 1336 num_vfs = 0; 1337 1338 /* stop all the interrupts */ 1339 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1340 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1341 for (i = 0; i < num_pf_int - 2; i++) 1342 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1343 1344 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1345 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1346 wr32(hw, I40E_PFINT_LNKLST0, val); 1347 for (i = 0; i < num_pf_int - 2; i++) 1348 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1349 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1350 for (i = 0; i < num_vfs; i++) 1351 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1352 for (i = 0; i < num_vf_int - 2; i++) 1353 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1354 1355 /* warn the HW of the coming Tx disables */ 1356 for (i = 0; i < num_queues; i++) { 1357 u32 abs_queue_idx = base_queue + i; 1358 u32 reg_block = 0; 1359 1360 if (abs_queue_idx >= 128) { 1361 reg_block = abs_queue_idx / 128; 1362 abs_queue_idx %= 128; 1363 } 1364 1365 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1366 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1367 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1368 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1369 1370 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1371 } 1372 udelay(400); 1373 1374 /* stop all the queues */ 1375 for (i = 0; i < num_queues; i++) { 1376 wr32(hw, I40E_QINT_TQCTL(i), 0); 1377 wr32(hw, I40E_QTX_ENA(i), 0); 1378 wr32(hw, I40E_QINT_RQCTL(i), 0); 1379 wr32(hw, I40E_QRX_ENA(i), 0); 1380 } 1381 1382 /* short wait for all queue disables to settle */ 1383 udelay(50); 1384 } 1385 1386 /** 1387 * i40e_clear_pxe_mode - clear pxe operations mode 1388 * @hw: pointer to the hw struct 1389 * 1390 * Make sure all PXE mode settings are cleared, including things 1391 * like descriptor fetch/write-back mode. 1392 **/ 1393 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1394 { 1395 u32 reg; 1396 1397 if (i40e_check_asq_alive(hw)) 1398 i40e_aq_clear_pxe_mode(hw, NULL); 1399 1400 /* Clear single descriptor fetch/write-back mode */ 1401 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1402 1403 if (hw->revision_id == 0) { 1404 /* As a work around clear PXE_MODE instead of setting it */ 1405 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1406 } else { 1407 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1408 } 1409 } 1410 1411 /** 1412 * i40e_led_is_mine - helper to find matching led 1413 * @hw: pointer to the hw struct 1414 * @idx: index into GPIO registers 1415 * 1416 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1417 */ 1418 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1419 { 1420 u32 gpio_val = 0; 1421 u32 port; 1422 1423 if (!hw->func_caps.led[idx]) 1424 return 0; 1425 1426 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1427 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1428 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1429 1430 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1431 * if it is not our port then ignore 1432 */ 1433 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1434 (port != hw->port)) 1435 return 0; 1436 1437 return gpio_val; 1438 } 1439 1440 #define I40E_COMBINED_ACTIVITY 0xA 1441 #define I40E_FILTER_ACTIVITY 0xE 1442 #define I40E_LINK_ACTIVITY 0xC 1443 #define I40E_MAC_ACTIVITY 0xD 1444 #define I40E_LED0 22 1445 1446 /** 1447 * i40e_led_get - return current on/off mode 1448 * @hw: pointer to the hw struct 1449 * 1450 * The value returned is the 'mode' field as defined in the 1451 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1452 * values are variations of possible behaviors relating to 1453 * blink, link, and wire. 1454 **/ 1455 u32 i40e_led_get(struct i40e_hw *hw) 1456 { 1457 u32 current_mode = 0; 1458 u32 mode = 0; 1459 int i; 1460 1461 /* as per the documentation GPIO 22-29 are the LED 1462 * GPIO pins named LED0..LED7 1463 */ 1464 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1465 u32 gpio_val = i40e_led_is_mine(hw, i); 1466 1467 if (!gpio_val) 1468 continue; 1469 1470 /* ignore gpio LED src mode entries related to the activity 1471 * LEDs 1472 */ 1473 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1474 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1475 switch (current_mode) { 1476 case I40E_COMBINED_ACTIVITY: 1477 case I40E_FILTER_ACTIVITY: 1478 case I40E_MAC_ACTIVITY: 1479 continue; 1480 default: 1481 break; 1482 } 1483 1484 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1485 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1486 break; 1487 } 1488 1489 return mode; 1490 } 1491 1492 /** 1493 * i40e_led_set - set new on/off mode 1494 * @hw: pointer to the hw struct 1495 * @mode: 0=off, 0xf=on (else see manual for mode details) 1496 * @blink: true if the LED should blink when on, false if steady 1497 * 1498 * if this function is used to turn on the blink it should 1499 * be used to disable the blink when restoring the original state. 1500 **/ 1501 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1502 { 1503 u32 current_mode = 0; 1504 int i; 1505 1506 if (mode & 0xfffffff0) 1507 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1508 1509 /* as per the documentation GPIO 22-29 are the LED 1510 * GPIO pins named LED0..LED7 1511 */ 1512 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1513 u32 gpio_val = i40e_led_is_mine(hw, i); 1514 1515 if (!gpio_val) 1516 continue; 1517 1518 /* ignore gpio LED src mode entries related to the activity 1519 * LEDs 1520 */ 1521 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1522 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1523 switch (current_mode) { 1524 case I40E_COMBINED_ACTIVITY: 1525 case I40E_FILTER_ACTIVITY: 1526 case I40E_MAC_ACTIVITY: 1527 continue; 1528 default: 1529 break; 1530 } 1531 1532 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1533 /* this & is a bit of paranoia, but serves as a range check */ 1534 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1535 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1536 1537 if (mode == I40E_LINK_ACTIVITY) 1538 blink = false; 1539 1540 if (blink) 1541 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1542 else 1543 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1544 1545 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1546 break; 1547 } 1548 } 1549 1550 /* Admin command wrappers */ 1551 1552 /** 1553 * i40e_aq_get_phy_capabilities 1554 * @hw: pointer to the hw struct 1555 * @abilities: structure for PHY capabilities to be filled 1556 * @qualified_modules: report Qualified Modules 1557 * @report_init: report init capabilities (active are default) 1558 * @cmd_details: pointer to command details structure or NULL 1559 * 1560 * Returns the various PHY abilities supported on the Port. 1561 **/ 1562 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1563 bool qualified_modules, bool report_init, 1564 struct i40e_aq_get_phy_abilities_resp *abilities, 1565 struct i40e_asq_cmd_details *cmd_details) 1566 { 1567 struct i40e_aq_desc desc; 1568 i40e_status status; 1569 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1570 1571 if (!abilities) 1572 return I40E_ERR_PARAM; 1573 1574 i40e_fill_default_direct_cmd_desc(&desc, 1575 i40e_aqc_opc_get_phy_abilities); 1576 1577 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1578 if (abilities_size > I40E_AQ_LARGE_BUF) 1579 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1580 1581 if (qualified_modules) 1582 desc.params.external.param0 |= 1583 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1584 1585 if (report_init) 1586 desc.params.external.param0 |= 1587 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1588 1589 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1590 cmd_details); 1591 1592 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1593 status = I40E_ERR_UNKNOWN_PHY; 1594 1595 if (report_init) { 1596 if (hw->mac.type == I40E_MAC_XL710 && 1597 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1598 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) 1599 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1600 } 1601 1602 return status; 1603 } 1604 1605 /** 1606 * i40e_aq_set_phy_config 1607 * @hw: pointer to the hw struct 1608 * @config: structure with PHY configuration to be set 1609 * @cmd_details: pointer to command details structure or NULL 1610 * 1611 * Set the various PHY configuration parameters 1612 * supported on the Port.One or more of the Set PHY config parameters may be 1613 * ignored in an MFP mode as the PF may not have the privilege to set some 1614 * of the PHY Config parameters. This status will be indicated by the 1615 * command response. 1616 **/ 1617 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1618 struct i40e_aq_set_phy_config *config, 1619 struct i40e_asq_cmd_details *cmd_details) 1620 { 1621 struct i40e_aq_desc desc; 1622 struct i40e_aq_set_phy_config *cmd = 1623 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1624 enum i40e_status_code status; 1625 1626 if (!config) 1627 return I40E_ERR_PARAM; 1628 1629 i40e_fill_default_direct_cmd_desc(&desc, 1630 i40e_aqc_opc_set_phy_config); 1631 1632 *cmd = *config; 1633 1634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1635 1636 return status; 1637 } 1638 1639 /** 1640 * i40e_set_fc 1641 * @hw: pointer to the hw struct 1642 * 1643 * Set the requested flow control mode using set_phy_config. 1644 **/ 1645 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1646 bool atomic_restart) 1647 { 1648 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1649 struct i40e_aq_get_phy_abilities_resp abilities; 1650 struct i40e_aq_set_phy_config config; 1651 enum i40e_status_code status; 1652 u8 pause_mask = 0x0; 1653 1654 *aq_failures = 0x0; 1655 1656 switch (fc_mode) { 1657 case I40E_FC_FULL: 1658 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1659 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1660 break; 1661 case I40E_FC_RX_PAUSE: 1662 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1663 break; 1664 case I40E_FC_TX_PAUSE: 1665 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1666 break; 1667 default: 1668 break; 1669 } 1670 1671 /* Get the current phy config */ 1672 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1673 NULL); 1674 if (status) { 1675 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1676 return status; 1677 } 1678 1679 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1680 /* clear the old pause settings */ 1681 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1682 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1683 /* set the new abilities */ 1684 config.abilities |= pause_mask; 1685 /* If the abilities have changed, then set the new config */ 1686 if (config.abilities != abilities.abilities) { 1687 /* Auto restart link so settings take effect */ 1688 if (atomic_restart) 1689 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1690 /* Copy over all the old settings */ 1691 config.phy_type = abilities.phy_type; 1692 config.phy_type_ext = abilities.phy_type_ext; 1693 config.link_speed = abilities.link_speed; 1694 config.eee_capability = abilities.eee_capability; 1695 config.eeer = abilities.eeer_val; 1696 config.low_power_ctrl = abilities.d3_lpan; 1697 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1698 I40E_AQ_PHY_FEC_CONFIG_MASK; 1699 status = i40e_aq_set_phy_config(hw, &config, NULL); 1700 1701 if (status) 1702 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1703 } 1704 /* Update the link info */ 1705 status = i40e_update_link_info(hw); 1706 if (status) { 1707 /* Wait a little bit (on 40G cards it sometimes takes a really 1708 * long time for link to come back from the atomic reset) 1709 * and try once more 1710 */ 1711 msleep(1000); 1712 status = i40e_update_link_info(hw); 1713 } 1714 if (status) 1715 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1716 1717 return status; 1718 } 1719 1720 /** 1721 * i40e_aq_clear_pxe_mode 1722 * @hw: pointer to the hw struct 1723 * @cmd_details: pointer to command details structure or NULL 1724 * 1725 * Tell the firmware that the driver is taking over from PXE 1726 **/ 1727 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1728 struct i40e_asq_cmd_details *cmd_details) 1729 { 1730 i40e_status status; 1731 struct i40e_aq_desc desc; 1732 struct i40e_aqc_clear_pxe *cmd = 1733 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1734 1735 i40e_fill_default_direct_cmd_desc(&desc, 1736 i40e_aqc_opc_clear_pxe_mode); 1737 1738 cmd->rx_cnt = 0x2; 1739 1740 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1741 1742 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1743 1744 return status; 1745 } 1746 1747 /** 1748 * i40e_aq_set_link_restart_an 1749 * @hw: pointer to the hw struct 1750 * @enable_link: if true: enable link, if false: disable link 1751 * @cmd_details: pointer to command details structure or NULL 1752 * 1753 * Sets up the link and restarts the Auto-Negotiation over the link. 1754 **/ 1755 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1756 bool enable_link, 1757 struct i40e_asq_cmd_details *cmd_details) 1758 { 1759 struct i40e_aq_desc desc; 1760 struct i40e_aqc_set_link_restart_an *cmd = 1761 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1762 i40e_status status; 1763 1764 i40e_fill_default_direct_cmd_desc(&desc, 1765 i40e_aqc_opc_set_link_restart_an); 1766 1767 cmd->command = I40E_AQ_PHY_RESTART_AN; 1768 if (enable_link) 1769 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1770 else 1771 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1772 1773 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1774 1775 return status; 1776 } 1777 1778 /** 1779 * i40e_aq_get_link_info 1780 * @hw: pointer to the hw struct 1781 * @enable_lse: enable/disable LinkStatusEvent reporting 1782 * @link: pointer to link status structure - optional 1783 * @cmd_details: pointer to command details structure or NULL 1784 * 1785 * Returns the link status of the adapter. 1786 **/ 1787 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1788 bool enable_lse, struct i40e_link_status *link, 1789 struct i40e_asq_cmd_details *cmd_details) 1790 { 1791 struct i40e_aq_desc desc; 1792 struct i40e_aqc_get_link_status *resp = 1793 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1794 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1795 i40e_status status; 1796 bool tx_pause, rx_pause; 1797 u16 command_flags; 1798 1799 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1800 1801 if (enable_lse) 1802 command_flags = I40E_AQ_LSE_ENABLE; 1803 else 1804 command_flags = I40E_AQ_LSE_DISABLE; 1805 resp->command_flags = cpu_to_le16(command_flags); 1806 1807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1808 1809 if (status) 1810 goto aq_get_link_info_exit; 1811 1812 /* save off old link status information */ 1813 hw->phy.link_info_old = *hw_link_info; 1814 1815 /* update link status */ 1816 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1817 hw->phy.media_type = i40e_get_media_type(hw); 1818 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1819 hw_link_info->link_info = resp->link_info; 1820 hw_link_info->an_info = resp->an_info; 1821 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1822 I40E_AQ_CONFIG_FEC_RS_ENA); 1823 hw_link_info->ext_info = resp->ext_info; 1824 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1825 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1826 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1827 1828 /* update fc info */ 1829 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1830 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1831 if (tx_pause & rx_pause) 1832 hw->fc.current_mode = I40E_FC_FULL; 1833 else if (tx_pause) 1834 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1835 else if (rx_pause) 1836 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1837 else 1838 hw->fc.current_mode = I40E_FC_NONE; 1839 1840 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1841 hw_link_info->crc_enable = true; 1842 else 1843 hw_link_info->crc_enable = false; 1844 1845 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1846 hw_link_info->lse_enable = true; 1847 else 1848 hw_link_info->lse_enable = false; 1849 1850 if ((hw->mac.type == I40E_MAC_XL710) && 1851 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1852 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1853 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1854 1855 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1856 hw->aq.api_min_ver >= 7) { 1857 __le32 tmp; 1858 1859 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1860 hw->phy.phy_types = le32_to_cpu(tmp); 1861 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1862 } 1863 1864 /* save link status information */ 1865 if (link) 1866 *link = *hw_link_info; 1867 1868 /* flag cleared so helper functions don't call AQ again */ 1869 hw->phy.get_link_info = false; 1870 1871 aq_get_link_info_exit: 1872 return status; 1873 } 1874 1875 /** 1876 * i40e_aq_set_phy_int_mask 1877 * @hw: pointer to the hw struct 1878 * @mask: interrupt mask to be set 1879 * @cmd_details: pointer to command details structure or NULL 1880 * 1881 * Set link interrupt mask. 1882 **/ 1883 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1884 u16 mask, 1885 struct i40e_asq_cmd_details *cmd_details) 1886 { 1887 struct i40e_aq_desc desc; 1888 struct i40e_aqc_set_phy_int_mask *cmd = 1889 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1890 i40e_status status; 1891 1892 i40e_fill_default_direct_cmd_desc(&desc, 1893 i40e_aqc_opc_set_phy_int_mask); 1894 1895 cmd->event_mask = cpu_to_le16(mask); 1896 1897 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1898 1899 return status; 1900 } 1901 1902 /** 1903 * i40e_aq_set_phy_debug 1904 * @hw: pointer to the hw struct 1905 * @cmd_flags: debug command flags 1906 * @cmd_details: pointer to command details structure or NULL 1907 * 1908 * Reset the external PHY. 1909 **/ 1910 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1911 struct i40e_asq_cmd_details *cmd_details) 1912 { 1913 struct i40e_aq_desc desc; 1914 struct i40e_aqc_set_phy_debug *cmd = 1915 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1916 i40e_status status; 1917 1918 i40e_fill_default_direct_cmd_desc(&desc, 1919 i40e_aqc_opc_set_phy_debug); 1920 1921 cmd->command_flags = cmd_flags; 1922 1923 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1924 1925 return status; 1926 } 1927 1928 /** 1929 * i40e_aq_add_vsi 1930 * @hw: pointer to the hw struct 1931 * @vsi_ctx: pointer to a vsi context struct 1932 * @cmd_details: pointer to command details structure or NULL 1933 * 1934 * Add a VSI context to the hardware. 1935 **/ 1936 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1937 struct i40e_vsi_context *vsi_ctx, 1938 struct i40e_asq_cmd_details *cmd_details) 1939 { 1940 struct i40e_aq_desc desc; 1941 struct i40e_aqc_add_get_update_vsi *cmd = 1942 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1943 struct i40e_aqc_add_get_update_vsi_completion *resp = 1944 (struct i40e_aqc_add_get_update_vsi_completion *) 1945 &desc.params.raw; 1946 i40e_status status; 1947 1948 i40e_fill_default_direct_cmd_desc(&desc, 1949 i40e_aqc_opc_add_vsi); 1950 1951 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1952 cmd->connection_type = vsi_ctx->connection_type; 1953 cmd->vf_id = vsi_ctx->vf_num; 1954 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1955 1956 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1957 1958 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1959 sizeof(vsi_ctx->info), cmd_details); 1960 1961 if (status) 1962 goto aq_add_vsi_exit; 1963 1964 vsi_ctx->seid = le16_to_cpu(resp->seid); 1965 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1966 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1967 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1968 1969 aq_add_vsi_exit: 1970 return status; 1971 } 1972 1973 /** 1974 * i40e_aq_set_default_vsi 1975 * @hw: pointer to the hw struct 1976 * @seid: vsi number 1977 * @cmd_details: pointer to command details structure or NULL 1978 **/ 1979 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 1980 u16 seid, 1981 struct i40e_asq_cmd_details *cmd_details) 1982 { 1983 struct i40e_aq_desc desc; 1984 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1985 (struct i40e_aqc_set_vsi_promiscuous_modes *) 1986 &desc.params.raw; 1987 i40e_status status; 1988 1989 i40e_fill_default_direct_cmd_desc(&desc, 1990 i40e_aqc_opc_set_vsi_promiscuous_modes); 1991 1992 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1993 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 1994 cmd->seid = cpu_to_le16(seid); 1995 1996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1997 1998 return status; 1999 } 2000 2001 /** 2002 * i40e_aq_clear_default_vsi 2003 * @hw: pointer to the hw struct 2004 * @seid: vsi number 2005 * @cmd_details: pointer to command details structure or NULL 2006 **/ 2007 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2008 u16 seid, 2009 struct i40e_asq_cmd_details *cmd_details) 2010 { 2011 struct i40e_aq_desc desc; 2012 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2013 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2014 &desc.params.raw; 2015 i40e_status status; 2016 2017 i40e_fill_default_direct_cmd_desc(&desc, 2018 i40e_aqc_opc_set_vsi_promiscuous_modes); 2019 2020 cmd->promiscuous_flags = cpu_to_le16(0); 2021 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2022 cmd->seid = cpu_to_le16(seid); 2023 2024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2025 2026 return status; 2027 } 2028 2029 /** 2030 * i40e_aq_set_vsi_unicast_promiscuous 2031 * @hw: pointer to the hw struct 2032 * @seid: vsi number 2033 * @set: set unicast promiscuous enable/disable 2034 * @cmd_details: pointer to command details structure or NULL 2035 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2036 **/ 2037 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2038 u16 seid, bool set, 2039 struct i40e_asq_cmd_details *cmd_details, 2040 bool rx_only_promisc) 2041 { 2042 struct i40e_aq_desc desc; 2043 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2044 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2045 i40e_status status; 2046 u16 flags = 0; 2047 2048 i40e_fill_default_direct_cmd_desc(&desc, 2049 i40e_aqc_opc_set_vsi_promiscuous_modes); 2050 2051 if (set) { 2052 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2053 if (rx_only_promisc && 2054 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2055 (hw->aq.api_maj_ver > 1))) 2056 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2057 } 2058 2059 cmd->promiscuous_flags = cpu_to_le16(flags); 2060 2061 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2062 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2063 (hw->aq.api_maj_ver > 1)) 2064 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2065 2066 cmd->seid = cpu_to_le16(seid); 2067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2068 2069 return status; 2070 } 2071 2072 /** 2073 * i40e_aq_set_vsi_multicast_promiscuous 2074 * @hw: pointer to the hw struct 2075 * @seid: vsi number 2076 * @set: set multicast promiscuous enable/disable 2077 * @cmd_details: pointer to command details structure or NULL 2078 **/ 2079 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2080 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2081 { 2082 struct i40e_aq_desc desc; 2083 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2084 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2085 i40e_status status; 2086 u16 flags = 0; 2087 2088 i40e_fill_default_direct_cmd_desc(&desc, 2089 i40e_aqc_opc_set_vsi_promiscuous_modes); 2090 2091 if (set) 2092 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2093 2094 cmd->promiscuous_flags = cpu_to_le16(flags); 2095 2096 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2097 2098 cmd->seid = cpu_to_le16(seid); 2099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2100 2101 return status; 2102 } 2103 2104 /** 2105 * i40e_aq_set_vsi_mc_promisc_on_vlan 2106 * @hw: pointer to the hw struct 2107 * @seid: vsi number 2108 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2109 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2110 * @cmd_details: pointer to command details structure or NULL 2111 **/ 2112 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2113 u16 seid, bool enable, 2114 u16 vid, 2115 struct i40e_asq_cmd_details *cmd_details) 2116 { 2117 struct i40e_aq_desc desc; 2118 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2119 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2120 enum i40e_status_code status; 2121 u16 flags = 0; 2122 2123 i40e_fill_default_direct_cmd_desc(&desc, 2124 i40e_aqc_opc_set_vsi_promiscuous_modes); 2125 2126 if (enable) 2127 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2128 2129 cmd->promiscuous_flags = cpu_to_le16(flags); 2130 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2131 cmd->seid = cpu_to_le16(seid); 2132 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2133 2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2135 2136 return status; 2137 } 2138 2139 /** 2140 * i40e_aq_set_vsi_uc_promisc_on_vlan 2141 * @hw: pointer to the hw struct 2142 * @seid: vsi number 2143 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2144 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2145 * @cmd_details: pointer to command details structure or NULL 2146 **/ 2147 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2148 u16 seid, bool enable, 2149 u16 vid, 2150 struct i40e_asq_cmd_details *cmd_details) 2151 { 2152 struct i40e_aq_desc desc; 2153 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2154 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2155 enum i40e_status_code status; 2156 u16 flags = 0; 2157 2158 i40e_fill_default_direct_cmd_desc(&desc, 2159 i40e_aqc_opc_set_vsi_promiscuous_modes); 2160 2161 if (enable) 2162 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2163 2164 cmd->promiscuous_flags = cpu_to_le16(flags); 2165 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2166 cmd->seid = cpu_to_le16(seid); 2167 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2168 2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2170 2171 return status; 2172 } 2173 2174 /** 2175 * i40e_aq_set_vsi_bc_promisc_on_vlan 2176 * @hw: pointer to the hw struct 2177 * @seid: vsi number 2178 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2179 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2180 * @cmd_details: pointer to command details structure or NULL 2181 **/ 2182 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2183 u16 seid, bool enable, u16 vid, 2184 struct i40e_asq_cmd_details *cmd_details) 2185 { 2186 struct i40e_aq_desc desc; 2187 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2188 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2189 i40e_status status; 2190 u16 flags = 0; 2191 2192 i40e_fill_default_direct_cmd_desc(&desc, 2193 i40e_aqc_opc_set_vsi_promiscuous_modes); 2194 2195 if (enable) 2196 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2197 2198 cmd->promiscuous_flags = cpu_to_le16(flags); 2199 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2200 cmd->seid = cpu_to_le16(seid); 2201 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2202 2203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2204 2205 return status; 2206 } 2207 2208 /** 2209 * i40e_aq_set_vsi_broadcast 2210 * @hw: pointer to the hw struct 2211 * @seid: vsi number 2212 * @set_filter: true to set filter, false to clear filter 2213 * @cmd_details: pointer to command details structure or NULL 2214 * 2215 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2216 **/ 2217 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2218 u16 seid, bool set_filter, 2219 struct i40e_asq_cmd_details *cmd_details) 2220 { 2221 struct i40e_aq_desc desc; 2222 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2223 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2224 i40e_status status; 2225 2226 i40e_fill_default_direct_cmd_desc(&desc, 2227 i40e_aqc_opc_set_vsi_promiscuous_modes); 2228 2229 if (set_filter) 2230 cmd->promiscuous_flags 2231 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2232 else 2233 cmd->promiscuous_flags 2234 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2235 2236 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2237 cmd->seid = cpu_to_le16(seid); 2238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2239 2240 return status; 2241 } 2242 2243 /** 2244 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2245 * @hw: pointer to the hw struct 2246 * @seid: vsi number 2247 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2248 * @cmd_details: pointer to command details structure or NULL 2249 **/ 2250 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2251 u16 seid, bool enable, 2252 struct i40e_asq_cmd_details *cmd_details) 2253 { 2254 struct i40e_aq_desc desc; 2255 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2256 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2257 i40e_status status; 2258 u16 flags = 0; 2259 2260 i40e_fill_default_direct_cmd_desc(&desc, 2261 i40e_aqc_opc_set_vsi_promiscuous_modes); 2262 if (enable) 2263 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2264 2265 cmd->promiscuous_flags = cpu_to_le16(flags); 2266 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2267 cmd->seid = cpu_to_le16(seid); 2268 2269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2270 2271 return status; 2272 } 2273 2274 /** 2275 * i40e_get_vsi_params - get VSI configuration info 2276 * @hw: pointer to the hw struct 2277 * @vsi_ctx: pointer to a vsi context struct 2278 * @cmd_details: pointer to command details structure or NULL 2279 **/ 2280 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2281 struct i40e_vsi_context *vsi_ctx, 2282 struct i40e_asq_cmd_details *cmd_details) 2283 { 2284 struct i40e_aq_desc desc; 2285 struct i40e_aqc_add_get_update_vsi *cmd = 2286 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2287 struct i40e_aqc_add_get_update_vsi_completion *resp = 2288 (struct i40e_aqc_add_get_update_vsi_completion *) 2289 &desc.params.raw; 2290 i40e_status status; 2291 2292 i40e_fill_default_direct_cmd_desc(&desc, 2293 i40e_aqc_opc_get_vsi_parameters); 2294 2295 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2296 2297 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2298 2299 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2300 sizeof(vsi_ctx->info), NULL); 2301 2302 if (status) 2303 goto aq_get_vsi_params_exit; 2304 2305 vsi_ctx->seid = le16_to_cpu(resp->seid); 2306 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2307 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2308 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2309 2310 aq_get_vsi_params_exit: 2311 return status; 2312 } 2313 2314 /** 2315 * i40e_aq_update_vsi_params 2316 * @hw: pointer to the hw struct 2317 * @vsi_ctx: pointer to a vsi context struct 2318 * @cmd_details: pointer to command details structure or NULL 2319 * 2320 * Update a VSI context. 2321 **/ 2322 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2323 struct i40e_vsi_context *vsi_ctx, 2324 struct i40e_asq_cmd_details *cmd_details) 2325 { 2326 struct i40e_aq_desc desc; 2327 struct i40e_aqc_add_get_update_vsi *cmd = 2328 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2329 struct i40e_aqc_add_get_update_vsi_completion *resp = 2330 (struct i40e_aqc_add_get_update_vsi_completion *) 2331 &desc.params.raw; 2332 i40e_status status; 2333 2334 i40e_fill_default_direct_cmd_desc(&desc, 2335 i40e_aqc_opc_update_vsi_parameters); 2336 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2337 2338 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2339 2340 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2341 sizeof(vsi_ctx->info), cmd_details); 2342 2343 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2344 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2345 2346 return status; 2347 } 2348 2349 /** 2350 * i40e_aq_get_switch_config 2351 * @hw: pointer to the hardware structure 2352 * @buf: pointer to the result buffer 2353 * @buf_size: length of input buffer 2354 * @start_seid: seid to start for the report, 0 == beginning 2355 * @cmd_details: pointer to command details structure or NULL 2356 * 2357 * Fill the buf with switch configuration returned from AdminQ command 2358 **/ 2359 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2360 struct i40e_aqc_get_switch_config_resp *buf, 2361 u16 buf_size, u16 *start_seid, 2362 struct i40e_asq_cmd_details *cmd_details) 2363 { 2364 struct i40e_aq_desc desc; 2365 struct i40e_aqc_switch_seid *scfg = 2366 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2367 i40e_status status; 2368 2369 i40e_fill_default_direct_cmd_desc(&desc, 2370 i40e_aqc_opc_get_switch_config); 2371 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2372 if (buf_size > I40E_AQ_LARGE_BUF) 2373 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2374 scfg->seid = cpu_to_le16(*start_seid); 2375 2376 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2377 *start_seid = le16_to_cpu(scfg->seid); 2378 2379 return status; 2380 } 2381 2382 /** 2383 * i40e_aq_set_switch_config 2384 * @hw: pointer to the hardware structure 2385 * @flags: bit flag values to set 2386 * @valid_flags: which bit flags to set 2387 * @cmd_details: pointer to command details structure or NULL 2388 * 2389 * Set switch configuration bits 2390 **/ 2391 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2392 u16 flags, 2393 u16 valid_flags, 2394 struct i40e_asq_cmd_details *cmd_details) 2395 { 2396 struct i40e_aq_desc desc; 2397 struct i40e_aqc_set_switch_config *scfg = 2398 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2399 enum i40e_status_code status; 2400 2401 i40e_fill_default_direct_cmd_desc(&desc, 2402 i40e_aqc_opc_set_switch_config); 2403 scfg->flags = cpu_to_le16(flags); 2404 scfg->valid_flags = cpu_to_le16(valid_flags); 2405 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2406 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2407 scfg->first_tag = cpu_to_le16(hw->first_tag); 2408 scfg->second_tag = cpu_to_le16(hw->second_tag); 2409 } 2410 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2411 2412 return status; 2413 } 2414 2415 /** 2416 * i40e_aq_get_firmware_version 2417 * @hw: pointer to the hw struct 2418 * @fw_major_version: firmware major version 2419 * @fw_minor_version: firmware minor version 2420 * @fw_build: firmware build number 2421 * @api_major_version: major queue version 2422 * @api_minor_version: minor queue version 2423 * @cmd_details: pointer to command details structure or NULL 2424 * 2425 * Get the firmware version from the admin queue commands 2426 **/ 2427 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2428 u16 *fw_major_version, u16 *fw_minor_version, 2429 u32 *fw_build, 2430 u16 *api_major_version, u16 *api_minor_version, 2431 struct i40e_asq_cmd_details *cmd_details) 2432 { 2433 struct i40e_aq_desc desc; 2434 struct i40e_aqc_get_version *resp = 2435 (struct i40e_aqc_get_version *)&desc.params.raw; 2436 i40e_status status; 2437 2438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2439 2440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2441 2442 if (!status) { 2443 if (fw_major_version) 2444 *fw_major_version = le16_to_cpu(resp->fw_major); 2445 if (fw_minor_version) 2446 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2447 if (fw_build) 2448 *fw_build = le32_to_cpu(resp->fw_build); 2449 if (api_major_version) 2450 *api_major_version = le16_to_cpu(resp->api_major); 2451 if (api_minor_version) 2452 *api_minor_version = le16_to_cpu(resp->api_minor); 2453 } 2454 2455 return status; 2456 } 2457 2458 /** 2459 * i40e_aq_send_driver_version 2460 * @hw: pointer to the hw struct 2461 * @dv: driver's major, minor version 2462 * @cmd_details: pointer to command details structure or NULL 2463 * 2464 * Send the driver version to the firmware 2465 **/ 2466 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2467 struct i40e_driver_version *dv, 2468 struct i40e_asq_cmd_details *cmd_details) 2469 { 2470 struct i40e_aq_desc desc; 2471 struct i40e_aqc_driver_version *cmd = 2472 (struct i40e_aqc_driver_version *)&desc.params.raw; 2473 i40e_status status; 2474 u16 len; 2475 2476 if (dv == NULL) 2477 return I40E_ERR_PARAM; 2478 2479 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2480 2481 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2482 cmd->driver_major_ver = dv->major_version; 2483 cmd->driver_minor_ver = dv->minor_version; 2484 cmd->driver_build_ver = dv->build_version; 2485 cmd->driver_subbuild_ver = dv->subbuild_version; 2486 2487 len = 0; 2488 while (len < sizeof(dv->driver_string) && 2489 (dv->driver_string[len] < 0x80) && 2490 dv->driver_string[len]) 2491 len++; 2492 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2493 len, cmd_details); 2494 2495 return status; 2496 } 2497 2498 /** 2499 * i40e_get_link_status - get status of the HW network link 2500 * @hw: pointer to the hw struct 2501 * @link_up: pointer to bool (true/false = linkup/linkdown) 2502 * 2503 * Variable link_up true if link is up, false if link is down. 2504 * The variable link_up is invalid if returned value of status != 0 2505 * 2506 * Side effect: LinkStatusEvent reporting becomes enabled 2507 **/ 2508 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2509 { 2510 i40e_status status = 0; 2511 2512 if (hw->phy.get_link_info) { 2513 status = i40e_update_link_info(hw); 2514 2515 if (status) 2516 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2517 status); 2518 } 2519 2520 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2521 2522 return status; 2523 } 2524 2525 /** 2526 * i40e_updatelink_status - update status of the HW network link 2527 * @hw: pointer to the hw struct 2528 **/ 2529 i40e_status i40e_update_link_info(struct i40e_hw *hw) 2530 { 2531 struct i40e_aq_get_phy_abilities_resp abilities; 2532 i40e_status status = 0; 2533 2534 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2535 if (status) 2536 return status; 2537 2538 /* extra checking needed to ensure link info to user is timely */ 2539 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2540 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2541 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2542 status = i40e_aq_get_phy_capabilities(hw, false, false, 2543 &abilities, NULL); 2544 if (status) 2545 return status; 2546 2547 hw->phy.link_info.req_fec_info = 2548 abilities.fec_cfg_curr_mod_ext_info & 2549 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2550 2551 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2552 sizeof(hw->phy.link_info.module_type)); 2553 } 2554 2555 return status; 2556 } 2557 2558 /** 2559 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2560 * @hw: pointer to the hw struct 2561 * @uplink_seid: the MAC or other gizmo SEID 2562 * @downlink_seid: the VSI SEID 2563 * @enabled_tc: bitmap of TCs to be enabled 2564 * @default_port: true for default port VSI, false for control port 2565 * @veb_seid: pointer to where to put the resulting VEB SEID 2566 * @enable_stats: true to turn on VEB stats 2567 * @cmd_details: pointer to command details structure or NULL 2568 * 2569 * This asks the FW to add a VEB between the uplink and downlink 2570 * elements. If the uplink SEID is 0, this will be a floating VEB. 2571 **/ 2572 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2573 u16 downlink_seid, u8 enabled_tc, 2574 bool default_port, u16 *veb_seid, 2575 bool enable_stats, 2576 struct i40e_asq_cmd_details *cmd_details) 2577 { 2578 struct i40e_aq_desc desc; 2579 struct i40e_aqc_add_veb *cmd = 2580 (struct i40e_aqc_add_veb *)&desc.params.raw; 2581 struct i40e_aqc_add_veb_completion *resp = 2582 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2583 i40e_status status; 2584 u16 veb_flags = 0; 2585 2586 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2587 if (!!uplink_seid != !!downlink_seid) 2588 return I40E_ERR_PARAM; 2589 2590 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2591 2592 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2593 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2594 cmd->enable_tcs = enabled_tc; 2595 if (!uplink_seid) 2596 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2597 if (default_port) 2598 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2599 else 2600 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2601 2602 /* reverse logic here: set the bitflag to disable the stats */ 2603 if (!enable_stats) 2604 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2605 2606 cmd->veb_flags = cpu_to_le16(veb_flags); 2607 2608 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2609 2610 if (!status && veb_seid) 2611 *veb_seid = le16_to_cpu(resp->veb_seid); 2612 2613 return status; 2614 } 2615 2616 /** 2617 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2618 * @hw: pointer to the hw struct 2619 * @veb_seid: the SEID of the VEB to query 2620 * @switch_id: the uplink switch id 2621 * @floating: set to true if the VEB is floating 2622 * @statistic_index: index of the stats counter block for this VEB 2623 * @vebs_used: number of VEB's used by function 2624 * @vebs_free: total VEB's not reserved by any function 2625 * @cmd_details: pointer to command details structure or NULL 2626 * 2627 * This retrieves the parameters for a particular VEB, specified by 2628 * uplink_seid, and returns them to the caller. 2629 **/ 2630 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2631 u16 veb_seid, u16 *switch_id, 2632 bool *floating, u16 *statistic_index, 2633 u16 *vebs_used, u16 *vebs_free, 2634 struct i40e_asq_cmd_details *cmd_details) 2635 { 2636 struct i40e_aq_desc desc; 2637 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2638 (struct i40e_aqc_get_veb_parameters_completion *) 2639 &desc.params.raw; 2640 i40e_status status; 2641 2642 if (veb_seid == 0) 2643 return I40E_ERR_PARAM; 2644 2645 i40e_fill_default_direct_cmd_desc(&desc, 2646 i40e_aqc_opc_get_veb_parameters); 2647 cmd_resp->seid = cpu_to_le16(veb_seid); 2648 2649 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2650 if (status) 2651 goto get_veb_exit; 2652 2653 if (switch_id) 2654 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2655 if (statistic_index) 2656 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2657 if (vebs_used) 2658 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2659 if (vebs_free) 2660 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2661 if (floating) { 2662 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2663 2664 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2665 *floating = true; 2666 else 2667 *floating = false; 2668 } 2669 2670 get_veb_exit: 2671 return status; 2672 } 2673 2674 /** 2675 * i40e_aq_add_macvlan 2676 * @hw: pointer to the hw struct 2677 * @seid: VSI for the mac address 2678 * @mv_list: list of macvlans to be added 2679 * @count: length of the list 2680 * @cmd_details: pointer to command details structure or NULL 2681 * 2682 * Add MAC/VLAN addresses to the HW filtering 2683 **/ 2684 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2685 struct i40e_aqc_add_macvlan_element_data *mv_list, 2686 u16 count, struct i40e_asq_cmd_details *cmd_details) 2687 { 2688 struct i40e_aq_desc desc; 2689 struct i40e_aqc_macvlan *cmd = 2690 (struct i40e_aqc_macvlan *)&desc.params.raw; 2691 i40e_status status; 2692 u16 buf_size; 2693 int i; 2694 2695 if (count == 0 || !mv_list || !hw) 2696 return I40E_ERR_PARAM; 2697 2698 buf_size = count * sizeof(*mv_list); 2699 2700 /* prep the rest of the request */ 2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2702 cmd->num_addresses = cpu_to_le16(count); 2703 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2704 cmd->seid[1] = 0; 2705 cmd->seid[2] = 0; 2706 2707 for (i = 0; i < count; i++) 2708 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2709 mv_list[i].flags |= 2710 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2711 2712 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2713 if (buf_size > I40E_AQ_LARGE_BUF) 2714 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2715 2716 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2717 cmd_details); 2718 2719 return status; 2720 } 2721 2722 /** 2723 * i40e_aq_remove_macvlan 2724 * @hw: pointer to the hw struct 2725 * @seid: VSI for the mac address 2726 * @mv_list: list of macvlans to be removed 2727 * @count: length of the list 2728 * @cmd_details: pointer to command details structure or NULL 2729 * 2730 * Remove MAC/VLAN addresses from the HW filtering 2731 **/ 2732 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2733 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2734 u16 count, struct i40e_asq_cmd_details *cmd_details) 2735 { 2736 struct i40e_aq_desc desc; 2737 struct i40e_aqc_macvlan *cmd = 2738 (struct i40e_aqc_macvlan *)&desc.params.raw; 2739 i40e_status status; 2740 u16 buf_size; 2741 2742 if (count == 0 || !mv_list || !hw) 2743 return I40E_ERR_PARAM; 2744 2745 buf_size = count * sizeof(*mv_list); 2746 2747 /* prep the rest of the request */ 2748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2749 cmd->num_addresses = cpu_to_le16(count); 2750 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2751 cmd->seid[1] = 0; 2752 cmd->seid[2] = 0; 2753 2754 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2755 if (buf_size > I40E_AQ_LARGE_BUF) 2756 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2757 2758 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2759 cmd_details); 2760 2761 return status; 2762 } 2763 2764 /** 2765 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2766 * @hw: pointer to the hw struct 2767 * @opcode: AQ opcode for add or delete mirror rule 2768 * @sw_seid: Switch SEID (to which rule refers) 2769 * @rule_type: Rule Type (ingress/egress/VLAN) 2770 * @id: Destination VSI SEID or Rule ID 2771 * @count: length of the list 2772 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2773 * @cmd_details: pointer to command details structure or NULL 2774 * @rule_id: Rule ID returned from FW 2775 * @rule_used: Number of rules used in internal switch 2776 * @rule_free: Number of rules free in internal switch 2777 * 2778 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2779 * VEBs/VEPA elements only 2780 **/ 2781 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2782 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2783 u16 count, __le16 *mr_list, 2784 struct i40e_asq_cmd_details *cmd_details, 2785 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2786 { 2787 struct i40e_aq_desc desc; 2788 struct i40e_aqc_add_delete_mirror_rule *cmd = 2789 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2790 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2791 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2792 i40e_status status; 2793 u16 buf_size; 2794 2795 buf_size = count * sizeof(*mr_list); 2796 2797 /* prep the rest of the request */ 2798 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2799 cmd->seid = cpu_to_le16(sw_seid); 2800 cmd->rule_type = cpu_to_le16(rule_type & 2801 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2802 cmd->num_entries = cpu_to_le16(count); 2803 /* Dest VSI for add, rule_id for delete */ 2804 cmd->destination = cpu_to_le16(id); 2805 if (mr_list) { 2806 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2807 I40E_AQ_FLAG_RD)); 2808 if (buf_size > I40E_AQ_LARGE_BUF) 2809 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2810 } 2811 2812 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2813 cmd_details); 2814 if (!status || 2815 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2816 if (rule_id) 2817 *rule_id = le16_to_cpu(resp->rule_id); 2818 if (rules_used) 2819 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2820 if (rules_free) 2821 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2822 } 2823 return status; 2824 } 2825 2826 /** 2827 * i40e_aq_add_mirrorrule - add a mirror rule 2828 * @hw: pointer to the hw struct 2829 * @sw_seid: Switch SEID (to which rule refers) 2830 * @rule_type: Rule Type (ingress/egress/VLAN) 2831 * @dest_vsi: SEID of VSI to which packets will be mirrored 2832 * @count: length of the list 2833 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2834 * @cmd_details: pointer to command details structure or NULL 2835 * @rule_id: Rule ID returned from FW 2836 * @rule_used: Number of rules used in internal switch 2837 * @rule_free: Number of rules free in internal switch 2838 * 2839 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2840 **/ 2841 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2842 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2843 struct i40e_asq_cmd_details *cmd_details, 2844 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2845 { 2846 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2847 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2848 if (count == 0 || !mr_list) 2849 return I40E_ERR_PARAM; 2850 } 2851 2852 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2853 rule_type, dest_vsi, count, mr_list, 2854 cmd_details, rule_id, rules_used, rules_free); 2855 } 2856 2857 /** 2858 * i40e_aq_delete_mirrorrule - delete a mirror rule 2859 * @hw: pointer to the hw struct 2860 * @sw_seid: Switch SEID (to which rule refers) 2861 * @rule_type: Rule Type (ingress/egress/VLAN) 2862 * @count: length of the list 2863 * @rule_id: Rule ID that is returned in the receive desc as part of 2864 * add_mirrorrule. 2865 * @mr_list: list of mirrored VLAN IDs to be removed 2866 * @cmd_details: pointer to command details structure or NULL 2867 * @rule_used: Number of rules used in internal switch 2868 * @rule_free: Number of rules free in internal switch 2869 * 2870 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2871 **/ 2872 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2873 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2874 struct i40e_asq_cmd_details *cmd_details, 2875 u16 *rules_used, u16 *rules_free) 2876 { 2877 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2878 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2879 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2880 * mirroring. For other rule_type, count and rule_type should 2881 * not matter. 2882 */ 2883 if (count == 0 || !mr_list) 2884 return I40E_ERR_PARAM; 2885 } 2886 2887 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2888 rule_type, rule_id, count, mr_list, 2889 cmd_details, NULL, rules_used, rules_free); 2890 } 2891 2892 /** 2893 * i40e_aq_send_msg_to_vf 2894 * @hw: pointer to the hardware structure 2895 * @vfid: VF id to send msg 2896 * @v_opcode: opcodes for VF-PF communication 2897 * @v_retval: return error code 2898 * @msg: pointer to the msg buffer 2899 * @msglen: msg length 2900 * @cmd_details: pointer to command details 2901 * 2902 * send msg to vf 2903 **/ 2904 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2905 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2906 struct i40e_asq_cmd_details *cmd_details) 2907 { 2908 struct i40e_aq_desc desc; 2909 struct i40e_aqc_pf_vf_message *cmd = 2910 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2911 i40e_status status; 2912 2913 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2914 cmd->id = cpu_to_le32(vfid); 2915 desc.cookie_high = cpu_to_le32(v_opcode); 2916 desc.cookie_low = cpu_to_le32(v_retval); 2917 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2918 if (msglen) { 2919 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2920 I40E_AQ_FLAG_RD)); 2921 if (msglen > I40E_AQ_LARGE_BUF) 2922 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2923 desc.datalen = cpu_to_le16(msglen); 2924 } 2925 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2926 2927 return status; 2928 } 2929 2930 /** 2931 * i40e_aq_debug_read_register 2932 * @hw: pointer to the hw struct 2933 * @reg_addr: register address 2934 * @reg_val: register value 2935 * @cmd_details: pointer to command details structure or NULL 2936 * 2937 * Read the register using the admin queue commands 2938 **/ 2939 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2940 u32 reg_addr, u64 *reg_val, 2941 struct i40e_asq_cmd_details *cmd_details) 2942 { 2943 struct i40e_aq_desc desc; 2944 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2945 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2946 i40e_status status; 2947 2948 if (reg_val == NULL) 2949 return I40E_ERR_PARAM; 2950 2951 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2952 2953 cmd_resp->address = cpu_to_le32(reg_addr); 2954 2955 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2956 2957 if (!status) { 2958 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2959 (u64)le32_to_cpu(cmd_resp->value_low); 2960 } 2961 2962 return status; 2963 } 2964 2965 /** 2966 * i40e_aq_debug_write_register 2967 * @hw: pointer to the hw struct 2968 * @reg_addr: register address 2969 * @reg_val: register value 2970 * @cmd_details: pointer to command details structure or NULL 2971 * 2972 * Write to a register using the admin queue commands 2973 **/ 2974 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2975 u32 reg_addr, u64 reg_val, 2976 struct i40e_asq_cmd_details *cmd_details) 2977 { 2978 struct i40e_aq_desc desc; 2979 struct i40e_aqc_debug_reg_read_write *cmd = 2980 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2981 i40e_status status; 2982 2983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2984 2985 cmd->address = cpu_to_le32(reg_addr); 2986 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2987 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2988 2989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2990 2991 return status; 2992 } 2993 2994 /** 2995 * i40e_aq_request_resource 2996 * @hw: pointer to the hw struct 2997 * @resource: resource id 2998 * @access: access type 2999 * @sdp_number: resource number 3000 * @timeout: the maximum time in ms that the driver may hold the resource 3001 * @cmd_details: pointer to command details structure or NULL 3002 * 3003 * requests common resource using the admin queue commands 3004 **/ 3005 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3006 enum i40e_aq_resources_ids resource, 3007 enum i40e_aq_resource_access_type access, 3008 u8 sdp_number, u64 *timeout, 3009 struct i40e_asq_cmd_details *cmd_details) 3010 { 3011 struct i40e_aq_desc desc; 3012 struct i40e_aqc_request_resource *cmd_resp = 3013 (struct i40e_aqc_request_resource *)&desc.params.raw; 3014 i40e_status status; 3015 3016 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3017 3018 cmd_resp->resource_id = cpu_to_le16(resource); 3019 cmd_resp->access_type = cpu_to_le16(access); 3020 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3021 3022 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3023 /* The completion specifies the maximum time in ms that the driver 3024 * may hold the resource in the Timeout field. 3025 * If the resource is held by someone else, the command completes with 3026 * busy return value and the timeout field indicates the maximum time 3027 * the current owner of the resource has to free it. 3028 */ 3029 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3030 *timeout = le32_to_cpu(cmd_resp->timeout); 3031 3032 return status; 3033 } 3034 3035 /** 3036 * i40e_aq_release_resource 3037 * @hw: pointer to the hw struct 3038 * @resource: resource id 3039 * @sdp_number: resource number 3040 * @cmd_details: pointer to command details structure or NULL 3041 * 3042 * release common resource using the admin queue commands 3043 **/ 3044 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3045 enum i40e_aq_resources_ids resource, 3046 u8 sdp_number, 3047 struct i40e_asq_cmd_details *cmd_details) 3048 { 3049 struct i40e_aq_desc desc; 3050 struct i40e_aqc_request_resource *cmd = 3051 (struct i40e_aqc_request_resource *)&desc.params.raw; 3052 i40e_status status; 3053 3054 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3055 3056 cmd->resource_id = cpu_to_le16(resource); 3057 cmd->resource_number = cpu_to_le32(sdp_number); 3058 3059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3060 3061 return status; 3062 } 3063 3064 /** 3065 * i40e_aq_read_nvm 3066 * @hw: pointer to the hw struct 3067 * @module_pointer: module pointer location in words from the NVM beginning 3068 * @offset: byte offset from the module beginning 3069 * @length: length of the section to be read (in bytes from the offset) 3070 * @data: command buffer (size [bytes] = length) 3071 * @last_command: tells if this is the last command in a series 3072 * @cmd_details: pointer to command details structure or NULL 3073 * 3074 * Read the NVM using the admin queue commands 3075 **/ 3076 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3077 u32 offset, u16 length, void *data, 3078 bool last_command, 3079 struct i40e_asq_cmd_details *cmd_details) 3080 { 3081 struct i40e_aq_desc desc; 3082 struct i40e_aqc_nvm_update *cmd = 3083 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3084 i40e_status status; 3085 3086 /* In offset the highest byte must be zeroed. */ 3087 if (offset & 0xFF000000) { 3088 status = I40E_ERR_PARAM; 3089 goto i40e_aq_read_nvm_exit; 3090 } 3091 3092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3093 3094 /* If this is the last command in a series, set the proper flag. */ 3095 if (last_command) 3096 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3097 cmd->module_pointer = module_pointer; 3098 cmd->offset = cpu_to_le32(offset); 3099 cmd->length = cpu_to_le16(length); 3100 3101 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3102 if (length > I40E_AQ_LARGE_BUF) 3103 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3104 3105 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3106 3107 i40e_aq_read_nvm_exit: 3108 return status; 3109 } 3110 3111 /** 3112 * i40e_aq_erase_nvm 3113 * @hw: pointer to the hw struct 3114 * @module_pointer: module pointer location in words from the NVM beginning 3115 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3116 * @length: length of the section to be erased (expressed in 4 KB) 3117 * @last_command: tells if this is the last command in a series 3118 * @cmd_details: pointer to command details structure or NULL 3119 * 3120 * Erase the NVM sector using the admin queue commands 3121 **/ 3122 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3123 u32 offset, u16 length, bool last_command, 3124 struct i40e_asq_cmd_details *cmd_details) 3125 { 3126 struct i40e_aq_desc desc; 3127 struct i40e_aqc_nvm_update *cmd = 3128 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3129 i40e_status status; 3130 3131 /* In offset the highest byte must be zeroed. */ 3132 if (offset & 0xFF000000) { 3133 status = I40E_ERR_PARAM; 3134 goto i40e_aq_erase_nvm_exit; 3135 } 3136 3137 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3138 3139 /* If this is the last command in a series, set the proper flag. */ 3140 if (last_command) 3141 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3142 cmd->module_pointer = module_pointer; 3143 cmd->offset = cpu_to_le32(offset); 3144 cmd->length = cpu_to_le16(length); 3145 3146 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3147 3148 i40e_aq_erase_nvm_exit: 3149 return status; 3150 } 3151 3152 /** 3153 * i40e_parse_discover_capabilities 3154 * @hw: pointer to the hw struct 3155 * @buff: pointer to a buffer containing device/function capability records 3156 * @cap_count: number of capability records in the list 3157 * @list_type_opc: type of capabilities list to parse 3158 * 3159 * Parse the device/function capabilities list. 3160 **/ 3161 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3162 u32 cap_count, 3163 enum i40e_admin_queue_opc list_type_opc) 3164 { 3165 struct i40e_aqc_list_capabilities_element_resp *cap; 3166 u32 valid_functions, num_functions; 3167 u32 number, logical_id, phys_id; 3168 struct i40e_hw_capabilities *p; 3169 u8 major_rev; 3170 u32 i = 0; 3171 u16 id; 3172 3173 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3174 3175 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3176 p = &hw->dev_caps; 3177 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3178 p = &hw->func_caps; 3179 else 3180 return; 3181 3182 for (i = 0; i < cap_count; i++, cap++) { 3183 id = le16_to_cpu(cap->id); 3184 number = le32_to_cpu(cap->number); 3185 logical_id = le32_to_cpu(cap->logical_id); 3186 phys_id = le32_to_cpu(cap->phys_id); 3187 major_rev = cap->major_rev; 3188 3189 switch (id) { 3190 case I40E_AQ_CAP_ID_SWITCH_MODE: 3191 p->switch_mode = number; 3192 break; 3193 case I40E_AQ_CAP_ID_MNG_MODE: 3194 p->management_mode = number; 3195 if (major_rev > 1) { 3196 p->mng_protocols_over_mctp = logical_id; 3197 i40e_debug(hw, I40E_DEBUG_INIT, 3198 "HW Capability: Protocols over MCTP = %d\n", 3199 p->mng_protocols_over_mctp); 3200 } else { 3201 p->mng_protocols_over_mctp = 0; 3202 } 3203 break; 3204 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3205 p->npar_enable = number; 3206 break; 3207 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3208 p->os2bmc = number; 3209 break; 3210 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3211 p->valid_functions = number; 3212 break; 3213 case I40E_AQ_CAP_ID_SRIOV: 3214 if (number == 1) 3215 p->sr_iov_1_1 = true; 3216 break; 3217 case I40E_AQ_CAP_ID_VF: 3218 p->num_vfs = number; 3219 p->vf_base_id = logical_id; 3220 break; 3221 case I40E_AQ_CAP_ID_VMDQ: 3222 if (number == 1) 3223 p->vmdq = true; 3224 break; 3225 case I40E_AQ_CAP_ID_8021QBG: 3226 if (number == 1) 3227 p->evb_802_1_qbg = true; 3228 break; 3229 case I40E_AQ_CAP_ID_8021QBR: 3230 if (number == 1) 3231 p->evb_802_1_qbh = true; 3232 break; 3233 case I40E_AQ_CAP_ID_VSI: 3234 p->num_vsis = number; 3235 break; 3236 case I40E_AQ_CAP_ID_DCB: 3237 if (number == 1) { 3238 p->dcb = true; 3239 p->enabled_tcmap = logical_id; 3240 p->maxtc = phys_id; 3241 } 3242 break; 3243 case I40E_AQ_CAP_ID_FCOE: 3244 if (number == 1) 3245 p->fcoe = true; 3246 break; 3247 case I40E_AQ_CAP_ID_ISCSI: 3248 if (number == 1) 3249 p->iscsi = true; 3250 break; 3251 case I40E_AQ_CAP_ID_RSS: 3252 p->rss = true; 3253 p->rss_table_size = number; 3254 p->rss_table_entry_width = logical_id; 3255 break; 3256 case I40E_AQ_CAP_ID_RXQ: 3257 p->num_rx_qp = number; 3258 p->base_queue = phys_id; 3259 break; 3260 case I40E_AQ_CAP_ID_TXQ: 3261 p->num_tx_qp = number; 3262 p->base_queue = phys_id; 3263 break; 3264 case I40E_AQ_CAP_ID_MSIX: 3265 p->num_msix_vectors = number; 3266 i40e_debug(hw, I40E_DEBUG_INIT, 3267 "HW Capability: MSIX vector count = %d\n", 3268 p->num_msix_vectors); 3269 break; 3270 case I40E_AQ_CAP_ID_VF_MSIX: 3271 p->num_msix_vectors_vf = number; 3272 break; 3273 case I40E_AQ_CAP_ID_FLEX10: 3274 if (major_rev == 1) { 3275 if (number == 1) { 3276 p->flex10_enable = true; 3277 p->flex10_capable = true; 3278 } 3279 } else { 3280 /* Capability revision >= 2 */ 3281 if (number & 1) 3282 p->flex10_enable = true; 3283 if (number & 2) 3284 p->flex10_capable = true; 3285 } 3286 p->flex10_mode = logical_id; 3287 p->flex10_status = phys_id; 3288 break; 3289 case I40E_AQ_CAP_ID_CEM: 3290 if (number == 1) 3291 p->mgmt_cem = true; 3292 break; 3293 case I40E_AQ_CAP_ID_IWARP: 3294 if (number == 1) 3295 p->iwarp = true; 3296 break; 3297 case I40E_AQ_CAP_ID_LED: 3298 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3299 p->led[phys_id] = true; 3300 break; 3301 case I40E_AQ_CAP_ID_SDP: 3302 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3303 p->sdp[phys_id] = true; 3304 break; 3305 case I40E_AQ_CAP_ID_MDIO: 3306 if (number == 1) { 3307 p->mdio_port_num = phys_id; 3308 p->mdio_port_mode = logical_id; 3309 } 3310 break; 3311 case I40E_AQ_CAP_ID_1588: 3312 if (number == 1) 3313 p->ieee_1588 = true; 3314 break; 3315 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3316 p->fd = true; 3317 p->fd_filters_guaranteed = number; 3318 p->fd_filters_best_effort = logical_id; 3319 break; 3320 case I40E_AQ_CAP_ID_WSR_PROT: 3321 p->wr_csr_prot = (u64)number; 3322 p->wr_csr_prot |= (u64)logical_id << 32; 3323 break; 3324 case I40E_AQ_CAP_ID_NVM_MGMT: 3325 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3326 p->sec_rev_disabled = true; 3327 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3328 p->update_disabled = true; 3329 break; 3330 default: 3331 break; 3332 } 3333 } 3334 3335 if (p->fcoe) 3336 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3337 3338 /* Software override ensuring FCoE is disabled if npar or mfp 3339 * mode because it is not supported in these modes. 3340 */ 3341 if (p->npar_enable || p->flex10_enable) 3342 p->fcoe = false; 3343 3344 /* count the enabled ports (aka the "not disabled" ports) */ 3345 hw->num_ports = 0; 3346 for (i = 0; i < 4; i++) { 3347 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3348 u64 port_cfg = 0; 3349 3350 /* use AQ read to get the physical register offset instead 3351 * of the port relative offset 3352 */ 3353 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3354 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3355 hw->num_ports++; 3356 } 3357 3358 valid_functions = p->valid_functions; 3359 num_functions = 0; 3360 while (valid_functions) { 3361 if (valid_functions & 1) 3362 num_functions++; 3363 valid_functions >>= 1; 3364 } 3365 3366 /* partition id is 1-based, and functions are evenly spread 3367 * across the ports as partitions 3368 */ 3369 if (hw->num_ports != 0) { 3370 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3371 hw->num_partitions = num_functions / hw->num_ports; 3372 } 3373 3374 /* additional HW specific goodies that might 3375 * someday be HW version specific 3376 */ 3377 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3378 } 3379 3380 /** 3381 * i40e_aq_discover_capabilities 3382 * @hw: pointer to the hw struct 3383 * @buff: a virtual buffer to hold the capabilities 3384 * @buff_size: Size of the virtual buffer 3385 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3386 * @list_type_opc: capabilities type to discover - pass in the command opcode 3387 * @cmd_details: pointer to command details structure or NULL 3388 * 3389 * Get the device capabilities descriptions from the firmware 3390 **/ 3391 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3392 void *buff, u16 buff_size, u16 *data_size, 3393 enum i40e_admin_queue_opc list_type_opc, 3394 struct i40e_asq_cmd_details *cmd_details) 3395 { 3396 struct i40e_aqc_list_capabilites *cmd; 3397 struct i40e_aq_desc desc; 3398 i40e_status status = 0; 3399 3400 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3401 3402 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3403 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3404 status = I40E_ERR_PARAM; 3405 goto exit; 3406 } 3407 3408 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3409 3410 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3411 if (buff_size > I40E_AQ_LARGE_BUF) 3412 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3413 3414 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3415 *data_size = le16_to_cpu(desc.datalen); 3416 3417 if (status) 3418 goto exit; 3419 3420 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3421 list_type_opc); 3422 3423 exit: 3424 return status; 3425 } 3426 3427 /** 3428 * i40e_aq_update_nvm 3429 * @hw: pointer to the hw struct 3430 * @module_pointer: module pointer location in words from the NVM beginning 3431 * @offset: byte offset from the module beginning 3432 * @length: length of the section to be written (in bytes from the offset) 3433 * @data: command buffer (size [bytes] = length) 3434 * @last_command: tells if this is the last command in a series 3435 * @cmd_details: pointer to command details structure or NULL 3436 * 3437 * Update the NVM using the admin queue commands 3438 **/ 3439 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3440 u32 offset, u16 length, void *data, 3441 bool last_command, 3442 struct i40e_asq_cmd_details *cmd_details) 3443 { 3444 struct i40e_aq_desc desc; 3445 struct i40e_aqc_nvm_update *cmd = 3446 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3447 i40e_status status; 3448 3449 /* In offset the highest byte must be zeroed. */ 3450 if (offset & 0xFF000000) { 3451 status = I40E_ERR_PARAM; 3452 goto i40e_aq_update_nvm_exit; 3453 } 3454 3455 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3456 3457 /* If this is the last command in a series, set the proper flag. */ 3458 if (last_command) 3459 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3460 cmd->module_pointer = module_pointer; 3461 cmd->offset = cpu_to_le32(offset); 3462 cmd->length = cpu_to_le16(length); 3463 3464 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3465 if (length > I40E_AQ_LARGE_BUF) 3466 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3467 3468 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3469 3470 i40e_aq_update_nvm_exit: 3471 return status; 3472 } 3473 3474 /** 3475 * i40e_aq_get_lldp_mib 3476 * @hw: pointer to the hw struct 3477 * @bridge_type: type of bridge requested 3478 * @mib_type: Local, Remote or both Local and Remote MIBs 3479 * @buff: pointer to a user supplied buffer to store the MIB block 3480 * @buff_size: size of the buffer (in bytes) 3481 * @local_len : length of the returned Local LLDP MIB 3482 * @remote_len: length of the returned Remote LLDP MIB 3483 * @cmd_details: pointer to command details structure or NULL 3484 * 3485 * Requests the complete LLDP MIB (entire packet). 3486 **/ 3487 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3488 u8 mib_type, void *buff, u16 buff_size, 3489 u16 *local_len, u16 *remote_len, 3490 struct i40e_asq_cmd_details *cmd_details) 3491 { 3492 struct i40e_aq_desc desc; 3493 struct i40e_aqc_lldp_get_mib *cmd = 3494 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3495 struct i40e_aqc_lldp_get_mib *resp = 3496 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3497 i40e_status status; 3498 3499 if (buff_size == 0 || !buff) 3500 return I40E_ERR_PARAM; 3501 3502 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3503 /* Indirect Command */ 3504 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3505 3506 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3507 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3508 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3509 3510 desc.datalen = cpu_to_le16(buff_size); 3511 3512 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3513 if (buff_size > I40E_AQ_LARGE_BUF) 3514 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3515 3516 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3517 if (!status) { 3518 if (local_len != NULL) 3519 *local_len = le16_to_cpu(resp->local_len); 3520 if (remote_len != NULL) 3521 *remote_len = le16_to_cpu(resp->remote_len); 3522 } 3523 3524 return status; 3525 } 3526 3527 /** 3528 * i40e_aq_cfg_lldp_mib_change_event 3529 * @hw: pointer to the hw struct 3530 * @enable_update: Enable or Disable event posting 3531 * @cmd_details: pointer to command details structure or NULL 3532 * 3533 * Enable or Disable posting of an event on ARQ when LLDP MIB 3534 * associated with the interface changes 3535 **/ 3536 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3537 bool enable_update, 3538 struct i40e_asq_cmd_details *cmd_details) 3539 { 3540 struct i40e_aq_desc desc; 3541 struct i40e_aqc_lldp_update_mib *cmd = 3542 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3543 i40e_status status; 3544 3545 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3546 3547 if (!enable_update) 3548 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3549 3550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3551 3552 return status; 3553 } 3554 3555 /** 3556 * i40e_aq_stop_lldp 3557 * @hw: pointer to the hw struct 3558 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3559 * @cmd_details: pointer to command details structure or NULL 3560 * 3561 * Stop or Shutdown the embedded LLDP Agent 3562 **/ 3563 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3564 struct i40e_asq_cmd_details *cmd_details) 3565 { 3566 struct i40e_aq_desc desc; 3567 struct i40e_aqc_lldp_stop *cmd = 3568 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3569 i40e_status status; 3570 3571 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3572 3573 if (shutdown_agent) 3574 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3575 3576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3577 3578 return status; 3579 } 3580 3581 /** 3582 * i40e_aq_start_lldp 3583 * @hw: pointer to the hw struct 3584 * @cmd_details: pointer to command details structure or NULL 3585 * 3586 * Start the embedded LLDP Agent on all ports. 3587 **/ 3588 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 3589 struct i40e_asq_cmd_details *cmd_details) 3590 { 3591 struct i40e_aq_desc desc; 3592 struct i40e_aqc_lldp_start *cmd = 3593 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3594 i40e_status status; 3595 3596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3597 3598 cmd->command = I40E_AQ_LLDP_AGENT_START; 3599 3600 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3601 3602 return status; 3603 } 3604 3605 /** 3606 * i40e_aq_get_cee_dcb_config 3607 * @hw: pointer to the hw struct 3608 * @buff: response buffer that stores CEE operational configuration 3609 * @buff_size: size of the buffer passed 3610 * @cmd_details: pointer to command details structure or NULL 3611 * 3612 * Get CEE DCBX mode operational configuration from firmware 3613 **/ 3614 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3615 void *buff, u16 buff_size, 3616 struct i40e_asq_cmd_details *cmd_details) 3617 { 3618 struct i40e_aq_desc desc; 3619 i40e_status status; 3620 3621 if (buff_size == 0 || !buff) 3622 return I40E_ERR_PARAM; 3623 3624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3625 3626 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3627 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3628 cmd_details); 3629 3630 return status; 3631 } 3632 3633 /** 3634 * i40e_aq_add_udp_tunnel 3635 * @hw: pointer to the hw struct 3636 * @udp_port: the UDP port to add in Host byte order 3637 * @header_len: length of the tunneling header length in DWords 3638 * @protocol_index: protocol index type 3639 * @filter_index: pointer to filter index 3640 * @cmd_details: pointer to command details structure or NULL 3641 * 3642 * Note: Firmware expects the udp_port value to be in Little Endian format, 3643 * and this function will call cpu_to_le16 to convert from Host byte order to 3644 * Little Endian order. 3645 **/ 3646 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3647 u16 udp_port, u8 protocol_index, 3648 u8 *filter_index, 3649 struct i40e_asq_cmd_details *cmd_details) 3650 { 3651 struct i40e_aq_desc desc; 3652 struct i40e_aqc_add_udp_tunnel *cmd = 3653 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3654 struct i40e_aqc_del_udp_tunnel_completion *resp = 3655 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3656 i40e_status status; 3657 3658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3659 3660 cmd->udp_port = cpu_to_le16(udp_port); 3661 cmd->protocol_type = protocol_index; 3662 3663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3664 3665 if (!status && filter_index) 3666 *filter_index = resp->index; 3667 3668 return status; 3669 } 3670 3671 /** 3672 * i40e_aq_del_udp_tunnel 3673 * @hw: pointer to the hw struct 3674 * @index: filter index 3675 * @cmd_details: pointer to command details structure or NULL 3676 **/ 3677 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3678 struct i40e_asq_cmd_details *cmd_details) 3679 { 3680 struct i40e_aq_desc desc; 3681 struct i40e_aqc_remove_udp_tunnel *cmd = 3682 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3683 i40e_status status; 3684 3685 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3686 3687 cmd->index = index; 3688 3689 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3690 3691 return status; 3692 } 3693 3694 /** 3695 * i40e_aq_delete_element - Delete switch element 3696 * @hw: pointer to the hw struct 3697 * @seid: the SEID to delete from the switch 3698 * @cmd_details: pointer to command details structure or NULL 3699 * 3700 * This deletes a switch element from the switch. 3701 **/ 3702 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3703 struct i40e_asq_cmd_details *cmd_details) 3704 { 3705 struct i40e_aq_desc desc; 3706 struct i40e_aqc_switch_seid *cmd = 3707 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3708 i40e_status status; 3709 3710 if (seid == 0) 3711 return I40E_ERR_PARAM; 3712 3713 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3714 3715 cmd->seid = cpu_to_le16(seid); 3716 3717 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3718 3719 return status; 3720 } 3721 3722 /** 3723 * i40e_aq_dcb_updated - DCB Updated Command 3724 * @hw: pointer to the hw struct 3725 * @cmd_details: pointer to command details structure or NULL 3726 * 3727 * EMP will return when the shared RPB settings have been 3728 * recomputed and modified. The retval field in the descriptor 3729 * will be set to 0 when RPB is modified. 3730 **/ 3731 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3732 struct i40e_asq_cmd_details *cmd_details) 3733 { 3734 struct i40e_aq_desc desc; 3735 i40e_status status; 3736 3737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3738 3739 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3740 3741 return status; 3742 } 3743 3744 /** 3745 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3746 * @hw: pointer to the hw struct 3747 * @seid: seid for the physical port/switching component/vsi 3748 * @buff: Indirect buffer to hold data parameters and response 3749 * @buff_size: Indirect buffer size 3750 * @opcode: Tx scheduler AQ command opcode 3751 * @cmd_details: pointer to command details structure or NULL 3752 * 3753 * Generic command handler for Tx scheduler AQ commands 3754 **/ 3755 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3756 void *buff, u16 buff_size, 3757 enum i40e_admin_queue_opc opcode, 3758 struct i40e_asq_cmd_details *cmd_details) 3759 { 3760 struct i40e_aq_desc desc; 3761 struct i40e_aqc_tx_sched_ind *cmd = 3762 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3763 i40e_status status; 3764 bool cmd_param_flag = false; 3765 3766 switch (opcode) { 3767 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3768 case i40e_aqc_opc_configure_vsi_tc_bw: 3769 case i40e_aqc_opc_enable_switching_comp_ets: 3770 case i40e_aqc_opc_modify_switching_comp_ets: 3771 case i40e_aqc_opc_disable_switching_comp_ets: 3772 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3773 case i40e_aqc_opc_configure_switching_comp_bw_config: 3774 cmd_param_flag = true; 3775 break; 3776 case i40e_aqc_opc_query_vsi_bw_config: 3777 case i40e_aqc_opc_query_vsi_ets_sla_config: 3778 case i40e_aqc_opc_query_switching_comp_ets_config: 3779 case i40e_aqc_opc_query_port_ets_config: 3780 case i40e_aqc_opc_query_switching_comp_bw_config: 3781 cmd_param_flag = false; 3782 break; 3783 default: 3784 return I40E_ERR_PARAM; 3785 } 3786 3787 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3788 3789 /* Indirect command */ 3790 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3791 if (cmd_param_flag) 3792 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3793 if (buff_size > I40E_AQ_LARGE_BUF) 3794 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3795 3796 desc.datalen = cpu_to_le16(buff_size); 3797 3798 cmd->vsi_seid = cpu_to_le16(seid); 3799 3800 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3801 3802 return status; 3803 } 3804 3805 /** 3806 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3807 * @hw: pointer to the hw struct 3808 * @seid: VSI seid 3809 * @credit: BW limit credits (0 = disabled) 3810 * @max_credit: Max BW limit credits 3811 * @cmd_details: pointer to command details structure or NULL 3812 **/ 3813 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3814 u16 seid, u16 credit, u8 max_credit, 3815 struct i40e_asq_cmd_details *cmd_details) 3816 { 3817 struct i40e_aq_desc desc; 3818 struct i40e_aqc_configure_vsi_bw_limit *cmd = 3819 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 3820 i40e_status status; 3821 3822 i40e_fill_default_direct_cmd_desc(&desc, 3823 i40e_aqc_opc_configure_vsi_bw_limit); 3824 3825 cmd->vsi_seid = cpu_to_le16(seid); 3826 cmd->credit = cpu_to_le16(credit); 3827 cmd->max_credit = max_credit; 3828 3829 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3830 3831 return status; 3832 } 3833 3834 /** 3835 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 3836 * @hw: pointer to the hw struct 3837 * @seid: VSI seid 3838 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 3839 * @cmd_details: pointer to command details structure or NULL 3840 **/ 3841 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 3842 u16 seid, 3843 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 3844 struct i40e_asq_cmd_details *cmd_details) 3845 { 3846 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3847 i40e_aqc_opc_configure_vsi_tc_bw, 3848 cmd_details); 3849 } 3850 3851 /** 3852 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 3853 * @hw: pointer to the hw struct 3854 * @seid: seid of the switching component connected to Physical Port 3855 * @ets_data: Buffer holding ETS parameters 3856 * @cmd_details: pointer to command details structure or NULL 3857 **/ 3858 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 3859 u16 seid, 3860 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 3861 enum i40e_admin_queue_opc opcode, 3862 struct i40e_asq_cmd_details *cmd_details) 3863 { 3864 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 3865 sizeof(*ets_data), opcode, cmd_details); 3866 } 3867 3868 /** 3869 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 3870 * @hw: pointer to the hw struct 3871 * @seid: seid of the switching component 3872 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 3873 * @cmd_details: pointer to command details structure or NULL 3874 **/ 3875 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 3876 u16 seid, 3877 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 3878 struct i40e_asq_cmd_details *cmd_details) 3879 { 3880 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3881 i40e_aqc_opc_configure_switching_comp_bw_config, 3882 cmd_details); 3883 } 3884 3885 /** 3886 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 3887 * @hw: pointer to the hw struct 3888 * @seid: seid of the VSI 3889 * @bw_data: Buffer to hold VSI BW configuration 3890 * @cmd_details: pointer to command details structure or NULL 3891 **/ 3892 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 3893 u16 seid, 3894 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 3895 struct i40e_asq_cmd_details *cmd_details) 3896 { 3897 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3898 i40e_aqc_opc_query_vsi_bw_config, 3899 cmd_details); 3900 } 3901 3902 /** 3903 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 3904 * @hw: pointer to the hw struct 3905 * @seid: seid of the VSI 3906 * @bw_data: Buffer to hold VSI BW configuration per TC 3907 * @cmd_details: pointer to command details structure or NULL 3908 **/ 3909 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 3910 u16 seid, 3911 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 3912 struct i40e_asq_cmd_details *cmd_details) 3913 { 3914 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3915 i40e_aqc_opc_query_vsi_ets_sla_config, 3916 cmd_details); 3917 } 3918 3919 /** 3920 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 3921 * @hw: pointer to the hw struct 3922 * @seid: seid of the switching component 3923 * @bw_data: Buffer to hold switching component's per TC BW config 3924 * @cmd_details: pointer to command details structure or NULL 3925 **/ 3926 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 3927 u16 seid, 3928 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 3929 struct i40e_asq_cmd_details *cmd_details) 3930 { 3931 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3932 i40e_aqc_opc_query_switching_comp_ets_config, 3933 cmd_details); 3934 } 3935 3936 /** 3937 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 3938 * @hw: pointer to the hw struct 3939 * @seid: seid of the VSI or switching component connected to Physical Port 3940 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 3941 * @cmd_details: pointer to command details structure or NULL 3942 **/ 3943 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 3944 u16 seid, 3945 struct i40e_aqc_query_port_ets_config_resp *bw_data, 3946 struct i40e_asq_cmd_details *cmd_details) 3947 { 3948 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3949 i40e_aqc_opc_query_port_ets_config, 3950 cmd_details); 3951 } 3952 3953 /** 3954 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 3955 * @hw: pointer to the hw struct 3956 * @seid: seid of the switching component 3957 * @bw_data: Buffer to hold switching component's BW configuration 3958 * @cmd_details: pointer to command details structure or NULL 3959 **/ 3960 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 3961 u16 seid, 3962 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 3963 struct i40e_asq_cmd_details *cmd_details) 3964 { 3965 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 3966 i40e_aqc_opc_query_switching_comp_bw_config, 3967 cmd_details); 3968 } 3969 3970 /** 3971 * i40e_validate_filter_settings 3972 * @hw: pointer to the hardware structure 3973 * @settings: Filter control settings 3974 * 3975 * Check and validate the filter control settings passed. 3976 * The function checks for the valid filter/context sizes being 3977 * passed for FCoE and PE. 3978 * 3979 * Returns 0 if the values passed are valid and within 3980 * range else returns an error. 3981 **/ 3982 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 3983 struct i40e_filter_control_settings *settings) 3984 { 3985 u32 fcoe_cntx_size, fcoe_filt_size; 3986 u32 pe_cntx_size, pe_filt_size; 3987 u32 fcoe_fmax; 3988 u32 val; 3989 3990 /* Validate FCoE settings passed */ 3991 switch (settings->fcoe_filt_num) { 3992 case I40E_HASH_FILTER_SIZE_1K: 3993 case I40E_HASH_FILTER_SIZE_2K: 3994 case I40E_HASH_FILTER_SIZE_4K: 3995 case I40E_HASH_FILTER_SIZE_8K: 3996 case I40E_HASH_FILTER_SIZE_16K: 3997 case I40E_HASH_FILTER_SIZE_32K: 3998 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3999 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4000 break; 4001 default: 4002 return I40E_ERR_PARAM; 4003 } 4004 4005 switch (settings->fcoe_cntx_num) { 4006 case I40E_DMA_CNTX_SIZE_512: 4007 case I40E_DMA_CNTX_SIZE_1K: 4008 case I40E_DMA_CNTX_SIZE_2K: 4009 case I40E_DMA_CNTX_SIZE_4K: 4010 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4011 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4012 break; 4013 default: 4014 return I40E_ERR_PARAM; 4015 } 4016 4017 /* Validate PE settings passed */ 4018 switch (settings->pe_filt_num) { 4019 case I40E_HASH_FILTER_SIZE_1K: 4020 case I40E_HASH_FILTER_SIZE_2K: 4021 case I40E_HASH_FILTER_SIZE_4K: 4022 case I40E_HASH_FILTER_SIZE_8K: 4023 case I40E_HASH_FILTER_SIZE_16K: 4024 case I40E_HASH_FILTER_SIZE_32K: 4025 case I40E_HASH_FILTER_SIZE_64K: 4026 case I40E_HASH_FILTER_SIZE_128K: 4027 case I40E_HASH_FILTER_SIZE_256K: 4028 case I40E_HASH_FILTER_SIZE_512K: 4029 case I40E_HASH_FILTER_SIZE_1M: 4030 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4031 pe_filt_size <<= (u32)settings->pe_filt_num; 4032 break; 4033 default: 4034 return I40E_ERR_PARAM; 4035 } 4036 4037 switch (settings->pe_cntx_num) { 4038 case I40E_DMA_CNTX_SIZE_512: 4039 case I40E_DMA_CNTX_SIZE_1K: 4040 case I40E_DMA_CNTX_SIZE_2K: 4041 case I40E_DMA_CNTX_SIZE_4K: 4042 case I40E_DMA_CNTX_SIZE_8K: 4043 case I40E_DMA_CNTX_SIZE_16K: 4044 case I40E_DMA_CNTX_SIZE_32K: 4045 case I40E_DMA_CNTX_SIZE_64K: 4046 case I40E_DMA_CNTX_SIZE_128K: 4047 case I40E_DMA_CNTX_SIZE_256K: 4048 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4049 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4050 break; 4051 default: 4052 return I40E_ERR_PARAM; 4053 } 4054 4055 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4056 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4057 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4058 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4059 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4060 return I40E_ERR_INVALID_SIZE; 4061 4062 return 0; 4063 } 4064 4065 /** 4066 * i40e_set_filter_control 4067 * @hw: pointer to the hardware structure 4068 * @settings: Filter control settings 4069 * 4070 * Set the Queue Filters for PE/FCoE and enable filters required 4071 * for a single PF. It is expected that these settings are programmed 4072 * at the driver initialization time. 4073 **/ 4074 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4075 struct i40e_filter_control_settings *settings) 4076 { 4077 i40e_status ret = 0; 4078 u32 hash_lut_size = 0; 4079 u32 val; 4080 4081 if (!settings) 4082 return I40E_ERR_PARAM; 4083 4084 /* Validate the input settings */ 4085 ret = i40e_validate_filter_settings(hw, settings); 4086 if (ret) 4087 return ret; 4088 4089 /* Read the PF Queue Filter control register */ 4090 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4091 4092 /* Program required PE hash buckets for the PF */ 4093 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4094 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4095 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4096 /* Program required PE contexts for the PF */ 4097 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4098 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4099 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4100 4101 /* Program required FCoE hash buckets for the PF */ 4102 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4103 val |= ((u32)settings->fcoe_filt_num << 4104 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4105 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4106 /* Program required FCoE DDP contexts for the PF */ 4107 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4108 val |= ((u32)settings->fcoe_cntx_num << 4109 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4110 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4111 4112 /* Program Hash LUT size for the PF */ 4113 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4114 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4115 hash_lut_size = 1; 4116 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4117 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4118 4119 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4120 if (settings->enable_fdir) 4121 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4122 if (settings->enable_ethtype) 4123 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4124 if (settings->enable_macvlan) 4125 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4126 4127 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4128 4129 return 0; 4130 } 4131 4132 /** 4133 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4134 * @hw: pointer to the hw struct 4135 * @mac_addr: MAC address to use in the filter 4136 * @ethtype: Ethertype to use in the filter 4137 * @flags: Flags that needs to be applied to the filter 4138 * @vsi_seid: seid of the control VSI 4139 * @queue: VSI queue number to send the packet to 4140 * @is_add: Add control packet filter if True else remove 4141 * @stats: Structure to hold information on control filter counts 4142 * @cmd_details: pointer to command details structure or NULL 4143 * 4144 * This command will Add or Remove control packet filter for a control VSI. 4145 * In return it will update the total number of perfect filter count in 4146 * the stats member. 4147 **/ 4148 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4149 u8 *mac_addr, u16 ethtype, u16 flags, 4150 u16 vsi_seid, u16 queue, bool is_add, 4151 struct i40e_control_filter_stats *stats, 4152 struct i40e_asq_cmd_details *cmd_details) 4153 { 4154 struct i40e_aq_desc desc; 4155 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4156 (struct i40e_aqc_add_remove_control_packet_filter *) 4157 &desc.params.raw; 4158 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4159 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4160 &desc.params.raw; 4161 i40e_status status; 4162 4163 if (vsi_seid == 0) 4164 return I40E_ERR_PARAM; 4165 4166 if (is_add) { 4167 i40e_fill_default_direct_cmd_desc(&desc, 4168 i40e_aqc_opc_add_control_packet_filter); 4169 cmd->queue = cpu_to_le16(queue); 4170 } else { 4171 i40e_fill_default_direct_cmd_desc(&desc, 4172 i40e_aqc_opc_remove_control_packet_filter); 4173 } 4174 4175 if (mac_addr) 4176 ether_addr_copy(cmd->mac, mac_addr); 4177 4178 cmd->etype = cpu_to_le16(ethtype); 4179 cmd->flags = cpu_to_le16(flags); 4180 cmd->seid = cpu_to_le16(vsi_seid); 4181 4182 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4183 4184 if (!status && stats) { 4185 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4186 stats->etype_used = le16_to_cpu(resp->etype_used); 4187 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4188 stats->etype_free = le16_to_cpu(resp->etype_free); 4189 } 4190 4191 return status; 4192 } 4193 4194 /** 4195 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4196 * @hw: pointer to the hw struct 4197 * @seid: VSI seid to add ethertype filter from 4198 **/ 4199 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4200 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4201 u16 seid) 4202 { 4203 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4204 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4205 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4206 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4207 i40e_status status; 4208 4209 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4210 seid, 0, true, NULL, 4211 NULL); 4212 if (status) 4213 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4214 } 4215 4216 /** 4217 * i40e_aq_alternate_read 4218 * @hw: pointer to the hardware structure 4219 * @reg_addr0: address of first dword to be read 4220 * @reg_val0: pointer for data read from 'reg_addr0' 4221 * @reg_addr1: address of second dword to be read 4222 * @reg_val1: pointer for data read from 'reg_addr1' 4223 * 4224 * Read one or two dwords from alternate structure. Fields are indicated 4225 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4226 * is not passed then only register at 'reg_addr0' is read. 4227 * 4228 **/ 4229 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4230 u32 reg_addr0, u32 *reg_val0, 4231 u32 reg_addr1, u32 *reg_val1) 4232 { 4233 struct i40e_aq_desc desc; 4234 struct i40e_aqc_alternate_write *cmd_resp = 4235 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4236 i40e_status status; 4237 4238 if (!reg_val0) 4239 return I40E_ERR_PARAM; 4240 4241 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4242 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4243 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4244 4245 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4246 4247 if (!status) { 4248 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4249 4250 if (reg_val1) 4251 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4252 } 4253 4254 return status; 4255 } 4256 4257 /** 4258 * i40e_aq_resume_port_tx 4259 * @hw: pointer to the hardware structure 4260 * @cmd_details: pointer to command details structure or NULL 4261 * 4262 * Resume port's Tx traffic 4263 **/ 4264 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4265 struct i40e_asq_cmd_details *cmd_details) 4266 { 4267 struct i40e_aq_desc desc; 4268 i40e_status status; 4269 4270 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4271 4272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4273 4274 return status; 4275 } 4276 4277 /** 4278 * i40e_set_pci_config_data - store PCI bus info 4279 * @hw: pointer to hardware structure 4280 * @link_status: the link status word from PCI config space 4281 * 4282 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4283 **/ 4284 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4285 { 4286 hw->bus.type = i40e_bus_type_pci_express; 4287 4288 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4289 case PCI_EXP_LNKSTA_NLW_X1: 4290 hw->bus.width = i40e_bus_width_pcie_x1; 4291 break; 4292 case PCI_EXP_LNKSTA_NLW_X2: 4293 hw->bus.width = i40e_bus_width_pcie_x2; 4294 break; 4295 case PCI_EXP_LNKSTA_NLW_X4: 4296 hw->bus.width = i40e_bus_width_pcie_x4; 4297 break; 4298 case PCI_EXP_LNKSTA_NLW_X8: 4299 hw->bus.width = i40e_bus_width_pcie_x8; 4300 break; 4301 default: 4302 hw->bus.width = i40e_bus_width_unknown; 4303 break; 4304 } 4305 4306 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4307 case PCI_EXP_LNKSTA_CLS_2_5GB: 4308 hw->bus.speed = i40e_bus_speed_2500; 4309 break; 4310 case PCI_EXP_LNKSTA_CLS_5_0GB: 4311 hw->bus.speed = i40e_bus_speed_5000; 4312 break; 4313 case PCI_EXP_LNKSTA_CLS_8_0GB: 4314 hw->bus.speed = i40e_bus_speed_8000; 4315 break; 4316 default: 4317 hw->bus.speed = i40e_bus_speed_unknown; 4318 break; 4319 } 4320 } 4321 4322 /** 4323 * i40e_aq_debug_dump 4324 * @hw: pointer to the hardware structure 4325 * @cluster_id: specific cluster to dump 4326 * @table_id: table id within cluster 4327 * @start_index: index of line in the block to read 4328 * @buff_size: dump buffer size 4329 * @buff: dump buffer 4330 * @ret_buff_size: actual buffer size returned 4331 * @ret_next_table: next block to read 4332 * @ret_next_index: next index to read 4333 * 4334 * Dump internal FW/HW data for debug purposes. 4335 * 4336 **/ 4337 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4338 u8 table_id, u32 start_index, u16 buff_size, 4339 void *buff, u16 *ret_buff_size, 4340 u8 *ret_next_table, u32 *ret_next_index, 4341 struct i40e_asq_cmd_details *cmd_details) 4342 { 4343 struct i40e_aq_desc desc; 4344 struct i40e_aqc_debug_dump_internals *cmd = 4345 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4346 struct i40e_aqc_debug_dump_internals *resp = 4347 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4348 i40e_status status; 4349 4350 if (buff_size == 0 || !buff) 4351 return I40E_ERR_PARAM; 4352 4353 i40e_fill_default_direct_cmd_desc(&desc, 4354 i40e_aqc_opc_debug_dump_internals); 4355 /* Indirect Command */ 4356 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4357 if (buff_size > I40E_AQ_LARGE_BUF) 4358 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4359 4360 cmd->cluster_id = cluster_id; 4361 cmd->table_id = table_id; 4362 cmd->idx = cpu_to_le32(start_index); 4363 4364 desc.datalen = cpu_to_le16(buff_size); 4365 4366 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4367 if (!status) { 4368 if (ret_buff_size) 4369 *ret_buff_size = le16_to_cpu(desc.datalen); 4370 if (ret_next_table) 4371 *ret_next_table = resp->table_id; 4372 if (ret_next_index) 4373 *ret_next_index = le32_to_cpu(resp->idx); 4374 } 4375 4376 return status; 4377 } 4378 4379 /** 4380 * i40e_read_bw_from_alt_ram 4381 * @hw: pointer to the hardware structure 4382 * @max_bw: pointer for max_bw read 4383 * @min_bw: pointer for min_bw read 4384 * @min_valid: pointer for bool that is true if min_bw is a valid value 4385 * @max_valid: pointer for bool that is true if max_bw is a valid value 4386 * 4387 * Read bw from the alternate ram for the given pf 4388 **/ 4389 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4390 u32 *max_bw, u32 *min_bw, 4391 bool *min_valid, bool *max_valid) 4392 { 4393 i40e_status status; 4394 u32 max_bw_addr, min_bw_addr; 4395 4396 /* Calculate the address of the min/max bw registers */ 4397 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4398 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4399 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4400 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4401 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4402 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4403 4404 /* Read the bandwidths from alt ram */ 4405 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4406 min_bw_addr, min_bw); 4407 4408 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4409 *min_valid = true; 4410 else 4411 *min_valid = false; 4412 4413 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4414 *max_valid = true; 4415 else 4416 *max_valid = false; 4417 4418 return status; 4419 } 4420 4421 /** 4422 * i40e_aq_configure_partition_bw 4423 * @hw: pointer to the hardware structure 4424 * @bw_data: Buffer holding valid pfs and bw limits 4425 * @cmd_details: pointer to command details 4426 * 4427 * Configure partitions guaranteed/max bw 4428 **/ 4429 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4430 struct i40e_aqc_configure_partition_bw_data *bw_data, 4431 struct i40e_asq_cmd_details *cmd_details) 4432 { 4433 i40e_status status; 4434 struct i40e_aq_desc desc; 4435 u16 bwd_size = sizeof(*bw_data); 4436 4437 i40e_fill_default_direct_cmd_desc(&desc, 4438 i40e_aqc_opc_configure_partition_bw); 4439 4440 /* Indirect command */ 4441 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4442 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4443 4444 if (bwd_size > I40E_AQ_LARGE_BUF) 4445 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4446 4447 desc.datalen = cpu_to_le16(bwd_size); 4448 4449 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4450 cmd_details); 4451 4452 return status; 4453 } 4454 4455 /** 4456 * i40e_read_phy_register_clause22 4457 * @hw: pointer to the HW structure 4458 * @reg: register address in the page 4459 * @phy_adr: PHY address on MDIO interface 4460 * @value: PHY register value 4461 * 4462 * Reads specified PHY register value 4463 **/ 4464 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4465 u16 reg, u8 phy_addr, u16 *value) 4466 { 4467 i40e_status status = I40E_ERR_TIMEOUT; 4468 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4469 u32 command = 0; 4470 u16 retry = 1000; 4471 4472 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4473 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4474 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4475 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4476 (I40E_GLGEN_MSCA_MDICMD_MASK); 4477 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4478 do { 4479 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4480 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4481 status = 0; 4482 break; 4483 } 4484 udelay(10); 4485 retry--; 4486 } while (retry); 4487 4488 if (status) { 4489 i40e_debug(hw, I40E_DEBUG_PHY, 4490 "PHY: Can't write command to external PHY.\n"); 4491 } else { 4492 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4493 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4494 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4495 } 4496 4497 return status; 4498 } 4499 4500 /** 4501 * i40e_write_phy_register_clause22 4502 * @hw: pointer to the HW structure 4503 * @reg: register address in the page 4504 * @phy_adr: PHY address on MDIO interface 4505 * @value: PHY register value 4506 * 4507 * Writes specified PHY register value 4508 **/ 4509 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4510 u16 reg, u8 phy_addr, u16 value) 4511 { 4512 i40e_status status = I40E_ERR_TIMEOUT; 4513 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4514 u32 command = 0; 4515 u16 retry = 1000; 4516 4517 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4518 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4519 4520 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4521 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4522 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4523 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4524 (I40E_GLGEN_MSCA_MDICMD_MASK); 4525 4526 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4527 do { 4528 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4529 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4530 status = 0; 4531 break; 4532 } 4533 udelay(10); 4534 retry--; 4535 } while (retry); 4536 4537 return status; 4538 } 4539 4540 /** 4541 * i40e_read_phy_register_clause45 4542 * @hw: pointer to the HW structure 4543 * @page: registers page number 4544 * @reg: register address in the page 4545 * @phy_adr: PHY address on MDIO interface 4546 * @value: PHY register value 4547 * 4548 * Reads specified PHY register value 4549 **/ 4550 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4551 u8 page, u16 reg, u8 phy_addr, u16 *value) 4552 { 4553 i40e_status status = I40E_ERR_TIMEOUT; 4554 u32 command = 0; 4555 u16 retry = 1000; 4556 u8 port_num = hw->func_caps.mdio_port_num; 4557 4558 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4559 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4560 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4561 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4562 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4563 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4564 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4565 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4566 do { 4567 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4568 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4569 status = 0; 4570 break; 4571 } 4572 usleep_range(10, 20); 4573 retry--; 4574 } while (retry); 4575 4576 if (status) { 4577 i40e_debug(hw, I40E_DEBUG_PHY, 4578 "PHY: Can't write command to external PHY.\n"); 4579 goto phy_read_end; 4580 } 4581 4582 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4583 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4584 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4585 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4586 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4587 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4588 status = I40E_ERR_TIMEOUT; 4589 retry = 1000; 4590 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4591 do { 4592 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4593 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4594 status = 0; 4595 break; 4596 } 4597 usleep_range(10, 20); 4598 retry--; 4599 } while (retry); 4600 4601 if (!status) { 4602 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4603 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4604 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4605 } else { 4606 i40e_debug(hw, I40E_DEBUG_PHY, 4607 "PHY: Can't read register value from external PHY.\n"); 4608 } 4609 4610 phy_read_end: 4611 return status; 4612 } 4613 4614 /** 4615 * i40e_write_phy_register_clause45 4616 * @hw: pointer to the HW structure 4617 * @page: registers page number 4618 * @reg: register address in the page 4619 * @phy_adr: PHY address on MDIO interface 4620 * @value: PHY register value 4621 * 4622 * Writes value to specified PHY register 4623 **/ 4624 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4625 u8 page, u16 reg, u8 phy_addr, u16 value) 4626 { 4627 i40e_status status = I40E_ERR_TIMEOUT; 4628 u32 command = 0; 4629 u16 retry = 1000; 4630 u8 port_num = hw->func_caps.mdio_port_num; 4631 4632 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4633 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4634 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4635 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4636 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4637 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4638 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4639 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4640 do { 4641 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4642 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4643 status = 0; 4644 break; 4645 } 4646 usleep_range(10, 20); 4647 retry--; 4648 } while (retry); 4649 if (status) { 4650 i40e_debug(hw, I40E_DEBUG_PHY, 4651 "PHY: Can't write command to external PHY.\n"); 4652 goto phy_write_end; 4653 } 4654 4655 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4656 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4657 4658 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4659 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4660 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4661 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4662 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4663 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4664 status = I40E_ERR_TIMEOUT; 4665 retry = 1000; 4666 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4667 do { 4668 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4669 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4670 status = 0; 4671 break; 4672 } 4673 usleep_range(10, 20); 4674 retry--; 4675 } while (retry); 4676 4677 phy_write_end: 4678 return status; 4679 } 4680 4681 /** 4682 * i40e_write_phy_register 4683 * @hw: pointer to the HW structure 4684 * @page: registers page number 4685 * @reg: register address in the page 4686 * @phy_adr: PHY address on MDIO interface 4687 * @value: PHY register value 4688 * 4689 * Writes value to specified PHY register 4690 **/ 4691 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4692 u8 page, u16 reg, u8 phy_addr, u16 value) 4693 { 4694 i40e_status status; 4695 4696 switch (hw->device_id) { 4697 case I40E_DEV_ID_1G_BASE_T_X722: 4698 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4699 value); 4700 break; 4701 case I40E_DEV_ID_10G_BASE_T: 4702 case I40E_DEV_ID_10G_BASE_T4: 4703 case I40E_DEV_ID_10G_BASE_T_X722: 4704 case I40E_DEV_ID_25G_B: 4705 case I40E_DEV_ID_25G_SFP28: 4706 status = i40e_write_phy_register_clause45(hw, page, reg, 4707 phy_addr, value); 4708 break; 4709 default: 4710 status = I40E_ERR_UNKNOWN_PHY; 4711 break; 4712 } 4713 4714 return status; 4715 } 4716 4717 /** 4718 * i40e_read_phy_register 4719 * @hw: pointer to the HW structure 4720 * @page: registers page number 4721 * @reg: register address in the page 4722 * @phy_adr: PHY address on MDIO interface 4723 * @value: PHY register value 4724 * 4725 * Reads specified PHY register value 4726 **/ 4727 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4728 u8 page, u16 reg, u8 phy_addr, u16 *value) 4729 { 4730 i40e_status status; 4731 4732 switch (hw->device_id) { 4733 case I40E_DEV_ID_1G_BASE_T_X722: 4734 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4735 value); 4736 break; 4737 case I40E_DEV_ID_10G_BASE_T: 4738 case I40E_DEV_ID_10G_BASE_T4: 4739 case I40E_DEV_ID_10G_BASE_T_X722: 4740 case I40E_DEV_ID_25G_B: 4741 case I40E_DEV_ID_25G_SFP28: 4742 status = i40e_read_phy_register_clause45(hw, page, reg, 4743 phy_addr, value); 4744 break; 4745 default: 4746 status = I40E_ERR_UNKNOWN_PHY; 4747 break; 4748 } 4749 4750 return status; 4751 } 4752 4753 /** 4754 * i40e_get_phy_address 4755 * @hw: pointer to the HW structure 4756 * @dev_num: PHY port num that address we want 4757 * @phy_addr: Returned PHY address 4758 * 4759 * Gets PHY address for current port 4760 **/ 4761 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4762 { 4763 u8 port_num = hw->func_caps.mdio_port_num; 4764 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4765 4766 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4767 } 4768 4769 /** 4770 * i40e_blink_phy_led 4771 * @hw: pointer to the HW structure 4772 * @time: time how long led will blinks in secs 4773 * @interval: gap between LED on and off in msecs 4774 * 4775 * Blinks PHY link LED 4776 **/ 4777 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4778 u32 time, u32 interval) 4779 { 4780 i40e_status status = 0; 4781 u32 i; 4782 u16 led_ctl; 4783 u16 gpio_led_port; 4784 u16 led_reg; 4785 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4786 u8 phy_addr = 0; 4787 u8 port_num; 4788 4789 i = rd32(hw, I40E_PFGEN_PORTNUM); 4790 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4791 phy_addr = i40e_get_phy_address(hw, port_num); 4792 4793 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4794 led_addr++) { 4795 status = i40e_read_phy_register_clause45(hw, 4796 I40E_PHY_COM_REG_PAGE, 4797 led_addr, phy_addr, 4798 &led_reg); 4799 if (status) 4800 goto phy_blinking_end; 4801 led_ctl = led_reg; 4802 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4803 led_reg = 0; 4804 status = i40e_write_phy_register_clause45(hw, 4805 I40E_PHY_COM_REG_PAGE, 4806 led_addr, phy_addr, 4807 led_reg); 4808 if (status) 4809 goto phy_blinking_end; 4810 break; 4811 } 4812 } 4813 4814 if (time > 0 && interval > 0) { 4815 for (i = 0; i < time * 1000; i += interval) { 4816 status = i40e_read_phy_register_clause45(hw, 4817 I40E_PHY_COM_REG_PAGE, 4818 led_addr, phy_addr, &led_reg); 4819 if (status) 4820 goto restore_config; 4821 if (led_reg & I40E_PHY_LED_MANUAL_ON) 4822 led_reg = 0; 4823 else 4824 led_reg = I40E_PHY_LED_MANUAL_ON; 4825 status = i40e_write_phy_register_clause45(hw, 4826 I40E_PHY_COM_REG_PAGE, 4827 led_addr, phy_addr, led_reg); 4828 if (status) 4829 goto restore_config; 4830 msleep(interval); 4831 } 4832 } 4833 4834 restore_config: 4835 status = i40e_write_phy_register_clause45(hw, 4836 I40E_PHY_COM_REG_PAGE, 4837 led_addr, phy_addr, led_ctl); 4838 4839 phy_blinking_end: 4840 return status; 4841 } 4842 4843 /** 4844 * i40e_led_get_reg - read LED register 4845 * @hw: pointer to the HW structure 4846 * @led_addr: LED register address 4847 * @reg_val: read register value 4848 **/ 4849 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 4850 u32 *reg_val) 4851 { 4852 enum i40e_status_code status; 4853 u8 phy_addr = 0; 4854 u8 port_num; 4855 u32 i; 4856 4857 *reg_val = 0; 4858 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4859 status = 4860 i40e_aq_get_phy_register(hw, 4861 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4862 I40E_PHY_COM_REG_PAGE, 4863 I40E_PHY_LED_PROV_REG_1, 4864 reg_val, NULL); 4865 } else { 4866 i = rd32(hw, I40E_PFGEN_PORTNUM); 4867 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4868 phy_addr = i40e_get_phy_address(hw, port_num); 4869 status = i40e_read_phy_register_clause45(hw, 4870 I40E_PHY_COM_REG_PAGE, 4871 led_addr, phy_addr, 4872 (u16 *)reg_val); 4873 } 4874 return status; 4875 } 4876 4877 /** 4878 * i40e_led_set_reg - write LED register 4879 * @hw: pointer to the HW structure 4880 * @led_addr: LED register address 4881 * @reg_val: register value to write 4882 **/ 4883 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 4884 u32 reg_val) 4885 { 4886 enum i40e_status_code status; 4887 u8 phy_addr = 0; 4888 u8 port_num; 4889 u32 i; 4890 4891 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4892 status = 4893 i40e_aq_set_phy_register(hw, 4894 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4895 I40E_PHY_COM_REG_PAGE, 4896 I40E_PHY_LED_PROV_REG_1, 4897 reg_val, NULL); 4898 } else { 4899 i = rd32(hw, I40E_PFGEN_PORTNUM); 4900 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4901 phy_addr = i40e_get_phy_address(hw, port_num); 4902 status = i40e_write_phy_register_clause45(hw, 4903 I40E_PHY_COM_REG_PAGE, 4904 led_addr, phy_addr, 4905 (u16)reg_val); 4906 } 4907 4908 return status; 4909 } 4910 4911 /** 4912 * i40e_led_get_phy - return current on/off mode 4913 * @hw: pointer to the hw struct 4914 * @led_addr: address of led register to use 4915 * @val: original value of register to use 4916 * 4917 **/ 4918 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 4919 u16 *val) 4920 { 4921 i40e_status status = 0; 4922 u16 gpio_led_port; 4923 u8 phy_addr = 0; 4924 u16 reg_val; 4925 u16 temp_addr; 4926 u8 port_num; 4927 u32 i; 4928 u32 reg_val_aq; 4929 4930 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 4931 status = 4932 i40e_aq_get_phy_register(hw, 4933 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 4934 I40E_PHY_COM_REG_PAGE, 4935 I40E_PHY_LED_PROV_REG_1, 4936 ®_val_aq, NULL); 4937 if (status == I40E_SUCCESS) 4938 *val = (u16)reg_val_aq; 4939 return status; 4940 } 4941 temp_addr = I40E_PHY_LED_PROV_REG_1; 4942 i = rd32(hw, I40E_PFGEN_PORTNUM); 4943 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4944 phy_addr = i40e_get_phy_address(hw, port_num); 4945 4946 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4947 temp_addr++) { 4948 status = i40e_read_phy_register_clause45(hw, 4949 I40E_PHY_COM_REG_PAGE, 4950 temp_addr, phy_addr, 4951 ®_val); 4952 if (status) 4953 return status; 4954 *val = reg_val; 4955 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 4956 *led_addr = temp_addr; 4957 break; 4958 } 4959 } 4960 return status; 4961 } 4962 4963 /** 4964 * i40e_led_set_phy 4965 * @hw: pointer to the HW structure 4966 * @on: true or false 4967 * @mode: original val plus bit for set or ignore 4968 * Set led's on or off when controlled by the PHY 4969 * 4970 **/ 4971 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 4972 u16 led_addr, u32 mode) 4973 { 4974 i40e_status status = 0; 4975 u32 led_ctl = 0; 4976 u32 led_reg = 0; 4977 4978 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4979 if (status) 4980 return status; 4981 led_ctl = led_reg; 4982 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4983 led_reg = 0; 4984 status = i40e_led_set_reg(hw, led_addr, led_reg); 4985 if (status) 4986 return status; 4987 } 4988 status = i40e_led_get_reg(hw, led_addr, &led_reg); 4989 if (status) 4990 goto restore_config; 4991 if (on) 4992 led_reg = I40E_PHY_LED_MANUAL_ON; 4993 else 4994 led_reg = 0; 4995 4996 status = i40e_led_set_reg(hw, led_addr, led_reg); 4997 if (status) 4998 goto restore_config; 4999 if (mode & I40E_PHY_LED_MODE_ORIG) { 5000 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5001 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5002 } 5003 return status; 5004 5005 restore_config: 5006 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5007 return status; 5008 } 5009 5010 /** 5011 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5012 * @hw: pointer to the hw struct 5013 * @reg_addr: register address 5014 * @reg_val: ptr to register value 5015 * @cmd_details: pointer to command details structure or NULL 5016 * 5017 * Use the firmware to read the Rx control register, 5018 * especially useful if the Rx unit is under heavy pressure 5019 **/ 5020 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5021 u32 reg_addr, u32 *reg_val, 5022 struct i40e_asq_cmd_details *cmd_details) 5023 { 5024 struct i40e_aq_desc desc; 5025 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5026 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5027 i40e_status status; 5028 5029 if (!reg_val) 5030 return I40E_ERR_PARAM; 5031 5032 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5033 5034 cmd_resp->address = cpu_to_le32(reg_addr); 5035 5036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5037 5038 if (status == 0) 5039 *reg_val = le32_to_cpu(cmd_resp->value); 5040 5041 return status; 5042 } 5043 5044 /** 5045 * i40e_read_rx_ctl - read from an Rx control register 5046 * @hw: pointer to the hw struct 5047 * @reg_addr: register address 5048 **/ 5049 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5050 { 5051 i40e_status status = 0; 5052 bool use_register; 5053 int retry = 5; 5054 u32 val = 0; 5055 5056 use_register = (((hw->aq.api_maj_ver == 1) && 5057 (hw->aq.api_min_ver < 5)) || 5058 (hw->mac.type == I40E_MAC_X722)); 5059 if (!use_register) { 5060 do_retry: 5061 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5062 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5063 usleep_range(1000, 2000); 5064 retry--; 5065 goto do_retry; 5066 } 5067 } 5068 5069 /* if the AQ access failed, try the old-fashioned way */ 5070 if (status || use_register) 5071 val = rd32(hw, reg_addr); 5072 5073 return val; 5074 } 5075 5076 /** 5077 * i40e_aq_rx_ctl_write_register 5078 * @hw: pointer to the hw struct 5079 * @reg_addr: register address 5080 * @reg_val: register value 5081 * @cmd_details: pointer to command details structure or NULL 5082 * 5083 * Use the firmware to write to an Rx control register, 5084 * especially useful if the Rx unit is under heavy pressure 5085 **/ 5086 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5087 u32 reg_addr, u32 reg_val, 5088 struct i40e_asq_cmd_details *cmd_details) 5089 { 5090 struct i40e_aq_desc desc; 5091 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5092 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5093 i40e_status status; 5094 5095 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5096 5097 cmd->address = cpu_to_le32(reg_addr); 5098 cmd->value = cpu_to_le32(reg_val); 5099 5100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5101 5102 return status; 5103 } 5104 5105 /** 5106 * i40e_write_rx_ctl - write to an Rx control register 5107 * @hw: pointer to the hw struct 5108 * @reg_addr: register address 5109 * @reg_val: register value 5110 **/ 5111 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5112 { 5113 i40e_status status = 0; 5114 bool use_register; 5115 int retry = 5; 5116 5117 use_register = (((hw->aq.api_maj_ver == 1) && 5118 (hw->aq.api_min_ver < 5)) || 5119 (hw->mac.type == I40E_MAC_X722)); 5120 if (!use_register) { 5121 do_retry: 5122 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5123 reg_val, NULL); 5124 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5125 usleep_range(1000, 2000); 5126 retry--; 5127 goto do_retry; 5128 } 5129 } 5130 5131 /* if the AQ access failed, try the old-fashioned way */ 5132 if (status || use_register) 5133 wr32(hw, reg_addr, reg_val); 5134 } 5135 5136 /** 5137 * i40e_aq_set_phy_register 5138 * @hw: pointer to the hw struct 5139 * @phy_select: select which phy should be accessed 5140 * @dev_addr: PHY device address 5141 * @reg_addr: PHY register address 5142 * @reg_val: new register value 5143 * @cmd_details: pointer to command details structure or NULL 5144 * 5145 * Write the external PHY register. 5146 **/ 5147 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5148 u8 phy_select, u8 dev_addr, 5149 u32 reg_addr, u32 reg_val, 5150 struct i40e_asq_cmd_details *cmd_details) 5151 { 5152 struct i40e_aq_desc desc; 5153 struct i40e_aqc_phy_register_access *cmd = 5154 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5155 i40e_status status; 5156 5157 i40e_fill_default_direct_cmd_desc(&desc, 5158 i40e_aqc_opc_set_phy_register); 5159 5160 cmd->phy_interface = phy_select; 5161 cmd->dev_address = dev_addr; 5162 cmd->reg_address = cpu_to_le32(reg_addr); 5163 cmd->reg_value = cpu_to_le32(reg_val); 5164 5165 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5166 5167 return status; 5168 } 5169 5170 /** 5171 * i40e_aq_get_phy_register 5172 * @hw: pointer to the hw struct 5173 * @phy_select: select which phy should be accessed 5174 * @dev_addr: PHY device address 5175 * @reg_addr: PHY register address 5176 * @reg_val: read register value 5177 * @cmd_details: pointer to command details structure or NULL 5178 * 5179 * Read the external PHY register. 5180 **/ 5181 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5182 u8 phy_select, u8 dev_addr, 5183 u32 reg_addr, u32 *reg_val, 5184 struct i40e_asq_cmd_details *cmd_details) 5185 { 5186 struct i40e_aq_desc desc; 5187 struct i40e_aqc_phy_register_access *cmd = 5188 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5189 i40e_status status; 5190 5191 i40e_fill_default_direct_cmd_desc(&desc, 5192 i40e_aqc_opc_get_phy_register); 5193 5194 cmd->phy_interface = phy_select; 5195 cmd->dev_address = dev_addr; 5196 cmd->reg_address = cpu_to_le32(reg_addr); 5197 5198 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5199 if (!status) 5200 *reg_val = le32_to_cpu(cmd->reg_value); 5201 5202 return status; 5203 } 5204 5205 /** 5206 * i40e_aq_write_ppp - Write pipeline personalization profile (ppp) 5207 * @hw: pointer to the hw struct 5208 * @buff: command buffer (size in bytes = buff_size) 5209 * @buff_size: buffer size in bytes 5210 * @track_id: package tracking id 5211 * @error_offset: returns error offset 5212 * @error_info: returns error information 5213 * @cmd_details: pointer to command details structure or NULL 5214 **/ 5215 enum 5216 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff, 5217 u16 buff_size, u32 track_id, 5218 u32 *error_offset, u32 *error_info, 5219 struct i40e_asq_cmd_details *cmd_details) 5220 { 5221 struct i40e_aq_desc desc; 5222 struct i40e_aqc_write_personalization_profile *cmd = 5223 (struct i40e_aqc_write_personalization_profile *) 5224 &desc.params.raw; 5225 struct i40e_aqc_write_ppp_resp *resp; 5226 i40e_status status; 5227 5228 i40e_fill_default_direct_cmd_desc(&desc, 5229 i40e_aqc_opc_write_personalization_profile); 5230 5231 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5232 if (buff_size > I40E_AQ_LARGE_BUF) 5233 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5234 5235 desc.datalen = cpu_to_le16(buff_size); 5236 5237 cmd->profile_track_id = cpu_to_le32(track_id); 5238 5239 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5240 if (!status) { 5241 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw; 5242 if (error_offset) 5243 *error_offset = le32_to_cpu(resp->error_offset); 5244 if (error_info) 5245 *error_info = le32_to_cpu(resp->error_info); 5246 } 5247 5248 return status; 5249 } 5250 5251 /** 5252 * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp) 5253 * @hw: pointer to the hw struct 5254 * @buff: command buffer (size in bytes = buff_size) 5255 * @buff_size: buffer size in bytes 5256 * @cmd_details: pointer to command details structure or NULL 5257 **/ 5258 enum 5259 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff, 5260 u16 buff_size, u8 flags, 5261 struct i40e_asq_cmd_details *cmd_details) 5262 { 5263 struct i40e_aq_desc desc; 5264 struct i40e_aqc_get_applied_profiles *cmd = 5265 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5266 i40e_status status; 5267 5268 i40e_fill_default_direct_cmd_desc(&desc, 5269 i40e_aqc_opc_get_personalization_profile_list); 5270 5271 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5272 if (buff_size > I40E_AQ_LARGE_BUF) 5273 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5274 desc.datalen = cpu_to_le16(buff_size); 5275 5276 cmd->flags = flags; 5277 5278 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5279 5280 return status; 5281 } 5282 5283 /** 5284 * i40e_find_segment_in_package 5285 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5286 * @pkg_hdr: pointer to the package header to be searched 5287 * 5288 * This function searches a package file for a particular segment type. On 5289 * success it returns a pointer to the segment header, otherwise it will 5290 * return NULL. 5291 **/ 5292 struct i40e_generic_seg_header * 5293 i40e_find_segment_in_package(u32 segment_type, 5294 struct i40e_package_header *pkg_hdr) 5295 { 5296 struct i40e_generic_seg_header *segment; 5297 u32 i; 5298 5299 /* Search all package segments for the requested segment type */ 5300 for (i = 0; i < pkg_hdr->segment_count; i++) { 5301 segment = 5302 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5303 pkg_hdr->segment_offset[i]); 5304 5305 if (segment->type == segment_type) 5306 return segment; 5307 } 5308 5309 return NULL; 5310 } 5311 5312 /** 5313 * i40e_write_profile 5314 * @hw: pointer to the hardware structure 5315 * @profile: pointer to the profile segment of the package to be downloaded 5316 * @track_id: package tracking id 5317 * 5318 * Handles the download of a complete package. 5319 */ 5320 enum i40e_status_code 5321 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5322 u32 track_id) 5323 { 5324 i40e_status status = 0; 5325 struct i40e_section_table *sec_tbl; 5326 struct i40e_profile_section_header *sec = NULL; 5327 u32 dev_cnt; 5328 u32 vendor_dev_id; 5329 u32 *nvm; 5330 u32 section_size = 0; 5331 u32 offset = 0, info = 0; 5332 u32 i; 5333 5334 if (!track_id) { 5335 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0."); 5336 return I40E_NOT_SUPPORTED; 5337 } 5338 5339 dev_cnt = profile->device_table_count; 5340 5341 for (i = 0; i < dev_cnt; i++) { 5342 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5343 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) 5344 if (hw->device_id == (vendor_dev_id & 0xFFFF)) 5345 break; 5346 } 5347 if (i == dev_cnt) { 5348 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP"); 5349 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5350 } 5351 5352 nvm = (u32 *)&profile->device_table[dev_cnt]; 5353 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; 5354 5355 for (i = 0; i < sec_tbl->section_count; i++) { 5356 sec = (struct i40e_profile_section_header *)((u8 *)profile + 5357 sec_tbl->section_offset[i]); 5358 5359 /* Skip 'AQ', 'note' and 'name' sections */ 5360 if (sec->section.type != SECTION_TYPE_MMIO) 5361 continue; 5362 5363 section_size = sec->section.size + 5364 sizeof(struct i40e_profile_section_header); 5365 5366 /* Write profile */ 5367 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size, 5368 track_id, &offset, &info, NULL); 5369 if (status) { 5370 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5371 "Failed to write profile: offset %d, info %d", 5372 offset, info); 5373 break; 5374 } 5375 } 5376 return status; 5377 } 5378 5379 /** 5380 * i40e_add_pinfo_to_list 5381 * @hw: pointer to the hardware structure 5382 * @profile: pointer to the profile segment of the package 5383 * @profile_info_sec: buffer for information section 5384 * @track_id: package tracking id 5385 * 5386 * Register a profile to the list of loaded profiles. 5387 */ 5388 enum i40e_status_code 5389 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5390 struct i40e_profile_segment *profile, 5391 u8 *profile_info_sec, u32 track_id) 5392 { 5393 i40e_status status = 0; 5394 struct i40e_profile_section_header *sec = NULL; 5395 struct i40e_profile_info *pinfo; 5396 u32 offset = 0, info = 0; 5397 5398 sec = (struct i40e_profile_section_header *)profile_info_sec; 5399 sec->tbl_size = 1; 5400 sec->data_end = sizeof(struct i40e_profile_section_header) + 5401 sizeof(struct i40e_profile_info); 5402 sec->section.type = SECTION_TYPE_INFO; 5403 sec->section.offset = sizeof(struct i40e_profile_section_header); 5404 sec->section.size = sizeof(struct i40e_profile_info); 5405 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5406 sec->section.offset); 5407 pinfo->track_id = track_id; 5408 pinfo->version = profile->version; 5409 pinfo->op = I40E_PPP_ADD_TRACKID; 5410 memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE); 5411 5412 status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end, 5413 track_id, &offset, &info, NULL); 5414 return status; 5415 } 5416