1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #include "i40e.h" 5 #include "i40e_type.h" 6 #include "i40e_adminq.h" 7 #include "i40e_prototype.h" 8 #include <linux/avf/virtchnl.h> 9 10 /** 11 * i40e_set_mac_type - Sets MAC type 12 * @hw: pointer to the HW structure 13 * 14 * This function sets the mac type of the adapter based on the 15 * vendor ID and device ID stored in the hw structure. 16 **/ 17 i40e_status i40e_set_mac_type(struct i40e_hw *hw) 18 { 19 i40e_status status = 0; 20 21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 22 switch (hw->device_id) { 23 case I40E_DEV_ID_SFP_XL710: 24 case I40E_DEV_ID_QEMU: 25 case I40E_DEV_ID_KX_B: 26 case I40E_DEV_ID_KX_C: 27 case I40E_DEV_ID_QSFP_A: 28 case I40E_DEV_ID_QSFP_B: 29 case I40E_DEV_ID_QSFP_C: 30 case I40E_DEV_ID_10G_BASE_T: 31 case I40E_DEV_ID_10G_BASE_T4: 32 case I40E_DEV_ID_10G_B: 33 case I40E_DEV_ID_10G_SFP: 34 case I40E_DEV_ID_20G_KR2: 35 case I40E_DEV_ID_20G_KR2_A: 36 case I40E_DEV_ID_25G_B: 37 case I40E_DEV_ID_25G_SFP28: 38 case I40E_DEV_ID_X710_N3000: 39 case I40E_DEV_ID_XXV710_N3000: 40 hw->mac.type = I40E_MAC_XL710; 41 break; 42 case I40E_DEV_ID_KX_X722: 43 case I40E_DEV_ID_QSFP_X722: 44 case I40E_DEV_ID_SFP_X722: 45 case I40E_DEV_ID_1G_BASE_T_X722: 46 case I40E_DEV_ID_10G_BASE_T_X722: 47 case I40E_DEV_ID_SFP_I_X722: 48 hw->mac.type = I40E_MAC_X722; 49 break; 50 default: 51 hw->mac.type = I40E_MAC_GENERIC; 52 break; 53 } 54 } else { 55 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 56 } 57 58 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 59 hw->mac.type, status); 60 return status; 61 } 62 63 /** 64 * i40e_aq_str - convert AQ err code to a string 65 * @hw: pointer to the HW structure 66 * @aq_err: the AQ error code to convert 67 **/ 68 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 69 { 70 switch (aq_err) { 71 case I40E_AQ_RC_OK: 72 return "OK"; 73 case I40E_AQ_RC_EPERM: 74 return "I40E_AQ_RC_EPERM"; 75 case I40E_AQ_RC_ENOENT: 76 return "I40E_AQ_RC_ENOENT"; 77 case I40E_AQ_RC_ESRCH: 78 return "I40E_AQ_RC_ESRCH"; 79 case I40E_AQ_RC_EINTR: 80 return "I40E_AQ_RC_EINTR"; 81 case I40E_AQ_RC_EIO: 82 return "I40E_AQ_RC_EIO"; 83 case I40E_AQ_RC_ENXIO: 84 return "I40E_AQ_RC_ENXIO"; 85 case I40E_AQ_RC_E2BIG: 86 return "I40E_AQ_RC_E2BIG"; 87 case I40E_AQ_RC_EAGAIN: 88 return "I40E_AQ_RC_EAGAIN"; 89 case I40E_AQ_RC_ENOMEM: 90 return "I40E_AQ_RC_ENOMEM"; 91 case I40E_AQ_RC_EACCES: 92 return "I40E_AQ_RC_EACCES"; 93 case I40E_AQ_RC_EFAULT: 94 return "I40E_AQ_RC_EFAULT"; 95 case I40E_AQ_RC_EBUSY: 96 return "I40E_AQ_RC_EBUSY"; 97 case I40E_AQ_RC_EEXIST: 98 return "I40E_AQ_RC_EEXIST"; 99 case I40E_AQ_RC_EINVAL: 100 return "I40E_AQ_RC_EINVAL"; 101 case I40E_AQ_RC_ENOTTY: 102 return "I40E_AQ_RC_ENOTTY"; 103 case I40E_AQ_RC_ENOSPC: 104 return "I40E_AQ_RC_ENOSPC"; 105 case I40E_AQ_RC_ENOSYS: 106 return "I40E_AQ_RC_ENOSYS"; 107 case I40E_AQ_RC_ERANGE: 108 return "I40E_AQ_RC_ERANGE"; 109 case I40E_AQ_RC_EFLUSHED: 110 return "I40E_AQ_RC_EFLUSHED"; 111 case I40E_AQ_RC_BAD_ADDR: 112 return "I40E_AQ_RC_BAD_ADDR"; 113 case I40E_AQ_RC_EMODE: 114 return "I40E_AQ_RC_EMODE"; 115 case I40E_AQ_RC_EFBIG: 116 return "I40E_AQ_RC_EFBIG"; 117 } 118 119 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 120 return hw->err_str; 121 } 122 123 /** 124 * i40e_stat_str - convert status err code to a string 125 * @hw: pointer to the HW structure 126 * @stat_err: the status error code to convert 127 **/ 128 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err) 129 { 130 switch (stat_err) { 131 case 0: 132 return "OK"; 133 case I40E_ERR_NVM: 134 return "I40E_ERR_NVM"; 135 case I40E_ERR_NVM_CHECKSUM: 136 return "I40E_ERR_NVM_CHECKSUM"; 137 case I40E_ERR_PHY: 138 return "I40E_ERR_PHY"; 139 case I40E_ERR_CONFIG: 140 return "I40E_ERR_CONFIG"; 141 case I40E_ERR_PARAM: 142 return "I40E_ERR_PARAM"; 143 case I40E_ERR_MAC_TYPE: 144 return "I40E_ERR_MAC_TYPE"; 145 case I40E_ERR_UNKNOWN_PHY: 146 return "I40E_ERR_UNKNOWN_PHY"; 147 case I40E_ERR_LINK_SETUP: 148 return "I40E_ERR_LINK_SETUP"; 149 case I40E_ERR_ADAPTER_STOPPED: 150 return "I40E_ERR_ADAPTER_STOPPED"; 151 case I40E_ERR_INVALID_MAC_ADDR: 152 return "I40E_ERR_INVALID_MAC_ADDR"; 153 case I40E_ERR_DEVICE_NOT_SUPPORTED: 154 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 155 case I40E_ERR_MASTER_REQUESTS_PENDING: 156 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 157 case I40E_ERR_INVALID_LINK_SETTINGS: 158 return "I40E_ERR_INVALID_LINK_SETTINGS"; 159 case I40E_ERR_AUTONEG_NOT_COMPLETE: 160 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 161 case I40E_ERR_RESET_FAILED: 162 return "I40E_ERR_RESET_FAILED"; 163 case I40E_ERR_SWFW_SYNC: 164 return "I40E_ERR_SWFW_SYNC"; 165 case I40E_ERR_NO_AVAILABLE_VSI: 166 return "I40E_ERR_NO_AVAILABLE_VSI"; 167 case I40E_ERR_NO_MEMORY: 168 return "I40E_ERR_NO_MEMORY"; 169 case I40E_ERR_BAD_PTR: 170 return "I40E_ERR_BAD_PTR"; 171 case I40E_ERR_RING_FULL: 172 return "I40E_ERR_RING_FULL"; 173 case I40E_ERR_INVALID_PD_ID: 174 return "I40E_ERR_INVALID_PD_ID"; 175 case I40E_ERR_INVALID_QP_ID: 176 return "I40E_ERR_INVALID_QP_ID"; 177 case I40E_ERR_INVALID_CQ_ID: 178 return "I40E_ERR_INVALID_CQ_ID"; 179 case I40E_ERR_INVALID_CEQ_ID: 180 return "I40E_ERR_INVALID_CEQ_ID"; 181 case I40E_ERR_INVALID_AEQ_ID: 182 return "I40E_ERR_INVALID_AEQ_ID"; 183 case I40E_ERR_INVALID_SIZE: 184 return "I40E_ERR_INVALID_SIZE"; 185 case I40E_ERR_INVALID_ARP_INDEX: 186 return "I40E_ERR_INVALID_ARP_INDEX"; 187 case I40E_ERR_INVALID_FPM_FUNC_ID: 188 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 189 case I40E_ERR_QP_INVALID_MSG_SIZE: 190 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 191 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 192 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 193 case I40E_ERR_INVALID_FRAG_COUNT: 194 return "I40E_ERR_INVALID_FRAG_COUNT"; 195 case I40E_ERR_QUEUE_EMPTY: 196 return "I40E_ERR_QUEUE_EMPTY"; 197 case I40E_ERR_INVALID_ALIGNMENT: 198 return "I40E_ERR_INVALID_ALIGNMENT"; 199 case I40E_ERR_FLUSHED_QUEUE: 200 return "I40E_ERR_FLUSHED_QUEUE"; 201 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 202 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 203 case I40E_ERR_INVALID_IMM_DATA_SIZE: 204 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 205 case I40E_ERR_TIMEOUT: 206 return "I40E_ERR_TIMEOUT"; 207 case I40E_ERR_OPCODE_MISMATCH: 208 return "I40E_ERR_OPCODE_MISMATCH"; 209 case I40E_ERR_CQP_COMPL_ERROR: 210 return "I40E_ERR_CQP_COMPL_ERROR"; 211 case I40E_ERR_INVALID_VF_ID: 212 return "I40E_ERR_INVALID_VF_ID"; 213 case I40E_ERR_INVALID_HMCFN_ID: 214 return "I40E_ERR_INVALID_HMCFN_ID"; 215 case I40E_ERR_BACKING_PAGE_ERROR: 216 return "I40E_ERR_BACKING_PAGE_ERROR"; 217 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 218 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 219 case I40E_ERR_INVALID_PBLE_INDEX: 220 return "I40E_ERR_INVALID_PBLE_INDEX"; 221 case I40E_ERR_INVALID_SD_INDEX: 222 return "I40E_ERR_INVALID_SD_INDEX"; 223 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 224 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 225 case I40E_ERR_INVALID_SD_TYPE: 226 return "I40E_ERR_INVALID_SD_TYPE"; 227 case I40E_ERR_MEMCPY_FAILED: 228 return "I40E_ERR_MEMCPY_FAILED"; 229 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 230 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 231 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 232 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 233 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 234 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 235 case I40E_ERR_SRQ_ENABLED: 236 return "I40E_ERR_SRQ_ENABLED"; 237 case I40E_ERR_ADMIN_QUEUE_ERROR: 238 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 239 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 240 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 241 case I40E_ERR_BUF_TOO_SHORT: 242 return "I40E_ERR_BUF_TOO_SHORT"; 243 case I40E_ERR_ADMIN_QUEUE_FULL: 244 return "I40E_ERR_ADMIN_QUEUE_FULL"; 245 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 246 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 247 case I40E_ERR_BAD_IWARP_CQE: 248 return "I40E_ERR_BAD_IWARP_CQE"; 249 case I40E_ERR_NVM_BLANK_MODE: 250 return "I40E_ERR_NVM_BLANK_MODE"; 251 case I40E_ERR_NOT_IMPLEMENTED: 252 return "I40E_ERR_NOT_IMPLEMENTED"; 253 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 254 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 255 case I40E_ERR_DIAG_TEST_FAILED: 256 return "I40E_ERR_DIAG_TEST_FAILED"; 257 case I40E_ERR_NOT_READY: 258 return "I40E_ERR_NOT_READY"; 259 case I40E_NOT_SUPPORTED: 260 return "I40E_NOT_SUPPORTED"; 261 case I40E_ERR_FIRMWARE_API_VERSION: 262 return "I40E_ERR_FIRMWARE_API_VERSION"; 263 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 264 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 265 } 266 267 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 268 return hw->err_str; 269 } 270 271 /** 272 * i40e_debug_aq 273 * @hw: debug mask related to admin queue 274 * @mask: debug mask 275 * @desc: pointer to admin queue descriptor 276 * @buffer: pointer to command buffer 277 * @buf_len: max length of buffer 278 * 279 * Dumps debug log about adminq command with descriptor contents. 280 **/ 281 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 282 void *buffer, u16 buf_len) 283 { 284 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 285 u32 effective_mask = hw->debug_mask & mask; 286 char prefix[27]; 287 u16 len; 288 u8 *buf = (u8 *)buffer; 289 290 if (!effective_mask || !desc) 291 return; 292 293 len = le16_to_cpu(aq_desc->datalen); 294 295 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 296 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 297 le16_to_cpu(aq_desc->opcode), 298 le16_to_cpu(aq_desc->flags), 299 le16_to_cpu(aq_desc->datalen), 300 le16_to_cpu(aq_desc->retval)); 301 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 302 "\tcookie (h,l) 0x%08X 0x%08X\n", 303 le32_to_cpu(aq_desc->cookie_high), 304 le32_to_cpu(aq_desc->cookie_low)); 305 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 306 "\tparam (0,1) 0x%08X 0x%08X\n", 307 le32_to_cpu(aq_desc->params.internal.param0), 308 le32_to_cpu(aq_desc->params.internal.param1)); 309 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, 310 "\taddr (h,l) 0x%08X 0x%08X\n", 311 le32_to_cpu(aq_desc->params.external.addr_high), 312 le32_to_cpu(aq_desc->params.external.addr_low)); 313 314 if (buffer && buf_len != 0 && len != 0 && 315 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) { 316 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 317 if (buf_len < len) 318 len = buf_len; 319 320 snprintf(prefix, sizeof(prefix), 321 "i40e %02x:%02x.%x: \t0x", 322 hw->bus.bus_id, 323 hw->bus.device, 324 hw->bus.func); 325 326 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 327 16, 1, buf, len, false); 328 } 329 } 330 331 /** 332 * i40e_check_asq_alive 333 * @hw: pointer to the hw struct 334 * 335 * Returns true if Queue is enabled else false. 336 **/ 337 bool i40e_check_asq_alive(struct i40e_hw *hw) 338 { 339 if (hw->aq.asq.len) 340 return !!(rd32(hw, hw->aq.asq.len) & 341 I40E_PF_ATQLEN_ATQENABLE_MASK); 342 else 343 return false; 344 } 345 346 /** 347 * i40e_aq_queue_shutdown 348 * @hw: pointer to the hw struct 349 * @unloading: is the driver unloading itself 350 * 351 * Tell the Firmware that we're shutting down the AdminQ and whether 352 * or not the driver is unloading as well. 353 **/ 354 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 355 bool unloading) 356 { 357 struct i40e_aq_desc desc; 358 struct i40e_aqc_queue_shutdown *cmd = 359 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 360 i40e_status status; 361 362 i40e_fill_default_direct_cmd_desc(&desc, 363 i40e_aqc_opc_queue_shutdown); 364 365 if (unloading) 366 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 367 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 368 369 return status; 370 } 371 372 /** 373 * i40e_aq_get_set_rss_lut 374 * @hw: pointer to the hardware structure 375 * @vsi_id: vsi fw index 376 * @pf_lut: for PF table set true, for VSI table set false 377 * @lut: pointer to the lut buffer provided by the caller 378 * @lut_size: size of the lut buffer 379 * @set: set true to set the table, false to get the table 380 * 381 * Internal function to get or set RSS look up table 382 **/ 383 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 384 u16 vsi_id, bool pf_lut, 385 u8 *lut, u16 lut_size, 386 bool set) 387 { 388 i40e_status status; 389 struct i40e_aq_desc desc; 390 struct i40e_aqc_get_set_rss_lut *cmd_resp = 391 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 392 393 if (set) 394 i40e_fill_default_direct_cmd_desc(&desc, 395 i40e_aqc_opc_set_rss_lut); 396 else 397 i40e_fill_default_direct_cmd_desc(&desc, 398 i40e_aqc_opc_get_rss_lut); 399 400 /* Indirect command */ 401 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 402 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 403 404 cmd_resp->vsi_id = 405 cpu_to_le16((u16)((vsi_id << 406 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 407 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 408 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 409 410 if (pf_lut) 411 cmd_resp->flags |= cpu_to_le16((u16) 412 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 413 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 414 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 415 else 416 cmd_resp->flags |= cpu_to_le16((u16) 417 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 420 421 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 422 423 return status; 424 } 425 426 /** 427 * i40e_aq_get_rss_lut 428 * @hw: pointer to the hardware structure 429 * @vsi_id: vsi fw index 430 * @pf_lut: for PF table set true, for VSI table set false 431 * @lut: pointer to the lut buffer provided by the caller 432 * @lut_size: size of the lut buffer 433 * 434 * get the RSS lookup table, PF or VSI type 435 **/ 436 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 437 bool pf_lut, u8 *lut, u16 lut_size) 438 { 439 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 440 false); 441 } 442 443 /** 444 * i40e_aq_set_rss_lut 445 * @hw: pointer to the hardware structure 446 * @vsi_id: vsi fw index 447 * @pf_lut: for PF table set true, for VSI table set false 448 * @lut: pointer to the lut buffer provided by the caller 449 * @lut_size: size of the lut buffer 450 * 451 * set the RSS lookup table, PF or VSI type 452 **/ 453 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 454 bool pf_lut, u8 *lut, u16 lut_size) 455 { 456 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true); 457 } 458 459 /** 460 * i40e_aq_get_set_rss_key 461 * @hw: pointer to the hw struct 462 * @vsi_id: vsi fw index 463 * @key: pointer to key info struct 464 * @set: set true to set the key, false to get the key 465 * 466 * get the RSS key per VSI 467 **/ 468 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw, 469 u16 vsi_id, 470 struct i40e_aqc_get_set_rss_key_data *key, 471 bool set) 472 { 473 i40e_status status; 474 struct i40e_aq_desc desc; 475 struct i40e_aqc_get_set_rss_key *cmd_resp = 476 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 477 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 478 479 if (set) 480 i40e_fill_default_direct_cmd_desc(&desc, 481 i40e_aqc_opc_set_rss_key); 482 else 483 i40e_fill_default_direct_cmd_desc(&desc, 484 i40e_aqc_opc_get_rss_key); 485 486 /* Indirect command */ 487 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 488 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 489 490 cmd_resp->vsi_id = 491 cpu_to_le16((u16)((vsi_id << 492 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 493 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 494 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 495 496 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 497 498 return status; 499 } 500 501 /** 502 * i40e_aq_get_rss_key 503 * @hw: pointer to the hw struct 504 * @vsi_id: vsi fw index 505 * @key: pointer to key info struct 506 * 507 **/ 508 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw, 509 u16 vsi_id, 510 struct i40e_aqc_get_set_rss_key_data *key) 511 { 512 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false); 513 } 514 515 /** 516 * i40e_aq_set_rss_key 517 * @hw: pointer to the hw struct 518 * @vsi_id: vsi fw index 519 * @key: pointer to key info struct 520 * 521 * set the RSS key per VSI 522 **/ 523 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw, 524 u16 vsi_id, 525 struct i40e_aqc_get_set_rss_key_data *key) 526 { 527 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); 528 } 529 530 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 531 * hardware to a bit-field that can be used by SW to more easily determine the 532 * packet type. 533 * 534 * Macros are used to shorten the table lines and make this table human 535 * readable. 536 * 537 * We store the PTYPE in the top byte of the bit field - this is just so that 538 * we can check that the table doesn't have a row missing, as the index into 539 * the table should be the PTYPE. 540 * 541 * Typical work flow: 542 * 543 * IF NOT i40e_ptype_lookup[ptype].known 544 * THEN 545 * Packet is unknown 546 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 547 * Use the rest of the fields to look at the tunnels, inner protocols, etc 548 * ELSE 549 * Use the enum i40e_rx_l2_ptype to decode the packet type 550 * ENDIF 551 */ 552 553 /* macro to make the table lines short */ 554 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 555 { PTYPE, \ 556 1, \ 557 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 558 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 559 I40E_RX_PTYPE_##OUTER_FRAG, \ 560 I40E_RX_PTYPE_TUNNEL_##T, \ 561 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 562 I40E_RX_PTYPE_##TEF, \ 563 I40E_RX_PTYPE_INNER_PROT_##I, \ 564 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 565 566 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 567 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 568 569 /* shorter macros makes the table fit but are terse */ 570 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 571 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 572 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 573 574 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 575 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 576 /* L2 Packet types */ 577 I40E_PTT_UNUSED_ENTRY(0), 578 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 579 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 580 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 581 I40E_PTT_UNUSED_ENTRY(4), 582 I40E_PTT_UNUSED_ENTRY(5), 583 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 584 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 585 I40E_PTT_UNUSED_ENTRY(8), 586 I40E_PTT_UNUSED_ENTRY(9), 587 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 588 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 589 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 590 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 591 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 592 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 593 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 594 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 595 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 596 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 597 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 598 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 599 600 /* Non Tunneled IPv4 */ 601 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 602 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 603 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 604 I40E_PTT_UNUSED_ENTRY(25), 605 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 606 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 607 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 608 609 /* IPv4 --> IPv4 */ 610 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 611 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 612 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 613 I40E_PTT_UNUSED_ENTRY(32), 614 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 615 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 616 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 617 618 /* IPv4 --> IPv6 */ 619 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 620 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 621 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 622 I40E_PTT_UNUSED_ENTRY(39), 623 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 624 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 625 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 626 627 /* IPv4 --> GRE/NAT */ 628 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 629 630 /* IPv4 --> GRE/NAT --> IPv4 */ 631 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 632 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 633 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 634 I40E_PTT_UNUSED_ENTRY(47), 635 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 636 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 637 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 638 639 /* IPv4 --> GRE/NAT --> IPv6 */ 640 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 641 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 642 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 643 I40E_PTT_UNUSED_ENTRY(54), 644 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 645 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 646 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 647 648 /* IPv4 --> GRE/NAT --> MAC */ 649 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 650 651 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 652 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 653 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 654 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 655 I40E_PTT_UNUSED_ENTRY(62), 656 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 657 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 658 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 659 660 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 661 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 662 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 663 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 664 I40E_PTT_UNUSED_ENTRY(69), 665 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 666 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 667 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 668 669 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 670 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 671 672 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 673 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 674 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 675 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 676 I40E_PTT_UNUSED_ENTRY(77), 677 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 678 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 679 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 680 681 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 682 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 683 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 684 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 685 I40E_PTT_UNUSED_ENTRY(84), 686 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 687 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 688 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 689 690 /* Non Tunneled IPv6 */ 691 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 692 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 693 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 694 I40E_PTT_UNUSED_ENTRY(91), 695 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 696 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 697 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 698 699 /* IPv6 --> IPv4 */ 700 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 701 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 702 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 703 I40E_PTT_UNUSED_ENTRY(98), 704 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 705 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 706 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 707 708 /* IPv6 --> IPv6 */ 709 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 710 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 711 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 712 I40E_PTT_UNUSED_ENTRY(105), 713 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 714 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 715 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 716 717 /* IPv6 --> GRE/NAT */ 718 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 719 720 /* IPv6 --> GRE/NAT -> IPv4 */ 721 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 722 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 723 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 724 I40E_PTT_UNUSED_ENTRY(113), 725 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 726 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 727 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 728 729 /* IPv6 --> GRE/NAT -> IPv6 */ 730 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 731 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 732 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 733 I40E_PTT_UNUSED_ENTRY(120), 734 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 735 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 736 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 737 738 /* IPv6 --> GRE/NAT -> MAC */ 739 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 740 741 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 742 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 743 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 744 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 745 I40E_PTT_UNUSED_ENTRY(128), 746 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 747 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 748 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 749 750 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 751 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 752 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 753 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 754 I40E_PTT_UNUSED_ENTRY(135), 755 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 756 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 757 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 758 759 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 760 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 761 762 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 763 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 764 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 765 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 766 I40E_PTT_UNUSED_ENTRY(143), 767 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 768 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 769 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 770 771 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 772 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 773 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 774 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 775 I40E_PTT_UNUSED_ENTRY(150), 776 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 777 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 778 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 779 780 /* unused entries */ 781 I40E_PTT_UNUSED_ENTRY(154), 782 I40E_PTT_UNUSED_ENTRY(155), 783 I40E_PTT_UNUSED_ENTRY(156), 784 I40E_PTT_UNUSED_ENTRY(157), 785 I40E_PTT_UNUSED_ENTRY(158), 786 I40E_PTT_UNUSED_ENTRY(159), 787 788 I40E_PTT_UNUSED_ENTRY(160), 789 I40E_PTT_UNUSED_ENTRY(161), 790 I40E_PTT_UNUSED_ENTRY(162), 791 I40E_PTT_UNUSED_ENTRY(163), 792 I40E_PTT_UNUSED_ENTRY(164), 793 I40E_PTT_UNUSED_ENTRY(165), 794 I40E_PTT_UNUSED_ENTRY(166), 795 I40E_PTT_UNUSED_ENTRY(167), 796 I40E_PTT_UNUSED_ENTRY(168), 797 I40E_PTT_UNUSED_ENTRY(169), 798 799 I40E_PTT_UNUSED_ENTRY(170), 800 I40E_PTT_UNUSED_ENTRY(171), 801 I40E_PTT_UNUSED_ENTRY(172), 802 I40E_PTT_UNUSED_ENTRY(173), 803 I40E_PTT_UNUSED_ENTRY(174), 804 I40E_PTT_UNUSED_ENTRY(175), 805 I40E_PTT_UNUSED_ENTRY(176), 806 I40E_PTT_UNUSED_ENTRY(177), 807 I40E_PTT_UNUSED_ENTRY(178), 808 I40E_PTT_UNUSED_ENTRY(179), 809 810 I40E_PTT_UNUSED_ENTRY(180), 811 I40E_PTT_UNUSED_ENTRY(181), 812 I40E_PTT_UNUSED_ENTRY(182), 813 I40E_PTT_UNUSED_ENTRY(183), 814 I40E_PTT_UNUSED_ENTRY(184), 815 I40E_PTT_UNUSED_ENTRY(185), 816 I40E_PTT_UNUSED_ENTRY(186), 817 I40E_PTT_UNUSED_ENTRY(187), 818 I40E_PTT_UNUSED_ENTRY(188), 819 I40E_PTT_UNUSED_ENTRY(189), 820 821 I40E_PTT_UNUSED_ENTRY(190), 822 I40E_PTT_UNUSED_ENTRY(191), 823 I40E_PTT_UNUSED_ENTRY(192), 824 I40E_PTT_UNUSED_ENTRY(193), 825 I40E_PTT_UNUSED_ENTRY(194), 826 I40E_PTT_UNUSED_ENTRY(195), 827 I40E_PTT_UNUSED_ENTRY(196), 828 I40E_PTT_UNUSED_ENTRY(197), 829 I40E_PTT_UNUSED_ENTRY(198), 830 I40E_PTT_UNUSED_ENTRY(199), 831 832 I40E_PTT_UNUSED_ENTRY(200), 833 I40E_PTT_UNUSED_ENTRY(201), 834 I40E_PTT_UNUSED_ENTRY(202), 835 I40E_PTT_UNUSED_ENTRY(203), 836 I40E_PTT_UNUSED_ENTRY(204), 837 I40E_PTT_UNUSED_ENTRY(205), 838 I40E_PTT_UNUSED_ENTRY(206), 839 I40E_PTT_UNUSED_ENTRY(207), 840 I40E_PTT_UNUSED_ENTRY(208), 841 I40E_PTT_UNUSED_ENTRY(209), 842 843 I40E_PTT_UNUSED_ENTRY(210), 844 I40E_PTT_UNUSED_ENTRY(211), 845 I40E_PTT_UNUSED_ENTRY(212), 846 I40E_PTT_UNUSED_ENTRY(213), 847 I40E_PTT_UNUSED_ENTRY(214), 848 I40E_PTT_UNUSED_ENTRY(215), 849 I40E_PTT_UNUSED_ENTRY(216), 850 I40E_PTT_UNUSED_ENTRY(217), 851 I40E_PTT_UNUSED_ENTRY(218), 852 I40E_PTT_UNUSED_ENTRY(219), 853 854 I40E_PTT_UNUSED_ENTRY(220), 855 I40E_PTT_UNUSED_ENTRY(221), 856 I40E_PTT_UNUSED_ENTRY(222), 857 I40E_PTT_UNUSED_ENTRY(223), 858 I40E_PTT_UNUSED_ENTRY(224), 859 I40E_PTT_UNUSED_ENTRY(225), 860 I40E_PTT_UNUSED_ENTRY(226), 861 I40E_PTT_UNUSED_ENTRY(227), 862 I40E_PTT_UNUSED_ENTRY(228), 863 I40E_PTT_UNUSED_ENTRY(229), 864 865 I40E_PTT_UNUSED_ENTRY(230), 866 I40E_PTT_UNUSED_ENTRY(231), 867 I40E_PTT_UNUSED_ENTRY(232), 868 I40E_PTT_UNUSED_ENTRY(233), 869 I40E_PTT_UNUSED_ENTRY(234), 870 I40E_PTT_UNUSED_ENTRY(235), 871 I40E_PTT_UNUSED_ENTRY(236), 872 I40E_PTT_UNUSED_ENTRY(237), 873 I40E_PTT_UNUSED_ENTRY(238), 874 I40E_PTT_UNUSED_ENTRY(239), 875 876 I40E_PTT_UNUSED_ENTRY(240), 877 I40E_PTT_UNUSED_ENTRY(241), 878 I40E_PTT_UNUSED_ENTRY(242), 879 I40E_PTT_UNUSED_ENTRY(243), 880 I40E_PTT_UNUSED_ENTRY(244), 881 I40E_PTT_UNUSED_ENTRY(245), 882 I40E_PTT_UNUSED_ENTRY(246), 883 I40E_PTT_UNUSED_ENTRY(247), 884 I40E_PTT_UNUSED_ENTRY(248), 885 I40E_PTT_UNUSED_ENTRY(249), 886 887 I40E_PTT_UNUSED_ENTRY(250), 888 I40E_PTT_UNUSED_ENTRY(251), 889 I40E_PTT_UNUSED_ENTRY(252), 890 I40E_PTT_UNUSED_ENTRY(253), 891 I40E_PTT_UNUSED_ENTRY(254), 892 I40E_PTT_UNUSED_ENTRY(255) 893 }; 894 895 /** 896 * i40e_init_shared_code - Initialize the shared code 897 * @hw: pointer to hardware structure 898 * 899 * This assigns the MAC type and PHY code and inits the NVM. 900 * Does not touch the hardware. This function must be called prior to any 901 * other function in the shared code. The i40e_hw structure should be 902 * memset to 0 prior to calling this function. The following fields in 903 * hw structure should be filled in prior to calling this function: 904 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 905 * subsystem_vendor_id, and revision_id 906 **/ 907 i40e_status i40e_init_shared_code(struct i40e_hw *hw) 908 { 909 i40e_status status = 0; 910 u32 port, ari, func_rid; 911 912 i40e_set_mac_type(hw); 913 914 switch (hw->mac.type) { 915 case I40E_MAC_XL710: 916 case I40E_MAC_X722: 917 break; 918 default: 919 return I40E_ERR_DEVICE_NOT_SUPPORTED; 920 } 921 922 hw->phy.get_link_info = true; 923 924 /* Determine port number and PF number*/ 925 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 926 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 927 hw->port = (u8)port; 928 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 929 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 930 func_rid = rd32(hw, I40E_PF_FUNC_RID); 931 if (ari) 932 hw->pf_id = (u8)(func_rid & 0xff); 933 else 934 hw->pf_id = (u8)(func_rid & 0x7); 935 936 if (hw->mac.type == I40E_MAC_X722) 937 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 938 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 939 940 status = i40e_init_nvm(hw); 941 return status; 942 } 943 944 /** 945 * i40e_aq_mac_address_read - Retrieve the MAC addresses 946 * @hw: pointer to the hw struct 947 * @flags: a return indicator of what addresses were added to the addr store 948 * @addrs: the requestor's mac addr store 949 * @cmd_details: pointer to command details structure or NULL 950 **/ 951 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 952 u16 *flags, 953 struct i40e_aqc_mac_address_read_data *addrs, 954 struct i40e_asq_cmd_details *cmd_details) 955 { 956 struct i40e_aq_desc desc; 957 struct i40e_aqc_mac_address_read *cmd_data = 958 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 959 i40e_status status; 960 961 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 962 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 963 964 status = i40e_asq_send_command(hw, &desc, addrs, 965 sizeof(*addrs), cmd_details); 966 *flags = le16_to_cpu(cmd_data->command_flags); 967 968 return status; 969 } 970 971 /** 972 * i40e_aq_mac_address_write - Change the MAC addresses 973 * @hw: pointer to the hw struct 974 * @flags: indicates which MAC to be written 975 * @mac_addr: address to write 976 * @cmd_details: pointer to command details structure or NULL 977 **/ 978 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 979 u16 flags, u8 *mac_addr, 980 struct i40e_asq_cmd_details *cmd_details) 981 { 982 struct i40e_aq_desc desc; 983 struct i40e_aqc_mac_address_write *cmd_data = 984 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 985 i40e_status status; 986 987 i40e_fill_default_direct_cmd_desc(&desc, 988 i40e_aqc_opc_mac_address_write); 989 cmd_data->command_flags = cpu_to_le16(flags); 990 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 991 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 992 ((u32)mac_addr[3] << 16) | 993 ((u32)mac_addr[4] << 8) | 994 mac_addr[5]); 995 996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 997 998 return status; 999 } 1000 1001 /** 1002 * i40e_get_mac_addr - get MAC address 1003 * @hw: pointer to the HW structure 1004 * @mac_addr: pointer to MAC address 1005 * 1006 * Reads the adapter's MAC address from register 1007 **/ 1008 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1009 { 1010 struct i40e_aqc_mac_address_read_data addrs; 1011 i40e_status status; 1012 u16 flags = 0; 1013 1014 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1015 1016 if (flags & I40E_AQC_LAN_ADDR_VALID) 1017 ether_addr_copy(mac_addr, addrs.pf_lan_mac); 1018 1019 return status; 1020 } 1021 1022 /** 1023 * i40e_get_port_mac_addr - get Port MAC address 1024 * @hw: pointer to the HW structure 1025 * @mac_addr: pointer to Port MAC address 1026 * 1027 * Reads the adapter's Port MAC address 1028 **/ 1029 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1030 { 1031 struct i40e_aqc_mac_address_read_data addrs; 1032 i40e_status status; 1033 u16 flags = 0; 1034 1035 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1036 if (status) 1037 return status; 1038 1039 if (flags & I40E_AQC_PORT_ADDR_VALID) 1040 ether_addr_copy(mac_addr, addrs.port_mac); 1041 else 1042 status = I40E_ERR_INVALID_MAC_ADDR; 1043 1044 return status; 1045 } 1046 1047 /** 1048 * i40e_pre_tx_queue_cfg - pre tx queue configure 1049 * @hw: pointer to the HW structure 1050 * @queue: target PF queue index 1051 * @enable: state change request 1052 * 1053 * Handles hw requirement to indicate intention to enable 1054 * or disable target queue. 1055 **/ 1056 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1057 { 1058 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1059 u32 reg_block = 0; 1060 u32 reg_val; 1061 1062 if (abs_queue_idx >= 128) { 1063 reg_block = abs_queue_idx / 128; 1064 abs_queue_idx %= 128; 1065 } 1066 1067 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1068 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1069 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1070 1071 if (enable) 1072 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1073 else 1074 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1075 1076 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1077 } 1078 1079 /** 1080 * i40e_read_pba_string - Reads part number string from EEPROM 1081 * @hw: pointer to hardware structure 1082 * @pba_num: stores the part number string from the EEPROM 1083 * @pba_num_size: part number string buffer length 1084 * 1085 * Reads the part number string from the EEPROM. 1086 **/ 1087 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1088 u32 pba_num_size) 1089 { 1090 i40e_status status = 0; 1091 u16 pba_word = 0; 1092 u16 pba_size = 0; 1093 u16 pba_ptr = 0; 1094 u16 i = 0; 1095 1096 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1097 if (status || (pba_word != 0xFAFA)) { 1098 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n"); 1099 return status; 1100 } 1101 1102 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1103 if (status) { 1104 hw_dbg(hw, "Failed to read PBA Block pointer.\n"); 1105 return status; 1106 } 1107 1108 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1109 if (status) { 1110 hw_dbg(hw, "Failed to read PBA Block size.\n"); 1111 return status; 1112 } 1113 1114 /* Subtract one to get PBA word count (PBA Size word is included in 1115 * total size) 1116 */ 1117 pba_size--; 1118 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1119 hw_dbg(hw, "Buffer to small for PBA data.\n"); 1120 return I40E_ERR_PARAM; 1121 } 1122 1123 for (i = 0; i < pba_size; i++) { 1124 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1125 if (status) { 1126 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i); 1127 return status; 1128 } 1129 1130 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1131 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1132 } 1133 pba_num[(pba_size * 2)] = '\0'; 1134 1135 return status; 1136 } 1137 1138 /** 1139 * i40e_get_media_type - Gets media type 1140 * @hw: pointer to the hardware structure 1141 **/ 1142 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1143 { 1144 enum i40e_media_type media; 1145 1146 switch (hw->phy.link_info.phy_type) { 1147 case I40E_PHY_TYPE_10GBASE_SR: 1148 case I40E_PHY_TYPE_10GBASE_LR: 1149 case I40E_PHY_TYPE_1000BASE_SX: 1150 case I40E_PHY_TYPE_1000BASE_LX: 1151 case I40E_PHY_TYPE_40GBASE_SR4: 1152 case I40E_PHY_TYPE_40GBASE_LR4: 1153 case I40E_PHY_TYPE_25GBASE_LR: 1154 case I40E_PHY_TYPE_25GBASE_SR: 1155 media = I40E_MEDIA_TYPE_FIBER; 1156 break; 1157 case I40E_PHY_TYPE_100BASE_TX: 1158 case I40E_PHY_TYPE_1000BASE_T: 1159 case I40E_PHY_TYPE_2_5GBASE_T: 1160 case I40E_PHY_TYPE_5GBASE_T: 1161 case I40E_PHY_TYPE_10GBASE_T: 1162 media = I40E_MEDIA_TYPE_BASET; 1163 break; 1164 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1165 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1166 case I40E_PHY_TYPE_10GBASE_CR1: 1167 case I40E_PHY_TYPE_40GBASE_CR4: 1168 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1169 case I40E_PHY_TYPE_40GBASE_AOC: 1170 case I40E_PHY_TYPE_10GBASE_AOC: 1171 case I40E_PHY_TYPE_25GBASE_CR: 1172 case I40E_PHY_TYPE_25GBASE_AOC: 1173 case I40E_PHY_TYPE_25GBASE_ACC: 1174 media = I40E_MEDIA_TYPE_DA; 1175 break; 1176 case I40E_PHY_TYPE_1000BASE_KX: 1177 case I40E_PHY_TYPE_10GBASE_KX4: 1178 case I40E_PHY_TYPE_10GBASE_KR: 1179 case I40E_PHY_TYPE_40GBASE_KR4: 1180 case I40E_PHY_TYPE_20GBASE_KR2: 1181 case I40E_PHY_TYPE_25GBASE_KR: 1182 media = I40E_MEDIA_TYPE_BACKPLANE; 1183 break; 1184 case I40E_PHY_TYPE_SGMII: 1185 case I40E_PHY_TYPE_XAUI: 1186 case I40E_PHY_TYPE_XFI: 1187 case I40E_PHY_TYPE_XLAUI: 1188 case I40E_PHY_TYPE_XLPPI: 1189 default: 1190 media = I40E_MEDIA_TYPE_UNKNOWN; 1191 break; 1192 } 1193 1194 return media; 1195 } 1196 1197 /** 1198 * i40e_poll_globr - Poll for Global Reset completion 1199 * @hw: pointer to the hardware structure 1200 * @retry_limit: how many times to retry before failure 1201 **/ 1202 static i40e_status i40e_poll_globr(struct i40e_hw *hw, 1203 u32 retry_limit) 1204 { 1205 u32 cnt, reg = 0; 1206 1207 for (cnt = 0; cnt < retry_limit; cnt++) { 1208 reg = rd32(hw, I40E_GLGEN_RSTAT); 1209 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1210 return 0; 1211 msleep(100); 1212 } 1213 1214 hw_dbg(hw, "Global reset failed.\n"); 1215 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); 1216 1217 return I40E_ERR_RESET_FAILED; 1218 } 1219 1220 #define I40E_PF_RESET_WAIT_COUNT_A0 200 1221 #define I40E_PF_RESET_WAIT_COUNT 200 1222 /** 1223 * i40e_pf_reset - Reset the PF 1224 * @hw: pointer to the hardware structure 1225 * 1226 * Assuming someone else has triggered a global reset, 1227 * assure the global reset is complete and then reset the PF 1228 **/ 1229 i40e_status i40e_pf_reset(struct i40e_hw *hw) 1230 { 1231 u32 cnt = 0; 1232 u32 cnt1 = 0; 1233 u32 reg = 0; 1234 u32 grst_del; 1235 1236 /* Poll for Global Reset steady state in case of recent GRST. 1237 * The grst delay value is in 100ms units, and we'll wait a 1238 * couple counts longer to be sure we don't just miss the end. 1239 */ 1240 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1241 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1242 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1243 1244 /* It can take upto 15 secs for GRST steady state. 1245 * Bump it to 16 secs max to be safe. 1246 */ 1247 grst_del = grst_del * 20; 1248 1249 for (cnt = 0; cnt < grst_del; cnt++) { 1250 reg = rd32(hw, I40E_GLGEN_RSTAT); 1251 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1252 break; 1253 msleep(100); 1254 } 1255 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1256 hw_dbg(hw, "Global reset polling failed to complete.\n"); 1257 return I40E_ERR_RESET_FAILED; 1258 } 1259 1260 /* Now Wait for the FW to be ready */ 1261 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1262 reg = rd32(hw, I40E_GLNVM_ULD); 1263 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1265 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1267 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 1268 break; 1269 } 1270 usleep_range(10000, 20000); 1271 } 1272 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1273 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1274 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 1275 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 1276 return I40E_ERR_RESET_FAILED; 1277 } 1278 1279 /* If there was a Global Reset in progress when we got here, 1280 * we don't need to do the PF Reset 1281 */ 1282 if (!cnt) { 1283 u32 reg2 = 0; 1284 if (hw->revision_id == 0) 1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 1286 else 1287 cnt = I40E_PF_RESET_WAIT_COUNT; 1288 reg = rd32(hw, I40E_PFGEN_CTRL); 1289 wr32(hw, I40E_PFGEN_CTRL, 1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1291 for (; cnt; cnt--) { 1292 reg = rd32(hw, I40E_PFGEN_CTRL); 1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1294 break; 1295 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1296 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) 1297 break; 1298 usleep_range(1000, 2000); 1299 } 1300 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1301 if (i40e_poll_globr(hw, grst_del)) 1302 return I40E_ERR_RESET_FAILED; 1303 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1304 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1305 return I40E_ERR_RESET_FAILED; 1306 } 1307 } 1308 1309 i40e_clear_pxe_mode(hw); 1310 1311 return 0; 1312 } 1313 1314 /** 1315 * i40e_clear_hw - clear out any left over hw state 1316 * @hw: pointer to the hw struct 1317 * 1318 * Clear queues and interrupts, typically called at init time, 1319 * but after the capabilities have been found so we know how many 1320 * queues and msix vectors have been allocated. 1321 **/ 1322 void i40e_clear_hw(struct i40e_hw *hw) 1323 { 1324 u32 num_queues, base_queue; 1325 u32 num_pf_int; 1326 u32 num_vf_int; 1327 u32 num_vfs; 1328 u32 i, j; 1329 u32 val; 1330 u32 eol = 0x7ff; 1331 1332 /* get number of interrupts, queues, and VFs */ 1333 val = rd32(hw, I40E_GLPCI_CNF2); 1334 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1335 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1336 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1337 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1338 1339 val = rd32(hw, I40E_PFLAN_QALLOC); 1340 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1341 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1342 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1343 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1344 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1345 num_queues = (j - base_queue) + 1; 1346 else 1347 num_queues = 0; 1348 1349 val = rd32(hw, I40E_PF_VT_PFALLOC); 1350 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1351 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1352 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1353 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1354 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1355 num_vfs = (j - i) + 1; 1356 else 1357 num_vfs = 0; 1358 1359 /* stop all the interrupts */ 1360 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1361 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1362 for (i = 0; i < num_pf_int - 2; i++) 1363 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1364 1365 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1366 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1367 wr32(hw, I40E_PFINT_LNKLST0, val); 1368 for (i = 0; i < num_pf_int - 2; i++) 1369 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1370 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1371 for (i = 0; i < num_vfs; i++) 1372 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1373 for (i = 0; i < num_vf_int - 2; i++) 1374 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1375 1376 /* warn the HW of the coming Tx disables */ 1377 for (i = 0; i < num_queues; i++) { 1378 u32 abs_queue_idx = base_queue + i; 1379 u32 reg_block = 0; 1380 1381 if (abs_queue_idx >= 128) { 1382 reg_block = abs_queue_idx / 128; 1383 abs_queue_idx %= 128; 1384 } 1385 1386 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1387 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1388 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1389 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1390 1391 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1392 } 1393 udelay(400); 1394 1395 /* stop all the queues */ 1396 for (i = 0; i < num_queues; i++) { 1397 wr32(hw, I40E_QINT_TQCTL(i), 0); 1398 wr32(hw, I40E_QTX_ENA(i), 0); 1399 wr32(hw, I40E_QINT_RQCTL(i), 0); 1400 wr32(hw, I40E_QRX_ENA(i), 0); 1401 } 1402 1403 /* short wait for all queue disables to settle */ 1404 udelay(50); 1405 } 1406 1407 /** 1408 * i40e_clear_pxe_mode - clear pxe operations mode 1409 * @hw: pointer to the hw struct 1410 * 1411 * Make sure all PXE mode settings are cleared, including things 1412 * like descriptor fetch/write-back mode. 1413 **/ 1414 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1415 { 1416 u32 reg; 1417 1418 if (i40e_check_asq_alive(hw)) 1419 i40e_aq_clear_pxe_mode(hw, NULL); 1420 1421 /* Clear single descriptor fetch/write-back mode */ 1422 reg = rd32(hw, I40E_GLLAN_RCTL_0); 1423 1424 if (hw->revision_id == 0) { 1425 /* As a work around clear PXE_MODE instead of setting it */ 1426 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 1427 } else { 1428 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 1429 } 1430 } 1431 1432 /** 1433 * i40e_led_is_mine - helper to find matching led 1434 * @hw: pointer to the hw struct 1435 * @idx: index into GPIO registers 1436 * 1437 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1438 */ 1439 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1440 { 1441 u32 gpio_val = 0; 1442 u32 port; 1443 1444 if (!hw->func_caps.led[idx]) 1445 return 0; 1446 1447 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1448 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1449 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1450 1451 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1452 * if it is not our port then ignore 1453 */ 1454 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1455 (port != hw->port)) 1456 return 0; 1457 1458 return gpio_val; 1459 } 1460 1461 #define I40E_COMBINED_ACTIVITY 0xA 1462 #define I40E_FILTER_ACTIVITY 0xE 1463 #define I40E_LINK_ACTIVITY 0xC 1464 #define I40E_MAC_ACTIVITY 0xD 1465 #define I40E_LED0 22 1466 1467 /** 1468 * i40e_led_get - return current on/off mode 1469 * @hw: pointer to the hw struct 1470 * 1471 * The value returned is the 'mode' field as defined in the 1472 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1473 * values are variations of possible behaviors relating to 1474 * blink, link, and wire. 1475 **/ 1476 u32 i40e_led_get(struct i40e_hw *hw) 1477 { 1478 u32 mode = 0; 1479 int i; 1480 1481 /* as per the documentation GPIO 22-29 are the LED 1482 * GPIO pins named LED0..LED7 1483 */ 1484 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1485 u32 gpio_val = i40e_led_is_mine(hw, i); 1486 1487 if (!gpio_val) 1488 continue; 1489 1490 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1491 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1492 break; 1493 } 1494 1495 return mode; 1496 } 1497 1498 /** 1499 * i40e_led_set - set new on/off mode 1500 * @hw: pointer to the hw struct 1501 * @mode: 0=off, 0xf=on (else see manual for mode details) 1502 * @blink: true if the LED should blink when on, false if steady 1503 * 1504 * if this function is used to turn on the blink it should 1505 * be used to disable the blink when restoring the original state. 1506 **/ 1507 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1508 { 1509 int i; 1510 1511 if (mode & 0xfffffff0) 1512 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1513 1514 /* as per the documentation GPIO 22-29 are the LED 1515 * GPIO pins named LED0..LED7 1516 */ 1517 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1518 u32 gpio_val = i40e_led_is_mine(hw, i); 1519 1520 if (!gpio_val) 1521 continue; 1522 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1523 /* this & is a bit of paranoia, but serves as a range check */ 1524 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1525 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1526 1527 if (blink) 1528 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1529 else 1530 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1531 1532 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1533 break; 1534 } 1535 } 1536 1537 /* Admin command wrappers */ 1538 1539 /** 1540 * i40e_aq_get_phy_capabilities 1541 * @hw: pointer to the hw struct 1542 * @abilities: structure for PHY capabilities to be filled 1543 * @qualified_modules: report Qualified Modules 1544 * @report_init: report init capabilities (active are default) 1545 * @cmd_details: pointer to command details structure or NULL 1546 * 1547 * Returns the various PHY abilities supported on the Port. 1548 **/ 1549 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1550 bool qualified_modules, bool report_init, 1551 struct i40e_aq_get_phy_abilities_resp *abilities, 1552 struct i40e_asq_cmd_details *cmd_details) 1553 { 1554 struct i40e_aq_desc desc; 1555 i40e_status status; 1556 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1557 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1558 1559 if (!abilities) 1560 return I40E_ERR_PARAM; 1561 1562 do { 1563 i40e_fill_default_direct_cmd_desc(&desc, 1564 i40e_aqc_opc_get_phy_abilities); 1565 1566 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1567 if (abilities_size > I40E_AQ_LARGE_BUF) 1568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1569 1570 if (qualified_modules) 1571 desc.params.external.param0 |= 1572 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1573 1574 if (report_init) 1575 desc.params.external.param0 |= 1576 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1577 1578 status = i40e_asq_send_command(hw, &desc, abilities, 1579 abilities_size, cmd_details); 1580 1581 switch (hw->aq.asq_last_status) { 1582 case I40E_AQ_RC_EIO: 1583 status = I40E_ERR_UNKNOWN_PHY; 1584 break; 1585 case I40E_AQ_RC_EAGAIN: 1586 usleep_range(1000, 2000); 1587 total_delay++; 1588 status = I40E_ERR_TIMEOUT; 1589 break; 1590 /* also covers I40E_AQ_RC_OK */ 1591 default: 1592 break; 1593 } 1594 1595 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) && 1596 (total_delay < max_delay)); 1597 1598 if (status) 1599 return status; 1600 1601 if (report_init) { 1602 if (hw->mac.type == I40E_MAC_XL710 && 1603 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1604 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1605 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1606 } else { 1607 hw->phy.phy_types = le32_to_cpu(abilities->phy_type); 1608 hw->phy.phy_types |= 1609 ((u64)abilities->phy_type_ext << 32); 1610 } 1611 } 1612 1613 return status; 1614 } 1615 1616 /** 1617 * i40e_aq_set_phy_config 1618 * @hw: pointer to the hw struct 1619 * @config: structure with PHY configuration to be set 1620 * @cmd_details: pointer to command details structure or NULL 1621 * 1622 * Set the various PHY configuration parameters 1623 * supported on the Port.One or more of the Set PHY config parameters may be 1624 * ignored in an MFP mode as the PF may not have the privilege to set some 1625 * of the PHY Config parameters. This status will be indicated by the 1626 * command response. 1627 **/ 1628 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1629 struct i40e_aq_set_phy_config *config, 1630 struct i40e_asq_cmd_details *cmd_details) 1631 { 1632 struct i40e_aq_desc desc; 1633 struct i40e_aq_set_phy_config *cmd = 1634 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1635 enum i40e_status_code status; 1636 1637 if (!config) 1638 return I40E_ERR_PARAM; 1639 1640 i40e_fill_default_direct_cmd_desc(&desc, 1641 i40e_aqc_opc_set_phy_config); 1642 1643 *cmd = *config; 1644 1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1646 1647 return status; 1648 } 1649 1650 static noinline_for_stack enum i40e_status_code 1651 i40e_set_fc_status(struct i40e_hw *hw, 1652 struct i40e_aq_get_phy_abilities_resp *abilities, 1653 bool atomic_restart) 1654 { 1655 struct i40e_aq_set_phy_config config; 1656 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1657 u8 pause_mask = 0x0; 1658 1659 switch (fc_mode) { 1660 case I40E_FC_FULL: 1661 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1662 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1663 break; 1664 case I40E_FC_RX_PAUSE: 1665 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1666 break; 1667 case I40E_FC_TX_PAUSE: 1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1669 break; 1670 default: 1671 break; 1672 } 1673 1674 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1675 /* clear the old pause settings */ 1676 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1677 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1678 /* set the new abilities */ 1679 config.abilities |= pause_mask; 1680 /* If the abilities have changed, then set the new config */ 1681 if (config.abilities == abilities->abilities) 1682 return 0; 1683 1684 /* Auto restart link so settings take effect */ 1685 if (atomic_restart) 1686 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1687 /* Copy over all the old settings */ 1688 config.phy_type = abilities->phy_type; 1689 config.phy_type_ext = abilities->phy_type_ext; 1690 config.link_speed = abilities->link_speed; 1691 config.eee_capability = abilities->eee_capability; 1692 config.eeer = abilities->eeer_val; 1693 config.low_power_ctrl = abilities->d3_lpan; 1694 config.fec_config = abilities->fec_cfg_curr_mod_ext_info & 1695 I40E_AQ_PHY_FEC_CONFIG_MASK; 1696 1697 return i40e_aq_set_phy_config(hw, &config, NULL); 1698 } 1699 1700 /** 1701 * i40e_set_fc 1702 * @hw: pointer to the hw struct 1703 * @aq_failures: buffer to return AdminQ failure information 1704 * @atomic_restart: whether to enable atomic link restart 1705 * 1706 * Set the requested flow control mode using set_phy_config. 1707 **/ 1708 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1709 bool atomic_restart) 1710 { 1711 struct i40e_aq_get_phy_abilities_resp abilities; 1712 enum i40e_status_code status; 1713 1714 *aq_failures = 0x0; 1715 1716 /* Get the current phy config */ 1717 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1718 NULL); 1719 if (status) { 1720 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1721 return status; 1722 } 1723 1724 status = i40e_set_fc_status(hw, &abilities, atomic_restart); 1725 if (status) 1726 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1727 1728 /* Update the link info */ 1729 status = i40e_update_link_info(hw); 1730 if (status) { 1731 /* Wait a little bit (on 40G cards it sometimes takes a really 1732 * long time for link to come back from the atomic reset) 1733 * and try once more 1734 */ 1735 msleep(1000); 1736 status = i40e_update_link_info(hw); 1737 } 1738 if (status) 1739 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1740 1741 return status; 1742 } 1743 1744 /** 1745 * i40e_aq_clear_pxe_mode 1746 * @hw: pointer to the hw struct 1747 * @cmd_details: pointer to command details structure or NULL 1748 * 1749 * Tell the firmware that the driver is taking over from PXE 1750 **/ 1751 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1752 struct i40e_asq_cmd_details *cmd_details) 1753 { 1754 i40e_status status; 1755 struct i40e_aq_desc desc; 1756 struct i40e_aqc_clear_pxe *cmd = 1757 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1758 1759 i40e_fill_default_direct_cmd_desc(&desc, 1760 i40e_aqc_opc_clear_pxe_mode); 1761 1762 cmd->rx_cnt = 0x2; 1763 1764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1765 1766 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1767 1768 return status; 1769 } 1770 1771 /** 1772 * i40e_aq_set_link_restart_an 1773 * @hw: pointer to the hw struct 1774 * @enable_link: if true: enable link, if false: disable link 1775 * @cmd_details: pointer to command details structure or NULL 1776 * 1777 * Sets up the link and restarts the Auto-Negotiation over the link. 1778 **/ 1779 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1780 bool enable_link, 1781 struct i40e_asq_cmd_details *cmd_details) 1782 { 1783 struct i40e_aq_desc desc; 1784 struct i40e_aqc_set_link_restart_an *cmd = 1785 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1786 i40e_status status; 1787 1788 i40e_fill_default_direct_cmd_desc(&desc, 1789 i40e_aqc_opc_set_link_restart_an); 1790 1791 cmd->command = I40E_AQ_PHY_RESTART_AN; 1792 if (enable_link) 1793 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1794 else 1795 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1796 1797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1798 1799 return status; 1800 } 1801 1802 /** 1803 * i40e_aq_get_link_info 1804 * @hw: pointer to the hw struct 1805 * @enable_lse: enable/disable LinkStatusEvent reporting 1806 * @link: pointer to link status structure - optional 1807 * @cmd_details: pointer to command details structure or NULL 1808 * 1809 * Returns the link status of the adapter. 1810 **/ 1811 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1812 bool enable_lse, struct i40e_link_status *link, 1813 struct i40e_asq_cmd_details *cmd_details) 1814 { 1815 struct i40e_aq_desc desc; 1816 struct i40e_aqc_get_link_status *resp = 1817 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1818 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1819 i40e_status status; 1820 bool tx_pause, rx_pause; 1821 u16 command_flags; 1822 1823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1824 1825 if (enable_lse) 1826 command_flags = I40E_AQ_LSE_ENABLE; 1827 else 1828 command_flags = I40E_AQ_LSE_DISABLE; 1829 resp->command_flags = cpu_to_le16(command_flags); 1830 1831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1832 1833 if (status) 1834 goto aq_get_link_info_exit; 1835 1836 /* save off old link status information */ 1837 hw->phy.link_info_old = *hw_link_info; 1838 1839 /* update link status */ 1840 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1841 hw->phy.media_type = i40e_get_media_type(hw); 1842 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1843 hw_link_info->link_info = resp->link_info; 1844 hw_link_info->an_info = resp->an_info; 1845 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1846 I40E_AQ_CONFIG_FEC_RS_ENA); 1847 hw_link_info->ext_info = resp->ext_info; 1848 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1849 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1850 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1851 1852 /* update fc info */ 1853 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1854 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1855 if (tx_pause & rx_pause) 1856 hw->fc.current_mode = I40E_FC_FULL; 1857 else if (tx_pause) 1858 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1859 else if (rx_pause) 1860 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1861 else 1862 hw->fc.current_mode = I40E_FC_NONE; 1863 1864 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1865 hw_link_info->crc_enable = true; 1866 else 1867 hw_link_info->crc_enable = false; 1868 1869 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED)) 1870 hw_link_info->lse_enable = true; 1871 else 1872 hw_link_info->lse_enable = false; 1873 1874 if ((hw->mac.type == I40E_MAC_XL710) && 1875 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1876 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1877 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1878 1879 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 1880 __le32 tmp; 1881 1882 memcpy(&tmp, resp->link_type, sizeof(tmp)); 1883 hw->phy.phy_types = le32_to_cpu(tmp); 1884 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1885 } 1886 1887 /* save link status information */ 1888 if (link) 1889 *link = *hw_link_info; 1890 1891 /* flag cleared so helper functions don't call AQ again */ 1892 hw->phy.get_link_info = false; 1893 1894 aq_get_link_info_exit: 1895 return status; 1896 } 1897 1898 /** 1899 * i40e_aq_set_phy_int_mask 1900 * @hw: pointer to the hw struct 1901 * @mask: interrupt mask to be set 1902 * @cmd_details: pointer to command details structure or NULL 1903 * 1904 * Set link interrupt mask. 1905 **/ 1906 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1907 u16 mask, 1908 struct i40e_asq_cmd_details *cmd_details) 1909 { 1910 struct i40e_aq_desc desc; 1911 struct i40e_aqc_set_phy_int_mask *cmd = 1912 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1913 i40e_status status; 1914 1915 i40e_fill_default_direct_cmd_desc(&desc, 1916 i40e_aqc_opc_set_phy_int_mask); 1917 1918 cmd->event_mask = cpu_to_le16(mask); 1919 1920 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1921 1922 return status; 1923 } 1924 1925 /** 1926 * i40e_aq_set_phy_debug 1927 * @hw: pointer to the hw struct 1928 * @cmd_flags: debug command flags 1929 * @cmd_details: pointer to command details structure or NULL 1930 * 1931 * Reset the external PHY. 1932 **/ 1933 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 1934 struct i40e_asq_cmd_details *cmd_details) 1935 { 1936 struct i40e_aq_desc desc; 1937 struct i40e_aqc_set_phy_debug *cmd = 1938 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 1939 i40e_status status; 1940 1941 i40e_fill_default_direct_cmd_desc(&desc, 1942 i40e_aqc_opc_set_phy_debug); 1943 1944 cmd->command_flags = cmd_flags; 1945 1946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1947 1948 return status; 1949 } 1950 1951 /** 1952 * i40e_aq_add_vsi 1953 * @hw: pointer to the hw struct 1954 * @vsi_ctx: pointer to a vsi context struct 1955 * @cmd_details: pointer to command details structure or NULL 1956 * 1957 * Add a VSI context to the hardware. 1958 **/ 1959 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1960 struct i40e_vsi_context *vsi_ctx, 1961 struct i40e_asq_cmd_details *cmd_details) 1962 { 1963 struct i40e_aq_desc desc; 1964 struct i40e_aqc_add_get_update_vsi *cmd = 1965 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1966 struct i40e_aqc_add_get_update_vsi_completion *resp = 1967 (struct i40e_aqc_add_get_update_vsi_completion *) 1968 &desc.params.raw; 1969 i40e_status status; 1970 1971 i40e_fill_default_direct_cmd_desc(&desc, 1972 i40e_aqc_opc_add_vsi); 1973 1974 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1975 cmd->connection_type = vsi_ctx->connection_type; 1976 cmd->vf_id = vsi_ctx->vf_num; 1977 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1978 1979 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1980 1981 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1982 sizeof(vsi_ctx->info), cmd_details); 1983 1984 if (status) 1985 goto aq_add_vsi_exit; 1986 1987 vsi_ctx->seid = le16_to_cpu(resp->seid); 1988 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1989 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1990 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1991 1992 aq_add_vsi_exit: 1993 return status; 1994 } 1995 1996 /** 1997 * i40e_aq_set_default_vsi 1998 * @hw: pointer to the hw struct 1999 * @seid: vsi number 2000 * @cmd_details: pointer to command details structure or NULL 2001 **/ 2002 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, 2003 u16 seid, 2004 struct i40e_asq_cmd_details *cmd_details) 2005 { 2006 struct i40e_aq_desc desc; 2007 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2008 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2009 &desc.params.raw; 2010 i40e_status status; 2011 2012 i40e_fill_default_direct_cmd_desc(&desc, 2013 i40e_aqc_opc_set_vsi_promiscuous_modes); 2014 2015 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2016 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2017 cmd->seid = cpu_to_le16(seid); 2018 2019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2020 2021 return status; 2022 } 2023 2024 /** 2025 * i40e_aq_clear_default_vsi 2026 * @hw: pointer to the hw struct 2027 * @seid: vsi number 2028 * @cmd_details: pointer to command details structure or NULL 2029 **/ 2030 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2031 u16 seid, 2032 struct i40e_asq_cmd_details *cmd_details) 2033 { 2034 struct i40e_aq_desc desc; 2035 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2036 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2037 &desc.params.raw; 2038 i40e_status status; 2039 2040 i40e_fill_default_direct_cmd_desc(&desc, 2041 i40e_aqc_opc_set_vsi_promiscuous_modes); 2042 2043 cmd->promiscuous_flags = cpu_to_le16(0); 2044 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT); 2045 cmd->seid = cpu_to_le16(seid); 2046 2047 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2048 2049 return status; 2050 } 2051 2052 /** 2053 * i40e_aq_set_vsi_unicast_promiscuous 2054 * @hw: pointer to the hw struct 2055 * @seid: vsi number 2056 * @set: set unicast promiscuous enable/disable 2057 * @cmd_details: pointer to command details structure or NULL 2058 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2059 **/ 2060 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2061 u16 seid, bool set, 2062 struct i40e_asq_cmd_details *cmd_details, 2063 bool rx_only_promisc) 2064 { 2065 struct i40e_aq_desc desc; 2066 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2067 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2068 i40e_status status; 2069 u16 flags = 0; 2070 2071 i40e_fill_default_direct_cmd_desc(&desc, 2072 i40e_aqc_opc_set_vsi_promiscuous_modes); 2073 2074 if (set) { 2075 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2076 if (rx_only_promisc && 2077 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2078 (hw->aq.api_maj_ver > 1))) 2079 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2080 } 2081 2082 cmd->promiscuous_flags = cpu_to_le16(flags); 2083 2084 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2085 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2086 (hw->aq.api_maj_ver > 1)) 2087 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX); 2088 2089 cmd->seid = cpu_to_le16(seid); 2090 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2091 2092 return status; 2093 } 2094 2095 /** 2096 * i40e_aq_set_vsi_multicast_promiscuous 2097 * @hw: pointer to the hw struct 2098 * @seid: vsi number 2099 * @set: set multicast promiscuous enable/disable 2100 * @cmd_details: pointer to command details structure or NULL 2101 **/ 2102 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2103 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2104 { 2105 struct i40e_aq_desc desc; 2106 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2107 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2108 i40e_status status; 2109 u16 flags = 0; 2110 2111 i40e_fill_default_direct_cmd_desc(&desc, 2112 i40e_aqc_opc_set_vsi_promiscuous_modes); 2113 2114 if (set) 2115 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2116 2117 cmd->promiscuous_flags = cpu_to_le16(flags); 2118 2119 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2120 2121 cmd->seid = cpu_to_le16(seid); 2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2123 2124 return status; 2125 } 2126 2127 /** 2128 * i40e_aq_set_vsi_mc_promisc_on_vlan 2129 * @hw: pointer to the hw struct 2130 * @seid: vsi number 2131 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2132 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2133 * @cmd_details: pointer to command details structure or NULL 2134 **/ 2135 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2136 u16 seid, bool enable, 2137 u16 vid, 2138 struct i40e_asq_cmd_details *cmd_details) 2139 { 2140 struct i40e_aq_desc desc; 2141 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2142 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2143 enum i40e_status_code status; 2144 u16 flags = 0; 2145 2146 i40e_fill_default_direct_cmd_desc(&desc, 2147 i40e_aqc_opc_set_vsi_promiscuous_modes); 2148 2149 if (enable) 2150 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2151 2152 cmd->promiscuous_flags = cpu_to_le16(flags); 2153 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2154 cmd->seid = cpu_to_le16(seid); 2155 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2156 2157 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2158 2159 return status; 2160 } 2161 2162 /** 2163 * i40e_aq_set_vsi_uc_promisc_on_vlan 2164 * @hw: pointer to the hw struct 2165 * @seid: vsi number 2166 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2167 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2168 * @cmd_details: pointer to command details structure or NULL 2169 **/ 2170 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2171 u16 seid, bool enable, 2172 u16 vid, 2173 struct i40e_asq_cmd_details *cmd_details) 2174 { 2175 struct i40e_aq_desc desc; 2176 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2177 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2178 enum i40e_status_code status; 2179 u16 flags = 0; 2180 2181 i40e_fill_default_direct_cmd_desc(&desc, 2182 i40e_aqc_opc_set_vsi_promiscuous_modes); 2183 2184 if (enable) 2185 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2186 2187 cmd->promiscuous_flags = cpu_to_le16(flags); 2188 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2189 cmd->seid = cpu_to_le16(seid); 2190 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2191 2192 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2193 2194 return status; 2195 } 2196 2197 /** 2198 * i40e_aq_set_vsi_bc_promisc_on_vlan 2199 * @hw: pointer to the hw struct 2200 * @seid: vsi number 2201 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2202 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2203 * @cmd_details: pointer to command details structure or NULL 2204 **/ 2205 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2206 u16 seid, bool enable, u16 vid, 2207 struct i40e_asq_cmd_details *cmd_details) 2208 { 2209 struct i40e_aq_desc desc; 2210 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2211 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2212 i40e_status status; 2213 u16 flags = 0; 2214 2215 i40e_fill_default_direct_cmd_desc(&desc, 2216 i40e_aqc_opc_set_vsi_promiscuous_modes); 2217 2218 if (enable) 2219 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2220 2221 cmd->promiscuous_flags = cpu_to_le16(flags); 2222 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2223 cmd->seid = cpu_to_le16(seid); 2224 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2225 2226 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2227 2228 return status; 2229 } 2230 2231 /** 2232 * i40e_aq_set_vsi_broadcast 2233 * @hw: pointer to the hw struct 2234 * @seid: vsi number 2235 * @set_filter: true to set filter, false to clear filter 2236 * @cmd_details: pointer to command details structure or NULL 2237 * 2238 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2239 **/ 2240 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2241 u16 seid, bool set_filter, 2242 struct i40e_asq_cmd_details *cmd_details) 2243 { 2244 struct i40e_aq_desc desc; 2245 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2246 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2247 i40e_status status; 2248 2249 i40e_fill_default_direct_cmd_desc(&desc, 2250 i40e_aqc_opc_set_vsi_promiscuous_modes); 2251 2252 if (set_filter) 2253 cmd->promiscuous_flags 2254 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2255 else 2256 cmd->promiscuous_flags 2257 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2258 2259 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2260 cmd->seid = cpu_to_le16(seid); 2261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2262 2263 return status; 2264 } 2265 2266 /** 2267 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2268 * @hw: pointer to the hw struct 2269 * @seid: vsi number 2270 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2271 * @cmd_details: pointer to command details structure or NULL 2272 **/ 2273 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2274 u16 seid, bool enable, 2275 struct i40e_asq_cmd_details *cmd_details) 2276 { 2277 struct i40e_aq_desc desc; 2278 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2279 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2280 i40e_status status; 2281 u16 flags = 0; 2282 2283 i40e_fill_default_direct_cmd_desc(&desc, 2284 i40e_aqc_opc_set_vsi_promiscuous_modes); 2285 if (enable) 2286 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2287 2288 cmd->promiscuous_flags = cpu_to_le16(flags); 2289 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2290 cmd->seid = cpu_to_le16(seid); 2291 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_get_vsi_params - get VSI configuration info 2299 * @hw: pointer to the hw struct 2300 * @vsi_ctx: pointer to a vsi context struct 2301 * @cmd_details: pointer to command details structure or NULL 2302 **/ 2303 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 2304 struct i40e_vsi_context *vsi_ctx, 2305 struct i40e_asq_cmd_details *cmd_details) 2306 { 2307 struct i40e_aq_desc desc; 2308 struct i40e_aqc_add_get_update_vsi *cmd = 2309 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2310 struct i40e_aqc_add_get_update_vsi_completion *resp = 2311 (struct i40e_aqc_add_get_update_vsi_completion *) 2312 &desc.params.raw; 2313 i40e_status status; 2314 2315 i40e_fill_default_direct_cmd_desc(&desc, 2316 i40e_aqc_opc_get_vsi_parameters); 2317 2318 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2319 2320 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2321 2322 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2323 sizeof(vsi_ctx->info), NULL); 2324 2325 if (status) 2326 goto aq_get_vsi_params_exit; 2327 2328 vsi_ctx->seid = le16_to_cpu(resp->seid); 2329 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 2330 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2331 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2332 2333 aq_get_vsi_params_exit: 2334 return status; 2335 } 2336 2337 /** 2338 * i40e_aq_update_vsi_params 2339 * @hw: pointer to the hw struct 2340 * @vsi_ctx: pointer to a vsi context struct 2341 * @cmd_details: pointer to command details structure or NULL 2342 * 2343 * Update a VSI context. 2344 **/ 2345 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 2346 struct i40e_vsi_context *vsi_ctx, 2347 struct i40e_asq_cmd_details *cmd_details) 2348 { 2349 struct i40e_aq_desc desc; 2350 struct i40e_aqc_add_get_update_vsi *cmd = 2351 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2352 struct i40e_aqc_add_get_update_vsi_completion *resp = 2353 (struct i40e_aqc_add_get_update_vsi_completion *) 2354 &desc.params.raw; 2355 i40e_status status; 2356 2357 i40e_fill_default_direct_cmd_desc(&desc, 2358 i40e_aqc_opc_update_vsi_parameters); 2359 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 2360 2361 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2362 2363 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2364 sizeof(vsi_ctx->info), cmd_details); 2365 2366 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 2367 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 2368 2369 return status; 2370 } 2371 2372 /** 2373 * i40e_aq_get_switch_config 2374 * @hw: pointer to the hardware structure 2375 * @buf: pointer to the result buffer 2376 * @buf_size: length of input buffer 2377 * @start_seid: seid to start for the report, 0 == beginning 2378 * @cmd_details: pointer to command details structure or NULL 2379 * 2380 * Fill the buf with switch configuration returned from AdminQ command 2381 **/ 2382 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 2383 struct i40e_aqc_get_switch_config_resp *buf, 2384 u16 buf_size, u16 *start_seid, 2385 struct i40e_asq_cmd_details *cmd_details) 2386 { 2387 struct i40e_aq_desc desc; 2388 struct i40e_aqc_switch_seid *scfg = 2389 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2390 i40e_status status; 2391 2392 i40e_fill_default_direct_cmd_desc(&desc, 2393 i40e_aqc_opc_get_switch_config); 2394 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2395 if (buf_size > I40E_AQ_LARGE_BUF) 2396 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2397 scfg->seid = cpu_to_le16(*start_seid); 2398 2399 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2400 *start_seid = le16_to_cpu(scfg->seid); 2401 2402 return status; 2403 } 2404 2405 /** 2406 * i40e_aq_set_switch_config 2407 * @hw: pointer to the hardware structure 2408 * @flags: bit flag values to set 2409 * @mode: cloud filter mode 2410 * @valid_flags: which bit flags to set 2411 * @mode: cloud filter mode 2412 * @cmd_details: pointer to command details structure or NULL 2413 * 2414 * Set switch configuration bits 2415 **/ 2416 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2417 u16 flags, 2418 u16 valid_flags, u8 mode, 2419 struct i40e_asq_cmd_details *cmd_details) 2420 { 2421 struct i40e_aq_desc desc; 2422 struct i40e_aqc_set_switch_config *scfg = 2423 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2424 enum i40e_status_code status; 2425 2426 i40e_fill_default_direct_cmd_desc(&desc, 2427 i40e_aqc_opc_set_switch_config); 2428 scfg->flags = cpu_to_le16(flags); 2429 scfg->valid_flags = cpu_to_le16(valid_flags); 2430 scfg->mode = mode; 2431 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2432 scfg->switch_tag = cpu_to_le16(hw->switch_tag); 2433 scfg->first_tag = cpu_to_le16(hw->first_tag); 2434 scfg->second_tag = cpu_to_le16(hw->second_tag); 2435 } 2436 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2437 2438 return status; 2439 } 2440 2441 /** 2442 * i40e_aq_get_firmware_version 2443 * @hw: pointer to the hw struct 2444 * @fw_major_version: firmware major version 2445 * @fw_minor_version: firmware minor version 2446 * @fw_build: firmware build number 2447 * @api_major_version: major queue version 2448 * @api_minor_version: minor queue version 2449 * @cmd_details: pointer to command details structure or NULL 2450 * 2451 * Get the firmware version from the admin queue commands 2452 **/ 2453 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 2454 u16 *fw_major_version, u16 *fw_minor_version, 2455 u32 *fw_build, 2456 u16 *api_major_version, u16 *api_minor_version, 2457 struct i40e_asq_cmd_details *cmd_details) 2458 { 2459 struct i40e_aq_desc desc; 2460 struct i40e_aqc_get_version *resp = 2461 (struct i40e_aqc_get_version *)&desc.params.raw; 2462 i40e_status status; 2463 2464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2465 2466 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2467 2468 if (!status) { 2469 if (fw_major_version) 2470 *fw_major_version = le16_to_cpu(resp->fw_major); 2471 if (fw_minor_version) 2472 *fw_minor_version = le16_to_cpu(resp->fw_minor); 2473 if (fw_build) 2474 *fw_build = le32_to_cpu(resp->fw_build); 2475 if (api_major_version) 2476 *api_major_version = le16_to_cpu(resp->api_major); 2477 if (api_minor_version) 2478 *api_minor_version = le16_to_cpu(resp->api_minor); 2479 } 2480 2481 return status; 2482 } 2483 2484 /** 2485 * i40e_aq_send_driver_version 2486 * @hw: pointer to the hw struct 2487 * @dv: driver's major, minor version 2488 * @cmd_details: pointer to command details structure or NULL 2489 * 2490 * Send the driver version to the firmware 2491 **/ 2492 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 2493 struct i40e_driver_version *dv, 2494 struct i40e_asq_cmd_details *cmd_details) 2495 { 2496 struct i40e_aq_desc desc; 2497 struct i40e_aqc_driver_version *cmd = 2498 (struct i40e_aqc_driver_version *)&desc.params.raw; 2499 i40e_status status; 2500 u16 len; 2501 2502 if (dv == NULL) 2503 return I40E_ERR_PARAM; 2504 2505 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2506 2507 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2508 cmd->driver_major_ver = dv->major_version; 2509 cmd->driver_minor_ver = dv->minor_version; 2510 cmd->driver_build_ver = dv->build_version; 2511 cmd->driver_subbuild_ver = dv->subbuild_version; 2512 2513 len = 0; 2514 while (len < sizeof(dv->driver_string) && 2515 (dv->driver_string[len] < 0x80) && 2516 dv->driver_string[len]) 2517 len++; 2518 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2519 len, cmd_details); 2520 2521 return status; 2522 } 2523 2524 /** 2525 * i40e_get_link_status - get status of the HW network link 2526 * @hw: pointer to the hw struct 2527 * @link_up: pointer to bool (true/false = linkup/linkdown) 2528 * 2529 * Variable link_up true if link is up, false if link is down. 2530 * The variable link_up is invalid if returned value of status != 0 2531 * 2532 * Side effect: LinkStatusEvent reporting becomes enabled 2533 **/ 2534 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2535 { 2536 i40e_status status = 0; 2537 2538 if (hw->phy.get_link_info) { 2539 status = i40e_update_link_info(hw); 2540 2541 if (status) 2542 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2543 status); 2544 } 2545 2546 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2547 2548 return status; 2549 } 2550 2551 /** 2552 * i40e_updatelink_status - update status of the HW network link 2553 * @hw: pointer to the hw struct 2554 **/ 2555 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw) 2556 { 2557 struct i40e_aq_get_phy_abilities_resp abilities; 2558 i40e_status status = 0; 2559 2560 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 2561 if (status) 2562 return status; 2563 2564 /* extra checking needed to ensure link info to user is timely */ 2565 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2566 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2567 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2568 status = i40e_aq_get_phy_capabilities(hw, false, false, 2569 &abilities, NULL); 2570 if (status) 2571 return status; 2572 2573 hw->phy.link_info.req_fec_info = 2574 abilities.fec_cfg_curr_mod_ext_info & 2575 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2576 2577 memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2578 sizeof(hw->phy.link_info.module_type)); 2579 } 2580 2581 return status; 2582 } 2583 2584 /** 2585 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2586 * @hw: pointer to the hw struct 2587 * @uplink_seid: the MAC or other gizmo SEID 2588 * @downlink_seid: the VSI SEID 2589 * @enabled_tc: bitmap of TCs to be enabled 2590 * @default_port: true for default port VSI, false for control port 2591 * @veb_seid: pointer to where to put the resulting VEB SEID 2592 * @enable_stats: true to turn on VEB stats 2593 * @cmd_details: pointer to command details structure or NULL 2594 * 2595 * This asks the FW to add a VEB between the uplink and downlink 2596 * elements. If the uplink SEID is 0, this will be a floating VEB. 2597 **/ 2598 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2599 u16 downlink_seid, u8 enabled_tc, 2600 bool default_port, u16 *veb_seid, 2601 bool enable_stats, 2602 struct i40e_asq_cmd_details *cmd_details) 2603 { 2604 struct i40e_aq_desc desc; 2605 struct i40e_aqc_add_veb *cmd = 2606 (struct i40e_aqc_add_veb *)&desc.params.raw; 2607 struct i40e_aqc_add_veb_completion *resp = 2608 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2609 i40e_status status; 2610 u16 veb_flags = 0; 2611 2612 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2613 if (!!uplink_seid != !!downlink_seid) 2614 return I40E_ERR_PARAM; 2615 2616 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2617 2618 cmd->uplink_seid = cpu_to_le16(uplink_seid); 2619 cmd->downlink_seid = cpu_to_le16(downlink_seid); 2620 cmd->enable_tcs = enabled_tc; 2621 if (!uplink_seid) 2622 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2623 if (default_port) 2624 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2625 else 2626 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2627 2628 /* reverse logic here: set the bitflag to disable the stats */ 2629 if (!enable_stats) 2630 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2631 2632 cmd->veb_flags = cpu_to_le16(veb_flags); 2633 2634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2635 2636 if (!status && veb_seid) 2637 *veb_seid = le16_to_cpu(resp->veb_seid); 2638 2639 return status; 2640 } 2641 2642 /** 2643 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2644 * @hw: pointer to the hw struct 2645 * @veb_seid: the SEID of the VEB to query 2646 * @switch_id: the uplink switch id 2647 * @floating: set to true if the VEB is floating 2648 * @statistic_index: index of the stats counter block for this VEB 2649 * @vebs_used: number of VEB's used by function 2650 * @vebs_free: total VEB's not reserved by any function 2651 * @cmd_details: pointer to command details structure or NULL 2652 * 2653 * This retrieves the parameters for a particular VEB, specified by 2654 * uplink_seid, and returns them to the caller. 2655 **/ 2656 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2657 u16 veb_seid, u16 *switch_id, 2658 bool *floating, u16 *statistic_index, 2659 u16 *vebs_used, u16 *vebs_free, 2660 struct i40e_asq_cmd_details *cmd_details) 2661 { 2662 struct i40e_aq_desc desc; 2663 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2664 (struct i40e_aqc_get_veb_parameters_completion *) 2665 &desc.params.raw; 2666 i40e_status status; 2667 2668 if (veb_seid == 0) 2669 return I40E_ERR_PARAM; 2670 2671 i40e_fill_default_direct_cmd_desc(&desc, 2672 i40e_aqc_opc_get_veb_parameters); 2673 cmd_resp->seid = cpu_to_le16(veb_seid); 2674 2675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2676 if (status) 2677 goto get_veb_exit; 2678 2679 if (switch_id) 2680 *switch_id = le16_to_cpu(cmd_resp->switch_id); 2681 if (statistic_index) 2682 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 2683 if (vebs_used) 2684 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 2685 if (vebs_free) 2686 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 2687 if (floating) { 2688 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 2689 2690 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2691 *floating = true; 2692 else 2693 *floating = false; 2694 } 2695 2696 get_veb_exit: 2697 return status; 2698 } 2699 2700 /** 2701 * i40e_aq_add_macvlan 2702 * @hw: pointer to the hw struct 2703 * @seid: VSI for the mac address 2704 * @mv_list: list of macvlans to be added 2705 * @count: length of the list 2706 * @cmd_details: pointer to command details structure or NULL 2707 * 2708 * Add MAC/VLAN addresses to the HW filtering 2709 **/ 2710 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2711 struct i40e_aqc_add_macvlan_element_data *mv_list, 2712 u16 count, struct i40e_asq_cmd_details *cmd_details) 2713 { 2714 struct i40e_aq_desc desc; 2715 struct i40e_aqc_macvlan *cmd = 2716 (struct i40e_aqc_macvlan *)&desc.params.raw; 2717 i40e_status status; 2718 u16 buf_size; 2719 int i; 2720 2721 if (count == 0 || !mv_list || !hw) 2722 return I40E_ERR_PARAM; 2723 2724 buf_size = count * sizeof(*mv_list); 2725 2726 /* prep the rest of the request */ 2727 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2728 cmd->num_addresses = cpu_to_le16(count); 2729 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2730 cmd->seid[1] = 0; 2731 cmd->seid[2] = 0; 2732 2733 for (i = 0; i < count; i++) 2734 if (is_multicast_ether_addr(mv_list[i].mac_addr)) 2735 mv_list[i].flags |= 2736 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2737 2738 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2739 if (buf_size > I40E_AQ_LARGE_BUF) 2740 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2741 2742 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2743 cmd_details); 2744 2745 return status; 2746 } 2747 2748 /** 2749 * i40e_aq_remove_macvlan 2750 * @hw: pointer to the hw struct 2751 * @seid: VSI for the mac address 2752 * @mv_list: list of macvlans to be removed 2753 * @count: length of the list 2754 * @cmd_details: pointer to command details structure or NULL 2755 * 2756 * Remove MAC/VLAN addresses from the HW filtering 2757 **/ 2758 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2759 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2760 u16 count, struct i40e_asq_cmd_details *cmd_details) 2761 { 2762 struct i40e_aq_desc desc; 2763 struct i40e_aqc_macvlan *cmd = 2764 (struct i40e_aqc_macvlan *)&desc.params.raw; 2765 i40e_status status; 2766 u16 buf_size; 2767 2768 if (count == 0 || !mv_list || !hw) 2769 return I40E_ERR_PARAM; 2770 2771 buf_size = count * sizeof(*mv_list); 2772 2773 /* prep the rest of the request */ 2774 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2775 cmd->num_addresses = cpu_to_le16(count); 2776 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2777 cmd->seid[1] = 0; 2778 cmd->seid[2] = 0; 2779 2780 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2781 if (buf_size > I40E_AQ_LARGE_BUF) 2782 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2783 2784 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2785 cmd_details); 2786 2787 return status; 2788 } 2789 2790 /** 2791 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2792 * @hw: pointer to the hw struct 2793 * @opcode: AQ opcode for add or delete mirror rule 2794 * @sw_seid: Switch SEID (to which rule refers) 2795 * @rule_type: Rule Type (ingress/egress/VLAN) 2796 * @id: Destination VSI SEID or Rule ID 2797 * @count: length of the list 2798 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2799 * @cmd_details: pointer to command details structure or NULL 2800 * @rule_id: Rule ID returned from FW 2801 * @rules_used: Number of rules used in internal switch 2802 * @rules_free: Number of rules free in internal switch 2803 * 2804 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2805 * VEBs/VEPA elements only 2806 **/ 2807 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw, 2808 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2809 u16 count, __le16 *mr_list, 2810 struct i40e_asq_cmd_details *cmd_details, 2811 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2812 { 2813 struct i40e_aq_desc desc; 2814 struct i40e_aqc_add_delete_mirror_rule *cmd = 2815 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2816 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2817 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2818 i40e_status status; 2819 u16 buf_size; 2820 2821 buf_size = count * sizeof(*mr_list); 2822 2823 /* prep the rest of the request */ 2824 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2825 cmd->seid = cpu_to_le16(sw_seid); 2826 cmd->rule_type = cpu_to_le16(rule_type & 2827 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2828 cmd->num_entries = cpu_to_le16(count); 2829 /* Dest VSI for add, rule_id for delete */ 2830 cmd->destination = cpu_to_le16(id); 2831 if (mr_list) { 2832 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2833 I40E_AQ_FLAG_RD)); 2834 if (buf_size > I40E_AQ_LARGE_BUF) 2835 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2836 } 2837 2838 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 2839 cmd_details); 2840 if (!status || 2841 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 2842 if (rule_id) 2843 *rule_id = le16_to_cpu(resp->rule_id); 2844 if (rules_used) 2845 *rules_used = le16_to_cpu(resp->mirror_rules_used); 2846 if (rules_free) 2847 *rules_free = le16_to_cpu(resp->mirror_rules_free); 2848 } 2849 return status; 2850 } 2851 2852 /** 2853 * i40e_aq_add_mirrorrule - add a mirror rule 2854 * @hw: pointer to the hw struct 2855 * @sw_seid: Switch SEID (to which rule refers) 2856 * @rule_type: Rule Type (ingress/egress/VLAN) 2857 * @dest_vsi: SEID of VSI to which packets will be mirrored 2858 * @count: length of the list 2859 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2860 * @cmd_details: pointer to command details structure or NULL 2861 * @rule_id: Rule ID returned from FW 2862 * @rules_used: Number of rules used in internal switch 2863 * @rules_free: Number of rules free in internal switch 2864 * 2865 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 2866 **/ 2867 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2868 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 2869 struct i40e_asq_cmd_details *cmd_details, 2870 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2871 { 2872 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 2873 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 2874 if (count == 0 || !mr_list) 2875 return I40E_ERR_PARAM; 2876 } 2877 2878 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 2879 rule_type, dest_vsi, count, mr_list, 2880 cmd_details, rule_id, rules_used, rules_free); 2881 } 2882 2883 /** 2884 * i40e_aq_delete_mirrorrule - delete a mirror rule 2885 * @hw: pointer to the hw struct 2886 * @sw_seid: Switch SEID (to which rule refers) 2887 * @rule_type: Rule Type (ingress/egress/VLAN) 2888 * @count: length of the list 2889 * @rule_id: Rule ID that is returned in the receive desc as part of 2890 * add_mirrorrule. 2891 * @mr_list: list of mirrored VLAN IDs to be removed 2892 * @cmd_details: pointer to command details structure or NULL 2893 * @rules_used: Number of rules used in internal switch 2894 * @rules_free: Number of rules free in internal switch 2895 * 2896 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 2897 **/ 2898 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 2899 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 2900 struct i40e_asq_cmd_details *cmd_details, 2901 u16 *rules_used, u16 *rules_free) 2902 { 2903 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 2904 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 2905 /* count and mr_list shall be valid for rule_type INGRESS VLAN 2906 * mirroring. For other rule_type, count and rule_type should 2907 * not matter. 2908 */ 2909 if (count == 0 || !mr_list) 2910 return I40E_ERR_PARAM; 2911 } 2912 2913 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 2914 rule_type, rule_id, count, mr_list, 2915 cmd_details, NULL, rules_used, rules_free); 2916 } 2917 2918 /** 2919 * i40e_aq_send_msg_to_vf 2920 * @hw: pointer to the hardware structure 2921 * @vfid: VF id to send msg 2922 * @v_opcode: opcodes for VF-PF communication 2923 * @v_retval: return error code 2924 * @msg: pointer to the msg buffer 2925 * @msglen: msg length 2926 * @cmd_details: pointer to command details 2927 * 2928 * send msg to vf 2929 **/ 2930 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 2931 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 2932 struct i40e_asq_cmd_details *cmd_details) 2933 { 2934 struct i40e_aq_desc desc; 2935 struct i40e_aqc_pf_vf_message *cmd = 2936 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 2937 i40e_status status; 2938 2939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 2940 cmd->id = cpu_to_le32(vfid); 2941 desc.cookie_high = cpu_to_le32(v_opcode); 2942 desc.cookie_low = cpu_to_le32(v_retval); 2943 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 2944 if (msglen) { 2945 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2946 I40E_AQ_FLAG_RD)); 2947 if (msglen > I40E_AQ_LARGE_BUF) 2948 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2949 desc.datalen = cpu_to_le16(msglen); 2950 } 2951 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2952 2953 return status; 2954 } 2955 2956 /** 2957 * i40e_aq_debug_read_register 2958 * @hw: pointer to the hw struct 2959 * @reg_addr: register address 2960 * @reg_val: register value 2961 * @cmd_details: pointer to command details structure or NULL 2962 * 2963 * Read the register using the admin queue commands 2964 **/ 2965 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw, 2966 u32 reg_addr, u64 *reg_val, 2967 struct i40e_asq_cmd_details *cmd_details) 2968 { 2969 struct i40e_aq_desc desc; 2970 struct i40e_aqc_debug_reg_read_write *cmd_resp = 2971 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2972 i40e_status status; 2973 2974 if (reg_val == NULL) 2975 return I40E_ERR_PARAM; 2976 2977 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 2978 2979 cmd_resp->address = cpu_to_le32(reg_addr); 2980 2981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2982 2983 if (!status) { 2984 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | 2985 (u64)le32_to_cpu(cmd_resp->value_low); 2986 } 2987 2988 return status; 2989 } 2990 2991 /** 2992 * i40e_aq_debug_write_register 2993 * @hw: pointer to the hw struct 2994 * @reg_addr: register address 2995 * @reg_val: register value 2996 * @cmd_details: pointer to command details structure or NULL 2997 * 2998 * Write to a register using the admin queue commands 2999 **/ 3000 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 3001 u32 reg_addr, u64 reg_val, 3002 struct i40e_asq_cmd_details *cmd_details) 3003 { 3004 struct i40e_aq_desc desc; 3005 struct i40e_aqc_debug_reg_read_write *cmd = 3006 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3007 i40e_status status; 3008 3009 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3010 3011 cmd->address = cpu_to_le32(reg_addr); 3012 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 3013 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 3014 3015 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3016 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_aq_request_resource 3022 * @hw: pointer to the hw struct 3023 * @resource: resource id 3024 * @access: access type 3025 * @sdp_number: resource number 3026 * @timeout: the maximum time in ms that the driver may hold the resource 3027 * @cmd_details: pointer to command details structure or NULL 3028 * 3029 * requests common resource using the admin queue commands 3030 **/ 3031 i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 3032 enum i40e_aq_resources_ids resource, 3033 enum i40e_aq_resource_access_type access, 3034 u8 sdp_number, u64 *timeout, 3035 struct i40e_asq_cmd_details *cmd_details) 3036 { 3037 struct i40e_aq_desc desc; 3038 struct i40e_aqc_request_resource *cmd_resp = 3039 (struct i40e_aqc_request_resource *)&desc.params.raw; 3040 i40e_status status; 3041 3042 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3043 3044 cmd_resp->resource_id = cpu_to_le16(resource); 3045 cmd_resp->access_type = cpu_to_le16(access); 3046 cmd_resp->resource_number = cpu_to_le32(sdp_number); 3047 3048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3049 /* The completion specifies the maximum time in ms that the driver 3050 * may hold the resource in the Timeout field. 3051 * If the resource is held by someone else, the command completes with 3052 * busy return value and the timeout field indicates the maximum time 3053 * the current owner of the resource has to free it. 3054 */ 3055 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3056 *timeout = le32_to_cpu(cmd_resp->timeout); 3057 3058 return status; 3059 } 3060 3061 /** 3062 * i40e_aq_release_resource 3063 * @hw: pointer to the hw struct 3064 * @resource: resource id 3065 * @sdp_number: resource number 3066 * @cmd_details: pointer to command details structure or NULL 3067 * 3068 * release common resource using the admin queue commands 3069 **/ 3070 i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 3071 enum i40e_aq_resources_ids resource, 3072 u8 sdp_number, 3073 struct i40e_asq_cmd_details *cmd_details) 3074 { 3075 struct i40e_aq_desc desc; 3076 struct i40e_aqc_request_resource *cmd = 3077 (struct i40e_aqc_request_resource *)&desc.params.raw; 3078 i40e_status status; 3079 3080 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3081 3082 cmd->resource_id = cpu_to_le16(resource); 3083 cmd->resource_number = cpu_to_le32(sdp_number); 3084 3085 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3086 3087 return status; 3088 } 3089 3090 /** 3091 * i40e_aq_read_nvm 3092 * @hw: pointer to the hw struct 3093 * @module_pointer: module pointer location in words from the NVM beginning 3094 * @offset: byte offset from the module beginning 3095 * @length: length of the section to be read (in bytes from the offset) 3096 * @data: command buffer (size [bytes] = length) 3097 * @last_command: tells if this is the last command in a series 3098 * @cmd_details: pointer to command details structure or NULL 3099 * 3100 * Read the NVM using the admin queue commands 3101 **/ 3102 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3103 u32 offset, u16 length, void *data, 3104 bool last_command, 3105 struct i40e_asq_cmd_details *cmd_details) 3106 { 3107 struct i40e_aq_desc desc; 3108 struct i40e_aqc_nvm_update *cmd = 3109 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3110 i40e_status status; 3111 3112 /* In offset the highest byte must be zeroed. */ 3113 if (offset & 0xFF000000) { 3114 status = I40E_ERR_PARAM; 3115 goto i40e_aq_read_nvm_exit; 3116 } 3117 3118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3119 3120 /* If this is the last command in a series, set the proper flag. */ 3121 if (last_command) 3122 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3123 cmd->module_pointer = module_pointer; 3124 cmd->offset = cpu_to_le32(offset); 3125 cmd->length = cpu_to_le16(length); 3126 3127 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3128 if (length > I40E_AQ_LARGE_BUF) 3129 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3130 3131 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3132 3133 i40e_aq_read_nvm_exit: 3134 return status; 3135 } 3136 3137 /** 3138 * i40e_aq_erase_nvm 3139 * @hw: pointer to the hw struct 3140 * @module_pointer: module pointer location in words from the NVM beginning 3141 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3142 * @length: length of the section to be erased (expressed in 4 KB) 3143 * @last_command: tells if this is the last command in a series 3144 * @cmd_details: pointer to command details structure or NULL 3145 * 3146 * Erase the NVM sector using the admin queue commands 3147 **/ 3148 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3149 u32 offset, u16 length, bool last_command, 3150 struct i40e_asq_cmd_details *cmd_details) 3151 { 3152 struct i40e_aq_desc desc; 3153 struct i40e_aqc_nvm_update *cmd = 3154 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3155 i40e_status status; 3156 3157 /* In offset the highest byte must be zeroed. */ 3158 if (offset & 0xFF000000) { 3159 status = I40E_ERR_PARAM; 3160 goto i40e_aq_erase_nvm_exit; 3161 } 3162 3163 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3164 3165 /* If this is the last command in a series, set the proper flag. */ 3166 if (last_command) 3167 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3168 cmd->module_pointer = module_pointer; 3169 cmd->offset = cpu_to_le32(offset); 3170 cmd->length = cpu_to_le16(length); 3171 3172 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3173 3174 i40e_aq_erase_nvm_exit: 3175 return status; 3176 } 3177 3178 /** 3179 * i40e_parse_discover_capabilities 3180 * @hw: pointer to the hw struct 3181 * @buff: pointer to a buffer containing device/function capability records 3182 * @cap_count: number of capability records in the list 3183 * @list_type_opc: type of capabilities list to parse 3184 * 3185 * Parse the device/function capabilities list. 3186 **/ 3187 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3188 u32 cap_count, 3189 enum i40e_admin_queue_opc list_type_opc) 3190 { 3191 struct i40e_aqc_list_capabilities_element_resp *cap; 3192 u32 valid_functions, num_functions; 3193 u32 number, logical_id, phys_id; 3194 struct i40e_hw_capabilities *p; 3195 u16 id, ocp_cfg_word0; 3196 i40e_status status; 3197 u8 major_rev; 3198 u32 i = 0; 3199 3200 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3201 3202 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3203 p = &hw->dev_caps; 3204 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3205 p = &hw->func_caps; 3206 else 3207 return; 3208 3209 for (i = 0; i < cap_count; i++, cap++) { 3210 id = le16_to_cpu(cap->id); 3211 number = le32_to_cpu(cap->number); 3212 logical_id = le32_to_cpu(cap->logical_id); 3213 phys_id = le32_to_cpu(cap->phys_id); 3214 major_rev = cap->major_rev; 3215 3216 switch (id) { 3217 case I40E_AQ_CAP_ID_SWITCH_MODE: 3218 p->switch_mode = number; 3219 break; 3220 case I40E_AQ_CAP_ID_MNG_MODE: 3221 p->management_mode = number; 3222 if (major_rev > 1) { 3223 p->mng_protocols_over_mctp = logical_id; 3224 i40e_debug(hw, I40E_DEBUG_INIT, 3225 "HW Capability: Protocols over MCTP = %d\n", 3226 p->mng_protocols_over_mctp); 3227 } else { 3228 p->mng_protocols_over_mctp = 0; 3229 } 3230 break; 3231 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3232 p->npar_enable = number; 3233 break; 3234 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3235 p->os2bmc = number; 3236 break; 3237 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3238 p->valid_functions = number; 3239 break; 3240 case I40E_AQ_CAP_ID_SRIOV: 3241 if (number == 1) 3242 p->sr_iov_1_1 = true; 3243 break; 3244 case I40E_AQ_CAP_ID_VF: 3245 p->num_vfs = number; 3246 p->vf_base_id = logical_id; 3247 break; 3248 case I40E_AQ_CAP_ID_VMDQ: 3249 if (number == 1) 3250 p->vmdq = true; 3251 break; 3252 case I40E_AQ_CAP_ID_8021QBG: 3253 if (number == 1) 3254 p->evb_802_1_qbg = true; 3255 break; 3256 case I40E_AQ_CAP_ID_8021QBR: 3257 if (number == 1) 3258 p->evb_802_1_qbh = true; 3259 break; 3260 case I40E_AQ_CAP_ID_VSI: 3261 p->num_vsis = number; 3262 break; 3263 case I40E_AQ_CAP_ID_DCB: 3264 if (number == 1) { 3265 p->dcb = true; 3266 p->enabled_tcmap = logical_id; 3267 p->maxtc = phys_id; 3268 } 3269 break; 3270 case I40E_AQ_CAP_ID_FCOE: 3271 if (number == 1) 3272 p->fcoe = true; 3273 break; 3274 case I40E_AQ_CAP_ID_ISCSI: 3275 if (number == 1) 3276 p->iscsi = true; 3277 break; 3278 case I40E_AQ_CAP_ID_RSS: 3279 p->rss = true; 3280 p->rss_table_size = number; 3281 p->rss_table_entry_width = logical_id; 3282 break; 3283 case I40E_AQ_CAP_ID_RXQ: 3284 p->num_rx_qp = number; 3285 p->base_queue = phys_id; 3286 break; 3287 case I40E_AQ_CAP_ID_TXQ: 3288 p->num_tx_qp = number; 3289 p->base_queue = phys_id; 3290 break; 3291 case I40E_AQ_CAP_ID_MSIX: 3292 p->num_msix_vectors = number; 3293 i40e_debug(hw, I40E_DEBUG_INIT, 3294 "HW Capability: MSIX vector count = %d\n", 3295 p->num_msix_vectors); 3296 break; 3297 case I40E_AQ_CAP_ID_VF_MSIX: 3298 p->num_msix_vectors_vf = number; 3299 break; 3300 case I40E_AQ_CAP_ID_FLEX10: 3301 if (major_rev == 1) { 3302 if (number == 1) { 3303 p->flex10_enable = true; 3304 p->flex10_capable = true; 3305 } 3306 } else { 3307 /* Capability revision >= 2 */ 3308 if (number & 1) 3309 p->flex10_enable = true; 3310 if (number & 2) 3311 p->flex10_capable = true; 3312 } 3313 p->flex10_mode = logical_id; 3314 p->flex10_status = phys_id; 3315 break; 3316 case I40E_AQ_CAP_ID_CEM: 3317 if (number == 1) 3318 p->mgmt_cem = true; 3319 break; 3320 case I40E_AQ_CAP_ID_IWARP: 3321 if (number == 1) 3322 p->iwarp = true; 3323 break; 3324 case I40E_AQ_CAP_ID_LED: 3325 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3326 p->led[phys_id] = true; 3327 break; 3328 case I40E_AQ_CAP_ID_SDP: 3329 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3330 p->sdp[phys_id] = true; 3331 break; 3332 case I40E_AQ_CAP_ID_MDIO: 3333 if (number == 1) { 3334 p->mdio_port_num = phys_id; 3335 p->mdio_port_mode = logical_id; 3336 } 3337 break; 3338 case I40E_AQ_CAP_ID_1588: 3339 if (number == 1) 3340 p->ieee_1588 = true; 3341 break; 3342 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3343 p->fd = true; 3344 p->fd_filters_guaranteed = number; 3345 p->fd_filters_best_effort = logical_id; 3346 break; 3347 case I40E_AQ_CAP_ID_WSR_PROT: 3348 p->wr_csr_prot = (u64)number; 3349 p->wr_csr_prot |= (u64)logical_id << 32; 3350 break; 3351 case I40E_AQ_CAP_ID_NVM_MGMT: 3352 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3353 p->sec_rev_disabled = true; 3354 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3355 p->update_disabled = true; 3356 break; 3357 default: 3358 break; 3359 } 3360 } 3361 3362 if (p->fcoe) 3363 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3364 3365 /* Software override ensuring FCoE is disabled if npar or mfp 3366 * mode because it is not supported in these modes. 3367 */ 3368 if (p->npar_enable || p->flex10_enable) 3369 p->fcoe = false; 3370 3371 /* count the enabled ports (aka the "not disabled" ports) */ 3372 hw->num_ports = 0; 3373 for (i = 0; i < 4; i++) { 3374 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3375 u64 port_cfg = 0; 3376 3377 /* use AQ read to get the physical register offset instead 3378 * of the port relative offset 3379 */ 3380 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3381 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3382 hw->num_ports++; 3383 } 3384 3385 /* OCP cards case: if a mezz is removed the Ethernet port is at 3386 * disabled state in PRTGEN_CNF register. Additional NVM read is 3387 * needed in order to check if we are dealing with OCP card. 3388 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3389 * physical ports results in wrong partition id calculation and thus 3390 * not supporting WoL. 3391 */ 3392 if (hw->mac.type == I40E_MAC_X722) { 3393 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) { 3394 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3395 2 * I40E_SR_OCP_CFG_WORD0, 3396 sizeof(ocp_cfg_word0), 3397 &ocp_cfg_word0, true, NULL); 3398 if (!status && 3399 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3400 hw->num_ports = 4; 3401 i40e_release_nvm(hw); 3402 } 3403 } 3404 3405 valid_functions = p->valid_functions; 3406 num_functions = 0; 3407 while (valid_functions) { 3408 if (valid_functions & 1) 3409 num_functions++; 3410 valid_functions >>= 1; 3411 } 3412 3413 /* partition id is 1-based, and functions are evenly spread 3414 * across the ports as partitions 3415 */ 3416 if (hw->num_ports != 0) { 3417 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3418 hw->num_partitions = num_functions / hw->num_ports; 3419 } 3420 3421 /* additional HW specific goodies that might 3422 * someday be HW version specific 3423 */ 3424 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3425 } 3426 3427 /** 3428 * i40e_aq_discover_capabilities 3429 * @hw: pointer to the hw struct 3430 * @buff: a virtual buffer to hold the capabilities 3431 * @buff_size: Size of the virtual buffer 3432 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3433 * @list_type_opc: capabilities type to discover - pass in the command opcode 3434 * @cmd_details: pointer to command details structure or NULL 3435 * 3436 * Get the device capabilities descriptions from the firmware 3437 **/ 3438 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 3439 void *buff, u16 buff_size, u16 *data_size, 3440 enum i40e_admin_queue_opc list_type_opc, 3441 struct i40e_asq_cmd_details *cmd_details) 3442 { 3443 struct i40e_aqc_list_capabilites *cmd; 3444 struct i40e_aq_desc desc; 3445 i40e_status status = 0; 3446 3447 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3448 3449 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3450 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3451 status = I40E_ERR_PARAM; 3452 goto exit; 3453 } 3454 3455 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3456 3457 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3458 if (buff_size > I40E_AQ_LARGE_BUF) 3459 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3460 3461 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3462 *data_size = le16_to_cpu(desc.datalen); 3463 3464 if (status) 3465 goto exit; 3466 3467 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 3468 list_type_opc); 3469 3470 exit: 3471 return status; 3472 } 3473 3474 /** 3475 * i40e_aq_update_nvm 3476 * @hw: pointer to the hw struct 3477 * @module_pointer: module pointer location in words from the NVM beginning 3478 * @offset: byte offset from the module beginning 3479 * @length: length of the section to be written (in bytes from the offset) 3480 * @data: command buffer (size [bytes] = length) 3481 * @last_command: tells if this is the last command in a series 3482 * @preservation_flags: Preservation mode flags 3483 * @cmd_details: pointer to command details structure or NULL 3484 * 3485 * Update the NVM using the admin queue commands 3486 **/ 3487 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3488 u32 offset, u16 length, void *data, 3489 bool last_command, u8 preservation_flags, 3490 struct i40e_asq_cmd_details *cmd_details) 3491 { 3492 struct i40e_aq_desc desc; 3493 struct i40e_aqc_nvm_update *cmd = 3494 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3495 i40e_status status; 3496 3497 /* In offset the highest byte must be zeroed. */ 3498 if (offset & 0xFF000000) { 3499 status = I40E_ERR_PARAM; 3500 goto i40e_aq_update_nvm_exit; 3501 } 3502 3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3504 3505 /* If this is the last command in a series, set the proper flag. */ 3506 if (last_command) 3507 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3508 if (hw->mac.type == I40E_MAC_X722) { 3509 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 3510 cmd->command_flags |= 3511 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 3512 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3513 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 3514 cmd->command_flags |= 3515 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 3516 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 3517 } 3518 cmd->module_pointer = module_pointer; 3519 cmd->offset = cpu_to_le32(offset); 3520 cmd->length = cpu_to_le16(length); 3521 3522 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3523 if (length > I40E_AQ_LARGE_BUF) 3524 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3525 3526 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3527 3528 i40e_aq_update_nvm_exit: 3529 return status; 3530 } 3531 3532 /** 3533 * i40e_aq_rearrange_nvm 3534 * @hw: pointer to the hw struct 3535 * @rearrange_nvm: defines direction of rearrangement 3536 * @cmd_details: pointer to command details structure or NULL 3537 * 3538 * Rearrange NVM structure, available only for transition FW 3539 **/ 3540 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw, 3541 u8 rearrange_nvm, 3542 struct i40e_asq_cmd_details *cmd_details) 3543 { 3544 struct i40e_aqc_nvm_update *cmd; 3545 i40e_status status; 3546 struct i40e_aq_desc desc; 3547 3548 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw; 3549 3550 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3551 3552 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT | 3553 I40E_AQ_NVM_REARRANGE_TO_STRUCT); 3554 3555 if (!rearrange_nvm) { 3556 status = I40E_ERR_PARAM; 3557 goto i40e_aq_rearrange_nvm_exit; 3558 } 3559 3560 cmd->command_flags |= rearrange_nvm; 3561 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3562 3563 i40e_aq_rearrange_nvm_exit: 3564 return status; 3565 } 3566 3567 /** 3568 * i40e_aq_get_lldp_mib 3569 * @hw: pointer to the hw struct 3570 * @bridge_type: type of bridge requested 3571 * @mib_type: Local, Remote or both Local and Remote MIBs 3572 * @buff: pointer to a user supplied buffer to store the MIB block 3573 * @buff_size: size of the buffer (in bytes) 3574 * @local_len : length of the returned Local LLDP MIB 3575 * @remote_len: length of the returned Remote LLDP MIB 3576 * @cmd_details: pointer to command details structure or NULL 3577 * 3578 * Requests the complete LLDP MIB (entire packet). 3579 **/ 3580 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 3581 u8 mib_type, void *buff, u16 buff_size, 3582 u16 *local_len, u16 *remote_len, 3583 struct i40e_asq_cmd_details *cmd_details) 3584 { 3585 struct i40e_aq_desc desc; 3586 struct i40e_aqc_lldp_get_mib *cmd = 3587 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3588 struct i40e_aqc_lldp_get_mib *resp = 3589 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 3590 i40e_status status; 3591 3592 if (buff_size == 0 || !buff) 3593 return I40E_ERR_PARAM; 3594 3595 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 3596 /* Indirect Command */ 3597 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3598 3599 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 3600 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 3601 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 3602 3603 desc.datalen = cpu_to_le16(buff_size); 3604 3605 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3606 if (buff_size > I40E_AQ_LARGE_BUF) 3607 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3608 3609 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3610 if (!status) { 3611 if (local_len != NULL) 3612 *local_len = le16_to_cpu(resp->local_len); 3613 if (remote_len != NULL) 3614 *remote_len = le16_to_cpu(resp->remote_len); 3615 } 3616 3617 return status; 3618 } 3619 3620 /** 3621 * i40e_aq_cfg_lldp_mib_change_event 3622 * @hw: pointer to the hw struct 3623 * @enable_update: Enable or Disable event posting 3624 * @cmd_details: pointer to command details structure or NULL 3625 * 3626 * Enable or Disable posting of an event on ARQ when LLDP MIB 3627 * associated with the interface changes 3628 **/ 3629 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 3630 bool enable_update, 3631 struct i40e_asq_cmd_details *cmd_details) 3632 { 3633 struct i40e_aq_desc desc; 3634 struct i40e_aqc_lldp_update_mib *cmd = 3635 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 3636 i40e_status status; 3637 3638 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 3639 3640 if (!enable_update) 3641 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 3642 3643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3644 3645 return status; 3646 } 3647 3648 /** 3649 * i40e_aq_restore_lldp 3650 * @hw: pointer to the hw struct 3651 * @setting: pointer to factory setting variable or NULL 3652 * @restore: True if factory settings should be restored 3653 * @cmd_details: pointer to command details structure or NULL 3654 * 3655 * Restore LLDP Agent factory settings if @restore set to True. In other case 3656 * only returns factory setting in AQ response. 3657 **/ 3658 enum i40e_status_code 3659 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore, 3660 struct i40e_asq_cmd_details *cmd_details) 3661 { 3662 struct i40e_aq_desc desc; 3663 struct i40e_aqc_lldp_restore *cmd = 3664 (struct i40e_aqc_lldp_restore *)&desc.params.raw; 3665 i40e_status status; 3666 3667 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) { 3668 i40e_debug(hw, I40E_DEBUG_ALL, 3669 "Restore LLDP not supported by current FW version.\n"); 3670 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3671 } 3672 3673 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore); 3674 3675 if (restore) 3676 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE; 3677 3678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3679 3680 if (setting) 3681 *setting = cmd->command & 1; 3682 3683 return status; 3684 } 3685 3686 /** 3687 * i40e_aq_stop_lldp 3688 * @hw: pointer to the hw struct 3689 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 3690 * @persist: True if stop of LLDP should be persistent across power cycles 3691 * @cmd_details: pointer to command details structure or NULL 3692 * 3693 * Stop or Shutdown the embedded LLDP Agent 3694 **/ 3695 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 3696 bool persist, 3697 struct i40e_asq_cmd_details *cmd_details) 3698 { 3699 struct i40e_aq_desc desc; 3700 struct i40e_aqc_lldp_stop *cmd = 3701 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 3702 i40e_status status; 3703 3704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 3705 3706 if (shutdown_agent) 3707 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 3708 3709 if (persist) { 3710 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3711 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST; 3712 else 3713 i40e_debug(hw, I40E_DEBUG_ALL, 3714 "Persistent Stop LLDP not supported by current FW version.\n"); 3715 } 3716 3717 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3718 3719 return status; 3720 } 3721 3722 /** 3723 * i40e_aq_start_lldp 3724 * @hw: pointer to the hw struct 3725 * @buff: buffer for result 3726 * @persist: True if start of LLDP should be persistent across power cycles 3727 * @buff_size: buffer size 3728 * @cmd_details: pointer to command details structure or NULL 3729 * 3730 * Start the embedded LLDP Agent on all ports. 3731 **/ 3732 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist, 3733 struct i40e_asq_cmd_details *cmd_details) 3734 { 3735 struct i40e_aq_desc desc; 3736 struct i40e_aqc_lldp_start *cmd = 3737 (struct i40e_aqc_lldp_start *)&desc.params.raw; 3738 i40e_status status; 3739 3740 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 3741 3742 cmd->command = I40E_AQ_LLDP_AGENT_START; 3743 3744 if (persist) { 3745 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) 3746 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST; 3747 else 3748 i40e_debug(hw, I40E_DEBUG_ALL, 3749 "Persistent Start LLDP not supported by current FW version.\n"); 3750 } 3751 3752 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3753 3754 return status; 3755 } 3756 3757 /** 3758 * i40e_aq_set_dcb_parameters 3759 * @hw: pointer to the hw struct 3760 * @cmd_details: pointer to command details structure or NULL 3761 * @dcb_enable: True if DCB configuration needs to be applied 3762 * 3763 **/ 3764 enum i40e_status_code 3765 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 3766 struct i40e_asq_cmd_details *cmd_details) 3767 { 3768 struct i40e_aq_desc desc; 3769 struct i40e_aqc_set_dcb_parameters *cmd = 3770 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 3771 i40e_status status; 3772 3773 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) 3774 return I40E_ERR_DEVICE_NOT_SUPPORTED; 3775 3776 i40e_fill_default_direct_cmd_desc(&desc, 3777 i40e_aqc_opc_set_dcb_parameters); 3778 3779 if (dcb_enable) { 3780 cmd->valid_flags = I40E_DCB_VALID; 3781 cmd->command = I40E_AQ_DCB_SET_AGENT; 3782 } 3783 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3784 3785 return status; 3786 } 3787 3788 /** 3789 * i40e_aq_get_cee_dcb_config 3790 * @hw: pointer to the hw struct 3791 * @buff: response buffer that stores CEE operational configuration 3792 * @buff_size: size of the buffer passed 3793 * @cmd_details: pointer to command details structure or NULL 3794 * 3795 * Get CEE DCBX mode operational configuration from firmware 3796 **/ 3797 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 3798 void *buff, u16 buff_size, 3799 struct i40e_asq_cmd_details *cmd_details) 3800 { 3801 struct i40e_aq_desc desc; 3802 i40e_status status; 3803 3804 if (buff_size == 0 || !buff) 3805 return I40E_ERR_PARAM; 3806 3807 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 3808 3809 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3810 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 3811 cmd_details); 3812 3813 return status; 3814 } 3815 3816 /** 3817 * i40e_aq_add_udp_tunnel 3818 * @hw: pointer to the hw struct 3819 * @udp_port: the UDP port to add in Host byte order 3820 * @protocol_index: protocol index type 3821 * @filter_index: pointer to filter index 3822 * @cmd_details: pointer to command details structure or NULL 3823 * 3824 * Note: Firmware expects the udp_port value to be in Little Endian format, 3825 * and this function will call cpu_to_le16 to convert from Host byte order to 3826 * Little Endian order. 3827 **/ 3828 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 3829 u16 udp_port, u8 protocol_index, 3830 u8 *filter_index, 3831 struct i40e_asq_cmd_details *cmd_details) 3832 { 3833 struct i40e_aq_desc desc; 3834 struct i40e_aqc_add_udp_tunnel *cmd = 3835 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 3836 struct i40e_aqc_del_udp_tunnel_completion *resp = 3837 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 3838 i40e_status status; 3839 3840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 3841 3842 cmd->udp_port = cpu_to_le16(udp_port); 3843 cmd->protocol_type = protocol_index; 3844 3845 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3846 3847 if (!status && filter_index) 3848 *filter_index = resp->index; 3849 3850 return status; 3851 } 3852 3853 /** 3854 * i40e_aq_del_udp_tunnel 3855 * @hw: pointer to the hw struct 3856 * @index: filter index 3857 * @cmd_details: pointer to command details structure or NULL 3858 **/ 3859 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 3860 struct i40e_asq_cmd_details *cmd_details) 3861 { 3862 struct i40e_aq_desc desc; 3863 struct i40e_aqc_remove_udp_tunnel *cmd = 3864 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 3865 i40e_status status; 3866 3867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 3868 3869 cmd->index = index; 3870 3871 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3872 3873 return status; 3874 } 3875 3876 /** 3877 * i40e_aq_delete_element - Delete switch element 3878 * @hw: pointer to the hw struct 3879 * @seid: the SEID to delete from the switch 3880 * @cmd_details: pointer to command details structure or NULL 3881 * 3882 * This deletes a switch element from the switch. 3883 **/ 3884 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 3885 struct i40e_asq_cmd_details *cmd_details) 3886 { 3887 struct i40e_aq_desc desc; 3888 struct i40e_aqc_switch_seid *cmd = 3889 (struct i40e_aqc_switch_seid *)&desc.params.raw; 3890 i40e_status status; 3891 3892 if (seid == 0) 3893 return I40E_ERR_PARAM; 3894 3895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 3896 3897 cmd->seid = cpu_to_le16(seid); 3898 3899 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3900 3901 return status; 3902 } 3903 3904 /** 3905 * i40e_aq_dcb_updated - DCB Updated Command 3906 * @hw: pointer to the hw struct 3907 * @cmd_details: pointer to command details structure or NULL 3908 * 3909 * EMP will return when the shared RPB settings have been 3910 * recomputed and modified. The retval field in the descriptor 3911 * will be set to 0 when RPB is modified. 3912 **/ 3913 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 3914 struct i40e_asq_cmd_details *cmd_details) 3915 { 3916 struct i40e_aq_desc desc; 3917 i40e_status status; 3918 3919 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 3920 3921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3922 3923 return status; 3924 } 3925 3926 /** 3927 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 3928 * @hw: pointer to the hw struct 3929 * @seid: seid for the physical port/switching component/vsi 3930 * @buff: Indirect buffer to hold data parameters and response 3931 * @buff_size: Indirect buffer size 3932 * @opcode: Tx scheduler AQ command opcode 3933 * @cmd_details: pointer to command details structure or NULL 3934 * 3935 * Generic command handler for Tx scheduler AQ commands 3936 **/ 3937 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 3938 void *buff, u16 buff_size, 3939 enum i40e_admin_queue_opc opcode, 3940 struct i40e_asq_cmd_details *cmd_details) 3941 { 3942 struct i40e_aq_desc desc; 3943 struct i40e_aqc_tx_sched_ind *cmd = 3944 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 3945 i40e_status status; 3946 bool cmd_param_flag = false; 3947 3948 switch (opcode) { 3949 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 3950 case i40e_aqc_opc_configure_vsi_tc_bw: 3951 case i40e_aqc_opc_enable_switching_comp_ets: 3952 case i40e_aqc_opc_modify_switching_comp_ets: 3953 case i40e_aqc_opc_disable_switching_comp_ets: 3954 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 3955 case i40e_aqc_opc_configure_switching_comp_bw_config: 3956 cmd_param_flag = true; 3957 break; 3958 case i40e_aqc_opc_query_vsi_bw_config: 3959 case i40e_aqc_opc_query_vsi_ets_sla_config: 3960 case i40e_aqc_opc_query_switching_comp_ets_config: 3961 case i40e_aqc_opc_query_port_ets_config: 3962 case i40e_aqc_opc_query_switching_comp_bw_config: 3963 cmd_param_flag = false; 3964 break; 3965 default: 3966 return I40E_ERR_PARAM; 3967 } 3968 3969 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3970 3971 /* Indirect command */ 3972 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 3973 if (cmd_param_flag) 3974 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 3975 if (buff_size > I40E_AQ_LARGE_BUF) 3976 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 3977 3978 desc.datalen = cpu_to_le16(buff_size); 3979 3980 cmd->vsi_seid = cpu_to_le16(seid); 3981 3982 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3983 3984 return status; 3985 } 3986 3987 /** 3988 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 3989 * @hw: pointer to the hw struct 3990 * @seid: VSI seid 3991 * @credit: BW limit credits (0 = disabled) 3992 * @max_credit: Max BW limit credits 3993 * @cmd_details: pointer to command details structure or NULL 3994 **/ 3995 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 3996 u16 seid, u16 credit, u8 max_credit, 3997 struct i40e_asq_cmd_details *cmd_details) 3998 { 3999 struct i40e_aq_desc desc; 4000 struct i40e_aqc_configure_vsi_bw_limit *cmd = 4001 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 4002 i40e_status status; 4003 4004 i40e_fill_default_direct_cmd_desc(&desc, 4005 i40e_aqc_opc_configure_vsi_bw_limit); 4006 4007 cmd->vsi_seid = cpu_to_le16(seid); 4008 cmd->credit = cpu_to_le16(credit); 4009 cmd->max_credit = max_credit; 4010 4011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4012 4013 return status; 4014 } 4015 4016 /** 4017 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 4018 * @hw: pointer to the hw struct 4019 * @seid: VSI seid 4020 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 4021 * @cmd_details: pointer to command details structure or NULL 4022 **/ 4023 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 4024 u16 seid, 4025 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 4026 struct i40e_asq_cmd_details *cmd_details) 4027 { 4028 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4029 i40e_aqc_opc_configure_vsi_tc_bw, 4030 cmd_details); 4031 } 4032 4033 /** 4034 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 4035 * @hw: pointer to the hw struct 4036 * @seid: seid of the switching component connected to Physical Port 4037 * @ets_data: Buffer holding ETS parameters 4038 * @opcode: Tx scheduler AQ command opcode 4039 * @cmd_details: pointer to command details structure or NULL 4040 **/ 4041 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 4042 u16 seid, 4043 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 4044 enum i40e_admin_queue_opc opcode, 4045 struct i40e_asq_cmd_details *cmd_details) 4046 { 4047 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 4048 sizeof(*ets_data), opcode, cmd_details); 4049 } 4050 4051 /** 4052 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 4053 * @hw: pointer to the hw struct 4054 * @seid: seid of the switching component 4055 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 4056 * @cmd_details: pointer to command details structure or NULL 4057 **/ 4058 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 4059 u16 seid, 4060 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 4061 struct i40e_asq_cmd_details *cmd_details) 4062 { 4063 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4064 i40e_aqc_opc_configure_switching_comp_bw_config, 4065 cmd_details); 4066 } 4067 4068 /** 4069 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 4070 * @hw: pointer to the hw struct 4071 * @seid: seid of the VSI 4072 * @bw_data: Buffer to hold VSI BW configuration 4073 * @cmd_details: pointer to command details structure or NULL 4074 **/ 4075 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 4076 u16 seid, 4077 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 4078 struct i40e_asq_cmd_details *cmd_details) 4079 { 4080 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4081 i40e_aqc_opc_query_vsi_bw_config, 4082 cmd_details); 4083 } 4084 4085 /** 4086 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 4087 * @hw: pointer to the hw struct 4088 * @seid: seid of the VSI 4089 * @bw_data: Buffer to hold VSI BW configuration per TC 4090 * @cmd_details: pointer to command details structure or NULL 4091 **/ 4092 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 4093 u16 seid, 4094 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 4095 struct i40e_asq_cmd_details *cmd_details) 4096 { 4097 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4098 i40e_aqc_opc_query_vsi_ets_sla_config, 4099 cmd_details); 4100 } 4101 4102 /** 4103 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 4104 * @hw: pointer to the hw struct 4105 * @seid: seid of the switching component 4106 * @bw_data: Buffer to hold switching component's per TC BW config 4107 * @cmd_details: pointer to command details structure or NULL 4108 **/ 4109 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 4110 u16 seid, 4111 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 4112 struct i40e_asq_cmd_details *cmd_details) 4113 { 4114 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4115 i40e_aqc_opc_query_switching_comp_ets_config, 4116 cmd_details); 4117 } 4118 4119 /** 4120 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 4121 * @hw: pointer to the hw struct 4122 * @seid: seid of the VSI or switching component connected to Physical Port 4123 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 4124 * @cmd_details: pointer to command details structure or NULL 4125 **/ 4126 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 4127 u16 seid, 4128 struct i40e_aqc_query_port_ets_config_resp *bw_data, 4129 struct i40e_asq_cmd_details *cmd_details) 4130 { 4131 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4132 i40e_aqc_opc_query_port_ets_config, 4133 cmd_details); 4134 } 4135 4136 /** 4137 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 4138 * @hw: pointer to the hw struct 4139 * @seid: seid of the switching component 4140 * @bw_data: Buffer to hold switching component's BW configuration 4141 * @cmd_details: pointer to command details structure or NULL 4142 **/ 4143 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 4144 u16 seid, 4145 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 4146 struct i40e_asq_cmd_details *cmd_details) 4147 { 4148 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 4149 i40e_aqc_opc_query_switching_comp_bw_config, 4150 cmd_details); 4151 } 4152 4153 /** 4154 * i40e_validate_filter_settings 4155 * @hw: pointer to the hardware structure 4156 * @settings: Filter control settings 4157 * 4158 * Check and validate the filter control settings passed. 4159 * The function checks for the valid filter/context sizes being 4160 * passed for FCoE and PE. 4161 * 4162 * Returns 0 if the values passed are valid and within 4163 * range else returns an error. 4164 **/ 4165 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 4166 struct i40e_filter_control_settings *settings) 4167 { 4168 u32 fcoe_cntx_size, fcoe_filt_size; 4169 u32 pe_cntx_size, pe_filt_size; 4170 u32 fcoe_fmax; 4171 u32 val; 4172 4173 /* Validate FCoE settings passed */ 4174 switch (settings->fcoe_filt_num) { 4175 case I40E_HASH_FILTER_SIZE_1K: 4176 case I40E_HASH_FILTER_SIZE_2K: 4177 case I40E_HASH_FILTER_SIZE_4K: 4178 case I40E_HASH_FILTER_SIZE_8K: 4179 case I40E_HASH_FILTER_SIZE_16K: 4180 case I40E_HASH_FILTER_SIZE_32K: 4181 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4182 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 4183 break; 4184 default: 4185 return I40E_ERR_PARAM; 4186 } 4187 4188 switch (settings->fcoe_cntx_num) { 4189 case I40E_DMA_CNTX_SIZE_512: 4190 case I40E_DMA_CNTX_SIZE_1K: 4191 case I40E_DMA_CNTX_SIZE_2K: 4192 case I40E_DMA_CNTX_SIZE_4K: 4193 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4194 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 4195 break; 4196 default: 4197 return I40E_ERR_PARAM; 4198 } 4199 4200 /* Validate PE settings passed */ 4201 switch (settings->pe_filt_num) { 4202 case I40E_HASH_FILTER_SIZE_1K: 4203 case I40E_HASH_FILTER_SIZE_2K: 4204 case I40E_HASH_FILTER_SIZE_4K: 4205 case I40E_HASH_FILTER_SIZE_8K: 4206 case I40E_HASH_FILTER_SIZE_16K: 4207 case I40E_HASH_FILTER_SIZE_32K: 4208 case I40E_HASH_FILTER_SIZE_64K: 4209 case I40E_HASH_FILTER_SIZE_128K: 4210 case I40E_HASH_FILTER_SIZE_256K: 4211 case I40E_HASH_FILTER_SIZE_512K: 4212 case I40E_HASH_FILTER_SIZE_1M: 4213 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 4214 pe_filt_size <<= (u32)settings->pe_filt_num; 4215 break; 4216 default: 4217 return I40E_ERR_PARAM; 4218 } 4219 4220 switch (settings->pe_cntx_num) { 4221 case I40E_DMA_CNTX_SIZE_512: 4222 case I40E_DMA_CNTX_SIZE_1K: 4223 case I40E_DMA_CNTX_SIZE_2K: 4224 case I40E_DMA_CNTX_SIZE_4K: 4225 case I40E_DMA_CNTX_SIZE_8K: 4226 case I40E_DMA_CNTX_SIZE_16K: 4227 case I40E_DMA_CNTX_SIZE_32K: 4228 case I40E_DMA_CNTX_SIZE_64K: 4229 case I40E_DMA_CNTX_SIZE_128K: 4230 case I40E_DMA_CNTX_SIZE_256K: 4231 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 4232 pe_cntx_size <<= (u32)settings->pe_cntx_num; 4233 break; 4234 default: 4235 return I40E_ERR_PARAM; 4236 } 4237 4238 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 4239 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 4240 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 4241 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 4242 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 4243 return I40E_ERR_INVALID_SIZE; 4244 4245 return 0; 4246 } 4247 4248 /** 4249 * i40e_set_filter_control 4250 * @hw: pointer to the hardware structure 4251 * @settings: Filter control settings 4252 * 4253 * Set the Queue Filters for PE/FCoE and enable filters required 4254 * for a single PF. It is expected that these settings are programmed 4255 * at the driver initialization time. 4256 **/ 4257 i40e_status i40e_set_filter_control(struct i40e_hw *hw, 4258 struct i40e_filter_control_settings *settings) 4259 { 4260 i40e_status ret = 0; 4261 u32 hash_lut_size = 0; 4262 u32 val; 4263 4264 if (!settings) 4265 return I40E_ERR_PARAM; 4266 4267 /* Validate the input settings */ 4268 ret = i40e_validate_filter_settings(hw, settings); 4269 if (ret) 4270 return ret; 4271 4272 /* Read the PF Queue Filter control register */ 4273 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 4274 4275 /* Program required PE hash buckets for the PF */ 4276 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 4277 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 4278 I40E_PFQF_CTL_0_PEHSIZE_MASK; 4279 /* Program required PE contexts for the PF */ 4280 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 4281 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 4282 I40E_PFQF_CTL_0_PEDSIZE_MASK; 4283 4284 /* Program required FCoE hash buckets for the PF */ 4285 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4286 val |= ((u32)settings->fcoe_filt_num << 4287 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 4288 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 4289 /* Program required FCoE DDP contexts for the PF */ 4290 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4291 val |= ((u32)settings->fcoe_cntx_num << 4292 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 4293 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 4294 4295 /* Program Hash LUT size for the PF */ 4296 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4297 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 4298 hash_lut_size = 1; 4299 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 4300 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 4301 4302 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 4303 if (settings->enable_fdir) 4304 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 4305 if (settings->enable_ethtype) 4306 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 4307 if (settings->enable_macvlan) 4308 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 4309 4310 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 4311 4312 return 0; 4313 } 4314 4315 /** 4316 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 4317 * @hw: pointer to the hw struct 4318 * @mac_addr: MAC address to use in the filter 4319 * @ethtype: Ethertype to use in the filter 4320 * @flags: Flags that needs to be applied to the filter 4321 * @vsi_seid: seid of the control VSI 4322 * @queue: VSI queue number to send the packet to 4323 * @is_add: Add control packet filter if True else remove 4324 * @stats: Structure to hold information on control filter counts 4325 * @cmd_details: pointer to command details structure or NULL 4326 * 4327 * This command will Add or Remove control packet filter for a control VSI. 4328 * In return it will update the total number of perfect filter count in 4329 * the stats member. 4330 **/ 4331 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 4332 u8 *mac_addr, u16 ethtype, u16 flags, 4333 u16 vsi_seid, u16 queue, bool is_add, 4334 struct i40e_control_filter_stats *stats, 4335 struct i40e_asq_cmd_details *cmd_details) 4336 { 4337 struct i40e_aq_desc desc; 4338 struct i40e_aqc_add_remove_control_packet_filter *cmd = 4339 (struct i40e_aqc_add_remove_control_packet_filter *) 4340 &desc.params.raw; 4341 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 4342 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 4343 &desc.params.raw; 4344 i40e_status status; 4345 4346 if (vsi_seid == 0) 4347 return I40E_ERR_PARAM; 4348 4349 if (is_add) { 4350 i40e_fill_default_direct_cmd_desc(&desc, 4351 i40e_aqc_opc_add_control_packet_filter); 4352 cmd->queue = cpu_to_le16(queue); 4353 } else { 4354 i40e_fill_default_direct_cmd_desc(&desc, 4355 i40e_aqc_opc_remove_control_packet_filter); 4356 } 4357 4358 if (mac_addr) 4359 ether_addr_copy(cmd->mac, mac_addr); 4360 4361 cmd->etype = cpu_to_le16(ethtype); 4362 cmd->flags = cpu_to_le16(flags); 4363 cmd->seid = cpu_to_le16(vsi_seid); 4364 4365 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4366 4367 if (!status && stats) { 4368 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 4369 stats->etype_used = le16_to_cpu(resp->etype_used); 4370 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 4371 stats->etype_free = le16_to_cpu(resp->etype_free); 4372 } 4373 4374 return status; 4375 } 4376 4377 /** 4378 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 4379 * @hw: pointer to the hw struct 4380 * @seid: VSI seid to add ethertype filter from 4381 **/ 4382 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 4383 u16 seid) 4384 { 4385 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 4386 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 4387 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 4388 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 4389 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 4390 i40e_status status; 4391 4392 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 4393 seid, 0, true, NULL, 4394 NULL); 4395 if (status) 4396 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 4397 } 4398 4399 /** 4400 * i40e_aq_alternate_read 4401 * @hw: pointer to the hardware structure 4402 * @reg_addr0: address of first dword to be read 4403 * @reg_val0: pointer for data read from 'reg_addr0' 4404 * @reg_addr1: address of second dword to be read 4405 * @reg_val1: pointer for data read from 'reg_addr1' 4406 * 4407 * Read one or two dwords from alternate structure. Fields are indicated 4408 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 4409 * is not passed then only register at 'reg_addr0' is read. 4410 * 4411 **/ 4412 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw, 4413 u32 reg_addr0, u32 *reg_val0, 4414 u32 reg_addr1, u32 *reg_val1) 4415 { 4416 struct i40e_aq_desc desc; 4417 struct i40e_aqc_alternate_write *cmd_resp = 4418 (struct i40e_aqc_alternate_write *)&desc.params.raw; 4419 i40e_status status; 4420 4421 if (!reg_val0) 4422 return I40E_ERR_PARAM; 4423 4424 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 4425 cmd_resp->address0 = cpu_to_le32(reg_addr0); 4426 cmd_resp->address1 = cpu_to_le32(reg_addr1); 4427 4428 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4429 4430 if (!status) { 4431 *reg_val0 = le32_to_cpu(cmd_resp->data0); 4432 4433 if (reg_val1) 4434 *reg_val1 = le32_to_cpu(cmd_resp->data1); 4435 } 4436 4437 return status; 4438 } 4439 4440 /** 4441 * i40e_aq_resume_port_tx 4442 * @hw: pointer to the hardware structure 4443 * @cmd_details: pointer to command details structure or NULL 4444 * 4445 * Resume port's Tx traffic 4446 **/ 4447 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw, 4448 struct i40e_asq_cmd_details *cmd_details) 4449 { 4450 struct i40e_aq_desc desc; 4451 i40e_status status; 4452 4453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 4454 4455 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4456 4457 return status; 4458 } 4459 4460 /** 4461 * i40e_set_pci_config_data - store PCI bus info 4462 * @hw: pointer to hardware structure 4463 * @link_status: the link status word from PCI config space 4464 * 4465 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 4466 **/ 4467 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 4468 { 4469 hw->bus.type = i40e_bus_type_pci_express; 4470 4471 switch (link_status & PCI_EXP_LNKSTA_NLW) { 4472 case PCI_EXP_LNKSTA_NLW_X1: 4473 hw->bus.width = i40e_bus_width_pcie_x1; 4474 break; 4475 case PCI_EXP_LNKSTA_NLW_X2: 4476 hw->bus.width = i40e_bus_width_pcie_x2; 4477 break; 4478 case PCI_EXP_LNKSTA_NLW_X4: 4479 hw->bus.width = i40e_bus_width_pcie_x4; 4480 break; 4481 case PCI_EXP_LNKSTA_NLW_X8: 4482 hw->bus.width = i40e_bus_width_pcie_x8; 4483 break; 4484 default: 4485 hw->bus.width = i40e_bus_width_unknown; 4486 break; 4487 } 4488 4489 switch (link_status & PCI_EXP_LNKSTA_CLS) { 4490 case PCI_EXP_LNKSTA_CLS_2_5GB: 4491 hw->bus.speed = i40e_bus_speed_2500; 4492 break; 4493 case PCI_EXP_LNKSTA_CLS_5_0GB: 4494 hw->bus.speed = i40e_bus_speed_5000; 4495 break; 4496 case PCI_EXP_LNKSTA_CLS_8_0GB: 4497 hw->bus.speed = i40e_bus_speed_8000; 4498 break; 4499 default: 4500 hw->bus.speed = i40e_bus_speed_unknown; 4501 break; 4502 } 4503 } 4504 4505 /** 4506 * i40e_aq_debug_dump 4507 * @hw: pointer to the hardware structure 4508 * @cluster_id: specific cluster to dump 4509 * @table_id: table id within cluster 4510 * @start_index: index of line in the block to read 4511 * @buff_size: dump buffer size 4512 * @buff: dump buffer 4513 * @ret_buff_size: actual buffer size returned 4514 * @ret_next_table: next block to read 4515 * @ret_next_index: next index to read 4516 * @cmd_details: pointer to command details structure or NULL 4517 * 4518 * Dump internal FW/HW data for debug purposes. 4519 * 4520 **/ 4521 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 4522 u8 table_id, u32 start_index, u16 buff_size, 4523 void *buff, u16 *ret_buff_size, 4524 u8 *ret_next_table, u32 *ret_next_index, 4525 struct i40e_asq_cmd_details *cmd_details) 4526 { 4527 struct i40e_aq_desc desc; 4528 struct i40e_aqc_debug_dump_internals *cmd = 4529 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4530 struct i40e_aqc_debug_dump_internals *resp = 4531 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 4532 i40e_status status; 4533 4534 if (buff_size == 0 || !buff) 4535 return I40E_ERR_PARAM; 4536 4537 i40e_fill_default_direct_cmd_desc(&desc, 4538 i40e_aqc_opc_debug_dump_internals); 4539 /* Indirect Command */ 4540 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4541 if (buff_size > I40E_AQ_LARGE_BUF) 4542 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4543 4544 cmd->cluster_id = cluster_id; 4545 cmd->table_id = table_id; 4546 cmd->idx = cpu_to_le32(start_index); 4547 4548 desc.datalen = cpu_to_le16(buff_size); 4549 4550 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4551 if (!status) { 4552 if (ret_buff_size) 4553 *ret_buff_size = le16_to_cpu(desc.datalen); 4554 if (ret_next_table) 4555 *ret_next_table = resp->table_id; 4556 if (ret_next_index) 4557 *ret_next_index = le32_to_cpu(resp->idx); 4558 } 4559 4560 return status; 4561 } 4562 4563 /** 4564 * i40e_read_bw_from_alt_ram 4565 * @hw: pointer to the hardware structure 4566 * @max_bw: pointer for max_bw read 4567 * @min_bw: pointer for min_bw read 4568 * @min_valid: pointer for bool that is true if min_bw is a valid value 4569 * @max_valid: pointer for bool that is true if max_bw is a valid value 4570 * 4571 * Read bw from the alternate ram for the given pf 4572 **/ 4573 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 4574 u32 *max_bw, u32 *min_bw, 4575 bool *min_valid, bool *max_valid) 4576 { 4577 i40e_status status; 4578 u32 max_bw_addr, min_bw_addr; 4579 4580 /* Calculate the address of the min/max bw registers */ 4581 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4582 I40E_ALT_STRUCT_MAX_BW_OFFSET + 4583 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4584 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 4585 I40E_ALT_STRUCT_MIN_BW_OFFSET + 4586 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 4587 4588 /* Read the bandwidths from alt ram */ 4589 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 4590 min_bw_addr, min_bw); 4591 4592 if (*min_bw & I40E_ALT_BW_VALID_MASK) 4593 *min_valid = true; 4594 else 4595 *min_valid = false; 4596 4597 if (*max_bw & I40E_ALT_BW_VALID_MASK) 4598 *max_valid = true; 4599 else 4600 *max_valid = false; 4601 4602 return status; 4603 } 4604 4605 /** 4606 * i40e_aq_configure_partition_bw 4607 * @hw: pointer to the hardware structure 4608 * @bw_data: Buffer holding valid pfs and bw limits 4609 * @cmd_details: pointer to command details 4610 * 4611 * Configure partitions guaranteed/max bw 4612 **/ 4613 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw, 4614 struct i40e_aqc_configure_partition_bw_data *bw_data, 4615 struct i40e_asq_cmd_details *cmd_details) 4616 { 4617 i40e_status status; 4618 struct i40e_aq_desc desc; 4619 u16 bwd_size = sizeof(*bw_data); 4620 4621 i40e_fill_default_direct_cmd_desc(&desc, 4622 i40e_aqc_opc_configure_partition_bw); 4623 4624 /* Indirect command */ 4625 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 4626 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 4627 4628 if (bwd_size > I40E_AQ_LARGE_BUF) 4629 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 4630 4631 desc.datalen = cpu_to_le16(bwd_size); 4632 4633 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, 4634 cmd_details); 4635 4636 return status; 4637 } 4638 4639 /** 4640 * i40e_read_phy_register_clause22 4641 * @hw: pointer to the HW structure 4642 * @reg: register address in the page 4643 * @phy_addr: PHY address on MDIO interface 4644 * @value: PHY register value 4645 * 4646 * Reads specified PHY register value 4647 **/ 4648 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw, 4649 u16 reg, u8 phy_addr, u16 *value) 4650 { 4651 i40e_status status = I40E_ERR_TIMEOUT; 4652 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4653 u32 command = 0; 4654 u16 retry = 1000; 4655 4656 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4657 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4658 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 4659 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4660 (I40E_GLGEN_MSCA_MDICMD_MASK); 4661 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4662 do { 4663 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4664 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4665 status = 0; 4666 break; 4667 } 4668 udelay(10); 4669 retry--; 4670 } while (retry); 4671 4672 if (status) { 4673 i40e_debug(hw, I40E_DEBUG_PHY, 4674 "PHY: Can't write command to external PHY.\n"); 4675 } else { 4676 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4677 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4678 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4679 } 4680 4681 return status; 4682 } 4683 4684 /** 4685 * i40e_write_phy_register_clause22 4686 * @hw: pointer to the HW structure 4687 * @reg: register address in the page 4688 * @phy_addr: PHY address on MDIO interface 4689 * @value: PHY register value 4690 * 4691 * Writes specified PHY register value 4692 **/ 4693 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw, 4694 u16 reg, u8 phy_addr, u16 value) 4695 { 4696 i40e_status status = I40E_ERR_TIMEOUT; 4697 u8 port_num = (u8)hw->func_caps.mdio_port_num; 4698 u32 command = 0; 4699 u16 retry = 1000; 4700 4701 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4702 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4703 4704 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4705 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4706 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 4707 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 4708 (I40E_GLGEN_MSCA_MDICMD_MASK); 4709 4710 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4711 do { 4712 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4713 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4714 status = 0; 4715 break; 4716 } 4717 udelay(10); 4718 retry--; 4719 } while (retry); 4720 4721 return status; 4722 } 4723 4724 /** 4725 * i40e_read_phy_register_clause45 4726 * @hw: pointer to the HW structure 4727 * @page: registers page number 4728 * @reg: register address in the page 4729 * @phy_addr: PHY address on MDIO interface 4730 * @value: PHY register value 4731 * 4732 * Reads specified PHY register value 4733 **/ 4734 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw, 4735 u8 page, u16 reg, u8 phy_addr, u16 *value) 4736 { 4737 i40e_status status = I40E_ERR_TIMEOUT; 4738 u32 command = 0; 4739 u16 retry = 1000; 4740 u8 port_num = hw->func_caps.mdio_port_num; 4741 4742 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4743 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4744 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4745 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4746 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4747 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4748 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4749 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4750 do { 4751 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4752 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4753 status = 0; 4754 break; 4755 } 4756 usleep_range(10, 20); 4757 retry--; 4758 } while (retry); 4759 4760 if (status) { 4761 i40e_debug(hw, I40E_DEBUG_PHY, 4762 "PHY: Can't write command to external PHY.\n"); 4763 goto phy_read_end; 4764 } 4765 4766 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4767 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4768 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 4769 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4770 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4771 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4772 status = I40E_ERR_TIMEOUT; 4773 retry = 1000; 4774 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4775 do { 4776 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4777 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4778 status = 0; 4779 break; 4780 } 4781 usleep_range(10, 20); 4782 retry--; 4783 } while (retry); 4784 4785 if (!status) { 4786 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 4787 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 4788 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 4789 } else { 4790 i40e_debug(hw, I40E_DEBUG_PHY, 4791 "PHY: Can't read register value from external PHY.\n"); 4792 } 4793 4794 phy_read_end: 4795 return status; 4796 } 4797 4798 /** 4799 * i40e_write_phy_register_clause45 4800 * @hw: pointer to the HW structure 4801 * @page: registers page number 4802 * @reg: register address in the page 4803 * @phy_addr: PHY address on MDIO interface 4804 * @value: PHY register value 4805 * 4806 * Writes value to specified PHY register 4807 **/ 4808 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw, 4809 u8 page, u16 reg, u8 phy_addr, u16 value) 4810 { 4811 i40e_status status = I40E_ERR_TIMEOUT; 4812 u32 command = 0; 4813 u16 retry = 1000; 4814 u8 port_num = hw->func_caps.mdio_port_num; 4815 4816 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 4817 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4818 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4819 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 4820 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4821 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4822 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4823 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4824 do { 4825 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4826 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4827 status = 0; 4828 break; 4829 } 4830 usleep_range(10, 20); 4831 retry--; 4832 } while (retry); 4833 if (status) { 4834 i40e_debug(hw, I40E_DEBUG_PHY, 4835 "PHY: Can't write command to external PHY.\n"); 4836 goto phy_write_end; 4837 } 4838 4839 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 4840 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 4841 4842 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 4843 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 4844 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 4845 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 4846 (I40E_GLGEN_MSCA_MDICMD_MASK) | 4847 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 4848 status = I40E_ERR_TIMEOUT; 4849 retry = 1000; 4850 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 4851 do { 4852 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 4853 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 4854 status = 0; 4855 break; 4856 } 4857 usleep_range(10, 20); 4858 retry--; 4859 } while (retry); 4860 4861 phy_write_end: 4862 return status; 4863 } 4864 4865 /** 4866 * i40e_write_phy_register 4867 * @hw: pointer to the HW structure 4868 * @page: registers page number 4869 * @reg: register address in the page 4870 * @phy_addr: PHY address on MDIO interface 4871 * @value: PHY register value 4872 * 4873 * Writes value to specified PHY register 4874 **/ 4875 i40e_status i40e_write_phy_register(struct i40e_hw *hw, 4876 u8 page, u16 reg, u8 phy_addr, u16 value) 4877 { 4878 i40e_status status; 4879 4880 switch (hw->device_id) { 4881 case I40E_DEV_ID_1G_BASE_T_X722: 4882 status = i40e_write_phy_register_clause22(hw, reg, phy_addr, 4883 value); 4884 break; 4885 case I40E_DEV_ID_10G_BASE_T: 4886 case I40E_DEV_ID_10G_BASE_T4: 4887 case I40E_DEV_ID_10G_BASE_T_X722: 4888 case I40E_DEV_ID_25G_B: 4889 case I40E_DEV_ID_25G_SFP28: 4890 status = i40e_write_phy_register_clause45(hw, page, reg, 4891 phy_addr, value); 4892 break; 4893 default: 4894 status = I40E_ERR_UNKNOWN_PHY; 4895 break; 4896 } 4897 4898 return status; 4899 } 4900 4901 /** 4902 * i40e_read_phy_register 4903 * @hw: pointer to the HW structure 4904 * @page: registers page number 4905 * @reg: register address in the page 4906 * @phy_addr: PHY address on MDIO interface 4907 * @value: PHY register value 4908 * 4909 * Reads specified PHY register value 4910 **/ 4911 i40e_status i40e_read_phy_register(struct i40e_hw *hw, 4912 u8 page, u16 reg, u8 phy_addr, u16 *value) 4913 { 4914 i40e_status status; 4915 4916 switch (hw->device_id) { 4917 case I40E_DEV_ID_1G_BASE_T_X722: 4918 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 4919 value); 4920 break; 4921 case I40E_DEV_ID_10G_BASE_T: 4922 case I40E_DEV_ID_10G_BASE_T4: 4923 case I40E_DEV_ID_10G_BASE_T_BC: 4924 case I40E_DEV_ID_10G_BASE_T_X722: 4925 case I40E_DEV_ID_25G_B: 4926 case I40E_DEV_ID_25G_SFP28: 4927 status = i40e_read_phy_register_clause45(hw, page, reg, 4928 phy_addr, value); 4929 break; 4930 default: 4931 status = I40E_ERR_UNKNOWN_PHY; 4932 break; 4933 } 4934 4935 return status; 4936 } 4937 4938 /** 4939 * i40e_get_phy_address 4940 * @hw: pointer to the HW structure 4941 * @dev_num: PHY port num that address we want 4942 * 4943 * Gets PHY address for current port 4944 **/ 4945 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 4946 { 4947 u8 port_num = hw->func_caps.mdio_port_num; 4948 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 4949 4950 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 4951 } 4952 4953 /** 4954 * i40e_blink_phy_led 4955 * @hw: pointer to the HW structure 4956 * @time: time how long led will blinks in secs 4957 * @interval: gap between LED on and off in msecs 4958 * 4959 * Blinks PHY link LED 4960 **/ 4961 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, 4962 u32 time, u32 interval) 4963 { 4964 i40e_status status = 0; 4965 u32 i; 4966 u16 led_ctl; 4967 u16 gpio_led_port; 4968 u16 led_reg; 4969 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 4970 u8 phy_addr = 0; 4971 u8 port_num; 4972 4973 i = rd32(hw, I40E_PFGEN_PORTNUM); 4974 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 4975 phy_addr = i40e_get_phy_address(hw, port_num); 4976 4977 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 4978 led_addr++) { 4979 status = i40e_read_phy_register_clause45(hw, 4980 I40E_PHY_COM_REG_PAGE, 4981 led_addr, phy_addr, 4982 &led_reg); 4983 if (status) 4984 goto phy_blinking_end; 4985 led_ctl = led_reg; 4986 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 4987 led_reg = 0; 4988 status = i40e_write_phy_register_clause45(hw, 4989 I40E_PHY_COM_REG_PAGE, 4990 led_addr, phy_addr, 4991 led_reg); 4992 if (status) 4993 goto phy_blinking_end; 4994 break; 4995 } 4996 } 4997 4998 if (time > 0 && interval > 0) { 4999 for (i = 0; i < time * 1000; i += interval) { 5000 status = i40e_read_phy_register_clause45(hw, 5001 I40E_PHY_COM_REG_PAGE, 5002 led_addr, phy_addr, &led_reg); 5003 if (status) 5004 goto restore_config; 5005 if (led_reg & I40E_PHY_LED_MANUAL_ON) 5006 led_reg = 0; 5007 else 5008 led_reg = I40E_PHY_LED_MANUAL_ON; 5009 status = i40e_write_phy_register_clause45(hw, 5010 I40E_PHY_COM_REG_PAGE, 5011 led_addr, phy_addr, led_reg); 5012 if (status) 5013 goto restore_config; 5014 msleep(interval); 5015 } 5016 } 5017 5018 restore_config: 5019 status = i40e_write_phy_register_clause45(hw, 5020 I40E_PHY_COM_REG_PAGE, 5021 led_addr, phy_addr, led_ctl); 5022 5023 phy_blinking_end: 5024 return status; 5025 } 5026 5027 /** 5028 * i40e_led_get_reg - read LED register 5029 * @hw: pointer to the HW structure 5030 * @led_addr: LED register address 5031 * @reg_val: read register value 5032 **/ 5033 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 5034 u32 *reg_val) 5035 { 5036 enum i40e_status_code status; 5037 u8 phy_addr = 0; 5038 u8 port_num; 5039 u32 i; 5040 5041 *reg_val = 0; 5042 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5043 status = 5044 i40e_aq_get_phy_register(hw, 5045 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5046 I40E_PHY_COM_REG_PAGE, 5047 I40E_PHY_LED_PROV_REG_1, 5048 reg_val, NULL); 5049 } else { 5050 i = rd32(hw, I40E_PFGEN_PORTNUM); 5051 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5052 phy_addr = i40e_get_phy_address(hw, port_num); 5053 status = i40e_read_phy_register_clause45(hw, 5054 I40E_PHY_COM_REG_PAGE, 5055 led_addr, phy_addr, 5056 (u16 *)reg_val); 5057 } 5058 return status; 5059 } 5060 5061 /** 5062 * i40e_led_set_reg - write LED register 5063 * @hw: pointer to the HW structure 5064 * @led_addr: LED register address 5065 * @reg_val: register value to write 5066 **/ 5067 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 5068 u32 reg_val) 5069 { 5070 enum i40e_status_code status; 5071 u8 phy_addr = 0; 5072 u8 port_num; 5073 u32 i; 5074 5075 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5076 status = 5077 i40e_aq_set_phy_register(hw, 5078 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5079 I40E_PHY_COM_REG_PAGE, 5080 I40E_PHY_LED_PROV_REG_1, 5081 reg_val, NULL); 5082 } else { 5083 i = rd32(hw, I40E_PFGEN_PORTNUM); 5084 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5085 phy_addr = i40e_get_phy_address(hw, port_num); 5086 status = i40e_write_phy_register_clause45(hw, 5087 I40E_PHY_COM_REG_PAGE, 5088 led_addr, phy_addr, 5089 (u16)reg_val); 5090 } 5091 5092 return status; 5093 } 5094 5095 /** 5096 * i40e_led_get_phy - return current on/off mode 5097 * @hw: pointer to the hw struct 5098 * @led_addr: address of led register to use 5099 * @val: original value of register to use 5100 * 5101 **/ 5102 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 5103 u16 *val) 5104 { 5105 i40e_status status = 0; 5106 u16 gpio_led_port; 5107 u8 phy_addr = 0; 5108 u16 reg_val; 5109 u16 temp_addr; 5110 u8 port_num; 5111 u32 i; 5112 u32 reg_val_aq; 5113 5114 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 5115 status = 5116 i40e_aq_get_phy_register(hw, 5117 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 5118 I40E_PHY_COM_REG_PAGE, 5119 I40E_PHY_LED_PROV_REG_1, 5120 ®_val_aq, NULL); 5121 if (status == I40E_SUCCESS) 5122 *val = (u16)reg_val_aq; 5123 return status; 5124 } 5125 temp_addr = I40E_PHY_LED_PROV_REG_1; 5126 i = rd32(hw, I40E_PFGEN_PORTNUM); 5127 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 5128 phy_addr = i40e_get_phy_address(hw, port_num); 5129 5130 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 5131 temp_addr++) { 5132 status = i40e_read_phy_register_clause45(hw, 5133 I40E_PHY_COM_REG_PAGE, 5134 temp_addr, phy_addr, 5135 ®_val); 5136 if (status) 5137 return status; 5138 *val = reg_val; 5139 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 5140 *led_addr = temp_addr; 5141 break; 5142 } 5143 } 5144 return status; 5145 } 5146 5147 /** 5148 * i40e_led_set_phy 5149 * @hw: pointer to the HW structure 5150 * @on: true or false 5151 * @led_addr: address of led register to use 5152 * @mode: original val plus bit for set or ignore 5153 * 5154 * Set led's on or off when controlled by the PHY 5155 * 5156 **/ 5157 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on, 5158 u16 led_addr, u32 mode) 5159 { 5160 i40e_status status = 0; 5161 u32 led_ctl = 0; 5162 u32 led_reg = 0; 5163 5164 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5165 if (status) 5166 return status; 5167 led_ctl = led_reg; 5168 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 5169 led_reg = 0; 5170 status = i40e_led_set_reg(hw, led_addr, led_reg); 5171 if (status) 5172 return status; 5173 } 5174 status = i40e_led_get_reg(hw, led_addr, &led_reg); 5175 if (status) 5176 goto restore_config; 5177 if (on) 5178 led_reg = I40E_PHY_LED_MANUAL_ON; 5179 else 5180 led_reg = 0; 5181 5182 status = i40e_led_set_reg(hw, led_addr, led_reg); 5183 if (status) 5184 goto restore_config; 5185 if (mode & I40E_PHY_LED_MODE_ORIG) { 5186 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 5187 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5188 } 5189 return status; 5190 5191 restore_config: 5192 status = i40e_led_set_reg(hw, led_addr, led_ctl); 5193 return status; 5194 } 5195 5196 /** 5197 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 5198 * @hw: pointer to the hw struct 5199 * @reg_addr: register address 5200 * @reg_val: ptr to register value 5201 * @cmd_details: pointer to command details structure or NULL 5202 * 5203 * Use the firmware to read the Rx control register, 5204 * especially useful if the Rx unit is under heavy pressure 5205 **/ 5206 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 5207 u32 reg_addr, u32 *reg_val, 5208 struct i40e_asq_cmd_details *cmd_details) 5209 { 5210 struct i40e_aq_desc desc; 5211 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 5212 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5213 i40e_status status; 5214 5215 if (!reg_val) 5216 return I40E_ERR_PARAM; 5217 5218 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 5219 5220 cmd_resp->address = cpu_to_le32(reg_addr); 5221 5222 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5223 5224 if (status == 0) 5225 *reg_val = le32_to_cpu(cmd_resp->value); 5226 5227 return status; 5228 } 5229 5230 /** 5231 * i40e_read_rx_ctl - read from an Rx control register 5232 * @hw: pointer to the hw struct 5233 * @reg_addr: register address 5234 **/ 5235 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 5236 { 5237 i40e_status status = 0; 5238 bool use_register; 5239 int retry = 5; 5240 u32 val = 0; 5241 5242 use_register = (((hw->aq.api_maj_ver == 1) && 5243 (hw->aq.api_min_ver < 5)) || 5244 (hw->mac.type == I40E_MAC_X722)); 5245 if (!use_register) { 5246 do_retry: 5247 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 5248 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5249 usleep_range(1000, 2000); 5250 retry--; 5251 goto do_retry; 5252 } 5253 } 5254 5255 /* if the AQ access failed, try the old-fashioned way */ 5256 if (status || use_register) 5257 val = rd32(hw, reg_addr); 5258 5259 return val; 5260 } 5261 5262 /** 5263 * i40e_aq_rx_ctl_write_register 5264 * @hw: pointer to the hw struct 5265 * @reg_addr: register address 5266 * @reg_val: register value 5267 * @cmd_details: pointer to command details structure or NULL 5268 * 5269 * Use the firmware to write to an Rx control register, 5270 * especially useful if the Rx unit is under heavy pressure 5271 **/ 5272 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 5273 u32 reg_addr, u32 reg_val, 5274 struct i40e_asq_cmd_details *cmd_details) 5275 { 5276 struct i40e_aq_desc desc; 5277 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 5278 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 5279 i40e_status status; 5280 5281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 5282 5283 cmd->address = cpu_to_le32(reg_addr); 5284 cmd->value = cpu_to_le32(reg_val); 5285 5286 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5287 5288 return status; 5289 } 5290 5291 /** 5292 * i40e_write_rx_ctl - write to an Rx control register 5293 * @hw: pointer to the hw struct 5294 * @reg_addr: register address 5295 * @reg_val: register value 5296 **/ 5297 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 5298 { 5299 i40e_status status = 0; 5300 bool use_register; 5301 int retry = 5; 5302 5303 use_register = (((hw->aq.api_maj_ver == 1) && 5304 (hw->aq.api_min_ver < 5)) || 5305 (hw->mac.type == I40E_MAC_X722)); 5306 if (!use_register) { 5307 do_retry: 5308 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 5309 reg_val, NULL); 5310 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 5311 usleep_range(1000, 2000); 5312 retry--; 5313 goto do_retry; 5314 } 5315 } 5316 5317 /* if the AQ access failed, try the old-fashioned way */ 5318 if (status || use_register) 5319 wr32(hw, reg_addr, reg_val); 5320 } 5321 5322 /** 5323 * i40e_aq_set_phy_register 5324 * @hw: pointer to the hw struct 5325 * @phy_select: select which phy should be accessed 5326 * @dev_addr: PHY device address 5327 * @reg_addr: PHY register address 5328 * @reg_val: new register value 5329 * @cmd_details: pointer to command details structure or NULL 5330 * 5331 * Write the external PHY register. 5332 **/ 5333 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, 5334 u8 phy_select, u8 dev_addr, 5335 u32 reg_addr, u32 reg_val, 5336 struct i40e_asq_cmd_details *cmd_details) 5337 { 5338 struct i40e_aq_desc desc; 5339 struct i40e_aqc_phy_register_access *cmd = 5340 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5341 i40e_status status; 5342 5343 i40e_fill_default_direct_cmd_desc(&desc, 5344 i40e_aqc_opc_set_phy_register); 5345 5346 cmd->phy_interface = phy_select; 5347 cmd->dev_address = dev_addr; 5348 cmd->reg_address = cpu_to_le32(reg_addr); 5349 cmd->reg_value = cpu_to_le32(reg_val); 5350 5351 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5352 5353 return status; 5354 } 5355 5356 /** 5357 * i40e_aq_get_phy_register 5358 * @hw: pointer to the hw struct 5359 * @phy_select: select which phy should be accessed 5360 * @dev_addr: PHY device address 5361 * @reg_addr: PHY register address 5362 * @reg_val: read register value 5363 * @cmd_details: pointer to command details structure or NULL 5364 * 5365 * Read the external PHY register. 5366 **/ 5367 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, 5368 u8 phy_select, u8 dev_addr, 5369 u32 reg_addr, u32 *reg_val, 5370 struct i40e_asq_cmd_details *cmd_details) 5371 { 5372 struct i40e_aq_desc desc; 5373 struct i40e_aqc_phy_register_access *cmd = 5374 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 5375 i40e_status status; 5376 5377 i40e_fill_default_direct_cmd_desc(&desc, 5378 i40e_aqc_opc_get_phy_register); 5379 5380 cmd->phy_interface = phy_select; 5381 cmd->dev_address = dev_addr; 5382 cmd->reg_address = cpu_to_le32(reg_addr); 5383 5384 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5385 if (!status) 5386 *reg_val = le32_to_cpu(cmd->reg_value); 5387 5388 return status; 5389 } 5390 5391 /** 5392 * i40e_aq_write_ddp - Write dynamic device personalization (ddp) 5393 * @hw: pointer to the hw struct 5394 * @buff: command buffer (size in bytes = buff_size) 5395 * @buff_size: buffer size in bytes 5396 * @track_id: package tracking id 5397 * @error_offset: returns error offset 5398 * @error_info: returns error information 5399 * @cmd_details: pointer to command details structure or NULL 5400 **/ 5401 enum 5402 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff, 5403 u16 buff_size, u32 track_id, 5404 u32 *error_offset, u32 *error_info, 5405 struct i40e_asq_cmd_details *cmd_details) 5406 { 5407 struct i40e_aq_desc desc; 5408 struct i40e_aqc_write_personalization_profile *cmd = 5409 (struct i40e_aqc_write_personalization_profile *) 5410 &desc.params.raw; 5411 struct i40e_aqc_write_ddp_resp *resp; 5412 i40e_status status; 5413 5414 i40e_fill_default_direct_cmd_desc(&desc, 5415 i40e_aqc_opc_write_personalization_profile); 5416 5417 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 5418 if (buff_size > I40E_AQ_LARGE_BUF) 5419 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5420 5421 desc.datalen = cpu_to_le16(buff_size); 5422 5423 cmd->profile_track_id = cpu_to_le32(track_id); 5424 5425 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5426 if (!status) { 5427 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; 5428 if (error_offset) 5429 *error_offset = le32_to_cpu(resp->error_offset); 5430 if (error_info) 5431 *error_info = le32_to_cpu(resp->error_info); 5432 } 5433 5434 return status; 5435 } 5436 5437 /** 5438 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp) 5439 * @hw: pointer to the hw struct 5440 * @buff: command buffer (size in bytes = buff_size) 5441 * @buff_size: buffer size in bytes 5442 * @flags: AdminQ command flags 5443 * @cmd_details: pointer to command details structure or NULL 5444 **/ 5445 enum 5446 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff, 5447 u16 buff_size, u8 flags, 5448 struct i40e_asq_cmd_details *cmd_details) 5449 { 5450 struct i40e_aq_desc desc; 5451 struct i40e_aqc_get_applied_profiles *cmd = 5452 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; 5453 i40e_status status; 5454 5455 i40e_fill_default_direct_cmd_desc(&desc, 5456 i40e_aqc_opc_get_personalization_profile_list); 5457 5458 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 5459 if (buff_size > I40E_AQ_LARGE_BUF) 5460 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5461 desc.datalen = cpu_to_le16(buff_size); 5462 5463 cmd->flags = flags; 5464 5465 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5466 5467 return status; 5468 } 5469 5470 /** 5471 * i40e_find_segment_in_package 5472 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) 5473 * @pkg_hdr: pointer to the package header to be searched 5474 * 5475 * This function searches a package file for a particular segment type. On 5476 * success it returns a pointer to the segment header, otherwise it will 5477 * return NULL. 5478 **/ 5479 struct i40e_generic_seg_header * 5480 i40e_find_segment_in_package(u32 segment_type, 5481 struct i40e_package_header *pkg_hdr) 5482 { 5483 struct i40e_generic_seg_header *segment; 5484 u32 i; 5485 5486 /* Search all package segments for the requested segment type */ 5487 for (i = 0; i < pkg_hdr->segment_count; i++) { 5488 segment = 5489 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + 5490 pkg_hdr->segment_offset[i]); 5491 5492 if (segment->type == segment_type) 5493 return segment; 5494 } 5495 5496 return NULL; 5497 } 5498 5499 /* Get section table in profile */ 5500 #define I40E_SECTION_TABLE(profile, sec_tbl) \ 5501 do { \ 5502 struct i40e_profile_segment *p = (profile); \ 5503 u32 count; \ 5504 u32 *nvm; \ 5505 count = p->device_table_count; \ 5506 nvm = (u32 *)&p->device_table[count]; \ 5507 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \ 5508 } while (0) 5509 5510 /* Get section header in profile */ 5511 #define I40E_SECTION_HEADER(profile, offset) \ 5512 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset)) 5513 5514 /** 5515 * i40e_find_section_in_profile 5516 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE) 5517 * @profile: pointer to the i40e segment header to be searched 5518 * 5519 * This function searches i40e segment for a particular section type. On 5520 * success it returns a pointer to the section header, otherwise it will 5521 * return NULL. 5522 **/ 5523 struct i40e_profile_section_header * 5524 i40e_find_section_in_profile(u32 section_type, 5525 struct i40e_profile_segment *profile) 5526 { 5527 struct i40e_profile_section_header *sec; 5528 struct i40e_section_table *sec_tbl; 5529 u32 sec_off; 5530 u32 i; 5531 5532 if (profile->header.type != SEGMENT_TYPE_I40E) 5533 return NULL; 5534 5535 I40E_SECTION_TABLE(profile, sec_tbl); 5536 5537 for (i = 0; i < sec_tbl->section_count; i++) { 5538 sec_off = sec_tbl->section_offset[i]; 5539 sec = I40E_SECTION_HEADER(profile, sec_off); 5540 if (sec->section.type == section_type) 5541 return sec; 5542 } 5543 5544 return NULL; 5545 } 5546 5547 /** 5548 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP 5549 * @hw: pointer to the hw struct 5550 * @aq: command buffer containing all data to execute AQ 5551 **/ 5552 static enum 5553 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw, 5554 struct i40e_profile_aq_section *aq) 5555 { 5556 i40e_status status; 5557 struct i40e_aq_desc desc; 5558 u8 *msg = NULL; 5559 u16 msglen; 5560 5561 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode); 5562 desc.flags |= cpu_to_le16(aq->flags); 5563 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw)); 5564 5565 msglen = aq->datalen; 5566 if (msglen) { 5567 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 5568 I40E_AQ_FLAG_RD)); 5569 if (msglen > I40E_AQ_LARGE_BUF) 5570 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 5571 desc.datalen = cpu_to_le16(msglen); 5572 msg = &aq->data[0]; 5573 } 5574 5575 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL); 5576 5577 if (status) { 5578 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5579 "unable to exec DDP AQ opcode %u, error %d\n", 5580 aq->opcode, status); 5581 return status; 5582 } 5583 5584 /* copy returned desc to aq_buf */ 5585 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw)); 5586 5587 return 0; 5588 } 5589 5590 /** 5591 * i40e_validate_profile 5592 * @hw: pointer to the hardware structure 5593 * @profile: pointer to the profile segment of the package to be validated 5594 * @track_id: package tracking id 5595 * @rollback: flag if the profile is for rollback. 5596 * 5597 * Validates supported devices and profile's sections. 5598 */ 5599 static enum i40e_status_code 5600 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5601 u32 track_id, bool rollback) 5602 { 5603 struct i40e_profile_section_header *sec = NULL; 5604 i40e_status status = 0; 5605 struct i40e_section_table *sec_tbl; 5606 u32 vendor_dev_id; 5607 u32 dev_cnt; 5608 u32 sec_off; 5609 u32 i; 5610 5611 if (track_id == I40E_DDP_TRACKID_INVALID) { 5612 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n"); 5613 return I40E_NOT_SUPPORTED; 5614 } 5615 5616 dev_cnt = profile->device_table_count; 5617 for (i = 0; i < dev_cnt; i++) { 5618 vendor_dev_id = profile->device_table[i].vendor_dev_id; 5619 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL && 5620 hw->device_id == (vendor_dev_id & 0xFFFF)) 5621 break; 5622 } 5623 if (dev_cnt && i == dev_cnt) { 5624 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5625 "Device doesn't support DDP\n"); 5626 return I40E_ERR_DEVICE_NOT_SUPPORTED; 5627 } 5628 5629 I40E_SECTION_TABLE(profile, sec_tbl); 5630 5631 /* Validate sections types */ 5632 for (i = 0; i < sec_tbl->section_count; i++) { 5633 sec_off = sec_tbl->section_offset[i]; 5634 sec = I40E_SECTION_HEADER(profile, sec_off); 5635 if (rollback) { 5636 if (sec->section.type == SECTION_TYPE_MMIO || 5637 sec->section.type == SECTION_TYPE_AQ || 5638 sec->section.type == SECTION_TYPE_RB_AQ) { 5639 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5640 "Not a roll-back package\n"); 5641 return I40E_NOT_SUPPORTED; 5642 } 5643 } else { 5644 if (sec->section.type == SECTION_TYPE_RB_AQ || 5645 sec->section.type == SECTION_TYPE_RB_MMIO) { 5646 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5647 "Not an original package\n"); 5648 return I40E_NOT_SUPPORTED; 5649 } 5650 } 5651 } 5652 5653 return status; 5654 } 5655 5656 /** 5657 * i40e_write_profile 5658 * @hw: pointer to the hardware structure 5659 * @profile: pointer to the profile segment of the package to be downloaded 5660 * @track_id: package tracking id 5661 * 5662 * Handles the download of a complete package. 5663 */ 5664 enum i40e_status_code 5665 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5666 u32 track_id) 5667 { 5668 i40e_status status = 0; 5669 struct i40e_section_table *sec_tbl; 5670 struct i40e_profile_section_header *sec = NULL; 5671 struct i40e_profile_aq_section *ddp_aq; 5672 u32 section_size = 0; 5673 u32 offset = 0, info = 0; 5674 u32 sec_off; 5675 u32 i; 5676 5677 status = i40e_validate_profile(hw, profile, track_id, false); 5678 if (status) 5679 return status; 5680 5681 I40E_SECTION_TABLE(profile, sec_tbl); 5682 5683 for (i = 0; i < sec_tbl->section_count; i++) { 5684 sec_off = sec_tbl->section_offset[i]; 5685 sec = I40E_SECTION_HEADER(profile, sec_off); 5686 /* Process generic admin command */ 5687 if (sec->section.type == SECTION_TYPE_AQ) { 5688 ddp_aq = (struct i40e_profile_aq_section *)&sec[1]; 5689 status = i40e_ddp_exec_aq_section(hw, ddp_aq); 5690 if (status) { 5691 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5692 "Failed to execute aq: section %d, opcode %u\n", 5693 i, ddp_aq->opcode); 5694 break; 5695 } 5696 sec->section.type = SECTION_TYPE_RB_AQ; 5697 } 5698 5699 /* Skip any non-mmio sections */ 5700 if (sec->section.type != SECTION_TYPE_MMIO) 5701 continue; 5702 5703 section_size = sec->section.size + 5704 sizeof(struct i40e_profile_section_header); 5705 5706 /* Write MMIO section */ 5707 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5708 track_id, &offset, &info, NULL); 5709 if (status) { 5710 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5711 "Failed to write profile: section %d, offset %d, info %d\n", 5712 i, offset, info); 5713 break; 5714 } 5715 } 5716 return status; 5717 } 5718 5719 /** 5720 * i40e_rollback_profile 5721 * @hw: pointer to the hardware structure 5722 * @profile: pointer to the profile segment of the package to be removed 5723 * @track_id: package tracking id 5724 * 5725 * Rolls back previously loaded package. 5726 */ 5727 enum i40e_status_code 5728 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, 5729 u32 track_id) 5730 { 5731 struct i40e_profile_section_header *sec = NULL; 5732 i40e_status status = 0; 5733 struct i40e_section_table *sec_tbl; 5734 u32 offset = 0, info = 0; 5735 u32 section_size = 0; 5736 u32 sec_off; 5737 int i; 5738 5739 status = i40e_validate_profile(hw, profile, track_id, true); 5740 if (status) 5741 return status; 5742 5743 I40E_SECTION_TABLE(profile, sec_tbl); 5744 5745 /* For rollback write sections in reverse */ 5746 for (i = sec_tbl->section_count - 1; i >= 0; i--) { 5747 sec_off = sec_tbl->section_offset[i]; 5748 sec = I40E_SECTION_HEADER(profile, sec_off); 5749 5750 /* Skip any non-rollback sections */ 5751 if (sec->section.type != SECTION_TYPE_RB_MMIO) 5752 continue; 5753 5754 section_size = sec->section.size + 5755 sizeof(struct i40e_profile_section_header); 5756 5757 /* Write roll-back MMIO section */ 5758 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size, 5759 track_id, &offset, &info, NULL); 5760 if (status) { 5761 i40e_debug(hw, I40E_DEBUG_PACKAGE, 5762 "Failed to write profile: section %d, offset %d, info %d\n", 5763 i, offset, info); 5764 break; 5765 } 5766 } 5767 return status; 5768 } 5769 5770 /** 5771 * i40e_add_pinfo_to_list 5772 * @hw: pointer to the hardware structure 5773 * @profile: pointer to the profile segment of the package 5774 * @profile_info_sec: buffer for information section 5775 * @track_id: package tracking id 5776 * 5777 * Register a profile to the list of loaded profiles. 5778 */ 5779 enum i40e_status_code 5780 i40e_add_pinfo_to_list(struct i40e_hw *hw, 5781 struct i40e_profile_segment *profile, 5782 u8 *profile_info_sec, u32 track_id) 5783 { 5784 i40e_status status = 0; 5785 struct i40e_profile_section_header *sec = NULL; 5786 struct i40e_profile_info *pinfo; 5787 u32 offset = 0, info = 0; 5788 5789 sec = (struct i40e_profile_section_header *)profile_info_sec; 5790 sec->tbl_size = 1; 5791 sec->data_end = sizeof(struct i40e_profile_section_header) + 5792 sizeof(struct i40e_profile_info); 5793 sec->section.type = SECTION_TYPE_INFO; 5794 sec->section.offset = sizeof(struct i40e_profile_section_header); 5795 sec->section.size = sizeof(struct i40e_profile_info); 5796 pinfo = (struct i40e_profile_info *)(profile_info_sec + 5797 sec->section.offset); 5798 pinfo->track_id = track_id; 5799 pinfo->version = profile->version; 5800 pinfo->op = I40E_DDP_ADD_TRACKID; 5801 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); 5802 5803 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end, 5804 track_id, &offset, &info, NULL); 5805 5806 return status; 5807 } 5808 5809 /** 5810 * i40e_aq_add_cloud_filters 5811 * @hw: pointer to the hardware structure 5812 * @seid: VSI seid to add cloud filters from 5813 * @filters: Buffer which contains the filters to be added 5814 * @filter_count: number of filters contained in the buffer 5815 * 5816 * Set the cloud filters for a given VSI. The contents of the 5817 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5818 * of the function. 5819 * 5820 **/ 5821 enum i40e_status_code 5822 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid, 5823 struct i40e_aqc_cloud_filters_element_data *filters, 5824 u8 filter_count) 5825 { 5826 struct i40e_aq_desc desc; 5827 struct i40e_aqc_add_remove_cloud_filters *cmd = 5828 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5829 enum i40e_status_code status; 5830 u16 buff_len; 5831 5832 i40e_fill_default_direct_cmd_desc(&desc, 5833 i40e_aqc_opc_add_cloud_filters); 5834 5835 buff_len = filter_count * sizeof(*filters); 5836 desc.datalen = cpu_to_le16(buff_len); 5837 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5838 cmd->num_filters = filter_count; 5839 cmd->seid = cpu_to_le16(seid); 5840 5841 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5842 5843 return status; 5844 } 5845 5846 /** 5847 * i40e_aq_add_cloud_filters_bb 5848 * @hw: pointer to the hardware structure 5849 * @seid: VSI seid to add cloud filters from 5850 * @filters: Buffer which contains the filters in big buffer to be added 5851 * @filter_count: number of filters contained in the buffer 5852 * 5853 * Set the big buffer cloud filters for a given VSI. The contents of the 5854 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5855 * function. 5856 * 5857 **/ 5858 enum i40e_status_code 5859 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5860 struct i40e_aqc_cloud_filters_element_bb *filters, 5861 u8 filter_count) 5862 { 5863 struct i40e_aq_desc desc; 5864 struct i40e_aqc_add_remove_cloud_filters *cmd = 5865 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5866 i40e_status status; 5867 u16 buff_len; 5868 int i; 5869 5870 i40e_fill_default_direct_cmd_desc(&desc, 5871 i40e_aqc_opc_add_cloud_filters); 5872 5873 buff_len = filter_count * sizeof(*filters); 5874 desc.datalen = cpu_to_le16(buff_len); 5875 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5876 cmd->num_filters = filter_count; 5877 cmd->seid = cpu_to_le16(seid); 5878 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5879 5880 for (i = 0; i < filter_count; i++) { 5881 u16 tnl_type; 5882 u32 ti; 5883 5884 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5885 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5886 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5887 5888 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5889 * one more byte further than normally used for Tenant ID in 5890 * other tunnel types. 5891 */ 5892 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5893 ti = le32_to_cpu(filters[i].element.tenant_id); 5894 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5895 } 5896 } 5897 5898 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5899 5900 return status; 5901 } 5902 5903 /** 5904 * i40e_aq_rem_cloud_filters 5905 * @hw: pointer to the hardware structure 5906 * @seid: VSI seid to remove cloud filters from 5907 * @filters: Buffer which contains the filters to be removed 5908 * @filter_count: number of filters contained in the buffer 5909 * 5910 * Remove the cloud filters for a given VSI. The contents of the 5911 * i40e_aqc_cloud_filters_element_data are filled in by the caller 5912 * of the function. 5913 * 5914 **/ 5915 enum i40e_status_code 5916 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid, 5917 struct i40e_aqc_cloud_filters_element_data *filters, 5918 u8 filter_count) 5919 { 5920 struct i40e_aq_desc desc; 5921 struct i40e_aqc_add_remove_cloud_filters *cmd = 5922 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5923 enum i40e_status_code status; 5924 u16 buff_len; 5925 5926 i40e_fill_default_direct_cmd_desc(&desc, 5927 i40e_aqc_opc_remove_cloud_filters); 5928 5929 buff_len = filter_count * sizeof(*filters); 5930 desc.datalen = cpu_to_le16(buff_len); 5931 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5932 cmd->num_filters = filter_count; 5933 cmd->seid = cpu_to_le16(seid); 5934 5935 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5936 5937 return status; 5938 } 5939 5940 /** 5941 * i40e_aq_rem_cloud_filters_bb 5942 * @hw: pointer to the hardware structure 5943 * @seid: VSI seid to remove cloud filters from 5944 * @filters: Buffer which contains the filters in big buffer to be removed 5945 * @filter_count: number of filters contained in the buffer 5946 * 5947 * Remove the big buffer cloud filters for a given VSI. The contents of the 5948 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the 5949 * function. 5950 * 5951 **/ 5952 enum i40e_status_code 5953 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid, 5954 struct i40e_aqc_cloud_filters_element_bb *filters, 5955 u8 filter_count) 5956 { 5957 struct i40e_aq_desc desc; 5958 struct i40e_aqc_add_remove_cloud_filters *cmd = 5959 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5960 i40e_status status; 5961 u16 buff_len; 5962 int i; 5963 5964 i40e_fill_default_direct_cmd_desc(&desc, 5965 i40e_aqc_opc_remove_cloud_filters); 5966 5967 buff_len = filter_count * sizeof(*filters); 5968 desc.datalen = cpu_to_le16(buff_len); 5969 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5970 cmd->num_filters = filter_count; 5971 cmd->seid = cpu_to_le16(seid); 5972 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB; 5973 5974 for (i = 0; i < filter_count; i++) { 5975 u16 tnl_type; 5976 u32 ti; 5977 5978 tnl_type = (le16_to_cpu(filters[i].element.flags) & 5979 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5980 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5981 5982 /* Due to hardware eccentricities, the VNI for Geneve is shifted 5983 * one more byte further than normally used for Tenant ID in 5984 * other tunnel types. 5985 */ 5986 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5987 ti = le32_to_cpu(filters[i].element.tenant_id); 5988 filters[i].element.tenant_id = cpu_to_le32(ti << 8); 5989 } 5990 } 5991 5992 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5993 5994 return status; 5995 } 5996