1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0005 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 /* LAA */ 136 i40e_aqc_opc_mac_address_read = 0x0107, 137 i40e_aqc_opc_mac_address_write = 0x0108, 138 139 /* PXE */ 140 i40e_aqc_opc_clear_pxe_mode = 0x0110, 141 142 /* internal switch commands */ 143 i40e_aqc_opc_get_switch_config = 0x0200, 144 i40e_aqc_opc_add_statistics = 0x0201, 145 i40e_aqc_opc_remove_statistics = 0x0202, 146 i40e_aqc_opc_set_port_parameters = 0x0203, 147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 148 i40e_aqc_opc_set_switch_config = 0x0205, 149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 151 152 i40e_aqc_opc_add_vsi = 0x0210, 153 i40e_aqc_opc_update_vsi_parameters = 0x0211, 154 i40e_aqc_opc_get_vsi_parameters = 0x0212, 155 156 i40e_aqc_opc_add_pv = 0x0220, 157 i40e_aqc_opc_update_pv_parameters = 0x0221, 158 i40e_aqc_opc_get_pv_parameters = 0x0222, 159 160 i40e_aqc_opc_add_veb = 0x0230, 161 i40e_aqc_opc_update_veb_parameters = 0x0231, 162 i40e_aqc_opc_get_veb_parameters = 0x0232, 163 164 i40e_aqc_opc_delete_element = 0x0243, 165 166 i40e_aqc_opc_add_macvlan = 0x0250, 167 i40e_aqc_opc_remove_macvlan = 0x0251, 168 i40e_aqc_opc_add_vlan = 0x0252, 169 i40e_aqc_opc_remove_vlan = 0x0253, 170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 171 i40e_aqc_opc_add_tag = 0x0255, 172 i40e_aqc_opc_remove_tag = 0x0256, 173 i40e_aqc_opc_add_multicast_etag = 0x0257, 174 i40e_aqc_opc_remove_multicast_etag = 0x0258, 175 i40e_aqc_opc_update_tag = 0x0259, 176 i40e_aqc_opc_add_control_packet_filter = 0x025A, 177 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 178 i40e_aqc_opc_add_cloud_filters = 0x025C, 179 i40e_aqc_opc_remove_cloud_filters = 0x025D, 180 181 i40e_aqc_opc_add_mirror_rule = 0x0260, 182 i40e_aqc_opc_delete_mirror_rule = 0x0261, 183 184 /* DCB commands */ 185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 186 i40e_aqc_opc_dcb_updated = 0x0302, 187 188 /* TX scheduler */ 189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 192 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 195 196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 202 i40e_aqc_opc_query_port_ets_config = 0x0419, 203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 204 i40e_aqc_opc_suspend_port_tx = 0x041B, 205 i40e_aqc_opc_resume_port_tx = 0x041C, 206 i40e_aqc_opc_configure_partition_bw = 0x041D, 207 /* hmc */ 208 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 209 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 210 211 /* phy commands*/ 212 i40e_aqc_opc_get_phy_abilities = 0x0600, 213 i40e_aqc_opc_set_phy_config = 0x0601, 214 i40e_aqc_opc_set_mac_config = 0x0603, 215 i40e_aqc_opc_set_link_restart_an = 0x0605, 216 i40e_aqc_opc_get_link_status = 0x0607, 217 i40e_aqc_opc_set_phy_int_mask = 0x0613, 218 i40e_aqc_opc_get_local_advt_reg = 0x0614, 219 i40e_aqc_opc_set_local_advt_reg = 0x0615, 220 i40e_aqc_opc_get_partner_advt = 0x0616, 221 i40e_aqc_opc_set_lb_modes = 0x0618, 222 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 223 i40e_aqc_opc_set_phy_debug = 0x0622, 224 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 225 i40e_aqc_opc_run_phy_activity = 0x0626, 226 227 /* NVM commands */ 228 i40e_aqc_opc_nvm_read = 0x0701, 229 i40e_aqc_opc_nvm_erase = 0x0702, 230 i40e_aqc_opc_nvm_update = 0x0703, 231 i40e_aqc_opc_nvm_config_read = 0x0704, 232 i40e_aqc_opc_nvm_config_write = 0x0705, 233 i40e_aqc_opc_oem_post_update = 0x0720, 234 i40e_aqc_opc_thermal_sensor = 0x0721, 235 236 /* virtualization commands */ 237 i40e_aqc_opc_send_msg_to_pf = 0x0801, 238 i40e_aqc_opc_send_msg_to_vf = 0x0802, 239 i40e_aqc_opc_send_msg_to_peer = 0x0803, 240 241 /* alternate structure */ 242 i40e_aqc_opc_alternate_write = 0x0900, 243 i40e_aqc_opc_alternate_write_indirect = 0x0901, 244 i40e_aqc_opc_alternate_read = 0x0902, 245 i40e_aqc_opc_alternate_read_indirect = 0x0903, 246 i40e_aqc_opc_alternate_write_done = 0x0904, 247 i40e_aqc_opc_alternate_set_mode = 0x0905, 248 i40e_aqc_opc_alternate_clear_port = 0x0906, 249 250 /* LLDP commands */ 251 i40e_aqc_opc_lldp_get_mib = 0x0A00, 252 i40e_aqc_opc_lldp_update_mib = 0x0A01, 253 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 254 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 255 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 256 i40e_aqc_opc_lldp_stop = 0x0A05, 257 i40e_aqc_opc_lldp_start = 0x0A06, 258 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 259 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 260 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 261 262 /* Tunnel commands */ 263 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 264 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 265 i40e_aqc_opc_set_rss_key = 0x0B02, 266 i40e_aqc_opc_set_rss_lut = 0x0B03, 267 i40e_aqc_opc_get_rss_key = 0x0B04, 268 i40e_aqc_opc_get_rss_lut = 0x0B05, 269 270 /* Async Events */ 271 i40e_aqc_opc_event_lan_overflow = 0x1001, 272 273 /* OEM commands */ 274 i40e_aqc_opc_oem_parameter_change = 0xFE00, 275 i40e_aqc_opc_oem_device_status_change = 0xFE01, 276 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 277 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 278 279 /* debug commands */ 280 i40e_aqc_opc_debug_read_reg = 0xFF03, 281 i40e_aqc_opc_debug_write_reg = 0xFF04, 282 i40e_aqc_opc_debug_modify_reg = 0xFF07, 283 i40e_aqc_opc_debug_dump_internals = 0xFF08, 284 }; 285 286 /* command structures and indirect data structures */ 287 288 /* Structure naming conventions: 289 * - no suffix for direct command descriptor structures 290 * - _data for indirect sent data 291 * - _resp for indirect return data (data which is both will use _data) 292 * - _completion for direct return data 293 * - _element_ for repeated elements (may also be _data or _resp) 294 * 295 * Command structures are expected to overlay the params.raw member of the basic 296 * descriptor, and as such cannot exceed 16 bytes in length. 297 */ 298 299 /* This macro is used to generate a compilation error if a structure 300 * is not exactly the correct length. It gives a divide by zero error if the 301 * structure is not of the correct size, otherwise it creates an enum that is 302 * never used. 303 */ 304 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 305 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 306 307 /* This macro is used extensively to ensure that command structures are 16 308 * bytes in length as they have to map to the raw array of that size. 309 */ 310 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 311 312 /* internal (0x00XX) commands */ 313 314 /* Get version (direct 0x0001) */ 315 struct i40e_aqc_get_version { 316 __le32 rom_ver; 317 __le32 fw_build; 318 __le16 fw_major; 319 __le16 fw_minor; 320 __le16 api_major; 321 __le16 api_minor; 322 }; 323 324 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 325 326 /* Send driver version (indirect 0x0002) */ 327 struct i40e_aqc_driver_version { 328 u8 driver_major_ver; 329 u8 driver_minor_ver; 330 u8 driver_build_ver; 331 u8 driver_subbuild_ver; 332 u8 reserved[4]; 333 __le32 address_high; 334 __le32 address_low; 335 }; 336 337 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 338 339 /* Queue Shutdown (direct 0x0003) */ 340 struct i40e_aqc_queue_shutdown { 341 __le32 driver_unloading; 342 #define I40E_AQ_DRIVER_UNLOADING 0x1 343 u8 reserved[12]; 344 }; 345 346 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 347 348 /* Set PF context (0x0004, direct) */ 349 struct i40e_aqc_set_pf_context { 350 u8 pf_id; 351 u8 reserved[15]; 352 }; 353 354 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 355 356 /* Request resource ownership (direct 0x0008) 357 * Release resource ownership (direct 0x0009) 358 */ 359 #define I40E_AQ_RESOURCE_NVM 1 360 #define I40E_AQ_RESOURCE_SDP 2 361 #define I40E_AQ_RESOURCE_ACCESS_READ 1 362 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 363 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 364 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 365 366 struct i40e_aqc_request_resource { 367 __le16 resource_id; 368 __le16 access_type; 369 __le32 timeout; 370 __le32 resource_number; 371 u8 reserved[4]; 372 }; 373 374 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 375 376 /* Get function capabilities (indirect 0x000A) 377 * Get device capabilities (indirect 0x000B) 378 */ 379 struct i40e_aqc_list_capabilites { 380 u8 command_flags; 381 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 382 u8 pf_index; 383 u8 reserved[2]; 384 __le32 count; 385 __le32 addr_high; 386 __le32 addr_low; 387 }; 388 389 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 390 391 struct i40e_aqc_list_capabilities_element_resp { 392 __le16 id; 393 u8 major_rev; 394 u8 minor_rev; 395 __le32 number; 396 __le32 logical_id; 397 __le32 phys_id; 398 u8 reserved[16]; 399 }; 400 401 /* list of caps */ 402 403 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 404 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 405 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 406 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 407 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 408 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 409 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 410 #define I40E_AQ_CAP_ID_SRIOV 0x0012 411 #define I40E_AQ_CAP_ID_VF 0x0013 412 #define I40E_AQ_CAP_ID_VMDQ 0x0014 413 #define I40E_AQ_CAP_ID_8021QBG 0x0015 414 #define I40E_AQ_CAP_ID_8021QBR 0x0016 415 #define I40E_AQ_CAP_ID_VSI 0x0017 416 #define I40E_AQ_CAP_ID_DCB 0x0018 417 #define I40E_AQ_CAP_ID_FCOE 0x0021 418 #define I40E_AQ_CAP_ID_ISCSI 0x0022 419 #define I40E_AQ_CAP_ID_RSS 0x0040 420 #define I40E_AQ_CAP_ID_RXQ 0x0041 421 #define I40E_AQ_CAP_ID_TXQ 0x0042 422 #define I40E_AQ_CAP_ID_MSIX 0x0043 423 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 424 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 425 #define I40E_AQ_CAP_ID_1588 0x0046 426 #define I40E_AQ_CAP_ID_IWARP 0x0051 427 #define I40E_AQ_CAP_ID_LED 0x0061 428 #define I40E_AQ_CAP_ID_SDP 0x0062 429 #define I40E_AQ_CAP_ID_MDIO 0x0063 430 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 431 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 432 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 433 #define I40E_AQ_CAP_ID_CEM 0x00F2 434 435 /* Set CPPM Configuration (direct 0x0103) */ 436 struct i40e_aqc_cppm_configuration { 437 __le16 command_flags; 438 #define I40E_AQ_CPPM_EN_LTRC 0x0800 439 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 440 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 441 #define I40E_AQ_CPPM_EN_HPTC 0x4000 442 #define I40E_AQ_CPPM_EN_DMARC 0x8000 443 __le16 ttlx; 444 __le32 dmacr; 445 __le16 dmcth; 446 u8 hptc; 447 u8 reserved; 448 __le32 pfltrc; 449 }; 450 451 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 452 453 /* Set ARP Proxy command / response (indirect 0x0104) */ 454 struct i40e_aqc_arp_proxy_data { 455 __le16 command_flags; 456 #define I40E_AQ_ARP_INIT_IPV4 0x0800 457 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 458 #define I40E_AQ_ARP_ENA 0x2000 459 #define I40E_AQ_ARP_ADD_IPV4 0x4000 460 #define I40E_AQ_ARP_DEL_IPV4 0x8000 461 __le16 table_id; 462 __le32 enabled_offloads; 463 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 464 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 465 __le32 ip_addr; 466 u8 mac_addr[6]; 467 u8 reserved[2]; 468 }; 469 470 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 471 472 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 473 struct i40e_aqc_ns_proxy_data { 474 __le16 table_idx_mac_addr_0; 475 __le16 table_idx_mac_addr_1; 476 __le16 table_idx_ipv6_0; 477 __le16 table_idx_ipv6_1; 478 __le16 control; 479 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 480 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 481 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 482 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 483 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 484 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 485 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 486 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 487 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 488 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 489 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 490 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 491 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 492 u8 mac_addr_0[6]; 493 u8 mac_addr_1[6]; 494 u8 local_mac_addr[6]; 495 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 496 u8 ipv6_addr_1[16]; 497 }; 498 499 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 500 501 /* Manage LAA Command (0x0106) - obsolete */ 502 struct i40e_aqc_mng_laa { 503 __le16 command_flags; 504 #define I40E_AQ_LAA_FLAG_WR 0x8000 505 u8 reserved[2]; 506 __le32 sal; 507 __le16 sah; 508 u8 reserved2[6]; 509 }; 510 511 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 512 513 /* Manage MAC Address Read Command (indirect 0x0107) */ 514 struct i40e_aqc_mac_address_read { 515 __le16 command_flags; 516 #define I40E_AQC_LAN_ADDR_VALID 0x10 517 #define I40E_AQC_SAN_ADDR_VALID 0x20 518 #define I40E_AQC_PORT_ADDR_VALID 0x40 519 #define I40E_AQC_WOL_ADDR_VALID 0x80 520 #define I40E_AQC_MC_MAG_EN_VALID 0x100 521 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 522 u8 reserved[6]; 523 __le32 addr_high; 524 __le32 addr_low; 525 }; 526 527 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 528 529 struct i40e_aqc_mac_address_read_data { 530 u8 pf_lan_mac[6]; 531 u8 pf_san_mac[6]; 532 u8 port_mac[6]; 533 u8 pf_wol_mac[6]; 534 }; 535 536 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 537 538 /* Manage MAC Address Write Command (0x0108) */ 539 struct i40e_aqc_mac_address_write { 540 __le16 command_flags; 541 #define I40E_AQC_MC_MAG_EN 0x0100 542 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 543 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 544 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 545 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 546 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 547 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 548 549 __le16 mac_sah; 550 __le32 mac_sal; 551 u8 reserved[8]; 552 }; 553 554 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 555 556 /* PXE commands (0x011x) */ 557 558 /* Clear PXE Command and response (direct 0x0110) */ 559 struct i40e_aqc_clear_pxe { 560 u8 rx_cnt; 561 u8 reserved[15]; 562 }; 563 564 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 565 566 /* Switch configuration commands (0x02xx) */ 567 568 /* Used by many indirect commands that only pass an seid and a buffer in the 569 * command 570 */ 571 struct i40e_aqc_switch_seid { 572 __le16 seid; 573 u8 reserved[6]; 574 __le32 addr_high; 575 __le32 addr_low; 576 }; 577 578 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 579 580 /* Get Switch Configuration command (indirect 0x0200) 581 * uses i40e_aqc_switch_seid for the descriptor 582 */ 583 struct i40e_aqc_get_switch_config_header_resp { 584 __le16 num_reported; 585 __le16 num_total; 586 u8 reserved[12]; 587 }; 588 589 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 590 591 struct i40e_aqc_switch_config_element_resp { 592 u8 element_type; 593 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 594 #define I40E_AQ_SW_ELEM_TYPE_PF 2 595 #define I40E_AQ_SW_ELEM_TYPE_VF 3 596 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 597 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 598 #define I40E_AQ_SW_ELEM_TYPE_PV 16 599 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 600 #define I40E_AQ_SW_ELEM_TYPE_PA 18 601 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 602 u8 revision; 603 #define I40E_AQ_SW_ELEM_REV_1 1 604 __le16 seid; 605 __le16 uplink_seid; 606 __le16 downlink_seid; 607 u8 reserved[3]; 608 u8 connection_type; 609 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 610 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 611 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 612 __le16 scheduler_id; 613 __le16 element_info; 614 }; 615 616 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 617 618 /* Get Switch Configuration (indirect 0x0200) 619 * an array of elements are returned in the response buffer 620 * the first in the array is the header, remainder are elements 621 */ 622 struct i40e_aqc_get_switch_config_resp { 623 struct i40e_aqc_get_switch_config_header_resp header; 624 struct i40e_aqc_switch_config_element_resp element[1]; 625 }; 626 627 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 628 629 /* Add Statistics (direct 0x0201) 630 * Remove Statistics (direct 0x0202) 631 */ 632 struct i40e_aqc_add_remove_statistics { 633 __le16 seid; 634 __le16 vlan; 635 __le16 stat_index; 636 u8 reserved[10]; 637 }; 638 639 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 640 641 /* Set Port Parameters command (direct 0x0203) */ 642 struct i40e_aqc_set_port_parameters { 643 __le16 command_flags; 644 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 645 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 646 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 647 __le16 bad_frame_vsi; 648 __le16 default_seid; /* reserved for command */ 649 u8 reserved[10]; 650 }; 651 652 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 653 654 /* Get Switch Resource Allocation (indirect 0x0204) */ 655 struct i40e_aqc_get_switch_resource_alloc { 656 u8 num_entries; /* reserved for command */ 657 u8 reserved[7]; 658 __le32 addr_high; 659 __le32 addr_low; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 663 664 /* expect an array of these structs in the response buffer */ 665 struct i40e_aqc_switch_resource_alloc_element_resp { 666 u8 resource_type; 667 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 668 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 669 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 670 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 671 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 672 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 673 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 674 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 675 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 676 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 677 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 678 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 679 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 680 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 681 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 682 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 683 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 684 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 685 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 686 u8 reserved1; 687 __le16 guaranteed; 688 __le16 total; 689 __le16 used; 690 __le16 total_unalloced; 691 u8 reserved2[6]; 692 }; 693 694 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 695 696 /* Set Switch Configuration (direct 0x0205) */ 697 struct i40e_aqc_set_switch_config { 698 __le16 flags; 699 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 700 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 701 __le16 valid_flags; 702 u8 reserved[12]; 703 }; 704 705 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 706 707 /* Read Receive control registers (direct 0x0206) 708 * Write Receive control registers (direct 0x0207) 709 * used for accessing Rx control registers that can be 710 * slow and need special handling when under high Rx load 711 */ 712 struct i40e_aqc_rx_ctl_reg_read_write { 713 __le32 reserved1; 714 __le32 address; 715 __le32 reserved2; 716 __le32 value; 717 }; 718 719 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 720 721 /* Add VSI (indirect 0x0210) 722 * this indirect command uses struct i40e_aqc_vsi_properties_data 723 * as the indirect buffer (128 bytes) 724 * 725 * Update VSI (indirect 0x211) 726 * uses the same data structure as Add VSI 727 * 728 * Get VSI (indirect 0x0212) 729 * uses the same completion and data structure as Add VSI 730 */ 731 struct i40e_aqc_add_get_update_vsi { 732 __le16 uplink_seid; 733 u8 connection_type; 734 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 735 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 736 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 737 u8 reserved1; 738 u8 vf_id; 739 u8 reserved2; 740 __le16 vsi_flags; 741 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 742 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 743 #define I40E_AQ_VSI_TYPE_VF 0x0 744 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 745 #define I40E_AQ_VSI_TYPE_PF 0x2 746 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 747 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 748 __le32 addr_high; 749 __le32 addr_low; 750 }; 751 752 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 753 754 struct i40e_aqc_add_get_update_vsi_completion { 755 __le16 seid; 756 __le16 vsi_number; 757 __le16 vsi_used; 758 __le16 vsi_free; 759 __le32 addr_high; 760 __le32 addr_low; 761 }; 762 763 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 764 765 struct i40e_aqc_vsi_properties_data { 766 /* first 96 byte are written by SW */ 767 __le16 valid_sections; 768 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 769 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 770 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 771 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 772 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 773 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 774 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 775 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 776 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 777 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 778 /* switch section */ 779 __le16 switch_id; /* 12bit id combined with flags below */ 780 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 781 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 782 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 783 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 784 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 785 u8 sw_reserved[2]; 786 /* security section */ 787 u8 sec_flags; 788 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 789 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 790 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 791 u8 sec_reserved; 792 /* VLAN section */ 793 __le16 pvid; /* VLANS include priority bits */ 794 __le16 fcoe_pvid; 795 u8 port_vlan_flags; 796 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 797 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 798 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 799 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 800 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 801 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 802 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 803 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 804 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 805 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 806 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 807 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 808 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 809 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 810 u8 pvlan_reserved[3]; 811 /* ingress egress up sections */ 812 __le32 ingress_table; /* bitmap, 3 bits per up */ 813 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 814 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 815 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 816 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 817 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 818 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 819 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 820 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 821 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 822 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 823 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 824 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 825 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 826 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 827 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 828 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 829 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 830 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 831 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 832 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 833 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 834 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 835 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 836 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 837 __le32 egress_table; /* same defines as for ingress table */ 838 /* cascaded PV section */ 839 __le16 cas_pv_tag; 840 u8 cas_pv_flags; 841 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 842 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 843 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 844 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 845 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 846 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 847 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 848 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 849 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 850 u8 cas_pv_reserved; 851 /* queue mapping section */ 852 __le16 mapping_flags; 853 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 854 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 855 __le16 queue_mapping[16]; 856 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 857 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 858 __le16 tc_mapping[8]; 859 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 860 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 861 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 862 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 863 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 864 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 865 /* queueing option section */ 866 u8 queueing_opt_flags; 867 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 868 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 869 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 870 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 871 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 872 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 873 u8 queueing_opt_reserved[3]; 874 /* scheduler section */ 875 u8 up_enable_bits; 876 u8 sched_reserved; 877 /* outer up section */ 878 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 879 u8 cmd_reserved[8]; 880 /* last 32 bytes are written by FW */ 881 __le16 qs_handle[8]; 882 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 883 __le16 stat_counter_idx; 884 __le16 sched_id; 885 u8 resp_reserved[12]; 886 }; 887 888 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 889 890 /* Add Port Virtualizer (direct 0x0220) 891 * also used for update PV (direct 0x0221) but only flags are used 892 * (IS_CTRL_PORT only works on add PV) 893 */ 894 struct i40e_aqc_add_update_pv { 895 __le16 command_flags; 896 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 897 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 898 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 899 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 900 __le16 uplink_seid; 901 __le16 connected_seid; 902 u8 reserved[10]; 903 }; 904 905 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 906 907 struct i40e_aqc_add_update_pv_completion { 908 /* reserved for update; for add also encodes error if rc == ENOSPC */ 909 __le16 pv_seid; 910 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 911 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 912 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 913 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 914 u8 reserved[14]; 915 }; 916 917 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 918 919 /* Get PV Params (direct 0x0222) 920 * uses i40e_aqc_switch_seid for the descriptor 921 */ 922 923 struct i40e_aqc_get_pv_params_completion { 924 __le16 seid; 925 __le16 default_stag; 926 __le16 pv_flags; /* same flags as add_pv */ 927 #define I40E_AQC_GET_PV_PV_TYPE 0x1 928 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 929 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 930 u8 reserved[8]; 931 __le16 default_port_seid; 932 }; 933 934 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 935 936 /* Add VEB (direct 0x0230) */ 937 struct i40e_aqc_add_veb { 938 __le16 uplink_seid; 939 __le16 downlink_seid; 940 __le16 veb_flags; 941 #define I40E_AQC_ADD_VEB_FLOATING 0x1 942 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 943 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 944 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 945 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 946 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 947 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 948 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 949 u8 enable_tcs; 950 u8 reserved[9]; 951 }; 952 953 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 954 955 struct i40e_aqc_add_veb_completion { 956 u8 reserved[6]; 957 __le16 switch_seid; 958 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 959 __le16 veb_seid; 960 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 961 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 962 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 963 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 964 __le16 statistic_index; 965 __le16 vebs_used; 966 __le16 vebs_free; 967 }; 968 969 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 970 971 /* Get VEB Parameters (direct 0x0232) 972 * uses i40e_aqc_switch_seid for the descriptor 973 */ 974 struct i40e_aqc_get_veb_parameters_completion { 975 __le16 seid; 976 __le16 switch_id; 977 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 978 __le16 statistic_index; 979 __le16 vebs_used; 980 __le16 vebs_free; 981 u8 reserved[4]; 982 }; 983 984 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 985 986 /* Delete Element (direct 0x0243) 987 * uses the generic i40e_aqc_switch_seid 988 */ 989 990 /* Add MAC-VLAN (indirect 0x0250) */ 991 992 /* used for the command for most vlan commands */ 993 struct i40e_aqc_macvlan { 994 __le16 num_addresses; 995 __le16 seid[3]; 996 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 997 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 998 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 999 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1000 __le32 addr_high; 1001 __le32 addr_low; 1002 }; 1003 1004 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1005 1006 /* indirect data for command and response */ 1007 struct i40e_aqc_add_macvlan_element_data { 1008 u8 mac_addr[6]; 1009 __le16 vlan_tag; 1010 __le16 flags; 1011 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1012 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1013 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1014 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1015 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1016 __le16 queue_number; 1017 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1018 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1019 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1020 /* response section */ 1021 u8 match_method; 1022 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1023 #define I40E_AQC_MM_HASH_MATCH 0x02 1024 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1025 u8 reserved1[3]; 1026 }; 1027 1028 struct i40e_aqc_add_remove_macvlan_completion { 1029 __le16 perfect_mac_used; 1030 __le16 perfect_mac_free; 1031 __le16 unicast_hash_free; 1032 __le16 multicast_hash_free; 1033 __le32 addr_high; 1034 __le32 addr_low; 1035 }; 1036 1037 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1038 1039 /* Remove MAC-VLAN (indirect 0x0251) 1040 * uses i40e_aqc_macvlan for the descriptor 1041 * data points to an array of num_addresses of elements 1042 */ 1043 1044 struct i40e_aqc_remove_macvlan_element_data { 1045 u8 mac_addr[6]; 1046 __le16 vlan_tag; 1047 u8 flags; 1048 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1049 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1050 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1051 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1052 u8 reserved[3]; 1053 /* reply section */ 1054 u8 error_code; 1055 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1056 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1057 u8 reply_reserved[3]; 1058 }; 1059 1060 /* Add VLAN (indirect 0x0252) 1061 * Remove VLAN (indirect 0x0253) 1062 * use the generic i40e_aqc_macvlan for the command 1063 */ 1064 struct i40e_aqc_add_remove_vlan_element_data { 1065 __le16 vlan_tag; 1066 u8 vlan_flags; 1067 /* flags for add VLAN */ 1068 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1069 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1070 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1071 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1072 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1073 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1074 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1075 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1076 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1077 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1078 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1079 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1080 /* flags for remove VLAN */ 1081 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1082 u8 reserved; 1083 u8 result; 1084 /* flags for add VLAN */ 1085 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1086 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1087 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1088 /* flags for remove VLAN */ 1089 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1090 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1091 u8 reserved1[3]; 1092 }; 1093 1094 struct i40e_aqc_add_remove_vlan_completion { 1095 u8 reserved[4]; 1096 __le16 vlans_used; 1097 __le16 vlans_free; 1098 __le32 addr_high; 1099 __le32 addr_low; 1100 }; 1101 1102 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1103 struct i40e_aqc_set_vsi_promiscuous_modes { 1104 __le16 promiscuous_flags; 1105 __le16 valid_flags; 1106 /* flags used for both fields above */ 1107 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1108 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1109 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1110 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1111 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1112 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1113 __le16 seid; 1114 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1115 __le16 vlan_tag; 1116 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1117 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1118 u8 reserved[8]; 1119 }; 1120 1121 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1122 1123 /* Add S/E-tag command (direct 0x0255) 1124 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1125 */ 1126 struct i40e_aqc_add_tag { 1127 __le16 flags; 1128 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1129 __le16 seid; 1130 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1131 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1132 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1133 __le16 tag; 1134 __le16 queue_number; 1135 u8 reserved[8]; 1136 }; 1137 1138 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1139 1140 struct i40e_aqc_add_remove_tag_completion { 1141 u8 reserved[12]; 1142 __le16 tags_used; 1143 __le16 tags_free; 1144 }; 1145 1146 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1147 1148 /* Remove S/E-tag command (direct 0x0256) 1149 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1150 */ 1151 struct i40e_aqc_remove_tag { 1152 __le16 seid; 1153 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1154 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1155 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1156 __le16 tag; 1157 u8 reserved[12]; 1158 }; 1159 1160 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1161 1162 /* Add multicast E-Tag (direct 0x0257) 1163 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1164 * and no external data 1165 */ 1166 struct i40e_aqc_add_remove_mcast_etag { 1167 __le16 pv_seid; 1168 __le16 etag; 1169 u8 num_unicast_etags; 1170 u8 reserved[3]; 1171 __le32 addr_high; /* address of array of 2-byte s-tags */ 1172 __le32 addr_low; 1173 }; 1174 1175 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1176 1177 struct i40e_aqc_add_remove_mcast_etag_completion { 1178 u8 reserved[4]; 1179 __le16 mcast_etags_used; 1180 __le16 mcast_etags_free; 1181 __le32 addr_high; 1182 __le32 addr_low; 1183 1184 }; 1185 1186 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1187 1188 /* Update S/E-Tag (direct 0x0259) */ 1189 struct i40e_aqc_update_tag { 1190 __le16 seid; 1191 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1192 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1193 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1194 __le16 old_tag; 1195 __le16 new_tag; 1196 u8 reserved[10]; 1197 }; 1198 1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1200 1201 struct i40e_aqc_update_tag_completion { 1202 u8 reserved[12]; 1203 __le16 tags_used; 1204 __le16 tags_free; 1205 }; 1206 1207 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1208 1209 /* Add Control Packet filter (direct 0x025A) 1210 * Remove Control Packet filter (direct 0x025B) 1211 * uses the i40e_aqc_add_oveb_cloud, 1212 * and the generic direct completion structure 1213 */ 1214 struct i40e_aqc_add_remove_control_packet_filter { 1215 u8 mac[6]; 1216 __le16 etype; 1217 __le16 flags; 1218 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1219 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1220 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1221 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1222 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1223 __le16 seid; 1224 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1225 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1226 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1227 __le16 queue; 1228 u8 reserved[2]; 1229 }; 1230 1231 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1232 1233 struct i40e_aqc_add_remove_control_packet_filter_completion { 1234 __le16 mac_etype_used; 1235 __le16 etype_used; 1236 __le16 mac_etype_free; 1237 __le16 etype_free; 1238 u8 reserved[8]; 1239 }; 1240 1241 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1242 1243 /* Add Cloud filters (indirect 0x025C) 1244 * Remove Cloud filters (indirect 0x025D) 1245 * uses the i40e_aqc_add_remove_cloud_filters, 1246 * and the generic indirect completion structure 1247 */ 1248 struct i40e_aqc_add_remove_cloud_filters { 1249 u8 num_filters; 1250 u8 reserved; 1251 __le16 seid; 1252 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1253 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1254 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1255 u8 reserved2[4]; 1256 __le32 addr_high; 1257 __le32 addr_low; 1258 }; 1259 1260 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1261 1262 struct i40e_aqc_add_remove_cloud_filters_element_data { 1263 u8 outer_mac[6]; 1264 u8 inner_mac[6]; 1265 __le16 inner_vlan; 1266 union { 1267 struct { 1268 u8 reserved[12]; 1269 u8 data[4]; 1270 } v4; 1271 struct { 1272 u8 data[16]; 1273 } v6; 1274 } ipaddr; 1275 __le16 flags; 1276 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1277 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1278 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1279 /* 0x0000 reserved */ 1280 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1281 /* 0x0002 reserved */ 1282 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1283 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1284 /* 0x0005 reserved */ 1285 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1286 /* 0x0007 reserved */ 1287 /* 0x0008 reserved */ 1288 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1289 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1290 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1291 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1292 1293 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1294 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1295 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1296 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1297 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1298 1299 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1300 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1301 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1302 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1303 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1304 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1305 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1306 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1307 1308 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1309 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1310 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1311 1312 __le32 tenant_id; 1313 u8 reserved[4]; 1314 __le16 queue_number; 1315 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1316 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1317 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1318 u8 reserved2[14]; 1319 /* response section */ 1320 u8 allocation_result; 1321 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1322 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1323 u8 response_reserved[7]; 1324 }; 1325 1326 struct i40e_aqc_remove_cloud_filters_completion { 1327 __le16 perfect_ovlan_used; 1328 __le16 perfect_ovlan_free; 1329 __le16 vlan_used; 1330 __le16 vlan_free; 1331 __le32 addr_high; 1332 __le32 addr_low; 1333 }; 1334 1335 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1336 1337 /* Add Mirror Rule (indirect or direct 0x0260) 1338 * Delete Mirror Rule (indirect or direct 0x0261) 1339 * note: some rule types (4,5) do not use an external buffer. 1340 * take care to set the flags correctly. 1341 */ 1342 struct i40e_aqc_add_delete_mirror_rule { 1343 __le16 seid; 1344 __le16 rule_type; 1345 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1346 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1347 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1348 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1349 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1350 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1351 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1352 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1353 __le16 num_entries; 1354 __le16 destination; /* VSI for add, rule id for delete */ 1355 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1356 __le32 addr_low; 1357 }; 1358 1359 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1360 1361 struct i40e_aqc_add_delete_mirror_rule_completion { 1362 u8 reserved[2]; 1363 __le16 rule_id; /* only used on add */ 1364 __le16 mirror_rules_used; 1365 __le16 mirror_rules_free; 1366 __le32 addr_high; 1367 __le32 addr_low; 1368 }; 1369 1370 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1371 1372 /* DCB 0x03xx*/ 1373 1374 /* PFC Ignore (direct 0x0301) 1375 * the command and response use the same descriptor structure 1376 */ 1377 struct i40e_aqc_pfc_ignore { 1378 u8 tc_bitmap; 1379 u8 command_flags; /* unused on response */ 1380 #define I40E_AQC_PFC_IGNORE_SET 0x80 1381 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1382 u8 reserved[14]; 1383 }; 1384 1385 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1386 1387 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1388 * with no parameters 1389 */ 1390 1391 /* TX scheduler 0x04xx */ 1392 1393 /* Almost all the indirect commands use 1394 * this generic struct to pass the SEID in param0 1395 */ 1396 struct i40e_aqc_tx_sched_ind { 1397 __le16 vsi_seid; 1398 u8 reserved[6]; 1399 __le32 addr_high; 1400 __le32 addr_low; 1401 }; 1402 1403 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1404 1405 /* Several commands respond with a set of queue set handles */ 1406 struct i40e_aqc_qs_handles_resp { 1407 __le16 qs_handles[8]; 1408 }; 1409 1410 /* Configure VSI BW limits (direct 0x0400) */ 1411 struct i40e_aqc_configure_vsi_bw_limit { 1412 __le16 vsi_seid; 1413 u8 reserved[2]; 1414 __le16 credit; 1415 u8 reserved1[2]; 1416 u8 max_credit; /* 0-3, limit = 2^max */ 1417 u8 reserved2[7]; 1418 }; 1419 1420 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1421 1422 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1423 * responds with i40e_aqc_qs_handles_resp 1424 */ 1425 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1426 u8 tc_valid_bits; 1427 u8 reserved[15]; 1428 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1429 1430 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1431 __le16 tc_bw_max[2]; 1432 u8 reserved1[28]; 1433 }; 1434 1435 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1436 1437 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1438 * responds with i40e_aqc_qs_handles_resp 1439 */ 1440 struct i40e_aqc_configure_vsi_tc_bw_data { 1441 u8 tc_valid_bits; 1442 u8 reserved[3]; 1443 u8 tc_bw_credits[8]; 1444 u8 reserved1[4]; 1445 __le16 qs_handles[8]; 1446 }; 1447 1448 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1449 1450 /* Query vsi bw configuration (indirect 0x0408) */ 1451 struct i40e_aqc_query_vsi_bw_config_resp { 1452 u8 tc_valid_bits; 1453 u8 tc_suspended_bits; 1454 u8 reserved[14]; 1455 __le16 qs_handles[8]; 1456 u8 reserved1[4]; 1457 __le16 port_bw_limit; 1458 u8 reserved2[2]; 1459 u8 max_bw; /* 0-3, limit = 2^max */ 1460 u8 reserved3[23]; 1461 }; 1462 1463 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1464 1465 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1466 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1467 u8 tc_valid_bits; 1468 u8 reserved[3]; 1469 u8 share_credits[8]; 1470 __le16 credits[8]; 1471 1472 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1473 __le16 tc_bw_max[2]; 1474 }; 1475 1476 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1477 1478 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1479 struct i40e_aqc_configure_switching_comp_bw_limit { 1480 __le16 seid; 1481 u8 reserved[2]; 1482 __le16 credit; 1483 u8 reserved1[2]; 1484 u8 max_bw; /* 0-3, limit = 2^max */ 1485 u8 reserved2[7]; 1486 }; 1487 1488 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1489 1490 /* Enable Physical Port ETS (indirect 0x0413) 1491 * Modify Physical Port ETS (indirect 0x0414) 1492 * Disable Physical Port ETS (indirect 0x0415) 1493 */ 1494 struct i40e_aqc_configure_switching_comp_ets_data { 1495 u8 reserved[4]; 1496 u8 tc_valid_bits; 1497 u8 seepage; 1498 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1499 u8 tc_strict_priority_flags; 1500 u8 reserved1[17]; 1501 u8 tc_bw_share_credits[8]; 1502 u8 reserved2[96]; 1503 }; 1504 1505 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1506 1507 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1508 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1509 u8 tc_valid_bits; 1510 u8 reserved[15]; 1511 __le16 tc_bw_credit[8]; 1512 1513 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1514 __le16 tc_bw_max[2]; 1515 u8 reserved1[28]; 1516 }; 1517 1518 I40E_CHECK_STRUCT_LEN(0x40, 1519 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1520 1521 /* Configure Switching Component Bandwidth Allocation per Tc 1522 * (indirect 0x0417) 1523 */ 1524 struct i40e_aqc_configure_switching_comp_bw_config_data { 1525 u8 tc_valid_bits; 1526 u8 reserved[2]; 1527 u8 absolute_credits; /* bool */ 1528 u8 tc_bw_share_credits[8]; 1529 u8 reserved1[20]; 1530 }; 1531 1532 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1533 1534 /* Query Switching Component Configuration (indirect 0x0418) */ 1535 struct i40e_aqc_query_switching_comp_ets_config_resp { 1536 u8 tc_valid_bits; 1537 u8 reserved[35]; 1538 __le16 port_bw_limit; 1539 u8 reserved1[2]; 1540 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1541 u8 reserved2[23]; 1542 }; 1543 1544 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1545 1546 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1547 struct i40e_aqc_query_port_ets_config_resp { 1548 u8 reserved[4]; 1549 u8 tc_valid_bits; 1550 u8 reserved1; 1551 u8 tc_strict_priority_bits; 1552 u8 reserved2; 1553 u8 tc_bw_share_credits[8]; 1554 __le16 tc_bw_limits[8]; 1555 1556 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1557 __le16 tc_bw_max[2]; 1558 u8 reserved3[32]; 1559 }; 1560 1561 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1562 1563 /* Query Switching Component Bandwidth Allocation per Traffic Type 1564 * (indirect 0x041A) 1565 */ 1566 struct i40e_aqc_query_switching_comp_bw_config_resp { 1567 u8 tc_valid_bits; 1568 u8 reserved[2]; 1569 u8 absolute_credits_enable; /* bool */ 1570 u8 tc_bw_share_credits[8]; 1571 __le16 tc_bw_limits[8]; 1572 1573 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1574 __le16 tc_bw_max[2]; 1575 }; 1576 1577 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1578 1579 /* Suspend/resume port TX traffic 1580 * (direct 0x041B and 0x041C) uses the generic SEID struct 1581 */ 1582 1583 /* Configure partition BW 1584 * (indirect 0x041D) 1585 */ 1586 struct i40e_aqc_configure_partition_bw_data { 1587 __le16 pf_valid_bits; 1588 u8 min_bw[16]; /* guaranteed bandwidth */ 1589 u8 max_bw[16]; /* bandwidth limit */ 1590 }; 1591 1592 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1593 1594 /* Get and set the active HMC resource profile and status. 1595 * (direct 0x0500) and (direct 0x0501) 1596 */ 1597 struct i40e_aq_get_set_hmc_resource_profile { 1598 u8 pm_profile; 1599 u8 pe_vf_enabled; 1600 u8 reserved[14]; 1601 }; 1602 1603 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1604 1605 enum i40e_aq_hmc_profile { 1606 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1607 I40E_HMC_PROFILE_DEFAULT = 1, 1608 I40E_HMC_PROFILE_FAVOR_VF = 2, 1609 I40E_HMC_PROFILE_EQUAL = 3, 1610 }; 1611 1612 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1613 1614 /* set in param0 for get phy abilities to report qualified modules */ 1615 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1616 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1617 1618 enum i40e_aq_phy_type { 1619 I40E_PHY_TYPE_SGMII = 0x0, 1620 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1621 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1622 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1623 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1624 I40E_PHY_TYPE_XAUI = 0x5, 1625 I40E_PHY_TYPE_XFI = 0x6, 1626 I40E_PHY_TYPE_SFI = 0x7, 1627 I40E_PHY_TYPE_XLAUI = 0x8, 1628 I40E_PHY_TYPE_XLPPI = 0x9, 1629 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1630 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1631 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1632 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1633 I40E_PHY_TYPE_100BASE_TX = 0x11, 1634 I40E_PHY_TYPE_1000BASE_T = 0x12, 1635 I40E_PHY_TYPE_10GBASE_T = 0x13, 1636 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1637 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1638 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1639 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1640 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1641 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1642 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1643 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1644 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1645 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1646 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1647 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1648 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1649 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1650 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1651 I40E_PHY_TYPE_MAX 1652 }; 1653 1654 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1655 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1656 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1657 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1658 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1659 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1660 1661 enum i40e_aq_link_speed { 1662 I40E_LINK_SPEED_UNKNOWN = 0, 1663 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1664 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1665 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1666 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1667 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1668 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1669 }; 1670 1671 struct i40e_aqc_module_desc { 1672 u8 oui[3]; 1673 u8 reserved1; 1674 u8 part_number[16]; 1675 u8 revision[4]; 1676 u8 reserved2[8]; 1677 }; 1678 1679 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1680 1681 struct i40e_aq_get_phy_abilities_resp { 1682 __le32 phy_type; /* bitmap using the above enum for offsets */ 1683 u8 link_speed; /* bitmap using the above enum bit patterns */ 1684 u8 abilities; 1685 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1686 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1687 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1688 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1689 #define I40E_AQ_PHY_AN_ENABLED 0x10 1690 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1691 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1692 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1693 __le16 eee_capability; 1694 #define I40E_AQ_EEE_100BASE_TX 0x0002 1695 #define I40E_AQ_EEE_1000BASE_T 0x0004 1696 #define I40E_AQ_EEE_10GBASE_T 0x0008 1697 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1698 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1699 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1700 __le32 eeer_val; 1701 u8 d3_lpan; 1702 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1703 u8 phy_type_ext; 1704 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1705 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1706 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1707 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1708 u8 fec_cfg_curr_mod_ext_info; 1709 #define I40E_AQ_ENABLE_FEC_KR 0x01 1710 #define I40E_AQ_ENABLE_FEC_RS 0x02 1711 #define I40E_AQ_REQUEST_FEC_KR 0x04 1712 #define I40E_AQ_REQUEST_FEC_RS 0x08 1713 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1714 #define I40E_AQ_FEC 1715 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1716 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1717 1718 u8 ext_comp_code; 1719 u8 phy_id[4]; 1720 u8 module_type[3]; 1721 u8 qualified_module_count; 1722 #define I40E_AQ_PHY_MAX_QMS 16 1723 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1724 }; 1725 1726 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1727 1728 /* Set PHY Config (direct 0x0601) */ 1729 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1730 __le32 phy_type; 1731 u8 link_speed; 1732 u8 abilities; 1733 /* bits 0-2 use the values from get_phy_abilities_resp */ 1734 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1735 #define I40E_AQ_PHY_ENABLE_AN 0x10 1736 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1737 __le16 eee_capability; 1738 __le32 eeer; 1739 u8 low_power_ctrl; 1740 u8 phy_type_ext; 1741 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1742 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1743 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1744 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1745 u8 fec_config; 1746 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1747 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1748 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1749 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1750 #define I40E_AQ_SET_FEC_AUTO BIT(4) 1751 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1752 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1753 u8 reserved; 1754 }; 1755 1756 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1757 1758 /* Set MAC Config command data structure (direct 0x0603) */ 1759 struct i40e_aq_set_mac_config { 1760 __le16 max_frame_size; 1761 u8 params; 1762 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1763 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1764 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1765 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1766 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1767 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1768 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1769 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1770 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1771 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1772 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1773 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1774 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1775 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1776 u8 tx_timer_priority; /* bitmap */ 1777 __le16 tx_timer_value; 1778 __le16 fc_refresh_threshold; 1779 u8 reserved[8]; 1780 }; 1781 1782 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1783 1784 /* Restart Auto-Negotiation (direct 0x605) */ 1785 struct i40e_aqc_set_link_restart_an { 1786 u8 command; 1787 #define I40E_AQ_PHY_RESTART_AN 0x02 1788 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1789 u8 reserved[15]; 1790 }; 1791 1792 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1793 1794 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1795 struct i40e_aqc_get_link_status { 1796 __le16 command_flags; /* only field set on command */ 1797 #define I40E_AQ_LSE_MASK 0x3 1798 #define I40E_AQ_LSE_NOP 0x0 1799 #define I40E_AQ_LSE_DISABLE 0x2 1800 #define I40E_AQ_LSE_ENABLE 0x3 1801 /* only response uses this flag */ 1802 #define I40E_AQ_LSE_IS_ENABLED 0x1 1803 u8 phy_type; /* i40e_aq_phy_type */ 1804 u8 link_speed; /* i40e_aq_link_speed */ 1805 u8 link_info; 1806 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1807 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1808 #define I40E_AQ_LINK_FAULT 0x02 1809 #define I40E_AQ_LINK_FAULT_TX 0x04 1810 #define I40E_AQ_LINK_FAULT_RX 0x08 1811 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1812 #define I40E_AQ_LINK_UP_PORT 0x20 1813 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1814 #define I40E_AQ_SIGNAL_DETECT 0x80 1815 u8 an_info; 1816 #define I40E_AQ_AN_COMPLETED 0x01 1817 #define I40E_AQ_LP_AN_ABILITY 0x02 1818 #define I40E_AQ_PD_FAULT 0x04 1819 #define I40E_AQ_FEC_EN 0x08 1820 #define I40E_AQ_PHY_LOW_POWER 0x10 1821 #define I40E_AQ_LINK_PAUSE_TX 0x20 1822 #define I40E_AQ_LINK_PAUSE_RX 0x40 1823 #define I40E_AQ_QUALIFIED_MODULE 0x80 1824 u8 ext_info; 1825 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1826 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1827 #define I40E_AQ_LINK_TX_SHIFT 0x02 1828 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1829 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1830 #define I40E_AQ_LINK_TX_DRAINED 0x01 1831 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1832 #define I40E_AQ_LINK_FORCED_40G 0x10 1833 /* 25G Error Codes */ 1834 #define I40E_AQ_25G_NO_ERR 0X00 1835 #define I40E_AQ_25G_NOT_PRESENT 0X01 1836 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 1837 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1838 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1839 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1840 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1841 __le16 max_frame_size; 1842 u8 config; 1843 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1844 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 1845 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1846 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1847 u8 external_power_ability; 1848 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 1849 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 1850 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 1851 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 1852 u8 reserved[4]; 1853 }; 1854 1855 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1856 1857 /* Set event mask command (direct 0x613) */ 1858 struct i40e_aqc_set_phy_int_mask { 1859 u8 reserved[8]; 1860 __le16 event_mask; 1861 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1862 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1863 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1864 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1865 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1866 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1867 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1868 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1869 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1870 u8 reserved1[6]; 1871 }; 1872 1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1874 1875 /* Get Local AN advt register (direct 0x0614) 1876 * Set Local AN advt register (direct 0x0615) 1877 * Get Link Partner AN advt register (direct 0x0616) 1878 */ 1879 struct i40e_aqc_an_advt_reg { 1880 __le32 local_an_reg0; 1881 __le16 local_an_reg1; 1882 u8 reserved[10]; 1883 }; 1884 1885 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1886 1887 /* Set Loopback mode (0x0618) */ 1888 struct i40e_aqc_set_lb_mode { 1889 __le16 lb_mode; 1890 #define I40E_AQ_LB_PHY_LOCAL 0x01 1891 #define I40E_AQ_LB_PHY_REMOTE 0x02 1892 #define I40E_AQ_LB_MAC_LOCAL 0x04 1893 u8 reserved[14]; 1894 }; 1895 1896 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1897 1898 /* Set PHY Debug command (0x0622) */ 1899 struct i40e_aqc_set_phy_debug { 1900 u8 command_flags; 1901 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1902 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1903 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1904 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1905 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1906 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1907 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1908 /* Disable link manageability on a single port */ 1909 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1910 /* Disable link manageability on all ports */ 1911 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1912 u8 reserved[15]; 1913 }; 1914 1915 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1916 1917 enum i40e_aq_phy_reg_type { 1918 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1919 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1920 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1921 }; 1922 1923 /* Run PHY Activity (0x0626) */ 1924 struct i40e_aqc_run_phy_activity { 1925 __le16 activity_id; 1926 u8 flags; 1927 u8 reserved1; 1928 __le32 control; 1929 __le32 data; 1930 u8 reserved2[4]; 1931 }; 1932 1933 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1934 1935 /* NVM Read command (indirect 0x0701) 1936 * NVM Erase commands (direct 0x0702) 1937 * NVM Update commands (indirect 0x0703) 1938 */ 1939 struct i40e_aqc_nvm_update { 1940 u8 command_flags; 1941 #define I40E_AQ_NVM_LAST_CMD 0x01 1942 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1943 u8 module_pointer; 1944 __le16 length; 1945 __le32 offset; 1946 __le32 addr_high; 1947 __le32 addr_low; 1948 }; 1949 1950 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1951 1952 /* NVM Config Read (indirect 0x0704) */ 1953 struct i40e_aqc_nvm_config_read { 1954 __le16 cmd_flags; 1955 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1956 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1957 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1958 __le16 element_count; 1959 __le16 element_id; /* Feature/field ID */ 1960 __le16 element_id_msw; /* MSWord of field ID */ 1961 __le32 address_high; 1962 __le32 address_low; 1963 }; 1964 1965 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1966 1967 /* NVM Config Write (indirect 0x0705) */ 1968 struct i40e_aqc_nvm_config_write { 1969 __le16 cmd_flags; 1970 __le16 element_count; 1971 u8 reserved[4]; 1972 __le32 address_high; 1973 __le32 address_low; 1974 }; 1975 1976 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1977 1978 /* Used for 0x0704 as well as for 0x0705 commands */ 1979 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1980 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1981 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1982 #define I40E_AQ_ANVM_FEATURE 0 1983 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 1984 struct i40e_aqc_nvm_config_data_feature { 1985 __le16 feature_id; 1986 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1987 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1988 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1989 __le16 feature_options; 1990 __le16 feature_selection; 1991 }; 1992 1993 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1994 1995 struct i40e_aqc_nvm_config_data_immediate_field { 1996 __le32 field_id; 1997 __le32 field_value; 1998 __le16 field_options; 1999 __le16 reserved; 2000 }; 2001 2002 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2003 2004 /* OEM Post Update (indirect 0x0720) 2005 * no command data struct used 2006 */ 2007 struct i40e_aqc_nvm_oem_post_update { 2008 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2009 u8 sel_data; 2010 u8 reserved[7]; 2011 }; 2012 2013 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2014 2015 struct i40e_aqc_nvm_oem_post_update_buffer { 2016 u8 str_len; 2017 u8 dev_addr; 2018 __le16 eeprom_addr; 2019 u8 data[36]; 2020 }; 2021 2022 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2023 2024 /* Thermal Sensor (indirect 0x0721) 2025 * read or set thermal sensor configs and values 2026 * takes a sensor and command specific data buffer, not detailed here 2027 */ 2028 struct i40e_aqc_thermal_sensor { 2029 u8 sensor_action; 2030 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2031 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2032 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2033 u8 reserved[7]; 2034 __le32 addr_high; 2035 __le32 addr_low; 2036 }; 2037 2038 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2039 2040 /* Send to PF command (indirect 0x0801) id is only used by PF 2041 * Send to VF command (indirect 0x0802) id is only used by PF 2042 * Send to Peer PF command (indirect 0x0803) 2043 */ 2044 struct i40e_aqc_pf_vf_message { 2045 __le32 id; 2046 u8 reserved[4]; 2047 __le32 addr_high; 2048 __le32 addr_low; 2049 }; 2050 2051 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2052 2053 /* Alternate structure */ 2054 2055 /* Direct write (direct 0x0900) 2056 * Direct read (direct 0x0902) 2057 */ 2058 struct i40e_aqc_alternate_write { 2059 __le32 address0; 2060 __le32 data0; 2061 __le32 address1; 2062 __le32 data1; 2063 }; 2064 2065 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2066 2067 /* Indirect write (indirect 0x0901) 2068 * Indirect read (indirect 0x0903) 2069 */ 2070 2071 struct i40e_aqc_alternate_ind_write { 2072 __le32 address; 2073 __le32 length; 2074 __le32 addr_high; 2075 __le32 addr_low; 2076 }; 2077 2078 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2079 2080 /* Done alternate write (direct 0x0904) 2081 * uses i40e_aq_desc 2082 */ 2083 struct i40e_aqc_alternate_write_done { 2084 __le16 cmd_flags; 2085 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2086 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2087 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2088 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2089 u8 reserved[14]; 2090 }; 2091 2092 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2093 2094 /* Set OEM mode (direct 0x0905) */ 2095 struct i40e_aqc_alternate_set_mode { 2096 __le32 mode; 2097 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2098 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2099 u8 reserved[12]; 2100 }; 2101 2102 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2103 2104 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2105 2106 /* async events 0x10xx */ 2107 2108 /* Lan Queue Overflow Event (direct, 0x1001) */ 2109 struct i40e_aqc_lan_overflow { 2110 __le32 prtdcb_rupto; 2111 __le32 otx_ctl; 2112 u8 reserved[8]; 2113 }; 2114 2115 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2116 2117 /* Get LLDP MIB (indirect 0x0A00) */ 2118 struct i40e_aqc_lldp_get_mib { 2119 u8 type; 2120 u8 reserved1; 2121 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2122 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2123 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2124 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2125 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2126 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2127 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2128 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2129 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2130 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2131 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2132 __le16 local_len; 2133 __le16 remote_len; 2134 u8 reserved2[2]; 2135 __le32 addr_high; 2136 __le32 addr_low; 2137 }; 2138 2139 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2140 2141 /* Configure LLDP MIB Change Event (direct 0x0A01) 2142 * also used for the event (with type in the command field) 2143 */ 2144 struct i40e_aqc_lldp_update_mib { 2145 u8 command; 2146 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2147 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2148 u8 reserved[7]; 2149 __le32 addr_high; 2150 __le32 addr_low; 2151 }; 2152 2153 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2154 2155 /* Add LLDP TLV (indirect 0x0A02) 2156 * Delete LLDP TLV (indirect 0x0A04) 2157 */ 2158 struct i40e_aqc_lldp_add_tlv { 2159 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2160 u8 reserved1[1]; 2161 __le16 len; 2162 u8 reserved2[4]; 2163 __le32 addr_high; 2164 __le32 addr_low; 2165 }; 2166 2167 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2168 2169 /* Update LLDP TLV (indirect 0x0A03) */ 2170 struct i40e_aqc_lldp_update_tlv { 2171 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2172 u8 reserved; 2173 __le16 old_len; 2174 __le16 new_offset; 2175 __le16 new_len; 2176 __le32 addr_high; 2177 __le32 addr_low; 2178 }; 2179 2180 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2181 2182 /* Stop LLDP (direct 0x0A05) */ 2183 struct i40e_aqc_lldp_stop { 2184 u8 command; 2185 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2186 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2187 u8 reserved[15]; 2188 }; 2189 2190 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2191 2192 /* Start LLDP (direct 0x0A06) */ 2193 2194 struct i40e_aqc_lldp_start { 2195 u8 command; 2196 #define I40E_AQ_LLDP_AGENT_START 0x1 2197 u8 reserved[15]; 2198 }; 2199 2200 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2201 2202 /* Get CEE DCBX Oper Config (0x0A07) 2203 * uses the generic descriptor struct 2204 * returns below as indirect response 2205 */ 2206 2207 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2208 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2209 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2210 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2211 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2212 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2213 2214 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2215 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2216 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2217 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2218 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2219 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2220 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2221 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2222 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2223 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2224 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2225 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2226 2227 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2228 * word boundary layout issues, which the Linux compilers silently deal 2229 * with by adding padding, making the actual struct larger than designed. 2230 * However, the FW compiler for the NIC is less lenient and complains 2231 * about the struct. Hence, the struct defined here has an extra byte in 2232 * fields reserved3 and reserved4 to directly acknowledge that padding, 2233 * and the new length is used in the length check macro. 2234 */ 2235 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2236 u8 reserved1; 2237 u8 oper_num_tc; 2238 u8 oper_prio_tc[4]; 2239 u8 reserved2; 2240 u8 oper_tc_bw[8]; 2241 u8 oper_pfc_en; 2242 u8 reserved3[2]; 2243 __le16 oper_app_prio; 2244 u8 reserved4[2]; 2245 __le16 tlv_status; 2246 }; 2247 2248 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2249 2250 struct i40e_aqc_get_cee_dcb_cfg_resp { 2251 u8 oper_num_tc; 2252 u8 oper_prio_tc[4]; 2253 u8 oper_tc_bw[8]; 2254 u8 oper_pfc_en; 2255 __le16 oper_app_prio; 2256 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2257 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2258 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2259 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2260 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2261 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2262 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2263 __le32 tlv_status; 2264 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2265 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2266 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2267 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2268 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2269 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2270 u8 reserved[12]; 2271 }; 2272 2273 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2274 2275 /* Set Local LLDP MIB (indirect 0x0A08) 2276 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2277 */ 2278 struct i40e_aqc_lldp_set_local_mib { 2279 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2280 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2281 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2282 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2283 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2284 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2285 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2286 u8 type; 2287 u8 reserved0; 2288 __le16 length; 2289 u8 reserved1[4]; 2290 __le32 address_high; 2291 __le32 address_low; 2292 }; 2293 2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2295 2296 /* Stop/Start LLDP Agent (direct 0x0A09) 2297 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2298 */ 2299 struct i40e_aqc_lldp_stop_start_specific_agent { 2300 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2301 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2302 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2303 u8 command; 2304 u8 reserved[15]; 2305 }; 2306 2307 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2308 2309 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2310 struct i40e_aqc_add_udp_tunnel { 2311 __le16 udp_port; 2312 u8 reserved0[3]; 2313 u8 protocol_type; 2314 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2315 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2316 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2317 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2318 u8 reserved1[10]; 2319 }; 2320 2321 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2322 2323 struct i40e_aqc_add_udp_tunnel_completion { 2324 __le16 udp_port; 2325 u8 filter_entry_index; 2326 u8 multiple_pfs; 2327 #define I40E_AQC_SINGLE_PF 0x0 2328 #define I40E_AQC_MULTIPLE_PFS 0x1 2329 u8 total_filters; 2330 u8 reserved[11]; 2331 }; 2332 2333 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2334 2335 /* remove UDP Tunnel command (0x0B01) */ 2336 struct i40e_aqc_remove_udp_tunnel { 2337 u8 reserved[2]; 2338 u8 index; /* 0 to 15 */ 2339 u8 reserved2[13]; 2340 }; 2341 2342 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2343 2344 struct i40e_aqc_del_udp_tunnel_completion { 2345 __le16 udp_port; 2346 u8 index; /* 0 to 15 */ 2347 u8 multiple_pfs; 2348 u8 total_filters_used; 2349 u8 reserved1[11]; 2350 }; 2351 2352 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2353 2354 struct i40e_aqc_get_set_rss_key { 2355 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2356 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2357 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2358 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2359 __le16 vsi_id; 2360 u8 reserved[6]; 2361 __le32 addr_high; 2362 __le32 addr_low; 2363 }; 2364 2365 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2366 2367 struct i40e_aqc_get_set_rss_key_data { 2368 u8 standard_rss_key[0x28]; 2369 u8 extended_hash_key[0xc]; 2370 }; 2371 2372 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2373 2374 struct i40e_aqc_get_set_rss_lut { 2375 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2376 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2377 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2378 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2379 __le16 vsi_id; 2380 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2381 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2382 2383 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2384 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2385 __le16 flags; 2386 u8 reserved[4]; 2387 __le32 addr_high; 2388 __le32 addr_low; 2389 }; 2390 2391 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2392 2393 /* tunnel key structure 0x0B10 */ 2394 2395 struct i40e_aqc_tunnel_key_structure { 2396 u8 key1_off; 2397 u8 key2_off; 2398 u8 key1_len; /* 0 to 15 */ 2399 u8 key2_len; /* 0 to 15 */ 2400 u8 flags; 2401 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2402 /* response flags */ 2403 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2404 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2405 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2406 u8 network_key_index; 2407 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2408 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2409 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2410 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2411 u8 reserved[10]; 2412 }; 2413 2414 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2415 2416 /* OEM mode commands (direct 0xFE0x) */ 2417 struct i40e_aqc_oem_param_change { 2418 __le32 param_type; 2419 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2420 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2421 #define I40E_AQ_OEM_PARAM_MAC 2 2422 __le32 param_value1; 2423 __le16 param_value2; 2424 u8 reserved[6]; 2425 }; 2426 2427 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2428 2429 struct i40e_aqc_oem_state_change { 2430 __le32 state; 2431 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2432 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2433 u8 reserved[12]; 2434 }; 2435 2436 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2437 2438 /* Initialize OCSD (0xFE02, direct) */ 2439 struct i40e_aqc_opc_oem_ocsd_initialize { 2440 u8 type_status; 2441 u8 reserved1[3]; 2442 __le32 ocsd_memory_block_addr_high; 2443 __le32 ocsd_memory_block_addr_low; 2444 __le32 requested_update_interval; 2445 }; 2446 2447 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2448 2449 /* Initialize OCBB (0xFE03, direct) */ 2450 struct i40e_aqc_opc_oem_ocbb_initialize { 2451 u8 type_status; 2452 u8 reserved1[3]; 2453 __le32 ocbb_memory_block_addr_high; 2454 __le32 ocbb_memory_block_addr_low; 2455 u8 reserved2[4]; 2456 }; 2457 2458 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2459 2460 /* debug commands */ 2461 2462 /* get device id (0xFF00) uses the generic structure */ 2463 2464 /* set test more (0xFF01, internal) */ 2465 2466 struct i40e_acq_set_test_mode { 2467 u8 mode; 2468 #define I40E_AQ_TEST_PARTIAL 0 2469 #define I40E_AQ_TEST_FULL 1 2470 #define I40E_AQ_TEST_NVM 2 2471 u8 reserved[3]; 2472 u8 command; 2473 #define I40E_AQ_TEST_OPEN 0 2474 #define I40E_AQ_TEST_CLOSE 1 2475 #define I40E_AQ_TEST_INC 2 2476 u8 reserved2[3]; 2477 __le32 address_high; 2478 __le32 address_low; 2479 }; 2480 2481 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2482 2483 /* Debug Read Register command (0xFF03) 2484 * Debug Write Register command (0xFF04) 2485 */ 2486 struct i40e_aqc_debug_reg_read_write { 2487 __le32 reserved; 2488 __le32 address; 2489 __le32 value_high; 2490 __le32 value_low; 2491 }; 2492 2493 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2494 2495 /* Scatter/gather Reg Read (indirect 0xFF05) 2496 * Scatter/gather Reg Write (indirect 0xFF06) 2497 */ 2498 2499 /* i40e_aq_desc is used for the command */ 2500 struct i40e_aqc_debug_reg_sg_element_data { 2501 __le32 address; 2502 __le32 value; 2503 }; 2504 2505 /* Debug Modify register (direct 0xFF07) */ 2506 struct i40e_aqc_debug_modify_reg { 2507 __le32 address; 2508 __le32 value; 2509 __le32 clear_mask; 2510 __le32 set_mask; 2511 }; 2512 2513 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2514 2515 /* dump internal data (0xFF08, indirect) */ 2516 2517 #define I40E_AQ_CLUSTER_ID_AUX 0 2518 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2519 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2520 #define I40E_AQ_CLUSTER_ID_HMC 3 2521 #define I40E_AQ_CLUSTER_ID_MAC0 4 2522 #define I40E_AQ_CLUSTER_ID_MAC1 5 2523 #define I40E_AQ_CLUSTER_ID_MAC2 6 2524 #define I40E_AQ_CLUSTER_ID_MAC3 7 2525 #define I40E_AQ_CLUSTER_ID_DCB 8 2526 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2527 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2528 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2529 2530 struct i40e_aqc_debug_dump_internals { 2531 u8 cluster_id; 2532 u8 table_id; 2533 __le16 data_size; 2534 __le32 idx; 2535 __le32 address_high; 2536 __le32 address_low; 2537 }; 2538 2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2540 2541 struct i40e_aqc_debug_modify_internals { 2542 u8 cluster_id; 2543 u8 cluster_specific_params[7]; 2544 __le32 address_high; 2545 __le32 address_low; 2546 }; 2547 2548 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2549 2550 #endif /* _I40E_ADMINQ_CMD_H_ */ 2551