1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 * 22 * Contact Information: 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * 26 ******************************************************************************/ 27 28 #ifndef _I40E_ADMINQ_CMD_H_ 29 #define _I40E_ADMINQ_CMD_H_ 30 31 /* This header file defines the i40e Admin Queue commands and is shared between 32 * i40e Firmware and Software. 33 * 34 * This file needs to comply with the Linux Kernel coding style. 35 */ 36 37 #define I40E_FW_API_VERSION_MAJOR 0x0001 38 #define I40E_FW_API_VERSION_MINOR 0x0000 39 40 struct i40e_aq_desc { 41 __le16 flags; 42 __le16 opcode; 43 __le16 datalen; 44 __le16 retval; 45 __le32 cookie_high; 46 __le32 cookie_low; 47 union { 48 struct { 49 __le32 param0; 50 __le32 param1; 51 __le32 param2; 52 __le32 param3; 53 } internal; 54 struct { 55 __le32 param0; 56 __le32 param1; 57 __le32 addr_high; 58 __le32 addr_low; 59 } external; 60 u8 raw[16]; 61 } params; 62 }; 63 64 /* Flags sub-structure 65 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 66 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 67 */ 68 69 /* command flags and offsets*/ 70 #define I40E_AQ_FLAG_DD_SHIFT 0 71 #define I40E_AQ_FLAG_CMP_SHIFT 1 72 #define I40E_AQ_FLAG_ERR_SHIFT 2 73 #define I40E_AQ_FLAG_VFE_SHIFT 3 74 #define I40E_AQ_FLAG_LB_SHIFT 9 75 #define I40E_AQ_FLAG_RD_SHIFT 10 76 #define I40E_AQ_FLAG_VFC_SHIFT 11 77 #define I40E_AQ_FLAG_BUF_SHIFT 12 78 #define I40E_AQ_FLAG_SI_SHIFT 13 79 #define I40E_AQ_FLAG_EI_SHIFT 14 80 #define I40E_AQ_FLAG_FE_SHIFT 15 81 82 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 83 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 84 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 85 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 86 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 87 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 88 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 89 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 90 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 91 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 92 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 93 94 /* error codes */ 95 enum i40e_admin_queue_err { 96 I40E_AQ_RC_OK = 0, /* success */ 97 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 98 I40E_AQ_RC_ENOENT = 2, /* No such element */ 99 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 100 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 101 I40E_AQ_RC_EIO = 5, /* I/O error */ 102 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 103 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 104 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 105 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 106 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 107 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 108 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 109 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 110 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 111 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 112 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 113 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 114 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 115 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */ 116 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 117 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 118 I40E_AQ_RC_EFBIG = 22, /* File too large */ 119 }; 120 121 /* Admin Queue command opcodes */ 122 enum i40e_admin_queue_opc { 123 /* aq commands */ 124 i40e_aqc_opc_get_version = 0x0001, 125 i40e_aqc_opc_driver_version = 0x0002, 126 i40e_aqc_opc_queue_shutdown = 0x0003, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 i40e_aqc_opc_set_cppm_configuration = 0x0103, 136 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 137 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 138 139 /* LAA */ 140 i40e_aqc_opc_mng_laa = 0x0106, 141 i40e_aqc_opc_mac_address_read = 0x0107, 142 i40e_aqc_opc_mac_address_write = 0x0108, 143 144 /* internal switch commands */ 145 i40e_aqc_opc_get_switch_config = 0x0200, 146 i40e_aqc_opc_add_statistics = 0x0201, 147 i40e_aqc_opc_remove_statistics = 0x0202, 148 i40e_aqc_opc_set_port_parameters = 0x0203, 149 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 150 151 i40e_aqc_opc_add_vsi = 0x0210, 152 i40e_aqc_opc_update_vsi_parameters = 0x0211, 153 i40e_aqc_opc_get_vsi_parameters = 0x0212, 154 155 i40e_aqc_opc_add_pv = 0x0220, 156 i40e_aqc_opc_update_pv_parameters = 0x0221, 157 i40e_aqc_opc_get_pv_parameters = 0x0222, 158 159 i40e_aqc_opc_add_veb = 0x0230, 160 i40e_aqc_opc_update_veb_parameters = 0x0231, 161 i40e_aqc_opc_get_veb_parameters = 0x0232, 162 163 i40e_aqc_opc_delete_element = 0x0243, 164 165 i40e_aqc_opc_add_macvlan = 0x0250, 166 i40e_aqc_opc_remove_macvlan = 0x0251, 167 i40e_aqc_opc_add_vlan = 0x0252, 168 i40e_aqc_opc_remove_vlan = 0x0253, 169 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 170 i40e_aqc_opc_add_tag = 0x0255, 171 i40e_aqc_opc_remove_tag = 0x0256, 172 i40e_aqc_opc_add_multicast_etag = 0x0257, 173 i40e_aqc_opc_remove_multicast_etag = 0x0258, 174 i40e_aqc_opc_update_tag = 0x0259, 175 i40e_aqc_opc_add_control_packet_filter = 0x025A, 176 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 177 i40e_aqc_opc_add_cloud_filters = 0x025C, 178 i40e_aqc_opc_remove_cloud_filters = 0x025D, 179 180 i40e_aqc_opc_add_mirror_rule = 0x0260, 181 i40e_aqc_opc_delete_mirror_rule = 0x0261, 182 183 i40e_aqc_opc_set_storm_control_config = 0x0280, 184 i40e_aqc_opc_get_storm_control_config = 0x0281, 185 186 /* DCB commands */ 187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 188 i40e_aqc_opc_dcb_updated = 0x0302, 189 190 /* TX scheduler */ 191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 194 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 197 198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 204 i40e_aqc_opc_query_port_ets_config = 0x0419, 205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 206 i40e_aqc_opc_suspend_port_tx = 0x041B, 207 i40e_aqc_opc_resume_port_tx = 0x041C, 208 209 /* hmc */ 210 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 211 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 212 213 /* phy commands*/ 214 i40e_aqc_opc_get_phy_abilities = 0x0600, 215 i40e_aqc_opc_set_phy_config = 0x0601, 216 i40e_aqc_opc_set_mac_config = 0x0603, 217 i40e_aqc_opc_set_link_restart_an = 0x0605, 218 i40e_aqc_opc_get_link_status = 0x0607, 219 i40e_aqc_opc_set_phy_int_mask = 0x0613, 220 i40e_aqc_opc_get_local_advt_reg = 0x0614, 221 i40e_aqc_opc_set_local_advt_reg = 0x0615, 222 i40e_aqc_opc_get_partner_advt = 0x0616, 223 i40e_aqc_opc_set_lb_modes = 0x0618, 224 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 225 i40e_aqc_opc_set_phy_reset = 0x0622, 226 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 227 228 /* NVM commands */ 229 i40e_aqc_opc_nvm_read = 0x0701, 230 i40e_aqc_opc_nvm_erase = 0x0702, 231 i40e_aqc_opc_nvm_update = 0x0703, 232 233 /* virtualization commands */ 234 i40e_aqc_opc_send_msg_to_pf = 0x0801, 235 i40e_aqc_opc_send_msg_to_vf = 0x0802, 236 i40e_aqc_opc_send_msg_to_peer = 0x0803, 237 238 /* alternate structure */ 239 i40e_aqc_opc_alternate_write = 0x0900, 240 i40e_aqc_opc_alternate_write_indirect = 0x0901, 241 i40e_aqc_opc_alternate_read = 0x0902, 242 i40e_aqc_opc_alternate_read_indirect = 0x0903, 243 i40e_aqc_opc_alternate_write_done = 0x0904, 244 i40e_aqc_opc_alternate_set_mode = 0x0905, 245 i40e_aqc_opc_alternate_clear_port = 0x0906, 246 247 /* LLDP commands */ 248 i40e_aqc_opc_lldp_get_mib = 0x0A00, 249 i40e_aqc_opc_lldp_update_mib = 0x0A01, 250 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 251 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 253 i40e_aqc_opc_lldp_stop = 0x0A05, 254 i40e_aqc_opc_lldp_start = 0x0A06, 255 256 /* Tunnel commands */ 257 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 258 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 259 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 260 261 /* Async Events */ 262 i40e_aqc_opc_event_lan_overflow = 0x1001, 263 264 /* OEM commands */ 265 i40e_aqc_opc_oem_parameter_change = 0xFE00, 266 i40e_aqc_opc_oem_device_status_change = 0xFE01, 267 268 /* debug commands */ 269 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 270 i40e_aqc_opc_debug_set_mode = 0xFF01, 271 i40e_aqc_opc_debug_read_reg = 0xFF03, 272 i40e_aqc_opc_debug_write_reg = 0xFF04, 273 i40e_aqc_opc_debug_read_reg_sg = 0xFF05, 274 i40e_aqc_opc_debug_write_reg_sg = 0xFF06, 275 i40e_aqc_opc_debug_modify_reg = 0xFF07, 276 i40e_aqc_opc_debug_dump_internals = 0xFF08, 277 i40e_aqc_opc_debug_modify_internals = 0xFF09, 278 }; 279 280 /* command structures and indirect data structures */ 281 282 /* Structure naming conventions: 283 * - no suffix for direct command descriptor structures 284 * - _data for indirect sent data 285 * - _resp for indirect return data (data which is both will use _data) 286 * - _completion for direct return data 287 * - _element_ for repeated elements (may also be _data or _resp) 288 * 289 * Command structures are expected to overlay the params.raw member of the basic 290 * descriptor, and as such cannot exceed 16 bytes in length. 291 */ 292 293 /* This macro is used to generate a compilation error if a structure 294 * is not exactly the correct length. It gives a divide by zero error if the 295 * structure is not of the correct size, otherwise it creates an enum that is 296 * never used. 297 */ 298 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 300 301 /* This macro is used extensively to ensure that command structures are 16 302 * bytes in length as they have to map to the raw array of that size. 303 */ 304 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 305 306 /* internal (0x00XX) commands */ 307 308 /* Get version (direct 0x0001) */ 309 struct i40e_aqc_get_version { 310 __le32 rom_ver; 311 __le32 fw_build; 312 __le16 fw_major; 313 __le16 fw_minor; 314 __le16 api_major; 315 __le16 api_minor; 316 }; 317 318 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 319 320 /* Send driver version (direct 0x0002) */ 321 struct i40e_aqc_driver_version { 322 u8 driver_major_ver; 323 u8 driver_minor_ver; 324 u8 driver_build_ver; 325 u8 driver_subbuild_ver; 326 u8 reserved[12]; 327 }; 328 329 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 330 331 /* Queue Shutdown (direct 0x0003) */ 332 struct i40e_aqc_queue_shutdown { 333 __le32 driver_unloading; 334 #define I40E_AQ_DRIVER_UNLOADING 0x1 335 u8 reserved[12]; 336 }; 337 338 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 339 340 /* Request resource ownership (direct 0x0008) 341 * Release resource ownership (direct 0x0009) 342 */ 343 #define I40E_AQ_RESOURCE_NVM 1 344 #define I40E_AQ_RESOURCE_SDP 2 345 #define I40E_AQ_RESOURCE_ACCESS_READ 1 346 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 347 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 348 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 349 350 struct i40e_aqc_request_resource { 351 __le16 resource_id; 352 __le16 access_type; 353 __le32 timeout; 354 __le32 resource_number; 355 u8 reserved[4]; 356 }; 357 358 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 359 360 /* Get function capabilities (indirect 0x000A) 361 * Get device capabilities (indirect 0x000B) 362 */ 363 struct i40e_aqc_list_capabilites { 364 u8 command_flags; 365 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 366 u8 pf_index; 367 u8 reserved[2]; 368 __le32 count; 369 __le32 addr_high; 370 __le32 addr_low; 371 }; 372 373 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 374 375 struct i40e_aqc_list_capabilities_element_resp { 376 __le16 id; 377 u8 major_rev; 378 u8 minor_rev; 379 __le32 number; 380 __le32 logical_id; 381 __le32 phys_id; 382 u8 reserved[16]; 383 }; 384 385 /* list of caps */ 386 387 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 388 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 389 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 390 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 391 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 392 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 393 #define I40E_AQ_CAP_ID_SRIOV 0x0012 394 #define I40E_AQ_CAP_ID_VF 0x0013 395 #define I40E_AQ_CAP_ID_VMDQ 0x0014 396 #define I40E_AQ_CAP_ID_8021QBG 0x0015 397 #define I40E_AQ_CAP_ID_8021QBR 0x0016 398 #define I40E_AQ_CAP_ID_VSI 0x0017 399 #define I40E_AQ_CAP_ID_DCB 0x0018 400 #define I40E_AQ_CAP_ID_FCOE 0x0021 401 #define I40E_AQ_CAP_ID_RSS 0x0040 402 #define I40E_AQ_CAP_ID_RXQ 0x0041 403 #define I40E_AQ_CAP_ID_TXQ 0x0042 404 #define I40E_AQ_CAP_ID_MSIX 0x0043 405 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 406 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 407 #define I40E_AQ_CAP_ID_1588 0x0046 408 #define I40E_AQ_CAP_ID_IWARP 0x0051 409 #define I40E_AQ_CAP_ID_LED 0x0061 410 #define I40E_AQ_CAP_ID_SDP 0x0062 411 #define I40E_AQ_CAP_ID_MDIO 0x0063 412 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 413 #define I40E_AQ_CAP_ID_CEM 0x00F2 414 415 /* Set CPPM Configuration (direct 0x0103) */ 416 struct i40e_aqc_cppm_configuration { 417 __le16 command_flags; 418 #define I40E_AQ_CPPM_EN_LTRC 0x0800 419 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 420 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 421 #define I40E_AQ_CPPM_EN_HPTC 0x4000 422 #define I40E_AQ_CPPM_EN_DMARC 0x8000 423 __le16 ttlx; 424 __le32 dmacr; 425 __le16 dmcth; 426 u8 hptc; 427 u8 reserved; 428 __le32 pfltrc; 429 }; 430 431 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 432 433 /* Set ARP Proxy command / response (indirect 0x0104) */ 434 struct i40e_aqc_arp_proxy_data { 435 __le16 command_flags; 436 #define I40E_AQ_ARP_INIT_IPV4 0x0008 437 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 438 #define I40E_AQ_ARP_ENA 0x0020 439 #define I40E_AQ_ARP_ADD_IPV4 0x0040 440 #define I40E_AQ_ARP_DEL_IPV4 0x0080 441 __le16 table_id; 442 __le32 pfpm_proxyfc; 443 __le32 ip_addr; 444 u8 mac_addr[6]; 445 }; 446 447 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 448 struct i40e_aqc_ns_proxy_data { 449 __le16 table_idx_mac_addr_0; 450 __le16 table_idx_mac_addr_1; 451 __le16 table_idx_ipv6_0; 452 __le16 table_idx_ipv6_1; 453 __le16 control; 454 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 455 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 456 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 457 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 458 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 459 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 460 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 461 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 462 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 463 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 464 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 465 u8 mac_addr_0[6]; 466 u8 mac_addr_1[6]; 467 u8 local_mac_addr[6]; 468 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 469 u8 ipv6_addr_1[16]; 470 }; 471 472 /* Manage LAA Command (0x0106) - obsolete */ 473 struct i40e_aqc_mng_laa { 474 __le16 command_flags; 475 #define I40E_AQ_LAA_FLAG_WR 0x8000 476 u8 reserved[2]; 477 __le32 sal; 478 __le16 sah; 479 u8 reserved2[6]; 480 }; 481 482 /* Manage MAC Address Read Command (0x0107) */ 483 struct i40e_aqc_mac_address_read { 484 __le16 command_flags; 485 #define I40E_AQC_LAN_ADDR_VALID 0x10 486 #define I40E_AQC_SAN_ADDR_VALID 0x20 487 #define I40E_AQC_PORT_ADDR_VALID 0x40 488 #define I40E_AQC_WOL_ADDR_VALID 0x80 489 #define I40E_AQC_ADDR_VALID_MASK 0xf0 490 u8 reserved[6]; 491 __le32 addr_high; 492 __le32 addr_low; 493 }; 494 495 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 496 497 struct i40e_aqc_mac_address_read_data { 498 u8 pf_lan_mac[6]; 499 u8 pf_san_mac[6]; 500 u8 port_mac[6]; 501 u8 pf_wol_mac[6]; 502 }; 503 504 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 505 506 /* Manage MAC Address Write Command (0x0108) */ 507 struct i40e_aqc_mac_address_write { 508 __le16 command_flags; 509 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 510 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 511 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 512 #define I40E_AQC_WRITE_TYPE_MASK 0xc000 513 __le16 mac_sah; 514 __le32 mac_sal; 515 u8 reserved[8]; 516 }; 517 518 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 519 520 /* Switch configuration commands (0x02xx) */ 521 522 /* Used by many indirect commands that only pass an seid and a buffer in the 523 * command 524 */ 525 struct i40e_aqc_switch_seid { 526 __le16 seid; 527 u8 reserved[6]; 528 __le32 addr_high; 529 __le32 addr_low; 530 }; 531 532 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 533 534 /* Get Switch Configuration command (indirect 0x0200) 535 * uses i40e_aqc_switch_seid for the descriptor 536 */ 537 struct i40e_aqc_get_switch_config_header_resp { 538 __le16 num_reported; 539 __le16 num_total; 540 u8 reserved[12]; 541 }; 542 543 struct i40e_aqc_switch_config_element_resp { 544 u8 element_type; 545 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 546 #define I40E_AQ_SW_ELEM_TYPE_PF 2 547 #define I40E_AQ_SW_ELEM_TYPE_VF 3 548 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 549 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 550 #define I40E_AQ_SW_ELEM_TYPE_PV 16 551 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 552 #define I40E_AQ_SW_ELEM_TYPE_PA 18 553 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 554 u8 revision; 555 #define I40E_AQ_SW_ELEM_REV_1 1 556 __le16 seid; 557 __le16 uplink_seid; 558 __le16 downlink_seid; 559 u8 reserved[3]; 560 u8 connection_type; 561 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 562 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 563 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 564 __le16 scheduler_id; 565 __le16 element_info; 566 }; 567 568 /* Get Switch Configuration (indirect 0x0200) 569 * an array of elements are returned in the response buffer 570 * the first in the array is the header, remainder are elements 571 */ 572 struct i40e_aqc_get_switch_config_resp { 573 struct i40e_aqc_get_switch_config_header_resp header; 574 struct i40e_aqc_switch_config_element_resp element[1]; 575 }; 576 577 /* Add Statistics (direct 0x0201) 578 * Remove Statistics (direct 0x0202) 579 */ 580 struct i40e_aqc_add_remove_statistics { 581 __le16 seid; 582 __le16 vlan; 583 __le16 stat_index; 584 u8 reserved[10]; 585 }; 586 587 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 588 589 /* Set Port Parameters command (direct 0x0203) */ 590 struct i40e_aqc_set_port_parameters { 591 __le16 command_flags; 592 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 593 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 594 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 595 __le16 bad_frame_vsi; 596 __le16 default_seid; /* reserved for command */ 597 u8 reserved[10]; 598 }; 599 600 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 601 602 /* Get Switch Resource Allocation (indirect 0x0204) */ 603 struct i40e_aqc_get_switch_resource_alloc { 604 u8 num_entries; /* reserved for command */ 605 u8 reserved[7]; 606 __le32 addr_high; 607 __le32 addr_low; 608 }; 609 610 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 611 612 /* expect an array of these structs in the response buffer */ 613 struct i40e_aqc_switch_resource_alloc_element_resp { 614 u8 resource_type; 615 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 616 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 617 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 618 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 619 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 620 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 621 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 622 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 623 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 624 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 625 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 626 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 627 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 628 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 629 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 630 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 631 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 632 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 633 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 634 u8 reserved1; 635 __le16 guaranteed; 636 __le16 total; 637 __le16 used; 638 __le16 total_unalloced; 639 u8 reserved2[6]; 640 }; 641 642 /* Add VSI (indirect 0x210) 643 * this indirect command uses struct i40e_aqc_vsi_properties_data 644 * as the indirect buffer (128 bytes) 645 * 646 * Update VSI (indirect 0x211) Get VSI (indirect 0x0212) 647 * use the generic i40e_aqc_switch_seid descriptor format 648 * use the same completion and data structure as Add VSI 649 */ 650 struct i40e_aqc_add_get_update_vsi { 651 __le16 uplink_seid; 652 u8 connection_type; 653 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 654 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 655 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 656 u8 reserved1; 657 u8 vf_id; 658 u8 reserved2; 659 __le16 vsi_flags; 660 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 661 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 662 #define I40E_AQ_VSI_TYPE_VF 0x0 663 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 664 #define I40E_AQ_VSI_TYPE_PF 0x2 665 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 666 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 667 #define I40E_AQ_VSI_FLAG_CLOUD_VSI 0x8 668 __le32 addr_high; 669 __le32 addr_low; 670 }; 671 672 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 673 674 struct i40e_aqc_add_get_update_vsi_completion { 675 __le16 seid; 676 __le16 vsi_number; 677 __le16 vsi_used; 678 __le16 vsi_free; 679 __le32 addr_high; 680 __le32 addr_low; 681 }; 682 683 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 684 685 struct i40e_aqc_vsi_properties_data { 686 /* first 96 byte are written by SW */ 687 __le16 valid_sections; 688 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 689 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 690 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 691 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 692 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 693 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 694 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 695 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 696 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 697 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 698 /* switch section */ 699 __le16 switch_id; /* 12bit id combined with flags below */ 700 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 701 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 702 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 703 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 704 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 705 u8 sw_reserved[2]; 706 /* security section */ 707 u8 sec_flags; 708 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 709 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 710 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 711 u8 sec_reserved; 712 /* VLAN section */ 713 __le16 pvid; /* VLANS include priority bits */ 714 __le16 fcoe_pvid; 715 u8 port_vlan_flags; 716 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 717 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 718 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 719 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 720 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 721 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 722 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 723 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 724 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 725 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 726 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 727 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 728 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 729 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 730 u8 pvlan_reserved[3]; 731 /* ingress egress up sections */ 732 __le32 ingress_table; /* bitmap, 3 bits per up */ 733 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 734 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 735 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 736 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 737 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 738 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 739 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 740 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 741 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 742 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 743 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 744 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 745 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 746 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 747 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 748 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 749 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 750 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 751 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 752 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 753 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 754 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 755 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 756 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 757 __le32 egress_table; /* same defines as for ingress table */ 758 /* cascaded PV section */ 759 __le16 cas_pv_tag; 760 u8 cas_pv_flags; 761 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 762 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 763 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 764 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 765 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 766 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 767 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 768 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 769 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 770 u8 cas_pv_reserved; 771 /* queue mapping section */ 772 __le16 mapping_flags; 773 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 774 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 775 __le16 queue_mapping[16]; 776 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 777 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 778 __le16 tc_mapping[8]; 779 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 780 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 781 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 782 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 783 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 784 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 785 /* queueing option section */ 786 u8 queueing_opt_flags; 787 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 788 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 789 u8 queueing_opt_reserved[3]; 790 /* scheduler section */ 791 u8 up_enable_bits; 792 u8 sched_reserved; 793 /* outer up section */ 794 __le32 outer_up_table; /* same structure and defines as ingress table */ 795 u8 cmd_reserved[8]; 796 /* last 32 bytes are written by FW */ 797 __le16 qs_handle[8]; 798 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 799 __le16 stat_counter_idx; 800 __le16 sched_id; 801 u8 resp_reserved[12]; 802 }; 803 804 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 805 806 /* Add Port Virtualizer (direct 0x0220) 807 * also used for update PV (direct 0x0221) but only flags are used 808 * (IS_CTRL_PORT only works on add PV) 809 */ 810 struct i40e_aqc_add_update_pv { 811 __le16 command_flags; 812 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 813 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 814 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 815 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 816 __le16 uplink_seid; 817 __le16 connected_seid; 818 u8 reserved[10]; 819 }; 820 821 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 822 823 struct i40e_aqc_add_update_pv_completion { 824 /* reserved for update; for add also encodes error if rc == ENOSPC */ 825 __le16 pv_seid; 826 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 827 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 828 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 829 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 830 u8 reserved[14]; 831 }; 832 833 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 834 835 /* Get PV Params (direct 0x0222) 836 * uses i40e_aqc_switch_seid for the descriptor 837 */ 838 839 struct i40e_aqc_get_pv_params_completion { 840 __le16 seid; 841 __le16 default_stag; 842 __le16 pv_flags; /* same flags as add_pv */ 843 #define I40E_AQC_GET_PV_PV_TYPE 0x1 844 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 845 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 846 u8 reserved[8]; 847 __le16 default_port_seid; 848 }; 849 850 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 851 852 /* Add VEB (direct 0x0230) */ 853 struct i40e_aqc_add_veb { 854 __le16 uplink_seid; 855 __le16 downlink_seid; 856 __le16 veb_flags; 857 #define I40E_AQC_ADD_VEB_FLOATING 0x1 858 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 859 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 860 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 861 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 862 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 863 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 864 u8 enable_tcs; 865 u8 reserved[9]; 866 }; 867 868 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 869 870 struct i40e_aqc_add_veb_completion { 871 u8 reserved[6]; 872 __le16 switch_seid; 873 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 874 __le16 veb_seid; 875 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 876 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 877 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 878 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 879 __le16 statistic_index; 880 __le16 vebs_used; 881 __le16 vebs_free; 882 }; 883 884 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 885 886 /* Get VEB Parameters (direct 0x0232) 887 * uses i40e_aqc_switch_seid for the descriptor 888 */ 889 struct i40e_aqc_get_veb_parameters_completion { 890 __le16 seid; 891 __le16 switch_id; 892 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 893 __le16 statistic_index; 894 __le16 vebs_used; 895 __le16 vebs_free; 896 u8 reserved[4]; 897 }; 898 899 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 900 901 /* Delete Element (direct 0x0243) 902 * uses the generic i40e_aqc_switch_seid 903 */ 904 905 /* Add MAC-VLAN (indirect 0x0250) */ 906 907 /* used for the command for most vlan commands */ 908 struct i40e_aqc_macvlan { 909 __le16 num_addresses; 910 __le16 seid[3]; 911 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 912 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 913 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 914 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 915 __le32 addr_high; 916 __le32 addr_low; 917 }; 918 919 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 920 921 /* indirect data for command and response */ 922 struct i40e_aqc_add_macvlan_element_data { 923 u8 mac_addr[6]; 924 __le16 vlan_tag; 925 __le16 flags; 926 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 927 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 928 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 929 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 930 __le16 queue_number; 931 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 932 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 933 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 934 /* response section */ 935 u8 match_method; 936 #define I40E_AQC_MM_PERFECT_MATCH 0x01 937 #define I40E_AQC_MM_HASH_MATCH 0x02 938 #define I40E_AQC_MM_ERR_NO_RES 0xFF 939 u8 reserved1[3]; 940 }; 941 942 struct i40e_aqc_add_remove_macvlan_completion { 943 __le16 perfect_mac_used; 944 __le16 perfect_mac_free; 945 __le16 unicast_hash_free; 946 __le16 multicast_hash_free; 947 __le32 addr_high; 948 __le32 addr_low; 949 }; 950 951 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 952 953 /* Remove MAC-VLAN (indirect 0x0251) 954 * uses i40e_aqc_macvlan for the descriptor 955 * data points to an array of num_addresses of elements 956 */ 957 958 struct i40e_aqc_remove_macvlan_element_data { 959 u8 mac_addr[6]; 960 __le16 vlan_tag; 961 u8 flags; 962 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 963 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 964 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 965 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 966 u8 reserved[3]; 967 /* reply section */ 968 u8 error_code; 969 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 970 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 971 u8 reply_reserved[3]; 972 }; 973 974 /* Add VLAN (indirect 0x0252) 975 * Remove VLAN (indirect 0x0253) 976 * use the generic i40e_aqc_macvlan for the command 977 */ 978 struct i40e_aqc_add_remove_vlan_element_data { 979 __le16 vlan_tag; 980 u8 vlan_flags; 981 /* flags for add VLAN */ 982 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 983 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 984 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \ 985 I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 986 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 987 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 988 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 989 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 990 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 991 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 992 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 993 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 994 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 995 /* flags for remove VLAN */ 996 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 997 u8 reserved; 998 u8 result; 999 /* flags for add VLAN */ 1000 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1001 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1002 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1003 /* flags for remove VLAN */ 1004 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1005 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1006 u8 reserved1[3]; 1007 }; 1008 1009 struct i40e_aqc_add_remove_vlan_completion { 1010 u8 reserved[4]; 1011 __le16 vlans_used; 1012 __le16 vlans_free; 1013 __le32 addr_high; 1014 __le32 addr_low; 1015 }; 1016 1017 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1018 struct i40e_aqc_set_vsi_promiscuous_modes { 1019 __le16 promiscuous_flags; 1020 __le16 valid_flags; 1021 /* flags used for both fields above */ 1022 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1023 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1024 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1025 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1026 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1027 __le16 seid; 1028 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1029 u8 reserved[10]; 1030 }; 1031 1032 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1033 1034 /* Add S/E-tag command (direct 0x0255) 1035 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1036 */ 1037 struct i40e_aqc_add_tag { 1038 __le16 flags; 1039 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1040 __le16 seid; 1041 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1042 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1043 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1044 __le16 tag; 1045 __le16 queue_number; 1046 u8 reserved[8]; 1047 }; 1048 1049 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1050 1051 struct i40e_aqc_add_remove_tag_completion { 1052 u8 reserved[12]; 1053 __le16 tags_used; 1054 __le16 tags_free; 1055 }; 1056 1057 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1058 1059 /* Remove S/E-tag command (direct 0x0256) 1060 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1061 */ 1062 struct i40e_aqc_remove_tag { 1063 __le16 seid; 1064 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1065 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1066 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1067 __le16 tag; 1068 u8 reserved[12]; 1069 }; 1070 1071 /* Add multicast E-Tag (direct 0x0257) 1072 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1073 * and no external data 1074 */ 1075 struct i40e_aqc_add_remove_mcast_etag { 1076 __le16 pv_seid; 1077 __le16 etag; 1078 u8 num_unicast_etags; 1079 u8 reserved[3]; 1080 __le32 addr_high; /* address of array of 2-byte s-tags */ 1081 __le32 addr_low; 1082 }; 1083 1084 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1085 1086 struct i40e_aqc_add_remove_mcast_etag_completion { 1087 u8 reserved[4]; 1088 __le16 mcast_etags_used; 1089 __le16 mcast_etags_free; 1090 __le32 addr_high; 1091 __le32 addr_low; 1092 1093 }; 1094 1095 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1096 1097 /* Update S/E-Tag (direct 0x0259) */ 1098 struct i40e_aqc_update_tag { 1099 __le16 seid; 1100 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1101 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1102 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1103 __le16 old_tag; 1104 __le16 new_tag; 1105 u8 reserved[10]; 1106 }; 1107 1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1109 1110 struct i40e_aqc_update_tag_completion { 1111 u8 reserved[12]; 1112 __le16 tags_used; 1113 __le16 tags_free; 1114 }; 1115 1116 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1117 1118 /* Add Control Packet filter (direct 0x025A) 1119 * Remove Control Packet filter (direct 0x025B) 1120 * uses the i40e_aqc_add_oveb_cloud, 1121 * and the generic direct completion structure 1122 */ 1123 struct i40e_aqc_add_remove_control_packet_filter { 1124 u8 mac[6]; 1125 __le16 etype; 1126 __le16 flags; 1127 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1128 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1129 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1130 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1131 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1132 __le16 seid; 1133 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1134 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1135 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1136 __le16 queue; 1137 u8 reserved[2]; 1138 }; 1139 1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1141 1142 struct i40e_aqc_add_remove_control_packet_filter_completion { 1143 __le16 mac_etype_used; 1144 __le16 etype_used; 1145 __le16 mac_etype_free; 1146 __le16 etype_free; 1147 u8 reserved[8]; 1148 }; 1149 1150 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1151 1152 /* Add Cloud filters (indirect 0x025C) 1153 * Remove Cloud filters (indirect 0x025D) 1154 * uses the i40e_aqc_add_remove_cloud_filters, 1155 * and the generic indirect completion structure 1156 */ 1157 struct i40e_aqc_add_remove_cloud_filters { 1158 u8 num_filters; 1159 u8 reserved; 1160 __le16 seid; 1161 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1162 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1163 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1164 u8 reserved2[4]; 1165 __le32 addr_high; 1166 __le32 addr_low; 1167 }; 1168 1169 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1170 1171 struct i40e_aqc_add_remove_cloud_filters_element_data { 1172 u8 outer_mac[6]; 1173 u8 inner_mac[6]; 1174 __le16 inner_vlan; 1175 union { 1176 struct { 1177 u8 reserved[12]; 1178 u8 data[4]; 1179 } v4; 1180 struct { 1181 u8 data[16]; 1182 } v6; 1183 } ipaddr; 1184 __le16 flags; 1185 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1186 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1187 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1188 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1189 #define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002 1190 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1191 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004 1192 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1193 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007 1194 /* 0x0008 reserved */ 1195 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1196 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1197 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1198 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1199 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1200 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1201 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1202 __le32 key_low; 1203 __le32 key_high; 1204 __le16 queue_number; 1205 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1206 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1207 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1208 u8 reserved[14]; 1209 /* response section */ 1210 u8 allocation_result; 1211 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1212 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1213 u8 response_reserved[7]; 1214 }; 1215 1216 struct i40e_aqc_remove_cloud_filters_completion { 1217 __le16 perfect_ovlan_used; 1218 __le16 perfect_ovlan_free; 1219 __le16 vlan_used; 1220 __le16 vlan_free; 1221 __le32 addr_high; 1222 __le32 addr_low; 1223 }; 1224 1225 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1226 1227 /* Add Mirror Rule (indirect or direct 0x0260) 1228 * Delete Mirror Rule (indirect or direct 0x0261) 1229 * note: some rule types (4,5) do not use an external buffer. 1230 * take care to set the flags correctly. 1231 */ 1232 struct i40e_aqc_add_delete_mirror_rule { 1233 __le16 seid; 1234 __le16 rule_type; 1235 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1236 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1237 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1238 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1239 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1240 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1241 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1242 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1243 __le16 num_entries; 1244 __le16 destination; /* VSI for add, rule id for delete */ 1245 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1246 __le32 addr_low; 1247 }; 1248 1249 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1250 1251 struct i40e_aqc_add_delete_mirror_rule_completion { 1252 u8 reserved[2]; 1253 __le16 rule_id; /* only used on add */ 1254 __le16 mirror_rules_used; 1255 __le16 mirror_rules_free; 1256 __le32 addr_high; 1257 __le32 addr_low; 1258 }; 1259 1260 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1261 1262 /* Set Storm Control Configuration (direct 0x0280) 1263 * Get Storm Control Configuration (direct 0x0281) 1264 * the command and response use the same descriptor structure 1265 */ 1266 struct i40e_aqc_set_get_storm_control_config { 1267 __le32 broadcast_threshold; 1268 __le32 multicast_threshold; 1269 __le32 control_flags; 1270 #define I40E_AQC_STORM_CONTROL_MDIPW 0x01 1271 #define I40E_AQC_STORM_CONTROL_MDICW 0x02 1272 #define I40E_AQC_STORM_CONTROL_BDIPW 0x04 1273 #define I40E_AQC_STORM_CONTROL_BDICW 0x08 1274 #define I40E_AQC_STORM_CONTROL_BIDU 0x10 1275 #define I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT 8 1276 #define I40E_AQC_STORM_CONTROL_INTERVAL_MASK (0x3FF << \ 1277 I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT) 1278 u8 reserved[4]; 1279 }; 1280 1281 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_get_storm_control_config); 1282 1283 /* DCB 0x03xx*/ 1284 1285 /* PFC Ignore (direct 0x0301) 1286 * the command and response use the same descriptor structure 1287 */ 1288 struct i40e_aqc_pfc_ignore { 1289 u8 tc_bitmap; 1290 u8 command_flags; /* unused on response */ 1291 #define I40E_AQC_PFC_IGNORE_SET 0x80 1292 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1293 u8 reserved[14]; 1294 }; 1295 1296 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1297 1298 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1299 * with no parameters 1300 */ 1301 1302 /* TX scheduler 0x04xx */ 1303 1304 /* Almost all the indirect commands use 1305 * this generic struct to pass the SEID in param0 1306 */ 1307 struct i40e_aqc_tx_sched_ind { 1308 __le16 vsi_seid; 1309 u8 reserved[6]; 1310 __le32 addr_high; 1311 __le32 addr_low; 1312 }; 1313 1314 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1315 1316 /* Several commands respond with a set of queue set handles */ 1317 struct i40e_aqc_qs_handles_resp { 1318 __le16 qs_handles[8]; 1319 }; 1320 1321 /* Configure VSI BW limits (direct 0x0400) */ 1322 struct i40e_aqc_configure_vsi_bw_limit { 1323 __le16 vsi_seid; 1324 u8 reserved[2]; 1325 __le16 credit; 1326 u8 reserved1[2]; 1327 u8 max_credit; /* 0-3, limit = 2^max */ 1328 u8 reserved2[7]; 1329 }; 1330 1331 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1332 1333 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1334 * responds with i40e_aqc_qs_handles_resp 1335 */ 1336 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1337 u8 tc_valid_bits; 1338 u8 reserved[15]; 1339 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1340 1341 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1342 __le16 tc_bw_max[2]; 1343 u8 reserved1[28]; 1344 }; 1345 1346 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1347 * responds with i40e_aqc_qs_handles_resp 1348 */ 1349 struct i40e_aqc_configure_vsi_tc_bw_data { 1350 u8 tc_valid_bits; 1351 u8 reserved[3]; 1352 u8 tc_bw_credits[8]; 1353 u8 reserved1[4]; 1354 __le16 qs_handles[8]; 1355 }; 1356 1357 /* Query vsi bw configuration (indirect 0x0408) */ 1358 struct i40e_aqc_query_vsi_bw_config_resp { 1359 u8 tc_valid_bits; 1360 u8 tc_suspended_bits; 1361 u8 reserved[14]; 1362 __le16 qs_handles[8]; 1363 u8 reserved1[4]; 1364 __le16 port_bw_limit; 1365 u8 reserved2[2]; 1366 u8 max_bw; /* 0-3, limit = 2^max */ 1367 u8 reserved3[23]; 1368 }; 1369 1370 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1371 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1372 u8 tc_valid_bits; 1373 u8 reserved[3]; 1374 u8 share_credits[8]; 1375 __le16 credits[8]; 1376 1377 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1378 __le16 tc_bw_max[2]; 1379 }; 1380 1381 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1382 struct i40e_aqc_configure_switching_comp_bw_limit { 1383 __le16 seid; 1384 u8 reserved[2]; 1385 __le16 credit; 1386 u8 reserved1[2]; 1387 u8 max_bw; /* 0-3, limit = 2^max */ 1388 u8 reserved2[7]; 1389 }; 1390 1391 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1392 1393 /* Enable Physical Port ETS (indirect 0x0413) 1394 * Modify Physical Port ETS (indirect 0x0414) 1395 * Disable Physical Port ETS (indirect 0x0415) 1396 */ 1397 struct i40e_aqc_configure_switching_comp_ets_data { 1398 u8 reserved[4]; 1399 u8 tc_valid_bits; 1400 u8 reserved1; 1401 u8 tc_strict_priority_flags; 1402 u8 reserved2[17]; 1403 u8 tc_bw_share_credits[8]; 1404 u8 reserved3[96]; 1405 }; 1406 1407 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1408 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1409 u8 tc_valid_bits; 1410 u8 reserved[15]; 1411 __le16 tc_bw_credit[8]; 1412 1413 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1414 __le16 tc_bw_max[2]; 1415 u8 reserved1[28]; 1416 }; 1417 1418 /* Configure Switching Component Bandwidth Allocation per Tc 1419 * (indirect 0x0417) 1420 */ 1421 struct i40e_aqc_configure_switching_comp_bw_config_data { 1422 u8 tc_valid_bits; 1423 u8 reserved[2]; 1424 u8 absolute_credits; /* bool */ 1425 u8 tc_bw_share_credits[8]; 1426 u8 reserved1[20]; 1427 }; 1428 1429 /* Query Switching Component Configuration (indirect 0x0418) */ 1430 struct i40e_aqc_query_switching_comp_ets_config_resp { 1431 u8 tc_valid_bits; 1432 u8 reserved[35]; 1433 __le16 port_bw_limit; 1434 u8 reserved1[2]; 1435 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1436 u8 reserved2[23]; 1437 }; 1438 1439 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1440 struct i40e_aqc_query_port_ets_config_resp { 1441 u8 reserved[4]; 1442 u8 tc_valid_bits; 1443 u8 reserved1; 1444 u8 tc_strict_priority_bits; 1445 u8 reserved2; 1446 u8 tc_bw_share_credits[8]; 1447 __le16 tc_bw_limits[8]; 1448 1449 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1450 __le16 tc_bw_max[2]; 1451 u8 reserved3[32]; 1452 }; 1453 1454 /* Query Switching Component Bandwidth Allocation per Traffic Type 1455 * (indirect 0x041A) 1456 */ 1457 struct i40e_aqc_query_switching_comp_bw_config_resp { 1458 u8 tc_valid_bits; 1459 u8 reserved[2]; 1460 u8 absolute_credits_enable; /* bool */ 1461 u8 tc_bw_share_credits[8]; 1462 __le16 tc_bw_limits[8]; 1463 1464 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1465 __le16 tc_bw_max[2]; 1466 }; 1467 1468 /* Suspend/resume port TX traffic 1469 * (direct 0x041B and 0x041C) uses the generic SEID struct 1470 */ 1471 1472 /* Get and set the active HMC resource profile and status. 1473 * (direct 0x0500) and (direct 0x0501) 1474 */ 1475 struct i40e_aq_get_set_hmc_resource_profile { 1476 u8 pm_profile; 1477 u8 pe_vf_enabled; 1478 u8 reserved[14]; 1479 }; 1480 1481 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1482 1483 enum i40e_aq_hmc_profile { 1484 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1485 I40E_HMC_PROFILE_DEFAULT = 1, 1486 I40E_HMC_PROFILE_FAVOR_VF = 2, 1487 I40E_HMC_PROFILE_EQUAL = 3, 1488 }; 1489 1490 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1491 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1492 1493 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1494 1495 /* set in param0 for get phy abilities to report qualified modules */ 1496 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1497 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1498 1499 enum i40e_aq_phy_type { 1500 I40E_PHY_TYPE_SGMII = 0x0, 1501 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1502 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1503 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1504 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1505 I40E_PHY_TYPE_XAUI = 0x5, 1506 I40E_PHY_TYPE_XFI = 0x6, 1507 I40E_PHY_TYPE_SFI = 0x7, 1508 I40E_PHY_TYPE_XLAUI = 0x8, 1509 I40E_PHY_TYPE_XLPPI = 0x9, 1510 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1511 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1512 I40E_PHY_TYPE_100BASE_TX = 0x11, 1513 I40E_PHY_TYPE_1000BASE_T = 0x12, 1514 I40E_PHY_TYPE_10GBASE_T = 0x13, 1515 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1516 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1517 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1518 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1519 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1520 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1521 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1522 I40E_PHY_TYPE_20GBASE_KR2 = 0x1B, 1523 I40E_PHY_TYPE_MAX 1524 }; 1525 1526 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1527 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1528 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1529 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1530 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1531 1532 enum i40e_aq_link_speed { 1533 I40E_LINK_SPEED_UNKNOWN = 0, 1534 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1535 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1536 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1537 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1538 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1539 }; 1540 1541 struct i40e_aqc_module_desc { 1542 u8 oui[3]; 1543 u8 reserved1; 1544 u8 part_number[16]; 1545 u8 revision[4]; 1546 u8 reserved2[8]; 1547 }; 1548 1549 struct i40e_aq_get_phy_abilities_resp { 1550 __le32 phy_type; /* bitmap using the above enum for offsets */ 1551 u8 link_speed; /* bitmap using the above enum */ 1552 u8 abilities; 1553 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1554 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1555 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1556 #define I40E_AQ_PHY_FLAG_AN_SHIFT 3 1557 #define I40E_AQ_PHY_FLAG_AN_MASK (0x3 << I40E_AQ_PHY_FLAG_AN_SHIFT) 1558 #define I40E_AQ_PHY_FLAG_AN_OFF 0x00 /* link forced on */ 1559 #define I40E_AQ_PHY_FLAG_AN_OFF_LINK_DOWN 0x01 1560 #define I40E_AQ_PHY_FLAG_AN_ON 0x02 1561 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1562 __le16 eee_capability; 1563 #define I40E_AQ_EEE_100BASE_TX 0x0002 1564 #define I40E_AQ_EEE_1000BASE_T 0x0004 1565 #define I40E_AQ_EEE_10GBASE_T 0x0008 1566 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1567 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1568 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1569 __le32 eeer_val; 1570 u8 d3_lpan; 1571 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1572 u8 reserved[3]; 1573 u8 phy_id[4]; 1574 u8 module_type[3]; 1575 u8 qualified_module_count; 1576 #define I40E_AQ_PHY_MAX_QMS 16 1577 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1578 }; 1579 1580 /* Set PHY Config (direct 0x0601) */ 1581 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1582 __le32 phy_type; 1583 u8 link_speed; 1584 u8 abilities; 1585 __le16 eee_capability; 1586 __le32 eeer; 1587 u8 low_power_ctrl; 1588 u8 reserved[3]; 1589 }; 1590 1591 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1592 1593 /* Set MAC Config command data structure (direct 0x0603) */ 1594 struct i40e_aq_set_mac_config { 1595 __le16 max_frame_size; 1596 u8 params; 1597 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1598 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1599 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1600 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1601 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1602 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1603 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1604 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1605 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1606 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1607 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1608 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1609 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1610 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1611 u8 tx_timer_priority; /* bitmap */ 1612 __le16 tx_timer_value; 1613 __le16 fc_refresh_threshold; 1614 u8 reserved[8]; 1615 }; 1616 1617 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1618 1619 /* Restart Auto-Negotiation (direct 0x605) */ 1620 struct i40e_aqc_set_link_restart_an { 1621 u8 command; 1622 #define I40E_AQ_PHY_RESTART_AN 0x02 1623 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1624 u8 reserved[15]; 1625 }; 1626 1627 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1628 1629 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1630 struct i40e_aqc_get_link_status { 1631 __le16 command_flags; /* only field set on command */ 1632 #define I40E_AQ_LSE_MASK 0x3 1633 #define I40E_AQ_LSE_NOP 0x0 1634 #define I40E_AQ_LSE_DISABLE 0x2 1635 #define I40E_AQ_LSE_ENABLE 0x3 1636 /* only response uses this flag */ 1637 #define I40E_AQ_LSE_IS_ENABLED 0x1 1638 u8 phy_type; /* i40e_aq_phy_type */ 1639 u8 link_speed; /* i40e_aq_link_speed */ 1640 u8 link_info; 1641 #define I40E_AQ_LINK_UP 0x01 1642 #define I40E_AQ_LINK_FAULT 0x02 1643 #define I40E_AQ_LINK_FAULT_TX 0x04 1644 #define I40E_AQ_LINK_FAULT_RX 0x08 1645 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1646 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1647 #define I40E_AQ_SIGNAL_DETECT 0x80 1648 u8 an_info; 1649 #define I40E_AQ_AN_COMPLETED 0x01 1650 #define I40E_AQ_LP_AN_ABILITY 0x02 1651 #define I40E_AQ_PD_FAULT 0x04 1652 #define I40E_AQ_FEC_EN 0x08 1653 #define I40E_AQ_PHY_LOW_POWER 0x10 1654 #define I40E_AQ_LINK_PAUSE_TX 0x20 1655 #define I40E_AQ_LINK_PAUSE_RX 0x40 1656 #define I40E_AQ_QUALIFIED_MODULE 0x80 1657 u8 ext_info; 1658 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1659 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1660 #define I40E_AQ_LINK_TX_SHIFT 0x02 1661 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1662 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1663 #define I40E_AQ_LINK_TX_DRAINED 0x01 1664 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1665 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1666 __le16 max_frame_size; 1667 u8 config; 1668 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1669 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1670 u8 reserved[5]; 1671 }; 1672 1673 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1674 1675 /* Set event mask command (direct 0x613) */ 1676 struct i40e_aqc_set_phy_int_mask { 1677 u8 reserved[8]; 1678 __le16 event_mask; 1679 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1680 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1681 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1682 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1683 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1684 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1685 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1686 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1687 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1688 u8 reserved1[6]; 1689 }; 1690 1691 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1692 1693 /* Get Local AN advt register (direct 0x0614) 1694 * Set Local AN advt register (direct 0x0615) 1695 * Get Link Partner AN advt register (direct 0x0616) 1696 */ 1697 struct i40e_aqc_an_advt_reg { 1698 __le32 local_an_reg0; 1699 __le16 local_an_reg1; 1700 u8 reserved[10]; 1701 }; 1702 1703 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1704 1705 /* Set Loopback mode (0x0618) */ 1706 struct i40e_aqc_set_lb_mode { 1707 __le16 lb_mode; 1708 #define I40E_AQ_LB_PHY_LOCAL 0x01 1709 #define I40E_AQ_LB_PHY_REMOTE 0x02 1710 #define I40E_AQ_LB_MAC_LOCAL 0x04 1711 u8 reserved[14]; 1712 }; 1713 1714 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1715 1716 /* Set PHY Reset command (0x0622) */ 1717 struct i40e_aqc_set_phy_reset { 1718 u8 reset_flags; 1719 #define I40E_AQ_PHY_RESET_REQUEST 0x02 1720 u8 reserved[15]; 1721 }; 1722 1723 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset); 1724 1725 enum i40e_aq_phy_reg_type { 1726 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1727 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1728 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1729 }; 1730 1731 /* NVM Read command (indirect 0x0701) 1732 * NVM Erase commands (direct 0x0702) 1733 * NVM Update commands (indirect 0x0703) 1734 */ 1735 struct i40e_aqc_nvm_update { 1736 u8 command_flags; 1737 #define I40E_AQ_NVM_LAST_CMD 0x01 1738 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1739 u8 module_pointer; 1740 __le16 length; 1741 __le32 offset; 1742 __le32 addr_high; 1743 __le32 addr_low; 1744 }; 1745 1746 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1747 1748 /* Send to PF command (indirect 0x0801) id is only used by PF 1749 * Send to VF command (indirect 0x0802) id is only used by PF 1750 * Send to Peer PF command (indirect 0x0803) 1751 */ 1752 struct i40e_aqc_pf_vf_message { 1753 __le32 id; 1754 u8 reserved[4]; 1755 __le32 addr_high; 1756 __le32 addr_low; 1757 }; 1758 1759 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1760 1761 /* Alternate structure */ 1762 1763 /* Direct write (direct 0x0900) 1764 * Direct read (direct 0x0902) 1765 */ 1766 struct i40e_aqc_alternate_write { 1767 __le32 address0; 1768 __le32 data0; 1769 __le32 address1; 1770 __le32 data1; 1771 }; 1772 1773 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1774 1775 /* Indirect write (indirect 0x0901) 1776 * Indirect read (indirect 0x0903) 1777 */ 1778 1779 struct i40e_aqc_alternate_ind_write { 1780 __le32 address; 1781 __le32 length; 1782 __le32 addr_high; 1783 __le32 addr_low; 1784 }; 1785 1786 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1787 1788 /* Done alternate write (direct 0x0904) 1789 * uses i40e_aq_desc 1790 */ 1791 struct i40e_aqc_alternate_write_done { 1792 __le16 cmd_flags; 1793 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1794 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1795 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1796 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1797 u8 reserved[14]; 1798 }; 1799 1800 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1801 1802 /* Set OEM mode (direct 0x0905) */ 1803 struct i40e_aqc_alternate_set_mode { 1804 __le32 mode; 1805 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1806 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1807 u8 reserved[12]; 1808 }; 1809 1810 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1811 1812 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1813 1814 /* async events 0x10xx */ 1815 1816 /* Lan Queue Overflow Event (direct, 0x1001) */ 1817 struct i40e_aqc_lan_overflow { 1818 __le32 prtdcb_rupto; 1819 __le32 otx_ctl; 1820 u8 reserved[8]; 1821 }; 1822 1823 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1824 1825 /* Get LLDP MIB (indirect 0x0A00) */ 1826 struct i40e_aqc_lldp_get_mib { 1827 u8 type; 1828 u8 reserved1; 1829 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1830 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1831 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1832 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1833 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1834 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1835 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1836 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1837 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1838 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1839 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1840 __le16 local_len; 1841 __le16 remote_len; 1842 u8 reserved2[2]; 1843 __le32 addr_high; 1844 __le32 addr_low; 1845 }; 1846 1847 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1848 1849 /* Configure LLDP MIB Change Event (direct 0x0A01) 1850 * also used for the event (with type in the command field) 1851 */ 1852 struct i40e_aqc_lldp_update_mib { 1853 u8 command; 1854 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1855 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1856 u8 reserved[7]; 1857 __le32 addr_high; 1858 __le32 addr_low; 1859 }; 1860 1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1862 1863 /* Add LLDP TLV (indirect 0x0A02) 1864 * Delete LLDP TLV (indirect 0x0A04) 1865 */ 1866 struct i40e_aqc_lldp_add_tlv { 1867 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1868 u8 reserved1[1]; 1869 __le16 len; 1870 u8 reserved2[4]; 1871 __le32 addr_high; 1872 __le32 addr_low; 1873 }; 1874 1875 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1876 1877 /* Update LLDP TLV (indirect 0x0A03) */ 1878 struct i40e_aqc_lldp_update_tlv { 1879 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1880 u8 reserved; 1881 __le16 old_len; 1882 __le16 new_offset; 1883 __le16 new_len; 1884 __le32 addr_high; 1885 __le32 addr_low; 1886 }; 1887 1888 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1889 1890 /* Stop LLDP (direct 0x0A05) */ 1891 struct i40e_aqc_lldp_stop { 1892 u8 command; 1893 #define I40E_AQ_LLDP_AGENT_STOP 0x0 1894 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1895 u8 reserved[15]; 1896 }; 1897 1898 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1899 1900 /* Start LLDP (direct 0x0A06) */ 1901 1902 struct i40e_aqc_lldp_start { 1903 u8 command; 1904 #define I40E_AQ_LLDP_AGENT_START 0x1 1905 u8 reserved[15]; 1906 }; 1907 1908 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 1909 1910 /* Apply MIB changes (0x0A07) 1911 * uses the generic struc as it contains no data 1912 */ 1913 1914 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 1915 struct i40e_aqc_add_udp_tunnel { 1916 __le16 udp_port; 1917 u8 header_len; /* in DWords, 1 to 15 */ 1918 u8 protocol_index; 1919 #define I40E_AQC_TUNNEL_TYPE_MAC 0x0 1920 #define I40E_AQC_TUNNEL_TYPE_UDP 0x1 1921 u8 reserved[12]; 1922 }; 1923 1924 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 1925 1926 /* remove UDP Tunnel command (0x0B01) */ 1927 struct i40e_aqc_remove_udp_tunnel { 1928 u8 reserved[2]; 1929 u8 index; /* 0 to 15 */ 1930 u8 pf_filters; 1931 u8 total_filters; 1932 u8 reserved2[11]; 1933 }; 1934 1935 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 1936 1937 struct i40e_aqc_del_udp_tunnel_completion { 1938 __le16 udp_port; 1939 u8 index; /* 0 to 15 */ 1940 u8 multiple_entries; 1941 u8 tunnels_used; 1942 u8 reserved; 1943 u8 tunnels_free; 1944 u8 reserved1[9]; 1945 }; 1946 1947 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 1948 1949 /* tunnel key structure 0x0B10 */ 1950 struct i40e_aqc_tunnel_key_structure { 1951 __le16 key1_off; 1952 __le16 key1_len; 1953 __le16 key2_off; 1954 __le16 key2_len; 1955 __le16 flags; 1956 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 1957 /* response flags */ 1958 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 1959 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 1960 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 1961 u8 resreved[6]; 1962 }; 1963 1964 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 1965 1966 /* OEM mode commands (direct 0xFE0x) */ 1967 struct i40e_aqc_oem_param_change { 1968 __le32 param_type; 1969 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 1970 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 1971 #define I40E_AQ_OEM_PARAM_MAC 2 1972 __le32 param_value1; 1973 u8 param_value2[8]; 1974 }; 1975 1976 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 1977 1978 struct i40e_aqc_oem_state_change { 1979 __le32 state; 1980 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 1981 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 1982 u8 reserved[12]; 1983 }; 1984 1985 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 1986 1987 /* debug commands */ 1988 1989 /* get device id (0xFF00) uses the generic structure */ 1990 1991 /* set test more (0xFF01, internal) */ 1992 1993 struct i40e_acq_set_test_mode { 1994 u8 mode; 1995 #define I40E_AQ_TEST_PARTIAL 0 1996 #define I40E_AQ_TEST_FULL 1 1997 #define I40E_AQ_TEST_NVM 2 1998 u8 reserved[3]; 1999 u8 command; 2000 #define I40E_AQ_TEST_OPEN 0 2001 #define I40E_AQ_TEST_CLOSE 1 2002 #define I40E_AQ_TEST_INC 2 2003 u8 reserved2[3]; 2004 __le32 address_high; 2005 __le32 address_low; 2006 }; 2007 2008 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2009 2010 /* Debug Read Register command (0xFF03) 2011 * Debug Write Register command (0xFF04) 2012 */ 2013 struct i40e_aqc_debug_reg_read_write { 2014 __le32 reserved; 2015 __le32 address; 2016 __le32 value_high; 2017 __le32 value_low; 2018 }; 2019 2020 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2021 2022 /* Scatter/gather Reg Read (indirect 0xFF05) 2023 * Scatter/gather Reg Write (indirect 0xFF06) 2024 */ 2025 2026 /* i40e_aq_desc is used for the command */ 2027 struct i40e_aqc_debug_reg_sg_element_data { 2028 __le32 address; 2029 __le32 value; 2030 }; 2031 2032 /* Debug Modify register (direct 0xFF07) */ 2033 struct i40e_aqc_debug_modify_reg { 2034 __le32 address; 2035 __le32 value; 2036 __le32 clear_mask; 2037 __le32 set_mask; 2038 }; 2039 2040 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2041 2042 /* dump internal data (0xFF08, indirect) */ 2043 2044 #define I40E_AQ_CLUSTER_ID_AUX 0 2045 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2046 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2047 #define I40E_AQ_CLUSTER_ID_HMC 3 2048 #define I40E_AQ_CLUSTER_ID_MAC0 4 2049 #define I40E_AQ_CLUSTER_ID_MAC1 5 2050 #define I40E_AQ_CLUSTER_ID_MAC2 6 2051 #define I40E_AQ_CLUSTER_ID_MAC3 7 2052 #define I40E_AQ_CLUSTER_ID_DCB 8 2053 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2054 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2055 2056 struct i40e_aqc_debug_dump_internals { 2057 u8 cluster_id; 2058 u8 table_id; 2059 __le16 data_size; 2060 __le32 idx; 2061 __le32 address_high; 2062 __le32 address_low; 2063 }; 2064 2065 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2066 2067 struct i40e_aqc_debug_modify_internals { 2068 u8 cluster_id; 2069 u8 cluster_specific_params[7]; 2070 __le32 address_high; 2071 __le32 address_low; 2072 }; 2073 2074 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2075 2076 #endif 2077