1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Driver
4  * Copyright(c) 2013 - 2014 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26 
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29 
30 /* This header file defines the i40e Admin Queue commands and is shared between
31  * i40e Firmware and Software.
32  *
33  * This file needs to comply with the Linux Kernel coding style.
34  */
35 
36 #define I40E_FW_API_VERSION_MAJOR	0x0001
37 #define I40E_FW_API_VERSION_MINOR	0x0002
38 
39 struct i40e_aq_desc {
40 	__le16 flags;
41 	__le16 opcode;
42 	__le16 datalen;
43 	__le16 retval;
44 	__le32 cookie_high;
45 	__le32 cookie_low;
46 	union {
47 		struct {
48 			__le32 param0;
49 			__le32 param1;
50 			__le32 param2;
51 			__le32 param3;
52 		} internal;
53 		struct {
54 			__le32 param0;
55 			__le32 param1;
56 			__le32 addr_high;
57 			__le32 addr_low;
58 		} external;
59 		u8 raw[16];
60 	} params;
61 };
62 
63 /* Flags sub-structure
64  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
65  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66  */
67 
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT	0
70 #define I40E_AQ_FLAG_CMP_SHIFT	1
71 #define I40E_AQ_FLAG_ERR_SHIFT	2
72 #define I40E_AQ_FLAG_VFE_SHIFT	3
73 #define I40E_AQ_FLAG_LB_SHIFT	9
74 #define I40E_AQ_FLAG_RD_SHIFT	10
75 #define I40E_AQ_FLAG_VFC_SHIFT	11
76 #define I40E_AQ_FLAG_BUF_SHIFT	12
77 #define I40E_AQ_FLAG_SI_SHIFT	13
78 #define I40E_AQ_FLAG_EI_SHIFT	14
79 #define I40E_AQ_FLAG_FE_SHIFT	15
80 
81 #define I40E_AQ_FLAG_DD		(1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
82 #define I40E_AQ_FLAG_CMP	(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
83 #define I40E_AQ_FLAG_ERR	(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
84 #define I40E_AQ_FLAG_VFE	(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
85 #define I40E_AQ_FLAG_LB		(1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
86 #define I40E_AQ_FLAG_RD		(1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
87 #define I40E_AQ_FLAG_VFC	(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
88 #define I40E_AQ_FLAG_BUF	(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI		(1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
90 #define I40E_AQ_FLAG_EI		(1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
91 #define I40E_AQ_FLAG_FE		(1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
92 
93 /* error codes */
94 enum i40e_admin_queue_err {
95 	I40E_AQ_RC_OK		= 0,  /* success */
96 	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */
97 	I40E_AQ_RC_ENOENT	= 2,  /* No such element */
98 	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */
99 	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */
100 	I40E_AQ_RC_EIO		= 5,  /* I/O error */
101 	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */
102 	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */
103 	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */
104 	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */
105 	I40E_AQ_RC_EACCES	= 10, /* Permission denied */
106 	I40E_AQ_RC_EFAULT	= 11, /* Bad address */
107 	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */
108 	I40E_AQ_RC_EEXIST	= 13, /* object already exists */
109 	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */
110 	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
111 	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */
112 	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */
113 	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */
114 	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
115 	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
116 	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */
117 	I40E_AQ_RC_EFBIG	= 22, /* File too large */
118 };
119 
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 	/* aq commands */
123 	i40e_aqc_opc_get_version	= 0x0001,
124 	i40e_aqc_opc_driver_version	= 0x0002,
125 	i40e_aqc_opc_queue_shutdown	= 0x0003,
126 	i40e_aqc_opc_set_pf_context	= 0x0004,
127 
128 	/* resource ownership */
129 	i40e_aqc_opc_request_resource	= 0x0008,
130 	i40e_aqc_opc_release_resource	= 0x0009,
131 
132 	i40e_aqc_opc_list_func_capabilities	= 0x000A,
133 	i40e_aqc_opc_list_dev_capabilities	= 0x000B,
134 
135 	i40e_aqc_opc_set_cppm_configuration	= 0x0103,
136 	i40e_aqc_opc_set_arp_proxy_entry	= 0x0104,
137 	i40e_aqc_opc_set_ns_proxy_entry		= 0x0105,
138 
139 	/* LAA */
140 	i40e_aqc_opc_mng_laa		= 0x0106,   /* AQ obsolete */
141 	i40e_aqc_opc_mac_address_read	= 0x0107,
142 	i40e_aqc_opc_mac_address_write	= 0x0108,
143 
144 	/* PXE */
145 	i40e_aqc_opc_clear_pxe_mode	= 0x0110,
146 
147 	/* internal switch commands */
148 	i40e_aqc_opc_get_switch_config		= 0x0200,
149 	i40e_aqc_opc_add_statistics		= 0x0201,
150 	i40e_aqc_opc_remove_statistics		= 0x0202,
151 	i40e_aqc_opc_set_port_parameters	= 0x0203,
152 	i40e_aqc_opc_get_switch_resource_alloc	= 0x0204,
153 
154 	i40e_aqc_opc_add_vsi			= 0x0210,
155 	i40e_aqc_opc_update_vsi_parameters	= 0x0211,
156 	i40e_aqc_opc_get_vsi_parameters		= 0x0212,
157 
158 	i40e_aqc_opc_add_pv			= 0x0220,
159 	i40e_aqc_opc_update_pv_parameters	= 0x0221,
160 	i40e_aqc_opc_get_pv_parameters		= 0x0222,
161 
162 	i40e_aqc_opc_add_veb			= 0x0230,
163 	i40e_aqc_opc_update_veb_parameters	= 0x0231,
164 	i40e_aqc_opc_get_veb_parameters		= 0x0232,
165 
166 	i40e_aqc_opc_delete_element		= 0x0243,
167 
168 	i40e_aqc_opc_add_macvlan		= 0x0250,
169 	i40e_aqc_opc_remove_macvlan		= 0x0251,
170 	i40e_aqc_opc_add_vlan			= 0x0252,
171 	i40e_aqc_opc_remove_vlan		= 0x0253,
172 	i40e_aqc_opc_set_vsi_promiscuous_modes	= 0x0254,
173 	i40e_aqc_opc_add_tag			= 0x0255,
174 	i40e_aqc_opc_remove_tag			= 0x0256,
175 	i40e_aqc_opc_add_multicast_etag		= 0x0257,
176 	i40e_aqc_opc_remove_multicast_etag	= 0x0258,
177 	i40e_aqc_opc_update_tag			= 0x0259,
178 	i40e_aqc_opc_add_control_packet_filter	= 0x025A,
179 	i40e_aqc_opc_remove_control_packet_filter	= 0x025B,
180 	i40e_aqc_opc_add_cloud_filters		= 0x025C,
181 	i40e_aqc_opc_remove_cloud_filters	= 0x025D,
182 
183 	i40e_aqc_opc_add_mirror_rule	= 0x0260,
184 	i40e_aqc_opc_delete_mirror_rule	= 0x0261,
185 
186 	/* DCB commands */
187 	i40e_aqc_opc_dcb_ignore_pfc	= 0x0301,
188 	i40e_aqc_opc_dcb_updated	= 0x0302,
189 
190 	/* TX scheduler */
191 	i40e_aqc_opc_configure_vsi_bw_limit		= 0x0400,
192 	i40e_aqc_opc_configure_vsi_ets_sla_bw_limit	= 0x0406,
193 	i40e_aqc_opc_configure_vsi_tc_bw		= 0x0407,
194 	i40e_aqc_opc_query_vsi_bw_config		= 0x0408,
195 	i40e_aqc_opc_query_vsi_ets_sla_config		= 0x040A,
196 	i40e_aqc_opc_configure_switching_comp_bw_limit	= 0x0410,
197 
198 	i40e_aqc_opc_enable_switching_comp_ets			= 0x0413,
199 	i40e_aqc_opc_modify_switching_comp_ets			= 0x0414,
200 	i40e_aqc_opc_disable_switching_comp_ets			= 0x0415,
201 	i40e_aqc_opc_configure_switching_comp_ets_bw_limit	= 0x0416,
202 	i40e_aqc_opc_configure_switching_comp_bw_config		= 0x0417,
203 	i40e_aqc_opc_query_switching_comp_ets_config		= 0x0418,
204 	i40e_aqc_opc_query_port_ets_config			= 0x0419,
205 	i40e_aqc_opc_query_switching_comp_bw_config		= 0x041A,
206 	i40e_aqc_opc_suspend_port_tx				= 0x041B,
207 	i40e_aqc_opc_resume_port_tx				= 0x041C,
208 	i40e_aqc_opc_configure_partition_bw			= 0x041D,
209 
210 	/* hmc */
211 	i40e_aqc_opc_query_hmc_resource_profile	= 0x0500,
212 	i40e_aqc_opc_set_hmc_resource_profile	= 0x0501,
213 
214 	/* phy commands*/
215 	i40e_aqc_opc_get_phy_abilities		= 0x0600,
216 	i40e_aqc_opc_set_phy_config		= 0x0601,
217 	i40e_aqc_opc_set_mac_config		= 0x0603,
218 	i40e_aqc_opc_set_link_restart_an	= 0x0605,
219 	i40e_aqc_opc_get_link_status		= 0x0607,
220 	i40e_aqc_opc_set_phy_int_mask		= 0x0613,
221 	i40e_aqc_opc_get_local_advt_reg		= 0x0614,
222 	i40e_aqc_opc_set_local_advt_reg		= 0x0615,
223 	i40e_aqc_opc_get_partner_advt		= 0x0616,
224 	i40e_aqc_opc_set_lb_modes		= 0x0618,
225 	i40e_aqc_opc_get_phy_wol_caps		= 0x0621,
226 	i40e_aqc_opc_set_phy_debug		= 0x0622,
227 	i40e_aqc_opc_upload_ext_phy_fm		= 0x0625,
228 
229 	/* NVM commands */
230 	i40e_aqc_opc_nvm_read			= 0x0701,
231 	i40e_aqc_opc_nvm_erase			= 0x0702,
232 	i40e_aqc_opc_nvm_update			= 0x0703,
233 	i40e_aqc_opc_nvm_config_read		= 0x0704,
234 	i40e_aqc_opc_nvm_config_write		= 0x0705,
235 
236 	/* virtualization commands */
237 	i40e_aqc_opc_send_msg_to_pf		= 0x0801,
238 	i40e_aqc_opc_send_msg_to_vf		= 0x0802,
239 	i40e_aqc_opc_send_msg_to_peer		= 0x0803,
240 
241 	/* alternate structure */
242 	i40e_aqc_opc_alternate_write		= 0x0900,
243 	i40e_aqc_opc_alternate_write_indirect	= 0x0901,
244 	i40e_aqc_opc_alternate_read		= 0x0902,
245 	i40e_aqc_opc_alternate_read_indirect	= 0x0903,
246 	i40e_aqc_opc_alternate_write_done	= 0x0904,
247 	i40e_aqc_opc_alternate_set_mode		= 0x0905,
248 	i40e_aqc_opc_alternate_clear_port	= 0x0906,
249 
250 	/* LLDP commands */
251 	i40e_aqc_opc_lldp_get_mib	= 0x0A00,
252 	i40e_aqc_opc_lldp_update_mib	= 0x0A01,
253 	i40e_aqc_opc_lldp_add_tlv	= 0x0A02,
254 	i40e_aqc_opc_lldp_update_tlv	= 0x0A03,
255 	i40e_aqc_opc_lldp_delete_tlv	= 0x0A04,
256 	i40e_aqc_opc_lldp_stop		= 0x0A05,
257 	i40e_aqc_opc_lldp_start		= 0x0A06,
258 	i40e_aqc_opc_get_cee_dcb_cfg	= 0x0A07,
259 
260 	/* Tunnel commands */
261 	i40e_aqc_opc_add_udp_tunnel	= 0x0B00,
262 	i40e_aqc_opc_del_udp_tunnel	= 0x0B01,
263 	i40e_aqc_opc_tunnel_key_structure	= 0x0B10,
264 
265 	/* Async Events */
266 	i40e_aqc_opc_event_lan_overflow		= 0x1001,
267 
268 	/* OEM commands */
269 	i40e_aqc_opc_oem_parameter_change	= 0xFE00,
270 	i40e_aqc_opc_oem_device_status_change	= 0xFE01,
271 
272 	/* debug commands */
273 	i40e_aqc_opc_debug_get_deviceid		= 0xFF00,
274 	i40e_aqc_opc_debug_set_mode		= 0xFF01,
275 	i40e_aqc_opc_debug_read_reg		= 0xFF03,
276 	i40e_aqc_opc_debug_write_reg		= 0xFF04,
277 	i40e_aqc_opc_debug_modify_reg		= 0xFF07,
278 	i40e_aqc_opc_debug_dump_internals	= 0xFF08,
279 	i40e_aqc_opc_debug_modify_internals	= 0xFF09,
280 };
281 
282 /* command structures and indirect data structures */
283 
284 /* Structure naming conventions:
285  * - no suffix for direct command descriptor structures
286  * - _data for indirect sent data
287  * - _resp for indirect return data (data which is both will use _data)
288  * - _completion for direct return data
289  * - _element_ for repeated elements (may also be _data or _resp)
290  *
291  * Command structures are expected to overlay the params.raw member of the basic
292  * descriptor, and as such cannot exceed 16 bytes in length.
293  */
294 
295 /* This macro is used to generate a compilation error if a structure
296  * is not exactly the correct length. It gives a divide by zero error if the
297  * structure is not of the correct size, otherwise it creates an enum that is
298  * never used.
299  */
300 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 	{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302 
303 /* This macro is used extensively to ensure that command structures are 16
304  * bytes in length as they have to map to the raw array of that size.
305  */
306 #define I40E_CHECK_CMD_LENGTH(X)	I40E_CHECK_STRUCT_LEN(16, X)
307 
308 /* internal (0x00XX) commands */
309 
310 /* Get version (direct 0x0001) */
311 struct i40e_aqc_get_version {
312 	__le32 rom_ver;
313 	__le32 fw_build;
314 	__le16 fw_major;
315 	__le16 fw_minor;
316 	__le16 api_major;
317 	__le16 api_minor;
318 };
319 
320 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321 
322 /* Send driver version (indirect 0x0002) */
323 struct i40e_aqc_driver_version {
324 	u8	driver_major_ver;
325 	u8	driver_minor_ver;
326 	u8	driver_build_ver;
327 	u8	driver_subbuild_ver;
328 	u8	reserved[4];
329 	__le32	address_high;
330 	__le32	address_low;
331 };
332 
333 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334 
335 /* Queue Shutdown (direct 0x0003) */
336 struct i40e_aqc_queue_shutdown {
337 	__le32	driver_unloading;
338 #define I40E_AQ_DRIVER_UNLOADING	0x1
339 	u8	reserved[12];
340 };
341 
342 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343 
344 /* Set PF context (0x0004, direct) */
345 struct i40e_aqc_set_pf_context {
346 	u8	pf_id;
347 	u8	reserved[15];
348 };
349 
350 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351 
352 /* Request resource ownership (direct 0x0008)
353  * Release resource ownership (direct 0x0009)
354  */
355 #define I40E_AQ_RESOURCE_NVM			1
356 #define I40E_AQ_RESOURCE_SDP			2
357 #define I40E_AQ_RESOURCE_ACCESS_READ		1
358 #define I40E_AQ_RESOURCE_ACCESS_WRITE		2
359 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT	3000
360 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT	180000
361 
362 struct i40e_aqc_request_resource {
363 	__le16	resource_id;
364 	__le16	access_type;
365 	__le32	timeout;
366 	__le32	resource_number;
367 	u8	reserved[4];
368 };
369 
370 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
371 
372 /* Get function capabilities (indirect 0x000A)
373  * Get device capabilities (indirect 0x000B)
374  */
375 struct i40e_aqc_list_capabilites {
376 	u8 command_flags;
377 #define I40E_AQ_LIST_CAP_PF_INDEX_EN	1
378 	u8 pf_index;
379 	u8 reserved[2];
380 	__le32 count;
381 	__le32 addr_high;
382 	__le32 addr_low;
383 };
384 
385 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
386 
387 struct i40e_aqc_list_capabilities_element_resp {
388 	__le16	id;
389 	u8	major_rev;
390 	u8	minor_rev;
391 	__le32	number;
392 	__le32	logical_id;
393 	__le32	phys_id;
394 	u8	reserved[16];
395 };
396 
397 /* list of caps */
398 
399 #define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001
400 #define I40E_AQ_CAP_ID_MNG_MODE		0x0002
401 #define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003
402 #define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004
403 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005
404 #define I40E_AQ_CAP_ID_ALTERNATE_RAM	0x0006
405 #define I40E_AQ_CAP_ID_SRIOV		0x0012
406 #define I40E_AQ_CAP_ID_VF		0x0013
407 #define I40E_AQ_CAP_ID_VMDQ		0x0014
408 #define I40E_AQ_CAP_ID_8021QBG		0x0015
409 #define I40E_AQ_CAP_ID_8021QBR		0x0016
410 #define I40E_AQ_CAP_ID_VSI		0x0017
411 #define I40E_AQ_CAP_ID_DCB		0x0018
412 #define I40E_AQ_CAP_ID_FCOE		0x0021
413 #define I40E_AQ_CAP_ID_RSS		0x0040
414 #define I40E_AQ_CAP_ID_RXQ		0x0041
415 #define I40E_AQ_CAP_ID_TXQ		0x0042
416 #define I40E_AQ_CAP_ID_MSIX		0x0043
417 #define I40E_AQ_CAP_ID_VF_MSIX		0x0044
418 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045
419 #define I40E_AQ_CAP_ID_1588		0x0046
420 #define I40E_AQ_CAP_ID_IWARP		0x0051
421 #define I40E_AQ_CAP_ID_LED		0x0061
422 #define I40E_AQ_CAP_ID_SDP		0x0062
423 #define I40E_AQ_CAP_ID_MDIO		0x0063
424 #define I40E_AQ_CAP_ID_FLEX10		0x00F1
425 #define I40E_AQ_CAP_ID_CEM		0x00F2
426 
427 /* Set CPPM Configuration (direct 0x0103) */
428 struct i40e_aqc_cppm_configuration {
429 	__le16	command_flags;
430 #define I40E_AQ_CPPM_EN_LTRC	0x0800
431 #define I40E_AQ_CPPM_EN_DMCTH	0x1000
432 #define I40E_AQ_CPPM_EN_DMCTLX	0x2000
433 #define I40E_AQ_CPPM_EN_HPTC	0x4000
434 #define I40E_AQ_CPPM_EN_DMARC	0x8000
435 	__le16	ttlx;
436 	__le32	dmacr;
437 	__le16	dmcth;
438 	u8	hptc;
439 	u8	reserved;
440 	__le32	pfltrc;
441 };
442 
443 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
444 
445 /* Set ARP Proxy command / response (indirect 0x0104) */
446 struct i40e_aqc_arp_proxy_data {
447 	__le16	command_flags;
448 #define I40E_AQ_ARP_INIT_IPV4	0x0008
449 #define I40E_AQ_ARP_UNSUP_CTL	0x0010
450 #define I40E_AQ_ARP_ENA		0x0020
451 #define I40E_AQ_ARP_ADD_IPV4	0x0040
452 #define I40E_AQ_ARP_DEL_IPV4	0x0080
453 	__le16	table_id;
454 	__le32	pfpm_proxyfc;
455 	__le32	ip_addr;
456 	u8	mac_addr[6];
457 };
458 
459 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
460 struct i40e_aqc_ns_proxy_data {
461 	__le16	table_idx_mac_addr_0;
462 	__le16	table_idx_mac_addr_1;
463 	__le16	table_idx_ipv6_0;
464 	__le16	table_idx_ipv6_1;
465 	__le16	control;
466 #define I40E_AQ_NS_PROXY_ADD_0		0x0100
467 #define I40E_AQ_NS_PROXY_DEL_0		0x0200
468 #define I40E_AQ_NS_PROXY_ADD_1		0x0400
469 #define I40E_AQ_NS_PROXY_DEL_1		0x0800
470 #define I40E_AQ_NS_PROXY_ADD_IPV6_0	0x1000
471 #define I40E_AQ_NS_PROXY_DEL_IPV6_0	0x2000
472 #define I40E_AQ_NS_PROXY_ADD_IPV6_1	0x4000
473 #define I40E_AQ_NS_PROXY_DEL_IPV6_1	0x8000
474 #define I40E_AQ_NS_PROXY_COMMAND_SEQ	0x0001
475 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL	0x0002
476 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL	0x0004
477 	u8	mac_addr_0[6];
478 	u8	mac_addr_1[6];
479 	u8	local_mac_addr[6];
480 	u8	ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
481 	u8	ipv6_addr_1[16];
482 };
483 
484 /* Manage LAA Command (0x0106) - obsolete */
485 struct i40e_aqc_mng_laa {
486 	__le16	command_flags;
487 #define I40E_AQ_LAA_FLAG_WR	0x8000
488 	u8	reserved[2];
489 	__le32	sal;
490 	__le16	sah;
491 	u8	reserved2[6];
492 };
493 
494 /* Manage MAC Address Read Command (indirect 0x0107) */
495 struct i40e_aqc_mac_address_read {
496 	__le16	command_flags;
497 #define I40E_AQC_LAN_ADDR_VALID		0x10
498 #define I40E_AQC_SAN_ADDR_VALID		0x20
499 #define I40E_AQC_PORT_ADDR_VALID	0x40
500 #define I40E_AQC_WOL_ADDR_VALID		0x80
501 #define I40E_AQC_ADDR_VALID_MASK	0xf0
502 	u8	reserved[6];
503 	__le32	addr_high;
504 	__le32	addr_low;
505 };
506 
507 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
508 
509 struct i40e_aqc_mac_address_read_data {
510 	u8 pf_lan_mac[6];
511 	u8 pf_san_mac[6];
512 	u8 port_mac[6];
513 	u8 pf_wol_mac[6];
514 };
515 
516 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
517 
518 /* Manage MAC Address Write Command (0x0108) */
519 struct i40e_aqc_mac_address_write {
520 	__le16	command_flags;
521 #define I40E_AQC_WRITE_TYPE_LAA_ONLY	0x0000
522 #define I40E_AQC_WRITE_TYPE_LAA_WOL	0x4000
523 #define I40E_AQC_WRITE_TYPE_PORT	0x8000
524 #define I40E_AQC_WRITE_TYPE_MASK	0xc000
525 	__le16	mac_sah;
526 	__le32	mac_sal;
527 	u8	reserved[8];
528 };
529 
530 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
531 
532 /* PXE commands (0x011x) */
533 
534 /* Clear PXE Command and response  (direct 0x0110) */
535 struct i40e_aqc_clear_pxe {
536 	u8	rx_cnt;
537 	u8	reserved[15];
538 };
539 
540 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
541 
542 /* Switch configuration commands (0x02xx) */
543 
544 /* Used by many indirect commands that only pass an seid and a buffer in the
545  * command
546  */
547 struct i40e_aqc_switch_seid {
548 	__le16	seid;
549 	u8	reserved[6];
550 	__le32	addr_high;
551 	__le32	addr_low;
552 };
553 
554 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
555 
556 /* Get Switch Configuration command (indirect 0x0200)
557  * uses i40e_aqc_switch_seid for the descriptor
558  */
559 struct i40e_aqc_get_switch_config_header_resp {
560 	__le16	num_reported;
561 	__le16	num_total;
562 	u8	reserved[12];
563 };
564 
565 struct i40e_aqc_switch_config_element_resp {
566 	u8	element_type;
567 #define I40E_AQ_SW_ELEM_TYPE_MAC	1
568 #define I40E_AQ_SW_ELEM_TYPE_PF		2
569 #define I40E_AQ_SW_ELEM_TYPE_VF		3
570 #define I40E_AQ_SW_ELEM_TYPE_EMP	4
571 #define I40E_AQ_SW_ELEM_TYPE_BMC	5
572 #define I40E_AQ_SW_ELEM_TYPE_PV		16
573 #define I40E_AQ_SW_ELEM_TYPE_VEB	17
574 #define I40E_AQ_SW_ELEM_TYPE_PA		18
575 #define I40E_AQ_SW_ELEM_TYPE_VSI	19
576 	u8	revision;
577 #define I40E_AQ_SW_ELEM_REV_1		1
578 	__le16	seid;
579 	__le16	uplink_seid;
580 	__le16	downlink_seid;
581 	u8	reserved[3];
582 	u8	connection_type;
583 #define I40E_AQ_CONN_TYPE_REGULAR	0x1
584 #define I40E_AQ_CONN_TYPE_DEFAULT	0x2
585 #define I40E_AQ_CONN_TYPE_CASCADED	0x3
586 	__le16	scheduler_id;
587 	__le16	element_info;
588 };
589 
590 /* Get Switch Configuration (indirect 0x0200)
591  *    an array of elements are returned in the response buffer
592  *    the first in the array is the header, remainder are elements
593  */
594 struct i40e_aqc_get_switch_config_resp {
595 	struct i40e_aqc_get_switch_config_header_resp	header;
596 	struct i40e_aqc_switch_config_element_resp	element[1];
597 };
598 
599 /* Add Statistics (direct 0x0201)
600  * Remove Statistics (direct 0x0202)
601  */
602 struct i40e_aqc_add_remove_statistics {
603 	__le16	seid;
604 	__le16	vlan;
605 	__le16	stat_index;
606 	u8	reserved[10];
607 };
608 
609 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
610 
611 /* Set Port Parameters command (direct 0x0203) */
612 struct i40e_aqc_set_port_parameters {
613 	__le16	command_flags;
614 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS	1
615 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS	2 /* must set! */
616 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA	4
617 	__le16	bad_frame_vsi;
618 	__le16	default_seid;        /* reserved for command */
619 	u8	reserved[10];
620 };
621 
622 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
623 
624 /* Get Switch Resource Allocation (indirect 0x0204) */
625 struct i40e_aqc_get_switch_resource_alloc {
626 	u8	num_entries;         /* reserved for command */
627 	u8	reserved[7];
628 	__le32	addr_high;
629 	__le32	addr_low;
630 };
631 
632 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
633 
634 /* expect an array of these structs in the response buffer */
635 struct i40e_aqc_switch_resource_alloc_element_resp {
636 	u8	resource_type;
637 #define I40E_AQ_RESOURCE_TYPE_VEB		0x0
638 #define I40E_AQ_RESOURCE_TYPE_VSI		0x1
639 #define I40E_AQ_RESOURCE_TYPE_MACADDR		0x2
640 #define I40E_AQ_RESOURCE_TYPE_STAG		0x3
641 #define I40E_AQ_RESOURCE_TYPE_ETAG		0x4
642 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH	0x5
643 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH	0x6
644 #define I40E_AQ_RESOURCE_TYPE_VLAN		0x7
645 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY	0x8
646 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY	0x9
647 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL	0xA
648 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE	0xB
649 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS	0xC
650 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS	0xD
651 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS	0xF
652 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS	0x10
653 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS	0x11
654 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS		0x12
655 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS	0x13
656 	u8	reserved1;
657 	__le16	guaranteed;
658 	__le16	total;
659 	__le16	used;
660 	__le16	total_unalloced;
661 	u8	reserved2[6];
662 };
663 
664 /* Add VSI (indirect 0x0210)
665  *    this indirect command uses struct i40e_aqc_vsi_properties_data
666  *    as the indirect buffer (128 bytes)
667  *
668  * Update VSI (indirect 0x211)
669  *     uses the same data structure as Add VSI
670  *
671  * Get VSI (indirect 0x0212)
672  *     uses the same completion and data structure as Add VSI
673  */
674 struct i40e_aqc_add_get_update_vsi {
675 	__le16	uplink_seid;
676 	u8	connection_type;
677 #define I40E_AQ_VSI_CONN_TYPE_NORMAL	0x1
678 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT	0x2
679 #define I40E_AQ_VSI_CONN_TYPE_CASCADED	0x3
680 	u8	reserved1;
681 	u8	vf_id;
682 	u8	reserved2;
683 	__le16	vsi_flags;
684 #define I40E_AQ_VSI_TYPE_SHIFT		0x0
685 #define I40E_AQ_VSI_TYPE_MASK		(0x3 << I40E_AQ_VSI_TYPE_SHIFT)
686 #define I40E_AQ_VSI_TYPE_VF		0x0
687 #define I40E_AQ_VSI_TYPE_VMDQ2		0x1
688 #define I40E_AQ_VSI_TYPE_PF		0x2
689 #define I40E_AQ_VSI_TYPE_EMP_MNG	0x3
690 #define I40E_AQ_VSI_FLAG_CASCADED_PV	0x4
691 	__le32	addr_high;
692 	__le32	addr_low;
693 };
694 
695 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
696 
697 struct i40e_aqc_add_get_update_vsi_completion {
698 	__le16 seid;
699 	__le16 vsi_number;
700 	__le16 vsi_used;
701 	__le16 vsi_free;
702 	__le32 addr_high;
703 	__le32 addr_low;
704 };
705 
706 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
707 
708 struct i40e_aqc_vsi_properties_data {
709 	/* first 96 byte are written by SW */
710 	__le16	valid_sections;
711 #define I40E_AQ_VSI_PROP_SWITCH_VALID		0x0001
712 #define I40E_AQ_VSI_PROP_SECURITY_VALID		0x0002
713 #define I40E_AQ_VSI_PROP_VLAN_VALID		0x0004
714 #define I40E_AQ_VSI_PROP_CAS_PV_VALID		0x0008
715 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID	0x0010
716 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID	0x0020
717 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID	0x0040
718 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID	0x0080
719 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID		0x0100
720 #define I40E_AQ_VSI_PROP_SCHED_VALID		0x0200
721 	/* switch section */
722 	__le16	switch_id; /* 12bit id combined with flags below */
723 #define I40E_AQ_VSI_SW_ID_SHIFT		0x0000
724 #define I40E_AQ_VSI_SW_ID_MASK		(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
725 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG	0x1000
726 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB	0x2000
727 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB	0x4000
728 	u8	sw_reserved[2];
729 	/* security section */
730 	u8	sec_flags;
731 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	0x01
732 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK	0x02
733 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK	0x04
734 	u8	sec_reserved;
735 	/* VLAN section */
736 	__le16	pvid; /* VLANS include priority bits */
737 	__le16	fcoe_pvid;
738 	u8	port_vlan_flags;
739 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
740 #define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
741 					 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
742 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED	0x01
743 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED	0x02
744 #define I40E_AQ_VSI_PVLAN_MODE_ALL	0x03
745 #define I40E_AQ_VSI_PVLAN_INSERT_PVID	0x04
746 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT	0x03
747 #define I40E_AQ_VSI_PVLAN_EMOD_MASK	(0x3 << \
748 					 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
749 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH	0x0
750 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP	0x08
751 #define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
752 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
753 	u8	pvlan_reserved[3];
754 	/* ingress egress up sections */
755 	__le32	ingress_table; /* bitmap, 3 bits per up */
756 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT	0
757 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK	(0x7 << \
758 					 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
759 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT	3
760 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK	(0x7 << \
761 					 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
762 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT	6
763 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK	(0x7 << \
764 					 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
765 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT	9
766 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK	(0x7 << \
767 					 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
768 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT	12
769 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK	(0x7 << \
770 					 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
771 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT	15
772 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK	(0x7 << \
773 					 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
774 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT	18
775 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK	(0x7 << \
776 					 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
777 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT	21
778 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK	(0x7 << \
779 					 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
780 	__le32	egress_table;   /* same defines as for ingress table */
781 	/* cascaded PV section */
782 	__le16	cas_pv_tag;
783 	u8	cas_pv_flags;
784 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT		0x00
785 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK		(0x03 << \
786 						 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
787 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE		0x00
788 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE		0x01
789 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY		0x02
790 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG		0x10
791 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE		0x20
792 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG	0x40
793 	u8	cas_pv_reserved;
794 	/* queue mapping section */
795 	__le16	mapping_flags;
796 #define I40E_AQ_VSI_QUE_MAP_CONTIG	0x0
797 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG	0x1
798 	__le16	queue_mapping[16];
799 #define I40E_AQ_VSI_QUEUE_SHIFT		0x0
800 #define I40E_AQ_VSI_QUEUE_MASK		(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
801 	__le16	tc_mapping[8];
802 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT	0
803 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK	(0x1FF << \
804 					 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
805 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT	9
806 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK	(0x7 << \
807 					 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
808 	/* queueing option section */
809 	u8	queueing_opt_flags;
810 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA	0x10
811 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA	0x20
812 	u8	queueing_opt_reserved[3];
813 	/* scheduler section */
814 	u8	up_enable_bits;
815 	u8	sched_reserved;
816 	/* outer up section */
817 	__le32	outer_up_table; /* same structure and defines as ingress tbl */
818 	u8	cmd_reserved[8];
819 	/* last 32 bytes are written by FW */
820 	__le16	qs_handle[8];
821 #define I40E_AQ_VSI_QS_HANDLE_INVALID	0xFFFF
822 	__le16	stat_counter_idx;
823 	__le16	sched_id;
824 	u8	resp_reserved[12];
825 };
826 
827 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
828 
829 /* Add Port Virtualizer (direct 0x0220)
830  * also used for update PV (direct 0x0221) but only flags are used
831  * (IS_CTRL_PORT only works on add PV)
832  */
833 struct i40e_aqc_add_update_pv {
834 	__le16	command_flags;
835 #define I40E_AQC_PV_FLAG_PV_TYPE		0x1
836 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN	0x2
837 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN	0x4
838 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT		0x8
839 	__le16	uplink_seid;
840 	__le16	connected_seid;
841 	u8	reserved[10];
842 };
843 
844 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
845 
846 struct i40e_aqc_add_update_pv_completion {
847 	/* reserved for update; for add also encodes error if rc == ENOSPC */
848 	__le16	pv_seid;
849 #define I40E_AQC_PV_ERR_FLAG_NO_PV	0x1
850 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED	0x2
851 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER	0x4
852 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY	0x8
853 	u8	reserved[14];
854 };
855 
856 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
857 
858 /* Get PV Params (direct 0x0222)
859  * uses i40e_aqc_switch_seid for the descriptor
860  */
861 
862 struct i40e_aqc_get_pv_params_completion {
863 	__le16	seid;
864 	__le16	default_stag;
865 	__le16	pv_flags; /* same flags as add_pv */
866 #define I40E_AQC_GET_PV_PV_TYPE			0x1
867 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG	0x2
868 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG	0x4
869 	u8	reserved[8];
870 	__le16	default_port_seid;
871 };
872 
873 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
874 
875 /* Add VEB (direct 0x0230) */
876 struct i40e_aqc_add_veb {
877 	__le16	uplink_seid;
878 	__le16	downlink_seid;
879 	__le16	veb_flags;
880 #define I40E_AQC_ADD_VEB_FLOATING		0x1
881 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT	1
882 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK		(0x3 << \
883 					I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
884 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT	0x2
885 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA		0x4
886 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER	0x8
887 	u8	enable_tcs;
888 	u8	reserved[9];
889 };
890 
891 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
892 
893 struct i40e_aqc_add_veb_completion {
894 	u8	reserved[6];
895 	__le16	switch_seid;
896 	/* also encodes error if rc == ENOSPC; codes are the same as add_pv */
897 	__le16	veb_seid;
898 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB		0x1
899 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED		0x2
900 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER	0x4
901 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY		0x8
902 	__le16	statistic_index;
903 	__le16	vebs_used;
904 	__le16	vebs_free;
905 };
906 
907 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
908 
909 /* Get VEB Parameters (direct 0x0232)
910  * uses i40e_aqc_switch_seid for the descriptor
911  */
912 struct i40e_aqc_get_veb_parameters_completion {
913 	__le16	seid;
914 	__le16	switch_id;
915 	__le16	veb_flags; /* only the first/last flags from 0x0230 is valid */
916 	__le16	statistic_index;
917 	__le16	vebs_used;
918 	__le16	vebs_free;
919 	u8	reserved[4];
920 };
921 
922 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
923 
924 /* Delete Element (direct 0x0243)
925  * uses the generic i40e_aqc_switch_seid
926  */
927 
928 /* Add MAC-VLAN (indirect 0x0250) */
929 
930 /* used for the command for most vlan commands */
931 struct i40e_aqc_macvlan {
932 	__le16	num_addresses;
933 	__le16	seid[3];
934 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT	0
935 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK	(0x3FF << \
936 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
937 #define I40E_AQC_MACVLAN_CMD_SEID_VALID		0x8000
938 	__le32	addr_high;
939 	__le32	addr_low;
940 };
941 
942 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
943 
944 /* indirect data for command and response */
945 struct i40e_aqc_add_macvlan_element_data {
946 	u8	mac_addr[6];
947 	__le16	vlan_tag;
948 	__le16	flags;
949 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH	0x0001
950 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH		0x0002
951 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN	0x0004
952 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE		0x0008
953 	__le16	queue_number;
954 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT	0
955 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK		(0x7FF << \
956 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
957 	/* response section */
958 	u8	match_method;
959 #define I40E_AQC_MM_PERFECT_MATCH	0x01
960 #define I40E_AQC_MM_HASH_MATCH		0x02
961 #define I40E_AQC_MM_ERR_NO_RES		0xFF
962 	u8	reserved1[3];
963 };
964 
965 struct i40e_aqc_add_remove_macvlan_completion {
966 	__le16 perfect_mac_used;
967 	__le16 perfect_mac_free;
968 	__le16 unicast_hash_free;
969 	__le16 multicast_hash_free;
970 	__le32 addr_high;
971 	__le32 addr_low;
972 };
973 
974 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
975 
976 /* Remove MAC-VLAN (indirect 0x0251)
977  * uses i40e_aqc_macvlan for the descriptor
978  * data points to an array of num_addresses of elements
979  */
980 
981 struct i40e_aqc_remove_macvlan_element_data {
982 	u8	mac_addr[6];
983 	__le16	vlan_tag;
984 	u8	flags;
985 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH	0x01
986 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH		0x02
987 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN	0x08
988 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS		0x10
989 	u8	reserved[3];
990 	/* reply section */
991 	u8	error_code;
992 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS		0x0
993 #define I40E_AQC_REMOVE_MACVLAN_FAIL		0xFF
994 	u8	reply_reserved[3];
995 };
996 
997 /* Add VLAN (indirect 0x0252)
998  * Remove VLAN (indirect 0x0253)
999  * use the generic i40e_aqc_macvlan for the command
1000  */
1001 struct i40e_aqc_add_remove_vlan_element_data {
1002 	__le16	vlan_tag;
1003 	u8	vlan_flags;
1004 /* flags for add VLAN */
1005 #define I40E_AQC_ADD_VLAN_LOCAL			0x1
1006 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT		1
1007 #define I40E_AQC_ADD_PVLAN_TYPE_MASK	(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1008 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR		0x0
1009 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY		0x2
1010 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY	0x4
1011 #define I40E_AQC_VLAN_PTYPE_SHIFT		3
1012 #define I40E_AQC_VLAN_PTYPE_MASK	(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1013 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI		0x0
1014 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI		0x8
1015 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI	0x10
1016 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI	0x18
1017 /* flags for remove VLAN */
1018 #define I40E_AQC_REMOVE_VLAN_ALL	0x1
1019 	u8	reserved;
1020 	u8	result;
1021 /* flags for add VLAN */
1022 #define I40E_AQC_ADD_VLAN_SUCCESS	0x0
1023 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST	0xFE
1024 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE	0xFF
1025 /* flags for remove VLAN */
1026 #define I40E_AQC_REMOVE_VLAN_SUCCESS	0x0
1027 #define I40E_AQC_REMOVE_VLAN_FAIL	0xFF
1028 	u8	reserved1[3];
1029 };
1030 
1031 struct i40e_aqc_add_remove_vlan_completion {
1032 	u8	reserved[4];
1033 	__le16	vlans_used;
1034 	__le16	vlans_free;
1035 	__le32	addr_high;
1036 	__le32	addr_low;
1037 };
1038 
1039 /* Set VSI Promiscuous Modes (direct 0x0254) */
1040 struct i40e_aqc_set_vsi_promiscuous_modes {
1041 	__le16	promiscuous_flags;
1042 	__le16	valid_flags;
1043 /* flags used for both fields above */
1044 #define I40E_AQC_SET_VSI_PROMISC_UNICAST	0x01
1045 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST	0x02
1046 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
1047 #define I40E_AQC_SET_VSI_DEFAULT		0x08
1048 #define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
1049 	__le16	seid;
1050 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK		0x3FF
1051 	__le16	vlan_tag;
1052 #define I40E_AQC_SET_VSI_VLAN_VALID		0x8000
1053 	u8	reserved[8];
1054 };
1055 
1056 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1057 
1058 /* Add S/E-tag command (direct 0x0255)
1059  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1060  */
1061 struct i40e_aqc_add_tag {
1062 	__le16	flags;
1063 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE		0x0001
1064 	__le16	seid;
1065 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT	0
1066 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1067 					I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1068 	__le16	tag;
1069 	__le16	queue_number;
1070 	u8	reserved[8];
1071 };
1072 
1073 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1074 
1075 struct i40e_aqc_add_remove_tag_completion {
1076 	u8	reserved[12];
1077 	__le16	tags_used;
1078 	__le16	tags_free;
1079 };
1080 
1081 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1082 
1083 /* Remove S/E-tag command (direct 0x0256)
1084  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1085  */
1086 struct i40e_aqc_remove_tag {
1087 	__le16	seid;
1088 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT	0
1089 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1090 					I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1091 	__le16	tag;
1092 	u8	reserved[12];
1093 };
1094 
1095 /* Add multicast E-Tag (direct 0x0257)
1096  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1097  * and no external data
1098  */
1099 struct i40e_aqc_add_remove_mcast_etag {
1100 	__le16	pv_seid;
1101 	__le16	etag;
1102 	u8	num_unicast_etags;
1103 	u8	reserved[3];
1104 	__le32	addr_high;          /* address of array of 2-byte s-tags */
1105 	__le32	addr_low;
1106 };
1107 
1108 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1109 
1110 struct i40e_aqc_add_remove_mcast_etag_completion {
1111 	u8	reserved[4];
1112 	__le16	mcast_etags_used;
1113 	__le16	mcast_etags_free;
1114 	__le32	addr_high;
1115 	__le32	addr_low;
1116 
1117 };
1118 
1119 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1120 
1121 /* Update S/E-Tag (direct 0x0259) */
1122 struct i40e_aqc_update_tag {
1123 	__le16	seid;
1124 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT	0
1125 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1126 					I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1127 	__le16	old_tag;
1128 	__le16	new_tag;
1129 	u8	reserved[10];
1130 };
1131 
1132 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1133 
1134 struct i40e_aqc_update_tag_completion {
1135 	u8	reserved[12];
1136 	__le16	tags_used;
1137 	__le16	tags_free;
1138 };
1139 
1140 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1141 
1142 /* Add Control Packet filter (direct 0x025A)
1143  * Remove Control Packet filter (direct 0x025B)
1144  * uses the i40e_aqc_add_oveb_cloud,
1145  * and the generic direct completion structure
1146  */
1147 struct i40e_aqc_add_remove_control_packet_filter {
1148 	u8	mac[6];
1149 	__le16	etype;
1150 	__le16	flags;
1151 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC	0x0001
1152 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP		0x0002
1153 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE	0x0004
1154 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX		0x0008
1155 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX		0x0000
1156 	__le16	seid;
1157 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT	0
1158 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK	(0x3FF << \
1159 				I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1160 	__le16	queue;
1161 	u8	reserved[2];
1162 };
1163 
1164 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1165 
1166 struct i40e_aqc_add_remove_control_packet_filter_completion {
1167 	__le16	mac_etype_used;
1168 	__le16	etype_used;
1169 	__le16	mac_etype_free;
1170 	__le16	etype_free;
1171 	u8	reserved[8];
1172 };
1173 
1174 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1175 
1176 /* Add Cloud filters (indirect 0x025C)
1177  * Remove Cloud filters (indirect 0x025D)
1178  * uses the i40e_aqc_add_remove_cloud_filters,
1179  * and the generic indirect completion structure
1180  */
1181 struct i40e_aqc_add_remove_cloud_filters {
1182 	u8	num_filters;
1183 	u8	reserved;
1184 	__le16	seid;
1185 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0
1186 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \
1187 					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1188 	u8	reserved2[4];
1189 	__le32	addr_high;
1190 	__le32	addr_low;
1191 };
1192 
1193 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1194 
1195 struct i40e_aqc_add_remove_cloud_filters_element_data {
1196 	u8	outer_mac[6];
1197 	u8	inner_mac[6];
1198 	__le16	inner_vlan;
1199 	union {
1200 		struct {
1201 			u8 reserved[12];
1202 			u8 data[4];
1203 		} v4;
1204 		struct {
1205 			u8 data[16];
1206 		} v6;
1207 	} ipaddr;
1208 	__le16	flags;
1209 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0
1210 #define I40E_AQC_ADD_CLOUD_FILTER_MASK			(0x3F << \
1211 					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1212 /* 0x0000 reserved */
1213 #define I40E_AQC_ADD_CLOUD_FILTER_OIP			0x0001
1214 /* 0x0002 reserved */
1215 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN		0x0003
1216 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID	0x0004
1217 /* 0x0005 reserved */
1218 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID		0x0006
1219 /* 0x0007 reserved */
1220 /* 0x0008 reserved */
1221 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC			0x0009
1222 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A
1223 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B
1224 #define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C
1225 
1226 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080
1227 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6
1228 #define I40E_AQC_ADD_CLOUD_VNK_MASK			0x00C0
1229 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4			0
1230 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6			0x0100
1231 
1232 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT		9
1233 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK		0x1E00
1234 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN		0
1235 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC		1
1236 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE			2
1237 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP			3
1238 
1239 	__le32	tenant_id;
1240 	u8	reserved[4];
1241 	__le16	queue_number;
1242 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT		0
1243 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK		(0x3F << \
1244 						 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1245 	u8	reserved2[14];
1246 	/* response section */
1247 	u8	allocation_result;
1248 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS	0x0
1249 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL		0xFF
1250 	u8	response_reserved[7];
1251 };
1252 
1253 struct i40e_aqc_remove_cloud_filters_completion {
1254 	__le16 perfect_ovlan_used;
1255 	__le16 perfect_ovlan_free;
1256 	__le16 vlan_used;
1257 	__le16 vlan_free;
1258 	__le32 addr_high;
1259 	__le32 addr_low;
1260 };
1261 
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1263 
1264 /* Add Mirror Rule (indirect or direct 0x0260)
1265  * Delete Mirror Rule (indirect or direct 0x0261)
1266  * note: some rule types (4,5) do not use an external buffer.
1267  *       take care to set the flags correctly.
1268  */
1269 struct i40e_aqc_add_delete_mirror_rule {
1270 	__le16 seid;
1271 	__le16 rule_type;
1272 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT		0
1273 #define I40E_AQC_MIRROR_RULE_TYPE_MASK		(0x7 << \
1274 						I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1275 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS	1
1276 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS	2
1277 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN		3
1278 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS	4
1279 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS	5
1280 	__le16 num_entries;
1281 	__le16 destination;  /* VSI for add, rule id for delete */
1282 	__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1283 	__le32 addr_low;
1284 };
1285 
1286 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1287 
1288 struct i40e_aqc_add_delete_mirror_rule_completion {
1289 	u8	reserved[2];
1290 	__le16	rule_id;  /* only used on add */
1291 	__le16	mirror_rules_used;
1292 	__le16	mirror_rules_free;
1293 	__le32	addr_high;
1294 	__le32	addr_low;
1295 };
1296 
1297 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1298 
1299 /* DCB 0x03xx*/
1300 
1301 /* PFC Ignore (direct 0x0301)
1302  *    the command and response use the same descriptor structure
1303  */
1304 struct i40e_aqc_pfc_ignore {
1305 	u8	tc_bitmap;
1306 	u8	command_flags; /* unused on response */
1307 #define I40E_AQC_PFC_IGNORE_SET		0x80
1308 #define I40E_AQC_PFC_IGNORE_CLEAR	0x0
1309 	u8	reserved[14];
1310 };
1311 
1312 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1313 
1314 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1315  * with no parameters
1316  */
1317 
1318 /* TX scheduler 0x04xx */
1319 
1320 /* Almost all the indirect commands use
1321  * this generic struct to pass the SEID in param0
1322  */
1323 struct i40e_aqc_tx_sched_ind {
1324 	__le16	vsi_seid;
1325 	u8	reserved[6];
1326 	__le32	addr_high;
1327 	__le32	addr_low;
1328 };
1329 
1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1331 
1332 /* Several commands respond with a set of queue set handles */
1333 struct i40e_aqc_qs_handles_resp {
1334 	__le16 qs_handles[8];
1335 };
1336 
1337 /* Configure VSI BW limits (direct 0x0400) */
1338 struct i40e_aqc_configure_vsi_bw_limit {
1339 	__le16	vsi_seid;
1340 	u8	reserved[2];
1341 	__le16	credit;
1342 	u8	reserved1[2];
1343 	u8	max_credit; /* 0-3, limit = 2^max */
1344 	u8	reserved2[7];
1345 };
1346 
1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1348 
1349 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1350  *    responds with i40e_aqc_qs_handles_resp
1351  */
1352 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1353 	u8	tc_valid_bits;
1354 	u8	reserved[15];
1355 	__le16	tc_bw_credits[8]; /* FW writesback QS handles here */
1356 
1357 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1358 	__le16	tc_bw_max[2];
1359 	u8	reserved1[28];
1360 };
1361 
1362 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1363  *    responds with i40e_aqc_qs_handles_resp
1364  */
1365 struct i40e_aqc_configure_vsi_tc_bw_data {
1366 	u8	tc_valid_bits;
1367 	u8	reserved[3];
1368 	u8	tc_bw_credits[8];
1369 	u8	reserved1[4];
1370 	__le16	qs_handles[8];
1371 };
1372 
1373 /* Query vsi bw configuration (indirect 0x0408) */
1374 struct i40e_aqc_query_vsi_bw_config_resp {
1375 	u8	tc_valid_bits;
1376 	u8	tc_suspended_bits;
1377 	u8	reserved[14];
1378 	__le16	qs_handles[8];
1379 	u8	reserved1[4];
1380 	__le16	port_bw_limit;
1381 	u8	reserved2[2];
1382 	u8	max_bw; /* 0-3, limit = 2^max */
1383 	u8	reserved3[23];
1384 };
1385 
1386 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1387 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1388 	u8	tc_valid_bits;
1389 	u8	reserved[3];
1390 	u8	share_credits[8];
1391 	__le16	credits[8];
1392 
1393 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1394 	__le16	tc_bw_max[2];
1395 };
1396 
1397 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1398 struct i40e_aqc_configure_switching_comp_bw_limit {
1399 	__le16	seid;
1400 	u8	reserved[2];
1401 	__le16	credit;
1402 	u8	reserved1[2];
1403 	u8	max_bw; /* 0-3, limit = 2^max */
1404 	u8	reserved2[7];
1405 };
1406 
1407 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1408 
1409 /* Enable  Physical Port ETS (indirect 0x0413)
1410  * Modify  Physical Port ETS (indirect 0x0414)
1411  * Disable Physical Port ETS (indirect 0x0415)
1412  */
1413 struct i40e_aqc_configure_switching_comp_ets_data {
1414 	u8	reserved[4];
1415 	u8	tc_valid_bits;
1416 	u8	seepage;
1417 #define I40E_AQ_ETS_SEEPAGE_EN_MASK	0x1
1418 	u8	tc_strict_priority_flags;
1419 	u8	reserved1[17];
1420 	u8	tc_bw_share_credits[8];
1421 	u8	reserved2[96];
1422 };
1423 
1424 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1425 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1426 	u8	tc_valid_bits;
1427 	u8	reserved[15];
1428 	__le16	tc_bw_credit[8];
1429 
1430 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1431 	__le16	tc_bw_max[2];
1432 	u8	reserved1[28];
1433 };
1434 
1435 /* Configure Switching Component Bandwidth Allocation per Tc
1436  * (indirect 0x0417)
1437  */
1438 struct i40e_aqc_configure_switching_comp_bw_config_data {
1439 	u8	tc_valid_bits;
1440 	u8	reserved[2];
1441 	u8	absolute_credits; /* bool */
1442 	u8	tc_bw_share_credits[8];
1443 	u8	reserved1[20];
1444 };
1445 
1446 /* Query Switching Component Configuration (indirect 0x0418) */
1447 struct i40e_aqc_query_switching_comp_ets_config_resp {
1448 	u8	tc_valid_bits;
1449 	u8	reserved[35];
1450 	__le16	port_bw_limit;
1451 	u8	reserved1[2];
1452 	u8	tc_bw_max; /* 0-3, limit = 2^max */
1453 	u8	reserved2[23];
1454 };
1455 
1456 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1457 struct i40e_aqc_query_port_ets_config_resp {
1458 	u8	reserved[4];
1459 	u8	tc_valid_bits;
1460 	u8	reserved1;
1461 	u8	tc_strict_priority_bits;
1462 	u8	reserved2;
1463 	u8	tc_bw_share_credits[8];
1464 	__le16	tc_bw_limits[8];
1465 
1466 	/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1467 	__le16	tc_bw_max[2];
1468 	u8	reserved3[32];
1469 };
1470 
1471 /* Query Switching Component Bandwidth Allocation per Traffic Type
1472  * (indirect 0x041A)
1473  */
1474 struct i40e_aqc_query_switching_comp_bw_config_resp {
1475 	u8	tc_valid_bits;
1476 	u8	reserved[2];
1477 	u8	absolute_credits_enable; /* bool */
1478 	u8	tc_bw_share_credits[8];
1479 	__le16	tc_bw_limits[8];
1480 
1481 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1482 	__le16	tc_bw_max[2];
1483 };
1484 
1485 /* Suspend/resume port TX traffic
1486  * (direct 0x041B and 0x041C) uses the generic SEID struct
1487  */
1488 
1489 /* Configure partition BW
1490  * (indirect 0x041D)
1491  */
1492 struct i40e_aqc_configure_partition_bw_data {
1493 	__le16	pf_valid_bits;
1494 	u8	min_bw[16];      /* guaranteed bandwidth */
1495 	u8	max_bw[16];      /* bandwidth limit */
1496 };
1497 
1498 /* Get and set the active HMC resource profile and status.
1499  * (direct 0x0500) and (direct 0x0501)
1500  */
1501 struct i40e_aq_get_set_hmc_resource_profile {
1502 	u8	pm_profile;
1503 	u8	pe_vf_enabled;
1504 	u8	reserved[14];
1505 };
1506 
1507 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1508 
1509 enum i40e_aq_hmc_profile {
1510 	/* I40E_HMC_PROFILE_NO_CHANGE    = 0, reserved */
1511 	I40E_HMC_PROFILE_DEFAULT	= 1,
1512 	I40E_HMC_PROFILE_FAVOR_VF	= 2,
1513 	I40E_HMC_PROFILE_EQUAL		= 3,
1514 };
1515 
1516 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK	0xF
1517 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK	0x3F
1518 
1519 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1520 
1521 /* set in param0 for get phy abilities to report qualified modules */
1522 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES	0x0001
1523 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES	0x0002
1524 
1525 enum i40e_aq_phy_type {
1526 	I40E_PHY_TYPE_SGMII			= 0x0,
1527 	I40E_PHY_TYPE_1000BASE_KX		= 0x1,
1528 	I40E_PHY_TYPE_10GBASE_KX4		= 0x2,
1529 	I40E_PHY_TYPE_10GBASE_KR		= 0x3,
1530 	I40E_PHY_TYPE_40GBASE_KR4		= 0x4,
1531 	I40E_PHY_TYPE_XAUI			= 0x5,
1532 	I40E_PHY_TYPE_XFI			= 0x6,
1533 	I40E_PHY_TYPE_SFI			= 0x7,
1534 	I40E_PHY_TYPE_XLAUI			= 0x8,
1535 	I40E_PHY_TYPE_XLPPI			= 0x9,
1536 	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,
1537 	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,
1538 	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,
1539 	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,
1540 	I40E_PHY_TYPE_100BASE_TX		= 0x11,
1541 	I40E_PHY_TYPE_1000BASE_T		= 0x12,
1542 	I40E_PHY_TYPE_10GBASE_T			= 0x13,
1543 	I40E_PHY_TYPE_10GBASE_SR		= 0x14,
1544 	I40E_PHY_TYPE_10GBASE_LR		= 0x15,
1545 	I40E_PHY_TYPE_10GBASE_SFPP_CU		= 0x16,
1546 	I40E_PHY_TYPE_10GBASE_CR1		= 0x17,
1547 	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,
1548 	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,
1549 	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,
1550 	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,
1551 	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
1552 	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
1553 	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
1554 	I40E_PHY_TYPE_MAX
1555 };
1556 
1557 #define I40E_LINK_SPEED_100MB_SHIFT	0x1
1558 #define I40E_LINK_SPEED_1000MB_SHIFT	0x2
1559 #define I40E_LINK_SPEED_10GB_SHIFT	0x3
1560 #define I40E_LINK_SPEED_40GB_SHIFT	0x4
1561 #define I40E_LINK_SPEED_20GB_SHIFT	0x5
1562 
1563 enum i40e_aq_link_speed {
1564 	I40E_LINK_SPEED_UNKNOWN	= 0,
1565 	I40E_LINK_SPEED_100MB	= (1 << I40E_LINK_SPEED_100MB_SHIFT),
1566 	I40E_LINK_SPEED_1GB	= (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1567 	I40E_LINK_SPEED_10GB	= (1 << I40E_LINK_SPEED_10GB_SHIFT),
1568 	I40E_LINK_SPEED_40GB	= (1 << I40E_LINK_SPEED_40GB_SHIFT),
1569 	I40E_LINK_SPEED_20GB	= (1 << I40E_LINK_SPEED_20GB_SHIFT)
1570 };
1571 
1572 struct i40e_aqc_module_desc {
1573 	u8 oui[3];
1574 	u8 reserved1;
1575 	u8 part_number[16];
1576 	u8 revision[4];
1577 	u8 reserved2[8];
1578 };
1579 
1580 struct i40e_aq_get_phy_abilities_resp {
1581 	__le32	phy_type;       /* bitmap using the above enum for offsets */
1582 	u8	link_speed;     /* bitmap using the above enum bit patterns */
1583 	u8	abilities;
1584 #define I40E_AQ_PHY_FLAG_PAUSE_TX	0x01
1585 #define I40E_AQ_PHY_FLAG_PAUSE_RX	0x02
1586 #define I40E_AQ_PHY_FLAG_LOW_POWER	0x04
1587 #define I40E_AQ_PHY_LINK_ENABLED	0x08
1588 #define I40E_AQ_PHY_AN_ENABLED		0x10
1589 #define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20
1590 	__le16	eee_capability;
1591 #define I40E_AQ_EEE_100BASE_TX		0x0002
1592 #define I40E_AQ_EEE_1000BASE_T		0x0004
1593 #define I40E_AQ_EEE_10GBASE_T		0x0008
1594 #define I40E_AQ_EEE_1000BASE_KX		0x0010
1595 #define I40E_AQ_EEE_10GBASE_KX4		0x0020
1596 #define I40E_AQ_EEE_10GBASE_KR		0x0040
1597 	__le32	eeer_val;
1598 	u8	d3_lpan;
1599 #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
1600 	u8	reserved[3];
1601 	u8	phy_id[4];
1602 	u8	module_type[3];
1603 	u8	qualified_module_count;
1604 #define I40E_AQ_PHY_MAX_QMS		16
1605 	struct i40e_aqc_module_desc	qualified_module[I40E_AQ_PHY_MAX_QMS];
1606 };
1607 
1608 /* Set PHY Config (direct 0x0601) */
1609 struct i40e_aq_set_phy_config { /* same bits as above in all */
1610 	__le32	phy_type;
1611 	u8	link_speed;
1612 	u8	abilities;
1613 /* bits 0-2 use the values from get_phy_abilities_resp */
1614 #define I40E_AQ_PHY_ENABLE_LINK		0x08
1615 #define I40E_AQ_PHY_ENABLE_AN		0x10
1616 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK	0x20
1617 	__le16	eee_capability;
1618 	__le32	eeer;
1619 	u8	low_power_ctrl;
1620 	u8	reserved[3];
1621 };
1622 
1623 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1624 
1625 /* Set MAC Config command data structure (direct 0x0603) */
1626 struct i40e_aq_set_mac_config {
1627 	__le16	max_frame_size;
1628 	u8	params;
1629 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN		0x04
1630 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK	0x78
1631 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT	3
1632 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE	0x0
1633 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX	0xF
1634 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX	0x9
1635 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX	0x8
1636 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX	0x7
1637 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX	0x6
1638 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX	0x5
1639 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX	0x4
1640 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX	0x3
1641 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX	0x2
1642 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX	0x1
1643 	u8	tx_timer_priority; /* bitmap */
1644 	__le16	tx_timer_value;
1645 	__le16	fc_refresh_threshold;
1646 	u8	reserved[8];
1647 };
1648 
1649 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1650 
1651 /* Restart Auto-Negotiation (direct 0x605) */
1652 struct i40e_aqc_set_link_restart_an {
1653 	u8	command;
1654 #define I40E_AQ_PHY_RESTART_AN	0x02
1655 #define I40E_AQ_PHY_LINK_ENABLE	0x04
1656 	u8	reserved[15];
1657 };
1658 
1659 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1660 
1661 /* Get Link Status cmd & response data structure (direct 0x0607) */
1662 struct i40e_aqc_get_link_status {
1663 	__le16	command_flags; /* only field set on command */
1664 #define I40E_AQ_LSE_MASK		0x3
1665 #define I40E_AQ_LSE_NOP			0x0
1666 #define I40E_AQ_LSE_DISABLE		0x2
1667 #define I40E_AQ_LSE_ENABLE		0x3
1668 /* only response uses this flag */
1669 #define I40E_AQ_LSE_IS_ENABLED		0x1
1670 	u8	phy_type;    /* i40e_aq_phy_type   */
1671 	u8	link_speed;  /* i40e_aq_link_speed */
1672 	u8	link_info;
1673 #define I40E_AQ_LINK_UP			0x01
1674 #define I40E_AQ_LINK_FAULT		0x02
1675 #define I40E_AQ_LINK_FAULT_TX		0x04
1676 #define I40E_AQ_LINK_FAULT_RX		0x08
1677 #define I40E_AQ_LINK_FAULT_REMOTE	0x10
1678 #define I40E_AQ_MEDIA_AVAILABLE		0x40
1679 #define I40E_AQ_SIGNAL_DETECT		0x80
1680 	u8	an_info;
1681 #define I40E_AQ_AN_COMPLETED		0x01
1682 #define I40E_AQ_LP_AN_ABILITY		0x02
1683 #define I40E_AQ_PD_FAULT		0x04
1684 #define I40E_AQ_FEC_EN			0x08
1685 #define I40E_AQ_PHY_LOW_POWER		0x10
1686 #define I40E_AQ_LINK_PAUSE_TX		0x20
1687 #define I40E_AQ_LINK_PAUSE_RX		0x40
1688 #define I40E_AQ_QUALIFIED_MODULE	0x80
1689 	u8	ext_info;
1690 #define I40E_AQ_LINK_PHY_TEMP_ALARM	0x01
1691 #define I40E_AQ_LINK_XCESSIVE_ERRORS	0x02
1692 #define I40E_AQ_LINK_TX_SHIFT		0x02
1693 #define I40E_AQ_LINK_TX_MASK		(0x03 << I40E_AQ_LINK_TX_SHIFT)
1694 #define I40E_AQ_LINK_TX_ACTIVE		0x00
1695 #define I40E_AQ_LINK_TX_DRAINED		0x01
1696 #define I40E_AQ_LINK_TX_FLUSHED		0x03
1697 #define I40E_AQ_LINK_FORCED_40G		0x10
1698 	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
1699 	__le16	max_frame_size;
1700 	u8	config;
1701 #define I40E_AQ_CONFIG_CRC_ENA		0x04
1702 #define I40E_AQ_CONFIG_PACING_MASK	0x78
1703 	u8	reserved[5];
1704 };
1705 
1706 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1707 
1708 /* Set event mask command (direct 0x613) */
1709 struct i40e_aqc_set_phy_int_mask {
1710 	u8	reserved[8];
1711 	__le16	event_mask;
1712 #define I40E_AQ_EVENT_LINK_UPDOWN	0x0002
1713 #define I40E_AQ_EVENT_MEDIA_NA		0x0004
1714 #define I40E_AQ_EVENT_LINK_FAULT	0x0008
1715 #define I40E_AQ_EVENT_PHY_TEMP_ALARM	0x0010
1716 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS	0x0020
1717 #define I40E_AQ_EVENT_SIGNAL_DETECT	0x0040
1718 #define I40E_AQ_EVENT_AN_COMPLETED	0x0080
1719 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL	0x0100
1720 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED	0x0200
1721 	u8	reserved1[6];
1722 };
1723 
1724 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1725 
1726 /* Get Local AN advt register (direct 0x0614)
1727  * Set Local AN advt register (direct 0x0615)
1728  * Get Link Partner AN advt register (direct 0x0616)
1729  */
1730 struct i40e_aqc_an_advt_reg {
1731 	__le32	local_an_reg0;
1732 	__le16	local_an_reg1;
1733 	u8	reserved[10];
1734 };
1735 
1736 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1737 
1738 /* Set Loopback mode (0x0618) */
1739 struct i40e_aqc_set_lb_mode {
1740 	__le16	lb_mode;
1741 #define I40E_AQ_LB_PHY_LOCAL	0x01
1742 #define I40E_AQ_LB_PHY_REMOTE	0x02
1743 #define I40E_AQ_LB_MAC_LOCAL	0x04
1744 	u8	reserved[14];
1745 };
1746 
1747 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1748 
1749 /* Set PHY Debug command (0x0622) */
1750 struct i40e_aqc_set_phy_debug {
1751 	u8	command_flags;
1752 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL	0x02
1753 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT	2
1754 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK	(0x03 << \
1755 					I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1756 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE	0x00
1757 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD	0x01
1758 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT	0x02
1759 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10
1760 	u8	reserved[15];
1761 };
1762 
1763 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1764 
1765 enum i40e_aq_phy_reg_type {
1766 	I40E_AQC_PHY_REG_INTERNAL	= 0x1,
1767 	I40E_AQC_PHY_REG_EXERNAL_BASET	= 0x2,
1768 	I40E_AQC_PHY_REG_EXERNAL_MODULE	= 0x3
1769 };
1770 
1771 /* NVM Read command (indirect 0x0701)
1772  * NVM Erase commands (direct 0x0702)
1773  * NVM Update commands (indirect 0x0703)
1774  */
1775 struct i40e_aqc_nvm_update {
1776 	u8	command_flags;
1777 #define I40E_AQ_NVM_LAST_CMD	0x01
1778 #define I40E_AQ_NVM_FLASH_ONLY	0x80
1779 	u8	module_pointer;
1780 	__le16	length;
1781 	__le32	offset;
1782 	__le32	addr_high;
1783 	__le32	addr_low;
1784 };
1785 
1786 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1787 
1788 /* NVM Config Read (indirect 0x0704) */
1789 struct i40e_aqc_nvm_config_read {
1790 	__le16	cmd_flags;
1791 #define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK	1
1792 #define ANVM_READ_SINGLE_FEATURE		0
1793 #define ANVM_READ_MULTIPLE_FEATURES		1
1794 	__le16	element_count;
1795 	__le16	element_id; /* Feature/field ID */
1796 	u8	reserved[2];
1797 	__le32	address_high;
1798 	__le32	address_low;
1799 };
1800 
1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1802 
1803 /* NVM Config Write (indirect 0x0705) */
1804 struct i40e_aqc_nvm_config_write {
1805 	__le16	cmd_flags;
1806 	__le16	element_count;
1807 	u8	reserved[4];
1808 	__le32	address_high;
1809 	__le32	address_low;
1810 };
1811 
1812 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1813 
1814 struct i40e_aqc_nvm_config_data_feature {
1815 	__le16 feature_id;
1816 	__le16 instance_id;
1817 	__le16 feature_options;
1818 	__le16 feature_selection;
1819 };
1820 
1821 struct i40e_aqc_nvm_config_data_immediate_field {
1822 #define ANVM_FEATURE_OR_IMMEDIATE_MASK	0x2
1823 	__le16 field_id;
1824 	__le16 instance_id;
1825 	__le16 field_options;
1826 	__le16 field_value;
1827 };
1828 
1829 /* Send to PF command (indirect 0x0801) id is only used by PF
1830  * Send to VF command (indirect 0x0802) id is only used by PF
1831  * Send to Peer PF command (indirect 0x0803)
1832  */
1833 struct i40e_aqc_pf_vf_message {
1834 	__le32	id;
1835 	u8	reserved[4];
1836 	__le32	addr_high;
1837 	__le32	addr_low;
1838 };
1839 
1840 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1841 
1842 /* Alternate structure */
1843 
1844 /* Direct write (direct 0x0900)
1845  * Direct read (direct 0x0902)
1846  */
1847 struct i40e_aqc_alternate_write {
1848 	__le32 address0;
1849 	__le32 data0;
1850 	__le32 address1;
1851 	__le32 data1;
1852 };
1853 
1854 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1855 
1856 /* Indirect write (indirect 0x0901)
1857  * Indirect read (indirect 0x0903)
1858  */
1859 
1860 struct i40e_aqc_alternate_ind_write {
1861 	__le32 address;
1862 	__le32 length;
1863 	__le32 addr_high;
1864 	__le32 addr_low;
1865 };
1866 
1867 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1868 
1869 /* Done alternate write (direct 0x0904)
1870  * uses i40e_aq_desc
1871  */
1872 struct i40e_aqc_alternate_write_done {
1873 	__le16	cmd_flags;
1874 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK	1
1875 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY	0
1876 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI	1
1877 #define I40E_AQ_ALTERNATE_RESET_NEEDED		2
1878 	u8	reserved[14];
1879 };
1880 
1881 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1882 
1883 /* Set OEM mode (direct 0x0905) */
1884 struct i40e_aqc_alternate_set_mode {
1885 	__le32	mode;
1886 #define I40E_AQ_ALTERNATE_MODE_NONE	0
1887 #define I40E_AQ_ALTERNATE_MODE_OEM	1
1888 	u8	reserved[12];
1889 };
1890 
1891 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1892 
1893 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1894 
1895 /* async events 0x10xx */
1896 
1897 /* Lan Queue Overflow Event (direct, 0x1001) */
1898 struct i40e_aqc_lan_overflow {
1899 	__le32	prtdcb_rupto;
1900 	__le32	otx_ctl;
1901 	u8	reserved[8];
1902 };
1903 
1904 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1905 
1906 /* Get LLDP MIB (indirect 0x0A00) */
1907 struct i40e_aqc_lldp_get_mib {
1908 	u8	type;
1909 	u8	reserved1;
1910 #define I40E_AQ_LLDP_MIB_TYPE_MASK		0x3
1911 #define I40E_AQ_LLDP_MIB_LOCAL			0x0
1912 #define I40E_AQ_LLDP_MIB_REMOTE			0x1
1913 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE	0x2
1914 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK		0xC
1915 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT		0x2
1916 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE	0x0
1917 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR	0x1
1918 #define I40E_AQ_LLDP_TX_SHIFT			0x4
1919 #define I40E_AQ_LLDP_TX_MASK			(0x03 << I40E_AQ_LLDP_TX_SHIFT)
1920 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1921 	__le16	local_len;
1922 	__le16	remote_len;
1923 	u8	reserved2[2];
1924 	__le32	addr_high;
1925 	__le32	addr_low;
1926 };
1927 
1928 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1929 
1930 /* Configure LLDP MIB Change Event (direct 0x0A01)
1931  * also used for the event (with type in the command field)
1932  */
1933 struct i40e_aqc_lldp_update_mib {
1934 	u8	command;
1935 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE	0x0
1936 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE	0x1
1937 	u8	reserved[7];
1938 	__le32	addr_high;
1939 	__le32	addr_low;
1940 };
1941 
1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1943 
1944 /* Add LLDP TLV (indirect 0x0A02)
1945  * Delete LLDP TLV (indirect 0x0A04)
1946  */
1947 struct i40e_aqc_lldp_add_tlv {
1948 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
1949 	u8	reserved1[1];
1950 	__le16	len;
1951 	u8	reserved2[4];
1952 	__le32	addr_high;
1953 	__le32	addr_low;
1954 };
1955 
1956 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1957 
1958 /* Update LLDP TLV (indirect 0x0A03) */
1959 struct i40e_aqc_lldp_update_tlv {
1960 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
1961 	u8	reserved;
1962 	__le16	old_len;
1963 	__le16	new_offset;
1964 	__le16	new_len;
1965 	__le32	addr_high;
1966 	__le32	addr_low;
1967 };
1968 
1969 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1970 
1971 /* Stop LLDP (direct 0x0A05) */
1972 struct i40e_aqc_lldp_stop {
1973 	u8	command;
1974 #define I40E_AQ_LLDP_AGENT_STOP		0x0
1975 #define I40E_AQ_LLDP_AGENT_SHUTDOWN	0x1
1976 	u8	reserved[15];
1977 };
1978 
1979 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1980 
1981 /* Start LLDP (direct 0x0A06) */
1982 
1983 struct i40e_aqc_lldp_start {
1984 	u8	command;
1985 #define I40E_AQ_LLDP_AGENT_START	0x1
1986 	u8	reserved[15];
1987 };
1988 
1989 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1990 
1991 /* Get CEE DCBX Oper Config (0x0A07)
1992  * uses the generic descriptor struct
1993  * returns below as indirect response
1994  */
1995 
1996 #define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
1997 #define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
1998 #define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
1999 #define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2000 #define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2001 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2002 #define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2003 #define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2004 #define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2005 #define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2006 #define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2007 #define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2008 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2009 	u8	reserved1;
2010 	u8	oper_num_tc;
2011 	u8	oper_prio_tc[4];
2012 	u8	reserved2;
2013 	u8	oper_tc_bw[8];
2014 	u8	oper_pfc_en;
2015 	u8	reserved3;
2016 	__le16	oper_app_prio;
2017 	u8	reserved4;
2018 	__le16	tlv_status;
2019 };
2020 
2021 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2022 
2023 struct i40e_aqc_get_cee_dcb_cfg_resp {
2024 	u8	oper_num_tc;
2025 	u8	oper_prio_tc[4];
2026 	u8	oper_tc_bw[8];
2027 	u8	oper_pfc_en;
2028 	__le16	oper_app_prio;
2029 	__le32	tlv_status;
2030 	u8	reserved[12];
2031 };
2032 
2033 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2034 
2035 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2036 struct i40e_aqc_add_udp_tunnel {
2037 	__le16	udp_port;
2038 	u8	reserved0[3];
2039 	u8	protocol_type;
2040 #define I40E_AQC_TUNNEL_TYPE_VXLAN	0x00
2041 #define I40E_AQC_TUNNEL_TYPE_NGE	0x01
2042 #define I40E_AQC_TUNNEL_TYPE_TEREDO	0x10
2043 	u8	reserved1[10];
2044 };
2045 
2046 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2047 
2048 struct i40e_aqc_add_udp_tunnel_completion {
2049 	__le16	udp_port;
2050 	u8	filter_entry_index;
2051 	u8	multiple_pfs;
2052 #define I40E_AQC_SINGLE_PF		0x0
2053 #define I40E_AQC_MULTIPLE_PFS		0x1
2054 	u8	total_filters;
2055 	u8	reserved[11];
2056 };
2057 
2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2059 
2060 /* remove UDP Tunnel command (0x0B01) */
2061 struct i40e_aqc_remove_udp_tunnel {
2062 	u8	reserved[2];
2063 	u8	index; /* 0 to 15 */
2064 	u8	reserved2[13];
2065 };
2066 
2067 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2068 
2069 struct i40e_aqc_del_udp_tunnel_completion {
2070 	__le16	udp_port;
2071 	u8	index; /* 0 to 15 */
2072 	u8	multiple_pfs;
2073 	u8	total_filters_used;
2074 	u8	reserved1[11];
2075 };
2076 
2077 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2078 
2079 /* tunnel key structure 0x0B10 */
2080 
2081 struct i40e_aqc_tunnel_key_structure {
2082 	u8	key1_off;
2083 	u8	key2_off;
2084 	u8	key1_len;  /* 0 to 15 */
2085 	u8	key2_len;  /* 0 to 15 */
2086 	u8	flags;
2087 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE	0x01
2088 /* response flags */
2089 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS	0x01
2090 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED	0x02
2091 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN	0x03
2092 	u8	network_key_index;
2093 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN		0x0
2094 #define I40E_AQC_NETWORK_KEY_INDEX_NGE			0x1
2095 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP	0x2
2096 #define I40E_AQC_NETWORK_KEY_INDEX_GRE			0x3
2097 	u8	reserved[10];
2098 };
2099 
2100 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2101 
2102 /* OEM mode commands (direct 0xFE0x) */
2103 struct i40e_aqc_oem_param_change {
2104 	__le32	param_type;
2105 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL	0
2106 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL	1
2107 #define I40E_AQ_OEM_PARAM_MAC		2
2108 	__le32	param_value1;
2109 	u8	param_value2[8];
2110 };
2111 
2112 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2113 
2114 struct i40e_aqc_oem_state_change {
2115 	__le32	state;
2116 #define I40E_AQ_OEM_STATE_LINK_DOWN	0x0
2117 #define I40E_AQ_OEM_STATE_LINK_UP	0x1
2118 	u8	reserved[12];
2119 };
2120 
2121 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2122 
2123 /* debug commands */
2124 
2125 /* get device id (0xFF00) uses the generic structure */
2126 
2127 /* set test more (0xFF01, internal) */
2128 
2129 struct i40e_acq_set_test_mode {
2130 	u8	mode;
2131 #define I40E_AQ_TEST_PARTIAL	0
2132 #define I40E_AQ_TEST_FULL	1
2133 #define I40E_AQ_TEST_NVM	2
2134 	u8	reserved[3];
2135 	u8	command;
2136 #define I40E_AQ_TEST_OPEN	0
2137 #define I40E_AQ_TEST_CLOSE	1
2138 #define I40E_AQ_TEST_INC	2
2139 	u8	reserved2[3];
2140 	__le32	address_high;
2141 	__le32	address_low;
2142 };
2143 
2144 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2145 
2146 /* Debug Read Register command (0xFF03)
2147  * Debug Write Register command (0xFF04)
2148  */
2149 struct i40e_aqc_debug_reg_read_write {
2150 	__le32 reserved;
2151 	__le32 address;
2152 	__le32 value_high;
2153 	__le32 value_low;
2154 };
2155 
2156 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2157 
2158 /* Scatter/gather Reg Read  (indirect 0xFF05)
2159  * Scatter/gather Reg Write (indirect 0xFF06)
2160  */
2161 
2162 /* i40e_aq_desc is used for the command */
2163 struct i40e_aqc_debug_reg_sg_element_data {
2164 	__le32 address;
2165 	__le32 value;
2166 };
2167 
2168 /* Debug Modify register (direct 0xFF07) */
2169 struct i40e_aqc_debug_modify_reg {
2170 	__le32 address;
2171 	__le32 value;
2172 	__le32 clear_mask;
2173 	__le32 set_mask;
2174 };
2175 
2176 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2177 
2178 /* dump internal data (0xFF08, indirect) */
2179 
2180 #define I40E_AQ_CLUSTER_ID_AUX		0
2181 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU	1
2182 #define I40E_AQ_CLUSTER_ID_TXSCHED	2
2183 #define I40E_AQ_CLUSTER_ID_HMC		3
2184 #define I40E_AQ_CLUSTER_ID_MAC0		4
2185 #define I40E_AQ_CLUSTER_ID_MAC1		5
2186 #define I40E_AQ_CLUSTER_ID_MAC2		6
2187 #define I40E_AQ_CLUSTER_ID_MAC3		7
2188 #define I40E_AQ_CLUSTER_ID_DCB		8
2189 #define I40E_AQ_CLUSTER_ID_EMP_MEM	9
2190 #define I40E_AQ_CLUSTER_ID_PKT_BUF	10
2191 #define I40E_AQ_CLUSTER_ID_ALTRAM	11
2192 
2193 struct i40e_aqc_debug_dump_internals {
2194 	u8	cluster_id;
2195 	u8	table_id;
2196 	__le16	data_size;
2197 	__le32	idx;
2198 	__le32	address_high;
2199 	__le32	address_low;
2200 };
2201 
2202 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2203 
2204 struct i40e_aqc_debug_modify_internals {
2205 	u8	cluster_id;
2206 	u8	cluster_specific_params[7];
2207 	__le32	address_high;
2208 	__le32	address_low;
2209 };
2210 
2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2212 
2213 #endif
2214