1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 38 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 39 40 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 41 I40E_FW_API_VERSION_MINOR_X710 : \ 42 I40E_FW_API_VERSION_MINOR_X722) 43 44 /* API version 1.7 implements additional link and PHY-specific APIs */ 45 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 i40e_aqc_opc_set_switch_config = 0x0205, 165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167 168 i40e_aqc_opc_add_vsi = 0x0210, 169 i40e_aqc_opc_update_vsi_parameters = 0x0211, 170 i40e_aqc_opc_get_vsi_parameters = 0x0212, 171 172 i40e_aqc_opc_add_pv = 0x0220, 173 i40e_aqc_opc_update_pv_parameters = 0x0221, 174 i40e_aqc_opc_get_pv_parameters = 0x0222, 175 176 i40e_aqc_opc_add_veb = 0x0230, 177 i40e_aqc_opc_update_veb_parameters = 0x0231, 178 i40e_aqc_opc_get_veb_parameters = 0x0232, 179 180 i40e_aqc_opc_delete_element = 0x0243, 181 182 i40e_aqc_opc_add_macvlan = 0x0250, 183 i40e_aqc_opc_remove_macvlan = 0x0251, 184 i40e_aqc_opc_add_vlan = 0x0252, 185 i40e_aqc_opc_remove_vlan = 0x0253, 186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 187 i40e_aqc_opc_add_tag = 0x0255, 188 i40e_aqc_opc_remove_tag = 0x0256, 189 i40e_aqc_opc_add_multicast_etag = 0x0257, 190 i40e_aqc_opc_remove_multicast_etag = 0x0258, 191 i40e_aqc_opc_update_tag = 0x0259, 192 i40e_aqc_opc_add_control_packet_filter = 0x025A, 193 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 194 i40e_aqc_opc_add_cloud_filters = 0x025C, 195 i40e_aqc_opc_remove_cloud_filters = 0x025D, 196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 197 198 i40e_aqc_opc_add_mirror_rule = 0x0260, 199 i40e_aqc_opc_delete_mirror_rule = 0x0261, 200 201 /* Pipeline Personalization Profile */ 202 i40e_aqc_opc_write_personalization_profile = 0x0270, 203 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 204 205 /* DCB commands */ 206 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 207 i40e_aqc_opc_dcb_updated = 0x0302, 208 209 /* TX scheduler */ 210 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 211 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 212 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 213 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 214 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 215 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 216 217 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 218 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 219 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 220 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 221 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 222 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 223 i40e_aqc_opc_query_port_ets_config = 0x0419, 224 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 225 i40e_aqc_opc_suspend_port_tx = 0x041B, 226 i40e_aqc_opc_resume_port_tx = 0x041C, 227 i40e_aqc_opc_configure_partition_bw = 0x041D, 228 /* hmc */ 229 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 230 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 231 232 /* phy commands*/ 233 i40e_aqc_opc_get_phy_abilities = 0x0600, 234 i40e_aqc_opc_set_phy_config = 0x0601, 235 i40e_aqc_opc_set_mac_config = 0x0603, 236 i40e_aqc_opc_set_link_restart_an = 0x0605, 237 i40e_aqc_opc_get_link_status = 0x0607, 238 i40e_aqc_opc_set_phy_int_mask = 0x0613, 239 i40e_aqc_opc_get_local_advt_reg = 0x0614, 240 i40e_aqc_opc_set_local_advt_reg = 0x0615, 241 i40e_aqc_opc_get_partner_advt = 0x0616, 242 i40e_aqc_opc_set_lb_modes = 0x0618, 243 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 244 i40e_aqc_opc_set_phy_debug = 0x0622, 245 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 246 i40e_aqc_opc_run_phy_activity = 0x0626, 247 i40e_aqc_opc_set_phy_register = 0x0628, 248 i40e_aqc_opc_get_phy_register = 0x0629, 249 250 /* NVM commands */ 251 i40e_aqc_opc_nvm_read = 0x0701, 252 i40e_aqc_opc_nvm_erase = 0x0702, 253 i40e_aqc_opc_nvm_update = 0x0703, 254 i40e_aqc_opc_nvm_config_read = 0x0704, 255 i40e_aqc_opc_nvm_config_write = 0x0705, 256 i40e_aqc_opc_oem_post_update = 0x0720, 257 i40e_aqc_opc_thermal_sensor = 0x0721, 258 259 /* virtualization commands */ 260 i40e_aqc_opc_send_msg_to_pf = 0x0801, 261 i40e_aqc_opc_send_msg_to_vf = 0x0802, 262 i40e_aqc_opc_send_msg_to_peer = 0x0803, 263 264 /* alternate structure */ 265 i40e_aqc_opc_alternate_write = 0x0900, 266 i40e_aqc_opc_alternate_write_indirect = 0x0901, 267 i40e_aqc_opc_alternate_read = 0x0902, 268 i40e_aqc_opc_alternate_read_indirect = 0x0903, 269 i40e_aqc_opc_alternate_write_done = 0x0904, 270 i40e_aqc_opc_alternate_set_mode = 0x0905, 271 i40e_aqc_opc_alternate_clear_port = 0x0906, 272 273 /* LLDP commands */ 274 i40e_aqc_opc_lldp_get_mib = 0x0A00, 275 i40e_aqc_opc_lldp_update_mib = 0x0A01, 276 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 277 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 278 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 279 i40e_aqc_opc_lldp_stop = 0x0A05, 280 i40e_aqc_opc_lldp_start = 0x0A06, 281 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 282 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 283 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 284 285 /* Tunnel commands */ 286 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 287 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 288 i40e_aqc_opc_set_rss_key = 0x0B02, 289 i40e_aqc_opc_set_rss_lut = 0x0B03, 290 i40e_aqc_opc_get_rss_key = 0x0B04, 291 i40e_aqc_opc_get_rss_lut = 0x0B05, 292 293 /* Async Events */ 294 i40e_aqc_opc_event_lan_overflow = 0x1001, 295 296 /* OEM commands */ 297 i40e_aqc_opc_oem_parameter_change = 0xFE00, 298 i40e_aqc_opc_oem_device_status_change = 0xFE01, 299 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 300 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 301 302 /* debug commands */ 303 i40e_aqc_opc_debug_read_reg = 0xFF03, 304 i40e_aqc_opc_debug_write_reg = 0xFF04, 305 i40e_aqc_opc_debug_modify_reg = 0xFF07, 306 i40e_aqc_opc_debug_dump_internals = 0xFF08, 307 }; 308 309 /* command structures and indirect data structures */ 310 311 /* Structure naming conventions: 312 * - no suffix for direct command descriptor structures 313 * - _data for indirect sent data 314 * - _resp for indirect return data (data which is both will use _data) 315 * - _completion for direct return data 316 * - _element_ for repeated elements (may also be _data or _resp) 317 * 318 * Command structures are expected to overlay the params.raw member of the basic 319 * descriptor, and as such cannot exceed 16 bytes in length. 320 */ 321 322 /* This macro is used to generate a compilation error if a structure 323 * is not exactly the correct length. It gives a divide by zero error if the 324 * structure is not of the correct size, otherwise it creates an enum that is 325 * never used. 326 */ 327 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 328 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 329 330 /* This macro is used extensively to ensure that command structures are 16 331 * bytes in length as they have to map to the raw array of that size. 332 */ 333 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 334 335 /* internal (0x00XX) commands */ 336 337 /* Get version (direct 0x0001) */ 338 struct i40e_aqc_get_version { 339 __le32 rom_ver; 340 __le32 fw_build; 341 __le16 fw_major; 342 __le16 fw_minor; 343 __le16 api_major; 344 __le16 api_minor; 345 }; 346 347 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 348 349 /* Send driver version (indirect 0x0002) */ 350 struct i40e_aqc_driver_version { 351 u8 driver_major_ver; 352 u8 driver_minor_ver; 353 u8 driver_build_ver; 354 u8 driver_subbuild_ver; 355 u8 reserved[4]; 356 __le32 address_high; 357 __le32 address_low; 358 }; 359 360 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 361 362 /* Queue Shutdown (direct 0x0003) */ 363 struct i40e_aqc_queue_shutdown { 364 __le32 driver_unloading; 365 #define I40E_AQ_DRIVER_UNLOADING 0x1 366 u8 reserved[12]; 367 }; 368 369 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 370 371 /* Set PF context (0x0004, direct) */ 372 struct i40e_aqc_set_pf_context { 373 u8 pf_id; 374 u8 reserved[15]; 375 }; 376 377 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 378 379 /* Request resource ownership (direct 0x0008) 380 * Release resource ownership (direct 0x0009) 381 */ 382 #define I40E_AQ_RESOURCE_NVM 1 383 #define I40E_AQ_RESOURCE_SDP 2 384 #define I40E_AQ_RESOURCE_ACCESS_READ 1 385 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 386 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 387 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 388 389 struct i40e_aqc_request_resource { 390 __le16 resource_id; 391 __le16 access_type; 392 __le32 timeout; 393 __le32 resource_number; 394 u8 reserved[4]; 395 }; 396 397 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 398 399 /* Get function capabilities (indirect 0x000A) 400 * Get device capabilities (indirect 0x000B) 401 */ 402 struct i40e_aqc_list_capabilites { 403 u8 command_flags; 404 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 405 u8 pf_index; 406 u8 reserved[2]; 407 __le32 count; 408 __le32 addr_high; 409 __le32 addr_low; 410 }; 411 412 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 413 414 struct i40e_aqc_list_capabilities_element_resp { 415 __le16 id; 416 u8 major_rev; 417 u8 minor_rev; 418 __le32 number; 419 __le32 logical_id; 420 __le32 phys_id; 421 u8 reserved[16]; 422 }; 423 424 /* list of caps */ 425 426 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 427 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 428 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 429 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 430 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 431 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 432 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 433 #define I40E_AQ_CAP_ID_SRIOV 0x0012 434 #define I40E_AQ_CAP_ID_VF 0x0013 435 #define I40E_AQ_CAP_ID_VMDQ 0x0014 436 #define I40E_AQ_CAP_ID_8021QBG 0x0015 437 #define I40E_AQ_CAP_ID_8021QBR 0x0016 438 #define I40E_AQ_CAP_ID_VSI 0x0017 439 #define I40E_AQ_CAP_ID_DCB 0x0018 440 #define I40E_AQ_CAP_ID_FCOE 0x0021 441 #define I40E_AQ_CAP_ID_ISCSI 0x0022 442 #define I40E_AQ_CAP_ID_RSS 0x0040 443 #define I40E_AQ_CAP_ID_RXQ 0x0041 444 #define I40E_AQ_CAP_ID_TXQ 0x0042 445 #define I40E_AQ_CAP_ID_MSIX 0x0043 446 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 447 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 448 #define I40E_AQ_CAP_ID_1588 0x0046 449 #define I40E_AQ_CAP_ID_IWARP 0x0051 450 #define I40E_AQ_CAP_ID_LED 0x0061 451 #define I40E_AQ_CAP_ID_SDP 0x0062 452 #define I40E_AQ_CAP_ID_MDIO 0x0063 453 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 454 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 455 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 456 #define I40E_AQ_CAP_ID_CEM 0x00F2 457 458 /* Set CPPM Configuration (direct 0x0103) */ 459 struct i40e_aqc_cppm_configuration { 460 __le16 command_flags; 461 #define I40E_AQ_CPPM_EN_LTRC 0x0800 462 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 463 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 464 #define I40E_AQ_CPPM_EN_HPTC 0x4000 465 #define I40E_AQ_CPPM_EN_DMARC 0x8000 466 __le16 ttlx; 467 __le32 dmacr; 468 __le16 dmcth; 469 u8 hptc; 470 u8 reserved; 471 __le32 pfltrc; 472 }; 473 474 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 475 476 /* Set ARP Proxy command / response (indirect 0x0104) */ 477 struct i40e_aqc_arp_proxy_data { 478 __le16 command_flags; 479 #define I40E_AQ_ARP_INIT_IPV4 0x0800 480 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 481 #define I40E_AQ_ARP_ENA 0x2000 482 #define I40E_AQ_ARP_ADD_IPV4 0x4000 483 #define I40E_AQ_ARP_DEL_IPV4 0x8000 484 __le16 table_id; 485 __le32 enabled_offloads; 486 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 487 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 488 __le32 ip_addr; 489 u8 mac_addr[6]; 490 u8 reserved[2]; 491 }; 492 493 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 494 495 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 496 struct i40e_aqc_ns_proxy_data { 497 __le16 table_idx_mac_addr_0; 498 __le16 table_idx_mac_addr_1; 499 __le16 table_idx_ipv6_0; 500 __le16 table_idx_ipv6_1; 501 __le16 control; 502 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 503 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 504 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 505 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 506 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 507 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 508 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 509 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 510 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 511 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 512 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 513 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 514 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 515 u8 mac_addr_0[6]; 516 u8 mac_addr_1[6]; 517 u8 local_mac_addr[6]; 518 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 519 u8 ipv6_addr_1[16]; 520 }; 521 522 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 523 524 /* Manage LAA Command (0x0106) - obsolete */ 525 struct i40e_aqc_mng_laa { 526 __le16 command_flags; 527 #define I40E_AQ_LAA_FLAG_WR 0x8000 528 u8 reserved[2]; 529 __le32 sal; 530 __le16 sah; 531 u8 reserved2[6]; 532 }; 533 534 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 535 536 /* Manage MAC Address Read Command (indirect 0x0107) */ 537 struct i40e_aqc_mac_address_read { 538 __le16 command_flags; 539 #define I40E_AQC_LAN_ADDR_VALID 0x10 540 #define I40E_AQC_SAN_ADDR_VALID 0x20 541 #define I40E_AQC_PORT_ADDR_VALID 0x40 542 #define I40E_AQC_WOL_ADDR_VALID 0x80 543 #define I40E_AQC_MC_MAG_EN_VALID 0x100 544 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 545 u8 reserved[6]; 546 __le32 addr_high; 547 __le32 addr_low; 548 }; 549 550 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 551 552 struct i40e_aqc_mac_address_read_data { 553 u8 pf_lan_mac[6]; 554 u8 pf_san_mac[6]; 555 u8 port_mac[6]; 556 u8 pf_wol_mac[6]; 557 }; 558 559 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 560 561 /* Manage MAC Address Write Command (0x0108) */ 562 struct i40e_aqc_mac_address_write { 563 __le16 command_flags; 564 #define I40E_AQC_MC_MAG_EN 0x0100 565 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 566 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 567 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 568 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 569 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 570 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 571 572 __le16 mac_sah; 573 __le32 mac_sal; 574 u8 reserved[8]; 575 }; 576 577 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 578 579 /* PXE commands (0x011x) */ 580 581 /* Clear PXE Command and response (direct 0x0110) */ 582 struct i40e_aqc_clear_pxe { 583 u8 rx_cnt; 584 u8 reserved[15]; 585 }; 586 587 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 588 589 /* Set WoL Filter (0x0120) */ 590 591 struct i40e_aqc_set_wol_filter { 592 __le16 filter_index; 593 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 594 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 595 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 596 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 597 598 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 599 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 600 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 601 __le16 cmd_flags; 602 #define I40E_AQC_SET_WOL_FILTER 0x8000 603 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 604 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 605 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 606 __le16 valid_flags; 607 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 608 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 609 u8 reserved[2]; 610 __le32 address_high; 611 __le32 address_low; 612 }; 613 614 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 615 616 struct i40e_aqc_set_wol_filter_data { 617 u8 filter[128]; 618 u8 mask[16]; 619 }; 620 621 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 622 623 /* Get Wake Reason (0x0121) */ 624 625 struct i40e_aqc_get_wake_reason_completion { 626 u8 reserved_1[2]; 627 __le16 wake_reason; 628 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 630 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 633 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 634 u8 reserved_2[12]; 635 }; 636 637 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 638 639 /* Switch configuration commands (0x02xx) */ 640 641 /* Used by many indirect commands that only pass an seid and a buffer in the 642 * command 643 */ 644 struct i40e_aqc_switch_seid { 645 __le16 seid; 646 u8 reserved[6]; 647 __le32 addr_high; 648 __le32 addr_low; 649 }; 650 651 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 652 653 /* Get Switch Configuration command (indirect 0x0200) 654 * uses i40e_aqc_switch_seid for the descriptor 655 */ 656 struct i40e_aqc_get_switch_config_header_resp { 657 __le16 num_reported; 658 __le16 num_total; 659 u8 reserved[12]; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 663 664 struct i40e_aqc_switch_config_element_resp { 665 u8 element_type; 666 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 667 #define I40E_AQ_SW_ELEM_TYPE_PF 2 668 #define I40E_AQ_SW_ELEM_TYPE_VF 3 669 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 670 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 671 #define I40E_AQ_SW_ELEM_TYPE_PV 16 672 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 673 #define I40E_AQ_SW_ELEM_TYPE_PA 18 674 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 675 u8 revision; 676 #define I40E_AQ_SW_ELEM_REV_1 1 677 __le16 seid; 678 __le16 uplink_seid; 679 __le16 downlink_seid; 680 u8 reserved[3]; 681 u8 connection_type; 682 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 683 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 684 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 685 __le16 scheduler_id; 686 __le16 element_info; 687 }; 688 689 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 690 691 /* Get Switch Configuration (indirect 0x0200) 692 * an array of elements are returned in the response buffer 693 * the first in the array is the header, remainder are elements 694 */ 695 struct i40e_aqc_get_switch_config_resp { 696 struct i40e_aqc_get_switch_config_header_resp header; 697 struct i40e_aqc_switch_config_element_resp element[1]; 698 }; 699 700 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 701 702 /* Add Statistics (direct 0x0201) 703 * Remove Statistics (direct 0x0202) 704 */ 705 struct i40e_aqc_add_remove_statistics { 706 __le16 seid; 707 __le16 vlan; 708 __le16 stat_index; 709 u8 reserved[10]; 710 }; 711 712 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 713 714 /* Set Port Parameters command (direct 0x0203) */ 715 struct i40e_aqc_set_port_parameters { 716 __le16 command_flags; 717 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 718 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 719 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 720 __le16 bad_frame_vsi; 721 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 723 __le16 default_seid; /* reserved for command */ 724 u8 reserved[10]; 725 }; 726 727 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 728 729 /* Get Switch Resource Allocation (indirect 0x0204) */ 730 struct i40e_aqc_get_switch_resource_alloc { 731 u8 num_entries; /* reserved for command */ 732 u8 reserved[7]; 733 __le32 addr_high; 734 __le32 addr_low; 735 }; 736 737 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 738 739 /* expect an array of these structs in the response buffer */ 740 struct i40e_aqc_switch_resource_alloc_element_resp { 741 u8 resource_type; 742 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 743 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 744 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 745 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 746 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 747 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 748 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 749 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 750 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 751 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 752 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 753 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 754 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 755 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 756 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 757 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 758 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 759 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 760 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 761 u8 reserved1; 762 __le16 guaranteed; 763 __le16 total; 764 __le16 used; 765 __le16 total_unalloced; 766 u8 reserved2[6]; 767 }; 768 769 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 770 771 /* Set Switch Configuration (direct 0x0205) */ 772 struct i40e_aqc_set_switch_config { 773 __le16 flags; 774 /* flags used for both fields below */ 775 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 776 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 777 __le16 valid_flags; 778 /* The ethertype in switch_tag is dropped on ingress and used 779 * internally by the switch. Set this to zero for the default 780 * of 0x88a8 (802.1ad). Should be zero for firmware API 781 * versions lower than 1.7. 782 */ 783 __le16 switch_tag; 784 /* The ethertypes in first_tag and second_tag are used to 785 * match the outer and inner VLAN tags (respectively) when HW 786 * double VLAN tagging is enabled via the set port parameters 787 * AQ command. Otherwise these are both ignored. Set them to 788 * zero for their defaults of 0x8100 (802.1Q). Should be zero 789 * for firmware API versions lower than 1.7. 790 */ 791 __le16 first_tag; 792 __le16 second_tag; 793 /* Next byte is split into following: 794 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 795 * Bit 6 : 0 : Destination Port, 1: source port 796 * Bit 5..4 : L4 type 797 * 0: rsvd 798 * 1: TCP 799 * 2: UDP 800 * 3: Both TCP and UDP 801 * Bits 3:0 Mode 802 * 0: default mode 803 * 1: L4 port only mode 804 * 2: non-tunneled mode 805 * 3: tunneled mode 806 */ 807 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 808 809 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 810 811 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 812 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 813 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 814 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 815 816 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 817 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 818 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 819 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 820 u8 mode; 821 u8 rsvd5[5]; 822 }; 823 824 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 825 826 /* Read Receive control registers (direct 0x0206) 827 * Write Receive control registers (direct 0x0207) 828 * used for accessing Rx control registers that can be 829 * slow and need special handling when under high Rx load 830 */ 831 struct i40e_aqc_rx_ctl_reg_read_write { 832 __le32 reserved1; 833 __le32 address; 834 __le32 reserved2; 835 __le32 value; 836 }; 837 838 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 839 840 /* Add VSI (indirect 0x0210) 841 * this indirect command uses struct i40e_aqc_vsi_properties_data 842 * as the indirect buffer (128 bytes) 843 * 844 * Update VSI (indirect 0x211) 845 * uses the same data structure as Add VSI 846 * 847 * Get VSI (indirect 0x0212) 848 * uses the same completion and data structure as Add VSI 849 */ 850 struct i40e_aqc_add_get_update_vsi { 851 __le16 uplink_seid; 852 u8 connection_type; 853 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 854 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 855 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 856 u8 reserved1; 857 u8 vf_id; 858 u8 reserved2; 859 __le16 vsi_flags; 860 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 861 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 862 #define I40E_AQ_VSI_TYPE_VF 0x0 863 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 864 #define I40E_AQ_VSI_TYPE_PF 0x2 865 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 866 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 867 __le32 addr_high; 868 __le32 addr_low; 869 }; 870 871 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 872 873 struct i40e_aqc_add_get_update_vsi_completion { 874 __le16 seid; 875 __le16 vsi_number; 876 __le16 vsi_used; 877 __le16 vsi_free; 878 __le32 addr_high; 879 __le32 addr_low; 880 }; 881 882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 883 884 struct i40e_aqc_vsi_properties_data { 885 /* first 96 byte are written by SW */ 886 __le16 valid_sections; 887 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 888 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 889 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 890 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 891 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 892 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 893 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 894 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 895 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 896 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 897 /* switch section */ 898 __le16 switch_id; /* 12bit id combined with flags below */ 899 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 900 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 901 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 902 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 903 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 904 u8 sw_reserved[2]; 905 /* security section */ 906 u8 sec_flags; 907 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 908 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 909 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 910 u8 sec_reserved; 911 /* VLAN section */ 912 __le16 pvid; /* VLANS include priority bits */ 913 __le16 fcoe_pvid; 914 u8 port_vlan_flags; 915 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 916 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 917 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 918 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 919 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 920 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 921 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 922 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 923 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 924 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 925 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 926 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 927 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 928 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 929 u8 pvlan_reserved[3]; 930 /* ingress egress up sections */ 931 __le32 ingress_table; /* bitmap, 3 bits per up */ 932 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 933 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 934 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 935 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 936 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 937 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 938 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 939 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 940 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 941 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 942 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 943 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 944 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 945 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 946 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 947 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 948 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 949 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 950 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 951 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 952 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 953 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 954 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 955 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 956 __le32 egress_table; /* same defines as for ingress table */ 957 /* cascaded PV section */ 958 __le16 cas_pv_tag; 959 u8 cas_pv_flags; 960 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 961 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 962 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 963 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 964 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 965 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 966 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 967 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 968 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 969 u8 cas_pv_reserved; 970 /* queue mapping section */ 971 __le16 mapping_flags; 972 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 973 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 974 __le16 queue_mapping[16]; 975 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 976 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 977 __le16 tc_mapping[8]; 978 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 979 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 980 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 981 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 982 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 983 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 984 /* queueing option section */ 985 u8 queueing_opt_flags; 986 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 987 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 988 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 989 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 990 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 991 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 992 u8 queueing_opt_reserved[3]; 993 /* scheduler section */ 994 u8 up_enable_bits; 995 u8 sched_reserved; 996 /* outer up section */ 997 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 998 u8 cmd_reserved[8]; 999 /* last 32 bytes are written by FW */ 1000 __le16 qs_handle[8]; 1001 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1002 __le16 stat_counter_idx; 1003 __le16 sched_id; 1004 u8 resp_reserved[12]; 1005 }; 1006 1007 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1008 1009 /* Add Port Virtualizer (direct 0x0220) 1010 * also used for update PV (direct 0x0221) but only flags are used 1011 * (IS_CTRL_PORT only works on add PV) 1012 */ 1013 struct i40e_aqc_add_update_pv { 1014 __le16 command_flags; 1015 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1016 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1017 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1018 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1019 __le16 uplink_seid; 1020 __le16 connected_seid; 1021 u8 reserved[10]; 1022 }; 1023 1024 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1025 1026 struct i40e_aqc_add_update_pv_completion { 1027 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1028 __le16 pv_seid; 1029 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1030 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1031 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1032 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1033 u8 reserved[14]; 1034 }; 1035 1036 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1037 1038 /* Get PV Params (direct 0x0222) 1039 * uses i40e_aqc_switch_seid for the descriptor 1040 */ 1041 1042 struct i40e_aqc_get_pv_params_completion { 1043 __le16 seid; 1044 __le16 default_stag; 1045 __le16 pv_flags; /* same flags as add_pv */ 1046 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1047 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1048 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1049 u8 reserved[8]; 1050 __le16 default_port_seid; 1051 }; 1052 1053 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1054 1055 /* Add VEB (direct 0x0230) */ 1056 struct i40e_aqc_add_veb { 1057 __le16 uplink_seid; 1058 __le16 downlink_seid; 1059 __le16 veb_flags; 1060 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1061 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1062 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1063 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1064 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1065 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1066 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1067 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1068 u8 enable_tcs; 1069 u8 reserved[9]; 1070 }; 1071 1072 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1073 1074 struct i40e_aqc_add_veb_completion { 1075 u8 reserved[6]; 1076 __le16 switch_seid; 1077 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1078 __le16 veb_seid; 1079 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1080 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1081 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1082 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1083 __le16 statistic_index; 1084 __le16 vebs_used; 1085 __le16 vebs_free; 1086 }; 1087 1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1089 1090 /* Get VEB Parameters (direct 0x0232) 1091 * uses i40e_aqc_switch_seid for the descriptor 1092 */ 1093 struct i40e_aqc_get_veb_parameters_completion { 1094 __le16 seid; 1095 __le16 switch_id; 1096 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1097 __le16 statistic_index; 1098 __le16 vebs_used; 1099 __le16 vebs_free; 1100 u8 reserved[4]; 1101 }; 1102 1103 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1104 1105 /* Delete Element (direct 0x0243) 1106 * uses the generic i40e_aqc_switch_seid 1107 */ 1108 1109 /* Add MAC-VLAN (indirect 0x0250) */ 1110 1111 /* used for the command for most vlan commands */ 1112 struct i40e_aqc_macvlan { 1113 __le16 num_addresses; 1114 __le16 seid[3]; 1115 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1116 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1117 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1118 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1119 __le32 addr_high; 1120 __le32 addr_low; 1121 }; 1122 1123 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1124 1125 /* indirect data for command and response */ 1126 struct i40e_aqc_add_macvlan_element_data { 1127 u8 mac_addr[6]; 1128 __le16 vlan_tag; 1129 __le16 flags; 1130 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1131 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1132 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1133 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1134 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1135 __le16 queue_number; 1136 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1137 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1138 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1139 /* response section */ 1140 u8 match_method; 1141 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1142 #define I40E_AQC_MM_HASH_MATCH 0x02 1143 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1144 u8 reserved1[3]; 1145 }; 1146 1147 struct i40e_aqc_add_remove_macvlan_completion { 1148 __le16 perfect_mac_used; 1149 __le16 perfect_mac_free; 1150 __le16 unicast_hash_free; 1151 __le16 multicast_hash_free; 1152 __le32 addr_high; 1153 __le32 addr_low; 1154 }; 1155 1156 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1157 1158 /* Remove MAC-VLAN (indirect 0x0251) 1159 * uses i40e_aqc_macvlan for the descriptor 1160 * data points to an array of num_addresses of elements 1161 */ 1162 1163 struct i40e_aqc_remove_macvlan_element_data { 1164 u8 mac_addr[6]; 1165 __le16 vlan_tag; 1166 u8 flags; 1167 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1168 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1169 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1170 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1171 u8 reserved[3]; 1172 /* reply section */ 1173 u8 error_code; 1174 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1175 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1176 u8 reply_reserved[3]; 1177 }; 1178 1179 /* Add VLAN (indirect 0x0252) 1180 * Remove VLAN (indirect 0x0253) 1181 * use the generic i40e_aqc_macvlan for the command 1182 */ 1183 struct i40e_aqc_add_remove_vlan_element_data { 1184 __le16 vlan_tag; 1185 u8 vlan_flags; 1186 /* flags for add VLAN */ 1187 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1188 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1189 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1190 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1191 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1192 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1193 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1194 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1195 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1196 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1197 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1198 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1199 /* flags for remove VLAN */ 1200 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1201 u8 reserved; 1202 u8 result; 1203 /* flags for add VLAN */ 1204 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1205 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1206 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1207 /* flags for remove VLAN */ 1208 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1209 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1210 u8 reserved1[3]; 1211 }; 1212 1213 struct i40e_aqc_add_remove_vlan_completion { 1214 u8 reserved[4]; 1215 __le16 vlans_used; 1216 __le16 vlans_free; 1217 __le32 addr_high; 1218 __le32 addr_low; 1219 }; 1220 1221 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1222 struct i40e_aqc_set_vsi_promiscuous_modes { 1223 __le16 promiscuous_flags; 1224 __le16 valid_flags; 1225 /* flags used for both fields above */ 1226 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1227 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1228 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1229 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1230 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1231 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1232 __le16 seid; 1233 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1234 __le16 vlan_tag; 1235 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1236 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1237 u8 reserved[8]; 1238 }; 1239 1240 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1241 1242 /* Add S/E-tag command (direct 0x0255) 1243 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1244 */ 1245 struct i40e_aqc_add_tag { 1246 __le16 flags; 1247 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1248 __le16 seid; 1249 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1250 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1251 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1252 __le16 tag; 1253 __le16 queue_number; 1254 u8 reserved[8]; 1255 }; 1256 1257 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1258 1259 struct i40e_aqc_add_remove_tag_completion { 1260 u8 reserved[12]; 1261 __le16 tags_used; 1262 __le16 tags_free; 1263 }; 1264 1265 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1266 1267 /* Remove S/E-tag command (direct 0x0256) 1268 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1269 */ 1270 struct i40e_aqc_remove_tag { 1271 __le16 seid; 1272 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1273 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1274 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1275 __le16 tag; 1276 u8 reserved[12]; 1277 }; 1278 1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1280 1281 /* Add multicast E-Tag (direct 0x0257) 1282 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1283 * and no external data 1284 */ 1285 struct i40e_aqc_add_remove_mcast_etag { 1286 __le16 pv_seid; 1287 __le16 etag; 1288 u8 num_unicast_etags; 1289 u8 reserved[3]; 1290 __le32 addr_high; /* address of array of 2-byte s-tags */ 1291 __le32 addr_low; 1292 }; 1293 1294 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1295 1296 struct i40e_aqc_add_remove_mcast_etag_completion { 1297 u8 reserved[4]; 1298 __le16 mcast_etags_used; 1299 __le16 mcast_etags_free; 1300 __le32 addr_high; 1301 __le32 addr_low; 1302 1303 }; 1304 1305 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1306 1307 /* Update S/E-Tag (direct 0x0259) */ 1308 struct i40e_aqc_update_tag { 1309 __le16 seid; 1310 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1311 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1312 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1313 __le16 old_tag; 1314 __le16 new_tag; 1315 u8 reserved[10]; 1316 }; 1317 1318 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1319 1320 struct i40e_aqc_update_tag_completion { 1321 u8 reserved[12]; 1322 __le16 tags_used; 1323 __le16 tags_free; 1324 }; 1325 1326 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1327 1328 /* Add Control Packet filter (direct 0x025A) 1329 * Remove Control Packet filter (direct 0x025B) 1330 * uses the i40e_aqc_add_oveb_cloud, 1331 * and the generic direct completion structure 1332 */ 1333 struct i40e_aqc_add_remove_control_packet_filter { 1334 u8 mac[6]; 1335 __le16 etype; 1336 __le16 flags; 1337 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1338 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1339 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1340 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1341 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1342 __le16 seid; 1343 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1344 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1345 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1346 __le16 queue; 1347 u8 reserved[2]; 1348 }; 1349 1350 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1351 1352 struct i40e_aqc_add_remove_control_packet_filter_completion { 1353 __le16 mac_etype_used; 1354 __le16 etype_used; 1355 __le16 mac_etype_free; 1356 __le16 etype_free; 1357 u8 reserved[8]; 1358 }; 1359 1360 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1361 1362 /* Add Cloud filters (indirect 0x025C) 1363 * Remove Cloud filters (indirect 0x025D) 1364 * uses the i40e_aqc_add_remove_cloud_filters, 1365 * and the generic indirect completion structure 1366 */ 1367 struct i40e_aqc_add_remove_cloud_filters { 1368 u8 num_filters; 1369 u8 reserved; 1370 __le16 seid; 1371 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1372 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1373 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1374 u8 big_buffer_flag; 1375 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1376 u8 reserved2[3]; 1377 __le32 addr_high; 1378 __le32 addr_low; 1379 }; 1380 1381 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1382 1383 struct i40e_aqc_cloud_filters_element_data { 1384 u8 outer_mac[6]; 1385 u8 inner_mac[6]; 1386 __le16 inner_vlan; 1387 union { 1388 struct { 1389 u8 reserved[12]; 1390 u8 data[4]; 1391 } v4; 1392 struct { 1393 u8 data[16]; 1394 } v6; 1395 struct { 1396 __le16 data[8]; 1397 } raw_v6; 1398 } ipaddr; 1399 __le16 flags; 1400 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1401 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1402 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1403 /* 0x0000 reserved */ 1404 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1405 /* 0x0002 reserved */ 1406 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1407 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1408 /* 0x0005 reserved */ 1409 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1410 /* 0x0007 reserved */ 1411 /* 0x0008 reserved */ 1412 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1413 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1414 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1415 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1416 /* 0x0010 to 0x0017 is for custom filters */ 1417 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1418 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1420 1421 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1422 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1423 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1424 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1425 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1426 1427 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1428 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1435 1436 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1437 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1438 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1439 1440 __le32 tenant_id; 1441 u8 reserved[4]; 1442 __le16 queue_number; 1443 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1444 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1445 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1446 u8 reserved2[14]; 1447 /* response section */ 1448 u8 allocation_result; 1449 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1450 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1451 u8 response_reserved[7]; 1452 }; 1453 1454 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1455 1456 /* i40e_aqc_cloud_filters_element_bb is used when 1457 * I40E_AQC_CLOUD_CMD_BB flag is set. 1458 */ 1459 struct i40e_aqc_cloud_filters_element_bb { 1460 struct i40e_aqc_cloud_filters_element_data element; 1461 u16 general_fields[32]; 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1493 }; 1494 1495 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1496 1497 struct i40e_aqc_remove_cloud_filters_completion { 1498 __le16 perfect_ovlan_used; 1499 __le16 perfect_ovlan_free; 1500 __le16 vlan_used; 1501 __le16 vlan_free; 1502 __le32 addr_high; 1503 __le32 addr_low; 1504 }; 1505 1506 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1507 1508 /* Replace filter Command 0x025F 1509 * uses the i40e_aqc_replace_cloud_filters, 1510 * and the generic indirect completion structure 1511 */ 1512 struct i40e_filter_data { 1513 u8 filter_type; 1514 u8 input[3]; 1515 }; 1516 1517 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1518 1519 struct i40e_aqc_replace_cloud_filters_cmd { 1520 u8 valid_flags; 1521 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1522 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1523 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1524 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1525 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1526 u8 old_filter_type; 1527 u8 new_filter_type; 1528 u8 tr_bit; 1529 u8 reserved[4]; 1530 __le32 addr_high; 1531 __le32 addr_low; 1532 }; 1533 1534 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1535 1536 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1537 u8 data[32]; 1538 /* Filter type INPUT codes*/ 1539 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1540 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1541 1542 /* Field Vector offsets */ 1543 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1544 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1545 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1546 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1547 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1548 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1549 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1550 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1551 /* big FLU */ 1552 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1553 /* big FLU */ 1554 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1555 1556 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1557 struct i40e_filter_data filters[8]; 1558 }; 1559 1560 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1561 1562 /* Add Mirror Rule (indirect or direct 0x0260) 1563 * Delete Mirror Rule (indirect or direct 0x0261) 1564 * note: some rule types (4,5) do not use an external buffer. 1565 * take care to set the flags correctly. 1566 */ 1567 struct i40e_aqc_add_delete_mirror_rule { 1568 __le16 seid; 1569 __le16 rule_type; 1570 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1571 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1572 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1573 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1574 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1575 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1576 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1577 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1578 __le16 num_entries; 1579 __le16 destination; /* VSI for add, rule id for delete */ 1580 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1581 __le32 addr_low; 1582 }; 1583 1584 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1585 1586 struct i40e_aqc_add_delete_mirror_rule_completion { 1587 u8 reserved[2]; 1588 __le16 rule_id; /* only used on add */ 1589 __le16 mirror_rules_used; 1590 __le16 mirror_rules_free; 1591 __le32 addr_high; 1592 __le32 addr_low; 1593 }; 1594 1595 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1596 1597 /* Pipeline Personalization Profile */ 1598 struct i40e_aqc_write_personalization_profile { 1599 u8 flags; 1600 u8 reserved[3]; 1601 __le32 profile_track_id; 1602 __le32 addr_high; 1603 __le32 addr_low; 1604 }; 1605 1606 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1607 1608 struct i40e_aqc_write_ppp_resp { 1609 __le32 error_offset; 1610 __le32 error_info; 1611 __le32 addr_high; 1612 __le32 addr_low; 1613 }; 1614 1615 struct i40e_aqc_get_applied_profiles { 1616 u8 flags; 1617 #define I40E_AQC_GET_PPP_GET_CONF 0x1 1618 #define I40E_AQC_GET_PPP_GET_RDPU_CONF 0x2 1619 u8 rsv[3]; 1620 __le32 reserved; 1621 __le32 addr_high; 1622 __le32 addr_low; 1623 }; 1624 1625 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1626 1627 /* DCB 0x03xx*/ 1628 1629 /* PFC Ignore (direct 0x0301) 1630 * the command and response use the same descriptor structure 1631 */ 1632 struct i40e_aqc_pfc_ignore { 1633 u8 tc_bitmap; 1634 u8 command_flags; /* unused on response */ 1635 #define I40E_AQC_PFC_IGNORE_SET 0x80 1636 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1637 u8 reserved[14]; 1638 }; 1639 1640 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1641 1642 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1643 * with no parameters 1644 */ 1645 1646 /* TX scheduler 0x04xx */ 1647 1648 /* Almost all the indirect commands use 1649 * this generic struct to pass the SEID in param0 1650 */ 1651 struct i40e_aqc_tx_sched_ind { 1652 __le16 vsi_seid; 1653 u8 reserved[6]; 1654 __le32 addr_high; 1655 __le32 addr_low; 1656 }; 1657 1658 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1659 1660 /* Several commands respond with a set of queue set handles */ 1661 struct i40e_aqc_qs_handles_resp { 1662 __le16 qs_handles[8]; 1663 }; 1664 1665 /* Configure VSI BW limits (direct 0x0400) */ 1666 struct i40e_aqc_configure_vsi_bw_limit { 1667 __le16 vsi_seid; 1668 u8 reserved[2]; 1669 __le16 credit; 1670 u8 reserved1[2]; 1671 u8 max_credit; /* 0-3, limit = 2^max */ 1672 u8 reserved2[7]; 1673 }; 1674 1675 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1676 1677 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1678 * responds with i40e_aqc_qs_handles_resp 1679 */ 1680 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1681 u8 tc_valid_bits; 1682 u8 reserved[15]; 1683 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1684 1685 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1686 __le16 tc_bw_max[2]; 1687 u8 reserved1[28]; 1688 }; 1689 1690 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1691 1692 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1693 * responds with i40e_aqc_qs_handles_resp 1694 */ 1695 struct i40e_aqc_configure_vsi_tc_bw_data { 1696 u8 tc_valid_bits; 1697 u8 reserved[3]; 1698 u8 tc_bw_credits[8]; 1699 u8 reserved1[4]; 1700 __le16 qs_handles[8]; 1701 }; 1702 1703 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1704 1705 /* Query vsi bw configuration (indirect 0x0408) */ 1706 struct i40e_aqc_query_vsi_bw_config_resp { 1707 u8 tc_valid_bits; 1708 u8 tc_suspended_bits; 1709 u8 reserved[14]; 1710 __le16 qs_handles[8]; 1711 u8 reserved1[4]; 1712 __le16 port_bw_limit; 1713 u8 reserved2[2]; 1714 u8 max_bw; /* 0-3, limit = 2^max */ 1715 u8 reserved3[23]; 1716 }; 1717 1718 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1719 1720 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1721 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1722 u8 tc_valid_bits; 1723 u8 reserved[3]; 1724 u8 share_credits[8]; 1725 __le16 credits[8]; 1726 1727 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1728 __le16 tc_bw_max[2]; 1729 }; 1730 1731 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1732 1733 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1734 struct i40e_aqc_configure_switching_comp_bw_limit { 1735 __le16 seid; 1736 u8 reserved[2]; 1737 __le16 credit; 1738 u8 reserved1[2]; 1739 u8 max_bw; /* 0-3, limit = 2^max */ 1740 u8 reserved2[7]; 1741 }; 1742 1743 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1744 1745 /* Enable Physical Port ETS (indirect 0x0413) 1746 * Modify Physical Port ETS (indirect 0x0414) 1747 * Disable Physical Port ETS (indirect 0x0415) 1748 */ 1749 struct i40e_aqc_configure_switching_comp_ets_data { 1750 u8 reserved[4]; 1751 u8 tc_valid_bits; 1752 u8 seepage; 1753 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1754 u8 tc_strict_priority_flags; 1755 u8 reserved1[17]; 1756 u8 tc_bw_share_credits[8]; 1757 u8 reserved2[96]; 1758 }; 1759 1760 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1761 1762 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1763 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1764 u8 tc_valid_bits; 1765 u8 reserved[15]; 1766 __le16 tc_bw_credit[8]; 1767 1768 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1769 __le16 tc_bw_max[2]; 1770 u8 reserved1[28]; 1771 }; 1772 1773 I40E_CHECK_STRUCT_LEN(0x40, 1774 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1775 1776 /* Configure Switching Component Bandwidth Allocation per Tc 1777 * (indirect 0x0417) 1778 */ 1779 struct i40e_aqc_configure_switching_comp_bw_config_data { 1780 u8 tc_valid_bits; 1781 u8 reserved[2]; 1782 u8 absolute_credits; /* bool */ 1783 u8 tc_bw_share_credits[8]; 1784 u8 reserved1[20]; 1785 }; 1786 1787 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1788 1789 /* Query Switching Component Configuration (indirect 0x0418) */ 1790 struct i40e_aqc_query_switching_comp_ets_config_resp { 1791 u8 tc_valid_bits; 1792 u8 reserved[35]; 1793 __le16 port_bw_limit; 1794 u8 reserved1[2]; 1795 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1796 u8 reserved2[23]; 1797 }; 1798 1799 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1800 1801 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1802 struct i40e_aqc_query_port_ets_config_resp { 1803 u8 reserved[4]; 1804 u8 tc_valid_bits; 1805 u8 reserved1; 1806 u8 tc_strict_priority_bits; 1807 u8 reserved2; 1808 u8 tc_bw_share_credits[8]; 1809 __le16 tc_bw_limits[8]; 1810 1811 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1812 __le16 tc_bw_max[2]; 1813 u8 reserved3[32]; 1814 }; 1815 1816 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1817 1818 /* Query Switching Component Bandwidth Allocation per Traffic Type 1819 * (indirect 0x041A) 1820 */ 1821 struct i40e_aqc_query_switching_comp_bw_config_resp { 1822 u8 tc_valid_bits; 1823 u8 reserved[2]; 1824 u8 absolute_credits_enable; /* bool */ 1825 u8 tc_bw_share_credits[8]; 1826 __le16 tc_bw_limits[8]; 1827 1828 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1829 __le16 tc_bw_max[2]; 1830 }; 1831 1832 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1833 1834 /* Suspend/resume port TX traffic 1835 * (direct 0x041B and 0x041C) uses the generic SEID struct 1836 */ 1837 1838 /* Configure partition BW 1839 * (indirect 0x041D) 1840 */ 1841 struct i40e_aqc_configure_partition_bw_data { 1842 __le16 pf_valid_bits; 1843 u8 min_bw[16]; /* guaranteed bandwidth */ 1844 u8 max_bw[16]; /* bandwidth limit */ 1845 }; 1846 1847 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1848 1849 /* Get and set the active HMC resource profile and status. 1850 * (direct 0x0500) and (direct 0x0501) 1851 */ 1852 struct i40e_aq_get_set_hmc_resource_profile { 1853 u8 pm_profile; 1854 u8 pe_vf_enabled; 1855 u8 reserved[14]; 1856 }; 1857 1858 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1859 1860 enum i40e_aq_hmc_profile { 1861 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1862 I40E_HMC_PROFILE_DEFAULT = 1, 1863 I40E_HMC_PROFILE_FAVOR_VF = 2, 1864 I40E_HMC_PROFILE_EQUAL = 3, 1865 }; 1866 1867 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1868 1869 /* set in param0 for get phy abilities to report qualified modules */ 1870 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1871 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1872 1873 enum i40e_aq_phy_type { 1874 I40E_PHY_TYPE_SGMII = 0x0, 1875 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1876 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1877 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1878 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1879 I40E_PHY_TYPE_XAUI = 0x5, 1880 I40E_PHY_TYPE_XFI = 0x6, 1881 I40E_PHY_TYPE_SFI = 0x7, 1882 I40E_PHY_TYPE_XLAUI = 0x8, 1883 I40E_PHY_TYPE_XLPPI = 0x9, 1884 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1885 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1886 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1887 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1888 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1889 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1890 I40E_PHY_TYPE_100BASE_TX = 0x11, 1891 I40E_PHY_TYPE_1000BASE_T = 0x12, 1892 I40E_PHY_TYPE_10GBASE_T = 0x13, 1893 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1894 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1895 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1896 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1897 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1898 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1899 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1900 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1901 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1902 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1903 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1904 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1905 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1906 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1907 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1908 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1909 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1910 I40E_PHY_TYPE_MAX, 1911 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1912 I40E_PHY_TYPE_EMPTY = 0xFE, 1913 I40E_PHY_TYPE_DEFAULT = 0xFF, 1914 }; 1915 1916 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1917 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1918 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1919 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1920 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1921 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1922 1923 enum i40e_aq_link_speed { 1924 I40E_LINK_SPEED_UNKNOWN = 0, 1925 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1926 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1927 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1928 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1929 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1930 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1931 }; 1932 1933 struct i40e_aqc_module_desc { 1934 u8 oui[3]; 1935 u8 reserved1; 1936 u8 part_number[16]; 1937 u8 revision[4]; 1938 u8 reserved2[8]; 1939 }; 1940 1941 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1942 1943 struct i40e_aq_get_phy_abilities_resp { 1944 __le32 phy_type; /* bitmap using the above enum for offsets */ 1945 u8 link_speed; /* bitmap using the above enum bit patterns */ 1946 u8 abilities; 1947 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1948 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1949 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1950 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1951 #define I40E_AQ_PHY_AN_ENABLED 0x10 1952 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1953 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1954 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1955 __le16 eee_capability; 1956 #define I40E_AQ_EEE_100BASE_TX 0x0002 1957 #define I40E_AQ_EEE_1000BASE_T 0x0004 1958 #define I40E_AQ_EEE_10GBASE_T 0x0008 1959 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1960 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1961 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1962 __le32 eeer_val; 1963 u8 d3_lpan; 1964 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1965 u8 phy_type_ext; 1966 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1967 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1968 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1969 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1970 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1971 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1972 u8 fec_cfg_curr_mod_ext_info; 1973 #define I40E_AQ_ENABLE_FEC_KR 0x01 1974 #define I40E_AQ_ENABLE_FEC_RS 0x02 1975 #define I40E_AQ_REQUEST_FEC_KR 0x04 1976 #define I40E_AQ_REQUEST_FEC_RS 0x08 1977 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1978 #define I40E_AQ_FEC 1979 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1980 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1981 1982 u8 ext_comp_code; 1983 u8 phy_id[4]; 1984 u8 module_type[3]; 1985 u8 qualified_module_count; 1986 #define I40E_AQ_PHY_MAX_QMS 16 1987 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1988 }; 1989 1990 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1991 1992 /* Set PHY Config (direct 0x0601) */ 1993 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1994 __le32 phy_type; 1995 u8 link_speed; 1996 u8 abilities; 1997 /* bits 0-2 use the values from get_phy_abilities_resp */ 1998 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1999 #define I40E_AQ_PHY_ENABLE_AN 0x10 2000 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2001 __le16 eee_capability; 2002 __le32 eeer; 2003 u8 low_power_ctrl; 2004 u8 phy_type_ext; 2005 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2006 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2007 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2008 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2009 u8 fec_config; 2010 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2011 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2012 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2013 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2014 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2015 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2016 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2017 u8 reserved; 2018 }; 2019 2020 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2021 2022 /* Set MAC Config command data structure (direct 0x0603) */ 2023 struct i40e_aq_set_mac_config { 2024 __le16 max_frame_size; 2025 u8 params; 2026 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2027 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2028 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2029 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2030 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2031 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2032 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2033 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2034 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2035 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2036 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2037 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2038 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2039 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2040 u8 tx_timer_priority; /* bitmap */ 2041 __le16 tx_timer_value; 2042 __le16 fc_refresh_threshold; 2043 u8 reserved[8]; 2044 }; 2045 2046 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2047 2048 /* Restart Auto-Negotiation (direct 0x605) */ 2049 struct i40e_aqc_set_link_restart_an { 2050 u8 command; 2051 #define I40E_AQ_PHY_RESTART_AN 0x02 2052 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2053 u8 reserved[15]; 2054 }; 2055 2056 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2057 2058 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2059 struct i40e_aqc_get_link_status { 2060 __le16 command_flags; /* only field set on command */ 2061 #define I40E_AQ_LSE_MASK 0x3 2062 #define I40E_AQ_LSE_NOP 0x0 2063 #define I40E_AQ_LSE_DISABLE 0x2 2064 #define I40E_AQ_LSE_ENABLE 0x3 2065 /* only response uses this flag */ 2066 #define I40E_AQ_LSE_IS_ENABLED 0x1 2067 u8 phy_type; /* i40e_aq_phy_type */ 2068 u8 link_speed; /* i40e_aq_link_speed */ 2069 u8 link_info; 2070 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2071 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2072 #define I40E_AQ_LINK_FAULT 0x02 2073 #define I40E_AQ_LINK_FAULT_TX 0x04 2074 #define I40E_AQ_LINK_FAULT_RX 0x08 2075 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2076 #define I40E_AQ_LINK_UP_PORT 0x20 2077 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2078 #define I40E_AQ_SIGNAL_DETECT 0x80 2079 u8 an_info; 2080 #define I40E_AQ_AN_COMPLETED 0x01 2081 #define I40E_AQ_LP_AN_ABILITY 0x02 2082 #define I40E_AQ_PD_FAULT 0x04 2083 #define I40E_AQ_FEC_EN 0x08 2084 #define I40E_AQ_PHY_LOW_POWER 0x10 2085 #define I40E_AQ_LINK_PAUSE_TX 0x20 2086 #define I40E_AQ_LINK_PAUSE_RX 0x40 2087 #define I40E_AQ_QUALIFIED_MODULE 0x80 2088 u8 ext_info; 2089 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2090 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2091 #define I40E_AQ_LINK_TX_SHIFT 0x02 2092 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2093 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2094 #define I40E_AQ_LINK_TX_DRAINED 0x01 2095 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2096 #define I40E_AQ_LINK_FORCED_40G 0x10 2097 /* 25G Error Codes */ 2098 #define I40E_AQ_25G_NO_ERR 0X00 2099 #define I40E_AQ_25G_NOT_PRESENT 0X01 2100 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2101 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2102 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2103 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2104 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2105 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2106 #define I40E_AQ_LOOPBACK_MASK 0x07 2107 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2108 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2109 __le16 max_frame_size; 2110 u8 config; 2111 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2112 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2113 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2114 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2115 union { 2116 struct { 2117 u8 power_desc; 2118 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2119 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2120 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2121 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2122 #define I40E_AQ_PWR_CLASS_MASK 0x03 2123 u8 reserved[4]; 2124 }; 2125 struct { 2126 u8 link_type[4]; 2127 u8 link_type_ext; 2128 }; 2129 }; 2130 }; 2131 2132 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2133 2134 /* Set event mask command (direct 0x613) */ 2135 struct i40e_aqc_set_phy_int_mask { 2136 u8 reserved[8]; 2137 __le16 event_mask; 2138 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2139 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2140 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2141 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2142 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2143 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2144 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2145 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2146 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2147 u8 reserved1[6]; 2148 }; 2149 2150 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2151 2152 /* Get Local AN advt register (direct 0x0614) 2153 * Set Local AN advt register (direct 0x0615) 2154 * Get Link Partner AN advt register (direct 0x0616) 2155 */ 2156 struct i40e_aqc_an_advt_reg { 2157 __le32 local_an_reg0; 2158 __le16 local_an_reg1; 2159 u8 reserved[10]; 2160 }; 2161 2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2163 2164 /* Set Loopback mode (0x0618) */ 2165 struct i40e_aqc_set_lb_mode { 2166 __le16 lb_mode; 2167 #define I40E_AQ_LB_PHY_LOCAL 0x01 2168 #define I40E_AQ_LB_PHY_REMOTE 0x02 2169 #define I40E_AQ_LB_MAC_LOCAL 0x04 2170 u8 reserved[14]; 2171 }; 2172 2173 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2174 2175 /* Set PHY Debug command (0x0622) */ 2176 struct i40e_aqc_set_phy_debug { 2177 u8 command_flags; 2178 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2179 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2180 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2181 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2182 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2183 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2184 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2185 /* Disable link manageability on a single port */ 2186 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2187 /* Disable link manageability on all ports */ 2188 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2189 u8 reserved[15]; 2190 }; 2191 2192 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2193 2194 enum i40e_aq_phy_reg_type { 2195 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2196 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2197 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2198 }; 2199 2200 /* Run PHY Activity (0x0626) */ 2201 struct i40e_aqc_run_phy_activity { 2202 __le16 activity_id; 2203 u8 flags; 2204 u8 reserved1; 2205 __le32 control; 2206 __le32 data; 2207 u8 reserved2[4]; 2208 }; 2209 2210 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2211 2212 /* Set PHY Register command (0x0628) */ 2213 /* Get PHY Register command (0x0629) */ 2214 struct i40e_aqc_phy_register_access { 2215 u8 phy_interface; 2216 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2217 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2218 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2219 u8 dev_address; 2220 u8 reserved1[2]; 2221 __le32 reg_address; 2222 __le32 reg_value; 2223 u8 reserved2[4]; 2224 }; 2225 2226 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2227 2228 /* NVM Read command (indirect 0x0701) 2229 * NVM Erase commands (direct 0x0702) 2230 * NVM Update commands (indirect 0x0703) 2231 */ 2232 struct i40e_aqc_nvm_update { 2233 u8 command_flags; 2234 #define I40E_AQ_NVM_LAST_CMD 0x01 2235 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2236 u8 module_pointer; 2237 __le16 length; 2238 __le32 offset; 2239 __le32 addr_high; 2240 __le32 addr_low; 2241 }; 2242 2243 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2244 2245 /* NVM Config Read (indirect 0x0704) */ 2246 struct i40e_aqc_nvm_config_read { 2247 __le16 cmd_flags; 2248 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2249 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2250 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2251 __le16 element_count; 2252 __le16 element_id; /* Feature/field ID */ 2253 __le16 element_id_msw; /* MSWord of field ID */ 2254 __le32 address_high; 2255 __le32 address_low; 2256 }; 2257 2258 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2259 2260 /* NVM Config Write (indirect 0x0705) */ 2261 struct i40e_aqc_nvm_config_write { 2262 __le16 cmd_flags; 2263 __le16 element_count; 2264 u8 reserved[4]; 2265 __le32 address_high; 2266 __le32 address_low; 2267 }; 2268 2269 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2270 2271 /* Used for 0x0704 as well as for 0x0705 commands */ 2272 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2273 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2274 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2275 #define I40E_AQ_ANVM_FEATURE 0 2276 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2277 struct i40e_aqc_nvm_config_data_feature { 2278 __le16 feature_id; 2279 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2280 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2281 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2282 __le16 feature_options; 2283 __le16 feature_selection; 2284 }; 2285 2286 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2287 2288 struct i40e_aqc_nvm_config_data_immediate_field { 2289 __le32 field_id; 2290 __le32 field_value; 2291 __le16 field_options; 2292 __le16 reserved; 2293 }; 2294 2295 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2296 2297 /* OEM Post Update (indirect 0x0720) 2298 * no command data struct used 2299 */ 2300 struct i40e_aqc_nvm_oem_post_update { 2301 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2302 u8 sel_data; 2303 u8 reserved[7]; 2304 }; 2305 2306 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2307 2308 struct i40e_aqc_nvm_oem_post_update_buffer { 2309 u8 str_len; 2310 u8 dev_addr; 2311 __le16 eeprom_addr; 2312 u8 data[36]; 2313 }; 2314 2315 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2316 2317 /* Thermal Sensor (indirect 0x0721) 2318 * read or set thermal sensor configs and values 2319 * takes a sensor and command specific data buffer, not detailed here 2320 */ 2321 struct i40e_aqc_thermal_sensor { 2322 u8 sensor_action; 2323 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2324 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2325 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2326 u8 reserved[7]; 2327 __le32 addr_high; 2328 __le32 addr_low; 2329 }; 2330 2331 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2332 2333 /* Send to PF command (indirect 0x0801) id is only used by PF 2334 * Send to VF command (indirect 0x0802) id is only used by PF 2335 * Send to Peer PF command (indirect 0x0803) 2336 */ 2337 struct i40e_aqc_pf_vf_message { 2338 __le32 id; 2339 u8 reserved[4]; 2340 __le32 addr_high; 2341 __le32 addr_low; 2342 }; 2343 2344 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2345 2346 /* Alternate structure */ 2347 2348 /* Direct write (direct 0x0900) 2349 * Direct read (direct 0x0902) 2350 */ 2351 struct i40e_aqc_alternate_write { 2352 __le32 address0; 2353 __le32 data0; 2354 __le32 address1; 2355 __le32 data1; 2356 }; 2357 2358 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2359 2360 /* Indirect write (indirect 0x0901) 2361 * Indirect read (indirect 0x0903) 2362 */ 2363 2364 struct i40e_aqc_alternate_ind_write { 2365 __le32 address; 2366 __le32 length; 2367 __le32 addr_high; 2368 __le32 addr_low; 2369 }; 2370 2371 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2372 2373 /* Done alternate write (direct 0x0904) 2374 * uses i40e_aq_desc 2375 */ 2376 struct i40e_aqc_alternate_write_done { 2377 __le16 cmd_flags; 2378 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2379 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2380 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2381 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2382 u8 reserved[14]; 2383 }; 2384 2385 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2386 2387 /* Set OEM mode (direct 0x0905) */ 2388 struct i40e_aqc_alternate_set_mode { 2389 __le32 mode; 2390 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2391 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2392 u8 reserved[12]; 2393 }; 2394 2395 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2396 2397 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2398 2399 /* async events 0x10xx */ 2400 2401 /* Lan Queue Overflow Event (direct, 0x1001) */ 2402 struct i40e_aqc_lan_overflow { 2403 __le32 prtdcb_rupto; 2404 __le32 otx_ctl; 2405 u8 reserved[8]; 2406 }; 2407 2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2409 2410 /* Get LLDP MIB (indirect 0x0A00) */ 2411 struct i40e_aqc_lldp_get_mib { 2412 u8 type; 2413 u8 reserved1; 2414 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2415 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2416 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2417 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2418 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2419 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2420 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2421 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2422 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2423 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2424 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2425 __le16 local_len; 2426 __le16 remote_len; 2427 u8 reserved2[2]; 2428 __le32 addr_high; 2429 __le32 addr_low; 2430 }; 2431 2432 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2433 2434 /* Configure LLDP MIB Change Event (direct 0x0A01) 2435 * also used for the event (with type in the command field) 2436 */ 2437 struct i40e_aqc_lldp_update_mib { 2438 u8 command; 2439 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2440 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2441 u8 reserved[7]; 2442 __le32 addr_high; 2443 __le32 addr_low; 2444 }; 2445 2446 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2447 2448 /* Add LLDP TLV (indirect 0x0A02) 2449 * Delete LLDP TLV (indirect 0x0A04) 2450 */ 2451 struct i40e_aqc_lldp_add_tlv { 2452 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2453 u8 reserved1[1]; 2454 __le16 len; 2455 u8 reserved2[4]; 2456 __le32 addr_high; 2457 __le32 addr_low; 2458 }; 2459 2460 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2461 2462 /* Update LLDP TLV (indirect 0x0A03) */ 2463 struct i40e_aqc_lldp_update_tlv { 2464 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2465 u8 reserved; 2466 __le16 old_len; 2467 __le16 new_offset; 2468 __le16 new_len; 2469 __le32 addr_high; 2470 __le32 addr_low; 2471 }; 2472 2473 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2474 2475 /* Stop LLDP (direct 0x0A05) */ 2476 struct i40e_aqc_lldp_stop { 2477 u8 command; 2478 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2479 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2480 u8 reserved[15]; 2481 }; 2482 2483 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2484 2485 /* Start LLDP (direct 0x0A06) */ 2486 2487 struct i40e_aqc_lldp_start { 2488 u8 command; 2489 #define I40E_AQ_LLDP_AGENT_START 0x1 2490 u8 reserved[15]; 2491 }; 2492 2493 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2494 2495 /* Get CEE DCBX Oper Config (0x0A07) 2496 * uses the generic descriptor struct 2497 * returns below as indirect response 2498 */ 2499 2500 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2501 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2502 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2503 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2504 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2505 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2506 2507 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2508 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2509 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2510 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2511 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2512 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2513 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2514 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2515 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2516 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2517 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2518 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2519 2520 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2521 * word boundary layout issues, which the Linux compilers silently deal 2522 * with by adding padding, making the actual struct larger than designed. 2523 * However, the FW compiler for the NIC is less lenient and complains 2524 * about the struct. Hence, the struct defined here has an extra byte in 2525 * fields reserved3 and reserved4 to directly acknowledge that padding, 2526 * and the new length is used in the length check macro. 2527 */ 2528 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2529 u8 reserved1; 2530 u8 oper_num_tc; 2531 u8 oper_prio_tc[4]; 2532 u8 reserved2; 2533 u8 oper_tc_bw[8]; 2534 u8 oper_pfc_en; 2535 u8 reserved3[2]; 2536 __le16 oper_app_prio; 2537 u8 reserved4[2]; 2538 __le16 tlv_status; 2539 }; 2540 2541 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2542 2543 struct i40e_aqc_get_cee_dcb_cfg_resp { 2544 u8 oper_num_tc; 2545 u8 oper_prio_tc[4]; 2546 u8 oper_tc_bw[8]; 2547 u8 oper_pfc_en; 2548 __le16 oper_app_prio; 2549 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2550 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2551 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2552 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2553 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2554 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2555 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2556 __le32 tlv_status; 2557 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2558 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2559 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2560 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2561 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2562 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2563 u8 reserved[12]; 2564 }; 2565 2566 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2567 2568 /* Set Local LLDP MIB (indirect 0x0A08) 2569 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2570 */ 2571 struct i40e_aqc_lldp_set_local_mib { 2572 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2573 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2574 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2575 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2576 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2577 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2578 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2579 u8 type; 2580 u8 reserved0; 2581 __le16 length; 2582 u8 reserved1[4]; 2583 __le32 address_high; 2584 __le32 address_low; 2585 }; 2586 2587 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2588 2589 /* Stop/Start LLDP Agent (direct 0x0A09) 2590 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2591 */ 2592 struct i40e_aqc_lldp_stop_start_specific_agent { 2593 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2594 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2595 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2596 u8 command; 2597 u8 reserved[15]; 2598 }; 2599 2600 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2601 2602 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2603 struct i40e_aqc_add_udp_tunnel { 2604 __le16 udp_port; 2605 u8 reserved0[3]; 2606 u8 protocol_type; 2607 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2608 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2609 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2610 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2611 u8 reserved1[10]; 2612 }; 2613 2614 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2615 2616 struct i40e_aqc_add_udp_tunnel_completion { 2617 __le16 udp_port; 2618 u8 filter_entry_index; 2619 u8 multiple_pfs; 2620 #define I40E_AQC_SINGLE_PF 0x0 2621 #define I40E_AQC_MULTIPLE_PFS 0x1 2622 u8 total_filters; 2623 u8 reserved[11]; 2624 }; 2625 2626 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2627 2628 /* remove UDP Tunnel command (0x0B01) */ 2629 struct i40e_aqc_remove_udp_tunnel { 2630 u8 reserved[2]; 2631 u8 index; /* 0 to 15 */ 2632 u8 reserved2[13]; 2633 }; 2634 2635 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2636 2637 struct i40e_aqc_del_udp_tunnel_completion { 2638 __le16 udp_port; 2639 u8 index; /* 0 to 15 */ 2640 u8 multiple_pfs; 2641 u8 total_filters_used; 2642 u8 reserved1[11]; 2643 }; 2644 2645 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2646 2647 struct i40e_aqc_get_set_rss_key { 2648 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2649 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2650 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2651 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2652 __le16 vsi_id; 2653 u8 reserved[6]; 2654 __le32 addr_high; 2655 __le32 addr_low; 2656 }; 2657 2658 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2659 2660 struct i40e_aqc_get_set_rss_key_data { 2661 u8 standard_rss_key[0x28]; 2662 u8 extended_hash_key[0xc]; 2663 }; 2664 2665 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2666 2667 struct i40e_aqc_get_set_rss_lut { 2668 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2669 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2670 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2671 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2672 __le16 vsi_id; 2673 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2674 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2675 2676 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2677 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2678 __le16 flags; 2679 u8 reserved[4]; 2680 __le32 addr_high; 2681 __le32 addr_low; 2682 }; 2683 2684 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2685 2686 /* tunnel key structure 0x0B10 */ 2687 2688 struct i40e_aqc_tunnel_key_structure { 2689 u8 key1_off; 2690 u8 key2_off; 2691 u8 key1_len; /* 0 to 15 */ 2692 u8 key2_len; /* 0 to 15 */ 2693 u8 flags; 2694 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2695 /* response flags */ 2696 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2697 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2698 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2699 u8 network_key_index; 2700 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2701 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2702 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2703 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2704 u8 reserved[10]; 2705 }; 2706 2707 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2708 2709 /* OEM mode commands (direct 0xFE0x) */ 2710 struct i40e_aqc_oem_param_change { 2711 __le32 param_type; 2712 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2713 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2714 #define I40E_AQ_OEM_PARAM_MAC 2 2715 __le32 param_value1; 2716 __le16 param_value2; 2717 u8 reserved[6]; 2718 }; 2719 2720 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2721 2722 struct i40e_aqc_oem_state_change { 2723 __le32 state; 2724 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2725 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2726 u8 reserved[12]; 2727 }; 2728 2729 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2730 2731 /* Initialize OCSD (0xFE02, direct) */ 2732 struct i40e_aqc_opc_oem_ocsd_initialize { 2733 u8 type_status; 2734 u8 reserved1[3]; 2735 __le32 ocsd_memory_block_addr_high; 2736 __le32 ocsd_memory_block_addr_low; 2737 __le32 requested_update_interval; 2738 }; 2739 2740 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2741 2742 /* Initialize OCBB (0xFE03, direct) */ 2743 struct i40e_aqc_opc_oem_ocbb_initialize { 2744 u8 type_status; 2745 u8 reserved1[3]; 2746 __le32 ocbb_memory_block_addr_high; 2747 __le32 ocbb_memory_block_addr_low; 2748 u8 reserved2[4]; 2749 }; 2750 2751 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2752 2753 /* debug commands */ 2754 2755 /* get device id (0xFF00) uses the generic structure */ 2756 2757 /* set test more (0xFF01, internal) */ 2758 2759 struct i40e_acq_set_test_mode { 2760 u8 mode; 2761 #define I40E_AQ_TEST_PARTIAL 0 2762 #define I40E_AQ_TEST_FULL 1 2763 #define I40E_AQ_TEST_NVM 2 2764 u8 reserved[3]; 2765 u8 command; 2766 #define I40E_AQ_TEST_OPEN 0 2767 #define I40E_AQ_TEST_CLOSE 1 2768 #define I40E_AQ_TEST_INC 2 2769 u8 reserved2[3]; 2770 __le32 address_high; 2771 __le32 address_low; 2772 }; 2773 2774 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2775 2776 /* Debug Read Register command (0xFF03) 2777 * Debug Write Register command (0xFF04) 2778 */ 2779 struct i40e_aqc_debug_reg_read_write { 2780 __le32 reserved; 2781 __le32 address; 2782 __le32 value_high; 2783 __le32 value_low; 2784 }; 2785 2786 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2787 2788 /* Scatter/gather Reg Read (indirect 0xFF05) 2789 * Scatter/gather Reg Write (indirect 0xFF06) 2790 */ 2791 2792 /* i40e_aq_desc is used for the command */ 2793 struct i40e_aqc_debug_reg_sg_element_data { 2794 __le32 address; 2795 __le32 value; 2796 }; 2797 2798 /* Debug Modify register (direct 0xFF07) */ 2799 struct i40e_aqc_debug_modify_reg { 2800 __le32 address; 2801 __le32 value; 2802 __le32 clear_mask; 2803 __le32 set_mask; 2804 }; 2805 2806 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2807 2808 /* dump internal data (0xFF08, indirect) */ 2809 2810 #define I40E_AQ_CLUSTER_ID_AUX 0 2811 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2812 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2813 #define I40E_AQ_CLUSTER_ID_HMC 3 2814 #define I40E_AQ_CLUSTER_ID_MAC0 4 2815 #define I40E_AQ_CLUSTER_ID_MAC1 5 2816 #define I40E_AQ_CLUSTER_ID_MAC2 6 2817 #define I40E_AQ_CLUSTER_ID_MAC3 7 2818 #define I40E_AQ_CLUSTER_ID_DCB 8 2819 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2820 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2821 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2822 2823 struct i40e_aqc_debug_dump_internals { 2824 u8 cluster_id; 2825 u8 table_id; 2826 __le16 data_size; 2827 __le32 idx; 2828 __le32 address_high; 2829 __le32 address_low; 2830 }; 2831 2832 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2833 2834 struct i40e_aqc_debug_modify_internals { 2835 u8 cluster_id; 2836 u8 cluster_specific_params[7]; 2837 __le32 address_high; 2838 __le32 address_low; 2839 }; 2840 2841 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2842 2843 #endif /* _I40E_ADMINQ_CMD_H_ */ 2844