1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0004 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 /* LAA */ 136 i40e_aqc_opc_mac_address_read = 0x0107, 137 i40e_aqc_opc_mac_address_write = 0x0108, 138 139 /* PXE */ 140 i40e_aqc_opc_clear_pxe_mode = 0x0110, 141 142 /* internal switch commands */ 143 i40e_aqc_opc_get_switch_config = 0x0200, 144 i40e_aqc_opc_add_statistics = 0x0201, 145 i40e_aqc_opc_remove_statistics = 0x0202, 146 i40e_aqc_opc_set_port_parameters = 0x0203, 147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 148 149 i40e_aqc_opc_add_vsi = 0x0210, 150 i40e_aqc_opc_update_vsi_parameters = 0x0211, 151 i40e_aqc_opc_get_vsi_parameters = 0x0212, 152 153 i40e_aqc_opc_add_pv = 0x0220, 154 i40e_aqc_opc_update_pv_parameters = 0x0221, 155 i40e_aqc_opc_get_pv_parameters = 0x0222, 156 157 i40e_aqc_opc_add_veb = 0x0230, 158 i40e_aqc_opc_update_veb_parameters = 0x0231, 159 i40e_aqc_opc_get_veb_parameters = 0x0232, 160 161 i40e_aqc_opc_delete_element = 0x0243, 162 163 i40e_aqc_opc_add_macvlan = 0x0250, 164 i40e_aqc_opc_remove_macvlan = 0x0251, 165 i40e_aqc_opc_add_vlan = 0x0252, 166 i40e_aqc_opc_remove_vlan = 0x0253, 167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 168 i40e_aqc_opc_add_tag = 0x0255, 169 i40e_aqc_opc_remove_tag = 0x0256, 170 i40e_aqc_opc_add_multicast_etag = 0x0257, 171 i40e_aqc_opc_remove_multicast_etag = 0x0258, 172 i40e_aqc_opc_update_tag = 0x0259, 173 i40e_aqc_opc_add_control_packet_filter = 0x025A, 174 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 175 i40e_aqc_opc_add_cloud_filters = 0x025C, 176 i40e_aqc_opc_remove_cloud_filters = 0x025D, 177 178 i40e_aqc_opc_add_mirror_rule = 0x0260, 179 i40e_aqc_opc_delete_mirror_rule = 0x0261, 180 181 /* DCB commands */ 182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 183 i40e_aqc_opc_dcb_updated = 0x0302, 184 185 /* TX scheduler */ 186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 189 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 192 193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 199 i40e_aqc_opc_query_port_ets_config = 0x0419, 200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 201 i40e_aqc_opc_suspend_port_tx = 0x041B, 202 i40e_aqc_opc_resume_port_tx = 0x041C, 203 i40e_aqc_opc_configure_partition_bw = 0x041D, 204 205 /* hmc */ 206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 208 209 /* phy commands*/ 210 i40e_aqc_opc_get_phy_abilities = 0x0600, 211 i40e_aqc_opc_set_phy_config = 0x0601, 212 i40e_aqc_opc_set_mac_config = 0x0603, 213 i40e_aqc_opc_set_link_restart_an = 0x0605, 214 i40e_aqc_opc_get_link_status = 0x0607, 215 i40e_aqc_opc_set_phy_int_mask = 0x0613, 216 i40e_aqc_opc_get_local_advt_reg = 0x0614, 217 i40e_aqc_opc_set_local_advt_reg = 0x0615, 218 i40e_aqc_opc_get_partner_advt = 0x0616, 219 i40e_aqc_opc_set_lb_modes = 0x0618, 220 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 221 i40e_aqc_opc_set_phy_debug = 0x0622, 222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 223 224 /* NVM commands */ 225 i40e_aqc_opc_nvm_read = 0x0701, 226 i40e_aqc_opc_nvm_erase = 0x0702, 227 i40e_aqc_opc_nvm_update = 0x0703, 228 i40e_aqc_opc_nvm_config_read = 0x0704, 229 i40e_aqc_opc_nvm_config_write = 0x0705, 230 231 /* virtualization commands */ 232 i40e_aqc_opc_send_msg_to_pf = 0x0801, 233 i40e_aqc_opc_send_msg_to_vf = 0x0802, 234 i40e_aqc_opc_send_msg_to_peer = 0x0803, 235 236 /* alternate structure */ 237 i40e_aqc_opc_alternate_write = 0x0900, 238 i40e_aqc_opc_alternate_write_indirect = 0x0901, 239 i40e_aqc_opc_alternate_read = 0x0902, 240 i40e_aqc_opc_alternate_read_indirect = 0x0903, 241 i40e_aqc_opc_alternate_write_done = 0x0904, 242 i40e_aqc_opc_alternate_set_mode = 0x0905, 243 i40e_aqc_opc_alternate_clear_port = 0x0906, 244 245 /* LLDP commands */ 246 i40e_aqc_opc_lldp_get_mib = 0x0A00, 247 i40e_aqc_opc_lldp_update_mib = 0x0A01, 248 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 249 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 251 i40e_aqc_opc_lldp_stop = 0x0A05, 252 i40e_aqc_opc_lldp_start = 0x0A06, 253 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 254 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 255 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 256 257 /* Tunnel commands */ 258 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 259 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 260 261 /* Async Events */ 262 i40e_aqc_opc_event_lan_overflow = 0x1001, 263 264 /* OEM commands */ 265 i40e_aqc_opc_oem_parameter_change = 0xFE00, 266 i40e_aqc_opc_oem_device_status_change = 0xFE01, 267 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 268 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 269 270 /* debug commands */ 271 i40e_aqc_opc_debug_read_reg = 0xFF03, 272 i40e_aqc_opc_debug_write_reg = 0xFF04, 273 i40e_aqc_opc_debug_modify_reg = 0xFF07, 274 i40e_aqc_opc_debug_dump_internals = 0xFF08, 275 }; 276 277 /* command structures and indirect data structures */ 278 279 /* Structure naming conventions: 280 * - no suffix for direct command descriptor structures 281 * - _data for indirect sent data 282 * - _resp for indirect return data (data which is both will use _data) 283 * - _completion for direct return data 284 * - _element_ for repeated elements (may also be _data or _resp) 285 * 286 * Command structures are expected to overlay the params.raw member of the basic 287 * descriptor, and as such cannot exceed 16 bytes in length. 288 */ 289 290 /* This macro is used to generate a compilation error if a structure 291 * is not exactly the correct length. It gives a divide by zero error if the 292 * structure is not of the correct size, otherwise it creates an enum that is 293 * never used. 294 */ 295 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 296 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 297 298 /* This macro is used extensively to ensure that command structures are 16 299 * bytes in length as they have to map to the raw array of that size. 300 */ 301 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 302 303 /* internal (0x00XX) commands */ 304 305 /* Get version (direct 0x0001) */ 306 struct i40e_aqc_get_version { 307 __le32 rom_ver; 308 __le32 fw_build; 309 __le16 fw_major; 310 __le16 fw_minor; 311 __le16 api_major; 312 __le16 api_minor; 313 }; 314 315 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 316 317 /* Send driver version (indirect 0x0002) */ 318 struct i40e_aqc_driver_version { 319 u8 driver_major_ver; 320 u8 driver_minor_ver; 321 u8 driver_build_ver; 322 u8 driver_subbuild_ver; 323 u8 reserved[4]; 324 __le32 address_high; 325 __le32 address_low; 326 }; 327 328 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 329 330 /* Queue Shutdown (direct 0x0003) */ 331 struct i40e_aqc_queue_shutdown { 332 __le32 driver_unloading; 333 #define I40E_AQ_DRIVER_UNLOADING 0x1 334 u8 reserved[12]; 335 }; 336 337 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 338 339 /* Set PF context (0x0004, direct) */ 340 struct i40e_aqc_set_pf_context { 341 u8 pf_id; 342 u8 reserved[15]; 343 }; 344 345 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 346 347 /* Request resource ownership (direct 0x0008) 348 * Release resource ownership (direct 0x0009) 349 */ 350 #define I40E_AQ_RESOURCE_NVM 1 351 #define I40E_AQ_RESOURCE_SDP 2 352 #define I40E_AQ_RESOURCE_ACCESS_READ 1 353 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 354 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 355 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 356 357 struct i40e_aqc_request_resource { 358 __le16 resource_id; 359 __le16 access_type; 360 __le32 timeout; 361 __le32 resource_number; 362 u8 reserved[4]; 363 }; 364 365 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 366 367 /* Get function capabilities (indirect 0x000A) 368 * Get device capabilities (indirect 0x000B) 369 */ 370 struct i40e_aqc_list_capabilites { 371 u8 command_flags; 372 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 373 u8 pf_index; 374 u8 reserved[2]; 375 __le32 count; 376 __le32 addr_high; 377 __le32 addr_low; 378 }; 379 380 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 381 382 struct i40e_aqc_list_capabilities_element_resp { 383 __le16 id; 384 u8 major_rev; 385 u8 minor_rev; 386 __le32 number; 387 __le32 logical_id; 388 __le32 phys_id; 389 u8 reserved[16]; 390 }; 391 392 /* list of caps */ 393 394 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 395 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 396 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 397 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 398 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 399 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 400 #define I40E_AQ_CAP_ID_SRIOV 0x0012 401 #define I40E_AQ_CAP_ID_VF 0x0013 402 #define I40E_AQ_CAP_ID_VMDQ 0x0014 403 #define I40E_AQ_CAP_ID_8021QBG 0x0015 404 #define I40E_AQ_CAP_ID_8021QBR 0x0016 405 #define I40E_AQ_CAP_ID_VSI 0x0017 406 #define I40E_AQ_CAP_ID_DCB 0x0018 407 #define I40E_AQ_CAP_ID_FCOE 0x0021 408 #define I40E_AQ_CAP_ID_ISCSI 0x0022 409 #define I40E_AQ_CAP_ID_RSS 0x0040 410 #define I40E_AQ_CAP_ID_RXQ 0x0041 411 #define I40E_AQ_CAP_ID_TXQ 0x0042 412 #define I40E_AQ_CAP_ID_MSIX 0x0043 413 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 414 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 415 #define I40E_AQ_CAP_ID_1588 0x0046 416 #define I40E_AQ_CAP_ID_IWARP 0x0051 417 #define I40E_AQ_CAP_ID_LED 0x0061 418 #define I40E_AQ_CAP_ID_SDP 0x0062 419 #define I40E_AQ_CAP_ID_MDIO 0x0063 420 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 421 #define I40E_AQ_CAP_ID_CEM 0x00F2 422 423 /* Set CPPM Configuration (direct 0x0103) */ 424 struct i40e_aqc_cppm_configuration { 425 __le16 command_flags; 426 #define I40E_AQ_CPPM_EN_LTRC 0x0800 427 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 428 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 429 #define I40E_AQ_CPPM_EN_HPTC 0x4000 430 #define I40E_AQ_CPPM_EN_DMARC 0x8000 431 __le16 ttlx; 432 __le32 dmacr; 433 __le16 dmcth; 434 u8 hptc; 435 u8 reserved; 436 __le32 pfltrc; 437 }; 438 439 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 440 441 /* Set ARP Proxy command / response (indirect 0x0104) */ 442 struct i40e_aqc_arp_proxy_data { 443 __le16 command_flags; 444 #define I40E_AQ_ARP_INIT_IPV4 0x0008 445 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 446 #define I40E_AQ_ARP_ENA 0x0020 447 #define I40E_AQ_ARP_ADD_IPV4 0x0040 448 #define I40E_AQ_ARP_DEL_IPV4 0x0080 449 __le16 table_id; 450 __le32 pfpm_proxyfc; 451 __le32 ip_addr; 452 u8 mac_addr[6]; 453 u8 reserved[2]; 454 }; 455 456 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 457 458 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 459 struct i40e_aqc_ns_proxy_data { 460 __le16 table_idx_mac_addr_0; 461 __le16 table_idx_mac_addr_1; 462 __le16 table_idx_ipv6_0; 463 __le16 table_idx_ipv6_1; 464 __le16 control; 465 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 466 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 467 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 468 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 469 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 470 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 471 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 472 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 473 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 474 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 475 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 476 u8 mac_addr_0[6]; 477 u8 mac_addr_1[6]; 478 u8 local_mac_addr[6]; 479 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 480 u8 ipv6_addr_1[16]; 481 }; 482 483 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 484 485 /* Manage LAA Command (0x0106) - obsolete */ 486 struct i40e_aqc_mng_laa { 487 __le16 command_flags; 488 #define I40E_AQ_LAA_FLAG_WR 0x8000 489 u8 reserved[2]; 490 __le32 sal; 491 __le16 sah; 492 u8 reserved2[6]; 493 }; 494 495 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 496 497 /* Manage MAC Address Read Command (indirect 0x0107) */ 498 struct i40e_aqc_mac_address_read { 499 __le16 command_flags; 500 #define I40E_AQC_LAN_ADDR_VALID 0x10 501 #define I40E_AQC_SAN_ADDR_VALID 0x20 502 #define I40E_AQC_PORT_ADDR_VALID 0x40 503 #define I40E_AQC_WOL_ADDR_VALID 0x80 504 #define I40E_AQC_MC_MAG_EN_VALID 0x100 505 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 506 u8 reserved[6]; 507 __le32 addr_high; 508 __le32 addr_low; 509 }; 510 511 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 512 513 struct i40e_aqc_mac_address_read_data { 514 u8 pf_lan_mac[6]; 515 u8 pf_san_mac[6]; 516 u8 port_mac[6]; 517 u8 pf_wol_mac[6]; 518 }; 519 520 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 521 522 /* Manage MAC Address Write Command (0x0108) */ 523 struct i40e_aqc_mac_address_write { 524 __le16 command_flags; 525 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 526 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 527 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 528 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 529 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 530 531 __le16 mac_sah; 532 __le32 mac_sal; 533 u8 reserved[8]; 534 }; 535 536 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 537 538 /* PXE commands (0x011x) */ 539 540 /* Clear PXE Command and response (direct 0x0110) */ 541 struct i40e_aqc_clear_pxe { 542 u8 rx_cnt; 543 u8 reserved[15]; 544 }; 545 546 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 547 548 /* Switch configuration commands (0x02xx) */ 549 550 /* Used by many indirect commands that only pass an seid and a buffer in the 551 * command 552 */ 553 struct i40e_aqc_switch_seid { 554 __le16 seid; 555 u8 reserved[6]; 556 __le32 addr_high; 557 __le32 addr_low; 558 }; 559 560 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 561 562 /* Get Switch Configuration command (indirect 0x0200) 563 * uses i40e_aqc_switch_seid for the descriptor 564 */ 565 struct i40e_aqc_get_switch_config_header_resp { 566 __le16 num_reported; 567 __le16 num_total; 568 u8 reserved[12]; 569 }; 570 571 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 572 573 struct i40e_aqc_switch_config_element_resp { 574 u8 element_type; 575 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 576 #define I40E_AQ_SW_ELEM_TYPE_PF 2 577 #define I40E_AQ_SW_ELEM_TYPE_VF 3 578 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 579 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 580 #define I40E_AQ_SW_ELEM_TYPE_PV 16 581 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 582 #define I40E_AQ_SW_ELEM_TYPE_PA 18 583 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 584 u8 revision; 585 #define I40E_AQ_SW_ELEM_REV_1 1 586 __le16 seid; 587 __le16 uplink_seid; 588 __le16 downlink_seid; 589 u8 reserved[3]; 590 u8 connection_type; 591 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 592 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 593 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 594 __le16 scheduler_id; 595 __le16 element_info; 596 }; 597 598 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 599 600 /* Get Switch Configuration (indirect 0x0200) 601 * an array of elements are returned in the response buffer 602 * the first in the array is the header, remainder are elements 603 */ 604 struct i40e_aqc_get_switch_config_resp { 605 struct i40e_aqc_get_switch_config_header_resp header; 606 struct i40e_aqc_switch_config_element_resp element[1]; 607 }; 608 609 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 610 611 /* Add Statistics (direct 0x0201) 612 * Remove Statistics (direct 0x0202) 613 */ 614 struct i40e_aqc_add_remove_statistics { 615 __le16 seid; 616 __le16 vlan; 617 __le16 stat_index; 618 u8 reserved[10]; 619 }; 620 621 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 622 623 /* Set Port Parameters command (direct 0x0203) */ 624 struct i40e_aqc_set_port_parameters { 625 __le16 command_flags; 626 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 627 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 628 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 629 __le16 bad_frame_vsi; 630 __le16 default_seid; /* reserved for command */ 631 u8 reserved[10]; 632 }; 633 634 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 635 636 /* Get Switch Resource Allocation (indirect 0x0204) */ 637 struct i40e_aqc_get_switch_resource_alloc { 638 u8 num_entries; /* reserved for command */ 639 u8 reserved[7]; 640 __le32 addr_high; 641 __le32 addr_low; 642 }; 643 644 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 645 646 /* expect an array of these structs in the response buffer */ 647 struct i40e_aqc_switch_resource_alloc_element_resp { 648 u8 resource_type; 649 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 650 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 651 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 652 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 653 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 654 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 655 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 656 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 657 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 658 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 659 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 660 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 661 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 662 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 663 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 664 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 665 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 666 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 667 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 668 u8 reserved1; 669 __le16 guaranteed; 670 __le16 total; 671 __le16 used; 672 __le16 total_unalloced; 673 u8 reserved2[6]; 674 }; 675 676 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 677 678 /* Add VSI (indirect 0x0210) 679 * this indirect command uses struct i40e_aqc_vsi_properties_data 680 * as the indirect buffer (128 bytes) 681 * 682 * Update VSI (indirect 0x211) 683 * uses the same data structure as Add VSI 684 * 685 * Get VSI (indirect 0x0212) 686 * uses the same completion and data structure as Add VSI 687 */ 688 struct i40e_aqc_add_get_update_vsi { 689 __le16 uplink_seid; 690 u8 connection_type; 691 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 692 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 693 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 694 u8 reserved1; 695 u8 vf_id; 696 u8 reserved2; 697 __le16 vsi_flags; 698 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 699 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 700 #define I40E_AQ_VSI_TYPE_VF 0x0 701 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 702 #define I40E_AQ_VSI_TYPE_PF 0x2 703 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 704 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 705 __le32 addr_high; 706 __le32 addr_low; 707 }; 708 709 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 710 711 struct i40e_aqc_add_get_update_vsi_completion { 712 __le16 seid; 713 __le16 vsi_number; 714 __le16 vsi_used; 715 __le16 vsi_free; 716 __le32 addr_high; 717 __le32 addr_low; 718 }; 719 720 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 721 722 struct i40e_aqc_vsi_properties_data { 723 /* first 96 byte are written by SW */ 724 __le16 valid_sections; 725 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 726 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 727 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 728 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 729 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 730 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 731 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 732 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 733 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 734 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 735 /* switch section */ 736 __le16 switch_id; /* 12bit id combined with flags below */ 737 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 738 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 739 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 740 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 741 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 742 u8 sw_reserved[2]; 743 /* security section */ 744 u8 sec_flags; 745 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 746 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 747 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 748 u8 sec_reserved; 749 /* VLAN section */ 750 __le16 pvid; /* VLANS include priority bits */ 751 __le16 fcoe_pvid; 752 u8 port_vlan_flags; 753 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 754 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 755 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 756 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 757 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 758 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 759 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 760 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 761 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 762 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 763 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 764 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 765 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 766 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 767 u8 pvlan_reserved[3]; 768 /* ingress egress up sections */ 769 __le32 ingress_table; /* bitmap, 3 bits per up */ 770 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 771 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 772 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 773 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 774 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 775 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 776 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 777 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 778 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 779 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 780 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 781 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 782 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 783 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 784 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 785 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 786 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 787 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 788 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 789 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 790 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 791 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 792 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 793 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 794 __le32 egress_table; /* same defines as for ingress table */ 795 /* cascaded PV section */ 796 __le16 cas_pv_tag; 797 u8 cas_pv_flags; 798 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 799 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 800 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 801 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 802 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 803 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 804 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 805 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 806 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 807 u8 cas_pv_reserved; 808 /* queue mapping section */ 809 __le16 mapping_flags; 810 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 811 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 812 __le16 queue_mapping[16]; 813 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 814 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 815 __le16 tc_mapping[8]; 816 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 817 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 818 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 819 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 820 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 821 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 822 /* queueing option section */ 823 u8 queueing_opt_flags; 824 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 825 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 826 u8 queueing_opt_reserved[3]; 827 /* scheduler section */ 828 u8 up_enable_bits; 829 u8 sched_reserved; 830 /* outer up section */ 831 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 832 u8 cmd_reserved[8]; 833 /* last 32 bytes are written by FW */ 834 __le16 qs_handle[8]; 835 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 836 __le16 stat_counter_idx; 837 __le16 sched_id; 838 u8 resp_reserved[12]; 839 }; 840 841 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 842 843 /* Add Port Virtualizer (direct 0x0220) 844 * also used for update PV (direct 0x0221) but only flags are used 845 * (IS_CTRL_PORT only works on add PV) 846 */ 847 struct i40e_aqc_add_update_pv { 848 __le16 command_flags; 849 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 850 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 851 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 852 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 853 __le16 uplink_seid; 854 __le16 connected_seid; 855 u8 reserved[10]; 856 }; 857 858 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 859 860 struct i40e_aqc_add_update_pv_completion { 861 /* reserved for update; for add also encodes error if rc == ENOSPC */ 862 __le16 pv_seid; 863 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 864 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 865 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 866 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 867 u8 reserved[14]; 868 }; 869 870 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 871 872 /* Get PV Params (direct 0x0222) 873 * uses i40e_aqc_switch_seid for the descriptor 874 */ 875 876 struct i40e_aqc_get_pv_params_completion { 877 __le16 seid; 878 __le16 default_stag; 879 __le16 pv_flags; /* same flags as add_pv */ 880 #define I40E_AQC_GET_PV_PV_TYPE 0x1 881 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 882 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 883 u8 reserved[8]; 884 __le16 default_port_seid; 885 }; 886 887 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 888 889 /* Add VEB (direct 0x0230) */ 890 struct i40e_aqc_add_veb { 891 __le16 uplink_seid; 892 __le16 downlink_seid; 893 __le16 veb_flags; 894 #define I40E_AQC_ADD_VEB_FLOATING 0x1 895 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 896 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 897 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 898 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 899 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 900 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 901 u8 enable_tcs; 902 u8 reserved[9]; 903 }; 904 905 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 906 907 struct i40e_aqc_add_veb_completion { 908 u8 reserved[6]; 909 __le16 switch_seid; 910 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 911 __le16 veb_seid; 912 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 913 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 914 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 915 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 916 __le16 statistic_index; 917 __le16 vebs_used; 918 __le16 vebs_free; 919 }; 920 921 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 922 923 /* Get VEB Parameters (direct 0x0232) 924 * uses i40e_aqc_switch_seid for the descriptor 925 */ 926 struct i40e_aqc_get_veb_parameters_completion { 927 __le16 seid; 928 __le16 switch_id; 929 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 930 __le16 statistic_index; 931 __le16 vebs_used; 932 __le16 vebs_free; 933 u8 reserved[4]; 934 }; 935 936 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 937 938 /* Delete Element (direct 0x0243) 939 * uses the generic i40e_aqc_switch_seid 940 */ 941 942 /* Add MAC-VLAN (indirect 0x0250) */ 943 944 /* used for the command for most vlan commands */ 945 struct i40e_aqc_macvlan { 946 __le16 num_addresses; 947 __le16 seid[3]; 948 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 949 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 950 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 951 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 952 __le32 addr_high; 953 __le32 addr_low; 954 }; 955 956 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 957 958 /* indirect data for command and response */ 959 struct i40e_aqc_add_macvlan_element_data { 960 u8 mac_addr[6]; 961 __le16 vlan_tag; 962 __le16 flags; 963 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 964 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 965 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 966 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 967 __le16 queue_number; 968 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 969 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 970 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 971 /* response section */ 972 u8 match_method; 973 #define I40E_AQC_MM_PERFECT_MATCH 0x01 974 #define I40E_AQC_MM_HASH_MATCH 0x02 975 #define I40E_AQC_MM_ERR_NO_RES 0xFF 976 u8 reserved1[3]; 977 }; 978 979 struct i40e_aqc_add_remove_macvlan_completion { 980 __le16 perfect_mac_used; 981 __le16 perfect_mac_free; 982 __le16 unicast_hash_free; 983 __le16 multicast_hash_free; 984 __le32 addr_high; 985 __le32 addr_low; 986 }; 987 988 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 989 990 /* Remove MAC-VLAN (indirect 0x0251) 991 * uses i40e_aqc_macvlan for the descriptor 992 * data points to an array of num_addresses of elements 993 */ 994 995 struct i40e_aqc_remove_macvlan_element_data { 996 u8 mac_addr[6]; 997 __le16 vlan_tag; 998 u8 flags; 999 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1000 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1001 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1002 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1003 u8 reserved[3]; 1004 /* reply section */ 1005 u8 error_code; 1006 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1007 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1008 u8 reply_reserved[3]; 1009 }; 1010 1011 /* Add VLAN (indirect 0x0252) 1012 * Remove VLAN (indirect 0x0253) 1013 * use the generic i40e_aqc_macvlan for the command 1014 */ 1015 struct i40e_aqc_add_remove_vlan_element_data { 1016 __le16 vlan_tag; 1017 u8 vlan_flags; 1018 /* flags for add VLAN */ 1019 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1020 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1021 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1022 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1023 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1024 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1025 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1026 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1027 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1028 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1029 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1030 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1031 /* flags for remove VLAN */ 1032 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1033 u8 reserved; 1034 u8 result; 1035 /* flags for add VLAN */ 1036 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1037 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1038 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1039 /* flags for remove VLAN */ 1040 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1041 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1042 u8 reserved1[3]; 1043 }; 1044 1045 struct i40e_aqc_add_remove_vlan_completion { 1046 u8 reserved[4]; 1047 __le16 vlans_used; 1048 __le16 vlans_free; 1049 __le32 addr_high; 1050 __le32 addr_low; 1051 }; 1052 1053 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1054 struct i40e_aqc_set_vsi_promiscuous_modes { 1055 __le16 promiscuous_flags; 1056 __le16 valid_flags; 1057 /* flags used for both fields above */ 1058 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1059 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1060 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1061 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1062 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1063 __le16 seid; 1064 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1065 __le16 vlan_tag; 1066 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1067 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1068 u8 reserved[8]; 1069 }; 1070 1071 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1072 1073 /* Add S/E-tag command (direct 0x0255) 1074 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1075 */ 1076 struct i40e_aqc_add_tag { 1077 __le16 flags; 1078 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1079 __le16 seid; 1080 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1081 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1082 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1083 __le16 tag; 1084 __le16 queue_number; 1085 u8 reserved[8]; 1086 }; 1087 1088 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1089 1090 struct i40e_aqc_add_remove_tag_completion { 1091 u8 reserved[12]; 1092 __le16 tags_used; 1093 __le16 tags_free; 1094 }; 1095 1096 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1097 1098 /* Remove S/E-tag command (direct 0x0256) 1099 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1100 */ 1101 struct i40e_aqc_remove_tag { 1102 __le16 seid; 1103 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1104 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1105 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1106 __le16 tag; 1107 u8 reserved[12]; 1108 }; 1109 1110 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1111 1112 /* Add multicast E-Tag (direct 0x0257) 1113 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1114 * and no external data 1115 */ 1116 struct i40e_aqc_add_remove_mcast_etag { 1117 __le16 pv_seid; 1118 __le16 etag; 1119 u8 num_unicast_etags; 1120 u8 reserved[3]; 1121 __le32 addr_high; /* address of array of 2-byte s-tags */ 1122 __le32 addr_low; 1123 }; 1124 1125 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1126 1127 struct i40e_aqc_add_remove_mcast_etag_completion { 1128 u8 reserved[4]; 1129 __le16 mcast_etags_used; 1130 __le16 mcast_etags_free; 1131 __le32 addr_high; 1132 __le32 addr_low; 1133 1134 }; 1135 1136 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1137 1138 /* Update S/E-Tag (direct 0x0259) */ 1139 struct i40e_aqc_update_tag { 1140 __le16 seid; 1141 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1142 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1143 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1144 __le16 old_tag; 1145 __le16 new_tag; 1146 u8 reserved[10]; 1147 }; 1148 1149 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1150 1151 struct i40e_aqc_update_tag_completion { 1152 u8 reserved[12]; 1153 __le16 tags_used; 1154 __le16 tags_free; 1155 }; 1156 1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1158 1159 /* Add Control Packet filter (direct 0x025A) 1160 * Remove Control Packet filter (direct 0x025B) 1161 * uses the i40e_aqc_add_oveb_cloud, 1162 * and the generic direct completion structure 1163 */ 1164 struct i40e_aqc_add_remove_control_packet_filter { 1165 u8 mac[6]; 1166 __le16 etype; 1167 __le16 flags; 1168 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1169 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1170 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1171 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1172 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1173 __le16 seid; 1174 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1175 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1176 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1177 __le16 queue; 1178 u8 reserved[2]; 1179 }; 1180 1181 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1182 1183 struct i40e_aqc_add_remove_control_packet_filter_completion { 1184 __le16 mac_etype_used; 1185 __le16 etype_used; 1186 __le16 mac_etype_free; 1187 __le16 etype_free; 1188 u8 reserved[8]; 1189 }; 1190 1191 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1192 1193 /* Add Cloud filters (indirect 0x025C) 1194 * Remove Cloud filters (indirect 0x025D) 1195 * uses the i40e_aqc_add_remove_cloud_filters, 1196 * and the generic indirect completion structure 1197 */ 1198 struct i40e_aqc_add_remove_cloud_filters { 1199 u8 num_filters; 1200 u8 reserved; 1201 __le16 seid; 1202 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1203 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1204 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1205 u8 reserved2[4]; 1206 __le32 addr_high; 1207 __le32 addr_low; 1208 }; 1209 1210 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1211 1212 struct i40e_aqc_add_remove_cloud_filters_element_data { 1213 u8 outer_mac[6]; 1214 u8 inner_mac[6]; 1215 __le16 inner_vlan; 1216 union { 1217 struct { 1218 u8 reserved[12]; 1219 u8 data[4]; 1220 } v4; 1221 struct { 1222 u8 data[16]; 1223 } v6; 1224 } ipaddr; 1225 __le16 flags; 1226 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1227 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1228 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1229 /* 0x0000 reserved */ 1230 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1231 /* 0x0002 reserved */ 1232 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1233 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1234 /* 0x0005 reserved */ 1235 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1236 /* 0x0007 reserved */ 1237 /* 0x0008 reserved */ 1238 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1239 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1240 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1241 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1242 1243 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1244 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1245 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1246 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1247 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1248 1249 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1250 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1251 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1252 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1253 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1254 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1255 1256 __le32 tenant_id; 1257 u8 reserved[4]; 1258 __le16 queue_number; 1259 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1260 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1261 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1262 u8 reserved2[14]; 1263 /* response section */ 1264 u8 allocation_result; 1265 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1266 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1267 u8 response_reserved[7]; 1268 }; 1269 1270 struct i40e_aqc_remove_cloud_filters_completion { 1271 __le16 perfect_ovlan_used; 1272 __le16 perfect_ovlan_free; 1273 __le16 vlan_used; 1274 __le16 vlan_free; 1275 __le32 addr_high; 1276 __le32 addr_low; 1277 }; 1278 1279 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1280 1281 /* Add Mirror Rule (indirect or direct 0x0260) 1282 * Delete Mirror Rule (indirect or direct 0x0261) 1283 * note: some rule types (4,5) do not use an external buffer. 1284 * take care to set the flags correctly. 1285 */ 1286 struct i40e_aqc_add_delete_mirror_rule { 1287 __le16 seid; 1288 __le16 rule_type; 1289 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1290 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1291 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1292 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1293 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1294 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1295 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1296 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1297 __le16 num_entries; 1298 __le16 destination; /* VSI for add, rule id for delete */ 1299 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1300 __le32 addr_low; 1301 }; 1302 1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1304 1305 struct i40e_aqc_add_delete_mirror_rule_completion { 1306 u8 reserved[2]; 1307 __le16 rule_id; /* only used on add */ 1308 __le16 mirror_rules_used; 1309 __le16 mirror_rules_free; 1310 __le32 addr_high; 1311 __le32 addr_low; 1312 }; 1313 1314 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1315 1316 /* DCB 0x03xx*/ 1317 1318 /* PFC Ignore (direct 0x0301) 1319 * the command and response use the same descriptor structure 1320 */ 1321 struct i40e_aqc_pfc_ignore { 1322 u8 tc_bitmap; 1323 u8 command_flags; /* unused on response */ 1324 #define I40E_AQC_PFC_IGNORE_SET 0x80 1325 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1326 u8 reserved[14]; 1327 }; 1328 1329 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1330 1331 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1332 * with no parameters 1333 */ 1334 1335 /* TX scheduler 0x04xx */ 1336 1337 /* Almost all the indirect commands use 1338 * this generic struct to pass the SEID in param0 1339 */ 1340 struct i40e_aqc_tx_sched_ind { 1341 __le16 vsi_seid; 1342 u8 reserved[6]; 1343 __le32 addr_high; 1344 __le32 addr_low; 1345 }; 1346 1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1348 1349 /* Several commands respond with a set of queue set handles */ 1350 struct i40e_aqc_qs_handles_resp { 1351 __le16 qs_handles[8]; 1352 }; 1353 1354 /* Configure VSI BW limits (direct 0x0400) */ 1355 struct i40e_aqc_configure_vsi_bw_limit { 1356 __le16 vsi_seid; 1357 u8 reserved[2]; 1358 __le16 credit; 1359 u8 reserved1[2]; 1360 u8 max_credit; /* 0-3, limit = 2^max */ 1361 u8 reserved2[7]; 1362 }; 1363 1364 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1365 1366 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1367 * responds with i40e_aqc_qs_handles_resp 1368 */ 1369 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1370 u8 tc_valid_bits; 1371 u8 reserved[15]; 1372 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1373 1374 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1375 __le16 tc_bw_max[2]; 1376 u8 reserved1[28]; 1377 }; 1378 1379 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1380 1381 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1382 * responds with i40e_aqc_qs_handles_resp 1383 */ 1384 struct i40e_aqc_configure_vsi_tc_bw_data { 1385 u8 tc_valid_bits; 1386 u8 reserved[3]; 1387 u8 tc_bw_credits[8]; 1388 u8 reserved1[4]; 1389 __le16 qs_handles[8]; 1390 }; 1391 1392 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1393 1394 /* Query vsi bw configuration (indirect 0x0408) */ 1395 struct i40e_aqc_query_vsi_bw_config_resp { 1396 u8 tc_valid_bits; 1397 u8 tc_suspended_bits; 1398 u8 reserved[14]; 1399 __le16 qs_handles[8]; 1400 u8 reserved1[4]; 1401 __le16 port_bw_limit; 1402 u8 reserved2[2]; 1403 u8 max_bw; /* 0-3, limit = 2^max */ 1404 u8 reserved3[23]; 1405 }; 1406 1407 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1408 1409 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1410 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1411 u8 tc_valid_bits; 1412 u8 reserved[3]; 1413 u8 share_credits[8]; 1414 __le16 credits[8]; 1415 1416 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1417 __le16 tc_bw_max[2]; 1418 }; 1419 1420 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1421 1422 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1423 struct i40e_aqc_configure_switching_comp_bw_limit { 1424 __le16 seid; 1425 u8 reserved[2]; 1426 __le16 credit; 1427 u8 reserved1[2]; 1428 u8 max_bw; /* 0-3, limit = 2^max */ 1429 u8 reserved2[7]; 1430 }; 1431 1432 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1433 1434 /* Enable Physical Port ETS (indirect 0x0413) 1435 * Modify Physical Port ETS (indirect 0x0414) 1436 * Disable Physical Port ETS (indirect 0x0415) 1437 */ 1438 struct i40e_aqc_configure_switching_comp_ets_data { 1439 u8 reserved[4]; 1440 u8 tc_valid_bits; 1441 u8 seepage; 1442 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1443 u8 tc_strict_priority_flags; 1444 u8 reserved1[17]; 1445 u8 tc_bw_share_credits[8]; 1446 u8 reserved2[96]; 1447 }; 1448 1449 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1450 1451 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1452 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1453 u8 tc_valid_bits; 1454 u8 reserved[15]; 1455 __le16 tc_bw_credit[8]; 1456 1457 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1458 __le16 tc_bw_max[2]; 1459 u8 reserved1[28]; 1460 }; 1461 1462 I40E_CHECK_STRUCT_LEN(0x40, 1463 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1464 1465 /* Configure Switching Component Bandwidth Allocation per Tc 1466 * (indirect 0x0417) 1467 */ 1468 struct i40e_aqc_configure_switching_comp_bw_config_data { 1469 u8 tc_valid_bits; 1470 u8 reserved[2]; 1471 u8 absolute_credits; /* bool */ 1472 u8 tc_bw_share_credits[8]; 1473 u8 reserved1[20]; 1474 }; 1475 1476 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1477 1478 /* Query Switching Component Configuration (indirect 0x0418) */ 1479 struct i40e_aqc_query_switching_comp_ets_config_resp { 1480 u8 tc_valid_bits; 1481 u8 reserved[35]; 1482 __le16 port_bw_limit; 1483 u8 reserved1[2]; 1484 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1485 u8 reserved2[23]; 1486 }; 1487 1488 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1489 1490 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1491 struct i40e_aqc_query_port_ets_config_resp { 1492 u8 reserved[4]; 1493 u8 tc_valid_bits; 1494 u8 reserved1; 1495 u8 tc_strict_priority_bits; 1496 u8 reserved2; 1497 u8 tc_bw_share_credits[8]; 1498 __le16 tc_bw_limits[8]; 1499 1500 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1501 __le16 tc_bw_max[2]; 1502 u8 reserved3[32]; 1503 }; 1504 1505 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1506 1507 /* Query Switching Component Bandwidth Allocation per Traffic Type 1508 * (indirect 0x041A) 1509 */ 1510 struct i40e_aqc_query_switching_comp_bw_config_resp { 1511 u8 tc_valid_bits; 1512 u8 reserved[2]; 1513 u8 absolute_credits_enable; /* bool */ 1514 u8 tc_bw_share_credits[8]; 1515 __le16 tc_bw_limits[8]; 1516 1517 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1518 __le16 tc_bw_max[2]; 1519 }; 1520 1521 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1522 1523 /* Suspend/resume port TX traffic 1524 * (direct 0x041B and 0x041C) uses the generic SEID struct 1525 */ 1526 1527 /* Configure partition BW 1528 * (indirect 0x041D) 1529 */ 1530 struct i40e_aqc_configure_partition_bw_data { 1531 __le16 pf_valid_bits; 1532 u8 min_bw[16]; /* guaranteed bandwidth */ 1533 u8 max_bw[16]; /* bandwidth limit */ 1534 }; 1535 1536 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1537 1538 /* Get and set the active HMC resource profile and status. 1539 * (direct 0x0500) and (direct 0x0501) 1540 */ 1541 struct i40e_aq_get_set_hmc_resource_profile { 1542 u8 pm_profile; 1543 u8 pe_vf_enabled; 1544 u8 reserved[14]; 1545 }; 1546 1547 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1548 1549 enum i40e_aq_hmc_profile { 1550 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1551 I40E_HMC_PROFILE_DEFAULT = 1, 1552 I40E_HMC_PROFILE_FAVOR_VF = 2, 1553 I40E_HMC_PROFILE_EQUAL = 3, 1554 }; 1555 1556 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1557 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1558 1559 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1560 1561 /* set in param0 for get phy abilities to report qualified modules */ 1562 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1563 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1564 1565 enum i40e_aq_phy_type { 1566 I40E_PHY_TYPE_SGMII = 0x0, 1567 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1568 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1569 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1570 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1571 I40E_PHY_TYPE_XAUI = 0x5, 1572 I40E_PHY_TYPE_XFI = 0x6, 1573 I40E_PHY_TYPE_SFI = 0x7, 1574 I40E_PHY_TYPE_XLAUI = 0x8, 1575 I40E_PHY_TYPE_XLPPI = 0x9, 1576 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1577 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1578 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1579 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1580 I40E_PHY_TYPE_100BASE_TX = 0x11, 1581 I40E_PHY_TYPE_1000BASE_T = 0x12, 1582 I40E_PHY_TYPE_10GBASE_T = 0x13, 1583 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1584 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1585 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1586 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1587 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1588 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1589 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1590 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1591 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1592 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1593 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1594 I40E_PHY_TYPE_MAX 1595 }; 1596 1597 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1598 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1599 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1600 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1601 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1602 1603 enum i40e_aq_link_speed { 1604 I40E_LINK_SPEED_UNKNOWN = 0, 1605 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1606 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1607 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1608 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1609 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1610 }; 1611 1612 struct i40e_aqc_module_desc { 1613 u8 oui[3]; 1614 u8 reserved1; 1615 u8 part_number[16]; 1616 u8 revision[4]; 1617 u8 reserved2[8]; 1618 }; 1619 1620 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1621 1622 struct i40e_aq_get_phy_abilities_resp { 1623 __le32 phy_type; /* bitmap using the above enum for offsets */ 1624 u8 link_speed; /* bitmap using the above enum bit patterns */ 1625 u8 abilities; 1626 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1627 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1628 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1629 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1630 #define I40E_AQ_PHY_AN_ENABLED 0x10 1631 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1632 __le16 eee_capability; 1633 #define I40E_AQ_EEE_100BASE_TX 0x0002 1634 #define I40E_AQ_EEE_1000BASE_T 0x0004 1635 #define I40E_AQ_EEE_10GBASE_T 0x0008 1636 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1637 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1638 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1639 __le32 eeer_val; 1640 u8 d3_lpan; 1641 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1642 u8 reserved[3]; 1643 u8 phy_id[4]; 1644 u8 module_type[3]; 1645 u8 qualified_module_count; 1646 #define I40E_AQ_PHY_MAX_QMS 16 1647 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1648 }; 1649 1650 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1651 1652 /* Set PHY Config (direct 0x0601) */ 1653 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1654 __le32 phy_type; 1655 u8 link_speed; 1656 u8 abilities; 1657 /* bits 0-2 use the values from get_phy_abilities_resp */ 1658 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1659 #define I40E_AQ_PHY_ENABLE_AN 0x10 1660 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1661 __le16 eee_capability; 1662 __le32 eeer; 1663 u8 low_power_ctrl; 1664 u8 reserved[3]; 1665 }; 1666 1667 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1668 1669 /* Set MAC Config command data structure (direct 0x0603) */ 1670 struct i40e_aq_set_mac_config { 1671 __le16 max_frame_size; 1672 u8 params; 1673 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1674 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1675 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1676 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1677 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1678 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1679 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1680 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1681 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1687 u8 tx_timer_priority; /* bitmap */ 1688 __le16 tx_timer_value; 1689 __le16 fc_refresh_threshold; 1690 u8 reserved[8]; 1691 }; 1692 1693 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1694 1695 /* Restart Auto-Negotiation (direct 0x605) */ 1696 struct i40e_aqc_set_link_restart_an { 1697 u8 command; 1698 #define I40E_AQ_PHY_RESTART_AN 0x02 1699 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1700 u8 reserved[15]; 1701 }; 1702 1703 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1704 1705 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1706 struct i40e_aqc_get_link_status { 1707 __le16 command_flags; /* only field set on command */ 1708 #define I40E_AQ_LSE_MASK 0x3 1709 #define I40E_AQ_LSE_NOP 0x0 1710 #define I40E_AQ_LSE_DISABLE 0x2 1711 #define I40E_AQ_LSE_ENABLE 0x3 1712 /* only response uses this flag */ 1713 #define I40E_AQ_LSE_IS_ENABLED 0x1 1714 u8 phy_type; /* i40e_aq_phy_type */ 1715 u8 link_speed; /* i40e_aq_link_speed */ 1716 u8 link_info; 1717 #define I40E_AQ_LINK_UP 0x01 1718 #define I40E_AQ_LINK_FAULT 0x02 1719 #define I40E_AQ_LINK_FAULT_TX 0x04 1720 #define I40E_AQ_LINK_FAULT_RX 0x08 1721 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1722 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1723 #define I40E_AQ_SIGNAL_DETECT 0x80 1724 u8 an_info; 1725 #define I40E_AQ_AN_COMPLETED 0x01 1726 #define I40E_AQ_LP_AN_ABILITY 0x02 1727 #define I40E_AQ_PD_FAULT 0x04 1728 #define I40E_AQ_FEC_EN 0x08 1729 #define I40E_AQ_PHY_LOW_POWER 0x10 1730 #define I40E_AQ_LINK_PAUSE_TX 0x20 1731 #define I40E_AQ_LINK_PAUSE_RX 0x40 1732 #define I40E_AQ_QUALIFIED_MODULE 0x80 1733 u8 ext_info; 1734 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1735 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1736 #define I40E_AQ_LINK_TX_SHIFT 0x02 1737 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1738 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1739 #define I40E_AQ_LINK_TX_DRAINED 0x01 1740 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1741 #define I40E_AQ_LINK_FORCED_40G 0x10 1742 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1743 __le16 max_frame_size; 1744 u8 config; 1745 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1746 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1747 u8 reserved[5]; 1748 }; 1749 1750 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1751 1752 /* Set event mask command (direct 0x613) */ 1753 struct i40e_aqc_set_phy_int_mask { 1754 u8 reserved[8]; 1755 __le16 event_mask; 1756 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1757 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1758 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1759 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1760 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1761 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1762 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1763 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1764 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1765 u8 reserved1[6]; 1766 }; 1767 1768 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1769 1770 /* Get Local AN advt register (direct 0x0614) 1771 * Set Local AN advt register (direct 0x0615) 1772 * Get Link Partner AN advt register (direct 0x0616) 1773 */ 1774 struct i40e_aqc_an_advt_reg { 1775 __le32 local_an_reg0; 1776 __le16 local_an_reg1; 1777 u8 reserved[10]; 1778 }; 1779 1780 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1781 1782 /* Set Loopback mode (0x0618) */ 1783 struct i40e_aqc_set_lb_mode { 1784 __le16 lb_mode; 1785 #define I40E_AQ_LB_PHY_LOCAL 0x01 1786 #define I40E_AQ_LB_PHY_REMOTE 0x02 1787 #define I40E_AQ_LB_MAC_LOCAL 0x04 1788 u8 reserved[14]; 1789 }; 1790 1791 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1792 1793 /* Set PHY Debug command (0x0622) */ 1794 struct i40e_aqc_set_phy_debug { 1795 u8 command_flags; 1796 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1797 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1798 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1799 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1800 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1801 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1802 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1803 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1804 u8 reserved[15]; 1805 }; 1806 1807 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1808 1809 enum i40e_aq_phy_reg_type { 1810 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1811 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1812 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1813 }; 1814 1815 /* NVM Read command (indirect 0x0701) 1816 * NVM Erase commands (direct 0x0702) 1817 * NVM Update commands (indirect 0x0703) 1818 */ 1819 struct i40e_aqc_nvm_update { 1820 u8 command_flags; 1821 #define I40E_AQ_NVM_LAST_CMD 0x01 1822 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1823 u8 module_pointer; 1824 __le16 length; 1825 __le32 offset; 1826 __le32 addr_high; 1827 __le32 addr_low; 1828 }; 1829 1830 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1831 1832 /* NVM Config Read (indirect 0x0704) */ 1833 struct i40e_aqc_nvm_config_read { 1834 __le16 cmd_flags; 1835 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1836 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1837 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1838 __le16 element_count; 1839 __le16 element_id; /* Feature/field ID */ 1840 __le16 element_id_msw; /* MSWord of field ID */ 1841 __le32 address_high; 1842 __le32 address_low; 1843 }; 1844 1845 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1846 1847 /* NVM Config Write (indirect 0x0705) */ 1848 struct i40e_aqc_nvm_config_write { 1849 __le16 cmd_flags; 1850 __le16 element_count; 1851 u8 reserved[4]; 1852 __le32 address_high; 1853 __le32 address_low; 1854 }; 1855 1856 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1857 1858 /* Used for 0x0704 as well as for 0x0705 commands */ 1859 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1860 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1861 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1862 #define I40E_AQ_ANVM_FEATURE 0 1863 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1864 struct i40e_aqc_nvm_config_data_feature { 1865 __le16 feature_id; 1866 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1867 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1868 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1869 __le16 feature_options; 1870 __le16 feature_selection; 1871 }; 1872 1873 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1874 1875 struct i40e_aqc_nvm_config_data_immediate_field { 1876 __le32 field_id; 1877 __le32 field_value; 1878 __le16 field_options; 1879 __le16 reserved; 1880 }; 1881 1882 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1883 1884 /* Send to PF command (indirect 0x0801) id is only used by PF 1885 * Send to VF command (indirect 0x0802) id is only used by PF 1886 * Send to Peer PF command (indirect 0x0803) 1887 */ 1888 struct i40e_aqc_pf_vf_message { 1889 __le32 id; 1890 u8 reserved[4]; 1891 __le32 addr_high; 1892 __le32 addr_low; 1893 }; 1894 1895 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1896 1897 /* Alternate structure */ 1898 1899 /* Direct write (direct 0x0900) 1900 * Direct read (direct 0x0902) 1901 */ 1902 struct i40e_aqc_alternate_write { 1903 __le32 address0; 1904 __le32 data0; 1905 __le32 address1; 1906 __le32 data1; 1907 }; 1908 1909 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1910 1911 /* Indirect write (indirect 0x0901) 1912 * Indirect read (indirect 0x0903) 1913 */ 1914 1915 struct i40e_aqc_alternate_ind_write { 1916 __le32 address; 1917 __le32 length; 1918 __le32 addr_high; 1919 __le32 addr_low; 1920 }; 1921 1922 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1923 1924 /* Done alternate write (direct 0x0904) 1925 * uses i40e_aq_desc 1926 */ 1927 struct i40e_aqc_alternate_write_done { 1928 __le16 cmd_flags; 1929 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1930 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1931 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1932 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1933 u8 reserved[14]; 1934 }; 1935 1936 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1937 1938 /* Set OEM mode (direct 0x0905) */ 1939 struct i40e_aqc_alternate_set_mode { 1940 __le32 mode; 1941 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1942 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1943 u8 reserved[12]; 1944 }; 1945 1946 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1947 1948 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1949 1950 /* async events 0x10xx */ 1951 1952 /* Lan Queue Overflow Event (direct, 0x1001) */ 1953 struct i40e_aqc_lan_overflow { 1954 __le32 prtdcb_rupto; 1955 __le32 otx_ctl; 1956 u8 reserved[8]; 1957 }; 1958 1959 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1960 1961 /* Get LLDP MIB (indirect 0x0A00) */ 1962 struct i40e_aqc_lldp_get_mib { 1963 u8 type; 1964 u8 reserved1; 1965 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1966 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1967 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1968 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1969 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1970 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1971 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1972 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1973 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1974 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1975 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1976 __le16 local_len; 1977 __le16 remote_len; 1978 u8 reserved2[2]; 1979 __le32 addr_high; 1980 __le32 addr_low; 1981 }; 1982 1983 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1984 1985 /* Configure LLDP MIB Change Event (direct 0x0A01) 1986 * also used for the event (with type in the command field) 1987 */ 1988 struct i40e_aqc_lldp_update_mib { 1989 u8 command; 1990 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1991 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1992 u8 reserved[7]; 1993 __le32 addr_high; 1994 __le32 addr_low; 1995 }; 1996 1997 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1998 1999 /* Add LLDP TLV (indirect 0x0A02) 2000 * Delete LLDP TLV (indirect 0x0A04) 2001 */ 2002 struct i40e_aqc_lldp_add_tlv { 2003 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2004 u8 reserved1[1]; 2005 __le16 len; 2006 u8 reserved2[4]; 2007 __le32 addr_high; 2008 __le32 addr_low; 2009 }; 2010 2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2012 2013 /* Update LLDP TLV (indirect 0x0A03) */ 2014 struct i40e_aqc_lldp_update_tlv { 2015 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2016 u8 reserved; 2017 __le16 old_len; 2018 __le16 new_offset; 2019 __le16 new_len; 2020 __le32 addr_high; 2021 __le32 addr_low; 2022 }; 2023 2024 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2025 2026 /* Stop LLDP (direct 0x0A05) */ 2027 struct i40e_aqc_lldp_stop { 2028 u8 command; 2029 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2030 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2031 u8 reserved[15]; 2032 }; 2033 2034 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2035 2036 /* Start LLDP (direct 0x0A06) */ 2037 2038 struct i40e_aqc_lldp_start { 2039 u8 command; 2040 #define I40E_AQ_LLDP_AGENT_START 0x1 2041 u8 reserved[15]; 2042 }; 2043 2044 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2045 2046 /* Get CEE DCBX Oper Config (0x0A07) 2047 * uses the generic descriptor struct 2048 * returns below as indirect response 2049 */ 2050 2051 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2052 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2053 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2054 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2055 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2056 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2057 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2058 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2059 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2060 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2061 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2062 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2063 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2064 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2065 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xA 2066 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2067 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2068 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2069 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2070 u8 reserved1; 2071 u8 oper_num_tc; 2072 u8 oper_prio_tc[4]; 2073 u8 reserved2; 2074 u8 oper_tc_bw[8]; 2075 u8 oper_pfc_en; 2076 u8 reserved3; 2077 __le16 oper_app_prio; 2078 u8 reserved4; 2079 __le16 tlv_status; 2080 }; 2081 2082 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2083 2084 struct i40e_aqc_get_cee_dcb_cfg_resp { 2085 u8 oper_num_tc; 2086 u8 oper_prio_tc[4]; 2087 u8 oper_tc_bw[8]; 2088 u8 oper_pfc_en; 2089 __le16 oper_app_prio; 2090 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2091 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2092 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2093 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2094 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2095 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2096 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2097 __le32 tlv_status; 2098 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2099 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2100 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2101 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2102 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2103 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2104 u8 reserved[12]; 2105 }; 2106 2107 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2108 2109 /* Set Local LLDP MIB (indirect 0x0A08) 2110 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2111 */ 2112 struct i40e_aqc_lldp_set_local_mib { 2113 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2114 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2115 u8 type; 2116 u8 reserved0; 2117 __le16 length; 2118 u8 reserved1[4]; 2119 __le32 address_high; 2120 __le32 address_low; 2121 }; 2122 2123 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2124 2125 /* Stop/Start LLDP Agent (direct 0x0A09) 2126 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2127 */ 2128 struct i40e_aqc_lldp_stop_start_specific_agent { 2129 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2130 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2131 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2132 u8 command; 2133 u8 reserved[15]; 2134 }; 2135 2136 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2137 2138 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2139 struct i40e_aqc_add_udp_tunnel { 2140 __le16 udp_port; 2141 u8 reserved0[3]; 2142 u8 protocol_type; 2143 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2144 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2145 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2146 u8 reserved1[10]; 2147 }; 2148 2149 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2150 2151 struct i40e_aqc_add_udp_tunnel_completion { 2152 __le16 udp_port; 2153 u8 filter_entry_index; 2154 u8 multiple_pfs; 2155 #define I40E_AQC_SINGLE_PF 0x0 2156 #define I40E_AQC_MULTIPLE_PFS 0x1 2157 u8 total_filters; 2158 u8 reserved[11]; 2159 }; 2160 2161 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2162 2163 /* remove UDP Tunnel command (0x0B01) */ 2164 struct i40e_aqc_remove_udp_tunnel { 2165 u8 reserved[2]; 2166 u8 index; /* 0 to 15 */ 2167 u8 reserved2[13]; 2168 }; 2169 2170 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2171 2172 struct i40e_aqc_del_udp_tunnel_completion { 2173 __le16 udp_port; 2174 u8 index; /* 0 to 15 */ 2175 u8 multiple_pfs; 2176 u8 total_filters_used; 2177 u8 reserved1[11]; 2178 }; 2179 2180 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2181 2182 /* tunnel key structure 0x0B10 */ 2183 2184 struct i40e_aqc_tunnel_key_structure { 2185 u8 key1_off; 2186 u8 key2_off; 2187 u8 key1_len; /* 0 to 15 */ 2188 u8 key2_len; /* 0 to 15 */ 2189 u8 flags; 2190 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2191 /* response flags */ 2192 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2193 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2194 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2195 u8 network_key_index; 2196 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2197 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2198 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2199 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2200 u8 reserved[10]; 2201 }; 2202 2203 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2204 2205 /* OEM mode commands (direct 0xFE0x) */ 2206 struct i40e_aqc_oem_param_change { 2207 __le32 param_type; 2208 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2209 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2210 #define I40E_AQ_OEM_PARAM_MAC 2 2211 __le32 param_value1; 2212 __le16 param_value2; 2213 u8 reserved[6]; 2214 }; 2215 2216 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2217 2218 struct i40e_aqc_oem_state_change { 2219 __le32 state; 2220 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2221 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2222 u8 reserved[12]; 2223 }; 2224 2225 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2226 2227 /* Initialize OCSD (0xFE02, direct) */ 2228 struct i40e_aqc_opc_oem_ocsd_initialize { 2229 u8 type_status; 2230 u8 reserved1[3]; 2231 __le32 ocsd_memory_block_addr_high; 2232 __le32 ocsd_memory_block_addr_low; 2233 __le32 requested_update_interval; 2234 }; 2235 2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2237 2238 /* Initialize OCBB (0xFE03, direct) */ 2239 struct i40e_aqc_opc_oem_ocbb_initialize { 2240 u8 type_status; 2241 u8 reserved1[3]; 2242 __le32 ocbb_memory_block_addr_high; 2243 __le32 ocbb_memory_block_addr_low; 2244 u8 reserved2[4]; 2245 }; 2246 2247 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2248 2249 /* debug commands */ 2250 2251 /* get device id (0xFF00) uses the generic structure */ 2252 2253 /* set test more (0xFF01, internal) */ 2254 2255 struct i40e_acq_set_test_mode { 2256 u8 mode; 2257 #define I40E_AQ_TEST_PARTIAL 0 2258 #define I40E_AQ_TEST_FULL 1 2259 #define I40E_AQ_TEST_NVM 2 2260 u8 reserved[3]; 2261 u8 command; 2262 #define I40E_AQ_TEST_OPEN 0 2263 #define I40E_AQ_TEST_CLOSE 1 2264 #define I40E_AQ_TEST_INC 2 2265 u8 reserved2[3]; 2266 __le32 address_high; 2267 __le32 address_low; 2268 }; 2269 2270 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2271 2272 /* Debug Read Register command (0xFF03) 2273 * Debug Write Register command (0xFF04) 2274 */ 2275 struct i40e_aqc_debug_reg_read_write { 2276 __le32 reserved; 2277 __le32 address; 2278 __le32 value_high; 2279 __le32 value_low; 2280 }; 2281 2282 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2283 2284 /* Scatter/gather Reg Read (indirect 0xFF05) 2285 * Scatter/gather Reg Write (indirect 0xFF06) 2286 */ 2287 2288 /* i40e_aq_desc is used for the command */ 2289 struct i40e_aqc_debug_reg_sg_element_data { 2290 __le32 address; 2291 __le32 value; 2292 }; 2293 2294 /* Debug Modify register (direct 0xFF07) */ 2295 struct i40e_aqc_debug_modify_reg { 2296 __le32 address; 2297 __le32 value; 2298 __le32 clear_mask; 2299 __le32 set_mask; 2300 }; 2301 2302 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2303 2304 /* dump internal data (0xFF08, indirect) */ 2305 2306 #define I40E_AQ_CLUSTER_ID_AUX 0 2307 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2308 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2309 #define I40E_AQ_CLUSTER_ID_HMC 3 2310 #define I40E_AQ_CLUSTER_ID_MAC0 4 2311 #define I40E_AQ_CLUSTER_ID_MAC1 5 2312 #define I40E_AQ_CLUSTER_ID_MAC2 6 2313 #define I40E_AQ_CLUSTER_ID_MAC3 7 2314 #define I40E_AQ_CLUSTER_ID_DCB 8 2315 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2316 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2317 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2318 2319 struct i40e_aqc_debug_dump_internals { 2320 u8 cluster_id; 2321 u8 table_id; 2322 __le16 data_size; 2323 __le32 idx; 2324 __le32 address_high; 2325 __le32 address_low; 2326 }; 2327 2328 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2329 2330 struct i40e_aqc_debug_modify_internals { 2331 u8 cluster_id; 2332 u8 cluster_specific_params[7]; 2333 __le32 address_high; 2334 __le32 address_low; 2335 }; 2336 2337 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2338 2339 #endif 2340