1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR 0x0004 38 39 struct i40e_aq_desc { 40 __le16 flags; 41 __le16 opcode; 42 __le16 datalen; 43 __le16 retval; 44 __le32 cookie_high; 45 __le32 cookie_low; 46 union { 47 struct { 48 __le32 param0; 49 __le32 param1; 50 __le32 param2; 51 __le32 param3; 52 } internal; 53 struct { 54 __le32 param0; 55 __le32 param1; 56 __le32 addr_high; 57 __le32 addr_low; 58 } external; 59 u8 raw[16]; 60 } params; 61 }; 62 63 /* Flags sub-structure 64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 66 */ 67 68 /* command flags and offsets*/ 69 #define I40E_AQ_FLAG_DD_SHIFT 0 70 #define I40E_AQ_FLAG_CMP_SHIFT 1 71 #define I40E_AQ_FLAG_ERR_SHIFT 2 72 #define I40E_AQ_FLAG_VFE_SHIFT 3 73 #define I40E_AQ_FLAG_LB_SHIFT 9 74 #define I40E_AQ_FLAG_RD_SHIFT 10 75 #define I40E_AQ_FLAG_VFC_SHIFT 11 76 #define I40E_AQ_FLAG_BUF_SHIFT 12 77 #define I40E_AQ_FLAG_SI_SHIFT 13 78 #define I40E_AQ_FLAG_EI_SHIFT 14 79 #define I40E_AQ_FLAG_FE_SHIFT 15 80 81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 92 93 /* error codes */ 94 enum i40e_admin_queue_err { 95 I40E_AQ_RC_OK = 0, /* success */ 96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 97 I40E_AQ_RC_ENOENT = 2, /* No such element */ 98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 100 I40E_AQ_RC_EIO = 5, /* I/O error */ 101 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 103 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 105 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 106 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 108 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 117 I40E_AQ_RC_EFBIG = 22, /* File too large */ 118 }; 119 120 /* Admin Queue command opcodes */ 121 enum i40e_admin_queue_opc { 122 /* aq commands */ 123 i40e_aqc_opc_get_version = 0x0001, 124 i40e_aqc_opc_driver_version = 0x0002, 125 i40e_aqc_opc_queue_shutdown = 0x0003, 126 i40e_aqc_opc_set_pf_context = 0x0004, 127 128 /* resource ownership */ 129 i40e_aqc_opc_request_resource = 0x0008, 130 i40e_aqc_opc_release_resource = 0x0009, 131 132 i40e_aqc_opc_list_func_capabilities = 0x000A, 133 i40e_aqc_opc_list_dev_capabilities = 0x000B, 134 135 /* LAA */ 136 i40e_aqc_opc_mac_address_read = 0x0107, 137 i40e_aqc_opc_mac_address_write = 0x0108, 138 139 /* PXE */ 140 i40e_aqc_opc_clear_pxe_mode = 0x0110, 141 142 /* internal switch commands */ 143 i40e_aqc_opc_get_switch_config = 0x0200, 144 i40e_aqc_opc_add_statistics = 0x0201, 145 i40e_aqc_opc_remove_statistics = 0x0202, 146 i40e_aqc_opc_set_port_parameters = 0x0203, 147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 148 149 i40e_aqc_opc_add_vsi = 0x0210, 150 i40e_aqc_opc_update_vsi_parameters = 0x0211, 151 i40e_aqc_opc_get_vsi_parameters = 0x0212, 152 153 i40e_aqc_opc_add_pv = 0x0220, 154 i40e_aqc_opc_update_pv_parameters = 0x0221, 155 i40e_aqc_opc_get_pv_parameters = 0x0222, 156 157 i40e_aqc_opc_add_veb = 0x0230, 158 i40e_aqc_opc_update_veb_parameters = 0x0231, 159 i40e_aqc_opc_get_veb_parameters = 0x0232, 160 161 i40e_aqc_opc_delete_element = 0x0243, 162 163 i40e_aqc_opc_add_macvlan = 0x0250, 164 i40e_aqc_opc_remove_macvlan = 0x0251, 165 i40e_aqc_opc_add_vlan = 0x0252, 166 i40e_aqc_opc_remove_vlan = 0x0253, 167 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 168 i40e_aqc_opc_add_tag = 0x0255, 169 i40e_aqc_opc_remove_tag = 0x0256, 170 i40e_aqc_opc_add_multicast_etag = 0x0257, 171 i40e_aqc_opc_remove_multicast_etag = 0x0258, 172 i40e_aqc_opc_update_tag = 0x0259, 173 i40e_aqc_opc_add_control_packet_filter = 0x025A, 174 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 175 i40e_aqc_opc_add_cloud_filters = 0x025C, 176 i40e_aqc_opc_remove_cloud_filters = 0x025D, 177 178 i40e_aqc_opc_add_mirror_rule = 0x0260, 179 i40e_aqc_opc_delete_mirror_rule = 0x0261, 180 181 /* DCB commands */ 182 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 183 i40e_aqc_opc_dcb_updated = 0x0302, 184 185 /* TX scheduler */ 186 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 187 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 188 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 189 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 190 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 191 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 192 193 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 194 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 195 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 196 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 197 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 198 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 199 i40e_aqc_opc_query_port_ets_config = 0x0419, 200 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 201 i40e_aqc_opc_suspend_port_tx = 0x041B, 202 i40e_aqc_opc_resume_port_tx = 0x041C, 203 i40e_aqc_opc_configure_partition_bw = 0x041D, 204 205 /* hmc */ 206 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 207 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 208 209 /* phy commands*/ 210 i40e_aqc_opc_get_phy_abilities = 0x0600, 211 i40e_aqc_opc_set_phy_config = 0x0601, 212 i40e_aqc_opc_set_mac_config = 0x0603, 213 i40e_aqc_opc_set_link_restart_an = 0x0605, 214 i40e_aqc_opc_get_link_status = 0x0607, 215 i40e_aqc_opc_set_phy_int_mask = 0x0613, 216 i40e_aqc_opc_get_local_advt_reg = 0x0614, 217 i40e_aqc_opc_set_local_advt_reg = 0x0615, 218 i40e_aqc_opc_get_partner_advt = 0x0616, 219 i40e_aqc_opc_set_lb_modes = 0x0618, 220 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 221 i40e_aqc_opc_set_phy_debug = 0x0622, 222 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 223 224 /* NVM commands */ 225 i40e_aqc_opc_nvm_read = 0x0701, 226 i40e_aqc_opc_nvm_erase = 0x0702, 227 i40e_aqc_opc_nvm_update = 0x0703, 228 i40e_aqc_opc_nvm_config_read = 0x0704, 229 i40e_aqc_opc_nvm_config_write = 0x0705, 230 231 /* virtualization commands */ 232 i40e_aqc_opc_send_msg_to_pf = 0x0801, 233 i40e_aqc_opc_send_msg_to_vf = 0x0802, 234 i40e_aqc_opc_send_msg_to_peer = 0x0803, 235 236 /* alternate structure */ 237 i40e_aqc_opc_alternate_write = 0x0900, 238 i40e_aqc_opc_alternate_write_indirect = 0x0901, 239 i40e_aqc_opc_alternate_read = 0x0902, 240 i40e_aqc_opc_alternate_read_indirect = 0x0903, 241 i40e_aqc_opc_alternate_write_done = 0x0904, 242 i40e_aqc_opc_alternate_set_mode = 0x0905, 243 i40e_aqc_opc_alternate_clear_port = 0x0906, 244 245 /* LLDP commands */ 246 i40e_aqc_opc_lldp_get_mib = 0x0A00, 247 i40e_aqc_opc_lldp_update_mib = 0x0A01, 248 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 249 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 251 i40e_aqc_opc_lldp_stop = 0x0A05, 252 i40e_aqc_opc_lldp_start = 0x0A06, 253 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 254 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 255 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 256 257 /* Tunnel commands */ 258 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 259 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 260 i40e_aqc_opc_set_rss_key = 0x0B02, 261 i40e_aqc_opc_set_rss_lut = 0x0B03, 262 i40e_aqc_opc_get_rss_key = 0x0B04, 263 i40e_aqc_opc_get_rss_lut = 0x0B05, 264 265 /* Async Events */ 266 i40e_aqc_opc_event_lan_overflow = 0x1001, 267 268 /* OEM commands */ 269 i40e_aqc_opc_oem_parameter_change = 0xFE00, 270 i40e_aqc_opc_oem_device_status_change = 0xFE01, 271 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 272 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 273 274 /* debug commands */ 275 i40e_aqc_opc_debug_read_reg = 0xFF03, 276 i40e_aqc_opc_debug_write_reg = 0xFF04, 277 i40e_aqc_opc_debug_modify_reg = 0xFF07, 278 i40e_aqc_opc_debug_dump_internals = 0xFF08, 279 }; 280 281 /* command structures and indirect data structures */ 282 283 /* Structure naming conventions: 284 * - no suffix for direct command descriptor structures 285 * - _data for indirect sent data 286 * - _resp for indirect return data (data which is both will use _data) 287 * - _completion for direct return data 288 * - _element_ for repeated elements (may also be _data or _resp) 289 * 290 * Command structures are expected to overlay the params.raw member of the basic 291 * descriptor, and as such cannot exceed 16 bytes in length. 292 */ 293 294 /* This macro is used to generate a compilation error if a structure 295 * is not exactly the correct length. It gives a divide by zero error if the 296 * structure is not of the correct size, otherwise it creates an enum that is 297 * never used. 298 */ 299 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 300 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 301 302 /* This macro is used extensively to ensure that command structures are 16 303 * bytes in length as they have to map to the raw array of that size. 304 */ 305 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 306 307 /* internal (0x00XX) commands */ 308 309 /* Get version (direct 0x0001) */ 310 struct i40e_aqc_get_version { 311 __le32 rom_ver; 312 __le32 fw_build; 313 __le16 fw_major; 314 __le16 fw_minor; 315 __le16 api_major; 316 __le16 api_minor; 317 }; 318 319 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 320 321 /* Send driver version (indirect 0x0002) */ 322 struct i40e_aqc_driver_version { 323 u8 driver_major_ver; 324 u8 driver_minor_ver; 325 u8 driver_build_ver; 326 u8 driver_subbuild_ver; 327 u8 reserved[4]; 328 __le32 address_high; 329 __le32 address_low; 330 }; 331 332 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 333 334 /* Queue Shutdown (direct 0x0003) */ 335 struct i40e_aqc_queue_shutdown { 336 __le32 driver_unloading; 337 #define I40E_AQ_DRIVER_UNLOADING 0x1 338 u8 reserved[12]; 339 }; 340 341 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 342 343 /* Set PF context (0x0004, direct) */ 344 struct i40e_aqc_set_pf_context { 345 u8 pf_id; 346 u8 reserved[15]; 347 }; 348 349 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 350 351 /* Request resource ownership (direct 0x0008) 352 * Release resource ownership (direct 0x0009) 353 */ 354 #define I40E_AQ_RESOURCE_NVM 1 355 #define I40E_AQ_RESOURCE_SDP 2 356 #define I40E_AQ_RESOURCE_ACCESS_READ 1 357 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 358 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 359 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 360 361 struct i40e_aqc_request_resource { 362 __le16 resource_id; 363 __le16 access_type; 364 __le32 timeout; 365 __le32 resource_number; 366 u8 reserved[4]; 367 }; 368 369 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 370 371 /* Get function capabilities (indirect 0x000A) 372 * Get device capabilities (indirect 0x000B) 373 */ 374 struct i40e_aqc_list_capabilites { 375 u8 command_flags; 376 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 377 u8 pf_index; 378 u8 reserved[2]; 379 __le32 count; 380 __le32 addr_high; 381 __le32 addr_low; 382 }; 383 384 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 385 386 struct i40e_aqc_list_capabilities_element_resp { 387 __le16 id; 388 u8 major_rev; 389 u8 minor_rev; 390 __le32 number; 391 __le32 logical_id; 392 __le32 phys_id; 393 u8 reserved[16]; 394 }; 395 396 /* list of caps */ 397 398 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 399 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 400 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 401 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 402 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 403 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 404 #define I40E_AQ_CAP_ID_SRIOV 0x0012 405 #define I40E_AQ_CAP_ID_VF 0x0013 406 #define I40E_AQ_CAP_ID_VMDQ 0x0014 407 #define I40E_AQ_CAP_ID_8021QBG 0x0015 408 #define I40E_AQ_CAP_ID_8021QBR 0x0016 409 #define I40E_AQ_CAP_ID_VSI 0x0017 410 #define I40E_AQ_CAP_ID_DCB 0x0018 411 #define I40E_AQ_CAP_ID_FCOE 0x0021 412 #define I40E_AQ_CAP_ID_ISCSI 0x0022 413 #define I40E_AQ_CAP_ID_RSS 0x0040 414 #define I40E_AQ_CAP_ID_RXQ 0x0041 415 #define I40E_AQ_CAP_ID_TXQ 0x0042 416 #define I40E_AQ_CAP_ID_MSIX 0x0043 417 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 418 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 419 #define I40E_AQ_CAP_ID_1588 0x0046 420 #define I40E_AQ_CAP_ID_IWARP 0x0051 421 #define I40E_AQ_CAP_ID_LED 0x0061 422 #define I40E_AQ_CAP_ID_SDP 0x0062 423 #define I40E_AQ_CAP_ID_MDIO 0x0063 424 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 425 #define I40E_AQ_CAP_ID_CEM 0x00F2 426 427 /* Set CPPM Configuration (direct 0x0103) */ 428 struct i40e_aqc_cppm_configuration { 429 __le16 command_flags; 430 #define I40E_AQ_CPPM_EN_LTRC 0x0800 431 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 432 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 433 #define I40E_AQ_CPPM_EN_HPTC 0x4000 434 #define I40E_AQ_CPPM_EN_DMARC 0x8000 435 __le16 ttlx; 436 __le32 dmacr; 437 __le16 dmcth; 438 u8 hptc; 439 u8 reserved; 440 __le32 pfltrc; 441 }; 442 443 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 444 445 /* Set ARP Proxy command / response (indirect 0x0104) */ 446 struct i40e_aqc_arp_proxy_data { 447 __le16 command_flags; 448 #define I40E_AQ_ARP_INIT_IPV4 0x0008 449 #define I40E_AQ_ARP_UNSUP_CTL 0x0010 450 #define I40E_AQ_ARP_ENA 0x0020 451 #define I40E_AQ_ARP_ADD_IPV4 0x0040 452 #define I40E_AQ_ARP_DEL_IPV4 0x0080 453 __le16 table_id; 454 __le32 pfpm_proxyfc; 455 __le32 ip_addr; 456 u8 mac_addr[6]; 457 u8 reserved[2]; 458 }; 459 460 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 461 462 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 463 struct i40e_aqc_ns_proxy_data { 464 __le16 table_idx_mac_addr_0; 465 __le16 table_idx_mac_addr_1; 466 __le16 table_idx_ipv6_0; 467 __le16 table_idx_ipv6_1; 468 __le16 control; 469 #define I40E_AQ_NS_PROXY_ADD_0 0x0100 470 #define I40E_AQ_NS_PROXY_DEL_0 0x0200 471 #define I40E_AQ_NS_PROXY_ADD_1 0x0400 472 #define I40E_AQ_NS_PROXY_DEL_1 0x0800 473 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 474 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 475 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 476 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 477 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 478 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 479 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 480 u8 mac_addr_0[6]; 481 u8 mac_addr_1[6]; 482 u8 local_mac_addr[6]; 483 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 484 u8 ipv6_addr_1[16]; 485 }; 486 487 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 488 489 /* Manage LAA Command (0x0106) - obsolete */ 490 struct i40e_aqc_mng_laa { 491 __le16 command_flags; 492 #define I40E_AQ_LAA_FLAG_WR 0x8000 493 u8 reserved[2]; 494 __le32 sal; 495 __le16 sah; 496 u8 reserved2[6]; 497 }; 498 499 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 500 501 /* Manage MAC Address Read Command (indirect 0x0107) */ 502 struct i40e_aqc_mac_address_read { 503 __le16 command_flags; 504 #define I40E_AQC_LAN_ADDR_VALID 0x10 505 #define I40E_AQC_SAN_ADDR_VALID 0x20 506 #define I40E_AQC_PORT_ADDR_VALID 0x40 507 #define I40E_AQC_WOL_ADDR_VALID 0x80 508 #define I40E_AQC_MC_MAG_EN_VALID 0x100 509 #define I40E_AQC_ADDR_VALID_MASK 0x1F0 510 u8 reserved[6]; 511 __le32 addr_high; 512 __le32 addr_low; 513 }; 514 515 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 516 517 struct i40e_aqc_mac_address_read_data { 518 u8 pf_lan_mac[6]; 519 u8 pf_san_mac[6]; 520 u8 port_mac[6]; 521 u8 pf_wol_mac[6]; 522 }; 523 524 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 525 526 /* Manage MAC Address Write Command (0x0108) */ 527 struct i40e_aqc_mac_address_write { 528 __le16 command_flags; 529 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 530 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 531 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 532 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 533 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 534 535 __le16 mac_sah; 536 __le32 mac_sal; 537 u8 reserved[8]; 538 }; 539 540 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 541 542 /* PXE commands (0x011x) */ 543 544 /* Clear PXE Command and response (direct 0x0110) */ 545 struct i40e_aqc_clear_pxe { 546 u8 rx_cnt; 547 u8 reserved[15]; 548 }; 549 550 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 551 552 /* Switch configuration commands (0x02xx) */ 553 554 /* Used by many indirect commands that only pass an seid and a buffer in the 555 * command 556 */ 557 struct i40e_aqc_switch_seid { 558 __le16 seid; 559 u8 reserved[6]; 560 __le32 addr_high; 561 __le32 addr_low; 562 }; 563 564 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 565 566 /* Get Switch Configuration command (indirect 0x0200) 567 * uses i40e_aqc_switch_seid for the descriptor 568 */ 569 struct i40e_aqc_get_switch_config_header_resp { 570 __le16 num_reported; 571 __le16 num_total; 572 u8 reserved[12]; 573 }; 574 575 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 576 577 struct i40e_aqc_switch_config_element_resp { 578 u8 element_type; 579 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 580 #define I40E_AQ_SW_ELEM_TYPE_PF 2 581 #define I40E_AQ_SW_ELEM_TYPE_VF 3 582 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 583 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 584 #define I40E_AQ_SW_ELEM_TYPE_PV 16 585 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 586 #define I40E_AQ_SW_ELEM_TYPE_PA 18 587 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 588 u8 revision; 589 #define I40E_AQ_SW_ELEM_REV_1 1 590 __le16 seid; 591 __le16 uplink_seid; 592 __le16 downlink_seid; 593 u8 reserved[3]; 594 u8 connection_type; 595 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 596 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 597 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 598 __le16 scheduler_id; 599 __le16 element_info; 600 }; 601 602 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 603 604 /* Get Switch Configuration (indirect 0x0200) 605 * an array of elements are returned in the response buffer 606 * the first in the array is the header, remainder are elements 607 */ 608 struct i40e_aqc_get_switch_config_resp { 609 struct i40e_aqc_get_switch_config_header_resp header; 610 struct i40e_aqc_switch_config_element_resp element[1]; 611 }; 612 613 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 614 615 /* Add Statistics (direct 0x0201) 616 * Remove Statistics (direct 0x0202) 617 */ 618 struct i40e_aqc_add_remove_statistics { 619 __le16 seid; 620 __le16 vlan; 621 __le16 stat_index; 622 u8 reserved[10]; 623 }; 624 625 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 626 627 /* Set Port Parameters command (direct 0x0203) */ 628 struct i40e_aqc_set_port_parameters { 629 __le16 command_flags; 630 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 631 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 632 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 633 __le16 bad_frame_vsi; 634 __le16 default_seid; /* reserved for command */ 635 u8 reserved[10]; 636 }; 637 638 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 639 640 /* Get Switch Resource Allocation (indirect 0x0204) */ 641 struct i40e_aqc_get_switch_resource_alloc { 642 u8 num_entries; /* reserved for command */ 643 u8 reserved[7]; 644 __le32 addr_high; 645 __le32 addr_low; 646 }; 647 648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 649 650 /* expect an array of these structs in the response buffer */ 651 struct i40e_aqc_switch_resource_alloc_element_resp { 652 u8 resource_type; 653 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 654 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 655 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 656 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 657 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 658 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 659 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 660 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 661 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 662 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 663 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 664 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 665 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 666 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 667 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 668 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 669 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 670 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 671 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 672 u8 reserved1; 673 __le16 guaranteed; 674 __le16 total; 675 __le16 used; 676 __le16 total_unalloced; 677 u8 reserved2[6]; 678 }; 679 680 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 681 682 /* Add VSI (indirect 0x0210) 683 * this indirect command uses struct i40e_aqc_vsi_properties_data 684 * as the indirect buffer (128 bytes) 685 * 686 * Update VSI (indirect 0x211) 687 * uses the same data structure as Add VSI 688 * 689 * Get VSI (indirect 0x0212) 690 * uses the same completion and data structure as Add VSI 691 */ 692 struct i40e_aqc_add_get_update_vsi { 693 __le16 uplink_seid; 694 u8 connection_type; 695 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 696 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 697 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 698 u8 reserved1; 699 u8 vf_id; 700 u8 reserved2; 701 __le16 vsi_flags; 702 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 703 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 704 #define I40E_AQ_VSI_TYPE_VF 0x0 705 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 706 #define I40E_AQ_VSI_TYPE_PF 0x2 707 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 708 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 709 __le32 addr_high; 710 __le32 addr_low; 711 }; 712 713 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 714 715 struct i40e_aqc_add_get_update_vsi_completion { 716 __le16 seid; 717 __le16 vsi_number; 718 __le16 vsi_used; 719 __le16 vsi_free; 720 __le32 addr_high; 721 __le32 addr_low; 722 }; 723 724 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 725 726 struct i40e_aqc_vsi_properties_data { 727 /* first 96 byte are written by SW */ 728 __le16 valid_sections; 729 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 730 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 731 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 732 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 733 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 734 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 735 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 736 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 737 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 738 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 739 /* switch section */ 740 __le16 switch_id; /* 12bit id combined with flags below */ 741 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 742 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 743 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 744 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 745 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 746 u8 sw_reserved[2]; 747 /* security section */ 748 u8 sec_flags; 749 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 750 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 751 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 752 u8 sec_reserved; 753 /* VLAN section */ 754 __le16 pvid; /* VLANS include priority bits */ 755 __le16 fcoe_pvid; 756 u8 port_vlan_flags; 757 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 758 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 759 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 760 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 761 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 762 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 763 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 764 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 765 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 766 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 767 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 768 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 769 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 770 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 771 u8 pvlan_reserved[3]; 772 /* ingress egress up sections */ 773 __le32 ingress_table; /* bitmap, 3 bits per up */ 774 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 775 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 776 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 777 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 778 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 779 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 780 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 781 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 782 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 783 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 784 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 785 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 786 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 787 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 788 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 789 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 790 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 791 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 792 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 793 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 794 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 795 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 796 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 797 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 798 __le32 egress_table; /* same defines as for ingress table */ 799 /* cascaded PV section */ 800 __le16 cas_pv_tag; 801 u8 cas_pv_flags; 802 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 803 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 804 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 805 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 806 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 807 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 808 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 809 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 810 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 811 u8 cas_pv_reserved; 812 /* queue mapping section */ 813 __le16 mapping_flags; 814 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 815 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 816 __le16 queue_mapping[16]; 817 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 818 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 819 __le16 tc_mapping[8]; 820 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 821 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 822 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 823 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 824 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 825 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 826 /* queueing option section */ 827 u8 queueing_opt_flags; 828 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 829 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 830 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 831 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 832 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 833 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 834 u8 queueing_opt_reserved[3]; 835 /* scheduler section */ 836 u8 up_enable_bits; 837 u8 sched_reserved; 838 /* outer up section */ 839 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 840 u8 cmd_reserved[8]; 841 /* last 32 bytes are written by FW */ 842 __le16 qs_handle[8]; 843 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 844 __le16 stat_counter_idx; 845 __le16 sched_id; 846 u8 resp_reserved[12]; 847 }; 848 849 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 850 851 /* Add Port Virtualizer (direct 0x0220) 852 * also used for update PV (direct 0x0221) but only flags are used 853 * (IS_CTRL_PORT only works on add PV) 854 */ 855 struct i40e_aqc_add_update_pv { 856 __le16 command_flags; 857 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 858 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 859 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 860 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 861 __le16 uplink_seid; 862 __le16 connected_seid; 863 u8 reserved[10]; 864 }; 865 866 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 867 868 struct i40e_aqc_add_update_pv_completion { 869 /* reserved for update; for add also encodes error if rc == ENOSPC */ 870 __le16 pv_seid; 871 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 872 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 873 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 874 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 875 u8 reserved[14]; 876 }; 877 878 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 879 880 /* Get PV Params (direct 0x0222) 881 * uses i40e_aqc_switch_seid for the descriptor 882 */ 883 884 struct i40e_aqc_get_pv_params_completion { 885 __le16 seid; 886 __le16 default_stag; 887 __le16 pv_flags; /* same flags as add_pv */ 888 #define I40E_AQC_GET_PV_PV_TYPE 0x1 889 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 890 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 891 u8 reserved[8]; 892 __le16 default_port_seid; 893 }; 894 895 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 896 897 /* Add VEB (direct 0x0230) */ 898 struct i40e_aqc_add_veb { 899 __le16 uplink_seid; 900 __le16 downlink_seid; 901 __le16 veb_flags; 902 #define I40E_AQC_ADD_VEB_FLOATING 0x1 903 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 904 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 905 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 906 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 907 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 908 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 909 u8 enable_tcs; 910 u8 reserved[9]; 911 }; 912 913 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 914 915 struct i40e_aqc_add_veb_completion { 916 u8 reserved[6]; 917 __le16 switch_seid; 918 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 919 __le16 veb_seid; 920 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 921 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 922 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 923 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 924 __le16 statistic_index; 925 __le16 vebs_used; 926 __le16 vebs_free; 927 }; 928 929 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 930 931 /* Get VEB Parameters (direct 0x0232) 932 * uses i40e_aqc_switch_seid for the descriptor 933 */ 934 struct i40e_aqc_get_veb_parameters_completion { 935 __le16 seid; 936 __le16 switch_id; 937 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 938 __le16 statistic_index; 939 __le16 vebs_used; 940 __le16 vebs_free; 941 u8 reserved[4]; 942 }; 943 944 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 945 946 /* Delete Element (direct 0x0243) 947 * uses the generic i40e_aqc_switch_seid 948 */ 949 950 /* Add MAC-VLAN (indirect 0x0250) */ 951 952 /* used for the command for most vlan commands */ 953 struct i40e_aqc_macvlan { 954 __le16 num_addresses; 955 __le16 seid[3]; 956 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 957 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 958 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 959 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 960 __le32 addr_high; 961 __le32 addr_low; 962 }; 963 964 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 965 966 /* indirect data for command and response */ 967 struct i40e_aqc_add_macvlan_element_data { 968 u8 mac_addr[6]; 969 __le16 vlan_tag; 970 __le16 flags; 971 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 972 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 973 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 974 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 975 __le16 queue_number; 976 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 977 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 978 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 979 /* response section */ 980 u8 match_method; 981 #define I40E_AQC_MM_PERFECT_MATCH 0x01 982 #define I40E_AQC_MM_HASH_MATCH 0x02 983 #define I40E_AQC_MM_ERR_NO_RES 0xFF 984 u8 reserved1[3]; 985 }; 986 987 struct i40e_aqc_add_remove_macvlan_completion { 988 __le16 perfect_mac_used; 989 __le16 perfect_mac_free; 990 __le16 unicast_hash_free; 991 __le16 multicast_hash_free; 992 __le32 addr_high; 993 __le32 addr_low; 994 }; 995 996 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 997 998 /* Remove MAC-VLAN (indirect 0x0251) 999 * uses i40e_aqc_macvlan for the descriptor 1000 * data points to an array of num_addresses of elements 1001 */ 1002 1003 struct i40e_aqc_remove_macvlan_element_data { 1004 u8 mac_addr[6]; 1005 __le16 vlan_tag; 1006 u8 flags; 1007 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1008 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1009 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1010 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1011 u8 reserved[3]; 1012 /* reply section */ 1013 u8 error_code; 1014 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1015 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1016 u8 reply_reserved[3]; 1017 }; 1018 1019 /* Add VLAN (indirect 0x0252) 1020 * Remove VLAN (indirect 0x0253) 1021 * use the generic i40e_aqc_macvlan for the command 1022 */ 1023 struct i40e_aqc_add_remove_vlan_element_data { 1024 __le16 vlan_tag; 1025 u8 vlan_flags; 1026 /* flags for add VLAN */ 1027 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1028 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1029 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1030 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1031 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1032 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1033 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1034 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1035 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1036 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1037 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1038 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1039 /* flags for remove VLAN */ 1040 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1041 u8 reserved; 1042 u8 result; 1043 /* flags for add VLAN */ 1044 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1045 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1046 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1047 /* flags for remove VLAN */ 1048 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1049 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1050 u8 reserved1[3]; 1051 }; 1052 1053 struct i40e_aqc_add_remove_vlan_completion { 1054 u8 reserved[4]; 1055 __le16 vlans_used; 1056 __le16 vlans_free; 1057 __le32 addr_high; 1058 __le32 addr_low; 1059 }; 1060 1061 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1062 struct i40e_aqc_set_vsi_promiscuous_modes { 1063 __le16 promiscuous_flags; 1064 __le16 valid_flags; 1065 /* flags used for both fields above */ 1066 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1067 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1068 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1069 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1070 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1071 __le16 seid; 1072 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1073 __le16 vlan_tag; 1074 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1075 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1076 u8 reserved[8]; 1077 }; 1078 1079 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1080 1081 /* Add S/E-tag command (direct 0x0255) 1082 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1083 */ 1084 struct i40e_aqc_add_tag { 1085 __le16 flags; 1086 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1087 __le16 seid; 1088 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1089 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1090 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1091 __le16 tag; 1092 __le16 queue_number; 1093 u8 reserved[8]; 1094 }; 1095 1096 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1097 1098 struct i40e_aqc_add_remove_tag_completion { 1099 u8 reserved[12]; 1100 __le16 tags_used; 1101 __le16 tags_free; 1102 }; 1103 1104 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1105 1106 /* Remove S/E-tag command (direct 0x0256) 1107 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1108 */ 1109 struct i40e_aqc_remove_tag { 1110 __le16 seid; 1111 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1112 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1113 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1114 __le16 tag; 1115 u8 reserved[12]; 1116 }; 1117 1118 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1119 1120 /* Add multicast E-Tag (direct 0x0257) 1121 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1122 * and no external data 1123 */ 1124 struct i40e_aqc_add_remove_mcast_etag { 1125 __le16 pv_seid; 1126 __le16 etag; 1127 u8 num_unicast_etags; 1128 u8 reserved[3]; 1129 __le32 addr_high; /* address of array of 2-byte s-tags */ 1130 __le32 addr_low; 1131 }; 1132 1133 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1134 1135 struct i40e_aqc_add_remove_mcast_etag_completion { 1136 u8 reserved[4]; 1137 __le16 mcast_etags_used; 1138 __le16 mcast_etags_free; 1139 __le32 addr_high; 1140 __le32 addr_low; 1141 1142 }; 1143 1144 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1145 1146 /* Update S/E-Tag (direct 0x0259) */ 1147 struct i40e_aqc_update_tag { 1148 __le16 seid; 1149 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1150 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1151 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1152 __le16 old_tag; 1153 __le16 new_tag; 1154 u8 reserved[10]; 1155 }; 1156 1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1158 1159 struct i40e_aqc_update_tag_completion { 1160 u8 reserved[12]; 1161 __le16 tags_used; 1162 __le16 tags_free; 1163 }; 1164 1165 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1166 1167 /* Add Control Packet filter (direct 0x025A) 1168 * Remove Control Packet filter (direct 0x025B) 1169 * uses the i40e_aqc_add_oveb_cloud, 1170 * and the generic direct completion structure 1171 */ 1172 struct i40e_aqc_add_remove_control_packet_filter { 1173 u8 mac[6]; 1174 __le16 etype; 1175 __le16 flags; 1176 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1177 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1178 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1181 __le16 seid; 1182 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1183 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1184 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1185 __le16 queue; 1186 u8 reserved[2]; 1187 }; 1188 1189 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1190 1191 struct i40e_aqc_add_remove_control_packet_filter_completion { 1192 __le16 mac_etype_used; 1193 __le16 etype_used; 1194 __le16 mac_etype_free; 1195 __le16 etype_free; 1196 u8 reserved[8]; 1197 }; 1198 1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1200 1201 /* Add Cloud filters (indirect 0x025C) 1202 * Remove Cloud filters (indirect 0x025D) 1203 * uses the i40e_aqc_add_remove_cloud_filters, 1204 * and the generic indirect completion structure 1205 */ 1206 struct i40e_aqc_add_remove_cloud_filters { 1207 u8 num_filters; 1208 u8 reserved; 1209 __le16 seid; 1210 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1211 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1212 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1213 u8 reserved2[4]; 1214 __le32 addr_high; 1215 __le32 addr_low; 1216 }; 1217 1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1219 1220 struct i40e_aqc_add_remove_cloud_filters_element_data { 1221 u8 outer_mac[6]; 1222 u8 inner_mac[6]; 1223 __le16 inner_vlan; 1224 union { 1225 struct { 1226 u8 reserved[12]; 1227 u8 data[4]; 1228 } v4; 1229 struct { 1230 u8 data[16]; 1231 } v6; 1232 } ipaddr; 1233 __le16 flags; 1234 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1235 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1236 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1237 /* 0x0000 reserved */ 1238 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1239 /* 0x0002 reserved */ 1240 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1241 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1242 /* 0x0005 reserved */ 1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1244 /* 0x0007 reserved */ 1245 /* 0x0008 reserved */ 1246 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1247 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1248 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1249 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1250 1251 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1252 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1253 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1254 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1255 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1256 1257 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1258 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1259 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1263 1264 __le32 tenant_id; 1265 u8 reserved[4]; 1266 __le16 queue_number; 1267 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1268 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1269 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1270 u8 reserved2[14]; 1271 /* response section */ 1272 u8 allocation_result; 1273 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1274 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1275 u8 response_reserved[7]; 1276 }; 1277 1278 struct i40e_aqc_remove_cloud_filters_completion { 1279 __le16 perfect_ovlan_used; 1280 __le16 perfect_ovlan_free; 1281 __le16 vlan_used; 1282 __le16 vlan_free; 1283 __le32 addr_high; 1284 __le32 addr_low; 1285 }; 1286 1287 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1288 1289 /* Add Mirror Rule (indirect or direct 0x0260) 1290 * Delete Mirror Rule (indirect or direct 0x0261) 1291 * note: some rule types (4,5) do not use an external buffer. 1292 * take care to set the flags correctly. 1293 */ 1294 struct i40e_aqc_add_delete_mirror_rule { 1295 __le16 seid; 1296 __le16 rule_type; 1297 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1298 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1299 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1300 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1301 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1302 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1303 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1304 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1305 __le16 num_entries; 1306 __le16 destination; /* VSI for add, rule id for delete */ 1307 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1308 __le32 addr_low; 1309 }; 1310 1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1312 1313 struct i40e_aqc_add_delete_mirror_rule_completion { 1314 u8 reserved[2]; 1315 __le16 rule_id; /* only used on add */ 1316 __le16 mirror_rules_used; 1317 __le16 mirror_rules_free; 1318 __le32 addr_high; 1319 __le32 addr_low; 1320 }; 1321 1322 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1323 1324 /* DCB 0x03xx*/ 1325 1326 /* PFC Ignore (direct 0x0301) 1327 * the command and response use the same descriptor structure 1328 */ 1329 struct i40e_aqc_pfc_ignore { 1330 u8 tc_bitmap; 1331 u8 command_flags; /* unused on response */ 1332 #define I40E_AQC_PFC_IGNORE_SET 0x80 1333 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1334 u8 reserved[14]; 1335 }; 1336 1337 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1338 1339 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1340 * with no parameters 1341 */ 1342 1343 /* TX scheduler 0x04xx */ 1344 1345 /* Almost all the indirect commands use 1346 * this generic struct to pass the SEID in param0 1347 */ 1348 struct i40e_aqc_tx_sched_ind { 1349 __le16 vsi_seid; 1350 u8 reserved[6]; 1351 __le32 addr_high; 1352 __le32 addr_low; 1353 }; 1354 1355 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1356 1357 /* Several commands respond with a set of queue set handles */ 1358 struct i40e_aqc_qs_handles_resp { 1359 __le16 qs_handles[8]; 1360 }; 1361 1362 /* Configure VSI BW limits (direct 0x0400) */ 1363 struct i40e_aqc_configure_vsi_bw_limit { 1364 __le16 vsi_seid; 1365 u8 reserved[2]; 1366 __le16 credit; 1367 u8 reserved1[2]; 1368 u8 max_credit; /* 0-3, limit = 2^max */ 1369 u8 reserved2[7]; 1370 }; 1371 1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1373 1374 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1375 * responds with i40e_aqc_qs_handles_resp 1376 */ 1377 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1378 u8 tc_valid_bits; 1379 u8 reserved[15]; 1380 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1381 1382 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1383 __le16 tc_bw_max[2]; 1384 u8 reserved1[28]; 1385 }; 1386 1387 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1388 1389 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1390 * responds with i40e_aqc_qs_handles_resp 1391 */ 1392 struct i40e_aqc_configure_vsi_tc_bw_data { 1393 u8 tc_valid_bits; 1394 u8 reserved[3]; 1395 u8 tc_bw_credits[8]; 1396 u8 reserved1[4]; 1397 __le16 qs_handles[8]; 1398 }; 1399 1400 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1401 1402 /* Query vsi bw configuration (indirect 0x0408) */ 1403 struct i40e_aqc_query_vsi_bw_config_resp { 1404 u8 tc_valid_bits; 1405 u8 tc_suspended_bits; 1406 u8 reserved[14]; 1407 __le16 qs_handles[8]; 1408 u8 reserved1[4]; 1409 __le16 port_bw_limit; 1410 u8 reserved2[2]; 1411 u8 max_bw; /* 0-3, limit = 2^max */ 1412 u8 reserved3[23]; 1413 }; 1414 1415 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1416 1417 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1418 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1419 u8 tc_valid_bits; 1420 u8 reserved[3]; 1421 u8 share_credits[8]; 1422 __le16 credits[8]; 1423 1424 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1425 __le16 tc_bw_max[2]; 1426 }; 1427 1428 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1429 1430 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1431 struct i40e_aqc_configure_switching_comp_bw_limit { 1432 __le16 seid; 1433 u8 reserved[2]; 1434 __le16 credit; 1435 u8 reserved1[2]; 1436 u8 max_bw; /* 0-3, limit = 2^max */ 1437 u8 reserved2[7]; 1438 }; 1439 1440 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1441 1442 /* Enable Physical Port ETS (indirect 0x0413) 1443 * Modify Physical Port ETS (indirect 0x0414) 1444 * Disable Physical Port ETS (indirect 0x0415) 1445 */ 1446 struct i40e_aqc_configure_switching_comp_ets_data { 1447 u8 reserved[4]; 1448 u8 tc_valid_bits; 1449 u8 seepage; 1450 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1451 u8 tc_strict_priority_flags; 1452 u8 reserved1[17]; 1453 u8 tc_bw_share_credits[8]; 1454 u8 reserved2[96]; 1455 }; 1456 1457 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1458 1459 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1460 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1461 u8 tc_valid_bits; 1462 u8 reserved[15]; 1463 __le16 tc_bw_credit[8]; 1464 1465 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1466 __le16 tc_bw_max[2]; 1467 u8 reserved1[28]; 1468 }; 1469 1470 I40E_CHECK_STRUCT_LEN(0x40, 1471 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1472 1473 /* Configure Switching Component Bandwidth Allocation per Tc 1474 * (indirect 0x0417) 1475 */ 1476 struct i40e_aqc_configure_switching_comp_bw_config_data { 1477 u8 tc_valid_bits; 1478 u8 reserved[2]; 1479 u8 absolute_credits; /* bool */ 1480 u8 tc_bw_share_credits[8]; 1481 u8 reserved1[20]; 1482 }; 1483 1484 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1485 1486 /* Query Switching Component Configuration (indirect 0x0418) */ 1487 struct i40e_aqc_query_switching_comp_ets_config_resp { 1488 u8 tc_valid_bits; 1489 u8 reserved[35]; 1490 __le16 port_bw_limit; 1491 u8 reserved1[2]; 1492 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1493 u8 reserved2[23]; 1494 }; 1495 1496 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1497 1498 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1499 struct i40e_aqc_query_port_ets_config_resp { 1500 u8 reserved[4]; 1501 u8 tc_valid_bits; 1502 u8 reserved1; 1503 u8 tc_strict_priority_bits; 1504 u8 reserved2; 1505 u8 tc_bw_share_credits[8]; 1506 __le16 tc_bw_limits[8]; 1507 1508 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1509 __le16 tc_bw_max[2]; 1510 u8 reserved3[32]; 1511 }; 1512 1513 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1514 1515 /* Query Switching Component Bandwidth Allocation per Traffic Type 1516 * (indirect 0x041A) 1517 */ 1518 struct i40e_aqc_query_switching_comp_bw_config_resp { 1519 u8 tc_valid_bits; 1520 u8 reserved[2]; 1521 u8 absolute_credits_enable; /* bool */ 1522 u8 tc_bw_share_credits[8]; 1523 __le16 tc_bw_limits[8]; 1524 1525 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1526 __le16 tc_bw_max[2]; 1527 }; 1528 1529 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1530 1531 /* Suspend/resume port TX traffic 1532 * (direct 0x041B and 0x041C) uses the generic SEID struct 1533 */ 1534 1535 /* Configure partition BW 1536 * (indirect 0x041D) 1537 */ 1538 struct i40e_aqc_configure_partition_bw_data { 1539 __le16 pf_valid_bits; 1540 u8 min_bw[16]; /* guaranteed bandwidth */ 1541 u8 max_bw[16]; /* bandwidth limit */ 1542 }; 1543 1544 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1545 1546 /* Get and set the active HMC resource profile and status. 1547 * (direct 0x0500) and (direct 0x0501) 1548 */ 1549 struct i40e_aq_get_set_hmc_resource_profile { 1550 u8 pm_profile; 1551 u8 pe_vf_enabled; 1552 u8 reserved[14]; 1553 }; 1554 1555 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1556 1557 enum i40e_aq_hmc_profile { 1558 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1559 I40E_HMC_PROFILE_DEFAULT = 1, 1560 I40E_HMC_PROFILE_FAVOR_VF = 2, 1561 I40E_HMC_PROFILE_EQUAL = 3, 1562 }; 1563 1564 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1565 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1566 1567 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1568 1569 /* set in param0 for get phy abilities to report qualified modules */ 1570 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1571 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1572 1573 enum i40e_aq_phy_type { 1574 I40E_PHY_TYPE_SGMII = 0x0, 1575 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1576 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1577 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1578 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1579 I40E_PHY_TYPE_XAUI = 0x5, 1580 I40E_PHY_TYPE_XFI = 0x6, 1581 I40E_PHY_TYPE_SFI = 0x7, 1582 I40E_PHY_TYPE_XLAUI = 0x8, 1583 I40E_PHY_TYPE_XLPPI = 0x9, 1584 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1585 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1586 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1587 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1588 I40E_PHY_TYPE_100BASE_TX = 0x11, 1589 I40E_PHY_TYPE_1000BASE_T = 0x12, 1590 I40E_PHY_TYPE_10GBASE_T = 0x13, 1591 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1592 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1593 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1594 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1595 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1596 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1597 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1598 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1599 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1600 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1601 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1602 I40E_PHY_TYPE_MAX 1603 }; 1604 1605 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1606 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1607 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1608 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1609 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1610 1611 enum i40e_aq_link_speed { 1612 I40E_LINK_SPEED_UNKNOWN = 0, 1613 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1614 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1615 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1616 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1617 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1618 }; 1619 1620 struct i40e_aqc_module_desc { 1621 u8 oui[3]; 1622 u8 reserved1; 1623 u8 part_number[16]; 1624 u8 revision[4]; 1625 u8 reserved2[8]; 1626 }; 1627 1628 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1629 1630 struct i40e_aq_get_phy_abilities_resp { 1631 __le32 phy_type; /* bitmap using the above enum for offsets */ 1632 u8 link_speed; /* bitmap using the above enum bit patterns */ 1633 u8 abilities; 1634 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1635 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1636 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1637 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1638 #define I40E_AQ_PHY_AN_ENABLED 0x10 1639 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1640 __le16 eee_capability; 1641 #define I40E_AQ_EEE_100BASE_TX 0x0002 1642 #define I40E_AQ_EEE_1000BASE_T 0x0004 1643 #define I40E_AQ_EEE_10GBASE_T 0x0008 1644 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1645 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1646 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1647 __le32 eeer_val; 1648 u8 d3_lpan; 1649 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1650 u8 reserved[3]; 1651 u8 phy_id[4]; 1652 u8 module_type[3]; 1653 u8 qualified_module_count; 1654 #define I40E_AQ_PHY_MAX_QMS 16 1655 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1656 }; 1657 1658 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1659 1660 /* Set PHY Config (direct 0x0601) */ 1661 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1662 __le32 phy_type; 1663 u8 link_speed; 1664 u8 abilities; 1665 /* bits 0-2 use the values from get_phy_abilities_resp */ 1666 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1667 #define I40E_AQ_PHY_ENABLE_AN 0x10 1668 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1669 __le16 eee_capability; 1670 __le32 eeer; 1671 u8 low_power_ctrl; 1672 u8 reserved[3]; 1673 }; 1674 1675 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1676 1677 /* Set MAC Config command data structure (direct 0x0603) */ 1678 struct i40e_aq_set_mac_config { 1679 __le16 max_frame_size; 1680 u8 params; 1681 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1682 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1683 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1695 u8 tx_timer_priority; /* bitmap */ 1696 __le16 tx_timer_value; 1697 __le16 fc_refresh_threshold; 1698 u8 reserved[8]; 1699 }; 1700 1701 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1702 1703 /* Restart Auto-Negotiation (direct 0x605) */ 1704 struct i40e_aqc_set_link_restart_an { 1705 u8 command; 1706 #define I40E_AQ_PHY_RESTART_AN 0x02 1707 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1708 u8 reserved[15]; 1709 }; 1710 1711 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1712 1713 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1714 struct i40e_aqc_get_link_status { 1715 __le16 command_flags; /* only field set on command */ 1716 #define I40E_AQ_LSE_MASK 0x3 1717 #define I40E_AQ_LSE_NOP 0x0 1718 #define I40E_AQ_LSE_DISABLE 0x2 1719 #define I40E_AQ_LSE_ENABLE 0x3 1720 /* only response uses this flag */ 1721 #define I40E_AQ_LSE_IS_ENABLED 0x1 1722 u8 phy_type; /* i40e_aq_phy_type */ 1723 u8 link_speed; /* i40e_aq_link_speed */ 1724 u8 link_info; 1725 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1726 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1727 #define I40E_AQ_LINK_FAULT 0x02 1728 #define I40E_AQ_LINK_FAULT_TX 0x04 1729 #define I40E_AQ_LINK_FAULT_RX 0x08 1730 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1731 #define I40E_AQ_LINK_UP_PORT 0x20 1732 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1733 #define I40E_AQ_SIGNAL_DETECT 0x80 1734 u8 an_info; 1735 #define I40E_AQ_AN_COMPLETED 0x01 1736 #define I40E_AQ_LP_AN_ABILITY 0x02 1737 #define I40E_AQ_PD_FAULT 0x04 1738 #define I40E_AQ_FEC_EN 0x08 1739 #define I40E_AQ_PHY_LOW_POWER 0x10 1740 #define I40E_AQ_LINK_PAUSE_TX 0x20 1741 #define I40E_AQ_LINK_PAUSE_RX 0x40 1742 #define I40E_AQ_QUALIFIED_MODULE 0x80 1743 u8 ext_info; 1744 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1745 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1746 #define I40E_AQ_LINK_TX_SHIFT 0x02 1747 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1748 #define I40E_AQ_LINK_TX_ACTIVE 0x00 1749 #define I40E_AQ_LINK_TX_DRAINED 0x01 1750 #define I40E_AQ_LINK_TX_FLUSHED 0x03 1751 #define I40E_AQ_LINK_FORCED_40G 0x10 1752 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1753 __le16 max_frame_size; 1754 u8 config; 1755 #define I40E_AQ_CONFIG_CRC_ENA 0x04 1756 #define I40E_AQ_CONFIG_PACING_MASK 0x78 1757 u8 reserved[5]; 1758 }; 1759 1760 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1761 1762 /* Set event mask command (direct 0x613) */ 1763 struct i40e_aqc_set_phy_int_mask { 1764 u8 reserved[8]; 1765 __le16 event_mask; 1766 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1767 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 1768 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 1769 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1770 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1771 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1772 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1773 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1774 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1775 u8 reserved1[6]; 1776 }; 1777 1778 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1779 1780 /* Get Local AN advt register (direct 0x0614) 1781 * Set Local AN advt register (direct 0x0615) 1782 * Get Link Partner AN advt register (direct 0x0616) 1783 */ 1784 struct i40e_aqc_an_advt_reg { 1785 __le32 local_an_reg0; 1786 __le16 local_an_reg1; 1787 u8 reserved[10]; 1788 }; 1789 1790 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1791 1792 /* Set Loopback mode (0x0618) */ 1793 struct i40e_aqc_set_lb_mode { 1794 __le16 lb_mode; 1795 #define I40E_AQ_LB_PHY_LOCAL 0x01 1796 #define I40E_AQ_LB_PHY_REMOTE 0x02 1797 #define I40E_AQ_LB_MAC_LOCAL 0x04 1798 u8 reserved[14]; 1799 }; 1800 1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1802 1803 /* Set PHY Debug command (0x0622) */ 1804 struct i40e_aqc_set_phy_debug { 1805 u8 command_flags; 1806 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1809 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1810 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1811 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1812 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1813 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1814 u8 reserved[15]; 1815 }; 1816 1817 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1818 1819 enum i40e_aq_phy_reg_type { 1820 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1821 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1822 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1823 }; 1824 1825 /* NVM Read command (indirect 0x0701) 1826 * NVM Erase commands (direct 0x0702) 1827 * NVM Update commands (indirect 0x0703) 1828 */ 1829 struct i40e_aqc_nvm_update { 1830 u8 command_flags; 1831 #define I40E_AQ_NVM_LAST_CMD 0x01 1832 #define I40E_AQ_NVM_FLASH_ONLY 0x80 1833 u8 module_pointer; 1834 __le16 length; 1835 __le32 offset; 1836 __le32 addr_high; 1837 __le32 addr_low; 1838 }; 1839 1840 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1841 1842 /* NVM Config Read (indirect 0x0704) */ 1843 struct i40e_aqc_nvm_config_read { 1844 __le16 cmd_flags; 1845 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1846 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1847 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1848 __le16 element_count; 1849 __le16 element_id; /* Feature/field ID */ 1850 __le16 element_id_msw; /* MSWord of field ID */ 1851 __le32 address_high; 1852 __le32 address_low; 1853 }; 1854 1855 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1856 1857 /* NVM Config Write (indirect 0x0705) */ 1858 struct i40e_aqc_nvm_config_write { 1859 __le16 cmd_flags; 1860 __le16 element_count; 1861 u8 reserved[4]; 1862 __le32 address_high; 1863 __le32 address_low; 1864 }; 1865 1866 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1867 1868 /* Used for 0x0704 as well as for 0x0705 commands */ 1869 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1870 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1871 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1872 #define I40E_AQ_ANVM_FEATURE 0 1873 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1874 struct i40e_aqc_nvm_config_data_feature { 1875 __le16 feature_id; 1876 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1877 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1878 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1879 __le16 feature_options; 1880 __le16 feature_selection; 1881 }; 1882 1883 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1884 1885 struct i40e_aqc_nvm_config_data_immediate_field { 1886 __le32 field_id; 1887 __le32 field_value; 1888 __le16 field_options; 1889 __le16 reserved; 1890 }; 1891 1892 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1893 1894 /* Send to PF command (indirect 0x0801) id is only used by PF 1895 * Send to VF command (indirect 0x0802) id is only used by PF 1896 * Send to Peer PF command (indirect 0x0803) 1897 */ 1898 struct i40e_aqc_pf_vf_message { 1899 __le32 id; 1900 u8 reserved[4]; 1901 __le32 addr_high; 1902 __le32 addr_low; 1903 }; 1904 1905 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1906 1907 /* Alternate structure */ 1908 1909 /* Direct write (direct 0x0900) 1910 * Direct read (direct 0x0902) 1911 */ 1912 struct i40e_aqc_alternate_write { 1913 __le32 address0; 1914 __le32 data0; 1915 __le32 address1; 1916 __le32 data1; 1917 }; 1918 1919 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1920 1921 /* Indirect write (indirect 0x0901) 1922 * Indirect read (indirect 0x0903) 1923 */ 1924 1925 struct i40e_aqc_alternate_ind_write { 1926 __le32 address; 1927 __le32 length; 1928 __le32 addr_high; 1929 __le32 addr_low; 1930 }; 1931 1932 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1933 1934 /* Done alternate write (direct 0x0904) 1935 * uses i40e_aq_desc 1936 */ 1937 struct i40e_aqc_alternate_write_done { 1938 __le16 cmd_flags; 1939 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1940 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1941 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1942 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1943 u8 reserved[14]; 1944 }; 1945 1946 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1947 1948 /* Set OEM mode (direct 0x0905) */ 1949 struct i40e_aqc_alternate_set_mode { 1950 __le32 mode; 1951 #define I40E_AQ_ALTERNATE_MODE_NONE 0 1952 #define I40E_AQ_ALTERNATE_MODE_OEM 1 1953 u8 reserved[12]; 1954 }; 1955 1956 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1957 1958 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1959 1960 /* async events 0x10xx */ 1961 1962 /* Lan Queue Overflow Event (direct, 0x1001) */ 1963 struct i40e_aqc_lan_overflow { 1964 __le32 prtdcb_rupto; 1965 __le32 otx_ctl; 1966 u8 reserved[8]; 1967 }; 1968 1969 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1970 1971 /* Get LLDP MIB (indirect 0x0A00) */ 1972 struct i40e_aqc_lldp_get_mib { 1973 u8 type; 1974 u8 reserved1; 1975 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1976 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 1977 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 1978 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1979 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1980 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1981 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1982 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1983 #define I40E_AQ_LLDP_TX_SHIFT 0x4 1984 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1985 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 1986 __le16 local_len; 1987 __le16 remote_len; 1988 u8 reserved2[2]; 1989 __le32 addr_high; 1990 __le32 addr_low; 1991 }; 1992 1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1994 1995 /* Configure LLDP MIB Change Event (direct 0x0A01) 1996 * also used for the event (with type in the command field) 1997 */ 1998 struct i40e_aqc_lldp_update_mib { 1999 u8 command; 2000 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2001 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2002 u8 reserved[7]; 2003 __le32 addr_high; 2004 __le32 addr_low; 2005 }; 2006 2007 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2008 2009 /* Add LLDP TLV (indirect 0x0A02) 2010 * Delete LLDP TLV (indirect 0x0A04) 2011 */ 2012 struct i40e_aqc_lldp_add_tlv { 2013 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2014 u8 reserved1[1]; 2015 __le16 len; 2016 u8 reserved2[4]; 2017 __le32 addr_high; 2018 __le32 addr_low; 2019 }; 2020 2021 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2022 2023 /* Update LLDP TLV (indirect 0x0A03) */ 2024 struct i40e_aqc_lldp_update_tlv { 2025 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2026 u8 reserved; 2027 __le16 old_len; 2028 __le16 new_offset; 2029 __le16 new_len; 2030 __le32 addr_high; 2031 __le32 addr_low; 2032 }; 2033 2034 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2035 2036 /* Stop LLDP (direct 0x0A05) */ 2037 struct i40e_aqc_lldp_stop { 2038 u8 command; 2039 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2040 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2041 u8 reserved[15]; 2042 }; 2043 2044 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2045 2046 /* Start LLDP (direct 0x0A06) */ 2047 2048 struct i40e_aqc_lldp_start { 2049 u8 command; 2050 #define I40E_AQ_LLDP_AGENT_START 0x1 2051 u8 reserved[15]; 2052 }; 2053 2054 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2055 2056 /* Get CEE DCBX Oper Config (0x0A07) 2057 * uses the generic descriptor struct 2058 * returns below as indirect response 2059 */ 2060 2061 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2062 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2063 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2064 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2065 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2066 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2067 2068 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2069 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2070 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2071 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2072 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2073 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2074 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2075 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2076 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2077 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2078 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2079 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2080 2081 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2082 * word boundary layout issues, which the Linux compilers silently deal 2083 * with by adding padding, making the actual struct larger than designed. 2084 * However, the FW compiler for the NIC is less lenient and complains 2085 * about the struct. Hence, the struct defined here has an extra byte in 2086 * fields reserved3 and reserved4 to directly acknowledge that padding, 2087 * and the new length is used in the length check macro. 2088 */ 2089 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2090 u8 reserved1; 2091 u8 oper_num_tc; 2092 u8 oper_prio_tc[4]; 2093 u8 reserved2; 2094 u8 oper_tc_bw[8]; 2095 u8 oper_pfc_en; 2096 u8 reserved3[2]; 2097 __le16 oper_app_prio; 2098 u8 reserved4[2]; 2099 __le16 tlv_status; 2100 }; 2101 2102 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2103 2104 struct i40e_aqc_get_cee_dcb_cfg_resp { 2105 u8 oper_num_tc; 2106 u8 oper_prio_tc[4]; 2107 u8 oper_tc_bw[8]; 2108 u8 oper_pfc_en; 2109 __le16 oper_app_prio; 2110 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2111 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2112 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2113 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2114 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2115 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2116 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2117 __le32 tlv_status; 2118 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2119 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2120 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2121 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2122 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2123 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2124 u8 reserved[12]; 2125 }; 2126 2127 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2128 2129 /* Set Local LLDP MIB (indirect 0x0A08) 2130 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2131 */ 2132 struct i40e_aqc_lldp_set_local_mib { 2133 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2134 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2135 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2136 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2137 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2138 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2139 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2140 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2141 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2142 u8 type; 2143 u8 reserved0; 2144 __le16 length; 2145 u8 reserved1[4]; 2146 __le32 address_high; 2147 __le32 address_low; 2148 }; 2149 2150 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2151 2152 /* Stop/Start LLDP Agent (direct 0x0A09) 2153 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2154 */ 2155 struct i40e_aqc_lldp_stop_start_specific_agent { 2156 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2157 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2158 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2159 u8 command; 2160 u8 reserved[15]; 2161 }; 2162 2163 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2164 2165 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2166 struct i40e_aqc_add_udp_tunnel { 2167 __le16 udp_port; 2168 u8 reserved0[3]; 2169 u8 protocol_type; 2170 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2171 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2172 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2173 u8 reserved1[10]; 2174 }; 2175 2176 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2177 2178 struct i40e_aqc_add_udp_tunnel_completion { 2179 __le16 udp_port; 2180 u8 filter_entry_index; 2181 u8 multiple_pfs; 2182 #define I40E_AQC_SINGLE_PF 0x0 2183 #define I40E_AQC_MULTIPLE_PFS 0x1 2184 u8 total_filters; 2185 u8 reserved[11]; 2186 }; 2187 2188 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2189 2190 /* remove UDP Tunnel command (0x0B01) */ 2191 struct i40e_aqc_remove_udp_tunnel { 2192 u8 reserved[2]; 2193 u8 index; /* 0 to 15 */ 2194 u8 reserved2[13]; 2195 }; 2196 2197 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2198 2199 struct i40e_aqc_del_udp_tunnel_completion { 2200 __le16 udp_port; 2201 u8 index; /* 0 to 15 */ 2202 u8 multiple_pfs; 2203 u8 total_filters_used; 2204 u8 reserved1[11]; 2205 }; 2206 2207 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2208 2209 struct i40e_aqc_get_set_rss_key { 2210 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2211 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2212 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2213 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2214 __le16 vsi_id; 2215 u8 reserved[6]; 2216 __le32 addr_high; 2217 __le32 addr_low; 2218 }; 2219 2220 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2221 2222 struct i40e_aqc_get_set_rss_key_data { 2223 u8 standard_rss_key[0x28]; 2224 u8 extended_hash_key[0xc]; 2225 }; 2226 2227 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2228 2229 struct i40e_aqc_get_set_rss_lut { 2230 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2231 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2232 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2233 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2234 __le16 vsi_id; 2235 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2236 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2237 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2238 2239 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2240 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2241 __le16 flags; 2242 u8 reserved[4]; 2243 __le32 addr_high; 2244 __le32 addr_low; 2245 }; 2246 2247 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2248 2249 /* tunnel key structure 0x0B10 */ 2250 2251 struct i40e_aqc_tunnel_key_structure { 2252 u8 key1_off; 2253 u8 key2_off; 2254 u8 key1_len; /* 0 to 15 */ 2255 u8 key2_len; /* 0 to 15 */ 2256 u8 flags; 2257 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2258 /* response flags */ 2259 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2260 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2261 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2262 u8 network_key_index; 2263 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2264 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2265 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2266 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2267 u8 reserved[10]; 2268 }; 2269 2270 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2271 2272 /* OEM mode commands (direct 0xFE0x) */ 2273 struct i40e_aqc_oem_param_change { 2274 __le32 param_type; 2275 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2276 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2277 #define I40E_AQ_OEM_PARAM_MAC 2 2278 __le32 param_value1; 2279 __le16 param_value2; 2280 u8 reserved[6]; 2281 }; 2282 2283 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2284 2285 struct i40e_aqc_oem_state_change { 2286 __le32 state; 2287 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2288 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2289 u8 reserved[12]; 2290 }; 2291 2292 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2293 2294 /* Initialize OCSD (0xFE02, direct) */ 2295 struct i40e_aqc_opc_oem_ocsd_initialize { 2296 u8 type_status; 2297 u8 reserved1[3]; 2298 __le32 ocsd_memory_block_addr_high; 2299 __le32 ocsd_memory_block_addr_low; 2300 __le32 requested_update_interval; 2301 }; 2302 2303 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2304 2305 /* Initialize OCBB (0xFE03, direct) */ 2306 struct i40e_aqc_opc_oem_ocbb_initialize { 2307 u8 type_status; 2308 u8 reserved1[3]; 2309 __le32 ocbb_memory_block_addr_high; 2310 __le32 ocbb_memory_block_addr_low; 2311 u8 reserved2[4]; 2312 }; 2313 2314 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2315 2316 /* debug commands */ 2317 2318 /* get device id (0xFF00) uses the generic structure */ 2319 2320 /* set test more (0xFF01, internal) */ 2321 2322 struct i40e_acq_set_test_mode { 2323 u8 mode; 2324 #define I40E_AQ_TEST_PARTIAL 0 2325 #define I40E_AQ_TEST_FULL 1 2326 #define I40E_AQ_TEST_NVM 2 2327 u8 reserved[3]; 2328 u8 command; 2329 #define I40E_AQ_TEST_OPEN 0 2330 #define I40E_AQ_TEST_CLOSE 1 2331 #define I40E_AQ_TEST_INC 2 2332 u8 reserved2[3]; 2333 __le32 address_high; 2334 __le32 address_low; 2335 }; 2336 2337 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2338 2339 /* Debug Read Register command (0xFF03) 2340 * Debug Write Register command (0xFF04) 2341 */ 2342 struct i40e_aqc_debug_reg_read_write { 2343 __le32 reserved; 2344 __le32 address; 2345 __le32 value_high; 2346 __le32 value_low; 2347 }; 2348 2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2350 2351 /* Scatter/gather Reg Read (indirect 0xFF05) 2352 * Scatter/gather Reg Write (indirect 0xFF06) 2353 */ 2354 2355 /* i40e_aq_desc is used for the command */ 2356 struct i40e_aqc_debug_reg_sg_element_data { 2357 __le32 address; 2358 __le32 value; 2359 }; 2360 2361 /* Debug Modify register (direct 0xFF07) */ 2362 struct i40e_aqc_debug_modify_reg { 2363 __le32 address; 2364 __le32 value; 2365 __le32 clear_mask; 2366 __le32 set_mask; 2367 }; 2368 2369 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2370 2371 /* dump internal data (0xFF08, indirect) */ 2372 2373 #define I40E_AQ_CLUSTER_ID_AUX 0 2374 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2375 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2376 #define I40E_AQ_CLUSTER_ID_HMC 3 2377 #define I40E_AQ_CLUSTER_ID_MAC0 4 2378 #define I40E_AQ_CLUSTER_ID_MAC1 5 2379 #define I40E_AQ_CLUSTER_ID_MAC2 6 2380 #define I40E_AQ_CLUSTER_ID_MAC3 7 2381 #define I40E_AQ_CLUSTER_ID_DCB 8 2382 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2383 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2384 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2385 2386 struct i40e_aqc_debug_dump_internals { 2387 u8 cluster_id; 2388 u8 table_id; 2389 __le16 data_size; 2390 __le32 idx; 2391 __le32 address_high; 2392 __le32 address_low; 2393 }; 2394 2395 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2396 2397 struct i40e_aqc_debug_modify_internals { 2398 u8 cluster_id; 2399 u8 cluster_specific_params[7]; 2400 __le32 address_high; 2401 __le32 address_low; 2402 }; 2403 2404 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2405 2406 #endif 2407