1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2017 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_ADMINQ_CMD_H_ 28 #define _I40E_ADMINQ_CMD_H_ 29 30 /* This header file defines the i40e Admin Queue commands and is shared between 31 * i40e Firmware and Software. 32 * 33 * This file needs to comply with the Linux Kernel coding style. 34 */ 35 36 #define I40E_FW_API_VERSION_MAJOR 0x0001 37 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 38 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 39 40 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 41 I40E_FW_API_VERSION_MINOR_X710 : \ 42 I40E_FW_API_VERSION_MINOR_X722) 43 44 /* API version 1.7 implements additional link and PHY-specific APIs */ 45 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 46 47 struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69 }; 70 71 /* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76 /* command flags and offsets*/ 77 #define I40E_AQ_FLAG_DD_SHIFT 0 78 #define I40E_AQ_FLAG_CMP_SHIFT 1 79 #define I40E_AQ_FLAG_ERR_SHIFT 2 80 #define I40E_AQ_FLAG_VFE_SHIFT 3 81 #define I40E_AQ_FLAG_LB_SHIFT 9 82 #define I40E_AQ_FLAG_RD_SHIFT 10 83 #define I40E_AQ_FLAG_VFC_SHIFT 11 84 #define I40E_AQ_FLAG_BUF_SHIFT 12 85 #define I40E_AQ_FLAG_SI_SHIFT 13 86 #define I40E_AQ_FLAG_EI_SHIFT 14 87 #define I40E_AQ_FLAG_FE_SHIFT 15 88 89 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101 /* error codes */ 102 enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126 }; 127 128 /* Admin Queue command opcodes */ 129 enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 i40e_aqc_opc_set_switch_config = 0x0205, 165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167 168 i40e_aqc_opc_add_vsi = 0x0210, 169 i40e_aqc_opc_update_vsi_parameters = 0x0211, 170 i40e_aqc_opc_get_vsi_parameters = 0x0212, 171 172 i40e_aqc_opc_add_pv = 0x0220, 173 i40e_aqc_opc_update_pv_parameters = 0x0221, 174 i40e_aqc_opc_get_pv_parameters = 0x0222, 175 176 i40e_aqc_opc_add_veb = 0x0230, 177 i40e_aqc_opc_update_veb_parameters = 0x0231, 178 i40e_aqc_opc_get_veb_parameters = 0x0232, 179 180 i40e_aqc_opc_delete_element = 0x0243, 181 182 i40e_aqc_opc_add_macvlan = 0x0250, 183 i40e_aqc_opc_remove_macvlan = 0x0251, 184 i40e_aqc_opc_add_vlan = 0x0252, 185 i40e_aqc_opc_remove_vlan = 0x0253, 186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 187 i40e_aqc_opc_add_tag = 0x0255, 188 i40e_aqc_opc_remove_tag = 0x0256, 189 i40e_aqc_opc_add_multicast_etag = 0x0257, 190 i40e_aqc_opc_remove_multicast_etag = 0x0258, 191 i40e_aqc_opc_update_tag = 0x0259, 192 i40e_aqc_opc_add_control_packet_filter = 0x025A, 193 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 194 i40e_aqc_opc_add_cloud_filters = 0x025C, 195 i40e_aqc_opc_remove_cloud_filters = 0x025D, 196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 197 198 i40e_aqc_opc_add_mirror_rule = 0x0260, 199 i40e_aqc_opc_delete_mirror_rule = 0x0261, 200 201 /* Dynamic Device Personalization */ 202 i40e_aqc_opc_write_personalization_profile = 0x0270, 203 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 204 205 /* DCB commands */ 206 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 207 i40e_aqc_opc_dcb_updated = 0x0302, 208 i40e_aqc_opc_set_dcb_parameters = 0x0303, 209 210 /* TX scheduler */ 211 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 212 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 213 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 214 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 215 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 216 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 217 218 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 219 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 220 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 221 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 222 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 223 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 224 i40e_aqc_opc_query_port_ets_config = 0x0419, 225 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 226 i40e_aqc_opc_suspend_port_tx = 0x041B, 227 i40e_aqc_opc_resume_port_tx = 0x041C, 228 i40e_aqc_opc_configure_partition_bw = 0x041D, 229 /* hmc */ 230 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 231 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 232 233 /* phy commands*/ 234 i40e_aqc_opc_get_phy_abilities = 0x0600, 235 i40e_aqc_opc_set_phy_config = 0x0601, 236 i40e_aqc_opc_set_mac_config = 0x0603, 237 i40e_aqc_opc_set_link_restart_an = 0x0605, 238 i40e_aqc_opc_get_link_status = 0x0607, 239 i40e_aqc_opc_set_phy_int_mask = 0x0613, 240 i40e_aqc_opc_get_local_advt_reg = 0x0614, 241 i40e_aqc_opc_set_local_advt_reg = 0x0615, 242 i40e_aqc_opc_get_partner_advt = 0x0616, 243 i40e_aqc_opc_set_lb_modes = 0x0618, 244 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 245 i40e_aqc_opc_set_phy_debug = 0x0622, 246 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 247 i40e_aqc_opc_run_phy_activity = 0x0626, 248 i40e_aqc_opc_set_phy_register = 0x0628, 249 i40e_aqc_opc_get_phy_register = 0x0629, 250 251 /* NVM commands */ 252 i40e_aqc_opc_nvm_read = 0x0701, 253 i40e_aqc_opc_nvm_erase = 0x0702, 254 i40e_aqc_opc_nvm_update = 0x0703, 255 i40e_aqc_opc_nvm_config_read = 0x0704, 256 i40e_aqc_opc_nvm_config_write = 0x0705, 257 i40e_aqc_opc_oem_post_update = 0x0720, 258 i40e_aqc_opc_thermal_sensor = 0x0721, 259 260 /* virtualization commands */ 261 i40e_aqc_opc_send_msg_to_pf = 0x0801, 262 i40e_aqc_opc_send_msg_to_vf = 0x0802, 263 i40e_aqc_opc_send_msg_to_peer = 0x0803, 264 265 /* alternate structure */ 266 i40e_aqc_opc_alternate_write = 0x0900, 267 i40e_aqc_opc_alternate_write_indirect = 0x0901, 268 i40e_aqc_opc_alternate_read = 0x0902, 269 i40e_aqc_opc_alternate_read_indirect = 0x0903, 270 i40e_aqc_opc_alternate_write_done = 0x0904, 271 i40e_aqc_opc_alternate_set_mode = 0x0905, 272 i40e_aqc_opc_alternate_clear_port = 0x0906, 273 274 /* LLDP commands */ 275 i40e_aqc_opc_lldp_get_mib = 0x0A00, 276 i40e_aqc_opc_lldp_update_mib = 0x0A01, 277 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 278 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 279 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 280 i40e_aqc_opc_lldp_stop = 0x0A05, 281 i40e_aqc_opc_lldp_start = 0x0A06, 282 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 283 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 284 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 285 286 /* Tunnel commands */ 287 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 288 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 289 i40e_aqc_opc_set_rss_key = 0x0B02, 290 i40e_aqc_opc_set_rss_lut = 0x0B03, 291 i40e_aqc_opc_get_rss_key = 0x0B04, 292 i40e_aqc_opc_get_rss_lut = 0x0B05, 293 294 /* Async Events */ 295 i40e_aqc_opc_event_lan_overflow = 0x1001, 296 297 /* OEM commands */ 298 i40e_aqc_opc_oem_parameter_change = 0xFE00, 299 i40e_aqc_opc_oem_device_status_change = 0xFE01, 300 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 301 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 302 303 /* debug commands */ 304 i40e_aqc_opc_debug_read_reg = 0xFF03, 305 i40e_aqc_opc_debug_write_reg = 0xFF04, 306 i40e_aqc_opc_debug_modify_reg = 0xFF07, 307 i40e_aqc_opc_debug_dump_internals = 0xFF08, 308 }; 309 310 /* command structures and indirect data structures */ 311 312 /* Structure naming conventions: 313 * - no suffix for direct command descriptor structures 314 * - _data for indirect sent data 315 * - _resp for indirect return data (data which is both will use _data) 316 * - _completion for direct return data 317 * - _element_ for repeated elements (may also be _data or _resp) 318 * 319 * Command structures are expected to overlay the params.raw member of the basic 320 * descriptor, and as such cannot exceed 16 bytes in length. 321 */ 322 323 /* This macro is used to generate a compilation error if a structure 324 * is not exactly the correct length. It gives a divide by zero error if the 325 * structure is not of the correct size, otherwise it creates an enum that is 326 * never used. 327 */ 328 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 329 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 330 331 /* This macro is used extensively to ensure that command structures are 16 332 * bytes in length as they have to map to the raw array of that size. 333 */ 334 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 335 336 /* internal (0x00XX) commands */ 337 338 /* Get version (direct 0x0001) */ 339 struct i40e_aqc_get_version { 340 __le32 rom_ver; 341 __le32 fw_build; 342 __le16 fw_major; 343 __le16 fw_minor; 344 __le16 api_major; 345 __le16 api_minor; 346 }; 347 348 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 349 350 /* Send driver version (indirect 0x0002) */ 351 struct i40e_aqc_driver_version { 352 u8 driver_major_ver; 353 u8 driver_minor_ver; 354 u8 driver_build_ver; 355 u8 driver_subbuild_ver; 356 u8 reserved[4]; 357 __le32 address_high; 358 __le32 address_low; 359 }; 360 361 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 362 363 /* Queue Shutdown (direct 0x0003) */ 364 struct i40e_aqc_queue_shutdown { 365 __le32 driver_unloading; 366 #define I40E_AQ_DRIVER_UNLOADING 0x1 367 u8 reserved[12]; 368 }; 369 370 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 371 372 /* Set PF context (0x0004, direct) */ 373 struct i40e_aqc_set_pf_context { 374 u8 pf_id; 375 u8 reserved[15]; 376 }; 377 378 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 379 380 /* Request resource ownership (direct 0x0008) 381 * Release resource ownership (direct 0x0009) 382 */ 383 #define I40E_AQ_RESOURCE_NVM 1 384 #define I40E_AQ_RESOURCE_SDP 2 385 #define I40E_AQ_RESOURCE_ACCESS_READ 1 386 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 387 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 388 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 389 390 struct i40e_aqc_request_resource { 391 __le16 resource_id; 392 __le16 access_type; 393 __le32 timeout; 394 __le32 resource_number; 395 u8 reserved[4]; 396 }; 397 398 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 399 400 /* Get function capabilities (indirect 0x000A) 401 * Get device capabilities (indirect 0x000B) 402 */ 403 struct i40e_aqc_list_capabilites { 404 u8 command_flags; 405 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 406 u8 pf_index; 407 u8 reserved[2]; 408 __le32 count; 409 __le32 addr_high; 410 __le32 addr_low; 411 }; 412 413 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 414 415 struct i40e_aqc_list_capabilities_element_resp { 416 __le16 id; 417 u8 major_rev; 418 u8 minor_rev; 419 __le32 number; 420 __le32 logical_id; 421 __le32 phys_id; 422 u8 reserved[16]; 423 }; 424 425 /* list of caps */ 426 427 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 428 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 429 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 430 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 431 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 432 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 433 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 434 #define I40E_AQ_CAP_ID_SRIOV 0x0012 435 #define I40E_AQ_CAP_ID_VF 0x0013 436 #define I40E_AQ_CAP_ID_VMDQ 0x0014 437 #define I40E_AQ_CAP_ID_8021QBG 0x0015 438 #define I40E_AQ_CAP_ID_8021QBR 0x0016 439 #define I40E_AQ_CAP_ID_VSI 0x0017 440 #define I40E_AQ_CAP_ID_DCB 0x0018 441 #define I40E_AQ_CAP_ID_FCOE 0x0021 442 #define I40E_AQ_CAP_ID_ISCSI 0x0022 443 #define I40E_AQ_CAP_ID_RSS 0x0040 444 #define I40E_AQ_CAP_ID_RXQ 0x0041 445 #define I40E_AQ_CAP_ID_TXQ 0x0042 446 #define I40E_AQ_CAP_ID_MSIX 0x0043 447 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 448 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 449 #define I40E_AQ_CAP_ID_1588 0x0046 450 #define I40E_AQ_CAP_ID_IWARP 0x0051 451 #define I40E_AQ_CAP_ID_LED 0x0061 452 #define I40E_AQ_CAP_ID_SDP 0x0062 453 #define I40E_AQ_CAP_ID_MDIO 0x0063 454 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 455 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 456 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 457 #define I40E_AQ_CAP_ID_CEM 0x00F2 458 459 /* Set CPPM Configuration (direct 0x0103) */ 460 struct i40e_aqc_cppm_configuration { 461 __le16 command_flags; 462 #define I40E_AQ_CPPM_EN_LTRC 0x0800 463 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 464 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 465 #define I40E_AQ_CPPM_EN_HPTC 0x4000 466 #define I40E_AQ_CPPM_EN_DMARC 0x8000 467 __le16 ttlx; 468 __le32 dmacr; 469 __le16 dmcth; 470 u8 hptc; 471 u8 reserved; 472 __le32 pfltrc; 473 }; 474 475 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 476 477 /* Set ARP Proxy command / response (indirect 0x0104) */ 478 struct i40e_aqc_arp_proxy_data { 479 __le16 command_flags; 480 #define I40E_AQ_ARP_INIT_IPV4 0x0800 481 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 482 #define I40E_AQ_ARP_ENA 0x2000 483 #define I40E_AQ_ARP_ADD_IPV4 0x4000 484 #define I40E_AQ_ARP_DEL_IPV4 0x8000 485 __le16 table_id; 486 __le32 enabled_offloads; 487 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 488 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 489 __le32 ip_addr; 490 u8 mac_addr[6]; 491 u8 reserved[2]; 492 }; 493 494 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 495 496 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 497 struct i40e_aqc_ns_proxy_data { 498 __le16 table_idx_mac_addr_0; 499 __le16 table_idx_mac_addr_1; 500 __le16 table_idx_ipv6_0; 501 __le16 table_idx_ipv6_1; 502 __le16 control; 503 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 504 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 505 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 506 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 507 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 508 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 509 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 510 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 511 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 512 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 513 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 514 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 515 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 516 u8 mac_addr_0[6]; 517 u8 mac_addr_1[6]; 518 u8 local_mac_addr[6]; 519 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 520 u8 ipv6_addr_1[16]; 521 }; 522 523 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 524 525 /* Manage LAA Command (0x0106) - obsolete */ 526 struct i40e_aqc_mng_laa { 527 __le16 command_flags; 528 #define I40E_AQ_LAA_FLAG_WR 0x8000 529 u8 reserved[2]; 530 __le32 sal; 531 __le16 sah; 532 u8 reserved2[6]; 533 }; 534 535 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 536 537 /* Manage MAC Address Read Command (indirect 0x0107) */ 538 struct i40e_aqc_mac_address_read { 539 __le16 command_flags; 540 #define I40E_AQC_LAN_ADDR_VALID 0x10 541 #define I40E_AQC_SAN_ADDR_VALID 0x20 542 #define I40E_AQC_PORT_ADDR_VALID 0x40 543 #define I40E_AQC_WOL_ADDR_VALID 0x80 544 #define I40E_AQC_MC_MAG_EN_VALID 0x100 545 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 546 u8 reserved[6]; 547 __le32 addr_high; 548 __le32 addr_low; 549 }; 550 551 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 552 553 struct i40e_aqc_mac_address_read_data { 554 u8 pf_lan_mac[6]; 555 u8 pf_san_mac[6]; 556 u8 port_mac[6]; 557 u8 pf_wol_mac[6]; 558 }; 559 560 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 561 562 /* Manage MAC Address Write Command (0x0108) */ 563 struct i40e_aqc_mac_address_write { 564 __le16 command_flags; 565 #define I40E_AQC_MC_MAG_EN 0x0100 566 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 567 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 568 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 569 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 570 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 571 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 572 573 __le16 mac_sah; 574 __le32 mac_sal; 575 u8 reserved[8]; 576 }; 577 578 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 579 580 /* PXE commands (0x011x) */ 581 582 /* Clear PXE Command and response (direct 0x0110) */ 583 struct i40e_aqc_clear_pxe { 584 u8 rx_cnt; 585 u8 reserved[15]; 586 }; 587 588 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 589 590 /* Set WoL Filter (0x0120) */ 591 592 struct i40e_aqc_set_wol_filter { 593 __le16 filter_index; 594 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 595 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 596 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 597 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 598 599 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 600 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 601 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 602 __le16 cmd_flags; 603 #define I40E_AQC_SET_WOL_FILTER 0x8000 604 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 605 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 606 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 607 __le16 valid_flags; 608 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 609 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 610 u8 reserved[2]; 611 __le32 address_high; 612 __le32 address_low; 613 }; 614 615 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 616 617 struct i40e_aqc_set_wol_filter_data { 618 u8 filter[128]; 619 u8 mask[16]; 620 }; 621 622 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 623 624 /* Get Wake Reason (0x0121) */ 625 626 struct i40e_aqc_get_wake_reason_completion { 627 u8 reserved_1[2]; 628 __le16 wake_reason; 629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 630 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 631 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 632 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 633 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 634 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 635 u8 reserved_2[12]; 636 }; 637 638 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 639 640 /* Switch configuration commands (0x02xx) */ 641 642 /* Used by many indirect commands that only pass an seid and a buffer in the 643 * command 644 */ 645 struct i40e_aqc_switch_seid { 646 __le16 seid; 647 u8 reserved[6]; 648 __le32 addr_high; 649 __le32 addr_low; 650 }; 651 652 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 653 654 /* Get Switch Configuration command (indirect 0x0200) 655 * uses i40e_aqc_switch_seid for the descriptor 656 */ 657 struct i40e_aqc_get_switch_config_header_resp { 658 __le16 num_reported; 659 __le16 num_total; 660 u8 reserved[12]; 661 }; 662 663 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 664 665 struct i40e_aqc_switch_config_element_resp { 666 u8 element_type; 667 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 668 #define I40E_AQ_SW_ELEM_TYPE_PF 2 669 #define I40E_AQ_SW_ELEM_TYPE_VF 3 670 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 671 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 672 #define I40E_AQ_SW_ELEM_TYPE_PV 16 673 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 674 #define I40E_AQ_SW_ELEM_TYPE_PA 18 675 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 676 u8 revision; 677 #define I40E_AQ_SW_ELEM_REV_1 1 678 __le16 seid; 679 __le16 uplink_seid; 680 __le16 downlink_seid; 681 u8 reserved[3]; 682 u8 connection_type; 683 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 684 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 685 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 686 __le16 scheduler_id; 687 __le16 element_info; 688 }; 689 690 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 691 692 /* Get Switch Configuration (indirect 0x0200) 693 * an array of elements are returned in the response buffer 694 * the first in the array is the header, remainder are elements 695 */ 696 struct i40e_aqc_get_switch_config_resp { 697 struct i40e_aqc_get_switch_config_header_resp header; 698 struct i40e_aqc_switch_config_element_resp element[1]; 699 }; 700 701 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 702 703 /* Add Statistics (direct 0x0201) 704 * Remove Statistics (direct 0x0202) 705 */ 706 struct i40e_aqc_add_remove_statistics { 707 __le16 seid; 708 __le16 vlan; 709 __le16 stat_index; 710 u8 reserved[10]; 711 }; 712 713 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 714 715 /* Set Port Parameters command (direct 0x0203) */ 716 struct i40e_aqc_set_port_parameters { 717 __le16 command_flags; 718 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 719 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 720 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 721 __le16 bad_frame_vsi; 722 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 723 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 724 __le16 default_seid; /* reserved for command */ 725 u8 reserved[10]; 726 }; 727 728 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 729 730 /* Get Switch Resource Allocation (indirect 0x0204) */ 731 struct i40e_aqc_get_switch_resource_alloc { 732 u8 num_entries; /* reserved for command */ 733 u8 reserved[7]; 734 __le32 addr_high; 735 __le32 addr_low; 736 }; 737 738 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 739 740 /* expect an array of these structs in the response buffer */ 741 struct i40e_aqc_switch_resource_alloc_element_resp { 742 u8 resource_type; 743 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 744 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 745 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 746 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 747 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 748 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 749 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 750 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 751 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 752 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 753 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 754 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 755 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 756 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 757 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 758 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 759 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 760 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 761 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 762 u8 reserved1; 763 __le16 guaranteed; 764 __le16 total; 765 __le16 used; 766 __le16 total_unalloced; 767 u8 reserved2[6]; 768 }; 769 770 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 771 772 /* Set Switch Configuration (direct 0x0205) */ 773 struct i40e_aqc_set_switch_config { 774 __le16 flags; 775 /* flags used for both fields below */ 776 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 777 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 778 __le16 valid_flags; 779 /* The ethertype in switch_tag is dropped on ingress and used 780 * internally by the switch. Set this to zero for the default 781 * of 0x88a8 (802.1ad). Should be zero for firmware API 782 * versions lower than 1.7. 783 */ 784 __le16 switch_tag; 785 /* The ethertypes in first_tag and second_tag are used to 786 * match the outer and inner VLAN tags (respectively) when HW 787 * double VLAN tagging is enabled via the set port parameters 788 * AQ command. Otherwise these are both ignored. Set them to 789 * zero for their defaults of 0x8100 (802.1Q). Should be zero 790 * for firmware API versions lower than 1.7. 791 */ 792 __le16 first_tag; 793 __le16 second_tag; 794 /* Next byte is split into following: 795 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 796 * Bit 6 : 0 : Destination Port, 1: source port 797 * Bit 5..4 : L4 type 798 * 0: rsvd 799 * 1: TCP 800 * 2: UDP 801 * 3: Both TCP and UDP 802 * Bits 3:0 Mode 803 * 0: default mode 804 * 1: L4 port only mode 805 * 2: non-tunneled mode 806 * 3: tunneled mode 807 */ 808 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 809 810 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 811 812 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 813 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 814 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 815 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 816 817 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 818 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 819 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 820 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 821 u8 mode; 822 u8 rsvd5[5]; 823 }; 824 825 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 826 827 /* Read Receive control registers (direct 0x0206) 828 * Write Receive control registers (direct 0x0207) 829 * used for accessing Rx control registers that can be 830 * slow and need special handling when under high Rx load 831 */ 832 struct i40e_aqc_rx_ctl_reg_read_write { 833 __le32 reserved1; 834 __le32 address; 835 __le32 reserved2; 836 __le32 value; 837 }; 838 839 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 840 841 /* Add VSI (indirect 0x0210) 842 * this indirect command uses struct i40e_aqc_vsi_properties_data 843 * as the indirect buffer (128 bytes) 844 * 845 * Update VSI (indirect 0x211) 846 * uses the same data structure as Add VSI 847 * 848 * Get VSI (indirect 0x0212) 849 * uses the same completion and data structure as Add VSI 850 */ 851 struct i40e_aqc_add_get_update_vsi { 852 __le16 uplink_seid; 853 u8 connection_type; 854 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 855 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 856 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 857 u8 reserved1; 858 u8 vf_id; 859 u8 reserved2; 860 __le16 vsi_flags; 861 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 862 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 863 #define I40E_AQ_VSI_TYPE_VF 0x0 864 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 865 #define I40E_AQ_VSI_TYPE_PF 0x2 866 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 867 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 868 __le32 addr_high; 869 __le32 addr_low; 870 }; 871 872 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 873 874 struct i40e_aqc_add_get_update_vsi_completion { 875 __le16 seid; 876 __le16 vsi_number; 877 __le16 vsi_used; 878 __le16 vsi_free; 879 __le32 addr_high; 880 __le32 addr_low; 881 }; 882 883 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 884 885 struct i40e_aqc_vsi_properties_data { 886 /* first 96 byte are written by SW */ 887 __le16 valid_sections; 888 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 889 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 890 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 891 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 892 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 893 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 894 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 895 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 896 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 897 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 898 /* switch section */ 899 __le16 switch_id; /* 12bit id combined with flags below */ 900 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 901 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 902 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 903 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 904 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 905 u8 sw_reserved[2]; 906 /* security section */ 907 u8 sec_flags; 908 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 909 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 910 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 911 u8 sec_reserved; 912 /* VLAN section */ 913 __le16 pvid; /* VLANS include priority bits */ 914 __le16 fcoe_pvid; 915 u8 port_vlan_flags; 916 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 917 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 918 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 919 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 920 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 921 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 922 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 923 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 924 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 925 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 926 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 927 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 928 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 929 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 930 u8 pvlan_reserved[3]; 931 /* ingress egress up sections */ 932 __le32 ingress_table; /* bitmap, 3 bits per up */ 933 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 934 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 935 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 936 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 937 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 938 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 939 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 940 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 941 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 942 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 943 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 944 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 945 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 946 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 947 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 948 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 949 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 950 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 951 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 952 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 953 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 954 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 955 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 956 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 957 __le32 egress_table; /* same defines as for ingress table */ 958 /* cascaded PV section */ 959 __le16 cas_pv_tag; 960 u8 cas_pv_flags; 961 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 962 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 963 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 964 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 965 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 966 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 967 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 968 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 969 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 970 u8 cas_pv_reserved; 971 /* queue mapping section */ 972 __le16 mapping_flags; 973 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 974 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 975 __le16 queue_mapping[16]; 976 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 977 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 978 __le16 tc_mapping[8]; 979 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 980 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 981 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 982 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 983 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 984 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 985 /* queueing option section */ 986 u8 queueing_opt_flags; 987 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 988 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 989 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 990 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 991 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 992 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 993 u8 queueing_opt_reserved[3]; 994 /* scheduler section */ 995 u8 up_enable_bits; 996 u8 sched_reserved; 997 /* outer up section */ 998 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 999 u8 cmd_reserved[8]; 1000 /* last 32 bytes are written by FW */ 1001 __le16 qs_handle[8]; 1002 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1003 __le16 stat_counter_idx; 1004 __le16 sched_id; 1005 u8 resp_reserved[12]; 1006 }; 1007 1008 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1009 1010 /* Add Port Virtualizer (direct 0x0220) 1011 * also used for update PV (direct 0x0221) but only flags are used 1012 * (IS_CTRL_PORT only works on add PV) 1013 */ 1014 struct i40e_aqc_add_update_pv { 1015 __le16 command_flags; 1016 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1017 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1018 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1019 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1020 __le16 uplink_seid; 1021 __le16 connected_seid; 1022 u8 reserved[10]; 1023 }; 1024 1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1026 1027 struct i40e_aqc_add_update_pv_completion { 1028 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1029 __le16 pv_seid; 1030 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1031 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1032 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1033 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1034 u8 reserved[14]; 1035 }; 1036 1037 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1038 1039 /* Get PV Params (direct 0x0222) 1040 * uses i40e_aqc_switch_seid for the descriptor 1041 */ 1042 1043 struct i40e_aqc_get_pv_params_completion { 1044 __le16 seid; 1045 __le16 default_stag; 1046 __le16 pv_flags; /* same flags as add_pv */ 1047 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1048 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1049 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1050 u8 reserved[8]; 1051 __le16 default_port_seid; 1052 }; 1053 1054 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1055 1056 /* Add VEB (direct 0x0230) */ 1057 struct i40e_aqc_add_veb { 1058 __le16 uplink_seid; 1059 __le16 downlink_seid; 1060 __le16 veb_flags; 1061 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1062 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1063 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1064 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1065 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1066 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1067 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1068 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1069 u8 enable_tcs; 1070 u8 reserved[9]; 1071 }; 1072 1073 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1074 1075 struct i40e_aqc_add_veb_completion { 1076 u8 reserved[6]; 1077 __le16 switch_seid; 1078 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1079 __le16 veb_seid; 1080 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1081 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1082 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1083 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1084 __le16 statistic_index; 1085 __le16 vebs_used; 1086 __le16 vebs_free; 1087 }; 1088 1089 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1090 1091 /* Get VEB Parameters (direct 0x0232) 1092 * uses i40e_aqc_switch_seid for the descriptor 1093 */ 1094 struct i40e_aqc_get_veb_parameters_completion { 1095 __le16 seid; 1096 __le16 switch_id; 1097 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1098 __le16 statistic_index; 1099 __le16 vebs_used; 1100 __le16 vebs_free; 1101 u8 reserved[4]; 1102 }; 1103 1104 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1105 1106 /* Delete Element (direct 0x0243) 1107 * uses the generic i40e_aqc_switch_seid 1108 */ 1109 1110 /* Add MAC-VLAN (indirect 0x0250) */ 1111 1112 /* used for the command for most vlan commands */ 1113 struct i40e_aqc_macvlan { 1114 __le16 num_addresses; 1115 __le16 seid[3]; 1116 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1117 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1118 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1119 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1120 __le32 addr_high; 1121 __le32 addr_low; 1122 }; 1123 1124 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1125 1126 /* indirect data for command and response */ 1127 struct i40e_aqc_add_macvlan_element_data { 1128 u8 mac_addr[6]; 1129 __le16 vlan_tag; 1130 __le16 flags; 1131 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1132 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1133 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1134 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1135 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1136 __le16 queue_number; 1137 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1138 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1139 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1140 /* response section */ 1141 u8 match_method; 1142 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1143 #define I40E_AQC_MM_HASH_MATCH 0x02 1144 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1145 u8 reserved1[3]; 1146 }; 1147 1148 struct i40e_aqc_add_remove_macvlan_completion { 1149 __le16 perfect_mac_used; 1150 __le16 perfect_mac_free; 1151 __le16 unicast_hash_free; 1152 __le16 multicast_hash_free; 1153 __le32 addr_high; 1154 __le32 addr_low; 1155 }; 1156 1157 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1158 1159 /* Remove MAC-VLAN (indirect 0x0251) 1160 * uses i40e_aqc_macvlan for the descriptor 1161 * data points to an array of num_addresses of elements 1162 */ 1163 1164 struct i40e_aqc_remove_macvlan_element_data { 1165 u8 mac_addr[6]; 1166 __le16 vlan_tag; 1167 u8 flags; 1168 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1169 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1170 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1171 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1172 u8 reserved[3]; 1173 /* reply section */ 1174 u8 error_code; 1175 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1176 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1177 u8 reply_reserved[3]; 1178 }; 1179 1180 /* Add VLAN (indirect 0x0252) 1181 * Remove VLAN (indirect 0x0253) 1182 * use the generic i40e_aqc_macvlan for the command 1183 */ 1184 struct i40e_aqc_add_remove_vlan_element_data { 1185 __le16 vlan_tag; 1186 u8 vlan_flags; 1187 /* flags for add VLAN */ 1188 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1189 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1190 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1191 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1192 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1193 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1194 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1195 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1196 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1197 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1198 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1199 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1200 /* flags for remove VLAN */ 1201 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1202 u8 reserved; 1203 u8 result; 1204 /* flags for add VLAN */ 1205 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1206 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1207 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1208 /* flags for remove VLAN */ 1209 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1210 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1211 u8 reserved1[3]; 1212 }; 1213 1214 struct i40e_aqc_add_remove_vlan_completion { 1215 u8 reserved[4]; 1216 __le16 vlans_used; 1217 __le16 vlans_free; 1218 __le32 addr_high; 1219 __le32 addr_low; 1220 }; 1221 1222 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1223 struct i40e_aqc_set_vsi_promiscuous_modes { 1224 __le16 promiscuous_flags; 1225 __le16 valid_flags; 1226 /* flags used for both fields above */ 1227 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1228 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1229 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1230 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1231 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1232 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1233 __le16 seid; 1234 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1235 __le16 vlan_tag; 1236 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1237 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1238 u8 reserved[8]; 1239 }; 1240 1241 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1242 1243 /* Add S/E-tag command (direct 0x0255) 1244 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1245 */ 1246 struct i40e_aqc_add_tag { 1247 __le16 flags; 1248 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1249 __le16 seid; 1250 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1251 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1252 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1253 __le16 tag; 1254 __le16 queue_number; 1255 u8 reserved[8]; 1256 }; 1257 1258 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1259 1260 struct i40e_aqc_add_remove_tag_completion { 1261 u8 reserved[12]; 1262 __le16 tags_used; 1263 __le16 tags_free; 1264 }; 1265 1266 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1267 1268 /* Remove S/E-tag command (direct 0x0256) 1269 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1270 */ 1271 struct i40e_aqc_remove_tag { 1272 __le16 seid; 1273 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1274 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1275 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1276 __le16 tag; 1277 u8 reserved[12]; 1278 }; 1279 1280 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1281 1282 /* Add multicast E-Tag (direct 0x0257) 1283 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1284 * and no external data 1285 */ 1286 struct i40e_aqc_add_remove_mcast_etag { 1287 __le16 pv_seid; 1288 __le16 etag; 1289 u8 num_unicast_etags; 1290 u8 reserved[3]; 1291 __le32 addr_high; /* address of array of 2-byte s-tags */ 1292 __le32 addr_low; 1293 }; 1294 1295 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1296 1297 struct i40e_aqc_add_remove_mcast_etag_completion { 1298 u8 reserved[4]; 1299 __le16 mcast_etags_used; 1300 __le16 mcast_etags_free; 1301 __le32 addr_high; 1302 __le32 addr_low; 1303 1304 }; 1305 1306 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1307 1308 /* Update S/E-Tag (direct 0x0259) */ 1309 struct i40e_aqc_update_tag { 1310 __le16 seid; 1311 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1312 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1313 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1314 __le16 old_tag; 1315 __le16 new_tag; 1316 u8 reserved[10]; 1317 }; 1318 1319 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1320 1321 struct i40e_aqc_update_tag_completion { 1322 u8 reserved[12]; 1323 __le16 tags_used; 1324 __le16 tags_free; 1325 }; 1326 1327 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1328 1329 /* Add Control Packet filter (direct 0x025A) 1330 * Remove Control Packet filter (direct 0x025B) 1331 * uses the i40e_aqc_add_oveb_cloud, 1332 * and the generic direct completion structure 1333 */ 1334 struct i40e_aqc_add_remove_control_packet_filter { 1335 u8 mac[6]; 1336 __le16 etype; 1337 __le16 flags; 1338 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1339 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1340 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1341 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1342 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1343 __le16 seid; 1344 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1345 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1346 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1347 __le16 queue; 1348 u8 reserved[2]; 1349 }; 1350 1351 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1352 1353 struct i40e_aqc_add_remove_control_packet_filter_completion { 1354 __le16 mac_etype_used; 1355 __le16 etype_used; 1356 __le16 mac_etype_free; 1357 __le16 etype_free; 1358 u8 reserved[8]; 1359 }; 1360 1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1362 1363 /* Add Cloud filters (indirect 0x025C) 1364 * Remove Cloud filters (indirect 0x025D) 1365 * uses the i40e_aqc_add_remove_cloud_filters, 1366 * and the generic indirect completion structure 1367 */ 1368 struct i40e_aqc_add_remove_cloud_filters { 1369 u8 num_filters; 1370 u8 reserved; 1371 __le16 seid; 1372 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1373 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1374 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1375 u8 big_buffer_flag; 1376 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1377 u8 reserved2[3]; 1378 __le32 addr_high; 1379 __le32 addr_low; 1380 }; 1381 1382 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1383 1384 struct i40e_aqc_cloud_filters_element_data { 1385 u8 outer_mac[6]; 1386 u8 inner_mac[6]; 1387 __le16 inner_vlan; 1388 union { 1389 struct { 1390 u8 reserved[12]; 1391 u8 data[4]; 1392 } v4; 1393 struct { 1394 u8 data[16]; 1395 } v6; 1396 struct { 1397 __le16 data[8]; 1398 } raw_v6; 1399 } ipaddr; 1400 __le16 flags; 1401 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1402 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1403 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1404 /* 0x0000 reserved */ 1405 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1406 /* 0x0002 reserved */ 1407 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1408 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1409 /* 0x0005 reserved */ 1410 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1411 /* 0x0007 reserved */ 1412 /* 0x0008 reserved */ 1413 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1414 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1415 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1416 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1417 /* 0x0010 to 0x0017 is for custom filters */ 1418 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1420 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1421 1422 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1423 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1424 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1425 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1426 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1427 1428 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1435 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1436 1437 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1438 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1439 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1440 1441 __le32 tenant_id; 1442 u8 reserved[4]; 1443 __le16 queue_number; 1444 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1445 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1446 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1447 u8 reserved2[14]; 1448 /* response section */ 1449 u8 allocation_result; 1450 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1451 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1452 u8 response_reserved[7]; 1453 }; 1454 1455 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1456 1457 /* i40e_aqc_cloud_filters_element_bb is used when 1458 * I40E_AQC_CLOUD_CMD_BB flag is set. 1459 */ 1460 struct i40e_aqc_cloud_filters_element_bb { 1461 struct i40e_aqc_cloud_filters_element_data element; 1462 u16 general_fields[32]; 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1494 }; 1495 1496 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1497 1498 struct i40e_aqc_remove_cloud_filters_completion { 1499 __le16 perfect_ovlan_used; 1500 __le16 perfect_ovlan_free; 1501 __le16 vlan_used; 1502 __le16 vlan_free; 1503 __le32 addr_high; 1504 __le32 addr_low; 1505 }; 1506 1507 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1508 1509 /* Replace filter Command 0x025F 1510 * uses the i40e_aqc_replace_cloud_filters, 1511 * and the generic indirect completion structure 1512 */ 1513 struct i40e_filter_data { 1514 u8 filter_type; 1515 u8 input[3]; 1516 }; 1517 1518 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1519 1520 struct i40e_aqc_replace_cloud_filters_cmd { 1521 u8 valid_flags; 1522 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1523 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1524 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1525 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1526 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1527 u8 old_filter_type; 1528 u8 new_filter_type; 1529 u8 tr_bit; 1530 u8 reserved[4]; 1531 __le32 addr_high; 1532 __le32 addr_low; 1533 }; 1534 1535 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1536 1537 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1538 u8 data[32]; 1539 /* Filter type INPUT codes*/ 1540 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1541 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1542 1543 /* Field Vector offsets */ 1544 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1545 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1546 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1547 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1548 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1549 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1550 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1551 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1552 /* big FLU */ 1553 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1554 /* big FLU */ 1555 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1556 1557 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1558 struct i40e_filter_data filters[8]; 1559 }; 1560 1561 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1562 1563 /* Add Mirror Rule (indirect or direct 0x0260) 1564 * Delete Mirror Rule (indirect or direct 0x0261) 1565 * note: some rule types (4,5) do not use an external buffer. 1566 * take care to set the flags correctly. 1567 */ 1568 struct i40e_aqc_add_delete_mirror_rule { 1569 __le16 seid; 1570 __le16 rule_type; 1571 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1572 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1573 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1574 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1575 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1576 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1577 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1578 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1579 __le16 num_entries; 1580 __le16 destination; /* VSI for add, rule id for delete */ 1581 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1582 __le32 addr_low; 1583 }; 1584 1585 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1586 1587 struct i40e_aqc_add_delete_mirror_rule_completion { 1588 u8 reserved[2]; 1589 __le16 rule_id; /* only used on add */ 1590 __le16 mirror_rules_used; 1591 __le16 mirror_rules_free; 1592 __le32 addr_high; 1593 __le32 addr_low; 1594 }; 1595 1596 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1597 1598 /* Dynamic Device Personalization */ 1599 struct i40e_aqc_write_personalization_profile { 1600 u8 flags; 1601 u8 reserved[3]; 1602 __le32 profile_track_id; 1603 __le32 addr_high; 1604 __le32 addr_low; 1605 }; 1606 1607 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1608 1609 struct i40e_aqc_write_ddp_resp { 1610 __le32 error_offset; 1611 __le32 error_info; 1612 __le32 addr_high; 1613 __le32 addr_low; 1614 }; 1615 1616 struct i40e_aqc_get_applied_profiles { 1617 u8 flags; 1618 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1619 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1620 u8 rsv[3]; 1621 __le32 reserved; 1622 __le32 addr_high; 1623 __le32 addr_low; 1624 }; 1625 1626 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1627 1628 /* DCB 0x03xx*/ 1629 1630 /* PFC Ignore (direct 0x0301) 1631 * the command and response use the same descriptor structure 1632 */ 1633 struct i40e_aqc_pfc_ignore { 1634 u8 tc_bitmap; 1635 u8 command_flags; /* unused on response */ 1636 #define I40E_AQC_PFC_IGNORE_SET 0x80 1637 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1638 u8 reserved[14]; 1639 }; 1640 1641 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1642 1643 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1644 * with no parameters 1645 */ 1646 1647 /* TX scheduler 0x04xx */ 1648 1649 /* Almost all the indirect commands use 1650 * this generic struct to pass the SEID in param0 1651 */ 1652 struct i40e_aqc_tx_sched_ind { 1653 __le16 vsi_seid; 1654 u8 reserved[6]; 1655 __le32 addr_high; 1656 __le32 addr_low; 1657 }; 1658 1659 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1660 1661 /* Several commands respond with a set of queue set handles */ 1662 struct i40e_aqc_qs_handles_resp { 1663 __le16 qs_handles[8]; 1664 }; 1665 1666 /* Configure VSI BW limits (direct 0x0400) */ 1667 struct i40e_aqc_configure_vsi_bw_limit { 1668 __le16 vsi_seid; 1669 u8 reserved[2]; 1670 __le16 credit; 1671 u8 reserved1[2]; 1672 u8 max_credit; /* 0-3, limit = 2^max */ 1673 u8 reserved2[7]; 1674 }; 1675 1676 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1677 1678 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1679 * responds with i40e_aqc_qs_handles_resp 1680 */ 1681 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1682 u8 tc_valid_bits; 1683 u8 reserved[15]; 1684 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1685 1686 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1687 __le16 tc_bw_max[2]; 1688 u8 reserved1[28]; 1689 }; 1690 1691 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1692 1693 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1694 * responds with i40e_aqc_qs_handles_resp 1695 */ 1696 struct i40e_aqc_configure_vsi_tc_bw_data { 1697 u8 tc_valid_bits; 1698 u8 reserved[3]; 1699 u8 tc_bw_credits[8]; 1700 u8 reserved1[4]; 1701 __le16 qs_handles[8]; 1702 }; 1703 1704 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1705 1706 /* Query vsi bw configuration (indirect 0x0408) */ 1707 struct i40e_aqc_query_vsi_bw_config_resp { 1708 u8 tc_valid_bits; 1709 u8 tc_suspended_bits; 1710 u8 reserved[14]; 1711 __le16 qs_handles[8]; 1712 u8 reserved1[4]; 1713 __le16 port_bw_limit; 1714 u8 reserved2[2]; 1715 u8 max_bw; /* 0-3, limit = 2^max */ 1716 u8 reserved3[23]; 1717 }; 1718 1719 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1720 1721 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1722 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1723 u8 tc_valid_bits; 1724 u8 reserved[3]; 1725 u8 share_credits[8]; 1726 __le16 credits[8]; 1727 1728 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1729 __le16 tc_bw_max[2]; 1730 }; 1731 1732 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1733 1734 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1735 struct i40e_aqc_configure_switching_comp_bw_limit { 1736 __le16 seid; 1737 u8 reserved[2]; 1738 __le16 credit; 1739 u8 reserved1[2]; 1740 u8 max_bw; /* 0-3, limit = 2^max */ 1741 u8 reserved2[7]; 1742 }; 1743 1744 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1745 1746 /* Enable Physical Port ETS (indirect 0x0413) 1747 * Modify Physical Port ETS (indirect 0x0414) 1748 * Disable Physical Port ETS (indirect 0x0415) 1749 */ 1750 struct i40e_aqc_configure_switching_comp_ets_data { 1751 u8 reserved[4]; 1752 u8 tc_valid_bits; 1753 u8 seepage; 1754 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1755 u8 tc_strict_priority_flags; 1756 u8 reserved1[17]; 1757 u8 tc_bw_share_credits[8]; 1758 u8 reserved2[96]; 1759 }; 1760 1761 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1762 1763 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1764 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1765 u8 tc_valid_bits; 1766 u8 reserved[15]; 1767 __le16 tc_bw_credit[8]; 1768 1769 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1770 __le16 tc_bw_max[2]; 1771 u8 reserved1[28]; 1772 }; 1773 1774 I40E_CHECK_STRUCT_LEN(0x40, 1775 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1776 1777 /* Configure Switching Component Bandwidth Allocation per Tc 1778 * (indirect 0x0417) 1779 */ 1780 struct i40e_aqc_configure_switching_comp_bw_config_data { 1781 u8 tc_valid_bits; 1782 u8 reserved[2]; 1783 u8 absolute_credits; /* bool */ 1784 u8 tc_bw_share_credits[8]; 1785 u8 reserved1[20]; 1786 }; 1787 1788 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1789 1790 /* Query Switching Component Configuration (indirect 0x0418) */ 1791 struct i40e_aqc_query_switching_comp_ets_config_resp { 1792 u8 tc_valid_bits; 1793 u8 reserved[35]; 1794 __le16 port_bw_limit; 1795 u8 reserved1[2]; 1796 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1797 u8 reserved2[23]; 1798 }; 1799 1800 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1801 1802 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1803 struct i40e_aqc_query_port_ets_config_resp { 1804 u8 reserved[4]; 1805 u8 tc_valid_bits; 1806 u8 reserved1; 1807 u8 tc_strict_priority_bits; 1808 u8 reserved2; 1809 u8 tc_bw_share_credits[8]; 1810 __le16 tc_bw_limits[8]; 1811 1812 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1813 __le16 tc_bw_max[2]; 1814 u8 reserved3[32]; 1815 }; 1816 1817 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1818 1819 /* Query Switching Component Bandwidth Allocation per Traffic Type 1820 * (indirect 0x041A) 1821 */ 1822 struct i40e_aqc_query_switching_comp_bw_config_resp { 1823 u8 tc_valid_bits; 1824 u8 reserved[2]; 1825 u8 absolute_credits_enable; /* bool */ 1826 u8 tc_bw_share_credits[8]; 1827 __le16 tc_bw_limits[8]; 1828 1829 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1830 __le16 tc_bw_max[2]; 1831 }; 1832 1833 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1834 1835 /* Suspend/resume port TX traffic 1836 * (direct 0x041B and 0x041C) uses the generic SEID struct 1837 */ 1838 1839 /* Configure partition BW 1840 * (indirect 0x041D) 1841 */ 1842 struct i40e_aqc_configure_partition_bw_data { 1843 __le16 pf_valid_bits; 1844 u8 min_bw[16]; /* guaranteed bandwidth */ 1845 u8 max_bw[16]; /* bandwidth limit */ 1846 }; 1847 1848 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1849 1850 /* Get and set the active HMC resource profile and status. 1851 * (direct 0x0500) and (direct 0x0501) 1852 */ 1853 struct i40e_aq_get_set_hmc_resource_profile { 1854 u8 pm_profile; 1855 u8 pe_vf_enabled; 1856 u8 reserved[14]; 1857 }; 1858 1859 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1860 1861 enum i40e_aq_hmc_profile { 1862 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1863 I40E_HMC_PROFILE_DEFAULT = 1, 1864 I40E_HMC_PROFILE_FAVOR_VF = 2, 1865 I40E_HMC_PROFILE_EQUAL = 3, 1866 }; 1867 1868 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1869 1870 /* set in param0 for get phy abilities to report qualified modules */ 1871 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1872 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1873 1874 enum i40e_aq_phy_type { 1875 I40E_PHY_TYPE_SGMII = 0x0, 1876 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1877 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1878 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1879 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1880 I40E_PHY_TYPE_XAUI = 0x5, 1881 I40E_PHY_TYPE_XFI = 0x6, 1882 I40E_PHY_TYPE_SFI = 0x7, 1883 I40E_PHY_TYPE_XLAUI = 0x8, 1884 I40E_PHY_TYPE_XLPPI = 0x9, 1885 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1886 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1887 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1888 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1889 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1890 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1891 I40E_PHY_TYPE_100BASE_TX = 0x11, 1892 I40E_PHY_TYPE_1000BASE_T = 0x12, 1893 I40E_PHY_TYPE_10GBASE_T = 0x13, 1894 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1895 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1896 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1897 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1898 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1899 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1900 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1901 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1902 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1903 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1904 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1905 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1906 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1907 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1908 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1909 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1910 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1911 I40E_PHY_TYPE_MAX, 1912 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1913 I40E_PHY_TYPE_EMPTY = 0xFE, 1914 I40E_PHY_TYPE_DEFAULT = 0xFF, 1915 }; 1916 1917 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1918 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1919 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1920 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1921 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1922 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1923 1924 enum i40e_aq_link_speed { 1925 I40E_LINK_SPEED_UNKNOWN = 0, 1926 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1927 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1928 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1929 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1930 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1931 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1932 }; 1933 1934 struct i40e_aqc_module_desc { 1935 u8 oui[3]; 1936 u8 reserved1; 1937 u8 part_number[16]; 1938 u8 revision[4]; 1939 u8 reserved2[8]; 1940 }; 1941 1942 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1943 1944 struct i40e_aq_get_phy_abilities_resp { 1945 __le32 phy_type; /* bitmap using the above enum for offsets */ 1946 u8 link_speed; /* bitmap using the above enum bit patterns */ 1947 u8 abilities; 1948 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1949 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1950 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1951 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1952 #define I40E_AQ_PHY_AN_ENABLED 0x10 1953 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1954 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1955 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1956 __le16 eee_capability; 1957 #define I40E_AQ_EEE_100BASE_TX 0x0002 1958 #define I40E_AQ_EEE_1000BASE_T 0x0004 1959 #define I40E_AQ_EEE_10GBASE_T 0x0008 1960 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1961 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1962 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1963 __le32 eeer_val; 1964 u8 d3_lpan; 1965 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1966 u8 phy_type_ext; 1967 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1968 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1969 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1970 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1971 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1972 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1973 u8 fec_cfg_curr_mod_ext_info; 1974 #define I40E_AQ_ENABLE_FEC_KR 0x01 1975 #define I40E_AQ_ENABLE_FEC_RS 0x02 1976 #define I40E_AQ_REQUEST_FEC_KR 0x04 1977 #define I40E_AQ_REQUEST_FEC_RS 0x08 1978 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1979 #define I40E_AQ_FEC 1980 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1981 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1982 1983 u8 ext_comp_code; 1984 u8 phy_id[4]; 1985 u8 module_type[3]; 1986 u8 qualified_module_count; 1987 #define I40E_AQ_PHY_MAX_QMS 16 1988 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1989 }; 1990 1991 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1992 1993 /* Set PHY Config (direct 0x0601) */ 1994 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1995 __le32 phy_type; 1996 u8 link_speed; 1997 u8 abilities; 1998 /* bits 0-2 use the values from get_phy_abilities_resp */ 1999 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2000 #define I40E_AQ_PHY_ENABLE_AN 0x10 2001 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2002 __le16 eee_capability; 2003 __le32 eeer; 2004 u8 low_power_ctrl; 2005 u8 phy_type_ext; 2006 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2007 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2008 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2009 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2010 u8 fec_config; 2011 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2012 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2013 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2014 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2015 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2016 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2017 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2018 u8 reserved; 2019 }; 2020 2021 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2022 2023 /* Set MAC Config command data structure (direct 0x0603) */ 2024 struct i40e_aq_set_mac_config { 2025 __le16 max_frame_size; 2026 u8 params; 2027 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2028 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2029 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2030 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2031 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2032 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2033 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2034 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2035 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2036 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2037 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2038 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2039 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2040 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2041 u8 tx_timer_priority; /* bitmap */ 2042 __le16 tx_timer_value; 2043 __le16 fc_refresh_threshold; 2044 u8 reserved[8]; 2045 }; 2046 2047 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2048 2049 /* Restart Auto-Negotiation (direct 0x605) */ 2050 struct i40e_aqc_set_link_restart_an { 2051 u8 command; 2052 #define I40E_AQ_PHY_RESTART_AN 0x02 2053 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2054 u8 reserved[15]; 2055 }; 2056 2057 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2058 2059 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2060 struct i40e_aqc_get_link_status { 2061 __le16 command_flags; /* only field set on command */ 2062 #define I40E_AQ_LSE_MASK 0x3 2063 #define I40E_AQ_LSE_NOP 0x0 2064 #define I40E_AQ_LSE_DISABLE 0x2 2065 #define I40E_AQ_LSE_ENABLE 0x3 2066 /* only response uses this flag */ 2067 #define I40E_AQ_LSE_IS_ENABLED 0x1 2068 u8 phy_type; /* i40e_aq_phy_type */ 2069 u8 link_speed; /* i40e_aq_link_speed */ 2070 u8 link_info; 2071 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2072 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2073 #define I40E_AQ_LINK_FAULT 0x02 2074 #define I40E_AQ_LINK_FAULT_TX 0x04 2075 #define I40E_AQ_LINK_FAULT_RX 0x08 2076 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2077 #define I40E_AQ_LINK_UP_PORT 0x20 2078 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2079 #define I40E_AQ_SIGNAL_DETECT 0x80 2080 u8 an_info; 2081 #define I40E_AQ_AN_COMPLETED 0x01 2082 #define I40E_AQ_LP_AN_ABILITY 0x02 2083 #define I40E_AQ_PD_FAULT 0x04 2084 #define I40E_AQ_FEC_EN 0x08 2085 #define I40E_AQ_PHY_LOW_POWER 0x10 2086 #define I40E_AQ_LINK_PAUSE_TX 0x20 2087 #define I40E_AQ_LINK_PAUSE_RX 0x40 2088 #define I40E_AQ_QUALIFIED_MODULE 0x80 2089 u8 ext_info; 2090 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2091 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2092 #define I40E_AQ_LINK_TX_SHIFT 0x02 2093 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2094 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2095 #define I40E_AQ_LINK_TX_DRAINED 0x01 2096 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2097 #define I40E_AQ_LINK_FORCED_40G 0x10 2098 /* 25G Error Codes */ 2099 #define I40E_AQ_25G_NO_ERR 0X00 2100 #define I40E_AQ_25G_NOT_PRESENT 0X01 2101 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2102 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2103 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2104 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2105 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2106 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2107 #define I40E_AQ_LOOPBACK_MASK 0x07 2108 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2109 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2110 __le16 max_frame_size; 2111 u8 config; 2112 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2113 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2114 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2115 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2116 union { 2117 struct { 2118 u8 power_desc; 2119 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2120 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2121 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2122 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2123 #define I40E_AQ_PWR_CLASS_MASK 0x03 2124 u8 reserved[4]; 2125 }; 2126 struct { 2127 u8 link_type[4]; 2128 u8 link_type_ext; 2129 }; 2130 }; 2131 }; 2132 2133 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2134 2135 /* Set event mask command (direct 0x613) */ 2136 struct i40e_aqc_set_phy_int_mask { 2137 u8 reserved[8]; 2138 __le16 event_mask; 2139 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2140 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2141 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2142 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2143 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2144 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2145 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2146 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2147 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2148 u8 reserved1[6]; 2149 }; 2150 2151 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2152 2153 /* Get Local AN advt register (direct 0x0614) 2154 * Set Local AN advt register (direct 0x0615) 2155 * Get Link Partner AN advt register (direct 0x0616) 2156 */ 2157 struct i40e_aqc_an_advt_reg { 2158 __le32 local_an_reg0; 2159 __le16 local_an_reg1; 2160 u8 reserved[10]; 2161 }; 2162 2163 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2164 2165 /* Set Loopback mode (0x0618) */ 2166 struct i40e_aqc_set_lb_mode { 2167 __le16 lb_mode; 2168 #define I40E_AQ_LB_PHY_LOCAL 0x01 2169 #define I40E_AQ_LB_PHY_REMOTE 0x02 2170 #define I40E_AQ_LB_MAC_LOCAL 0x04 2171 u8 reserved[14]; 2172 }; 2173 2174 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2175 2176 /* Set PHY Debug command (0x0622) */ 2177 struct i40e_aqc_set_phy_debug { 2178 u8 command_flags; 2179 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2180 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2181 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2182 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2183 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2184 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2185 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2186 /* Disable link manageability on a single port */ 2187 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2188 /* Disable link manageability on all ports */ 2189 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2190 u8 reserved[15]; 2191 }; 2192 2193 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2194 2195 enum i40e_aq_phy_reg_type { 2196 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2197 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2198 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2199 }; 2200 2201 /* Run PHY Activity (0x0626) */ 2202 struct i40e_aqc_run_phy_activity { 2203 __le16 activity_id; 2204 u8 flags; 2205 u8 reserved1; 2206 __le32 control; 2207 __le32 data; 2208 u8 reserved2[4]; 2209 }; 2210 2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2212 2213 /* Set PHY Register command (0x0628) */ 2214 /* Get PHY Register command (0x0629) */ 2215 struct i40e_aqc_phy_register_access { 2216 u8 phy_interface; 2217 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2218 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2219 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2220 u8 dev_address; 2221 u8 reserved1[2]; 2222 __le32 reg_address; 2223 __le32 reg_value; 2224 u8 reserved2[4]; 2225 }; 2226 2227 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2228 2229 /* NVM Read command (indirect 0x0701) 2230 * NVM Erase commands (direct 0x0702) 2231 * NVM Update commands (indirect 0x0703) 2232 */ 2233 struct i40e_aqc_nvm_update { 2234 u8 command_flags; 2235 #define I40E_AQ_NVM_LAST_CMD 0x01 2236 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2237 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2238 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2239 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2240 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2241 u8 module_pointer; 2242 __le16 length; 2243 __le32 offset; 2244 __le32 addr_high; 2245 __le32 addr_low; 2246 }; 2247 2248 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2249 2250 /* NVM Config Read (indirect 0x0704) */ 2251 struct i40e_aqc_nvm_config_read { 2252 __le16 cmd_flags; 2253 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2254 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2255 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2256 __le16 element_count; 2257 __le16 element_id; /* Feature/field ID */ 2258 __le16 element_id_msw; /* MSWord of field ID */ 2259 __le32 address_high; 2260 __le32 address_low; 2261 }; 2262 2263 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2264 2265 /* NVM Config Write (indirect 0x0705) */ 2266 struct i40e_aqc_nvm_config_write { 2267 __le16 cmd_flags; 2268 __le16 element_count; 2269 u8 reserved[4]; 2270 __le32 address_high; 2271 __le32 address_low; 2272 }; 2273 2274 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2275 2276 /* Used for 0x0704 as well as for 0x0705 commands */ 2277 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2278 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2279 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2280 #define I40E_AQ_ANVM_FEATURE 0 2281 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2282 struct i40e_aqc_nvm_config_data_feature { 2283 __le16 feature_id; 2284 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2285 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2286 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2287 __le16 feature_options; 2288 __le16 feature_selection; 2289 }; 2290 2291 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2292 2293 struct i40e_aqc_nvm_config_data_immediate_field { 2294 __le32 field_id; 2295 __le32 field_value; 2296 __le16 field_options; 2297 __le16 reserved; 2298 }; 2299 2300 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2301 2302 /* OEM Post Update (indirect 0x0720) 2303 * no command data struct used 2304 */ 2305 struct i40e_aqc_nvm_oem_post_update { 2306 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2307 u8 sel_data; 2308 u8 reserved[7]; 2309 }; 2310 2311 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2312 2313 struct i40e_aqc_nvm_oem_post_update_buffer { 2314 u8 str_len; 2315 u8 dev_addr; 2316 __le16 eeprom_addr; 2317 u8 data[36]; 2318 }; 2319 2320 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2321 2322 /* Thermal Sensor (indirect 0x0721) 2323 * read or set thermal sensor configs and values 2324 * takes a sensor and command specific data buffer, not detailed here 2325 */ 2326 struct i40e_aqc_thermal_sensor { 2327 u8 sensor_action; 2328 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2329 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2330 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2331 u8 reserved[7]; 2332 __le32 addr_high; 2333 __le32 addr_low; 2334 }; 2335 2336 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2337 2338 /* Send to PF command (indirect 0x0801) id is only used by PF 2339 * Send to VF command (indirect 0x0802) id is only used by PF 2340 * Send to Peer PF command (indirect 0x0803) 2341 */ 2342 struct i40e_aqc_pf_vf_message { 2343 __le32 id; 2344 u8 reserved[4]; 2345 __le32 addr_high; 2346 __le32 addr_low; 2347 }; 2348 2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2350 2351 /* Alternate structure */ 2352 2353 /* Direct write (direct 0x0900) 2354 * Direct read (direct 0x0902) 2355 */ 2356 struct i40e_aqc_alternate_write { 2357 __le32 address0; 2358 __le32 data0; 2359 __le32 address1; 2360 __le32 data1; 2361 }; 2362 2363 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2364 2365 /* Indirect write (indirect 0x0901) 2366 * Indirect read (indirect 0x0903) 2367 */ 2368 2369 struct i40e_aqc_alternate_ind_write { 2370 __le32 address; 2371 __le32 length; 2372 __le32 addr_high; 2373 __le32 addr_low; 2374 }; 2375 2376 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2377 2378 /* Done alternate write (direct 0x0904) 2379 * uses i40e_aq_desc 2380 */ 2381 struct i40e_aqc_alternate_write_done { 2382 __le16 cmd_flags; 2383 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2384 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2385 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2386 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2387 u8 reserved[14]; 2388 }; 2389 2390 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2391 2392 /* Set OEM mode (direct 0x0905) */ 2393 struct i40e_aqc_alternate_set_mode { 2394 __le32 mode; 2395 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2396 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2397 u8 reserved[12]; 2398 }; 2399 2400 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2401 2402 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2403 2404 /* async events 0x10xx */ 2405 2406 /* Lan Queue Overflow Event (direct, 0x1001) */ 2407 struct i40e_aqc_lan_overflow { 2408 __le32 prtdcb_rupto; 2409 __le32 otx_ctl; 2410 u8 reserved[8]; 2411 }; 2412 2413 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2414 2415 /* Get LLDP MIB (indirect 0x0A00) */ 2416 struct i40e_aqc_lldp_get_mib { 2417 u8 type; 2418 u8 reserved1; 2419 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2420 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2421 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2422 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2423 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2424 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2425 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2426 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2427 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2428 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2429 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2430 __le16 local_len; 2431 __le16 remote_len; 2432 u8 reserved2[2]; 2433 __le32 addr_high; 2434 __le32 addr_low; 2435 }; 2436 2437 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2438 2439 /* Configure LLDP MIB Change Event (direct 0x0A01) 2440 * also used for the event (with type in the command field) 2441 */ 2442 struct i40e_aqc_lldp_update_mib { 2443 u8 command; 2444 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2445 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2446 u8 reserved[7]; 2447 __le32 addr_high; 2448 __le32 addr_low; 2449 }; 2450 2451 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2452 2453 /* Add LLDP TLV (indirect 0x0A02) 2454 * Delete LLDP TLV (indirect 0x0A04) 2455 */ 2456 struct i40e_aqc_lldp_add_tlv { 2457 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2458 u8 reserved1[1]; 2459 __le16 len; 2460 u8 reserved2[4]; 2461 __le32 addr_high; 2462 __le32 addr_low; 2463 }; 2464 2465 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2466 2467 /* Update LLDP TLV (indirect 0x0A03) */ 2468 struct i40e_aqc_lldp_update_tlv { 2469 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2470 u8 reserved; 2471 __le16 old_len; 2472 __le16 new_offset; 2473 __le16 new_len; 2474 __le32 addr_high; 2475 __le32 addr_low; 2476 }; 2477 2478 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2479 2480 /* Stop LLDP (direct 0x0A05) */ 2481 struct i40e_aqc_lldp_stop { 2482 u8 command; 2483 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2484 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2485 u8 reserved[15]; 2486 }; 2487 2488 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2489 2490 /* Start LLDP (direct 0x0A06) */ 2491 2492 struct i40e_aqc_lldp_start { 2493 u8 command; 2494 #define I40E_AQ_LLDP_AGENT_START 0x1 2495 u8 reserved[15]; 2496 }; 2497 2498 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2499 2500 /* Set DCB (direct 0x0303) */ 2501 struct i40e_aqc_set_dcb_parameters { 2502 u8 command; 2503 #define I40E_AQ_DCB_SET_AGENT 0x1 2504 #define I40E_DCB_VALID 0x1 2505 u8 valid_flags; 2506 u8 reserved[14]; 2507 }; 2508 2509 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2510 2511 /* Get CEE DCBX Oper Config (0x0A07) 2512 * uses the generic descriptor struct 2513 * returns below as indirect response 2514 */ 2515 2516 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2517 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2518 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2519 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2520 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2521 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2522 2523 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2524 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2525 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2526 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2527 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2528 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2529 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2530 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2531 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2532 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2533 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2534 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2535 2536 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2537 * word boundary layout issues, which the Linux compilers silently deal 2538 * with by adding padding, making the actual struct larger than designed. 2539 * However, the FW compiler for the NIC is less lenient and complains 2540 * about the struct. Hence, the struct defined here has an extra byte in 2541 * fields reserved3 and reserved4 to directly acknowledge that padding, 2542 * and the new length is used in the length check macro. 2543 */ 2544 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2545 u8 reserved1; 2546 u8 oper_num_tc; 2547 u8 oper_prio_tc[4]; 2548 u8 reserved2; 2549 u8 oper_tc_bw[8]; 2550 u8 oper_pfc_en; 2551 u8 reserved3[2]; 2552 __le16 oper_app_prio; 2553 u8 reserved4[2]; 2554 __le16 tlv_status; 2555 }; 2556 2557 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2558 2559 struct i40e_aqc_get_cee_dcb_cfg_resp { 2560 u8 oper_num_tc; 2561 u8 oper_prio_tc[4]; 2562 u8 oper_tc_bw[8]; 2563 u8 oper_pfc_en; 2564 __le16 oper_app_prio; 2565 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2566 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2567 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2568 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2569 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2570 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2571 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2572 __le32 tlv_status; 2573 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2574 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2575 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2576 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2577 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2578 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2579 u8 reserved[12]; 2580 }; 2581 2582 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2583 2584 /* Set Local LLDP MIB (indirect 0x0A08) 2585 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2586 */ 2587 struct i40e_aqc_lldp_set_local_mib { 2588 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2589 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2590 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2591 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2592 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2593 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2594 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2595 u8 type; 2596 u8 reserved0; 2597 __le16 length; 2598 u8 reserved1[4]; 2599 __le32 address_high; 2600 __le32 address_low; 2601 }; 2602 2603 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2604 2605 /* Stop/Start LLDP Agent (direct 0x0A09) 2606 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2607 */ 2608 struct i40e_aqc_lldp_stop_start_specific_agent { 2609 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2610 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2611 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2612 u8 command; 2613 u8 reserved[15]; 2614 }; 2615 2616 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2617 2618 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2619 struct i40e_aqc_add_udp_tunnel { 2620 __le16 udp_port; 2621 u8 reserved0[3]; 2622 u8 protocol_type; 2623 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2624 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2625 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2626 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2627 u8 reserved1[10]; 2628 }; 2629 2630 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2631 2632 struct i40e_aqc_add_udp_tunnel_completion { 2633 __le16 udp_port; 2634 u8 filter_entry_index; 2635 u8 multiple_pfs; 2636 #define I40E_AQC_SINGLE_PF 0x0 2637 #define I40E_AQC_MULTIPLE_PFS 0x1 2638 u8 total_filters; 2639 u8 reserved[11]; 2640 }; 2641 2642 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2643 2644 /* remove UDP Tunnel command (0x0B01) */ 2645 struct i40e_aqc_remove_udp_tunnel { 2646 u8 reserved[2]; 2647 u8 index; /* 0 to 15 */ 2648 u8 reserved2[13]; 2649 }; 2650 2651 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2652 2653 struct i40e_aqc_del_udp_tunnel_completion { 2654 __le16 udp_port; 2655 u8 index; /* 0 to 15 */ 2656 u8 multiple_pfs; 2657 u8 total_filters_used; 2658 u8 reserved1[11]; 2659 }; 2660 2661 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2662 2663 struct i40e_aqc_get_set_rss_key { 2664 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2665 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2666 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2667 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2668 __le16 vsi_id; 2669 u8 reserved[6]; 2670 __le32 addr_high; 2671 __le32 addr_low; 2672 }; 2673 2674 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2675 2676 struct i40e_aqc_get_set_rss_key_data { 2677 u8 standard_rss_key[0x28]; 2678 u8 extended_hash_key[0xc]; 2679 }; 2680 2681 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2682 2683 struct i40e_aqc_get_set_rss_lut { 2684 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2685 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2686 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2687 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2688 __le16 vsi_id; 2689 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2690 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2691 2692 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2693 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2694 __le16 flags; 2695 u8 reserved[4]; 2696 __le32 addr_high; 2697 __le32 addr_low; 2698 }; 2699 2700 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2701 2702 /* tunnel key structure 0x0B10 */ 2703 2704 struct i40e_aqc_tunnel_key_structure { 2705 u8 key1_off; 2706 u8 key2_off; 2707 u8 key1_len; /* 0 to 15 */ 2708 u8 key2_len; /* 0 to 15 */ 2709 u8 flags; 2710 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2711 /* response flags */ 2712 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2713 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2714 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2715 u8 network_key_index; 2716 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2717 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2718 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2719 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2720 u8 reserved[10]; 2721 }; 2722 2723 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2724 2725 /* OEM mode commands (direct 0xFE0x) */ 2726 struct i40e_aqc_oem_param_change { 2727 __le32 param_type; 2728 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2729 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2730 #define I40E_AQ_OEM_PARAM_MAC 2 2731 __le32 param_value1; 2732 __le16 param_value2; 2733 u8 reserved[6]; 2734 }; 2735 2736 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2737 2738 struct i40e_aqc_oem_state_change { 2739 __le32 state; 2740 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2741 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2742 u8 reserved[12]; 2743 }; 2744 2745 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2746 2747 /* Initialize OCSD (0xFE02, direct) */ 2748 struct i40e_aqc_opc_oem_ocsd_initialize { 2749 u8 type_status; 2750 u8 reserved1[3]; 2751 __le32 ocsd_memory_block_addr_high; 2752 __le32 ocsd_memory_block_addr_low; 2753 __le32 requested_update_interval; 2754 }; 2755 2756 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2757 2758 /* Initialize OCBB (0xFE03, direct) */ 2759 struct i40e_aqc_opc_oem_ocbb_initialize { 2760 u8 type_status; 2761 u8 reserved1[3]; 2762 __le32 ocbb_memory_block_addr_high; 2763 __le32 ocbb_memory_block_addr_low; 2764 u8 reserved2[4]; 2765 }; 2766 2767 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2768 2769 /* debug commands */ 2770 2771 /* get device id (0xFF00) uses the generic structure */ 2772 2773 /* set test more (0xFF01, internal) */ 2774 2775 struct i40e_acq_set_test_mode { 2776 u8 mode; 2777 #define I40E_AQ_TEST_PARTIAL 0 2778 #define I40E_AQ_TEST_FULL 1 2779 #define I40E_AQ_TEST_NVM 2 2780 u8 reserved[3]; 2781 u8 command; 2782 #define I40E_AQ_TEST_OPEN 0 2783 #define I40E_AQ_TEST_CLOSE 1 2784 #define I40E_AQ_TEST_INC 2 2785 u8 reserved2[3]; 2786 __le32 address_high; 2787 __le32 address_low; 2788 }; 2789 2790 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2791 2792 /* Debug Read Register command (0xFF03) 2793 * Debug Write Register command (0xFF04) 2794 */ 2795 struct i40e_aqc_debug_reg_read_write { 2796 __le32 reserved; 2797 __le32 address; 2798 __le32 value_high; 2799 __le32 value_low; 2800 }; 2801 2802 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2803 2804 /* Scatter/gather Reg Read (indirect 0xFF05) 2805 * Scatter/gather Reg Write (indirect 0xFF06) 2806 */ 2807 2808 /* i40e_aq_desc is used for the command */ 2809 struct i40e_aqc_debug_reg_sg_element_data { 2810 __le32 address; 2811 __le32 value; 2812 }; 2813 2814 /* Debug Modify register (direct 0xFF07) */ 2815 struct i40e_aqc_debug_modify_reg { 2816 __le32 address; 2817 __le32 value; 2818 __le32 clear_mask; 2819 __le32 set_mask; 2820 }; 2821 2822 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2823 2824 /* dump internal data (0xFF08, indirect) */ 2825 2826 #define I40E_AQ_CLUSTER_ID_AUX 0 2827 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2828 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2829 #define I40E_AQ_CLUSTER_ID_HMC 3 2830 #define I40E_AQ_CLUSTER_ID_MAC0 4 2831 #define I40E_AQ_CLUSTER_ID_MAC1 5 2832 #define I40E_AQ_CLUSTER_ID_MAC2 6 2833 #define I40E_AQ_CLUSTER_ID_MAC3 7 2834 #define I40E_AQ_CLUSTER_ID_DCB 8 2835 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2836 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2837 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2838 2839 struct i40e_aqc_debug_dump_internals { 2840 u8 cluster_id; 2841 u8 table_id; 2842 __le16 data_size; 2843 __le32 idx; 2844 __le32 address_high; 2845 __le32 address_low; 2846 }; 2847 2848 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2849 2850 struct i40e_aqc_debug_modify_internals { 2851 u8 cluster_id; 2852 u8 cluster_specific_params[7]; 2853 __le32 address_high; 2854 __le32 address_low; 2855 }; 2856 2857 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2858 2859 #endif /* _I40E_ADMINQ_CMD_H_ */ 2860