1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************* 3 * 4 * Intel Ethernet Controller XL710 Family Linux Driver 5 * Copyright(c) 2013 - 2017 Intel Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 * 22 * Contact Information: 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * 26 ******************************************************************************/ 27 28 #ifndef _I40E_ADMINQ_CMD_H_ 29 #define _I40E_ADMINQ_CMD_H_ 30 31 /* This header file defines the i40e Admin Queue commands and is shared between 32 * i40e Firmware and Software. 33 * 34 * This file needs to comply with the Linux Kernel coding style. 35 */ 36 37 #define I40E_FW_API_VERSION_MAJOR 0x0001 38 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 39 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 40 41 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 42 I40E_FW_API_VERSION_MINOR_X710 : \ 43 I40E_FW_API_VERSION_MINOR_X722) 44 45 /* API version 1.7 implements additional link and PHY-specific APIs */ 46 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 47 48 struct i40e_aq_desc { 49 __le16 flags; 50 __le16 opcode; 51 __le16 datalen; 52 __le16 retval; 53 __le32 cookie_high; 54 __le32 cookie_low; 55 union { 56 struct { 57 __le32 param0; 58 __le32 param1; 59 __le32 param2; 60 __le32 param3; 61 } internal; 62 struct { 63 __le32 param0; 64 __le32 param1; 65 __le32 addr_high; 66 __le32 addr_low; 67 } external; 68 u8 raw[16]; 69 } params; 70 }; 71 72 /* Flags sub-structure 73 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 74 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 75 */ 76 77 /* command flags and offsets*/ 78 #define I40E_AQ_FLAG_DD_SHIFT 0 79 #define I40E_AQ_FLAG_CMP_SHIFT 1 80 #define I40E_AQ_FLAG_ERR_SHIFT 2 81 #define I40E_AQ_FLAG_VFE_SHIFT 3 82 #define I40E_AQ_FLAG_LB_SHIFT 9 83 #define I40E_AQ_FLAG_RD_SHIFT 10 84 #define I40E_AQ_FLAG_VFC_SHIFT 11 85 #define I40E_AQ_FLAG_BUF_SHIFT 12 86 #define I40E_AQ_FLAG_SI_SHIFT 13 87 #define I40E_AQ_FLAG_EI_SHIFT 14 88 #define I40E_AQ_FLAG_FE_SHIFT 15 89 90 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 91 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 92 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 93 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 94 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 95 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 96 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 97 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 98 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 99 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 100 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 101 102 /* error codes */ 103 enum i40e_admin_queue_err { 104 I40E_AQ_RC_OK = 0, /* success */ 105 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 106 I40E_AQ_RC_ENOENT = 2, /* No such element */ 107 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 108 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 109 I40E_AQ_RC_EIO = 5, /* I/O error */ 110 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 111 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 112 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 113 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 114 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 115 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 116 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 117 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 118 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 119 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 120 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 121 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 122 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 123 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 124 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 125 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 126 I40E_AQ_RC_EFBIG = 22, /* File too large */ 127 }; 128 129 /* Admin Queue command opcodes */ 130 enum i40e_admin_queue_opc { 131 /* aq commands */ 132 i40e_aqc_opc_get_version = 0x0001, 133 i40e_aqc_opc_driver_version = 0x0002, 134 i40e_aqc_opc_queue_shutdown = 0x0003, 135 i40e_aqc_opc_set_pf_context = 0x0004, 136 137 /* resource ownership */ 138 i40e_aqc_opc_request_resource = 0x0008, 139 i40e_aqc_opc_release_resource = 0x0009, 140 141 i40e_aqc_opc_list_func_capabilities = 0x000A, 142 i40e_aqc_opc_list_dev_capabilities = 0x000B, 143 144 /* Proxy commands */ 145 i40e_aqc_opc_set_proxy_config = 0x0104, 146 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 147 148 /* LAA */ 149 i40e_aqc_opc_mac_address_read = 0x0107, 150 i40e_aqc_opc_mac_address_write = 0x0108, 151 152 /* PXE */ 153 i40e_aqc_opc_clear_pxe_mode = 0x0110, 154 155 /* WoL commands */ 156 i40e_aqc_opc_set_wol_filter = 0x0120, 157 i40e_aqc_opc_get_wake_reason = 0x0121, 158 159 /* internal switch commands */ 160 i40e_aqc_opc_get_switch_config = 0x0200, 161 i40e_aqc_opc_add_statistics = 0x0201, 162 i40e_aqc_opc_remove_statistics = 0x0202, 163 i40e_aqc_opc_set_port_parameters = 0x0203, 164 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 165 i40e_aqc_opc_set_switch_config = 0x0205, 166 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 167 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 168 169 i40e_aqc_opc_add_vsi = 0x0210, 170 i40e_aqc_opc_update_vsi_parameters = 0x0211, 171 i40e_aqc_opc_get_vsi_parameters = 0x0212, 172 173 i40e_aqc_opc_add_pv = 0x0220, 174 i40e_aqc_opc_update_pv_parameters = 0x0221, 175 i40e_aqc_opc_get_pv_parameters = 0x0222, 176 177 i40e_aqc_opc_add_veb = 0x0230, 178 i40e_aqc_opc_update_veb_parameters = 0x0231, 179 i40e_aqc_opc_get_veb_parameters = 0x0232, 180 181 i40e_aqc_opc_delete_element = 0x0243, 182 183 i40e_aqc_opc_add_macvlan = 0x0250, 184 i40e_aqc_opc_remove_macvlan = 0x0251, 185 i40e_aqc_opc_add_vlan = 0x0252, 186 i40e_aqc_opc_remove_vlan = 0x0253, 187 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 188 i40e_aqc_opc_add_tag = 0x0255, 189 i40e_aqc_opc_remove_tag = 0x0256, 190 i40e_aqc_opc_add_multicast_etag = 0x0257, 191 i40e_aqc_opc_remove_multicast_etag = 0x0258, 192 i40e_aqc_opc_update_tag = 0x0259, 193 i40e_aqc_opc_add_control_packet_filter = 0x025A, 194 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 195 i40e_aqc_opc_add_cloud_filters = 0x025C, 196 i40e_aqc_opc_remove_cloud_filters = 0x025D, 197 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 198 199 i40e_aqc_opc_add_mirror_rule = 0x0260, 200 i40e_aqc_opc_delete_mirror_rule = 0x0261, 201 202 /* Dynamic Device Personalization */ 203 i40e_aqc_opc_write_personalization_profile = 0x0270, 204 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 205 206 /* DCB commands */ 207 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 208 i40e_aqc_opc_dcb_updated = 0x0302, 209 i40e_aqc_opc_set_dcb_parameters = 0x0303, 210 211 /* TX scheduler */ 212 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 213 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 214 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 215 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 216 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 217 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 218 219 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 220 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 221 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 222 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 223 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 224 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 225 i40e_aqc_opc_query_port_ets_config = 0x0419, 226 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 227 i40e_aqc_opc_suspend_port_tx = 0x041B, 228 i40e_aqc_opc_resume_port_tx = 0x041C, 229 i40e_aqc_opc_configure_partition_bw = 0x041D, 230 /* hmc */ 231 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 232 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 233 234 /* phy commands*/ 235 i40e_aqc_opc_get_phy_abilities = 0x0600, 236 i40e_aqc_opc_set_phy_config = 0x0601, 237 i40e_aqc_opc_set_mac_config = 0x0603, 238 i40e_aqc_opc_set_link_restart_an = 0x0605, 239 i40e_aqc_opc_get_link_status = 0x0607, 240 i40e_aqc_opc_set_phy_int_mask = 0x0613, 241 i40e_aqc_opc_get_local_advt_reg = 0x0614, 242 i40e_aqc_opc_set_local_advt_reg = 0x0615, 243 i40e_aqc_opc_get_partner_advt = 0x0616, 244 i40e_aqc_opc_set_lb_modes = 0x0618, 245 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 246 i40e_aqc_opc_set_phy_debug = 0x0622, 247 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 248 i40e_aqc_opc_run_phy_activity = 0x0626, 249 i40e_aqc_opc_set_phy_register = 0x0628, 250 i40e_aqc_opc_get_phy_register = 0x0629, 251 252 /* NVM commands */ 253 i40e_aqc_opc_nvm_read = 0x0701, 254 i40e_aqc_opc_nvm_erase = 0x0702, 255 i40e_aqc_opc_nvm_update = 0x0703, 256 i40e_aqc_opc_nvm_config_read = 0x0704, 257 i40e_aqc_opc_nvm_config_write = 0x0705, 258 i40e_aqc_opc_oem_post_update = 0x0720, 259 i40e_aqc_opc_thermal_sensor = 0x0721, 260 261 /* virtualization commands */ 262 i40e_aqc_opc_send_msg_to_pf = 0x0801, 263 i40e_aqc_opc_send_msg_to_vf = 0x0802, 264 i40e_aqc_opc_send_msg_to_peer = 0x0803, 265 266 /* alternate structure */ 267 i40e_aqc_opc_alternate_write = 0x0900, 268 i40e_aqc_opc_alternate_write_indirect = 0x0901, 269 i40e_aqc_opc_alternate_read = 0x0902, 270 i40e_aqc_opc_alternate_read_indirect = 0x0903, 271 i40e_aqc_opc_alternate_write_done = 0x0904, 272 i40e_aqc_opc_alternate_set_mode = 0x0905, 273 i40e_aqc_opc_alternate_clear_port = 0x0906, 274 275 /* LLDP commands */ 276 i40e_aqc_opc_lldp_get_mib = 0x0A00, 277 i40e_aqc_opc_lldp_update_mib = 0x0A01, 278 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 279 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 280 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 281 i40e_aqc_opc_lldp_stop = 0x0A05, 282 i40e_aqc_opc_lldp_start = 0x0A06, 283 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 284 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 285 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 286 287 /* Tunnel commands */ 288 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 289 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 290 i40e_aqc_opc_set_rss_key = 0x0B02, 291 i40e_aqc_opc_set_rss_lut = 0x0B03, 292 i40e_aqc_opc_get_rss_key = 0x0B04, 293 i40e_aqc_opc_get_rss_lut = 0x0B05, 294 295 /* Async Events */ 296 i40e_aqc_opc_event_lan_overflow = 0x1001, 297 298 /* OEM commands */ 299 i40e_aqc_opc_oem_parameter_change = 0xFE00, 300 i40e_aqc_opc_oem_device_status_change = 0xFE01, 301 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 302 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 303 304 /* debug commands */ 305 i40e_aqc_opc_debug_read_reg = 0xFF03, 306 i40e_aqc_opc_debug_write_reg = 0xFF04, 307 i40e_aqc_opc_debug_modify_reg = 0xFF07, 308 i40e_aqc_opc_debug_dump_internals = 0xFF08, 309 }; 310 311 /* command structures and indirect data structures */ 312 313 /* Structure naming conventions: 314 * - no suffix for direct command descriptor structures 315 * - _data for indirect sent data 316 * - _resp for indirect return data (data which is both will use _data) 317 * - _completion for direct return data 318 * - _element_ for repeated elements (may also be _data or _resp) 319 * 320 * Command structures are expected to overlay the params.raw member of the basic 321 * descriptor, and as such cannot exceed 16 bytes in length. 322 */ 323 324 /* This macro is used to generate a compilation error if a structure 325 * is not exactly the correct length. It gives a divide by zero error if the 326 * structure is not of the correct size, otherwise it creates an enum that is 327 * never used. 328 */ 329 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 330 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 331 332 /* This macro is used extensively to ensure that command structures are 16 333 * bytes in length as they have to map to the raw array of that size. 334 */ 335 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 336 337 /* internal (0x00XX) commands */ 338 339 /* Get version (direct 0x0001) */ 340 struct i40e_aqc_get_version { 341 __le32 rom_ver; 342 __le32 fw_build; 343 __le16 fw_major; 344 __le16 fw_minor; 345 __le16 api_major; 346 __le16 api_minor; 347 }; 348 349 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 350 351 /* Send driver version (indirect 0x0002) */ 352 struct i40e_aqc_driver_version { 353 u8 driver_major_ver; 354 u8 driver_minor_ver; 355 u8 driver_build_ver; 356 u8 driver_subbuild_ver; 357 u8 reserved[4]; 358 __le32 address_high; 359 __le32 address_low; 360 }; 361 362 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 363 364 /* Queue Shutdown (direct 0x0003) */ 365 struct i40e_aqc_queue_shutdown { 366 __le32 driver_unloading; 367 #define I40E_AQ_DRIVER_UNLOADING 0x1 368 u8 reserved[12]; 369 }; 370 371 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 372 373 /* Set PF context (0x0004, direct) */ 374 struct i40e_aqc_set_pf_context { 375 u8 pf_id; 376 u8 reserved[15]; 377 }; 378 379 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 380 381 /* Request resource ownership (direct 0x0008) 382 * Release resource ownership (direct 0x0009) 383 */ 384 #define I40E_AQ_RESOURCE_NVM 1 385 #define I40E_AQ_RESOURCE_SDP 2 386 #define I40E_AQ_RESOURCE_ACCESS_READ 1 387 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 388 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 389 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 390 391 struct i40e_aqc_request_resource { 392 __le16 resource_id; 393 __le16 access_type; 394 __le32 timeout; 395 __le32 resource_number; 396 u8 reserved[4]; 397 }; 398 399 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 400 401 /* Get function capabilities (indirect 0x000A) 402 * Get device capabilities (indirect 0x000B) 403 */ 404 struct i40e_aqc_list_capabilites { 405 u8 command_flags; 406 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 407 u8 pf_index; 408 u8 reserved[2]; 409 __le32 count; 410 __le32 addr_high; 411 __le32 addr_low; 412 }; 413 414 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 415 416 struct i40e_aqc_list_capabilities_element_resp { 417 __le16 id; 418 u8 major_rev; 419 u8 minor_rev; 420 __le32 number; 421 __le32 logical_id; 422 __le32 phys_id; 423 u8 reserved[16]; 424 }; 425 426 /* list of caps */ 427 428 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 429 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 430 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 431 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 432 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 433 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 434 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 435 #define I40E_AQ_CAP_ID_SRIOV 0x0012 436 #define I40E_AQ_CAP_ID_VF 0x0013 437 #define I40E_AQ_CAP_ID_VMDQ 0x0014 438 #define I40E_AQ_CAP_ID_8021QBG 0x0015 439 #define I40E_AQ_CAP_ID_8021QBR 0x0016 440 #define I40E_AQ_CAP_ID_VSI 0x0017 441 #define I40E_AQ_CAP_ID_DCB 0x0018 442 #define I40E_AQ_CAP_ID_FCOE 0x0021 443 #define I40E_AQ_CAP_ID_ISCSI 0x0022 444 #define I40E_AQ_CAP_ID_RSS 0x0040 445 #define I40E_AQ_CAP_ID_RXQ 0x0041 446 #define I40E_AQ_CAP_ID_TXQ 0x0042 447 #define I40E_AQ_CAP_ID_MSIX 0x0043 448 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 449 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 450 #define I40E_AQ_CAP_ID_1588 0x0046 451 #define I40E_AQ_CAP_ID_IWARP 0x0051 452 #define I40E_AQ_CAP_ID_LED 0x0061 453 #define I40E_AQ_CAP_ID_SDP 0x0062 454 #define I40E_AQ_CAP_ID_MDIO 0x0063 455 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 456 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 457 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 458 #define I40E_AQ_CAP_ID_CEM 0x00F2 459 460 /* Set CPPM Configuration (direct 0x0103) */ 461 struct i40e_aqc_cppm_configuration { 462 __le16 command_flags; 463 #define I40E_AQ_CPPM_EN_LTRC 0x0800 464 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 465 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 466 #define I40E_AQ_CPPM_EN_HPTC 0x4000 467 #define I40E_AQ_CPPM_EN_DMARC 0x8000 468 __le16 ttlx; 469 __le32 dmacr; 470 __le16 dmcth; 471 u8 hptc; 472 u8 reserved; 473 __le32 pfltrc; 474 }; 475 476 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 477 478 /* Set ARP Proxy command / response (indirect 0x0104) */ 479 struct i40e_aqc_arp_proxy_data { 480 __le16 command_flags; 481 #define I40E_AQ_ARP_INIT_IPV4 0x0800 482 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 483 #define I40E_AQ_ARP_ENA 0x2000 484 #define I40E_AQ_ARP_ADD_IPV4 0x4000 485 #define I40E_AQ_ARP_DEL_IPV4 0x8000 486 __le16 table_id; 487 __le32 enabled_offloads; 488 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 489 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 490 __le32 ip_addr; 491 u8 mac_addr[6]; 492 u8 reserved[2]; 493 }; 494 495 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 496 497 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 498 struct i40e_aqc_ns_proxy_data { 499 __le16 table_idx_mac_addr_0; 500 __le16 table_idx_mac_addr_1; 501 __le16 table_idx_ipv6_0; 502 __le16 table_idx_ipv6_1; 503 __le16 control; 504 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 505 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 506 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 507 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 508 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 509 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 510 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 511 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 512 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 513 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 514 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 515 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 516 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 517 u8 mac_addr_0[6]; 518 u8 mac_addr_1[6]; 519 u8 local_mac_addr[6]; 520 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 521 u8 ipv6_addr_1[16]; 522 }; 523 524 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 525 526 /* Manage LAA Command (0x0106) - obsolete */ 527 struct i40e_aqc_mng_laa { 528 __le16 command_flags; 529 #define I40E_AQ_LAA_FLAG_WR 0x8000 530 u8 reserved[2]; 531 __le32 sal; 532 __le16 sah; 533 u8 reserved2[6]; 534 }; 535 536 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 537 538 /* Manage MAC Address Read Command (indirect 0x0107) */ 539 struct i40e_aqc_mac_address_read { 540 __le16 command_flags; 541 #define I40E_AQC_LAN_ADDR_VALID 0x10 542 #define I40E_AQC_SAN_ADDR_VALID 0x20 543 #define I40E_AQC_PORT_ADDR_VALID 0x40 544 #define I40E_AQC_WOL_ADDR_VALID 0x80 545 #define I40E_AQC_MC_MAG_EN_VALID 0x100 546 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 547 u8 reserved[6]; 548 __le32 addr_high; 549 __le32 addr_low; 550 }; 551 552 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 553 554 struct i40e_aqc_mac_address_read_data { 555 u8 pf_lan_mac[6]; 556 u8 pf_san_mac[6]; 557 u8 port_mac[6]; 558 u8 pf_wol_mac[6]; 559 }; 560 561 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 562 563 /* Manage MAC Address Write Command (0x0108) */ 564 struct i40e_aqc_mac_address_write { 565 __le16 command_flags; 566 #define I40E_AQC_MC_MAG_EN 0x0100 567 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 568 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 569 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 570 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 571 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 572 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 573 574 __le16 mac_sah; 575 __le32 mac_sal; 576 u8 reserved[8]; 577 }; 578 579 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 580 581 /* PXE commands (0x011x) */ 582 583 /* Clear PXE Command and response (direct 0x0110) */ 584 struct i40e_aqc_clear_pxe { 585 u8 rx_cnt; 586 u8 reserved[15]; 587 }; 588 589 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 590 591 /* Set WoL Filter (0x0120) */ 592 593 struct i40e_aqc_set_wol_filter { 594 __le16 filter_index; 595 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 596 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 597 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 598 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 599 600 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 601 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 602 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 603 __le16 cmd_flags; 604 #define I40E_AQC_SET_WOL_FILTER 0x8000 605 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 606 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 607 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 608 __le16 valid_flags; 609 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 610 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 611 u8 reserved[2]; 612 __le32 address_high; 613 __le32 address_low; 614 }; 615 616 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 617 618 struct i40e_aqc_set_wol_filter_data { 619 u8 filter[128]; 620 u8 mask[16]; 621 }; 622 623 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 624 625 /* Get Wake Reason (0x0121) */ 626 627 struct i40e_aqc_get_wake_reason_completion { 628 u8 reserved_1[2]; 629 __le16 wake_reason; 630 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 631 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 632 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 633 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 634 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 635 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 636 u8 reserved_2[12]; 637 }; 638 639 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 640 641 /* Switch configuration commands (0x02xx) */ 642 643 /* Used by many indirect commands that only pass an seid and a buffer in the 644 * command 645 */ 646 struct i40e_aqc_switch_seid { 647 __le16 seid; 648 u8 reserved[6]; 649 __le32 addr_high; 650 __le32 addr_low; 651 }; 652 653 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 654 655 /* Get Switch Configuration command (indirect 0x0200) 656 * uses i40e_aqc_switch_seid for the descriptor 657 */ 658 struct i40e_aqc_get_switch_config_header_resp { 659 __le16 num_reported; 660 __le16 num_total; 661 u8 reserved[12]; 662 }; 663 664 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 665 666 struct i40e_aqc_switch_config_element_resp { 667 u8 element_type; 668 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 669 #define I40E_AQ_SW_ELEM_TYPE_PF 2 670 #define I40E_AQ_SW_ELEM_TYPE_VF 3 671 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 672 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 673 #define I40E_AQ_SW_ELEM_TYPE_PV 16 674 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 675 #define I40E_AQ_SW_ELEM_TYPE_PA 18 676 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 677 u8 revision; 678 #define I40E_AQ_SW_ELEM_REV_1 1 679 __le16 seid; 680 __le16 uplink_seid; 681 __le16 downlink_seid; 682 u8 reserved[3]; 683 u8 connection_type; 684 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 685 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 686 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 687 __le16 scheduler_id; 688 __le16 element_info; 689 }; 690 691 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 692 693 /* Get Switch Configuration (indirect 0x0200) 694 * an array of elements are returned in the response buffer 695 * the first in the array is the header, remainder are elements 696 */ 697 struct i40e_aqc_get_switch_config_resp { 698 struct i40e_aqc_get_switch_config_header_resp header; 699 struct i40e_aqc_switch_config_element_resp element[1]; 700 }; 701 702 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 703 704 /* Add Statistics (direct 0x0201) 705 * Remove Statistics (direct 0x0202) 706 */ 707 struct i40e_aqc_add_remove_statistics { 708 __le16 seid; 709 __le16 vlan; 710 __le16 stat_index; 711 u8 reserved[10]; 712 }; 713 714 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 715 716 /* Set Port Parameters command (direct 0x0203) */ 717 struct i40e_aqc_set_port_parameters { 718 __le16 command_flags; 719 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 720 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 721 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 722 __le16 bad_frame_vsi; 723 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 724 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 725 __le16 default_seid; /* reserved for command */ 726 u8 reserved[10]; 727 }; 728 729 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 730 731 /* Get Switch Resource Allocation (indirect 0x0204) */ 732 struct i40e_aqc_get_switch_resource_alloc { 733 u8 num_entries; /* reserved for command */ 734 u8 reserved[7]; 735 __le32 addr_high; 736 __le32 addr_low; 737 }; 738 739 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 740 741 /* expect an array of these structs in the response buffer */ 742 struct i40e_aqc_switch_resource_alloc_element_resp { 743 u8 resource_type; 744 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 745 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 746 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 747 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 748 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 749 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 750 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 751 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 752 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 753 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 754 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 755 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 756 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 757 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 758 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 759 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 760 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 761 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 762 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 763 u8 reserved1; 764 __le16 guaranteed; 765 __le16 total; 766 __le16 used; 767 __le16 total_unalloced; 768 u8 reserved2[6]; 769 }; 770 771 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 772 773 /* Set Switch Configuration (direct 0x0205) */ 774 struct i40e_aqc_set_switch_config { 775 __le16 flags; 776 /* flags used for both fields below */ 777 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 778 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 779 __le16 valid_flags; 780 /* The ethertype in switch_tag is dropped on ingress and used 781 * internally by the switch. Set this to zero for the default 782 * of 0x88a8 (802.1ad). Should be zero for firmware API 783 * versions lower than 1.7. 784 */ 785 __le16 switch_tag; 786 /* The ethertypes in first_tag and second_tag are used to 787 * match the outer and inner VLAN tags (respectively) when HW 788 * double VLAN tagging is enabled via the set port parameters 789 * AQ command. Otherwise these are both ignored. Set them to 790 * zero for their defaults of 0x8100 (802.1Q). Should be zero 791 * for firmware API versions lower than 1.7. 792 */ 793 __le16 first_tag; 794 __le16 second_tag; 795 /* Next byte is split into following: 796 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 797 * Bit 6 : 0 : Destination Port, 1: source port 798 * Bit 5..4 : L4 type 799 * 0: rsvd 800 * 1: TCP 801 * 2: UDP 802 * 3: Both TCP and UDP 803 * Bits 3:0 Mode 804 * 0: default mode 805 * 1: L4 port only mode 806 * 2: non-tunneled mode 807 * 3: tunneled mode 808 */ 809 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 810 811 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 812 813 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 814 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 815 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 816 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 817 818 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 819 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 820 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 821 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 822 u8 mode; 823 u8 rsvd5[5]; 824 }; 825 826 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 827 828 /* Read Receive control registers (direct 0x0206) 829 * Write Receive control registers (direct 0x0207) 830 * used for accessing Rx control registers that can be 831 * slow and need special handling when under high Rx load 832 */ 833 struct i40e_aqc_rx_ctl_reg_read_write { 834 __le32 reserved1; 835 __le32 address; 836 __le32 reserved2; 837 __le32 value; 838 }; 839 840 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 841 842 /* Add VSI (indirect 0x0210) 843 * this indirect command uses struct i40e_aqc_vsi_properties_data 844 * as the indirect buffer (128 bytes) 845 * 846 * Update VSI (indirect 0x211) 847 * uses the same data structure as Add VSI 848 * 849 * Get VSI (indirect 0x0212) 850 * uses the same completion and data structure as Add VSI 851 */ 852 struct i40e_aqc_add_get_update_vsi { 853 __le16 uplink_seid; 854 u8 connection_type; 855 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 856 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 857 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 858 u8 reserved1; 859 u8 vf_id; 860 u8 reserved2; 861 __le16 vsi_flags; 862 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 863 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 864 #define I40E_AQ_VSI_TYPE_VF 0x0 865 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 866 #define I40E_AQ_VSI_TYPE_PF 0x2 867 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 868 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 869 __le32 addr_high; 870 __le32 addr_low; 871 }; 872 873 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 874 875 struct i40e_aqc_add_get_update_vsi_completion { 876 __le16 seid; 877 __le16 vsi_number; 878 __le16 vsi_used; 879 __le16 vsi_free; 880 __le32 addr_high; 881 __le32 addr_low; 882 }; 883 884 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 885 886 struct i40e_aqc_vsi_properties_data { 887 /* first 96 byte are written by SW */ 888 __le16 valid_sections; 889 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 890 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 891 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 892 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 893 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 894 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 895 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 896 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 897 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 898 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 899 /* switch section */ 900 __le16 switch_id; /* 12bit id combined with flags below */ 901 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 902 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 903 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 904 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 905 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 906 u8 sw_reserved[2]; 907 /* security section */ 908 u8 sec_flags; 909 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 910 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 911 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 912 u8 sec_reserved; 913 /* VLAN section */ 914 __le16 pvid; /* VLANS include priority bits */ 915 __le16 fcoe_pvid; 916 u8 port_vlan_flags; 917 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 918 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 919 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 920 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 921 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 922 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 923 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 924 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 925 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 926 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 927 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 928 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 929 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 930 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 931 u8 pvlan_reserved[3]; 932 /* ingress egress up sections */ 933 __le32 ingress_table; /* bitmap, 3 bits per up */ 934 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 935 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 936 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 937 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 938 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 939 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 940 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 941 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 942 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 943 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 944 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 945 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 946 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 947 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 948 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 949 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 950 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 951 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 952 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 953 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 954 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 955 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 956 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 957 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 958 __le32 egress_table; /* same defines as for ingress table */ 959 /* cascaded PV section */ 960 __le16 cas_pv_tag; 961 u8 cas_pv_flags; 962 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 963 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 964 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 965 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 966 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 967 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 968 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 969 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 970 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 971 u8 cas_pv_reserved; 972 /* queue mapping section */ 973 __le16 mapping_flags; 974 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 975 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 976 __le16 queue_mapping[16]; 977 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 978 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 979 __le16 tc_mapping[8]; 980 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 981 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 982 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 983 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 984 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 985 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 986 /* queueing option section */ 987 u8 queueing_opt_flags; 988 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 989 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 990 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 991 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 992 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 993 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 994 u8 queueing_opt_reserved[3]; 995 /* scheduler section */ 996 u8 up_enable_bits; 997 u8 sched_reserved; 998 /* outer up section */ 999 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1000 u8 cmd_reserved[8]; 1001 /* last 32 bytes are written by FW */ 1002 __le16 qs_handle[8]; 1003 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1004 __le16 stat_counter_idx; 1005 __le16 sched_id; 1006 u8 resp_reserved[12]; 1007 }; 1008 1009 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1010 1011 /* Add Port Virtualizer (direct 0x0220) 1012 * also used for update PV (direct 0x0221) but only flags are used 1013 * (IS_CTRL_PORT only works on add PV) 1014 */ 1015 struct i40e_aqc_add_update_pv { 1016 __le16 command_flags; 1017 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1018 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1019 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1020 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1021 __le16 uplink_seid; 1022 __le16 connected_seid; 1023 u8 reserved[10]; 1024 }; 1025 1026 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1027 1028 struct i40e_aqc_add_update_pv_completion { 1029 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1030 __le16 pv_seid; 1031 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1032 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1033 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1034 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1035 u8 reserved[14]; 1036 }; 1037 1038 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1039 1040 /* Get PV Params (direct 0x0222) 1041 * uses i40e_aqc_switch_seid for the descriptor 1042 */ 1043 1044 struct i40e_aqc_get_pv_params_completion { 1045 __le16 seid; 1046 __le16 default_stag; 1047 __le16 pv_flags; /* same flags as add_pv */ 1048 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1049 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1050 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1051 u8 reserved[8]; 1052 __le16 default_port_seid; 1053 }; 1054 1055 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1056 1057 /* Add VEB (direct 0x0230) */ 1058 struct i40e_aqc_add_veb { 1059 __le16 uplink_seid; 1060 __le16 downlink_seid; 1061 __le16 veb_flags; 1062 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1063 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1064 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1065 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1066 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1067 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1068 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1069 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1070 u8 enable_tcs; 1071 u8 reserved[9]; 1072 }; 1073 1074 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1075 1076 struct i40e_aqc_add_veb_completion { 1077 u8 reserved[6]; 1078 __le16 switch_seid; 1079 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1080 __le16 veb_seid; 1081 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1082 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1083 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1084 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1085 __le16 statistic_index; 1086 __le16 vebs_used; 1087 __le16 vebs_free; 1088 }; 1089 1090 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1091 1092 /* Get VEB Parameters (direct 0x0232) 1093 * uses i40e_aqc_switch_seid for the descriptor 1094 */ 1095 struct i40e_aqc_get_veb_parameters_completion { 1096 __le16 seid; 1097 __le16 switch_id; 1098 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1099 __le16 statistic_index; 1100 __le16 vebs_used; 1101 __le16 vebs_free; 1102 u8 reserved[4]; 1103 }; 1104 1105 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1106 1107 /* Delete Element (direct 0x0243) 1108 * uses the generic i40e_aqc_switch_seid 1109 */ 1110 1111 /* Add MAC-VLAN (indirect 0x0250) */ 1112 1113 /* used for the command for most vlan commands */ 1114 struct i40e_aqc_macvlan { 1115 __le16 num_addresses; 1116 __le16 seid[3]; 1117 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1118 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1119 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1120 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1121 __le32 addr_high; 1122 __le32 addr_low; 1123 }; 1124 1125 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1126 1127 /* indirect data for command and response */ 1128 struct i40e_aqc_add_macvlan_element_data { 1129 u8 mac_addr[6]; 1130 __le16 vlan_tag; 1131 __le16 flags; 1132 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1133 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1134 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1135 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1136 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1137 __le16 queue_number; 1138 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1139 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1140 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1141 /* response section */ 1142 u8 match_method; 1143 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1144 #define I40E_AQC_MM_HASH_MATCH 0x02 1145 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1146 u8 reserved1[3]; 1147 }; 1148 1149 struct i40e_aqc_add_remove_macvlan_completion { 1150 __le16 perfect_mac_used; 1151 __le16 perfect_mac_free; 1152 __le16 unicast_hash_free; 1153 __le16 multicast_hash_free; 1154 __le32 addr_high; 1155 __le32 addr_low; 1156 }; 1157 1158 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1159 1160 /* Remove MAC-VLAN (indirect 0x0251) 1161 * uses i40e_aqc_macvlan for the descriptor 1162 * data points to an array of num_addresses of elements 1163 */ 1164 1165 struct i40e_aqc_remove_macvlan_element_data { 1166 u8 mac_addr[6]; 1167 __le16 vlan_tag; 1168 u8 flags; 1169 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1170 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1171 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1172 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1173 u8 reserved[3]; 1174 /* reply section */ 1175 u8 error_code; 1176 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1177 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1178 u8 reply_reserved[3]; 1179 }; 1180 1181 /* Add VLAN (indirect 0x0252) 1182 * Remove VLAN (indirect 0x0253) 1183 * use the generic i40e_aqc_macvlan for the command 1184 */ 1185 struct i40e_aqc_add_remove_vlan_element_data { 1186 __le16 vlan_tag; 1187 u8 vlan_flags; 1188 /* flags for add VLAN */ 1189 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1190 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1191 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1192 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1193 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1194 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1195 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1196 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1197 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1198 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1199 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1200 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1201 /* flags for remove VLAN */ 1202 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1203 u8 reserved; 1204 u8 result; 1205 /* flags for add VLAN */ 1206 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1207 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1208 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1209 /* flags for remove VLAN */ 1210 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1211 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1212 u8 reserved1[3]; 1213 }; 1214 1215 struct i40e_aqc_add_remove_vlan_completion { 1216 u8 reserved[4]; 1217 __le16 vlans_used; 1218 __le16 vlans_free; 1219 __le32 addr_high; 1220 __le32 addr_low; 1221 }; 1222 1223 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1224 struct i40e_aqc_set_vsi_promiscuous_modes { 1225 __le16 promiscuous_flags; 1226 __le16 valid_flags; 1227 /* flags used for both fields above */ 1228 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1229 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1230 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1231 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1232 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1233 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1234 __le16 seid; 1235 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1236 __le16 vlan_tag; 1237 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1238 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1239 u8 reserved[8]; 1240 }; 1241 1242 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1243 1244 /* Add S/E-tag command (direct 0x0255) 1245 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1246 */ 1247 struct i40e_aqc_add_tag { 1248 __le16 flags; 1249 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1250 __le16 seid; 1251 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1252 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1253 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1254 __le16 tag; 1255 __le16 queue_number; 1256 u8 reserved[8]; 1257 }; 1258 1259 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1260 1261 struct i40e_aqc_add_remove_tag_completion { 1262 u8 reserved[12]; 1263 __le16 tags_used; 1264 __le16 tags_free; 1265 }; 1266 1267 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1268 1269 /* Remove S/E-tag command (direct 0x0256) 1270 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1271 */ 1272 struct i40e_aqc_remove_tag { 1273 __le16 seid; 1274 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1275 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1276 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1277 __le16 tag; 1278 u8 reserved[12]; 1279 }; 1280 1281 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1282 1283 /* Add multicast E-Tag (direct 0x0257) 1284 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1285 * and no external data 1286 */ 1287 struct i40e_aqc_add_remove_mcast_etag { 1288 __le16 pv_seid; 1289 __le16 etag; 1290 u8 num_unicast_etags; 1291 u8 reserved[3]; 1292 __le32 addr_high; /* address of array of 2-byte s-tags */ 1293 __le32 addr_low; 1294 }; 1295 1296 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1297 1298 struct i40e_aqc_add_remove_mcast_etag_completion { 1299 u8 reserved[4]; 1300 __le16 mcast_etags_used; 1301 __le16 mcast_etags_free; 1302 __le32 addr_high; 1303 __le32 addr_low; 1304 1305 }; 1306 1307 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1308 1309 /* Update S/E-Tag (direct 0x0259) */ 1310 struct i40e_aqc_update_tag { 1311 __le16 seid; 1312 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1313 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1314 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1315 __le16 old_tag; 1316 __le16 new_tag; 1317 u8 reserved[10]; 1318 }; 1319 1320 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1321 1322 struct i40e_aqc_update_tag_completion { 1323 u8 reserved[12]; 1324 __le16 tags_used; 1325 __le16 tags_free; 1326 }; 1327 1328 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1329 1330 /* Add Control Packet filter (direct 0x025A) 1331 * Remove Control Packet filter (direct 0x025B) 1332 * uses the i40e_aqc_add_oveb_cloud, 1333 * and the generic direct completion structure 1334 */ 1335 struct i40e_aqc_add_remove_control_packet_filter { 1336 u8 mac[6]; 1337 __le16 etype; 1338 __le16 flags; 1339 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1340 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1341 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1342 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1343 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1344 __le16 seid; 1345 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1346 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1347 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1348 __le16 queue; 1349 u8 reserved[2]; 1350 }; 1351 1352 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1353 1354 struct i40e_aqc_add_remove_control_packet_filter_completion { 1355 __le16 mac_etype_used; 1356 __le16 etype_used; 1357 __le16 mac_etype_free; 1358 __le16 etype_free; 1359 u8 reserved[8]; 1360 }; 1361 1362 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1363 1364 /* Add Cloud filters (indirect 0x025C) 1365 * Remove Cloud filters (indirect 0x025D) 1366 * uses the i40e_aqc_add_remove_cloud_filters, 1367 * and the generic indirect completion structure 1368 */ 1369 struct i40e_aqc_add_remove_cloud_filters { 1370 u8 num_filters; 1371 u8 reserved; 1372 __le16 seid; 1373 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1374 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1375 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1376 u8 big_buffer_flag; 1377 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1378 u8 reserved2[3]; 1379 __le32 addr_high; 1380 __le32 addr_low; 1381 }; 1382 1383 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1384 1385 struct i40e_aqc_cloud_filters_element_data { 1386 u8 outer_mac[6]; 1387 u8 inner_mac[6]; 1388 __le16 inner_vlan; 1389 union { 1390 struct { 1391 u8 reserved[12]; 1392 u8 data[4]; 1393 } v4; 1394 struct { 1395 u8 data[16]; 1396 } v6; 1397 struct { 1398 __le16 data[8]; 1399 } raw_v6; 1400 } ipaddr; 1401 __le16 flags; 1402 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1403 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1404 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1405 /* 0x0000 reserved */ 1406 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1407 /* 0x0002 reserved */ 1408 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1409 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1410 /* 0x0005 reserved */ 1411 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1412 /* 0x0007 reserved */ 1413 /* 0x0008 reserved */ 1414 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1415 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1416 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1417 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1418 /* 0x0010 to 0x0017 is for custom filters */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1420 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1421 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1422 1423 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1424 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1425 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1426 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1427 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1428 1429 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1435 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1436 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1437 1438 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1439 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1440 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1441 1442 __le32 tenant_id; 1443 u8 reserved[4]; 1444 __le16 queue_number; 1445 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1446 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1447 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1448 u8 reserved2[14]; 1449 /* response section */ 1450 u8 allocation_result; 1451 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1452 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1453 u8 response_reserved[7]; 1454 }; 1455 1456 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1457 1458 /* i40e_aqc_cloud_filters_element_bb is used when 1459 * I40E_AQC_CLOUD_CMD_BB flag is set. 1460 */ 1461 struct i40e_aqc_cloud_filters_element_bb { 1462 struct i40e_aqc_cloud_filters_element_data element; 1463 u16 general_fields[32]; 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1473 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1474 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1475 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1476 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1477 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1478 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1479 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1480 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1481 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1482 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1483 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1484 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1485 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1486 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1487 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1488 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1489 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1490 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1491 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1492 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1493 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1494 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1495 }; 1496 1497 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1498 1499 struct i40e_aqc_remove_cloud_filters_completion { 1500 __le16 perfect_ovlan_used; 1501 __le16 perfect_ovlan_free; 1502 __le16 vlan_used; 1503 __le16 vlan_free; 1504 __le32 addr_high; 1505 __le32 addr_low; 1506 }; 1507 1508 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1509 1510 /* Replace filter Command 0x025F 1511 * uses the i40e_aqc_replace_cloud_filters, 1512 * and the generic indirect completion structure 1513 */ 1514 struct i40e_filter_data { 1515 u8 filter_type; 1516 u8 input[3]; 1517 }; 1518 1519 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1520 1521 struct i40e_aqc_replace_cloud_filters_cmd { 1522 u8 valid_flags; 1523 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1524 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1525 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1526 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1527 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1528 u8 old_filter_type; 1529 u8 new_filter_type; 1530 u8 tr_bit; 1531 u8 reserved[4]; 1532 __le32 addr_high; 1533 __le32 addr_low; 1534 }; 1535 1536 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1537 1538 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1539 u8 data[32]; 1540 /* Filter type INPUT codes*/ 1541 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1542 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1543 1544 /* Field Vector offsets */ 1545 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1546 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1547 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1548 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1549 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1550 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1551 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1552 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1553 /* big FLU */ 1554 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1555 /* big FLU */ 1556 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1557 1558 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1559 struct i40e_filter_data filters[8]; 1560 }; 1561 1562 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1563 1564 /* Add Mirror Rule (indirect or direct 0x0260) 1565 * Delete Mirror Rule (indirect or direct 0x0261) 1566 * note: some rule types (4,5) do not use an external buffer. 1567 * take care to set the flags correctly. 1568 */ 1569 struct i40e_aqc_add_delete_mirror_rule { 1570 __le16 seid; 1571 __le16 rule_type; 1572 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1573 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1574 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1575 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1576 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1577 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1578 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1579 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1580 __le16 num_entries; 1581 __le16 destination; /* VSI for add, rule id for delete */ 1582 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1583 __le32 addr_low; 1584 }; 1585 1586 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1587 1588 struct i40e_aqc_add_delete_mirror_rule_completion { 1589 u8 reserved[2]; 1590 __le16 rule_id; /* only used on add */ 1591 __le16 mirror_rules_used; 1592 __le16 mirror_rules_free; 1593 __le32 addr_high; 1594 __le32 addr_low; 1595 }; 1596 1597 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1598 1599 /* Dynamic Device Personalization */ 1600 struct i40e_aqc_write_personalization_profile { 1601 u8 flags; 1602 u8 reserved[3]; 1603 __le32 profile_track_id; 1604 __le32 addr_high; 1605 __le32 addr_low; 1606 }; 1607 1608 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1609 1610 struct i40e_aqc_write_ddp_resp { 1611 __le32 error_offset; 1612 __le32 error_info; 1613 __le32 addr_high; 1614 __le32 addr_low; 1615 }; 1616 1617 struct i40e_aqc_get_applied_profiles { 1618 u8 flags; 1619 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1620 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1621 u8 rsv[3]; 1622 __le32 reserved; 1623 __le32 addr_high; 1624 __le32 addr_low; 1625 }; 1626 1627 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1628 1629 /* DCB 0x03xx*/ 1630 1631 /* PFC Ignore (direct 0x0301) 1632 * the command and response use the same descriptor structure 1633 */ 1634 struct i40e_aqc_pfc_ignore { 1635 u8 tc_bitmap; 1636 u8 command_flags; /* unused on response */ 1637 #define I40E_AQC_PFC_IGNORE_SET 0x80 1638 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1639 u8 reserved[14]; 1640 }; 1641 1642 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1643 1644 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1645 * with no parameters 1646 */ 1647 1648 /* TX scheduler 0x04xx */ 1649 1650 /* Almost all the indirect commands use 1651 * this generic struct to pass the SEID in param0 1652 */ 1653 struct i40e_aqc_tx_sched_ind { 1654 __le16 vsi_seid; 1655 u8 reserved[6]; 1656 __le32 addr_high; 1657 __le32 addr_low; 1658 }; 1659 1660 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1661 1662 /* Several commands respond with a set of queue set handles */ 1663 struct i40e_aqc_qs_handles_resp { 1664 __le16 qs_handles[8]; 1665 }; 1666 1667 /* Configure VSI BW limits (direct 0x0400) */ 1668 struct i40e_aqc_configure_vsi_bw_limit { 1669 __le16 vsi_seid; 1670 u8 reserved[2]; 1671 __le16 credit; 1672 u8 reserved1[2]; 1673 u8 max_credit; /* 0-3, limit = 2^max */ 1674 u8 reserved2[7]; 1675 }; 1676 1677 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1678 1679 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1680 * responds with i40e_aqc_qs_handles_resp 1681 */ 1682 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1683 u8 tc_valid_bits; 1684 u8 reserved[15]; 1685 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1686 1687 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1688 __le16 tc_bw_max[2]; 1689 u8 reserved1[28]; 1690 }; 1691 1692 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1693 1694 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1695 * responds with i40e_aqc_qs_handles_resp 1696 */ 1697 struct i40e_aqc_configure_vsi_tc_bw_data { 1698 u8 tc_valid_bits; 1699 u8 reserved[3]; 1700 u8 tc_bw_credits[8]; 1701 u8 reserved1[4]; 1702 __le16 qs_handles[8]; 1703 }; 1704 1705 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1706 1707 /* Query vsi bw configuration (indirect 0x0408) */ 1708 struct i40e_aqc_query_vsi_bw_config_resp { 1709 u8 tc_valid_bits; 1710 u8 tc_suspended_bits; 1711 u8 reserved[14]; 1712 __le16 qs_handles[8]; 1713 u8 reserved1[4]; 1714 __le16 port_bw_limit; 1715 u8 reserved2[2]; 1716 u8 max_bw; /* 0-3, limit = 2^max */ 1717 u8 reserved3[23]; 1718 }; 1719 1720 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1721 1722 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1723 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1724 u8 tc_valid_bits; 1725 u8 reserved[3]; 1726 u8 share_credits[8]; 1727 __le16 credits[8]; 1728 1729 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1730 __le16 tc_bw_max[2]; 1731 }; 1732 1733 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1734 1735 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1736 struct i40e_aqc_configure_switching_comp_bw_limit { 1737 __le16 seid; 1738 u8 reserved[2]; 1739 __le16 credit; 1740 u8 reserved1[2]; 1741 u8 max_bw; /* 0-3, limit = 2^max */ 1742 u8 reserved2[7]; 1743 }; 1744 1745 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1746 1747 /* Enable Physical Port ETS (indirect 0x0413) 1748 * Modify Physical Port ETS (indirect 0x0414) 1749 * Disable Physical Port ETS (indirect 0x0415) 1750 */ 1751 struct i40e_aqc_configure_switching_comp_ets_data { 1752 u8 reserved[4]; 1753 u8 tc_valid_bits; 1754 u8 seepage; 1755 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1756 u8 tc_strict_priority_flags; 1757 u8 reserved1[17]; 1758 u8 tc_bw_share_credits[8]; 1759 u8 reserved2[96]; 1760 }; 1761 1762 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1763 1764 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1765 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1766 u8 tc_valid_bits; 1767 u8 reserved[15]; 1768 __le16 tc_bw_credit[8]; 1769 1770 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1771 __le16 tc_bw_max[2]; 1772 u8 reserved1[28]; 1773 }; 1774 1775 I40E_CHECK_STRUCT_LEN(0x40, 1776 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1777 1778 /* Configure Switching Component Bandwidth Allocation per Tc 1779 * (indirect 0x0417) 1780 */ 1781 struct i40e_aqc_configure_switching_comp_bw_config_data { 1782 u8 tc_valid_bits; 1783 u8 reserved[2]; 1784 u8 absolute_credits; /* bool */ 1785 u8 tc_bw_share_credits[8]; 1786 u8 reserved1[20]; 1787 }; 1788 1789 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1790 1791 /* Query Switching Component Configuration (indirect 0x0418) */ 1792 struct i40e_aqc_query_switching_comp_ets_config_resp { 1793 u8 tc_valid_bits; 1794 u8 reserved[35]; 1795 __le16 port_bw_limit; 1796 u8 reserved1[2]; 1797 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1798 u8 reserved2[23]; 1799 }; 1800 1801 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1802 1803 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1804 struct i40e_aqc_query_port_ets_config_resp { 1805 u8 reserved[4]; 1806 u8 tc_valid_bits; 1807 u8 reserved1; 1808 u8 tc_strict_priority_bits; 1809 u8 reserved2; 1810 u8 tc_bw_share_credits[8]; 1811 __le16 tc_bw_limits[8]; 1812 1813 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1814 __le16 tc_bw_max[2]; 1815 u8 reserved3[32]; 1816 }; 1817 1818 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1819 1820 /* Query Switching Component Bandwidth Allocation per Traffic Type 1821 * (indirect 0x041A) 1822 */ 1823 struct i40e_aqc_query_switching_comp_bw_config_resp { 1824 u8 tc_valid_bits; 1825 u8 reserved[2]; 1826 u8 absolute_credits_enable; /* bool */ 1827 u8 tc_bw_share_credits[8]; 1828 __le16 tc_bw_limits[8]; 1829 1830 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1831 __le16 tc_bw_max[2]; 1832 }; 1833 1834 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1835 1836 /* Suspend/resume port TX traffic 1837 * (direct 0x041B and 0x041C) uses the generic SEID struct 1838 */ 1839 1840 /* Configure partition BW 1841 * (indirect 0x041D) 1842 */ 1843 struct i40e_aqc_configure_partition_bw_data { 1844 __le16 pf_valid_bits; 1845 u8 min_bw[16]; /* guaranteed bandwidth */ 1846 u8 max_bw[16]; /* bandwidth limit */ 1847 }; 1848 1849 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1850 1851 /* Get and set the active HMC resource profile and status. 1852 * (direct 0x0500) and (direct 0x0501) 1853 */ 1854 struct i40e_aq_get_set_hmc_resource_profile { 1855 u8 pm_profile; 1856 u8 pe_vf_enabled; 1857 u8 reserved[14]; 1858 }; 1859 1860 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1861 1862 enum i40e_aq_hmc_profile { 1863 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1864 I40E_HMC_PROFILE_DEFAULT = 1, 1865 I40E_HMC_PROFILE_FAVOR_VF = 2, 1866 I40E_HMC_PROFILE_EQUAL = 3, 1867 }; 1868 1869 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1870 1871 /* set in param0 for get phy abilities to report qualified modules */ 1872 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1873 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1874 1875 enum i40e_aq_phy_type { 1876 I40E_PHY_TYPE_SGMII = 0x0, 1877 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1878 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1879 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1880 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1881 I40E_PHY_TYPE_XAUI = 0x5, 1882 I40E_PHY_TYPE_XFI = 0x6, 1883 I40E_PHY_TYPE_SFI = 0x7, 1884 I40E_PHY_TYPE_XLAUI = 0x8, 1885 I40E_PHY_TYPE_XLPPI = 0x9, 1886 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1887 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1888 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1889 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1890 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1891 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1892 I40E_PHY_TYPE_100BASE_TX = 0x11, 1893 I40E_PHY_TYPE_1000BASE_T = 0x12, 1894 I40E_PHY_TYPE_10GBASE_T = 0x13, 1895 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1896 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1897 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1898 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1899 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1900 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1901 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1902 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1903 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1904 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1905 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1906 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1907 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1908 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1909 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1910 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1911 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1912 I40E_PHY_TYPE_MAX, 1913 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1914 I40E_PHY_TYPE_EMPTY = 0xFE, 1915 I40E_PHY_TYPE_DEFAULT = 0xFF, 1916 }; 1917 1918 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1919 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1920 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1921 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1922 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1923 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1924 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1925 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1926 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1927 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1928 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1929 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1930 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1931 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1932 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1933 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1934 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1935 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1936 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1937 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1938 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1939 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1940 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1941 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1942 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1943 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1944 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1945 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1946 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1947 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1948 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1949 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1950 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1951 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1952 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1953 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) 1954 1955 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1956 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1957 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1958 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1959 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1960 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1961 1962 enum i40e_aq_link_speed { 1963 I40E_LINK_SPEED_UNKNOWN = 0, 1964 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1965 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1966 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1967 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1968 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1969 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1970 }; 1971 1972 struct i40e_aqc_module_desc { 1973 u8 oui[3]; 1974 u8 reserved1; 1975 u8 part_number[16]; 1976 u8 revision[4]; 1977 u8 reserved2[8]; 1978 }; 1979 1980 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1981 1982 struct i40e_aq_get_phy_abilities_resp { 1983 __le32 phy_type; /* bitmap using the above enum for offsets */ 1984 u8 link_speed; /* bitmap using the above enum bit patterns */ 1985 u8 abilities; 1986 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1987 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1988 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1989 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1990 #define I40E_AQ_PHY_AN_ENABLED 0x10 1991 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1992 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1993 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1994 __le16 eee_capability; 1995 #define I40E_AQ_EEE_100BASE_TX 0x0002 1996 #define I40E_AQ_EEE_1000BASE_T 0x0004 1997 #define I40E_AQ_EEE_10GBASE_T 0x0008 1998 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1999 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 2000 #define I40E_AQ_EEE_10GBASE_KR 0x0040 2001 __le32 eeer_val; 2002 u8 d3_lpan; 2003 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 2004 u8 phy_type_ext; 2005 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2006 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2007 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2008 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2009 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 2010 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 2011 u8 fec_cfg_curr_mod_ext_info; 2012 #define I40E_AQ_ENABLE_FEC_KR 0x01 2013 #define I40E_AQ_ENABLE_FEC_RS 0x02 2014 #define I40E_AQ_REQUEST_FEC_KR 0x04 2015 #define I40E_AQ_REQUEST_FEC_RS 0x08 2016 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 2017 #define I40E_AQ_FEC 2018 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 2019 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 2020 2021 u8 ext_comp_code; 2022 u8 phy_id[4]; 2023 u8 module_type[3]; 2024 u8 qualified_module_count; 2025 #define I40E_AQ_PHY_MAX_QMS 16 2026 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2027 }; 2028 2029 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2030 2031 /* Set PHY Config (direct 0x0601) */ 2032 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2033 __le32 phy_type; 2034 u8 link_speed; 2035 u8 abilities; 2036 /* bits 0-2 use the values from get_phy_abilities_resp */ 2037 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2038 #define I40E_AQ_PHY_ENABLE_AN 0x10 2039 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2040 __le16 eee_capability; 2041 __le32 eeer; 2042 u8 low_power_ctrl; 2043 u8 phy_type_ext; 2044 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2045 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2046 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2047 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2048 u8 fec_config; 2049 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2050 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2051 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2052 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2053 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2054 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2055 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2056 u8 reserved; 2057 }; 2058 2059 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2060 2061 /* Set MAC Config command data structure (direct 0x0603) */ 2062 struct i40e_aq_set_mac_config { 2063 __le16 max_frame_size; 2064 u8 params; 2065 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2066 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2067 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2068 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2069 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2070 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2071 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2072 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2073 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2074 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2075 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2076 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2077 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2078 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2079 u8 tx_timer_priority; /* bitmap */ 2080 __le16 tx_timer_value; 2081 __le16 fc_refresh_threshold; 2082 u8 reserved[8]; 2083 }; 2084 2085 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2086 2087 /* Restart Auto-Negotiation (direct 0x605) */ 2088 struct i40e_aqc_set_link_restart_an { 2089 u8 command; 2090 #define I40E_AQ_PHY_RESTART_AN 0x02 2091 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2092 u8 reserved[15]; 2093 }; 2094 2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2096 2097 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2098 struct i40e_aqc_get_link_status { 2099 __le16 command_flags; /* only field set on command */ 2100 #define I40E_AQ_LSE_MASK 0x3 2101 #define I40E_AQ_LSE_NOP 0x0 2102 #define I40E_AQ_LSE_DISABLE 0x2 2103 #define I40E_AQ_LSE_ENABLE 0x3 2104 /* only response uses this flag */ 2105 #define I40E_AQ_LSE_IS_ENABLED 0x1 2106 u8 phy_type; /* i40e_aq_phy_type */ 2107 u8 link_speed; /* i40e_aq_link_speed */ 2108 u8 link_info; 2109 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2110 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2111 #define I40E_AQ_LINK_FAULT 0x02 2112 #define I40E_AQ_LINK_FAULT_TX 0x04 2113 #define I40E_AQ_LINK_FAULT_RX 0x08 2114 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2115 #define I40E_AQ_LINK_UP_PORT 0x20 2116 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2117 #define I40E_AQ_SIGNAL_DETECT 0x80 2118 u8 an_info; 2119 #define I40E_AQ_AN_COMPLETED 0x01 2120 #define I40E_AQ_LP_AN_ABILITY 0x02 2121 #define I40E_AQ_PD_FAULT 0x04 2122 #define I40E_AQ_FEC_EN 0x08 2123 #define I40E_AQ_PHY_LOW_POWER 0x10 2124 #define I40E_AQ_LINK_PAUSE_TX 0x20 2125 #define I40E_AQ_LINK_PAUSE_RX 0x40 2126 #define I40E_AQ_QUALIFIED_MODULE 0x80 2127 u8 ext_info; 2128 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2129 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2130 #define I40E_AQ_LINK_TX_SHIFT 0x02 2131 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2132 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2133 #define I40E_AQ_LINK_TX_DRAINED 0x01 2134 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2135 #define I40E_AQ_LINK_FORCED_40G 0x10 2136 /* 25G Error Codes */ 2137 #define I40E_AQ_25G_NO_ERR 0X00 2138 #define I40E_AQ_25G_NOT_PRESENT 0X01 2139 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2140 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2141 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2142 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2143 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2144 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2145 #define I40E_AQ_LOOPBACK_MASK 0x07 2146 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2147 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2148 __le16 max_frame_size; 2149 u8 config; 2150 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2151 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2152 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2153 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2154 union { 2155 struct { 2156 u8 power_desc; 2157 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2158 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2159 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2160 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2161 #define I40E_AQ_PWR_CLASS_MASK 0x03 2162 u8 reserved[4]; 2163 }; 2164 struct { 2165 u8 link_type[4]; 2166 u8 link_type_ext; 2167 }; 2168 }; 2169 }; 2170 2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2172 2173 /* Set event mask command (direct 0x613) */ 2174 struct i40e_aqc_set_phy_int_mask { 2175 u8 reserved[8]; 2176 __le16 event_mask; 2177 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2178 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2179 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2180 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2181 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2182 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2183 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2184 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2185 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2186 u8 reserved1[6]; 2187 }; 2188 2189 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2190 2191 /* Get Local AN advt register (direct 0x0614) 2192 * Set Local AN advt register (direct 0x0615) 2193 * Get Link Partner AN advt register (direct 0x0616) 2194 */ 2195 struct i40e_aqc_an_advt_reg { 2196 __le32 local_an_reg0; 2197 __le16 local_an_reg1; 2198 u8 reserved[10]; 2199 }; 2200 2201 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2202 2203 /* Set Loopback mode (0x0618) */ 2204 struct i40e_aqc_set_lb_mode { 2205 __le16 lb_mode; 2206 #define I40E_AQ_LB_PHY_LOCAL 0x01 2207 #define I40E_AQ_LB_PHY_REMOTE 0x02 2208 #define I40E_AQ_LB_MAC_LOCAL 0x04 2209 u8 reserved[14]; 2210 }; 2211 2212 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2213 2214 /* Set PHY Debug command (0x0622) */ 2215 struct i40e_aqc_set_phy_debug { 2216 u8 command_flags; 2217 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2218 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2219 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2220 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2221 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2222 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2223 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2224 /* Disable link manageability on a single port */ 2225 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2226 /* Disable link manageability on all ports */ 2227 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2228 u8 reserved[15]; 2229 }; 2230 2231 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2232 2233 enum i40e_aq_phy_reg_type { 2234 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2235 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2236 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2237 }; 2238 2239 /* Run PHY Activity (0x0626) */ 2240 struct i40e_aqc_run_phy_activity { 2241 __le16 activity_id; 2242 u8 flags; 2243 u8 reserved1; 2244 __le32 control; 2245 __le32 data; 2246 u8 reserved2[4]; 2247 }; 2248 2249 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2250 2251 /* Set PHY Register command (0x0628) */ 2252 /* Get PHY Register command (0x0629) */ 2253 struct i40e_aqc_phy_register_access { 2254 u8 phy_interface; 2255 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2256 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2257 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2258 u8 dev_address; 2259 u8 reserved1[2]; 2260 __le32 reg_address; 2261 __le32 reg_value; 2262 u8 reserved2[4]; 2263 }; 2264 2265 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2266 2267 /* NVM Read command (indirect 0x0701) 2268 * NVM Erase commands (direct 0x0702) 2269 * NVM Update commands (indirect 0x0703) 2270 */ 2271 struct i40e_aqc_nvm_update { 2272 u8 command_flags; 2273 #define I40E_AQ_NVM_LAST_CMD 0x01 2274 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2275 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2276 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2277 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2278 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2279 u8 module_pointer; 2280 __le16 length; 2281 __le32 offset; 2282 __le32 addr_high; 2283 __le32 addr_low; 2284 }; 2285 2286 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2287 2288 /* NVM Config Read (indirect 0x0704) */ 2289 struct i40e_aqc_nvm_config_read { 2290 __le16 cmd_flags; 2291 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2292 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2293 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2294 __le16 element_count; 2295 __le16 element_id; /* Feature/field ID */ 2296 __le16 element_id_msw; /* MSWord of field ID */ 2297 __le32 address_high; 2298 __le32 address_low; 2299 }; 2300 2301 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2302 2303 /* NVM Config Write (indirect 0x0705) */ 2304 struct i40e_aqc_nvm_config_write { 2305 __le16 cmd_flags; 2306 __le16 element_count; 2307 u8 reserved[4]; 2308 __le32 address_high; 2309 __le32 address_low; 2310 }; 2311 2312 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2313 2314 /* Used for 0x0704 as well as for 0x0705 commands */ 2315 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2316 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2317 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2318 #define I40E_AQ_ANVM_FEATURE 0 2319 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2320 struct i40e_aqc_nvm_config_data_feature { 2321 __le16 feature_id; 2322 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2323 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2324 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2325 __le16 feature_options; 2326 __le16 feature_selection; 2327 }; 2328 2329 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2330 2331 struct i40e_aqc_nvm_config_data_immediate_field { 2332 __le32 field_id; 2333 __le32 field_value; 2334 __le16 field_options; 2335 __le16 reserved; 2336 }; 2337 2338 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2339 2340 /* OEM Post Update (indirect 0x0720) 2341 * no command data struct used 2342 */ 2343 struct i40e_aqc_nvm_oem_post_update { 2344 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2345 u8 sel_data; 2346 u8 reserved[7]; 2347 }; 2348 2349 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2350 2351 struct i40e_aqc_nvm_oem_post_update_buffer { 2352 u8 str_len; 2353 u8 dev_addr; 2354 __le16 eeprom_addr; 2355 u8 data[36]; 2356 }; 2357 2358 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2359 2360 /* Thermal Sensor (indirect 0x0721) 2361 * read or set thermal sensor configs and values 2362 * takes a sensor and command specific data buffer, not detailed here 2363 */ 2364 struct i40e_aqc_thermal_sensor { 2365 u8 sensor_action; 2366 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2367 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2368 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2369 u8 reserved[7]; 2370 __le32 addr_high; 2371 __le32 addr_low; 2372 }; 2373 2374 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2375 2376 /* Send to PF command (indirect 0x0801) id is only used by PF 2377 * Send to VF command (indirect 0x0802) id is only used by PF 2378 * Send to Peer PF command (indirect 0x0803) 2379 */ 2380 struct i40e_aqc_pf_vf_message { 2381 __le32 id; 2382 u8 reserved[4]; 2383 __le32 addr_high; 2384 __le32 addr_low; 2385 }; 2386 2387 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2388 2389 /* Alternate structure */ 2390 2391 /* Direct write (direct 0x0900) 2392 * Direct read (direct 0x0902) 2393 */ 2394 struct i40e_aqc_alternate_write { 2395 __le32 address0; 2396 __le32 data0; 2397 __le32 address1; 2398 __le32 data1; 2399 }; 2400 2401 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2402 2403 /* Indirect write (indirect 0x0901) 2404 * Indirect read (indirect 0x0903) 2405 */ 2406 2407 struct i40e_aqc_alternate_ind_write { 2408 __le32 address; 2409 __le32 length; 2410 __le32 addr_high; 2411 __le32 addr_low; 2412 }; 2413 2414 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2415 2416 /* Done alternate write (direct 0x0904) 2417 * uses i40e_aq_desc 2418 */ 2419 struct i40e_aqc_alternate_write_done { 2420 __le16 cmd_flags; 2421 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2422 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2423 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2424 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2425 u8 reserved[14]; 2426 }; 2427 2428 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2429 2430 /* Set OEM mode (direct 0x0905) */ 2431 struct i40e_aqc_alternate_set_mode { 2432 __le32 mode; 2433 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2434 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2435 u8 reserved[12]; 2436 }; 2437 2438 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2439 2440 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2441 2442 /* async events 0x10xx */ 2443 2444 /* Lan Queue Overflow Event (direct, 0x1001) */ 2445 struct i40e_aqc_lan_overflow { 2446 __le32 prtdcb_rupto; 2447 __le32 otx_ctl; 2448 u8 reserved[8]; 2449 }; 2450 2451 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2452 2453 /* Get LLDP MIB (indirect 0x0A00) */ 2454 struct i40e_aqc_lldp_get_mib { 2455 u8 type; 2456 u8 reserved1; 2457 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2458 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2459 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2460 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2461 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2462 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2463 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2464 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2465 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2466 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2467 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2468 __le16 local_len; 2469 __le16 remote_len; 2470 u8 reserved2[2]; 2471 __le32 addr_high; 2472 __le32 addr_low; 2473 }; 2474 2475 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2476 2477 /* Configure LLDP MIB Change Event (direct 0x0A01) 2478 * also used for the event (with type in the command field) 2479 */ 2480 struct i40e_aqc_lldp_update_mib { 2481 u8 command; 2482 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2483 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2484 u8 reserved[7]; 2485 __le32 addr_high; 2486 __le32 addr_low; 2487 }; 2488 2489 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2490 2491 /* Add LLDP TLV (indirect 0x0A02) 2492 * Delete LLDP TLV (indirect 0x0A04) 2493 */ 2494 struct i40e_aqc_lldp_add_tlv { 2495 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2496 u8 reserved1[1]; 2497 __le16 len; 2498 u8 reserved2[4]; 2499 __le32 addr_high; 2500 __le32 addr_low; 2501 }; 2502 2503 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2504 2505 /* Update LLDP TLV (indirect 0x0A03) */ 2506 struct i40e_aqc_lldp_update_tlv { 2507 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2508 u8 reserved; 2509 __le16 old_len; 2510 __le16 new_offset; 2511 __le16 new_len; 2512 __le32 addr_high; 2513 __le32 addr_low; 2514 }; 2515 2516 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2517 2518 /* Stop LLDP (direct 0x0A05) */ 2519 struct i40e_aqc_lldp_stop { 2520 u8 command; 2521 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2522 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2523 u8 reserved[15]; 2524 }; 2525 2526 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2527 2528 /* Start LLDP (direct 0x0A06) */ 2529 2530 struct i40e_aqc_lldp_start { 2531 u8 command; 2532 #define I40E_AQ_LLDP_AGENT_START 0x1 2533 u8 reserved[15]; 2534 }; 2535 2536 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2537 2538 /* Set DCB (direct 0x0303) */ 2539 struct i40e_aqc_set_dcb_parameters { 2540 u8 command; 2541 #define I40E_AQ_DCB_SET_AGENT 0x1 2542 #define I40E_DCB_VALID 0x1 2543 u8 valid_flags; 2544 u8 reserved[14]; 2545 }; 2546 2547 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2548 2549 /* Get CEE DCBX Oper Config (0x0A07) 2550 * uses the generic descriptor struct 2551 * returns below as indirect response 2552 */ 2553 2554 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2555 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2556 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2557 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2558 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2559 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2560 2561 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2562 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2563 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2564 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2565 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2566 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2567 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2568 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2569 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2570 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2571 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2572 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2573 2574 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2575 * word boundary layout issues, which the Linux compilers silently deal 2576 * with by adding padding, making the actual struct larger than designed. 2577 * However, the FW compiler for the NIC is less lenient and complains 2578 * about the struct. Hence, the struct defined here has an extra byte in 2579 * fields reserved3 and reserved4 to directly acknowledge that padding, 2580 * and the new length is used in the length check macro. 2581 */ 2582 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2583 u8 reserved1; 2584 u8 oper_num_tc; 2585 u8 oper_prio_tc[4]; 2586 u8 reserved2; 2587 u8 oper_tc_bw[8]; 2588 u8 oper_pfc_en; 2589 u8 reserved3[2]; 2590 __le16 oper_app_prio; 2591 u8 reserved4[2]; 2592 __le16 tlv_status; 2593 }; 2594 2595 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2596 2597 struct i40e_aqc_get_cee_dcb_cfg_resp { 2598 u8 oper_num_tc; 2599 u8 oper_prio_tc[4]; 2600 u8 oper_tc_bw[8]; 2601 u8 oper_pfc_en; 2602 __le16 oper_app_prio; 2603 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2604 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2605 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2606 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2607 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2608 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2609 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2610 __le32 tlv_status; 2611 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2612 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2613 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2614 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2615 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2616 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2617 u8 reserved[12]; 2618 }; 2619 2620 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2621 2622 /* Set Local LLDP MIB (indirect 0x0A08) 2623 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2624 */ 2625 struct i40e_aqc_lldp_set_local_mib { 2626 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2627 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2628 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2629 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2630 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2631 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2632 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2633 u8 type; 2634 u8 reserved0; 2635 __le16 length; 2636 u8 reserved1[4]; 2637 __le32 address_high; 2638 __le32 address_low; 2639 }; 2640 2641 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2642 2643 /* Stop/Start LLDP Agent (direct 0x0A09) 2644 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2645 */ 2646 struct i40e_aqc_lldp_stop_start_specific_agent { 2647 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2648 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2649 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2650 u8 command; 2651 u8 reserved[15]; 2652 }; 2653 2654 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2655 2656 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2657 struct i40e_aqc_add_udp_tunnel { 2658 __le16 udp_port; 2659 u8 reserved0[3]; 2660 u8 protocol_type; 2661 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2662 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2663 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2664 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2665 u8 reserved1[10]; 2666 }; 2667 2668 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2669 2670 struct i40e_aqc_add_udp_tunnel_completion { 2671 __le16 udp_port; 2672 u8 filter_entry_index; 2673 u8 multiple_pfs; 2674 #define I40E_AQC_SINGLE_PF 0x0 2675 #define I40E_AQC_MULTIPLE_PFS 0x1 2676 u8 total_filters; 2677 u8 reserved[11]; 2678 }; 2679 2680 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2681 2682 /* remove UDP Tunnel command (0x0B01) */ 2683 struct i40e_aqc_remove_udp_tunnel { 2684 u8 reserved[2]; 2685 u8 index; /* 0 to 15 */ 2686 u8 reserved2[13]; 2687 }; 2688 2689 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2690 2691 struct i40e_aqc_del_udp_tunnel_completion { 2692 __le16 udp_port; 2693 u8 index; /* 0 to 15 */ 2694 u8 multiple_pfs; 2695 u8 total_filters_used; 2696 u8 reserved1[11]; 2697 }; 2698 2699 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2700 2701 struct i40e_aqc_get_set_rss_key { 2702 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2703 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2704 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2705 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2706 __le16 vsi_id; 2707 u8 reserved[6]; 2708 __le32 addr_high; 2709 __le32 addr_low; 2710 }; 2711 2712 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2713 2714 struct i40e_aqc_get_set_rss_key_data { 2715 u8 standard_rss_key[0x28]; 2716 u8 extended_hash_key[0xc]; 2717 }; 2718 2719 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2720 2721 struct i40e_aqc_get_set_rss_lut { 2722 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2723 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2724 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2725 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2726 __le16 vsi_id; 2727 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2728 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2729 2730 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2731 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2732 __le16 flags; 2733 u8 reserved[4]; 2734 __le32 addr_high; 2735 __le32 addr_low; 2736 }; 2737 2738 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2739 2740 /* tunnel key structure 0x0B10 */ 2741 2742 struct i40e_aqc_tunnel_key_structure { 2743 u8 key1_off; 2744 u8 key2_off; 2745 u8 key1_len; /* 0 to 15 */ 2746 u8 key2_len; /* 0 to 15 */ 2747 u8 flags; 2748 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2749 /* response flags */ 2750 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2751 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2752 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2753 u8 network_key_index; 2754 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2755 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2756 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2757 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2758 u8 reserved[10]; 2759 }; 2760 2761 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2762 2763 /* OEM mode commands (direct 0xFE0x) */ 2764 struct i40e_aqc_oem_param_change { 2765 __le32 param_type; 2766 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2767 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2768 #define I40E_AQ_OEM_PARAM_MAC 2 2769 __le32 param_value1; 2770 __le16 param_value2; 2771 u8 reserved[6]; 2772 }; 2773 2774 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2775 2776 struct i40e_aqc_oem_state_change { 2777 __le32 state; 2778 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2779 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2780 u8 reserved[12]; 2781 }; 2782 2783 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2784 2785 /* Initialize OCSD (0xFE02, direct) */ 2786 struct i40e_aqc_opc_oem_ocsd_initialize { 2787 u8 type_status; 2788 u8 reserved1[3]; 2789 __le32 ocsd_memory_block_addr_high; 2790 __le32 ocsd_memory_block_addr_low; 2791 __le32 requested_update_interval; 2792 }; 2793 2794 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2795 2796 /* Initialize OCBB (0xFE03, direct) */ 2797 struct i40e_aqc_opc_oem_ocbb_initialize { 2798 u8 type_status; 2799 u8 reserved1[3]; 2800 __le32 ocbb_memory_block_addr_high; 2801 __le32 ocbb_memory_block_addr_low; 2802 u8 reserved2[4]; 2803 }; 2804 2805 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2806 2807 /* debug commands */ 2808 2809 /* get device id (0xFF00) uses the generic structure */ 2810 2811 /* set test more (0xFF01, internal) */ 2812 2813 struct i40e_acq_set_test_mode { 2814 u8 mode; 2815 #define I40E_AQ_TEST_PARTIAL 0 2816 #define I40E_AQ_TEST_FULL 1 2817 #define I40E_AQ_TEST_NVM 2 2818 u8 reserved[3]; 2819 u8 command; 2820 #define I40E_AQ_TEST_OPEN 0 2821 #define I40E_AQ_TEST_CLOSE 1 2822 #define I40E_AQ_TEST_INC 2 2823 u8 reserved2[3]; 2824 __le32 address_high; 2825 __le32 address_low; 2826 }; 2827 2828 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2829 2830 /* Debug Read Register command (0xFF03) 2831 * Debug Write Register command (0xFF04) 2832 */ 2833 struct i40e_aqc_debug_reg_read_write { 2834 __le32 reserved; 2835 __le32 address; 2836 __le32 value_high; 2837 __le32 value_low; 2838 }; 2839 2840 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2841 2842 /* Scatter/gather Reg Read (indirect 0xFF05) 2843 * Scatter/gather Reg Write (indirect 0xFF06) 2844 */ 2845 2846 /* i40e_aq_desc is used for the command */ 2847 struct i40e_aqc_debug_reg_sg_element_data { 2848 __le32 address; 2849 __le32 value; 2850 }; 2851 2852 /* Debug Modify register (direct 0xFF07) */ 2853 struct i40e_aqc_debug_modify_reg { 2854 __le32 address; 2855 __le32 value; 2856 __le32 clear_mask; 2857 __le32 set_mask; 2858 }; 2859 2860 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2861 2862 /* dump internal data (0xFF08, indirect) */ 2863 2864 #define I40E_AQ_CLUSTER_ID_AUX 0 2865 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2866 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2867 #define I40E_AQ_CLUSTER_ID_HMC 3 2868 #define I40E_AQ_CLUSTER_ID_MAC0 4 2869 #define I40E_AQ_CLUSTER_ID_MAC1 5 2870 #define I40E_AQ_CLUSTER_ID_MAC2 6 2871 #define I40E_AQ_CLUSTER_ID_MAC3 7 2872 #define I40E_AQ_CLUSTER_ID_DCB 8 2873 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2874 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2875 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2876 2877 struct i40e_aqc_debug_dump_internals { 2878 u8 cluster_id; 2879 u8 table_id; 2880 __le16 data_size; 2881 __le32 idx; 2882 __le32 address_high; 2883 __le32 address_low; 2884 }; 2885 2886 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2887 2888 struct i40e_aqc_debug_modify_internals { 2889 u8 cluster_id; 2890 u8 cluster_specific_params[7]; 2891 __le32 address_high; 2892 __le32 address_low; 2893 }; 2894 2895 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2896 2897 #endif /* _I40E_ADMINQ_CMD_H_ */ 2898