1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_ADMINQ_CMD_H_ 5 #define _I40E_ADMINQ_CMD_H_ 6 7 /* This header file defines the i40e Admin Queue commands and is shared between 8 * i40e Firmware and Software. 9 * 10 * This file needs to comply with the Linux Kernel coding style. 11 */ 12 13 #define I40E_FW_API_VERSION_MAJOR 0x0001 14 #define I40E_FW_API_VERSION_MINOR_X722 0x0008 15 #define I40E_FW_API_VERSION_MINOR_X710 0x0008 16 17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 18 I40E_FW_API_VERSION_MINOR_X710 : \ 19 I40E_FW_API_VERSION_MINOR_X722) 20 21 /* API version 1.7 implements additional link and PHY-specific APIs */ 22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 23 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 24 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 25 26 struct i40e_aq_desc { 27 __le16 flags; 28 __le16 opcode; 29 __le16 datalen; 30 __le16 retval; 31 __le32 cookie_high; 32 __le32 cookie_low; 33 union { 34 struct { 35 __le32 param0; 36 __le32 param1; 37 __le32 param2; 38 __le32 param3; 39 } internal; 40 struct { 41 __le32 param0; 42 __le32 param1; 43 __le32 addr_high; 44 __le32 addr_low; 45 } external; 46 u8 raw[16]; 47 } params; 48 }; 49 50 /* Flags sub-structure 51 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 52 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 53 */ 54 55 /* command flags and offsets*/ 56 #define I40E_AQ_FLAG_DD_SHIFT 0 57 #define I40E_AQ_FLAG_CMP_SHIFT 1 58 #define I40E_AQ_FLAG_ERR_SHIFT 2 59 #define I40E_AQ_FLAG_VFE_SHIFT 3 60 #define I40E_AQ_FLAG_LB_SHIFT 9 61 #define I40E_AQ_FLAG_RD_SHIFT 10 62 #define I40E_AQ_FLAG_VFC_SHIFT 11 63 #define I40E_AQ_FLAG_BUF_SHIFT 12 64 #define I40E_AQ_FLAG_SI_SHIFT 13 65 #define I40E_AQ_FLAG_EI_SHIFT 14 66 #define I40E_AQ_FLAG_FE_SHIFT 15 67 68 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 69 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 70 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 71 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 72 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 73 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 74 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 75 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 76 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 77 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 78 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 79 80 /* error codes */ 81 enum i40e_admin_queue_err { 82 I40E_AQ_RC_OK = 0, /* success */ 83 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 84 I40E_AQ_RC_ENOENT = 2, /* No such element */ 85 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 86 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 87 I40E_AQ_RC_EIO = 5, /* I/O error */ 88 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 89 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 90 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 91 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 92 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 93 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 94 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 95 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 96 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 97 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 98 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 99 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 100 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 101 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 102 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 103 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 104 I40E_AQ_RC_EFBIG = 22, /* File too large */ 105 }; 106 107 /* Admin Queue command opcodes */ 108 enum i40e_admin_queue_opc { 109 /* aq commands */ 110 i40e_aqc_opc_get_version = 0x0001, 111 i40e_aqc_opc_driver_version = 0x0002, 112 i40e_aqc_opc_queue_shutdown = 0x0003, 113 i40e_aqc_opc_set_pf_context = 0x0004, 114 115 /* resource ownership */ 116 i40e_aqc_opc_request_resource = 0x0008, 117 i40e_aqc_opc_release_resource = 0x0009, 118 119 i40e_aqc_opc_list_func_capabilities = 0x000A, 120 i40e_aqc_opc_list_dev_capabilities = 0x000B, 121 122 /* Proxy commands */ 123 i40e_aqc_opc_set_proxy_config = 0x0104, 124 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 125 126 /* LAA */ 127 i40e_aqc_opc_mac_address_read = 0x0107, 128 i40e_aqc_opc_mac_address_write = 0x0108, 129 130 /* PXE */ 131 i40e_aqc_opc_clear_pxe_mode = 0x0110, 132 133 /* WoL commands */ 134 i40e_aqc_opc_set_wol_filter = 0x0120, 135 i40e_aqc_opc_get_wake_reason = 0x0121, 136 137 /* internal switch commands */ 138 i40e_aqc_opc_get_switch_config = 0x0200, 139 i40e_aqc_opc_add_statistics = 0x0201, 140 i40e_aqc_opc_remove_statistics = 0x0202, 141 i40e_aqc_opc_set_port_parameters = 0x0203, 142 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 143 i40e_aqc_opc_set_switch_config = 0x0205, 144 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 145 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 146 147 i40e_aqc_opc_add_vsi = 0x0210, 148 i40e_aqc_opc_update_vsi_parameters = 0x0211, 149 i40e_aqc_opc_get_vsi_parameters = 0x0212, 150 151 i40e_aqc_opc_add_pv = 0x0220, 152 i40e_aqc_opc_update_pv_parameters = 0x0221, 153 i40e_aqc_opc_get_pv_parameters = 0x0222, 154 155 i40e_aqc_opc_add_veb = 0x0230, 156 i40e_aqc_opc_update_veb_parameters = 0x0231, 157 i40e_aqc_opc_get_veb_parameters = 0x0232, 158 159 i40e_aqc_opc_delete_element = 0x0243, 160 161 i40e_aqc_opc_add_macvlan = 0x0250, 162 i40e_aqc_opc_remove_macvlan = 0x0251, 163 i40e_aqc_opc_add_vlan = 0x0252, 164 i40e_aqc_opc_remove_vlan = 0x0253, 165 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 166 i40e_aqc_opc_add_tag = 0x0255, 167 i40e_aqc_opc_remove_tag = 0x0256, 168 i40e_aqc_opc_add_multicast_etag = 0x0257, 169 i40e_aqc_opc_remove_multicast_etag = 0x0258, 170 i40e_aqc_opc_update_tag = 0x0259, 171 i40e_aqc_opc_add_control_packet_filter = 0x025A, 172 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 173 i40e_aqc_opc_add_cloud_filters = 0x025C, 174 i40e_aqc_opc_remove_cloud_filters = 0x025D, 175 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 176 177 i40e_aqc_opc_add_mirror_rule = 0x0260, 178 i40e_aqc_opc_delete_mirror_rule = 0x0261, 179 180 /* Dynamic Device Personalization */ 181 i40e_aqc_opc_write_personalization_profile = 0x0270, 182 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 183 184 /* DCB commands */ 185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 186 i40e_aqc_opc_dcb_updated = 0x0302, 187 i40e_aqc_opc_set_dcb_parameters = 0x0303, 188 189 /* TX scheduler */ 190 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 191 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 192 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 193 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 194 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 195 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 196 197 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 198 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 199 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 200 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 201 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 202 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 203 i40e_aqc_opc_query_port_ets_config = 0x0419, 204 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 205 i40e_aqc_opc_suspend_port_tx = 0x041B, 206 i40e_aqc_opc_resume_port_tx = 0x041C, 207 i40e_aqc_opc_configure_partition_bw = 0x041D, 208 /* hmc */ 209 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 210 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 211 212 /* phy commands*/ 213 i40e_aqc_opc_get_phy_abilities = 0x0600, 214 i40e_aqc_opc_set_phy_config = 0x0601, 215 i40e_aqc_opc_set_mac_config = 0x0603, 216 i40e_aqc_opc_set_link_restart_an = 0x0605, 217 i40e_aqc_opc_get_link_status = 0x0607, 218 i40e_aqc_opc_set_phy_int_mask = 0x0613, 219 i40e_aqc_opc_get_local_advt_reg = 0x0614, 220 i40e_aqc_opc_set_local_advt_reg = 0x0615, 221 i40e_aqc_opc_get_partner_advt = 0x0616, 222 i40e_aqc_opc_set_lb_modes = 0x0618, 223 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 224 i40e_aqc_opc_set_phy_debug = 0x0622, 225 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 226 i40e_aqc_opc_run_phy_activity = 0x0626, 227 i40e_aqc_opc_set_phy_register = 0x0628, 228 i40e_aqc_opc_get_phy_register = 0x0629, 229 230 /* NVM commands */ 231 i40e_aqc_opc_nvm_read = 0x0701, 232 i40e_aqc_opc_nvm_erase = 0x0702, 233 i40e_aqc_opc_nvm_update = 0x0703, 234 i40e_aqc_opc_nvm_config_read = 0x0704, 235 i40e_aqc_opc_nvm_config_write = 0x0705, 236 i40e_aqc_opc_oem_post_update = 0x0720, 237 i40e_aqc_opc_thermal_sensor = 0x0721, 238 239 /* virtualization commands */ 240 i40e_aqc_opc_send_msg_to_pf = 0x0801, 241 i40e_aqc_opc_send_msg_to_vf = 0x0802, 242 i40e_aqc_opc_send_msg_to_peer = 0x0803, 243 244 /* alternate structure */ 245 i40e_aqc_opc_alternate_write = 0x0900, 246 i40e_aqc_opc_alternate_write_indirect = 0x0901, 247 i40e_aqc_opc_alternate_read = 0x0902, 248 i40e_aqc_opc_alternate_read_indirect = 0x0903, 249 i40e_aqc_opc_alternate_write_done = 0x0904, 250 i40e_aqc_opc_alternate_set_mode = 0x0905, 251 i40e_aqc_opc_alternate_clear_port = 0x0906, 252 253 /* LLDP commands */ 254 i40e_aqc_opc_lldp_get_mib = 0x0A00, 255 i40e_aqc_opc_lldp_update_mib = 0x0A01, 256 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 257 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 258 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 259 i40e_aqc_opc_lldp_stop = 0x0A05, 260 i40e_aqc_opc_lldp_start = 0x0A06, 261 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 262 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 263 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 264 265 /* Tunnel commands */ 266 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 267 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 268 i40e_aqc_opc_set_rss_key = 0x0B02, 269 i40e_aqc_opc_set_rss_lut = 0x0B03, 270 i40e_aqc_opc_get_rss_key = 0x0B04, 271 i40e_aqc_opc_get_rss_lut = 0x0B05, 272 273 /* Async Events */ 274 i40e_aqc_opc_event_lan_overflow = 0x1001, 275 276 /* OEM commands */ 277 i40e_aqc_opc_oem_parameter_change = 0xFE00, 278 i40e_aqc_opc_oem_device_status_change = 0xFE01, 279 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 280 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 281 282 /* debug commands */ 283 i40e_aqc_opc_debug_read_reg = 0xFF03, 284 i40e_aqc_opc_debug_write_reg = 0xFF04, 285 i40e_aqc_opc_debug_modify_reg = 0xFF07, 286 i40e_aqc_opc_debug_dump_internals = 0xFF08, 287 }; 288 289 /* command structures and indirect data structures */ 290 291 /* Structure naming conventions: 292 * - no suffix for direct command descriptor structures 293 * - _data for indirect sent data 294 * - _resp for indirect return data (data which is both will use _data) 295 * - _completion for direct return data 296 * - _element_ for repeated elements (may also be _data or _resp) 297 * 298 * Command structures are expected to overlay the params.raw member of the basic 299 * descriptor, and as such cannot exceed 16 bytes in length. 300 */ 301 302 /* This macro is used to generate a compilation error if a structure 303 * is not exactly the correct length. It gives a divide by zero error if the 304 * structure is not of the correct size, otherwise it creates an enum that is 305 * never used. 306 */ 307 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 308 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 309 310 /* This macro is used extensively to ensure that command structures are 16 311 * bytes in length as they have to map to the raw array of that size. 312 */ 313 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 314 315 /* internal (0x00XX) commands */ 316 317 /* Get version (direct 0x0001) */ 318 struct i40e_aqc_get_version { 319 __le32 rom_ver; 320 __le32 fw_build; 321 __le16 fw_major; 322 __le16 fw_minor; 323 __le16 api_major; 324 __le16 api_minor; 325 }; 326 327 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 328 329 /* Send driver version (indirect 0x0002) */ 330 struct i40e_aqc_driver_version { 331 u8 driver_major_ver; 332 u8 driver_minor_ver; 333 u8 driver_build_ver; 334 u8 driver_subbuild_ver; 335 u8 reserved[4]; 336 __le32 address_high; 337 __le32 address_low; 338 }; 339 340 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 341 342 /* Queue Shutdown (direct 0x0003) */ 343 struct i40e_aqc_queue_shutdown { 344 __le32 driver_unloading; 345 #define I40E_AQ_DRIVER_UNLOADING 0x1 346 u8 reserved[12]; 347 }; 348 349 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 350 351 /* Set PF context (0x0004, direct) */ 352 struct i40e_aqc_set_pf_context { 353 u8 pf_id; 354 u8 reserved[15]; 355 }; 356 357 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 358 359 /* Request resource ownership (direct 0x0008) 360 * Release resource ownership (direct 0x0009) 361 */ 362 #define I40E_AQ_RESOURCE_NVM 1 363 #define I40E_AQ_RESOURCE_SDP 2 364 #define I40E_AQ_RESOURCE_ACCESS_READ 1 365 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 366 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 367 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 368 369 struct i40e_aqc_request_resource { 370 __le16 resource_id; 371 __le16 access_type; 372 __le32 timeout; 373 __le32 resource_number; 374 u8 reserved[4]; 375 }; 376 377 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 378 379 /* Get function capabilities (indirect 0x000A) 380 * Get device capabilities (indirect 0x000B) 381 */ 382 struct i40e_aqc_list_capabilites { 383 u8 command_flags; 384 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 385 u8 pf_index; 386 u8 reserved[2]; 387 __le32 count; 388 __le32 addr_high; 389 __le32 addr_low; 390 }; 391 392 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 393 394 struct i40e_aqc_list_capabilities_element_resp { 395 __le16 id; 396 u8 major_rev; 397 u8 minor_rev; 398 __le32 number; 399 __le32 logical_id; 400 __le32 phys_id; 401 u8 reserved[16]; 402 }; 403 404 /* list of caps */ 405 406 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 407 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 408 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 409 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 410 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 411 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 412 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 413 #define I40E_AQ_CAP_ID_SRIOV 0x0012 414 #define I40E_AQ_CAP_ID_VF 0x0013 415 #define I40E_AQ_CAP_ID_VMDQ 0x0014 416 #define I40E_AQ_CAP_ID_8021QBG 0x0015 417 #define I40E_AQ_CAP_ID_8021QBR 0x0016 418 #define I40E_AQ_CAP_ID_VSI 0x0017 419 #define I40E_AQ_CAP_ID_DCB 0x0018 420 #define I40E_AQ_CAP_ID_FCOE 0x0021 421 #define I40E_AQ_CAP_ID_ISCSI 0x0022 422 #define I40E_AQ_CAP_ID_RSS 0x0040 423 #define I40E_AQ_CAP_ID_RXQ 0x0041 424 #define I40E_AQ_CAP_ID_TXQ 0x0042 425 #define I40E_AQ_CAP_ID_MSIX 0x0043 426 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 427 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 428 #define I40E_AQ_CAP_ID_1588 0x0046 429 #define I40E_AQ_CAP_ID_IWARP 0x0051 430 #define I40E_AQ_CAP_ID_LED 0x0061 431 #define I40E_AQ_CAP_ID_SDP 0x0062 432 #define I40E_AQ_CAP_ID_MDIO 0x0063 433 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 434 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 435 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 436 #define I40E_AQ_CAP_ID_CEM 0x00F2 437 438 /* Set CPPM Configuration (direct 0x0103) */ 439 struct i40e_aqc_cppm_configuration { 440 __le16 command_flags; 441 #define I40E_AQ_CPPM_EN_LTRC 0x0800 442 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 443 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 444 #define I40E_AQ_CPPM_EN_HPTC 0x4000 445 #define I40E_AQ_CPPM_EN_DMARC 0x8000 446 __le16 ttlx; 447 __le32 dmacr; 448 __le16 dmcth; 449 u8 hptc; 450 u8 reserved; 451 __le32 pfltrc; 452 }; 453 454 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 455 456 /* Set ARP Proxy command / response (indirect 0x0104) */ 457 struct i40e_aqc_arp_proxy_data { 458 __le16 command_flags; 459 #define I40E_AQ_ARP_INIT_IPV4 0x0800 460 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 461 #define I40E_AQ_ARP_ENA 0x2000 462 #define I40E_AQ_ARP_ADD_IPV4 0x4000 463 #define I40E_AQ_ARP_DEL_IPV4 0x8000 464 __le16 table_id; 465 __le32 enabled_offloads; 466 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 467 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 468 __le32 ip_addr; 469 u8 mac_addr[6]; 470 u8 reserved[2]; 471 }; 472 473 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 474 475 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 476 struct i40e_aqc_ns_proxy_data { 477 __le16 table_idx_mac_addr_0; 478 __le16 table_idx_mac_addr_1; 479 __le16 table_idx_ipv6_0; 480 __le16 table_idx_ipv6_1; 481 __le16 control; 482 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 483 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 484 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 485 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 486 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 487 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 488 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 489 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 490 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 491 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 492 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 493 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 494 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 495 u8 mac_addr_0[6]; 496 u8 mac_addr_1[6]; 497 u8 local_mac_addr[6]; 498 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 499 u8 ipv6_addr_1[16]; 500 }; 501 502 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 503 504 /* Manage LAA Command (0x0106) - obsolete */ 505 struct i40e_aqc_mng_laa { 506 __le16 command_flags; 507 #define I40E_AQ_LAA_FLAG_WR 0x8000 508 u8 reserved[2]; 509 __le32 sal; 510 __le16 sah; 511 u8 reserved2[6]; 512 }; 513 514 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 515 516 /* Manage MAC Address Read Command (indirect 0x0107) */ 517 struct i40e_aqc_mac_address_read { 518 __le16 command_flags; 519 #define I40E_AQC_LAN_ADDR_VALID 0x10 520 #define I40E_AQC_SAN_ADDR_VALID 0x20 521 #define I40E_AQC_PORT_ADDR_VALID 0x40 522 #define I40E_AQC_WOL_ADDR_VALID 0x80 523 #define I40E_AQC_MC_MAG_EN_VALID 0x100 524 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 525 u8 reserved[6]; 526 __le32 addr_high; 527 __le32 addr_low; 528 }; 529 530 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 531 532 struct i40e_aqc_mac_address_read_data { 533 u8 pf_lan_mac[6]; 534 u8 pf_san_mac[6]; 535 u8 port_mac[6]; 536 u8 pf_wol_mac[6]; 537 }; 538 539 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 540 541 /* Manage MAC Address Write Command (0x0108) */ 542 struct i40e_aqc_mac_address_write { 543 __le16 command_flags; 544 #define I40E_AQC_MC_MAG_EN 0x0100 545 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 546 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 547 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 548 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 549 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 550 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 551 552 __le16 mac_sah; 553 __le32 mac_sal; 554 u8 reserved[8]; 555 }; 556 557 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 558 559 /* PXE commands (0x011x) */ 560 561 /* Clear PXE Command and response (direct 0x0110) */ 562 struct i40e_aqc_clear_pxe { 563 u8 rx_cnt; 564 u8 reserved[15]; 565 }; 566 567 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 568 569 /* Set WoL Filter (0x0120) */ 570 571 struct i40e_aqc_set_wol_filter { 572 __le16 filter_index; 573 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 574 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 575 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 576 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 577 578 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 579 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 580 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 581 __le16 cmd_flags; 582 #define I40E_AQC_SET_WOL_FILTER 0x8000 583 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 584 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 585 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 586 __le16 valid_flags; 587 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 588 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 589 u8 reserved[2]; 590 __le32 address_high; 591 __le32 address_low; 592 }; 593 594 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 595 596 struct i40e_aqc_set_wol_filter_data { 597 u8 filter[128]; 598 u8 mask[16]; 599 }; 600 601 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 602 603 /* Get Wake Reason (0x0121) */ 604 605 struct i40e_aqc_get_wake_reason_completion { 606 u8 reserved_1[2]; 607 __le16 wake_reason; 608 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 609 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 610 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 611 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 612 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 613 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 614 u8 reserved_2[12]; 615 }; 616 617 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 618 619 /* Switch configuration commands (0x02xx) */ 620 621 /* Used by many indirect commands that only pass an seid and a buffer in the 622 * command 623 */ 624 struct i40e_aqc_switch_seid { 625 __le16 seid; 626 u8 reserved[6]; 627 __le32 addr_high; 628 __le32 addr_low; 629 }; 630 631 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 632 633 /* Get Switch Configuration command (indirect 0x0200) 634 * uses i40e_aqc_switch_seid for the descriptor 635 */ 636 struct i40e_aqc_get_switch_config_header_resp { 637 __le16 num_reported; 638 __le16 num_total; 639 u8 reserved[12]; 640 }; 641 642 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 643 644 struct i40e_aqc_switch_config_element_resp { 645 u8 element_type; 646 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 647 #define I40E_AQ_SW_ELEM_TYPE_PF 2 648 #define I40E_AQ_SW_ELEM_TYPE_VF 3 649 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 650 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 651 #define I40E_AQ_SW_ELEM_TYPE_PV 16 652 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 653 #define I40E_AQ_SW_ELEM_TYPE_PA 18 654 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 655 u8 revision; 656 #define I40E_AQ_SW_ELEM_REV_1 1 657 __le16 seid; 658 __le16 uplink_seid; 659 __le16 downlink_seid; 660 u8 reserved[3]; 661 u8 connection_type; 662 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 663 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 664 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 665 __le16 scheduler_id; 666 __le16 element_info; 667 }; 668 669 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 670 671 /* Get Switch Configuration (indirect 0x0200) 672 * an array of elements are returned in the response buffer 673 * the first in the array is the header, remainder are elements 674 */ 675 struct i40e_aqc_get_switch_config_resp { 676 struct i40e_aqc_get_switch_config_header_resp header; 677 struct i40e_aqc_switch_config_element_resp element[1]; 678 }; 679 680 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 681 682 /* Add Statistics (direct 0x0201) 683 * Remove Statistics (direct 0x0202) 684 */ 685 struct i40e_aqc_add_remove_statistics { 686 __le16 seid; 687 __le16 vlan; 688 __le16 stat_index; 689 u8 reserved[10]; 690 }; 691 692 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 693 694 /* Set Port Parameters command (direct 0x0203) */ 695 struct i40e_aqc_set_port_parameters { 696 __le16 command_flags; 697 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 698 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 699 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 700 __le16 bad_frame_vsi; 701 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 702 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 703 __le16 default_seid; /* reserved for command */ 704 u8 reserved[10]; 705 }; 706 707 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 708 709 /* Get Switch Resource Allocation (indirect 0x0204) */ 710 struct i40e_aqc_get_switch_resource_alloc { 711 u8 num_entries; /* reserved for command */ 712 u8 reserved[7]; 713 __le32 addr_high; 714 __le32 addr_low; 715 }; 716 717 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 718 719 /* expect an array of these structs in the response buffer */ 720 struct i40e_aqc_switch_resource_alloc_element_resp { 721 u8 resource_type; 722 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 723 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 724 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 725 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 726 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 727 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 728 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 729 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 730 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 731 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 732 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 733 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 734 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 735 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 736 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 737 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 738 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 739 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 740 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 741 u8 reserved1; 742 __le16 guaranteed; 743 __le16 total; 744 __le16 used; 745 __le16 total_unalloced; 746 u8 reserved2[6]; 747 }; 748 749 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 750 751 /* Set Switch Configuration (direct 0x0205) */ 752 struct i40e_aqc_set_switch_config { 753 __le16 flags; 754 /* flags used for both fields below */ 755 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 756 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 757 __le16 valid_flags; 758 /* The ethertype in switch_tag is dropped on ingress and used 759 * internally by the switch. Set this to zero for the default 760 * of 0x88a8 (802.1ad). Should be zero for firmware API 761 * versions lower than 1.7. 762 */ 763 __le16 switch_tag; 764 /* The ethertypes in first_tag and second_tag are used to 765 * match the outer and inner VLAN tags (respectively) when HW 766 * double VLAN tagging is enabled via the set port parameters 767 * AQ command. Otherwise these are both ignored. Set them to 768 * zero for their defaults of 0x8100 (802.1Q). Should be zero 769 * for firmware API versions lower than 1.7. 770 */ 771 __le16 first_tag; 772 __le16 second_tag; 773 /* Next byte is split into following: 774 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 775 * Bit 6 : 0 : Destination Port, 1: source port 776 * Bit 5..4 : L4 type 777 * 0: rsvd 778 * 1: TCP 779 * 2: UDP 780 * 3: Both TCP and UDP 781 * Bits 3:0 Mode 782 * 0: default mode 783 * 1: L4 port only mode 784 * 2: non-tunneled mode 785 * 3: tunneled mode 786 */ 787 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 788 789 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 790 791 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 792 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 793 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 794 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 795 796 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 797 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 798 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 799 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 800 u8 mode; 801 u8 rsvd5[5]; 802 }; 803 804 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 805 806 /* Read Receive control registers (direct 0x0206) 807 * Write Receive control registers (direct 0x0207) 808 * used for accessing Rx control registers that can be 809 * slow and need special handling when under high Rx load 810 */ 811 struct i40e_aqc_rx_ctl_reg_read_write { 812 __le32 reserved1; 813 __le32 address; 814 __le32 reserved2; 815 __le32 value; 816 }; 817 818 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 819 820 /* Add VSI (indirect 0x0210) 821 * this indirect command uses struct i40e_aqc_vsi_properties_data 822 * as the indirect buffer (128 bytes) 823 * 824 * Update VSI (indirect 0x211) 825 * uses the same data structure as Add VSI 826 * 827 * Get VSI (indirect 0x0212) 828 * uses the same completion and data structure as Add VSI 829 */ 830 struct i40e_aqc_add_get_update_vsi { 831 __le16 uplink_seid; 832 u8 connection_type; 833 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 834 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 835 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 836 u8 reserved1; 837 u8 vf_id; 838 u8 reserved2; 839 __le16 vsi_flags; 840 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 841 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 842 #define I40E_AQ_VSI_TYPE_VF 0x0 843 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 844 #define I40E_AQ_VSI_TYPE_PF 0x2 845 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 846 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 847 __le32 addr_high; 848 __le32 addr_low; 849 }; 850 851 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 852 853 struct i40e_aqc_add_get_update_vsi_completion { 854 __le16 seid; 855 __le16 vsi_number; 856 __le16 vsi_used; 857 __le16 vsi_free; 858 __le32 addr_high; 859 __le32 addr_low; 860 }; 861 862 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 863 864 struct i40e_aqc_vsi_properties_data { 865 /* first 96 byte are written by SW */ 866 __le16 valid_sections; 867 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 868 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 869 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 870 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 871 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 872 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 873 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 874 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 875 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 876 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 877 /* switch section */ 878 __le16 switch_id; /* 12bit id combined with flags below */ 879 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 880 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 881 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 882 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 883 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 884 u8 sw_reserved[2]; 885 /* security section */ 886 u8 sec_flags; 887 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 888 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 889 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 890 u8 sec_reserved; 891 /* VLAN section */ 892 __le16 pvid; /* VLANS include priority bits */ 893 __le16 fcoe_pvid; 894 u8 port_vlan_flags; 895 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 896 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 897 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 898 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 899 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 900 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 901 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 902 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 903 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 904 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 905 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 906 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 907 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 908 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 909 u8 pvlan_reserved[3]; 910 /* ingress egress up sections */ 911 __le32 ingress_table; /* bitmap, 3 bits per up */ 912 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 913 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 914 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 915 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 916 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 917 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 918 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 919 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 920 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 921 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 922 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 923 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 924 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 925 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 926 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 927 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 928 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 929 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 930 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 931 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 932 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 933 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 934 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 935 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 936 __le32 egress_table; /* same defines as for ingress table */ 937 /* cascaded PV section */ 938 __le16 cas_pv_tag; 939 u8 cas_pv_flags; 940 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 941 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 942 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 943 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 944 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 945 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 946 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 947 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 948 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 949 u8 cas_pv_reserved; 950 /* queue mapping section */ 951 __le16 mapping_flags; 952 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 953 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 954 __le16 queue_mapping[16]; 955 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 956 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 957 __le16 tc_mapping[8]; 958 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 959 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 960 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 961 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 962 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 963 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 964 /* queueing option section */ 965 u8 queueing_opt_flags; 966 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 967 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 968 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 969 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 970 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 971 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 972 u8 queueing_opt_reserved[3]; 973 /* scheduler section */ 974 u8 up_enable_bits; 975 u8 sched_reserved; 976 /* outer up section */ 977 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 978 u8 cmd_reserved[8]; 979 /* last 32 bytes are written by FW */ 980 __le16 qs_handle[8]; 981 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 982 __le16 stat_counter_idx; 983 __le16 sched_id; 984 u8 resp_reserved[12]; 985 }; 986 987 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 988 989 /* Add Port Virtualizer (direct 0x0220) 990 * also used for update PV (direct 0x0221) but only flags are used 991 * (IS_CTRL_PORT only works on add PV) 992 */ 993 struct i40e_aqc_add_update_pv { 994 __le16 command_flags; 995 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 996 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 997 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 998 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 999 __le16 uplink_seid; 1000 __le16 connected_seid; 1001 u8 reserved[10]; 1002 }; 1003 1004 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1005 1006 struct i40e_aqc_add_update_pv_completion { 1007 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1008 __le16 pv_seid; 1009 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1010 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1011 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1012 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1013 u8 reserved[14]; 1014 }; 1015 1016 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1017 1018 /* Get PV Params (direct 0x0222) 1019 * uses i40e_aqc_switch_seid for the descriptor 1020 */ 1021 1022 struct i40e_aqc_get_pv_params_completion { 1023 __le16 seid; 1024 __le16 default_stag; 1025 __le16 pv_flags; /* same flags as add_pv */ 1026 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1027 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1028 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1029 u8 reserved[8]; 1030 __le16 default_port_seid; 1031 }; 1032 1033 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1034 1035 /* Add VEB (direct 0x0230) */ 1036 struct i40e_aqc_add_veb { 1037 __le16 uplink_seid; 1038 __le16 downlink_seid; 1039 __le16 veb_flags; 1040 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1041 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1042 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1043 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1044 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1045 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1046 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1047 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1048 u8 enable_tcs; 1049 u8 reserved[9]; 1050 }; 1051 1052 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1053 1054 struct i40e_aqc_add_veb_completion { 1055 u8 reserved[6]; 1056 __le16 switch_seid; 1057 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1058 __le16 veb_seid; 1059 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1060 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1061 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1062 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1063 __le16 statistic_index; 1064 __le16 vebs_used; 1065 __le16 vebs_free; 1066 }; 1067 1068 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1069 1070 /* Get VEB Parameters (direct 0x0232) 1071 * uses i40e_aqc_switch_seid for the descriptor 1072 */ 1073 struct i40e_aqc_get_veb_parameters_completion { 1074 __le16 seid; 1075 __le16 switch_id; 1076 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1077 __le16 statistic_index; 1078 __le16 vebs_used; 1079 __le16 vebs_free; 1080 u8 reserved[4]; 1081 }; 1082 1083 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1084 1085 /* Delete Element (direct 0x0243) 1086 * uses the generic i40e_aqc_switch_seid 1087 */ 1088 1089 /* Add MAC-VLAN (indirect 0x0250) */ 1090 1091 /* used for the command for most vlan commands */ 1092 struct i40e_aqc_macvlan { 1093 __le16 num_addresses; 1094 __le16 seid[3]; 1095 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1096 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1097 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1098 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1099 __le32 addr_high; 1100 __le32 addr_low; 1101 }; 1102 1103 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1104 1105 /* indirect data for command and response */ 1106 struct i40e_aqc_add_macvlan_element_data { 1107 u8 mac_addr[6]; 1108 __le16 vlan_tag; 1109 __le16 flags; 1110 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1111 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1112 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1113 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1114 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1115 __le16 queue_number; 1116 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1117 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1118 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1119 /* response section */ 1120 u8 match_method; 1121 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1122 #define I40E_AQC_MM_HASH_MATCH 0x02 1123 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1124 u8 reserved1[3]; 1125 }; 1126 1127 struct i40e_aqc_add_remove_macvlan_completion { 1128 __le16 perfect_mac_used; 1129 __le16 perfect_mac_free; 1130 __le16 unicast_hash_free; 1131 __le16 multicast_hash_free; 1132 __le32 addr_high; 1133 __le32 addr_low; 1134 }; 1135 1136 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1137 1138 /* Remove MAC-VLAN (indirect 0x0251) 1139 * uses i40e_aqc_macvlan for the descriptor 1140 * data points to an array of num_addresses of elements 1141 */ 1142 1143 struct i40e_aqc_remove_macvlan_element_data { 1144 u8 mac_addr[6]; 1145 __le16 vlan_tag; 1146 u8 flags; 1147 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1148 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1149 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1150 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1151 u8 reserved[3]; 1152 /* reply section */ 1153 u8 error_code; 1154 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1155 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1156 u8 reply_reserved[3]; 1157 }; 1158 1159 /* Add VLAN (indirect 0x0252) 1160 * Remove VLAN (indirect 0x0253) 1161 * use the generic i40e_aqc_macvlan for the command 1162 */ 1163 struct i40e_aqc_add_remove_vlan_element_data { 1164 __le16 vlan_tag; 1165 u8 vlan_flags; 1166 /* flags for add VLAN */ 1167 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1168 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1169 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1170 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1171 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1172 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1173 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1174 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1175 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1176 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1177 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1178 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1179 /* flags for remove VLAN */ 1180 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1181 u8 reserved; 1182 u8 result; 1183 /* flags for add VLAN */ 1184 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1185 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1186 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1187 /* flags for remove VLAN */ 1188 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1189 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1190 u8 reserved1[3]; 1191 }; 1192 1193 struct i40e_aqc_add_remove_vlan_completion { 1194 u8 reserved[4]; 1195 __le16 vlans_used; 1196 __le16 vlans_free; 1197 __le32 addr_high; 1198 __le32 addr_low; 1199 }; 1200 1201 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1202 struct i40e_aqc_set_vsi_promiscuous_modes { 1203 __le16 promiscuous_flags; 1204 __le16 valid_flags; 1205 /* flags used for both fields above */ 1206 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1207 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1208 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1209 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1210 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1211 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1212 __le16 seid; 1213 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1214 __le16 vlan_tag; 1215 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1216 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1217 u8 reserved[8]; 1218 }; 1219 1220 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1221 1222 /* Add S/E-tag command (direct 0x0255) 1223 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1224 */ 1225 struct i40e_aqc_add_tag { 1226 __le16 flags; 1227 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1228 __le16 seid; 1229 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1230 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1231 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1232 __le16 tag; 1233 __le16 queue_number; 1234 u8 reserved[8]; 1235 }; 1236 1237 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1238 1239 struct i40e_aqc_add_remove_tag_completion { 1240 u8 reserved[12]; 1241 __le16 tags_used; 1242 __le16 tags_free; 1243 }; 1244 1245 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1246 1247 /* Remove S/E-tag command (direct 0x0256) 1248 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1249 */ 1250 struct i40e_aqc_remove_tag { 1251 __le16 seid; 1252 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1253 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1254 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1255 __le16 tag; 1256 u8 reserved[12]; 1257 }; 1258 1259 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1260 1261 /* Add multicast E-Tag (direct 0x0257) 1262 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1263 * and no external data 1264 */ 1265 struct i40e_aqc_add_remove_mcast_etag { 1266 __le16 pv_seid; 1267 __le16 etag; 1268 u8 num_unicast_etags; 1269 u8 reserved[3]; 1270 __le32 addr_high; /* address of array of 2-byte s-tags */ 1271 __le32 addr_low; 1272 }; 1273 1274 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1275 1276 struct i40e_aqc_add_remove_mcast_etag_completion { 1277 u8 reserved[4]; 1278 __le16 mcast_etags_used; 1279 __le16 mcast_etags_free; 1280 __le32 addr_high; 1281 __le32 addr_low; 1282 1283 }; 1284 1285 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1286 1287 /* Update S/E-Tag (direct 0x0259) */ 1288 struct i40e_aqc_update_tag { 1289 __le16 seid; 1290 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1291 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1292 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1293 __le16 old_tag; 1294 __le16 new_tag; 1295 u8 reserved[10]; 1296 }; 1297 1298 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1299 1300 struct i40e_aqc_update_tag_completion { 1301 u8 reserved[12]; 1302 __le16 tags_used; 1303 __le16 tags_free; 1304 }; 1305 1306 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1307 1308 /* Add Control Packet filter (direct 0x025A) 1309 * Remove Control Packet filter (direct 0x025B) 1310 * uses the i40e_aqc_add_oveb_cloud, 1311 * and the generic direct completion structure 1312 */ 1313 struct i40e_aqc_add_remove_control_packet_filter { 1314 u8 mac[6]; 1315 __le16 etype; 1316 __le16 flags; 1317 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1318 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1319 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1320 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1321 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1322 __le16 seid; 1323 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1324 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1325 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1326 __le16 queue; 1327 u8 reserved[2]; 1328 }; 1329 1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1331 1332 struct i40e_aqc_add_remove_control_packet_filter_completion { 1333 __le16 mac_etype_used; 1334 __le16 etype_used; 1335 __le16 mac_etype_free; 1336 __le16 etype_free; 1337 u8 reserved[8]; 1338 }; 1339 1340 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1341 1342 /* Add Cloud filters (indirect 0x025C) 1343 * Remove Cloud filters (indirect 0x025D) 1344 * uses the i40e_aqc_add_remove_cloud_filters, 1345 * and the generic indirect completion structure 1346 */ 1347 struct i40e_aqc_add_remove_cloud_filters { 1348 u8 num_filters; 1349 u8 reserved; 1350 __le16 seid; 1351 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1352 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1353 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1354 u8 big_buffer_flag; 1355 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1356 u8 reserved2[3]; 1357 __le32 addr_high; 1358 __le32 addr_low; 1359 }; 1360 1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1362 1363 struct i40e_aqc_cloud_filters_element_data { 1364 u8 outer_mac[6]; 1365 u8 inner_mac[6]; 1366 __le16 inner_vlan; 1367 union { 1368 struct { 1369 u8 reserved[12]; 1370 u8 data[4]; 1371 } v4; 1372 struct { 1373 u8 data[16]; 1374 } v6; 1375 struct { 1376 __le16 data[8]; 1377 } raw_v6; 1378 } ipaddr; 1379 __le16 flags; 1380 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1381 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1382 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1383 /* 0x0000 reserved */ 1384 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1385 /* 0x0002 reserved */ 1386 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1387 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1388 /* 0x0005 reserved */ 1389 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1390 /* 0x0007 reserved */ 1391 /* 0x0008 reserved */ 1392 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1393 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1394 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1395 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1396 /* 0x0010 to 0x0017 is for custom filters */ 1397 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1398 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1399 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1400 1401 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1402 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1403 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1404 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1405 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1406 1407 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1408 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1409 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1413 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1414 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1415 1416 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1417 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1418 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1419 1420 __le32 tenant_id; 1421 u8 reserved[4]; 1422 __le16 queue_number; 1423 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1424 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1425 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1426 u8 reserved2[14]; 1427 /* response section */ 1428 u8 allocation_result; 1429 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1430 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1431 u8 response_reserved[7]; 1432 }; 1433 1434 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1435 1436 /* i40e_aqc_cloud_filters_element_bb is used when 1437 * I40E_AQC_CLOUD_CMD_BB flag is set. 1438 */ 1439 struct i40e_aqc_cloud_filters_element_bb { 1440 struct i40e_aqc_cloud_filters_element_data element; 1441 u16 general_fields[32]; 1442 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1443 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1444 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1445 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1446 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1471 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1472 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1473 }; 1474 1475 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1476 1477 struct i40e_aqc_remove_cloud_filters_completion { 1478 __le16 perfect_ovlan_used; 1479 __le16 perfect_ovlan_free; 1480 __le16 vlan_used; 1481 __le16 vlan_free; 1482 __le32 addr_high; 1483 __le32 addr_low; 1484 }; 1485 1486 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1487 1488 /* Replace filter Command 0x025F 1489 * uses the i40e_aqc_replace_cloud_filters, 1490 * and the generic indirect completion structure 1491 */ 1492 struct i40e_filter_data { 1493 u8 filter_type; 1494 u8 input[3]; 1495 }; 1496 1497 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1498 1499 struct i40e_aqc_replace_cloud_filters_cmd { 1500 u8 valid_flags; 1501 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1502 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1503 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1504 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1505 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1506 u8 old_filter_type; 1507 u8 new_filter_type; 1508 u8 tr_bit; 1509 u8 reserved[4]; 1510 __le32 addr_high; 1511 __le32 addr_low; 1512 }; 1513 1514 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1515 1516 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1517 u8 data[32]; 1518 /* Filter type INPUT codes*/ 1519 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1520 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1521 1522 /* Field Vector offsets */ 1523 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1524 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1526 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1527 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1528 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1529 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1530 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1531 /* big FLU */ 1532 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1533 /* big FLU */ 1534 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1535 1536 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1537 struct i40e_filter_data filters[8]; 1538 }; 1539 1540 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1541 1542 /* Add Mirror Rule (indirect or direct 0x0260) 1543 * Delete Mirror Rule (indirect or direct 0x0261) 1544 * note: some rule types (4,5) do not use an external buffer. 1545 * take care to set the flags correctly. 1546 */ 1547 struct i40e_aqc_add_delete_mirror_rule { 1548 __le16 seid; 1549 __le16 rule_type; 1550 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1551 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1552 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1553 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1554 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1555 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1556 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1557 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1558 __le16 num_entries; 1559 __le16 destination; /* VSI for add, rule id for delete */ 1560 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1561 __le32 addr_low; 1562 }; 1563 1564 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1565 1566 struct i40e_aqc_add_delete_mirror_rule_completion { 1567 u8 reserved[2]; 1568 __le16 rule_id; /* only used on add */ 1569 __le16 mirror_rules_used; 1570 __le16 mirror_rules_free; 1571 __le32 addr_high; 1572 __le32 addr_low; 1573 }; 1574 1575 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1576 1577 /* Dynamic Device Personalization */ 1578 struct i40e_aqc_write_personalization_profile { 1579 u8 flags; 1580 u8 reserved[3]; 1581 __le32 profile_track_id; 1582 __le32 addr_high; 1583 __le32 addr_low; 1584 }; 1585 1586 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1587 1588 struct i40e_aqc_write_ddp_resp { 1589 __le32 error_offset; 1590 __le32 error_info; 1591 __le32 addr_high; 1592 __le32 addr_low; 1593 }; 1594 1595 struct i40e_aqc_get_applied_profiles { 1596 u8 flags; 1597 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1598 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1599 u8 rsv[3]; 1600 __le32 reserved; 1601 __le32 addr_high; 1602 __le32 addr_low; 1603 }; 1604 1605 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1606 1607 /* DCB 0x03xx*/ 1608 1609 /* PFC Ignore (direct 0x0301) 1610 * the command and response use the same descriptor structure 1611 */ 1612 struct i40e_aqc_pfc_ignore { 1613 u8 tc_bitmap; 1614 u8 command_flags; /* unused on response */ 1615 #define I40E_AQC_PFC_IGNORE_SET 0x80 1616 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1617 u8 reserved[14]; 1618 }; 1619 1620 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1621 1622 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1623 * with no parameters 1624 */ 1625 1626 /* TX scheduler 0x04xx */ 1627 1628 /* Almost all the indirect commands use 1629 * this generic struct to pass the SEID in param0 1630 */ 1631 struct i40e_aqc_tx_sched_ind { 1632 __le16 vsi_seid; 1633 u8 reserved[6]; 1634 __le32 addr_high; 1635 __le32 addr_low; 1636 }; 1637 1638 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1639 1640 /* Several commands respond with a set of queue set handles */ 1641 struct i40e_aqc_qs_handles_resp { 1642 __le16 qs_handles[8]; 1643 }; 1644 1645 /* Configure VSI BW limits (direct 0x0400) */ 1646 struct i40e_aqc_configure_vsi_bw_limit { 1647 __le16 vsi_seid; 1648 u8 reserved[2]; 1649 __le16 credit; 1650 u8 reserved1[2]; 1651 u8 max_credit; /* 0-3, limit = 2^max */ 1652 u8 reserved2[7]; 1653 }; 1654 1655 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1656 1657 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1658 * responds with i40e_aqc_qs_handles_resp 1659 */ 1660 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1661 u8 tc_valid_bits; 1662 u8 reserved[15]; 1663 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1664 1665 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1666 __le16 tc_bw_max[2]; 1667 u8 reserved1[28]; 1668 }; 1669 1670 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1671 1672 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1673 * responds with i40e_aqc_qs_handles_resp 1674 */ 1675 struct i40e_aqc_configure_vsi_tc_bw_data { 1676 u8 tc_valid_bits; 1677 u8 reserved[3]; 1678 u8 tc_bw_credits[8]; 1679 u8 reserved1[4]; 1680 __le16 qs_handles[8]; 1681 }; 1682 1683 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1684 1685 /* Query vsi bw configuration (indirect 0x0408) */ 1686 struct i40e_aqc_query_vsi_bw_config_resp { 1687 u8 tc_valid_bits; 1688 u8 tc_suspended_bits; 1689 u8 reserved[14]; 1690 __le16 qs_handles[8]; 1691 u8 reserved1[4]; 1692 __le16 port_bw_limit; 1693 u8 reserved2[2]; 1694 u8 max_bw; /* 0-3, limit = 2^max */ 1695 u8 reserved3[23]; 1696 }; 1697 1698 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1699 1700 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1701 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1702 u8 tc_valid_bits; 1703 u8 reserved[3]; 1704 u8 share_credits[8]; 1705 __le16 credits[8]; 1706 1707 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1708 __le16 tc_bw_max[2]; 1709 }; 1710 1711 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1712 1713 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1714 struct i40e_aqc_configure_switching_comp_bw_limit { 1715 __le16 seid; 1716 u8 reserved[2]; 1717 __le16 credit; 1718 u8 reserved1[2]; 1719 u8 max_bw; /* 0-3, limit = 2^max */ 1720 u8 reserved2[7]; 1721 }; 1722 1723 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1724 1725 /* Enable Physical Port ETS (indirect 0x0413) 1726 * Modify Physical Port ETS (indirect 0x0414) 1727 * Disable Physical Port ETS (indirect 0x0415) 1728 */ 1729 struct i40e_aqc_configure_switching_comp_ets_data { 1730 u8 reserved[4]; 1731 u8 tc_valid_bits; 1732 u8 seepage; 1733 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1734 u8 tc_strict_priority_flags; 1735 u8 reserved1[17]; 1736 u8 tc_bw_share_credits[8]; 1737 u8 reserved2[96]; 1738 }; 1739 1740 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1741 1742 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1743 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1744 u8 tc_valid_bits; 1745 u8 reserved[15]; 1746 __le16 tc_bw_credit[8]; 1747 1748 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1749 __le16 tc_bw_max[2]; 1750 u8 reserved1[28]; 1751 }; 1752 1753 I40E_CHECK_STRUCT_LEN(0x40, 1754 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1755 1756 /* Configure Switching Component Bandwidth Allocation per Tc 1757 * (indirect 0x0417) 1758 */ 1759 struct i40e_aqc_configure_switching_comp_bw_config_data { 1760 u8 tc_valid_bits; 1761 u8 reserved[2]; 1762 u8 absolute_credits; /* bool */ 1763 u8 tc_bw_share_credits[8]; 1764 u8 reserved1[20]; 1765 }; 1766 1767 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1768 1769 /* Query Switching Component Configuration (indirect 0x0418) */ 1770 struct i40e_aqc_query_switching_comp_ets_config_resp { 1771 u8 tc_valid_bits; 1772 u8 reserved[35]; 1773 __le16 port_bw_limit; 1774 u8 reserved1[2]; 1775 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1776 u8 reserved2[23]; 1777 }; 1778 1779 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1780 1781 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1782 struct i40e_aqc_query_port_ets_config_resp { 1783 u8 reserved[4]; 1784 u8 tc_valid_bits; 1785 u8 reserved1; 1786 u8 tc_strict_priority_bits; 1787 u8 reserved2; 1788 u8 tc_bw_share_credits[8]; 1789 __le16 tc_bw_limits[8]; 1790 1791 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1792 __le16 tc_bw_max[2]; 1793 u8 reserved3[32]; 1794 }; 1795 1796 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1797 1798 /* Query Switching Component Bandwidth Allocation per Traffic Type 1799 * (indirect 0x041A) 1800 */ 1801 struct i40e_aqc_query_switching_comp_bw_config_resp { 1802 u8 tc_valid_bits; 1803 u8 reserved[2]; 1804 u8 absolute_credits_enable; /* bool */ 1805 u8 tc_bw_share_credits[8]; 1806 __le16 tc_bw_limits[8]; 1807 1808 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1809 __le16 tc_bw_max[2]; 1810 }; 1811 1812 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1813 1814 /* Suspend/resume port TX traffic 1815 * (direct 0x041B and 0x041C) uses the generic SEID struct 1816 */ 1817 1818 /* Configure partition BW 1819 * (indirect 0x041D) 1820 */ 1821 struct i40e_aqc_configure_partition_bw_data { 1822 __le16 pf_valid_bits; 1823 u8 min_bw[16]; /* guaranteed bandwidth */ 1824 u8 max_bw[16]; /* bandwidth limit */ 1825 }; 1826 1827 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1828 1829 /* Get and set the active HMC resource profile and status. 1830 * (direct 0x0500) and (direct 0x0501) 1831 */ 1832 struct i40e_aq_get_set_hmc_resource_profile { 1833 u8 pm_profile; 1834 u8 pe_vf_enabled; 1835 u8 reserved[14]; 1836 }; 1837 1838 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1839 1840 enum i40e_aq_hmc_profile { 1841 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1842 I40E_HMC_PROFILE_DEFAULT = 1, 1843 I40E_HMC_PROFILE_FAVOR_VF = 2, 1844 I40E_HMC_PROFILE_EQUAL = 3, 1845 }; 1846 1847 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1848 1849 /* set in param0 for get phy abilities to report qualified modules */ 1850 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1851 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1852 1853 enum i40e_aq_phy_type { 1854 I40E_PHY_TYPE_SGMII = 0x0, 1855 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1856 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1857 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1858 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1859 I40E_PHY_TYPE_XAUI = 0x5, 1860 I40E_PHY_TYPE_XFI = 0x6, 1861 I40E_PHY_TYPE_SFI = 0x7, 1862 I40E_PHY_TYPE_XLAUI = 0x8, 1863 I40E_PHY_TYPE_XLPPI = 0x9, 1864 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1865 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1866 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1867 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1868 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1869 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1870 I40E_PHY_TYPE_100BASE_TX = 0x11, 1871 I40E_PHY_TYPE_1000BASE_T = 0x12, 1872 I40E_PHY_TYPE_10GBASE_T = 0x13, 1873 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1874 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1875 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1876 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1877 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1878 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1879 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1880 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1881 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1882 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1883 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1884 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1885 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1886 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1887 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1888 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1889 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1890 I40E_PHY_TYPE_MAX, 1891 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1892 I40E_PHY_TYPE_EMPTY = 0xFE, 1893 I40E_PHY_TYPE_DEFAULT = 0xFF, 1894 }; 1895 1896 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1897 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1898 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1899 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1900 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1901 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1902 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1903 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1904 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1905 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1906 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1907 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1908 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1909 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1910 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1911 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1912 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1913 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1914 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1915 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1916 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1917 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1918 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1919 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1920 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1921 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1922 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1923 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1924 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1925 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1926 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1927 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1928 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1929 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1930 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1931 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) 1932 1933 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1934 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1935 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1936 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1937 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1938 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1939 1940 enum i40e_aq_link_speed { 1941 I40E_LINK_SPEED_UNKNOWN = 0, 1942 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1943 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1944 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1945 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1946 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1947 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1948 }; 1949 1950 struct i40e_aqc_module_desc { 1951 u8 oui[3]; 1952 u8 reserved1; 1953 u8 part_number[16]; 1954 u8 revision[4]; 1955 u8 reserved2[8]; 1956 }; 1957 1958 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1959 1960 struct i40e_aq_get_phy_abilities_resp { 1961 __le32 phy_type; /* bitmap using the above enum for offsets */ 1962 u8 link_speed; /* bitmap using the above enum bit patterns */ 1963 u8 abilities; 1964 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1965 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1966 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1967 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1968 #define I40E_AQ_PHY_AN_ENABLED 0x10 1969 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1970 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1971 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1972 __le16 eee_capability; 1973 #define I40E_AQ_EEE_100BASE_TX 0x0002 1974 #define I40E_AQ_EEE_1000BASE_T 0x0004 1975 #define I40E_AQ_EEE_10GBASE_T 0x0008 1976 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1977 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1978 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1979 __le32 eeer_val; 1980 u8 d3_lpan; 1981 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1982 u8 phy_type_ext; 1983 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1984 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1985 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1986 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1987 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1988 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1989 u8 fec_cfg_curr_mod_ext_info; 1990 #define I40E_AQ_ENABLE_FEC_KR 0x01 1991 #define I40E_AQ_ENABLE_FEC_RS 0x02 1992 #define I40E_AQ_REQUEST_FEC_KR 0x04 1993 #define I40E_AQ_REQUEST_FEC_RS 0x08 1994 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1995 #define I40E_AQ_FEC 1996 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1997 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1998 1999 u8 ext_comp_code; 2000 u8 phy_id[4]; 2001 u8 module_type[3]; 2002 u8 qualified_module_count; 2003 #define I40E_AQ_PHY_MAX_QMS 16 2004 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2005 }; 2006 2007 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2008 2009 /* Set PHY Config (direct 0x0601) */ 2010 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2011 __le32 phy_type; 2012 u8 link_speed; 2013 u8 abilities; 2014 /* bits 0-2 use the values from get_phy_abilities_resp */ 2015 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2016 #define I40E_AQ_PHY_ENABLE_AN 0x10 2017 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2018 __le16 eee_capability; 2019 __le32 eeer; 2020 u8 low_power_ctrl; 2021 u8 phy_type_ext; 2022 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2023 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2024 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2025 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2026 u8 fec_config; 2027 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2028 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2029 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2030 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2031 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2032 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2033 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2034 u8 reserved; 2035 }; 2036 2037 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2038 2039 /* Set MAC Config command data structure (direct 0x0603) */ 2040 struct i40e_aq_set_mac_config { 2041 __le16 max_frame_size; 2042 u8 params; 2043 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2044 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2045 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2046 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2047 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2048 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2049 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2050 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2051 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2052 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2053 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2054 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2055 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2056 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2057 u8 tx_timer_priority; /* bitmap */ 2058 __le16 tx_timer_value; 2059 __le16 fc_refresh_threshold; 2060 u8 reserved[8]; 2061 }; 2062 2063 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2064 2065 /* Restart Auto-Negotiation (direct 0x605) */ 2066 struct i40e_aqc_set_link_restart_an { 2067 u8 command; 2068 #define I40E_AQ_PHY_RESTART_AN 0x02 2069 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2070 u8 reserved[15]; 2071 }; 2072 2073 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2074 2075 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2076 struct i40e_aqc_get_link_status { 2077 __le16 command_flags; /* only field set on command */ 2078 #define I40E_AQ_LSE_MASK 0x3 2079 #define I40E_AQ_LSE_NOP 0x0 2080 #define I40E_AQ_LSE_DISABLE 0x2 2081 #define I40E_AQ_LSE_ENABLE 0x3 2082 /* only response uses this flag */ 2083 #define I40E_AQ_LSE_IS_ENABLED 0x1 2084 u8 phy_type; /* i40e_aq_phy_type */ 2085 u8 link_speed; /* i40e_aq_link_speed */ 2086 u8 link_info; 2087 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2088 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2089 #define I40E_AQ_LINK_FAULT 0x02 2090 #define I40E_AQ_LINK_FAULT_TX 0x04 2091 #define I40E_AQ_LINK_FAULT_RX 0x08 2092 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2093 #define I40E_AQ_LINK_UP_PORT 0x20 2094 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2095 #define I40E_AQ_SIGNAL_DETECT 0x80 2096 u8 an_info; 2097 #define I40E_AQ_AN_COMPLETED 0x01 2098 #define I40E_AQ_LP_AN_ABILITY 0x02 2099 #define I40E_AQ_PD_FAULT 0x04 2100 #define I40E_AQ_FEC_EN 0x08 2101 #define I40E_AQ_PHY_LOW_POWER 0x10 2102 #define I40E_AQ_LINK_PAUSE_TX 0x20 2103 #define I40E_AQ_LINK_PAUSE_RX 0x40 2104 #define I40E_AQ_QUALIFIED_MODULE 0x80 2105 u8 ext_info; 2106 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2107 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2108 #define I40E_AQ_LINK_TX_SHIFT 0x02 2109 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2110 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2111 #define I40E_AQ_LINK_TX_DRAINED 0x01 2112 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2113 #define I40E_AQ_LINK_FORCED_40G 0x10 2114 /* 25G Error Codes */ 2115 #define I40E_AQ_25G_NO_ERR 0X00 2116 #define I40E_AQ_25G_NOT_PRESENT 0X01 2117 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2118 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2119 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2120 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2121 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2122 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2123 #define I40E_AQ_LOOPBACK_MASK 0x07 2124 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2125 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2126 __le16 max_frame_size; 2127 u8 config; 2128 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2129 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2130 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2131 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2132 union { 2133 struct { 2134 u8 power_desc; 2135 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2136 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2137 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2138 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2139 #define I40E_AQ_PWR_CLASS_MASK 0x03 2140 u8 reserved[4]; 2141 }; 2142 struct { 2143 u8 link_type[4]; 2144 u8 link_type_ext; 2145 }; 2146 }; 2147 }; 2148 2149 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2150 2151 /* Set event mask command (direct 0x613) */ 2152 struct i40e_aqc_set_phy_int_mask { 2153 u8 reserved[8]; 2154 __le16 event_mask; 2155 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2156 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2157 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2158 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2159 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2160 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2161 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2162 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2163 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2164 u8 reserved1[6]; 2165 }; 2166 2167 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2168 2169 /* Get Local AN advt register (direct 0x0614) 2170 * Set Local AN advt register (direct 0x0615) 2171 * Get Link Partner AN advt register (direct 0x0616) 2172 */ 2173 struct i40e_aqc_an_advt_reg { 2174 __le32 local_an_reg0; 2175 __le16 local_an_reg1; 2176 u8 reserved[10]; 2177 }; 2178 2179 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2180 2181 /* Set Loopback mode (0x0618) */ 2182 struct i40e_aqc_set_lb_mode { 2183 __le16 lb_mode; 2184 #define I40E_AQ_LB_PHY_LOCAL 0x01 2185 #define I40E_AQ_LB_PHY_REMOTE 0x02 2186 #define I40E_AQ_LB_MAC_LOCAL 0x04 2187 u8 reserved[14]; 2188 }; 2189 2190 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2191 2192 /* Set PHY Debug command (0x0622) */ 2193 struct i40e_aqc_set_phy_debug { 2194 u8 command_flags; 2195 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2196 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2197 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2198 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2199 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2200 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2201 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2202 /* Disable link manageability on a single port */ 2203 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2204 /* Disable link manageability on all ports */ 2205 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2206 u8 reserved[15]; 2207 }; 2208 2209 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2210 2211 enum i40e_aq_phy_reg_type { 2212 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2213 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2214 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2215 }; 2216 2217 /* Run PHY Activity (0x0626) */ 2218 struct i40e_aqc_run_phy_activity { 2219 __le16 activity_id; 2220 u8 flags; 2221 u8 reserved1; 2222 __le32 control; 2223 __le32 data; 2224 u8 reserved2[4]; 2225 }; 2226 2227 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2228 2229 /* Set PHY Register command (0x0628) */ 2230 /* Get PHY Register command (0x0629) */ 2231 struct i40e_aqc_phy_register_access { 2232 u8 phy_interface; 2233 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2234 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2235 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2236 u8 dev_address; 2237 u8 reserved1[2]; 2238 __le32 reg_address; 2239 __le32 reg_value; 2240 u8 reserved2[4]; 2241 }; 2242 2243 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2244 2245 /* NVM Read command (indirect 0x0701) 2246 * NVM Erase commands (direct 0x0702) 2247 * NVM Update commands (indirect 0x0703) 2248 */ 2249 struct i40e_aqc_nvm_update { 2250 u8 command_flags; 2251 #define I40E_AQ_NVM_LAST_CMD 0x01 2252 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2253 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2254 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2255 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2256 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2257 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2258 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2259 u8 module_pointer; 2260 __le16 length; 2261 __le32 offset; 2262 __le32 addr_high; 2263 __le32 addr_low; 2264 }; 2265 2266 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2267 2268 /* NVM Config Read (indirect 0x0704) */ 2269 struct i40e_aqc_nvm_config_read { 2270 __le16 cmd_flags; 2271 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2272 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2273 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2274 __le16 element_count; 2275 __le16 element_id; /* Feature/field ID */ 2276 __le16 element_id_msw; /* MSWord of field ID */ 2277 __le32 address_high; 2278 __le32 address_low; 2279 }; 2280 2281 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2282 2283 /* NVM Config Write (indirect 0x0705) */ 2284 struct i40e_aqc_nvm_config_write { 2285 __le16 cmd_flags; 2286 __le16 element_count; 2287 u8 reserved[4]; 2288 __le32 address_high; 2289 __le32 address_low; 2290 }; 2291 2292 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2293 2294 /* Used for 0x0704 as well as for 0x0705 commands */ 2295 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2296 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2297 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2298 #define I40E_AQ_ANVM_FEATURE 0 2299 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2300 struct i40e_aqc_nvm_config_data_feature { 2301 __le16 feature_id; 2302 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2303 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2304 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2305 __le16 feature_options; 2306 __le16 feature_selection; 2307 }; 2308 2309 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2310 2311 struct i40e_aqc_nvm_config_data_immediate_field { 2312 __le32 field_id; 2313 __le32 field_value; 2314 __le16 field_options; 2315 __le16 reserved; 2316 }; 2317 2318 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2319 2320 /* OEM Post Update (indirect 0x0720) 2321 * no command data struct used 2322 */ 2323 struct i40e_aqc_nvm_oem_post_update { 2324 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2325 u8 sel_data; 2326 u8 reserved[7]; 2327 }; 2328 2329 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2330 2331 struct i40e_aqc_nvm_oem_post_update_buffer { 2332 u8 str_len; 2333 u8 dev_addr; 2334 __le16 eeprom_addr; 2335 u8 data[36]; 2336 }; 2337 2338 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2339 2340 /* Thermal Sensor (indirect 0x0721) 2341 * read or set thermal sensor configs and values 2342 * takes a sensor and command specific data buffer, not detailed here 2343 */ 2344 struct i40e_aqc_thermal_sensor { 2345 u8 sensor_action; 2346 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2347 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2348 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2349 u8 reserved[7]; 2350 __le32 addr_high; 2351 __le32 addr_low; 2352 }; 2353 2354 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2355 2356 /* Send to PF command (indirect 0x0801) id is only used by PF 2357 * Send to VF command (indirect 0x0802) id is only used by PF 2358 * Send to Peer PF command (indirect 0x0803) 2359 */ 2360 struct i40e_aqc_pf_vf_message { 2361 __le32 id; 2362 u8 reserved[4]; 2363 __le32 addr_high; 2364 __le32 addr_low; 2365 }; 2366 2367 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2368 2369 /* Alternate structure */ 2370 2371 /* Direct write (direct 0x0900) 2372 * Direct read (direct 0x0902) 2373 */ 2374 struct i40e_aqc_alternate_write { 2375 __le32 address0; 2376 __le32 data0; 2377 __le32 address1; 2378 __le32 data1; 2379 }; 2380 2381 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2382 2383 /* Indirect write (indirect 0x0901) 2384 * Indirect read (indirect 0x0903) 2385 */ 2386 2387 struct i40e_aqc_alternate_ind_write { 2388 __le32 address; 2389 __le32 length; 2390 __le32 addr_high; 2391 __le32 addr_low; 2392 }; 2393 2394 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2395 2396 /* Done alternate write (direct 0x0904) 2397 * uses i40e_aq_desc 2398 */ 2399 struct i40e_aqc_alternate_write_done { 2400 __le16 cmd_flags; 2401 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2402 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2403 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2404 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2405 u8 reserved[14]; 2406 }; 2407 2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2409 2410 /* Set OEM mode (direct 0x0905) */ 2411 struct i40e_aqc_alternate_set_mode { 2412 __le32 mode; 2413 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2414 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2415 u8 reserved[12]; 2416 }; 2417 2418 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2419 2420 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2421 2422 /* async events 0x10xx */ 2423 2424 /* Lan Queue Overflow Event (direct, 0x1001) */ 2425 struct i40e_aqc_lan_overflow { 2426 __le32 prtdcb_rupto; 2427 __le32 otx_ctl; 2428 u8 reserved[8]; 2429 }; 2430 2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2432 2433 /* Get LLDP MIB (indirect 0x0A00) */ 2434 struct i40e_aqc_lldp_get_mib { 2435 u8 type; 2436 u8 reserved1; 2437 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2438 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2439 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2440 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2441 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2442 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2443 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2444 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2445 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2446 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2447 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2448 __le16 local_len; 2449 __le16 remote_len; 2450 u8 reserved2[2]; 2451 __le32 addr_high; 2452 __le32 addr_low; 2453 }; 2454 2455 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2456 2457 /* Configure LLDP MIB Change Event (direct 0x0A01) 2458 * also used for the event (with type in the command field) 2459 */ 2460 struct i40e_aqc_lldp_update_mib { 2461 u8 command; 2462 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2463 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2464 u8 reserved[7]; 2465 __le32 addr_high; 2466 __le32 addr_low; 2467 }; 2468 2469 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2470 2471 /* Add LLDP TLV (indirect 0x0A02) 2472 * Delete LLDP TLV (indirect 0x0A04) 2473 */ 2474 struct i40e_aqc_lldp_add_tlv { 2475 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2476 u8 reserved1[1]; 2477 __le16 len; 2478 u8 reserved2[4]; 2479 __le32 addr_high; 2480 __le32 addr_low; 2481 }; 2482 2483 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2484 2485 /* Update LLDP TLV (indirect 0x0A03) */ 2486 struct i40e_aqc_lldp_update_tlv { 2487 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2488 u8 reserved; 2489 __le16 old_len; 2490 __le16 new_offset; 2491 __le16 new_len; 2492 __le32 addr_high; 2493 __le32 addr_low; 2494 }; 2495 2496 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2497 2498 /* Stop LLDP (direct 0x0A05) */ 2499 struct i40e_aqc_lldp_stop { 2500 u8 command; 2501 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2502 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2503 u8 reserved[15]; 2504 }; 2505 2506 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2507 2508 /* Start LLDP (direct 0x0A06) */ 2509 2510 struct i40e_aqc_lldp_start { 2511 u8 command; 2512 #define I40E_AQ_LLDP_AGENT_START 0x1 2513 u8 reserved[15]; 2514 }; 2515 2516 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2517 2518 /* Set DCB (direct 0x0303) */ 2519 struct i40e_aqc_set_dcb_parameters { 2520 u8 command; 2521 #define I40E_AQ_DCB_SET_AGENT 0x1 2522 #define I40E_DCB_VALID 0x1 2523 u8 valid_flags; 2524 u8 reserved[14]; 2525 }; 2526 2527 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2528 2529 /* Get CEE DCBX Oper Config (0x0A07) 2530 * uses the generic descriptor struct 2531 * returns below as indirect response 2532 */ 2533 2534 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2535 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2536 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2537 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2538 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2539 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2540 2541 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2542 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2543 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2544 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2545 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2546 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2547 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2548 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2549 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2550 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2551 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2552 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2553 2554 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2555 * word boundary layout issues, which the Linux compilers silently deal 2556 * with by adding padding, making the actual struct larger than designed. 2557 * However, the FW compiler for the NIC is less lenient and complains 2558 * about the struct. Hence, the struct defined here has an extra byte in 2559 * fields reserved3 and reserved4 to directly acknowledge that padding, 2560 * and the new length is used in the length check macro. 2561 */ 2562 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2563 u8 reserved1; 2564 u8 oper_num_tc; 2565 u8 oper_prio_tc[4]; 2566 u8 reserved2; 2567 u8 oper_tc_bw[8]; 2568 u8 oper_pfc_en; 2569 u8 reserved3[2]; 2570 __le16 oper_app_prio; 2571 u8 reserved4[2]; 2572 __le16 tlv_status; 2573 }; 2574 2575 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2576 2577 struct i40e_aqc_get_cee_dcb_cfg_resp { 2578 u8 oper_num_tc; 2579 u8 oper_prio_tc[4]; 2580 u8 oper_tc_bw[8]; 2581 u8 oper_pfc_en; 2582 __le16 oper_app_prio; 2583 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2584 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2585 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2586 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2587 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2588 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2589 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2590 __le32 tlv_status; 2591 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2592 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2593 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2594 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2595 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2596 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2597 u8 reserved[12]; 2598 }; 2599 2600 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2601 2602 /* Set Local LLDP MIB (indirect 0x0A08) 2603 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2604 */ 2605 struct i40e_aqc_lldp_set_local_mib { 2606 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2607 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2608 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2609 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2610 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2611 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2612 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2613 u8 type; 2614 u8 reserved0; 2615 __le16 length; 2616 u8 reserved1[4]; 2617 __le32 address_high; 2618 __le32 address_low; 2619 }; 2620 2621 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2622 2623 /* Stop/Start LLDP Agent (direct 0x0A09) 2624 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2625 */ 2626 struct i40e_aqc_lldp_stop_start_specific_agent { 2627 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2628 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2629 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2630 u8 command; 2631 u8 reserved[15]; 2632 }; 2633 2634 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2635 2636 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2637 struct i40e_aqc_add_udp_tunnel { 2638 __le16 udp_port; 2639 u8 reserved0[3]; 2640 u8 protocol_type; 2641 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2642 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2643 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2644 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2645 u8 reserved1[10]; 2646 }; 2647 2648 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2649 2650 struct i40e_aqc_add_udp_tunnel_completion { 2651 __le16 udp_port; 2652 u8 filter_entry_index; 2653 u8 multiple_pfs; 2654 #define I40E_AQC_SINGLE_PF 0x0 2655 #define I40E_AQC_MULTIPLE_PFS 0x1 2656 u8 total_filters; 2657 u8 reserved[11]; 2658 }; 2659 2660 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2661 2662 /* remove UDP Tunnel command (0x0B01) */ 2663 struct i40e_aqc_remove_udp_tunnel { 2664 u8 reserved[2]; 2665 u8 index; /* 0 to 15 */ 2666 u8 reserved2[13]; 2667 }; 2668 2669 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2670 2671 struct i40e_aqc_del_udp_tunnel_completion { 2672 __le16 udp_port; 2673 u8 index; /* 0 to 15 */ 2674 u8 multiple_pfs; 2675 u8 total_filters_used; 2676 u8 reserved1[11]; 2677 }; 2678 2679 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2680 2681 struct i40e_aqc_get_set_rss_key { 2682 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2683 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2684 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2685 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2686 __le16 vsi_id; 2687 u8 reserved[6]; 2688 __le32 addr_high; 2689 __le32 addr_low; 2690 }; 2691 2692 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2693 2694 struct i40e_aqc_get_set_rss_key_data { 2695 u8 standard_rss_key[0x28]; 2696 u8 extended_hash_key[0xc]; 2697 }; 2698 2699 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2700 2701 struct i40e_aqc_get_set_rss_lut { 2702 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2703 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2704 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2705 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2706 __le16 vsi_id; 2707 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2708 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2709 2710 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2711 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2712 __le16 flags; 2713 u8 reserved[4]; 2714 __le32 addr_high; 2715 __le32 addr_low; 2716 }; 2717 2718 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2719 2720 /* tunnel key structure 0x0B10 */ 2721 2722 struct i40e_aqc_tunnel_key_structure { 2723 u8 key1_off; 2724 u8 key2_off; 2725 u8 key1_len; /* 0 to 15 */ 2726 u8 key2_len; /* 0 to 15 */ 2727 u8 flags; 2728 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2729 /* response flags */ 2730 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2731 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2732 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2733 u8 network_key_index; 2734 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2735 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2736 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2737 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2738 u8 reserved[10]; 2739 }; 2740 2741 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2742 2743 /* OEM mode commands (direct 0xFE0x) */ 2744 struct i40e_aqc_oem_param_change { 2745 __le32 param_type; 2746 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2747 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2748 #define I40E_AQ_OEM_PARAM_MAC 2 2749 __le32 param_value1; 2750 __le16 param_value2; 2751 u8 reserved[6]; 2752 }; 2753 2754 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2755 2756 struct i40e_aqc_oem_state_change { 2757 __le32 state; 2758 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2759 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2760 u8 reserved[12]; 2761 }; 2762 2763 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2764 2765 /* Initialize OCSD (0xFE02, direct) */ 2766 struct i40e_aqc_opc_oem_ocsd_initialize { 2767 u8 type_status; 2768 u8 reserved1[3]; 2769 __le32 ocsd_memory_block_addr_high; 2770 __le32 ocsd_memory_block_addr_low; 2771 __le32 requested_update_interval; 2772 }; 2773 2774 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2775 2776 /* Initialize OCBB (0xFE03, direct) */ 2777 struct i40e_aqc_opc_oem_ocbb_initialize { 2778 u8 type_status; 2779 u8 reserved1[3]; 2780 __le32 ocbb_memory_block_addr_high; 2781 __le32 ocbb_memory_block_addr_low; 2782 u8 reserved2[4]; 2783 }; 2784 2785 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2786 2787 /* debug commands */ 2788 2789 /* get device id (0xFF00) uses the generic structure */ 2790 2791 /* set test more (0xFF01, internal) */ 2792 2793 struct i40e_acq_set_test_mode { 2794 u8 mode; 2795 #define I40E_AQ_TEST_PARTIAL 0 2796 #define I40E_AQ_TEST_FULL 1 2797 #define I40E_AQ_TEST_NVM 2 2798 u8 reserved[3]; 2799 u8 command; 2800 #define I40E_AQ_TEST_OPEN 0 2801 #define I40E_AQ_TEST_CLOSE 1 2802 #define I40E_AQ_TEST_INC 2 2803 u8 reserved2[3]; 2804 __le32 address_high; 2805 __le32 address_low; 2806 }; 2807 2808 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2809 2810 /* Debug Read Register command (0xFF03) 2811 * Debug Write Register command (0xFF04) 2812 */ 2813 struct i40e_aqc_debug_reg_read_write { 2814 __le32 reserved; 2815 __le32 address; 2816 __le32 value_high; 2817 __le32 value_low; 2818 }; 2819 2820 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2821 2822 /* Scatter/gather Reg Read (indirect 0xFF05) 2823 * Scatter/gather Reg Write (indirect 0xFF06) 2824 */ 2825 2826 /* i40e_aq_desc is used for the command */ 2827 struct i40e_aqc_debug_reg_sg_element_data { 2828 __le32 address; 2829 __le32 value; 2830 }; 2831 2832 /* Debug Modify register (direct 0xFF07) */ 2833 struct i40e_aqc_debug_modify_reg { 2834 __le32 address; 2835 __le32 value; 2836 __le32 clear_mask; 2837 __le32 set_mask; 2838 }; 2839 2840 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2841 2842 /* dump internal data (0xFF08, indirect) */ 2843 2844 #define I40E_AQ_CLUSTER_ID_AUX 0 2845 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2846 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2847 #define I40E_AQ_CLUSTER_ID_HMC 3 2848 #define I40E_AQ_CLUSTER_ID_MAC0 4 2849 #define I40E_AQ_CLUSTER_ID_MAC1 5 2850 #define I40E_AQ_CLUSTER_ID_MAC2 6 2851 #define I40E_AQ_CLUSTER_ID_MAC3 7 2852 #define I40E_AQ_CLUSTER_ID_DCB 8 2853 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2854 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2855 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2856 2857 struct i40e_aqc_debug_dump_internals { 2858 u8 cluster_id; 2859 u8 table_id; 2860 __le16 data_size; 2861 __le32 idx; 2862 __le32 address_high; 2863 __le32 address_low; 2864 }; 2865 2866 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2867 2868 struct i40e_aqc_debug_modify_internals { 2869 u8 cluster_id; 2870 u8 cluster_specific_params[7]; 2871 __le32 address_high; 2872 __le32 address_low; 2873 }; 2874 2875 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2876 2877 #endif /* _I40E_ADMINQ_CMD_H_ */ 2878