1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_ADMINQ_CMD_H_ 5 #define _I40E_ADMINQ_CMD_H_ 6 7 /* This header file defines the i40e Admin Queue commands and is shared between 8 * i40e Firmware and Software. 9 * 10 * This file needs to comply with the Linux Kernel coding style. 11 */ 12 13 #define I40E_FW_API_VERSION_MAJOR 0x0001 14 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 15 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 16 17 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 18 I40E_FW_API_VERSION_MINOR_X710 : \ 19 I40E_FW_API_VERSION_MINOR_X722) 20 21 /* API version 1.7 implements additional link and PHY-specific APIs */ 22 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 23 24 struct i40e_aq_desc { 25 __le16 flags; 26 __le16 opcode; 27 __le16 datalen; 28 __le16 retval; 29 __le32 cookie_high; 30 __le32 cookie_low; 31 union { 32 struct { 33 __le32 param0; 34 __le32 param1; 35 __le32 param2; 36 __le32 param3; 37 } internal; 38 struct { 39 __le32 param0; 40 __le32 param1; 41 __le32 addr_high; 42 __le32 addr_low; 43 } external; 44 u8 raw[16]; 45 } params; 46 }; 47 48 /* Flags sub-structure 49 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 50 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 51 */ 52 53 /* command flags and offsets*/ 54 #define I40E_AQ_FLAG_DD_SHIFT 0 55 #define I40E_AQ_FLAG_CMP_SHIFT 1 56 #define I40E_AQ_FLAG_ERR_SHIFT 2 57 #define I40E_AQ_FLAG_VFE_SHIFT 3 58 #define I40E_AQ_FLAG_LB_SHIFT 9 59 #define I40E_AQ_FLAG_RD_SHIFT 10 60 #define I40E_AQ_FLAG_VFC_SHIFT 11 61 #define I40E_AQ_FLAG_BUF_SHIFT 12 62 #define I40E_AQ_FLAG_SI_SHIFT 13 63 #define I40E_AQ_FLAG_EI_SHIFT 14 64 #define I40E_AQ_FLAG_FE_SHIFT 15 65 66 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 67 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 68 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 69 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 70 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 71 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 72 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 73 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 74 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 75 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 76 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 77 78 /* error codes */ 79 enum i40e_admin_queue_err { 80 I40E_AQ_RC_OK = 0, /* success */ 81 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 82 I40E_AQ_RC_ENOENT = 2, /* No such element */ 83 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 84 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 85 I40E_AQ_RC_EIO = 5, /* I/O error */ 86 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 87 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 88 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 89 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 90 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 91 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 92 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 93 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 94 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 95 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 96 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 97 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 98 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 99 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 100 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 101 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 102 I40E_AQ_RC_EFBIG = 22, /* File too large */ 103 }; 104 105 /* Admin Queue command opcodes */ 106 enum i40e_admin_queue_opc { 107 /* aq commands */ 108 i40e_aqc_opc_get_version = 0x0001, 109 i40e_aqc_opc_driver_version = 0x0002, 110 i40e_aqc_opc_queue_shutdown = 0x0003, 111 i40e_aqc_opc_set_pf_context = 0x0004, 112 113 /* resource ownership */ 114 i40e_aqc_opc_request_resource = 0x0008, 115 i40e_aqc_opc_release_resource = 0x0009, 116 117 i40e_aqc_opc_list_func_capabilities = 0x000A, 118 i40e_aqc_opc_list_dev_capabilities = 0x000B, 119 120 /* Proxy commands */ 121 i40e_aqc_opc_set_proxy_config = 0x0104, 122 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 123 124 /* LAA */ 125 i40e_aqc_opc_mac_address_read = 0x0107, 126 i40e_aqc_opc_mac_address_write = 0x0108, 127 128 /* PXE */ 129 i40e_aqc_opc_clear_pxe_mode = 0x0110, 130 131 /* WoL commands */ 132 i40e_aqc_opc_set_wol_filter = 0x0120, 133 i40e_aqc_opc_get_wake_reason = 0x0121, 134 135 /* internal switch commands */ 136 i40e_aqc_opc_get_switch_config = 0x0200, 137 i40e_aqc_opc_add_statistics = 0x0201, 138 i40e_aqc_opc_remove_statistics = 0x0202, 139 i40e_aqc_opc_set_port_parameters = 0x0203, 140 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 141 i40e_aqc_opc_set_switch_config = 0x0205, 142 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 143 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 144 145 i40e_aqc_opc_add_vsi = 0x0210, 146 i40e_aqc_opc_update_vsi_parameters = 0x0211, 147 i40e_aqc_opc_get_vsi_parameters = 0x0212, 148 149 i40e_aqc_opc_add_pv = 0x0220, 150 i40e_aqc_opc_update_pv_parameters = 0x0221, 151 i40e_aqc_opc_get_pv_parameters = 0x0222, 152 153 i40e_aqc_opc_add_veb = 0x0230, 154 i40e_aqc_opc_update_veb_parameters = 0x0231, 155 i40e_aqc_opc_get_veb_parameters = 0x0232, 156 157 i40e_aqc_opc_delete_element = 0x0243, 158 159 i40e_aqc_opc_add_macvlan = 0x0250, 160 i40e_aqc_opc_remove_macvlan = 0x0251, 161 i40e_aqc_opc_add_vlan = 0x0252, 162 i40e_aqc_opc_remove_vlan = 0x0253, 163 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 164 i40e_aqc_opc_add_tag = 0x0255, 165 i40e_aqc_opc_remove_tag = 0x0256, 166 i40e_aqc_opc_add_multicast_etag = 0x0257, 167 i40e_aqc_opc_remove_multicast_etag = 0x0258, 168 i40e_aqc_opc_update_tag = 0x0259, 169 i40e_aqc_opc_add_control_packet_filter = 0x025A, 170 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 171 i40e_aqc_opc_add_cloud_filters = 0x025C, 172 i40e_aqc_opc_remove_cloud_filters = 0x025D, 173 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 174 175 i40e_aqc_opc_add_mirror_rule = 0x0260, 176 i40e_aqc_opc_delete_mirror_rule = 0x0261, 177 178 /* Dynamic Device Personalization */ 179 i40e_aqc_opc_write_personalization_profile = 0x0270, 180 i40e_aqc_opc_get_personalization_profile_list = 0x0271, 181 182 /* DCB commands */ 183 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 184 i40e_aqc_opc_dcb_updated = 0x0302, 185 i40e_aqc_opc_set_dcb_parameters = 0x0303, 186 187 /* TX scheduler */ 188 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 189 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 190 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 191 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 192 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 193 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 194 195 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 196 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 197 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 198 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 199 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 200 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 201 i40e_aqc_opc_query_port_ets_config = 0x0419, 202 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 203 i40e_aqc_opc_suspend_port_tx = 0x041B, 204 i40e_aqc_opc_resume_port_tx = 0x041C, 205 i40e_aqc_opc_configure_partition_bw = 0x041D, 206 /* hmc */ 207 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 208 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 209 210 /* phy commands*/ 211 i40e_aqc_opc_get_phy_abilities = 0x0600, 212 i40e_aqc_opc_set_phy_config = 0x0601, 213 i40e_aqc_opc_set_mac_config = 0x0603, 214 i40e_aqc_opc_set_link_restart_an = 0x0605, 215 i40e_aqc_opc_get_link_status = 0x0607, 216 i40e_aqc_opc_set_phy_int_mask = 0x0613, 217 i40e_aqc_opc_get_local_advt_reg = 0x0614, 218 i40e_aqc_opc_set_local_advt_reg = 0x0615, 219 i40e_aqc_opc_get_partner_advt = 0x0616, 220 i40e_aqc_opc_set_lb_modes = 0x0618, 221 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 222 i40e_aqc_opc_set_phy_debug = 0x0622, 223 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 224 i40e_aqc_opc_run_phy_activity = 0x0626, 225 i40e_aqc_opc_set_phy_register = 0x0628, 226 i40e_aqc_opc_get_phy_register = 0x0629, 227 228 /* NVM commands */ 229 i40e_aqc_opc_nvm_read = 0x0701, 230 i40e_aqc_opc_nvm_erase = 0x0702, 231 i40e_aqc_opc_nvm_update = 0x0703, 232 i40e_aqc_opc_nvm_config_read = 0x0704, 233 i40e_aqc_opc_nvm_config_write = 0x0705, 234 i40e_aqc_opc_oem_post_update = 0x0720, 235 i40e_aqc_opc_thermal_sensor = 0x0721, 236 237 /* virtualization commands */ 238 i40e_aqc_opc_send_msg_to_pf = 0x0801, 239 i40e_aqc_opc_send_msg_to_vf = 0x0802, 240 i40e_aqc_opc_send_msg_to_peer = 0x0803, 241 242 /* alternate structure */ 243 i40e_aqc_opc_alternate_write = 0x0900, 244 i40e_aqc_opc_alternate_write_indirect = 0x0901, 245 i40e_aqc_opc_alternate_read = 0x0902, 246 i40e_aqc_opc_alternate_read_indirect = 0x0903, 247 i40e_aqc_opc_alternate_write_done = 0x0904, 248 i40e_aqc_opc_alternate_set_mode = 0x0905, 249 i40e_aqc_opc_alternate_clear_port = 0x0906, 250 251 /* LLDP commands */ 252 i40e_aqc_opc_lldp_get_mib = 0x0A00, 253 i40e_aqc_opc_lldp_update_mib = 0x0A01, 254 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 255 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 256 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 257 i40e_aqc_opc_lldp_stop = 0x0A05, 258 i40e_aqc_opc_lldp_start = 0x0A06, 259 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 260 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 261 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 262 263 /* Tunnel commands */ 264 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 265 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 266 i40e_aqc_opc_set_rss_key = 0x0B02, 267 i40e_aqc_opc_set_rss_lut = 0x0B03, 268 i40e_aqc_opc_get_rss_key = 0x0B04, 269 i40e_aqc_opc_get_rss_lut = 0x0B05, 270 271 /* Async Events */ 272 i40e_aqc_opc_event_lan_overflow = 0x1001, 273 274 /* OEM commands */ 275 i40e_aqc_opc_oem_parameter_change = 0xFE00, 276 i40e_aqc_opc_oem_device_status_change = 0xFE01, 277 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 278 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 279 280 /* debug commands */ 281 i40e_aqc_opc_debug_read_reg = 0xFF03, 282 i40e_aqc_opc_debug_write_reg = 0xFF04, 283 i40e_aqc_opc_debug_modify_reg = 0xFF07, 284 i40e_aqc_opc_debug_dump_internals = 0xFF08, 285 }; 286 287 /* command structures and indirect data structures */ 288 289 /* Structure naming conventions: 290 * - no suffix for direct command descriptor structures 291 * - _data for indirect sent data 292 * - _resp for indirect return data (data which is both will use _data) 293 * - _completion for direct return data 294 * - _element_ for repeated elements (may also be _data or _resp) 295 * 296 * Command structures are expected to overlay the params.raw member of the basic 297 * descriptor, and as such cannot exceed 16 bytes in length. 298 */ 299 300 /* This macro is used to generate a compilation error if a structure 301 * is not exactly the correct length. It gives a divide by zero error if the 302 * structure is not of the correct size, otherwise it creates an enum that is 303 * never used. 304 */ 305 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 306 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 307 308 /* This macro is used extensively to ensure that command structures are 16 309 * bytes in length as they have to map to the raw array of that size. 310 */ 311 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 312 313 /* internal (0x00XX) commands */ 314 315 /* Get version (direct 0x0001) */ 316 struct i40e_aqc_get_version { 317 __le32 rom_ver; 318 __le32 fw_build; 319 __le16 fw_major; 320 __le16 fw_minor; 321 __le16 api_major; 322 __le16 api_minor; 323 }; 324 325 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 326 327 /* Send driver version (indirect 0x0002) */ 328 struct i40e_aqc_driver_version { 329 u8 driver_major_ver; 330 u8 driver_minor_ver; 331 u8 driver_build_ver; 332 u8 driver_subbuild_ver; 333 u8 reserved[4]; 334 __le32 address_high; 335 __le32 address_low; 336 }; 337 338 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 339 340 /* Queue Shutdown (direct 0x0003) */ 341 struct i40e_aqc_queue_shutdown { 342 __le32 driver_unloading; 343 #define I40E_AQ_DRIVER_UNLOADING 0x1 344 u8 reserved[12]; 345 }; 346 347 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 348 349 /* Set PF context (0x0004, direct) */ 350 struct i40e_aqc_set_pf_context { 351 u8 pf_id; 352 u8 reserved[15]; 353 }; 354 355 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 356 357 /* Request resource ownership (direct 0x0008) 358 * Release resource ownership (direct 0x0009) 359 */ 360 #define I40E_AQ_RESOURCE_NVM 1 361 #define I40E_AQ_RESOURCE_SDP 2 362 #define I40E_AQ_RESOURCE_ACCESS_READ 1 363 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 364 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 365 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 366 367 struct i40e_aqc_request_resource { 368 __le16 resource_id; 369 __le16 access_type; 370 __le32 timeout; 371 __le32 resource_number; 372 u8 reserved[4]; 373 }; 374 375 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 376 377 /* Get function capabilities (indirect 0x000A) 378 * Get device capabilities (indirect 0x000B) 379 */ 380 struct i40e_aqc_list_capabilites { 381 u8 command_flags; 382 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 383 u8 pf_index; 384 u8 reserved[2]; 385 __le32 count; 386 __le32 addr_high; 387 __le32 addr_low; 388 }; 389 390 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 391 392 struct i40e_aqc_list_capabilities_element_resp { 393 __le16 id; 394 u8 major_rev; 395 u8 minor_rev; 396 __le32 number; 397 __le32 logical_id; 398 __le32 phys_id; 399 u8 reserved[16]; 400 }; 401 402 /* list of caps */ 403 404 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 405 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 406 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 407 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 408 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 409 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 410 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 411 #define I40E_AQ_CAP_ID_SRIOV 0x0012 412 #define I40E_AQ_CAP_ID_VF 0x0013 413 #define I40E_AQ_CAP_ID_VMDQ 0x0014 414 #define I40E_AQ_CAP_ID_8021QBG 0x0015 415 #define I40E_AQ_CAP_ID_8021QBR 0x0016 416 #define I40E_AQ_CAP_ID_VSI 0x0017 417 #define I40E_AQ_CAP_ID_DCB 0x0018 418 #define I40E_AQ_CAP_ID_FCOE 0x0021 419 #define I40E_AQ_CAP_ID_ISCSI 0x0022 420 #define I40E_AQ_CAP_ID_RSS 0x0040 421 #define I40E_AQ_CAP_ID_RXQ 0x0041 422 #define I40E_AQ_CAP_ID_TXQ 0x0042 423 #define I40E_AQ_CAP_ID_MSIX 0x0043 424 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 425 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 426 #define I40E_AQ_CAP_ID_1588 0x0046 427 #define I40E_AQ_CAP_ID_IWARP 0x0051 428 #define I40E_AQ_CAP_ID_LED 0x0061 429 #define I40E_AQ_CAP_ID_SDP 0x0062 430 #define I40E_AQ_CAP_ID_MDIO 0x0063 431 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 432 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 433 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 434 #define I40E_AQ_CAP_ID_CEM 0x00F2 435 436 /* Set CPPM Configuration (direct 0x0103) */ 437 struct i40e_aqc_cppm_configuration { 438 __le16 command_flags; 439 #define I40E_AQ_CPPM_EN_LTRC 0x0800 440 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 441 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 442 #define I40E_AQ_CPPM_EN_HPTC 0x4000 443 #define I40E_AQ_CPPM_EN_DMARC 0x8000 444 __le16 ttlx; 445 __le32 dmacr; 446 __le16 dmcth; 447 u8 hptc; 448 u8 reserved; 449 __le32 pfltrc; 450 }; 451 452 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 453 454 /* Set ARP Proxy command / response (indirect 0x0104) */ 455 struct i40e_aqc_arp_proxy_data { 456 __le16 command_flags; 457 #define I40E_AQ_ARP_INIT_IPV4 0x0800 458 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 459 #define I40E_AQ_ARP_ENA 0x2000 460 #define I40E_AQ_ARP_ADD_IPV4 0x4000 461 #define I40E_AQ_ARP_DEL_IPV4 0x8000 462 __le16 table_id; 463 __le32 enabled_offloads; 464 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 465 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 466 __le32 ip_addr; 467 u8 mac_addr[6]; 468 u8 reserved[2]; 469 }; 470 471 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 472 473 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 474 struct i40e_aqc_ns_proxy_data { 475 __le16 table_idx_mac_addr_0; 476 __le16 table_idx_mac_addr_1; 477 __le16 table_idx_ipv6_0; 478 __le16 table_idx_ipv6_1; 479 __le16 control; 480 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 481 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 482 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 483 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 484 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 485 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 486 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 487 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 488 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 489 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 490 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 491 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 492 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 493 u8 mac_addr_0[6]; 494 u8 mac_addr_1[6]; 495 u8 local_mac_addr[6]; 496 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 497 u8 ipv6_addr_1[16]; 498 }; 499 500 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 501 502 /* Manage LAA Command (0x0106) - obsolete */ 503 struct i40e_aqc_mng_laa { 504 __le16 command_flags; 505 #define I40E_AQ_LAA_FLAG_WR 0x8000 506 u8 reserved[2]; 507 __le32 sal; 508 __le16 sah; 509 u8 reserved2[6]; 510 }; 511 512 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 513 514 /* Manage MAC Address Read Command (indirect 0x0107) */ 515 struct i40e_aqc_mac_address_read { 516 __le16 command_flags; 517 #define I40E_AQC_LAN_ADDR_VALID 0x10 518 #define I40E_AQC_SAN_ADDR_VALID 0x20 519 #define I40E_AQC_PORT_ADDR_VALID 0x40 520 #define I40E_AQC_WOL_ADDR_VALID 0x80 521 #define I40E_AQC_MC_MAG_EN_VALID 0x100 522 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 523 u8 reserved[6]; 524 __le32 addr_high; 525 __le32 addr_low; 526 }; 527 528 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 529 530 struct i40e_aqc_mac_address_read_data { 531 u8 pf_lan_mac[6]; 532 u8 pf_san_mac[6]; 533 u8 port_mac[6]; 534 u8 pf_wol_mac[6]; 535 }; 536 537 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 538 539 /* Manage MAC Address Write Command (0x0108) */ 540 struct i40e_aqc_mac_address_write { 541 __le16 command_flags; 542 #define I40E_AQC_MC_MAG_EN 0x0100 543 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 544 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 545 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 546 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 547 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 548 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 549 550 __le16 mac_sah; 551 __le32 mac_sal; 552 u8 reserved[8]; 553 }; 554 555 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 556 557 /* PXE commands (0x011x) */ 558 559 /* Clear PXE Command and response (direct 0x0110) */ 560 struct i40e_aqc_clear_pxe { 561 u8 rx_cnt; 562 u8 reserved[15]; 563 }; 564 565 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 566 567 /* Set WoL Filter (0x0120) */ 568 569 struct i40e_aqc_set_wol_filter { 570 __le16 filter_index; 571 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 572 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 573 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 574 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 575 576 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 577 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 578 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 579 __le16 cmd_flags; 580 #define I40E_AQC_SET_WOL_FILTER 0x8000 581 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 582 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 583 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 584 __le16 valid_flags; 585 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 586 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 587 u8 reserved[2]; 588 __le32 address_high; 589 __le32 address_low; 590 }; 591 592 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 593 594 struct i40e_aqc_set_wol_filter_data { 595 u8 filter[128]; 596 u8 mask[16]; 597 }; 598 599 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 600 601 /* Get Wake Reason (0x0121) */ 602 603 struct i40e_aqc_get_wake_reason_completion { 604 u8 reserved_1[2]; 605 __le16 wake_reason; 606 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 607 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 608 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 609 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 610 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 611 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 612 u8 reserved_2[12]; 613 }; 614 615 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 616 617 /* Switch configuration commands (0x02xx) */ 618 619 /* Used by many indirect commands that only pass an seid and a buffer in the 620 * command 621 */ 622 struct i40e_aqc_switch_seid { 623 __le16 seid; 624 u8 reserved[6]; 625 __le32 addr_high; 626 __le32 addr_low; 627 }; 628 629 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 630 631 /* Get Switch Configuration command (indirect 0x0200) 632 * uses i40e_aqc_switch_seid for the descriptor 633 */ 634 struct i40e_aqc_get_switch_config_header_resp { 635 __le16 num_reported; 636 __le16 num_total; 637 u8 reserved[12]; 638 }; 639 640 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 641 642 struct i40e_aqc_switch_config_element_resp { 643 u8 element_type; 644 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 645 #define I40E_AQ_SW_ELEM_TYPE_PF 2 646 #define I40E_AQ_SW_ELEM_TYPE_VF 3 647 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 648 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 649 #define I40E_AQ_SW_ELEM_TYPE_PV 16 650 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 651 #define I40E_AQ_SW_ELEM_TYPE_PA 18 652 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 653 u8 revision; 654 #define I40E_AQ_SW_ELEM_REV_1 1 655 __le16 seid; 656 __le16 uplink_seid; 657 __le16 downlink_seid; 658 u8 reserved[3]; 659 u8 connection_type; 660 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 661 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 662 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 663 __le16 scheduler_id; 664 __le16 element_info; 665 }; 666 667 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 668 669 /* Get Switch Configuration (indirect 0x0200) 670 * an array of elements are returned in the response buffer 671 * the first in the array is the header, remainder are elements 672 */ 673 struct i40e_aqc_get_switch_config_resp { 674 struct i40e_aqc_get_switch_config_header_resp header; 675 struct i40e_aqc_switch_config_element_resp element[1]; 676 }; 677 678 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 679 680 /* Add Statistics (direct 0x0201) 681 * Remove Statistics (direct 0x0202) 682 */ 683 struct i40e_aqc_add_remove_statistics { 684 __le16 seid; 685 __le16 vlan; 686 __le16 stat_index; 687 u8 reserved[10]; 688 }; 689 690 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 691 692 /* Set Port Parameters command (direct 0x0203) */ 693 struct i40e_aqc_set_port_parameters { 694 __le16 command_flags; 695 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 696 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 697 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 698 __le16 bad_frame_vsi; 699 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 700 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 701 __le16 default_seid; /* reserved for command */ 702 u8 reserved[10]; 703 }; 704 705 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 706 707 /* Get Switch Resource Allocation (indirect 0x0204) */ 708 struct i40e_aqc_get_switch_resource_alloc { 709 u8 num_entries; /* reserved for command */ 710 u8 reserved[7]; 711 __le32 addr_high; 712 __le32 addr_low; 713 }; 714 715 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 716 717 /* expect an array of these structs in the response buffer */ 718 struct i40e_aqc_switch_resource_alloc_element_resp { 719 u8 resource_type; 720 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 721 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 722 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 723 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 724 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 725 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 726 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 727 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 728 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 729 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 730 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 731 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 732 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 733 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 734 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 735 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 736 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 737 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 738 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 739 u8 reserved1; 740 __le16 guaranteed; 741 __le16 total; 742 __le16 used; 743 __le16 total_unalloced; 744 u8 reserved2[6]; 745 }; 746 747 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 748 749 /* Set Switch Configuration (direct 0x0205) */ 750 struct i40e_aqc_set_switch_config { 751 __le16 flags; 752 /* flags used for both fields below */ 753 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 754 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 755 __le16 valid_flags; 756 /* The ethertype in switch_tag is dropped on ingress and used 757 * internally by the switch. Set this to zero for the default 758 * of 0x88a8 (802.1ad). Should be zero for firmware API 759 * versions lower than 1.7. 760 */ 761 __le16 switch_tag; 762 /* The ethertypes in first_tag and second_tag are used to 763 * match the outer and inner VLAN tags (respectively) when HW 764 * double VLAN tagging is enabled via the set port parameters 765 * AQ command. Otherwise these are both ignored. Set them to 766 * zero for their defaults of 0x8100 (802.1Q). Should be zero 767 * for firmware API versions lower than 1.7. 768 */ 769 __le16 first_tag; 770 __le16 second_tag; 771 /* Next byte is split into following: 772 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 773 * Bit 6 : 0 : Destination Port, 1: source port 774 * Bit 5..4 : L4 type 775 * 0: rsvd 776 * 1: TCP 777 * 2: UDP 778 * 3: Both TCP and UDP 779 * Bits 3:0 Mode 780 * 0: default mode 781 * 1: L4 port only mode 782 * 2: non-tunneled mode 783 * 3: tunneled mode 784 */ 785 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 786 787 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 788 789 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 790 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 791 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 792 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 793 794 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 795 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 796 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 797 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 798 u8 mode; 799 u8 rsvd5[5]; 800 }; 801 802 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 803 804 /* Read Receive control registers (direct 0x0206) 805 * Write Receive control registers (direct 0x0207) 806 * used for accessing Rx control registers that can be 807 * slow and need special handling when under high Rx load 808 */ 809 struct i40e_aqc_rx_ctl_reg_read_write { 810 __le32 reserved1; 811 __le32 address; 812 __le32 reserved2; 813 __le32 value; 814 }; 815 816 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 817 818 /* Add VSI (indirect 0x0210) 819 * this indirect command uses struct i40e_aqc_vsi_properties_data 820 * as the indirect buffer (128 bytes) 821 * 822 * Update VSI (indirect 0x211) 823 * uses the same data structure as Add VSI 824 * 825 * Get VSI (indirect 0x0212) 826 * uses the same completion and data structure as Add VSI 827 */ 828 struct i40e_aqc_add_get_update_vsi { 829 __le16 uplink_seid; 830 u8 connection_type; 831 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 832 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 833 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 834 u8 reserved1; 835 u8 vf_id; 836 u8 reserved2; 837 __le16 vsi_flags; 838 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 839 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 840 #define I40E_AQ_VSI_TYPE_VF 0x0 841 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 842 #define I40E_AQ_VSI_TYPE_PF 0x2 843 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 844 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 845 __le32 addr_high; 846 __le32 addr_low; 847 }; 848 849 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 850 851 struct i40e_aqc_add_get_update_vsi_completion { 852 __le16 seid; 853 __le16 vsi_number; 854 __le16 vsi_used; 855 __le16 vsi_free; 856 __le32 addr_high; 857 __le32 addr_low; 858 }; 859 860 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 861 862 struct i40e_aqc_vsi_properties_data { 863 /* first 96 byte are written by SW */ 864 __le16 valid_sections; 865 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 866 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 867 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 868 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 869 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 870 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 871 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 872 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 873 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 874 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 875 /* switch section */ 876 __le16 switch_id; /* 12bit id combined with flags below */ 877 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 878 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 879 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 880 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 881 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 882 u8 sw_reserved[2]; 883 /* security section */ 884 u8 sec_flags; 885 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 886 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 887 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 888 u8 sec_reserved; 889 /* VLAN section */ 890 __le16 pvid; /* VLANS include priority bits */ 891 __le16 fcoe_pvid; 892 u8 port_vlan_flags; 893 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 894 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 895 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 896 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 897 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 898 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 899 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 900 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 901 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 902 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 903 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 904 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 905 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 906 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 907 u8 pvlan_reserved[3]; 908 /* ingress egress up sections */ 909 __le32 ingress_table; /* bitmap, 3 bits per up */ 910 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 911 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 912 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 913 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 914 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 915 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 916 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 917 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 918 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 919 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 920 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 921 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 922 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 923 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 924 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 925 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 926 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 927 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 928 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 929 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 930 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 931 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 932 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 933 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 934 __le32 egress_table; /* same defines as for ingress table */ 935 /* cascaded PV section */ 936 __le16 cas_pv_tag; 937 u8 cas_pv_flags; 938 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 939 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 940 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 941 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 942 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 943 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 944 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 945 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 946 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 947 u8 cas_pv_reserved; 948 /* queue mapping section */ 949 __le16 mapping_flags; 950 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 951 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 952 __le16 queue_mapping[16]; 953 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 954 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 955 __le16 tc_mapping[8]; 956 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 957 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 958 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 959 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 960 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 961 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 962 /* queueing option section */ 963 u8 queueing_opt_flags; 964 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 965 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 966 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 967 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 968 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 969 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 970 u8 queueing_opt_reserved[3]; 971 /* scheduler section */ 972 u8 up_enable_bits; 973 u8 sched_reserved; 974 /* outer up section */ 975 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 976 u8 cmd_reserved[8]; 977 /* last 32 bytes are written by FW */ 978 __le16 qs_handle[8]; 979 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 980 __le16 stat_counter_idx; 981 __le16 sched_id; 982 u8 resp_reserved[12]; 983 }; 984 985 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 986 987 /* Add Port Virtualizer (direct 0x0220) 988 * also used for update PV (direct 0x0221) but only flags are used 989 * (IS_CTRL_PORT only works on add PV) 990 */ 991 struct i40e_aqc_add_update_pv { 992 __le16 command_flags; 993 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 994 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 995 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 996 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 997 __le16 uplink_seid; 998 __le16 connected_seid; 999 u8 reserved[10]; 1000 }; 1001 1002 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1003 1004 struct i40e_aqc_add_update_pv_completion { 1005 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1006 __le16 pv_seid; 1007 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1008 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1009 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1010 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1011 u8 reserved[14]; 1012 }; 1013 1014 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1015 1016 /* Get PV Params (direct 0x0222) 1017 * uses i40e_aqc_switch_seid for the descriptor 1018 */ 1019 1020 struct i40e_aqc_get_pv_params_completion { 1021 __le16 seid; 1022 __le16 default_stag; 1023 __le16 pv_flags; /* same flags as add_pv */ 1024 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1025 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1026 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1027 u8 reserved[8]; 1028 __le16 default_port_seid; 1029 }; 1030 1031 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1032 1033 /* Add VEB (direct 0x0230) */ 1034 struct i40e_aqc_add_veb { 1035 __le16 uplink_seid; 1036 __le16 downlink_seid; 1037 __le16 veb_flags; 1038 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1039 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1040 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1041 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1042 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1043 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1044 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1045 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1046 u8 enable_tcs; 1047 u8 reserved[9]; 1048 }; 1049 1050 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1051 1052 struct i40e_aqc_add_veb_completion { 1053 u8 reserved[6]; 1054 __le16 switch_seid; 1055 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1056 __le16 veb_seid; 1057 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1058 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1059 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1060 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1061 __le16 statistic_index; 1062 __le16 vebs_used; 1063 __le16 vebs_free; 1064 }; 1065 1066 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1067 1068 /* Get VEB Parameters (direct 0x0232) 1069 * uses i40e_aqc_switch_seid for the descriptor 1070 */ 1071 struct i40e_aqc_get_veb_parameters_completion { 1072 __le16 seid; 1073 __le16 switch_id; 1074 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1075 __le16 statistic_index; 1076 __le16 vebs_used; 1077 __le16 vebs_free; 1078 u8 reserved[4]; 1079 }; 1080 1081 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1082 1083 /* Delete Element (direct 0x0243) 1084 * uses the generic i40e_aqc_switch_seid 1085 */ 1086 1087 /* Add MAC-VLAN (indirect 0x0250) */ 1088 1089 /* used for the command for most vlan commands */ 1090 struct i40e_aqc_macvlan { 1091 __le16 num_addresses; 1092 __le16 seid[3]; 1093 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1094 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1095 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1096 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1097 __le32 addr_high; 1098 __le32 addr_low; 1099 }; 1100 1101 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1102 1103 /* indirect data for command and response */ 1104 struct i40e_aqc_add_macvlan_element_data { 1105 u8 mac_addr[6]; 1106 __le16 vlan_tag; 1107 __le16 flags; 1108 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1109 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1110 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1111 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1112 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1113 __le16 queue_number; 1114 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1115 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1116 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1117 /* response section */ 1118 u8 match_method; 1119 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1120 #define I40E_AQC_MM_HASH_MATCH 0x02 1121 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1122 u8 reserved1[3]; 1123 }; 1124 1125 struct i40e_aqc_add_remove_macvlan_completion { 1126 __le16 perfect_mac_used; 1127 __le16 perfect_mac_free; 1128 __le16 unicast_hash_free; 1129 __le16 multicast_hash_free; 1130 __le32 addr_high; 1131 __le32 addr_low; 1132 }; 1133 1134 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1135 1136 /* Remove MAC-VLAN (indirect 0x0251) 1137 * uses i40e_aqc_macvlan for the descriptor 1138 * data points to an array of num_addresses of elements 1139 */ 1140 1141 struct i40e_aqc_remove_macvlan_element_data { 1142 u8 mac_addr[6]; 1143 __le16 vlan_tag; 1144 u8 flags; 1145 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1146 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1147 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1148 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1149 u8 reserved[3]; 1150 /* reply section */ 1151 u8 error_code; 1152 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1153 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1154 u8 reply_reserved[3]; 1155 }; 1156 1157 /* Add VLAN (indirect 0x0252) 1158 * Remove VLAN (indirect 0x0253) 1159 * use the generic i40e_aqc_macvlan for the command 1160 */ 1161 struct i40e_aqc_add_remove_vlan_element_data { 1162 __le16 vlan_tag; 1163 u8 vlan_flags; 1164 /* flags for add VLAN */ 1165 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1166 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1167 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1168 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1169 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1170 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1171 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1172 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1173 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1174 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1175 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1176 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1177 /* flags for remove VLAN */ 1178 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1179 u8 reserved; 1180 u8 result; 1181 /* flags for add VLAN */ 1182 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1183 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1184 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1185 /* flags for remove VLAN */ 1186 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1187 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1188 u8 reserved1[3]; 1189 }; 1190 1191 struct i40e_aqc_add_remove_vlan_completion { 1192 u8 reserved[4]; 1193 __le16 vlans_used; 1194 __le16 vlans_free; 1195 __le32 addr_high; 1196 __le32 addr_low; 1197 }; 1198 1199 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1200 struct i40e_aqc_set_vsi_promiscuous_modes { 1201 __le16 promiscuous_flags; 1202 __le16 valid_flags; 1203 /* flags used for both fields above */ 1204 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1205 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1206 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1207 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1208 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1209 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1210 __le16 seid; 1211 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1212 __le16 vlan_tag; 1213 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1214 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1215 u8 reserved[8]; 1216 }; 1217 1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1219 1220 /* Add S/E-tag command (direct 0x0255) 1221 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1222 */ 1223 struct i40e_aqc_add_tag { 1224 __le16 flags; 1225 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1226 __le16 seid; 1227 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1228 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1229 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1230 __le16 tag; 1231 __le16 queue_number; 1232 u8 reserved[8]; 1233 }; 1234 1235 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1236 1237 struct i40e_aqc_add_remove_tag_completion { 1238 u8 reserved[12]; 1239 __le16 tags_used; 1240 __le16 tags_free; 1241 }; 1242 1243 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1244 1245 /* Remove S/E-tag command (direct 0x0256) 1246 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1247 */ 1248 struct i40e_aqc_remove_tag { 1249 __le16 seid; 1250 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1251 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1252 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1253 __le16 tag; 1254 u8 reserved[12]; 1255 }; 1256 1257 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1258 1259 /* Add multicast E-Tag (direct 0x0257) 1260 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1261 * and no external data 1262 */ 1263 struct i40e_aqc_add_remove_mcast_etag { 1264 __le16 pv_seid; 1265 __le16 etag; 1266 u8 num_unicast_etags; 1267 u8 reserved[3]; 1268 __le32 addr_high; /* address of array of 2-byte s-tags */ 1269 __le32 addr_low; 1270 }; 1271 1272 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1273 1274 struct i40e_aqc_add_remove_mcast_etag_completion { 1275 u8 reserved[4]; 1276 __le16 mcast_etags_used; 1277 __le16 mcast_etags_free; 1278 __le32 addr_high; 1279 __le32 addr_low; 1280 1281 }; 1282 1283 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1284 1285 /* Update S/E-Tag (direct 0x0259) */ 1286 struct i40e_aqc_update_tag { 1287 __le16 seid; 1288 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1289 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1290 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1291 __le16 old_tag; 1292 __le16 new_tag; 1293 u8 reserved[10]; 1294 }; 1295 1296 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1297 1298 struct i40e_aqc_update_tag_completion { 1299 u8 reserved[12]; 1300 __le16 tags_used; 1301 __le16 tags_free; 1302 }; 1303 1304 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1305 1306 /* Add Control Packet filter (direct 0x025A) 1307 * Remove Control Packet filter (direct 0x025B) 1308 * uses the i40e_aqc_add_oveb_cloud, 1309 * and the generic direct completion structure 1310 */ 1311 struct i40e_aqc_add_remove_control_packet_filter { 1312 u8 mac[6]; 1313 __le16 etype; 1314 __le16 flags; 1315 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1316 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1317 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1318 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1319 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1320 __le16 seid; 1321 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1322 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1323 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1324 __le16 queue; 1325 u8 reserved[2]; 1326 }; 1327 1328 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1329 1330 struct i40e_aqc_add_remove_control_packet_filter_completion { 1331 __le16 mac_etype_used; 1332 __le16 etype_used; 1333 __le16 mac_etype_free; 1334 __le16 etype_free; 1335 u8 reserved[8]; 1336 }; 1337 1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1339 1340 /* Add Cloud filters (indirect 0x025C) 1341 * Remove Cloud filters (indirect 0x025D) 1342 * uses the i40e_aqc_add_remove_cloud_filters, 1343 * and the generic indirect completion structure 1344 */ 1345 struct i40e_aqc_add_remove_cloud_filters { 1346 u8 num_filters; 1347 u8 reserved; 1348 __le16 seid; 1349 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1350 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1351 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1352 u8 big_buffer_flag; 1353 #define I40E_AQC_ADD_CLOUD_CMD_BB 1 1354 u8 reserved2[3]; 1355 __le32 addr_high; 1356 __le32 addr_low; 1357 }; 1358 1359 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1360 1361 struct i40e_aqc_cloud_filters_element_data { 1362 u8 outer_mac[6]; 1363 u8 inner_mac[6]; 1364 __le16 inner_vlan; 1365 union { 1366 struct { 1367 u8 reserved[12]; 1368 u8 data[4]; 1369 } v4; 1370 struct { 1371 u8 data[16]; 1372 } v6; 1373 struct { 1374 __le16 data[8]; 1375 } raw_v6; 1376 } ipaddr; 1377 __le16 flags; 1378 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1379 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1380 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1381 /* 0x0000 reserved */ 1382 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1383 /* 0x0002 reserved */ 1384 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1385 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1386 /* 0x0005 reserved */ 1387 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1388 /* 0x0007 reserved */ 1389 /* 0x0008 reserved */ 1390 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1391 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1392 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1393 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1394 /* 0x0010 to 0x0017 is for custom filters */ 1395 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ 1396 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ 1397 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ 1398 1399 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1400 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1401 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1402 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1403 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1404 1405 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1406 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1407 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1408 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1409 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1410 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1411 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1412 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1413 1414 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1415 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1416 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1417 1418 __le32 tenant_id; 1419 u8 reserved[4]; 1420 __le16 queue_number; 1421 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1422 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1423 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1424 u8 reserved2[14]; 1425 /* response section */ 1426 u8 allocation_result; 1427 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1428 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1429 u8 response_reserved[7]; 1430 }; 1431 1432 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); 1433 1434 /* i40e_aqc_cloud_filters_element_bb is used when 1435 * I40E_AQC_CLOUD_CMD_BB flag is set. 1436 */ 1437 struct i40e_aqc_cloud_filters_element_bb { 1438 struct i40e_aqc_cloud_filters_element_data element; 1439 u16 general_fields[32]; 1440 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 1441 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 1442 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 1443 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 1444 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 1445 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 1446 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 1447 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 1448 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 1449 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 1450 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 1451 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 1452 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 1453 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 1454 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 1455 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 1456 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 1457 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 1458 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 1459 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 1460 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 1461 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 1462 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 1463 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 1464 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 1465 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 1466 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 1467 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 1468 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 1469 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 1470 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 1471 }; 1472 1473 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); 1474 1475 struct i40e_aqc_remove_cloud_filters_completion { 1476 __le16 perfect_ovlan_used; 1477 __le16 perfect_ovlan_free; 1478 __le16 vlan_used; 1479 __le16 vlan_free; 1480 __le32 addr_high; 1481 __le32 addr_low; 1482 }; 1483 1484 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1485 1486 /* Replace filter Command 0x025F 1487 * uses the i40e_aqc_replace_cloud_filters, 1488 * and the generic indirect completion structure 1489 */ 1490 struct i40e_filter_data { 1491 u8 filter_type; 1492 u8 input[3]; 1493 }; 1494 1495 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); 1496 1497 struct i40e_aqc_replace_cloud_filters_cmd { 1498 u8 valid_flags; 1499 #define I40E_AQC_REPLACE_L1_FILTER 0x0 1500 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 1501 #define I40E_AQC_GET_CLOUD_FILTERS 0x2 1502 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 1503 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 1504 u8 old_filter_type; 1505 u8 new_filter_type; 1506 u8 tr_bit; 1507 u8 reserved[4]; 1508 __le32 addr_high; 1509 __le32 addr_low; 1510 }; 1511 1512 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); 1513 1514 struct i40e_aqc_replace_cloud_filters_cmd_buf { 1515 u8 data[32]; 1516 /* Filter type INPUT codes*/ 1517 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 1518 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) 1519 1520 /* Field Vector offsets */ 1521 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 1522 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 1523 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 1524 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 1525 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 1526 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 1527 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 1528 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 1529 /* big FLU */ 1530 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 1531 /* big FLU */ 1532 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 1533 1534 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 1535 struct i40e_filter_data filters[8]; 1536 }; 1537 1538 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); 1539 1540 /* Add Mirror Rule (indirect or direct 0x0260) 1541 * Delete Mirror Rule (indirect or direct 0x0261) 1542 * note: some rule types (4,5) do not use an external buffer. 1543 * take care to set the flags correctly. 1544 */ 1545 struct i40e_aqc_add_delete_mirror_rule { 1546 __le16 seid; 1547 __le16 rule_type; 1548 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1549 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1550 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1551 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1552 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1553 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1554 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1555 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1556 __le16 num_entries; 1557 __le16 destination; /* VSI for add, rule id for delete */ 1558 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1559 __le32 addr_low; 1560 }; 1561 1562 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1563 1564 struct i40e_aqc_add_delete_mirror_rule_completion { 1565 u8 reserved[2]; 1566 __le16 rule_id; /* only used on add */ 1567 __le16 mirror_rules_used; 1568 __le16 mirror_rules_free; 1569 __le32 addr_high; 1570 __le32 addr_low; 1571 }; 1572 1573 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1574 1575 /* Dynamic Device Personalization */ 1576 struct i40e_aqc_write_personalization_profile { 1577 u8 flags; 1578 u8 reserved[3]; 1579 __le32 profile_track_id; 1580 __le32 addr_high; 1581 __le32 addr_low; 1582 }; 1583 1584 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); 1585 1586 struct i40e_aqc_write_ddp_resp { 1587 __le32 error_offset; 1588 __le32 error_info; 1589 __le32 addr_high; 1590 __le32 addr_low; 1591 }; 1592 1593 struct i40e_aqc_get_applied_profiles { 1594 u8 flags; 1595 #define I40E_AQC_GET_DDP_GET_CONF 0x1 1596 #define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 1597 u8 rsv[3]; 1598 __le32 reserved; 1599 __le32 addr_high; 1600 __le32 addr_low; 1601 }; 1602 1603 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); 1604 1605 /* DCB 0x03xx*/ 1606 1607 /* PFC Ignore (direct 0x0301) 1608 * the command and response use the same descriptor structure 1609 */ 1610 struct i40e_aqc_pfc_ignore { 1611 u8 tc_bitmap; 1612 u8 command_flags; /* unused on response */ 1613 #define I40E_AQC_PFC_IGNORE_SET 0x80 1614 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1615 u8 reserved[14]; 1616 }; 1617 1618 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1619 1620 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1621 * with no parameters 1622 */ 1623 1624 /* TX scheduler 0x04xx */ 1625 1626 /* Almost all the indirect commands use 1627 * this generic struct to pass the SEID in param0 1628 */ 1629 struct i40e_aqc_tx_sched_ind { 1630 __le16 vsi_seid; 1631 u8 reserved[6]; 1632 __le32 addr_high; 1633 __le32 addr_low; 1634 }; 1635 1636 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1637 1638 /* Several commands respond with a set of queue set handles */ 1639 struct i40e_aqc_qs_handles_resp { 1640 __le16 qs_handles[8]; 1641 }; 1642 1643 /* Configure VSI BW limits (direct 0x0400) */ 1644 struct i40e_aqc_configure_vsi_bw_limit { 1645 __le16 vsi_seid; 1646 u8 reserved[2]; 1647 __le16 credit; 1648 u8 reserved1[2]; 1649 u8 max_credit; /* 0-3, limit = 2^max */ 1650 u8 reserved2[7]; 1651 }; 1652 1653 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1654 1655 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1656 * responds with i40e_aqc_qs_handles_resp 1657 */ 1658 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1659 u8 tc_valid_bits; 1660 u8 reserved[15]; 1661 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1662 1663 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1664 __le16 tc_bw_max[2]; 1665 u8 reserved1[28]; 1666 }; 1667 1668 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1669 1670 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1671 * responds with i40e_aqc_qs_handles_resp 1672 */ 1673 struct i40e_aqc_configure_vsi_tc_bw_data { 1674 u8 tc_valid_bits; 1675 u8 reserved[3]; 1676 u8 tc_bw_credits[8]; 1677 u8 reserved1[4]; 1678 __le16 qs_handles[8]; 1679 }; 1680 1681 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1682 1683 /* Query vsi bw configuration (indirect 0x0408) */ 1684 struct i40e_aqc_query_vsi_bw_config_resp { 1685 u8 tc_valid_bits; 1686 u8 tc_suspended_bits; 1687 u8 reserved[14]; 1688 __le16 qs_handles[8]; 1689 u8 reserved1[4]; 1690 __le16 port_bw_limit; 1691 u8 reserved2[2]; 1692 u8 max_bw; /* 0-3, limit = 2^max */ 1693 u8 reserved3[23]; 1694 }; 1695 1696 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1697 1698 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1699 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1700 u8 tc_valid_bits; 1701 u8 reserved[3]; 1702 u8 share_credits[8]; 1703 __le16 credits[8]; 1704 1705 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1706 __le16 tc_bw_max[2]; 1707 }; 1708 1709 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1710 1711 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1712 struct i40e_aqc_configure_switching_comp_bw_limit { 1713 __le16 seid; 1714 u8 reserved[2]; 1715 __le16 credit; 1716 u8 reserved1[2]; 1717 u8 max_bw; /* 0-3, limit = 2^max */ 1718 u8 reserved2[7]; 1719 }; 1720 1721 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1722 1723 /* Enable Physical Port ETS (indirect 0x0413) 1724 * Modify Physical Port ETS (indirect 0x0414) 1725 * Disable Physical Port ETS (indirect 0x0415) 1726 */ 1727 struct i40e_aqc_configure_switching_comp_ets_data { 1728 u8 reserved[4]; 1729 u8 tc_valid_bits; 1730 u8 seepage; 1731 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1732 u8 tc_strict_priority_flags; 1733 u8 reserved1[17]; 1734 u8 tc_bw_share_credits[8]; 1735 u8 reserved2[96]; 1736 }; 1737 1738 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1739 1740 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1741 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1742 u8 tc_valid_bits; 1743 u8 reserved[15]; 1744 __le16 tc_bw_credit[8]; 1745 1746 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1747 __le16 tc_bw_max[2]; 1748 u8 reserved1[28]; 1749 }; 1750 1751 I40E_CHECK_STRUCT_LEN(0x40, 1752 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1753 1754 /* Configure Switching Component Bandwidth Allocation per Tc 1755 * (indirect 0x0417) 1756 */ 1757 struct i40e_aqc_configure_switching_comp_bw_config_data { 1758 u8 tc_valid_bits; 1759 u8 reserved[2]; 1760 u8 absolute_credits; /* bool */ 1761 u8 tc_bw_share_credits[8]; 1762 u8 reserved1[20]; 1763 }; 1764 1765 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1766 1767 /* Query Switching Component Configuration (indirect 0x0418) */ 1768 struct i40e_aqc_query_switching_comp_ets_config_resp { 1769 u8 tc_valid_bits; 1770 u8 reserved[35]; 1771 __le16 port_bw_limit; 1772 u8 reserved1[2]; 1773 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1774 u8 reserved2[23]; 1775 }; 1776 1777 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1778 1779 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1780 struct i40e_aqc_query_port_ets_config_resp { 1781 u8 reserved[4]; 1782 u8 tc_valid_bits; 1783 u8 reserved1; 1784 u8 tc_strict_priority_bits; 1785 u8 reserved2; 1786 u8 tc_bw_share_credits[8]; 1787 __le16 tc_bw_limits[8]; 1788 1789 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1790 __le16 tc_bw_max[2]; 1791 u8 reserved3[32]; 1792 }; 1793 1794 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1795 1796 /* Query Switching Component Bandwidth Allocation per Traffic Type 1797 * (indirect 0x041A) 1798 */ 1799 struct i40e_aqc_query_switching_comp_bw_config_resp { 1800 u8 tc_valid_bits; 1801 u8 reserved[2]; 1802 u8 absolute_credits_enable; /* bool */ 1803 u8 tc_bw_share_credits[8]; 1804 __le16 tc_bw_limits[8]; 1805 1806 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1807 __le16 tc_bw_max[2]; 1808 }; 1809 1810 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1811 1812 /* Suspend/resume port TX traffic 1813 * (direct 0x041B and 0x041C) uses the generic SEID struct 1814 */ 1815 1816 /* Configure partition BW 1817 * (indirect 0x041D) 1818 */ 1819 struct i40e_aqc_configure_partition_bw_data { 1820 __le16 pf_valid_bits; 1821 u8 min_bw[16]; /* guaranteed bandwidth */ 1822 u8 max_bw[16]; /* bandwidth limit */ 1823 }; 1824 1825 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1826 1827 /* Get and set the active HMC resource profile and status. 1828 * (direct 0x0500) and (direct 0x0501) 1829 */ 1830 struct i40e_aq_get_set_hmc_resource_profile { 1831 u8 pm_profile; 1832 u8 pe_vf_enabled; 1833 u8 reserved[14]; 1834 }; 1835 1836 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1837 1838 enum i40e_aq_hmc_profile { 1839 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1840 I40E_HMC_PROFILE_DEFAULT = 1, 1841 I40E_HMC_PROFILE_FAVOR_VF = 2, 1842 I40E_HMC_PROFILE_EQUAL = 3, 1843 }; 1844 1845 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1846 1847 /* set in param0 for get phy abilities to report qualified modules */ 1848 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1849 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1850 1851 enum i40e_aq_phy_type { 1852 I40E_PHY_TYPE_SGMII = 0x0, 1853 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1854 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1855 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1856 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1857 I40E_PHY_TYPE_XAUI = 0x5, 1858 I40E_PHY_TYPE_XFI = 0x6, 1859 I40E_PHY_TYPE_SFI = 0x7, 1860 I40E_PHY_TYPE_XLAUI = 0x8, 1861 I40E_PHY_TYPE_XLPPI = 0x9, 1862 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1863 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1864 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1865 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1866 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1867 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1868 I40E_PHY_TYPE_100BASE_TX = 0x11, 1869 I40E_PHY_TYPE_1000BASE_T = 0x12, 1870 I40E_PHY_TYPE_10GBASE_T = 0x13, 1871 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1872 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1873 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1874 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1875 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1876 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1877 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1878 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1879 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1880 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1881 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1882 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1883 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1884 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1885 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1886 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1887 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1888 I40E_PHY_TYPE_MAX, 1889 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1890 I40E_PHY_TYPE_EMPTY = 0xFE, 1891 I40E_PHY_TYPE_DEFAULT = 0xFF, 1892 }; 1893 1894 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1895 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1896 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1897 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1898 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1899 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1900 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1901 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1902 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1903 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1904 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1905 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1906 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1907 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1908 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1909 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1910 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1911 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1912 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1913 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1914 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1915 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1916 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1917 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1918 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1919 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1920 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1921 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1922 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1923 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1924 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1925 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1926 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1927 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1928 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1929 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) 1930 1931 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1932 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1933 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1934 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1935 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1936 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1937 1938 enum i40e_aq_link_speed { 1939 I40E_LINK_SPEED_UNKNOWN = 0, 1940 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), 1941 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), 1942 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), 1943 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), 1944 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), 1945 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), 1946 }; 1947 1948 struct i40e_aqc_module_desc { 1949 u8 oui[3]; 1950 u8 reserved1; 1951 u8 part_number[16]; 1952 u8 revision[4]; 1953 u8 reserved2[8]; 1954 }; 1955 1956 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1957 1958 struct i40e_aq_get_phy_abilities_resp { 1959 __le32 phy_type; /* bitmap using the above enum for offsets */ 1960 u8 link_speed; /* bitmap using the above enum bit patterns */ 1961 u8 abilities; 1962 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1963 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1964 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1965 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1966 #define I40E_AQ_PHY_AN_ENABLED 0x10 1967 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1968 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1969 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1970 __le16 eee_capability; 1971 #define I40E_AQ_EEE_100BASE_TX 0x0002 1972 #define I40E_AQ_EEE_1000BASE_T 0x0004 1973 #define I40E_AQ_EEE_10GBASE_T 0x0008 1974 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1975 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1976 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1977 __le32 eeer_val; 1978 u8 d3_lpan; 1979 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1980 u8 phy_type_ext; 1981 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1982 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1983 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1984 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1985 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1986 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1987 u8 fec_cfg_curr_mod_ext_info; 1988 #define I40E_AQ_ENABLE_FEC_KR 0x01 1989 #define I40E_AQ_ENABLE_FEC_RS 0x02 1990 #define I40E_AQ_REQUEST_FEC_KR 0x04 1991 #define I40E_AQ_REQUEST_FEC_RS 0x08 1992 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1993 #define I40E_AQ_FEC 1994 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1995 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1996 1997 u8 ext_comp_code; 1998 u8 phy_id[4]; 1999 u8 module_type[3]; 2000 u8 qualified_module_count; 2001 #define I40E_AQ_PHY_MAX_QMS 16 2002 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 2003 }; 2004 2005 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 2006 2007 /* Set PHY Config (direct 0x0601) */ 2008 struct i40e_aq_set_phy_config { /* same bits as above in all */ 2009 __le32 phy_type; 2010 u8 link_speed; 2011 u8 abilities; 2012 /* bits 0-2 use the values from get_phy_abilities_resp */ 2013 #define I40E_AQ_PHY_ENABLE_LINK 0x08 2014 #define I40E_AQ_PHY_ENABLE_AN 0x10 2015 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 2016 __le16 eee_capability; 2017 __le32 eeer; 2018 u8 low_power_ctrl; 2019 u8 phy_type_ext; 2020 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 2021 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 2022 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 2023 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 2024 u8 fec_config; 2025 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 2026 #define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 2027 #define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 2028 #define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 2029 #define I40E_AQ_SET_FEC_AUTO BIT(4) 2030 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 2031 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 2032 u8 reserved; 2033 }; 2034 2035 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 2036 2037 /* Set MAC Config command data structure (direct 0x0603) */ 2038 struct i40e_aq_set_mac_config { 2039 __le16 max_frame_size; 2040 u8 params; 2041 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 2042 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 2043 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 2044 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 2045 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 2046 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 2047 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 2048 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 2049 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 2050 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 2051 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 2052 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 2053 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 2054 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 2055 u8 tx_timer_priority; /* bitmap */ 2056 __le16 tx_timer_value; 2057 __le16 fc_refresh_threshold; 2058 u8 reserved[8]; 2059 }; 2060 2061 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 2062 2063 /* Restart Auto-Negotiation (direct 0x605) */ 2064 struct i40e_aqc_set_link_restart_an { 2065 u8 command; 2066 #define I40E_AQ_PHY_RESTART_AN 0x02 2067 #define I40E_AQ_PHY_LINK_ENABLE 0x04 2068 u8 reserved[15]; 2069 }; 2070 2071 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 2072 2073 /* Get Link Status cmd & response data structure (direct 0x0607) */ 2074 struct i40e_aqc_get_link_status { 2075 __le16 command_flags; /* only field set on command */ 2076 #define I40E_AQ_LSE_MASK 0x3 2077 #define I40E_AQ_LSE_NOP 0x0 2078 #define I40E_AQ_LSE_DISABLE 0x2 2079 #define I40E_AQ_LSE_ENABLE 0x3 2080 /* only response uses this flag */ 2081 #define I40E_AQ_LSE_IS_ENABLED 0x1 2082 u8 phy_type; /* i40e_aq_phy_type */ 2083 u8 link_speed; /* i40e_aq_link_speed */ 2084 u8 link_info; 2085 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 2086 #define I40E_AQ_LINK_UP_FUNCTION 0x01 2087 #define I40E_AQ_LINK_FAULT 0x02 2088 #define I40E_AQ_LINK_FAULT_TX 0x04 2089 #define I40E_AQ_LINK_FAULT_RX 0x08 2090 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 2091 #define I40E_AQ_LINK_UP_PORT 0x20 2092 #define I40E_AQ_MEDIA_AVAILABLE 0x40 2093 #define I40E_AQ_SIGNAL_DETECT 0x80 2094 u8 an_info; 2095 #define I40E_AQ_AN_COMPLETED 0x01 2096 #define I40E_AQ_LP_AN_ABILITY 0x02 2097 #define I40E_AQ_PD_FAULT 0x04 2098 #define I40E_AQ_FEC_EN 0x08 2099 #define I40E_AQ_PHY_LOW_POWER 0x10 2100 #define I40E_AQ_LINK_PAUSE_TX 0x20 2101 #define I40E_AQ_LINK_PAUSE_RX 0x40 2102 #define I40E_AQ_QUALIFIED_MODULE 0x80 2103 u8 ext_info; 2104 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2105 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2106 #define I40E_AQ_LINK_TX_SHIFT 0x02 2107 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2108 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2109 #define I40E_AQ_LINK_TX_DRAINED 0x01 2110 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2111 #define I40E_AQ_LINK_FORCED_40G 0x10 2112 /* 25G Error Codes */ 2113 #define I40E_AQ_25G_NO_ERR 0X00 2114 #define I40E_AQ_25G_NOT_PRESENT 0X01 2115 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2116 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2117 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2118 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2119 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2120 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2121 #define I40E_AQ_LOOPBACK_MASK 0x07 2122 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2123 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2124 __le16 max_frame_size; 2125 u8 config; 2126 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2127 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2128 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2129 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2130 union { 2131 struct { 2132 u8 power_desc; 2133 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2134 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2135 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2136 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2137 #define I40E_AQ_PWR_CLASS_MASK 0x03 2138 u8 reserved[4]; 2139 }; 2140 struct { 2141 u8 link_type[4]; 2142 u8 link_type_ext; 2143 }; 2144 }; 2145 }; 2146 2147 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2148 2149 /* Set event mask command (direct 0x613) */ 2150 struct i40e_aqc_set_phy_int_mask { 2151 u8 reserved[8]; 2152 __le16 event_mask; 2153 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2154 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2155 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2156 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2157 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2158 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2159 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2160 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2161 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2162 u8 reserved1[6]; 2163 }; 2164 2165 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2166 2167 /* Get Local AN advt register (direct 0x0614) 2168 * Set Local AN advt register (direct 0x0615) 2169 * Get Link Partner AN advt register (direct 0x0616) 2170 */ 2171 struct i40e_aqc_an_advt_reg { 2172 __le32 local_an_reg0; 2173 __le16 local_an_reg1; 2174 u8 reserved[10]; 2175 }; 2176 2177 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2178 2179 /* Set Loopback mode (0x0618) */ 2180 struct i40e_aqc_set_lb_mode { 2181 __le16 lb_mode; 2182 #define I40E_AQ_LB_PHY_LOCAL 0x01 2183 #define I40E_AQ_LB_PHY_REMOTE 0x02 2184 #define I40E_AQ_LB_MAC_LOCAL 0x04 2185 u8 reserved[14]; 2186 }; 2187 2188 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2189 2190 /* Set PHY Debug command (0x0622) */ 2191 struct i40e_aqc_set_phy_debug { 2192 u8 command_flags; 2193 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2194 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2195 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2196 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2197 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2198 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2199 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2200 /* Disable link manageability on a single port */ 2201 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2202 /* Disable link manageability on all ports */ 2203 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2204 u8 reserved[15]; 2205 }; 2206 2207 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2208 2209 enum i40e_aq_phy_reg_type { 2210 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2211 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2212 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2213 }; 2214 2215 /* Run PHY Activity (0x0626) */ 2216 struct i40e_aqc_run_phy_activity { 2217 __le16 activity_id; 2218 u8 flags; 2219 u8 reserved1; 2220 __le32 control; 2221 __le32 data; 2222 u8 reserved2[4]; 2223 }; 2224 2225 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2226 2227 /* Set PHY Register command (0x0628) */ 2228 /* Get PHY Register command (0x0629) */ 2229 struct i40e_aqc_phy_register_access { 2230 u8 phy_interface; 2231 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2232 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2233 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2234 u8 dev_address; 2235 u8 reserved1[2]; 2236 __le32 reg_address; 2237 __le32 reg_value; 2238 u8 reserved2[4]; 2239 }; 2240 2241 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2242 2243 /* NVM Read command (indirect 0x0701) 2244 * NVM Erase commands (direct 0x0702) 2245 * NVM Update commands (indirect 0x0703) 2246 */ 2247 struct i40e_aqc_nvm_update { 2248 u8 command_flags; 2249 #define I40E_AQ_NVM_LAST_CMD 0x01 2250 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2251 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2252 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2253 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2254 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2255 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2256 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2257 u8 module_pointer; 2258 __le16 length; 2259 __le32 offset; 2260 __le32 addr_high; 2261 __le32 addr_low; 2262 }; 2263 2264 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2265 2266 /* NVM Config Read (indirect 0x0704) */ 2267 struct i40e_aqc_nvm_config_read { 2268 __le16 cmd_flags; 2269 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2270 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2271 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2272 __le16 element_count; 2273 __le16 element_id; /* Feature/field ID */ 2274 __le16 element_id_msw; /* MSWord of field ID */ 2275 __le32 address_high; 2276 __le32 address_low; 2277 }; 2278 2279 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2280 2281 /* NVM Config Write (indirect 0x0705) */ 2282 struct i40e_aqc_nvm_config_write { 2283 __le16 cmd_flags; 2284 __le16 element_count; 2285 u8 reserved[4]; 2286 __le32 address_high; 2287 __le32 address_low; 2288 }; 2289 2290 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2291 2292 /* Used for 0x0704 as well as for 0x0705 commands */ 2293 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2294 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2295 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2296 #define I40E_AQ_ANVM_FEATURE 0 2297 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) 2298 struct i40e_aqc_nvm_config_data_feature { 2299 __le16 feature_id; 2300 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2301 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2302 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2303 __le16 feature_options; 2304 __le16 feature_selection; 2305 }; 2306 2307 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2308 2309 struct i40e_aqc_nvm_config_data_immediate_field { 2310 __le32 field_id; 2311 __le32 field_value; 2312 __le16 field_options; 2313 __le16 reserved; 2314 }; 2315 2316 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2317 2318 /* OEM Post Update (indirect 0x0720) 2319 * no command data struct used 2320 */ 2321 struct i40e_aqc_nvm_oem_post_update { 2322 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2323 u8 sel_data; 2324 u8 reserved[7]; 2325 }; 2326 2327 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2328 2329 struct i40e_aqc_nvm_oem_post_update_buffer { 2330 u8 str_len; 2331 u8 dev_addr; 2332 __le16 eeprom_addr; 2333 u8 data[36]; 2334 }; 2335 2336 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2337 2338 /* Thermal Sensor (indirect 0x0721) 2339 * read or set thermal sensor configs and values 2340 * takes a sensor and command specific data buffer, not detailed here 2341 */ 2342 struct i40e_aqc_thermal_sensor { 2343 u8 sensor_action; 2344 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2345 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2346 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2347 u8 reserved[7]; 2348 __le32 addr_high; 2349 __le32 addr_low; 2350 }; 2351 2352 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2353 2354 /* Send to PF command (indirect 0x0801) id is only used by PF 2355 * Send to VF command (indirect 0x0802) id is only used by PF 2356 * Send to Peer PF command (indirect 0x0803) 2357 */ 2358 struct i40e_aqc_pf_vf_message { 2359 __le32 id; 2360 u8 reserved[4]; 2361 __le32 addr_high; 2362 __le32 addr_low; 2363 }; 2364 2365 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2366 2367 /* Alternate structure */ 2368 2369 /* Direct write (direct 0x0900) 2370 * Direct read (direct 0x0902) 2371 */ 2372 struct i40e_aqc_alternate_write { 2373 __le32 address0; 2374 __le32 data0; 2375 __le32 address1; 2376 __le32 data1; 2377 }; 2378 2379 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2380 2381 /* Indirect write (indirect 0x0901) 2382 * Indirect read (indirect 0x0903) 2383 */ 2384 2385 struct i40e_aqc_alternate_ind_write { 2386 __le32 address; 2387 __le32 length; 2388 __le32 addr_high; 2389 __le32 addr_low; 2390 }; 2391 2392 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2393 2394 /* Done alternate write (direct 0x0904) 2395 * uses i40e_aq_desc 2396 */ 2397 struct i40e_aqc_alternate_write_done { 2398 __le16 cmd_flags; 2399 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2400 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2401 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2402 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2403 u8 reserved[14]; 2404 }; 2405 2406 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2407 2408 /* Set OEM mode (direct 0x0905) */ 2409 struct i40e_aqc_alternate_set_mode { 2410 __le32 mode; 2411 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2412 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2413 u8 reserved[12]; 2414 }; 2415 2416 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2417 2418 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2419 2420 /* async events 0x10xx */ 2421 2422 /* Lan Queue Overflow Event (direct, 0x1001) */ 2423 struct i40e_aqc_lan_overflow { 2424 __le32 prtdcb_rupto; 2425 __le32 otx_ctl; 2426 u8 reserved[8]; 2427 }; 2428 2429 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2430 2431 /* Get LLDP MIB (indirect 0x0A00) */ 2432 struct i40e_aqc_lldp_get_mib { 2433 u8 type; 2434 u8 reserved1; 2435 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2436 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2437 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2438 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2439 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2440 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2441 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2442 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2443 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2444 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2445 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2446 __le16 local_len; 2447 __le16 remote_len; 2448 u8 reserved2[2]; 2449 __le32 addr_high; 2450 __le32 addr_low; 2451 }; 2452 2453 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2454 2455 /* Configure LLDP MIB Change Event (direct 0x0A01) 2456 * also used for the event (with type in the command field) 2457 */ 2458 struct i40e_aqc_lldp_update_mib { 2459 u8 command; 2460 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2461 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2462 u8 reserved[7]; 2463 __le32 addr_high; 2464 __le32 addr_low; 2465 }; 2466 2467 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2468 2469 /* Add LLDP TLV (indirect 0x0A02) 2470 * Delete LLDP TLV (indirect 0x0A04) 2471 */ 2472 struct i40e_aqc_lldp_add_tlv { 2473 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2474 u8 reserved1[1]; 2475 __le16 len; 2476 u8 reserved2[4]; 2477 __le32 addr_high; 2478 __le32 addr_low; 2479 }; 2480 2481 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2482 2483 /* Update LLDP TLV (indirect 0x0A03) */ 2484 struct i40e_aqc_lldp_update_tlv { 2485 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2486 u8 reserved; 2487 __le16 old_len; 2488 __le16 new_offset; 2489 __le16 new_len; 2490 __le32 addr_high; 2491 __le32 addr_low; 2492 }; 2493 2494 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2495 2496 /* Stop LLDP (direct 0x0A05) */ 2497 struct i40e_aqc_lldp_stop { 2498 u8 command; 2499 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2500 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2501 u8 reserved[15]; 2502 }; 2503 2504 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2505 2506 /* Start LLDP (direct 0x0A06) */ 2507 2508 struct i40e_aqc_lldp_start { 2509 u8 command; 2510 #define I40E_AQ_LLDP_AGENT_START 0x1 2511 u8 reserved[15]; 2512 }; 2513 2514 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2515 2516 /* Set DCB (direct 0x0303) */ 2517 struct i40e_aqc_set_dcb_parameters { 2518 u8 command; 2519 #define I40E_AQ_DCB_SET_AGENT 0x1 2520 #define I40E_DCB_VALID 0x1 2521 u8 valid_flags; 2522 u8 reserved[14]; 2523 }; 2524 2525 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2526 2527 /* Get CEE DCBX Oper Config (0x0A07) 2528 * uses the generic descriptor struct 2529 * returns below as indirect response 2530 */ 2531 2532 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2533 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2534 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2535 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2536 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2537 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2538 2539 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2540 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2541 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2542 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2543 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2544 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2545 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2546 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2547 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2548 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2549 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2550 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2551 2552 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2553 * word boundary layout issues, which the Linux compilers silently deal 2554 * with by adding padding, making the actual struct larger than designed. 2555 * However, the FW compiler for the NIC is less lenient and complains 2556 * about the struct. Hence, the struct defined here has an extra byte in 2557 * fields reserved3 and reserved4 to directly acknowledge that padding, 2558 * and the new length is used in the length check macro. 2559 */ 2560 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2561 u8 reserved1; 2562 u8 oper_num_tc; 2563 u8 oper_prio_tc[4]; 2564 u8 reserved2; 2565 u8 oper_tc_bw[8]; 2566 u8 oper_pfc_en; 2567 u8 reserved3[2]; 2568 __le16 oper_app_prio; 2569 u8 reserved4[2]; 2570 __le16 tlv_status; 2571 }; 2572 2573 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2574 2575 struct i40e_aqc_get_cee_dcb_cfg_resp { 2576 u8 oper_num_tc; 2577 u8 oper_prio_tc[4]; 2578 u8 oper_tc_bw[8]; 2579 u8 oper_pfc_en; 2580 __le16 oper_app_prio; 2581 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2582 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2583 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2584 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2585 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2586 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2587 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2588 __le32 tlv_status; 2589 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2590 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2591 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2592 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2593 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2594 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2595 u8 reserved[12]; 2596 }; 2597 2598 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2599 2600 /* Set Local LLDP MIB (indirect 0x0A08) 2601 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2602 */ 2603 struct i40e_aqc_lldp_set_local_mib { 2604 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2605 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK BIT(SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2606 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2607 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2608 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK \ 2609 BIT(SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2610 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2611 u8 type; 2612 u8 reserved0; 2613 __le16 length; 2614 u8 reserved1[4]; 2615 __le32 address_high; 2616 __le32 address_low; 2617 }; 2618 2619 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2620 2621 /* Stop/Start LLDP Agent (direct 0x0A09) 2622 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2623 */ 2624 struct i40e_aqc_lldp_stop_start_specific_agent { 2625 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2626 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2627 BIT(I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2628 u8 command; 2629 u8 reserved[15]; 2630 }; 2631 2632 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2633 2634 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2635 struct i40e_aqc_add_udp_tunnel { 2636 __le16 udp_port; 2637 u8 reserved0[3]; 2638 u8 protocol_type; 2639 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2640 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2641 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2642 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2643 u8 reserved1[10]; 2644 }; 2645 2646 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2647 2648 struct i40e_aqc_add_udp_tunnel_completion { 2649 __le16 udp_port; 2650 u8 filter_entry_index; 2651 u8 multiple_pfs; 2652 #define I40E_AQC_SINGLE_PF 0x0 2653 #define I40E_AQC_MULTIPLE_PFS 0x1 2654 u8 total_filters; 2655 u8 reserved[11]; 2656 }; 2657 2658 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2659 2660 /* remove UDP Tunnel command (0x0B01) */ 2661 struct i40e_aqc_remove_udp_tunnel { 2662 u8 reserved[2]; 2663 u8 index; /* 0 to 15 */ 2664 u8 reserved2[13]; 2665 }; 2666 2667 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2668 2669 struct i40e_aqc_del_udp_tunnel_completion { 2670 __le16 udp_port; 2671 u8 index; /* 0 to 15 */ 2672 u8 multiple_pfs; 2673 u8 total_filters_used; 2674 u8 reserved1[11]; 2675 }; 2676 2677 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2678 2679 struct i40e_aqc_get_set_rss_key { 2680 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) 2681 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2682 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2683 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2684 __le16 vsi_id; 2685 u8 reserved[6]; 2686 __le32 addr_high; 2687 __le32 addr_low; 2688 }; 2689 2690 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2691 2692 struct i40e_aqc_get_set_rss_key_data { 2693 u8 standard_rss_key[0x28]; 2694 u8 extended_hash_key[0xc]; 2695 }; 2696 2697 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2698 2699 struct i40e_aqc_get_set_rss_lut { 2700 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) 2701 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2702 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2703 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2704 __le16 vsi_id; 2705 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2706 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2707 2708 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2709 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2710 __le16 flags; 2711 u8 reserved[4]; 2712 __le32 addr_high; 2713 __le32 addr_low; 2714 }; 2715 2716 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2717 2718 /* tunnel key structure 0x0B10 */ 2719 2720 struct i40e_aqc_tunnel_key_structure { 2721 u8 key1_off; 2722 u8 key2_off; 2723 u8 key1_len; /* 0 to 15 */ 2724 u8 key2_len; /* 0 to 15 */ 2725 u8 flags; 2726 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2727 /* response flags */ 2728 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2729 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2730 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2731 u8 network_key_index; 2732 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2733 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2734 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2735 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2736 u8 reserved[10]; 2737 }; 2738 2739 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2740 2741 /* OEM mode commands (direct 0xFE0x) */ 2742 struct i40e_aqc_oem_param_change { 2743 __le32 param_type; 2744 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2745 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2746 #define I40E_AQ_OEM_PARAM_MAC 2 2747 __le32 param_value1; 2748 __le16 param_value2; 2749 u8 reserved[6]; 2750 }; 2751 2752 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2753 2754 struct i40e_aqc_oem_state_change { 2755 __le32 state; 2756 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2757 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2758 u8 reserved[12]; 2759 }; 2760 2761 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2762 2763 /* Initialize OCSD (0xFE02, direct) */ 2764 struct i40e_aqc_opc_oem_ocsd_initialize { 2765 u8 type_status; 2766 u8 reserved1[3]; 2767 __le32 ocsd_memory_block_addr_high; 2768 __le32 ocsd_memory_block_addr_low; 2769 __le32 requested_update_interval; 2770 }; 2771 2772 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2773 2774 /* Initialize OCBB (0xFE03, direct) */ 2775 struct i40e_aqc_opc_oem_ocbb_initialize { 2776 u8 type_status; 2777 u8 reserved1[3]; 2778 __le32 ocbb_memory_block_addr_high; 2779 __le32 ocbb_memory_block_addr_low; 2780 u8 reserved2[4]; 2781 }; 2782 2783 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2784 2785 /* debug commands */ 2786 2787 /* get device id (0xFF00) uses the generic structure */ 2788 2789 /* set test more (0xFF01, internal) */ 2790 2791 struct i40e_acq_set_test_mode { 2792 u8 mode; 2793 #define I40E_AQ_TEST_PARTIAL 0 2794 #define I40E_AQ_TEST_FULL 1 2795 #define I40E_AQ_TEST_NVM 2 2796 u8 reserved[3]; 2797 u8 command; 2798 #define I40E_AQ_TEST_OPEN 0 2799 #define I40E_AQ_TEST_CLOSE 1 2800 #define I40E_AQ_TEST_INC 2 2801 u8 reserved2[3]; 2802 __le32 address_high; 2803 __le32 address_low; 2804 }; 2805 2806 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2807 2808 /* Debug Read Register command (0xFF03) 2809 * Debug Write Register command (0xFF04) 2810 */ 2811 struct i40e_aqc_debug_reg_read_write { 2812 __le32 reserved; 2813 __le32 address; 2814 __le32 value_high; 2815 __le32 value_low; 2816 }; 2817 2818 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2819 2820 /* Scatter/gather Reg Read (indirect 0xFF05) 2821 * Scatter/gather Reg Write (indirect 0xFF06) 2822 */ 2823 2824 /* i40e_aq_desc is used for the command */ 2825 struct i40e_aqc_debug_reg_sg_element_data { 2826 __le32 address; 2827 __le32 value; 2828 }; 2829 2830 /* Debug Modify register (direct 0xFF07) */ 2831 struct i40e_aqc_debug_modify_reg { 2832 __le32 address; 2833 __le32 value; 2834 __le32 clear_mask; 2835 __le32 set_mask; 2836 }; 2837 2838 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2839 2840 /* dump internal data (0xFF08, indirect) */ 2841 2842 #define I40E_AQ_CLUSTER_ID_AUX 0 2843 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2844 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2845 #define I40E_AQ_CLUSTER_ID_HMC 3 2846 #define I40E_AQ_CLUSTER_ID_MAC0 4 2847 #define I40E_AQ_CLUSTER_ID_MAC1 5 2848 #define I40E_AQ_CLUSTER_ID_MAC2 6 2849 #define I40E_AQ_CLUSTER_ID_MAC3 7 2850 #define I40E_AQ_CLUSTER_ID_DCB 8 2851 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2852 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2853 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2854 2855 struct i40e_aqc_debug_dump_internals { 2856 u8 cluster_id; 2857 u8 table_id; 2858 __le16 data_size; 2859 __le32 idx; 2860 __le32 address_high; 2861 __le32 address_low; 2862 }; 2863 2864 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2865 2866 struct i40e_aqc_debug_modify_internals { 2867 u8 cluster_id; 2868 u8 cluster_specific_params[7]; 2869 __le32 address_high; 2870 __le32 address_low; 2871 }; 2872 2873 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2874 2875 #endif /* _I40E_ADMINQ_CMD_H_ */ 2876