1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_ADMINQ_H_ 5 #define _I40E_ADMINQ_H_ 6 7 #include "i40e_osdep.h" 8 #include "i40e_status.h" 9 #include "i40e_adminq_cmd.h" 10 11 #define I40E_ADMINQ_DESC(R, i) \ 12 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i])) 13 14 #define I40E_ADMINQ_DESC_ALIGNMENT 4096 15 16 struct i40e_adminq_ring { 17 struct i40e_virt_mem dma_head; /* space for dma structures */ 18 struct i40e_dma_mem desc_buf; /* descriptor ring memory */ 19 struct i40e_virt_mem cmd_buf; /* command buffer memory */ 20 21 union { 22 struct i40e_dma_mem *asq_bi; 23 struct i40e_dma_mem *arq_bi; 24 } r; 25 26 u16 count; /* Number of descriptors */ 27 u16 rx_buf_len; /* Admin Receive Queue buffer length */ 28 29 /* used for interrupt processing */ 30 u16 next_to_use; 31 u16 next_to_clean; 32 33 /* used for queue tracking */ 34 u32 head; 35 u32 tail; 36 u32 len; 37 u32 bah; 38 u32 bal; 39 }; 40 41 /* ASQ transaction details */ 42 struct i40e_asq_cmd_details { 43 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */ 44 u64 cookie; 45 u16 flags_ena; 46 u16 flags_dis; 47 bool async; 48 bool postpone; 49 struct i40e_aq_desc *wb_desc; 50 }; 51 52 #define I40E_ADMINQ_DETAILS(R, i) \ 53 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i])) 54 55 /* ARQ event information */ 56 struct i40e_arq_event_info { 57 struct i40e_aq_desc desc; 58 u16 msg_len; 59 u16 buf_len; 60 u8 *msg_buf; 61 }; 62 63 /* Admin Queue information */ 64 struct i40e_adminq_info { 65 struct i40e_adminq_ring arq; /* receive queue */ 66 struct i40e_adminq_ring asq; /* send queue */ 67 u32 asq_cmd_timeout; /* send queue cmd write back timeout*/ 68 u16 num_arq_entries; /* receive queue depth */ 69 u16 num_asq_entries; /* send queue depth */ 70 u16 arq_buf_size; /* receive queue buffer size */ 71 u16 asq_buf_size; /* send queue buffer size */ 72 u16 fw_maj_ver; /* firmware major version */ 73 u16 fw_min_ver; /* firmware minor version */ 74 u32 fw_build; /* firmware build number */ 75 u16 api_maj_ver; /* api major version */ 76 u16 api_min_ver; /* api minor version */ 77 78 struct mutex asq_mutex; /* Send queue lock */ 79 struct mutex arq_mutex; /* Receive queue lock */ 80 81 /* last status values on send and receive queues */ 82 enum i40e_admin_queue_err asq_last_status; 83 enum i40e_admin_queue_err arq_last_status; 84 }; 85 86 /** 87 * i40e_aq_rc_to_posix - convert errors to user-land codes 88 * aq_ret: AdminQ handler error code can override aq_rc 89 * aq_rc: AdminQ firmware error code to convert 90 **/ 91 static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc) 92 { 93 int aq_to_posix[] = { 94 0, /* I40E_AQ_RC_OK */ 95 -EPERM, /* I40E_AQ_RC_EPERM */ 96 -ENOENT, /* I40E_AQ_RC_ENOENT */ 97 -ESRCH, /* I40E_AQ_RC_ESRCH */ 98 -EINTR, /* I40E_AQ_RC_EINTR */ 99 -EIO, /* I40E_AQ_RC_EIO */ 100 -ENXIO, /* I40E_AQ_RC_ENXIO */ 101 -E2BIG, /* I40E_AQ_RC_E2BIG */ 102 -EAGAIN, /* I40E_AQ_RC_EAGAIN */ 103 -ENOMEM, /* I40E_AQ_RC_ENOMEM */ 104 -EACCES, /* I40E_AQ_RC_EACCES */ 105 -EFAULT, /* I40E_AQ_RC_EFAULT */ 106 -EBUSY, /* I40E_AQ_RC_EBUSY */ 107 -EEXIST, /* I40E_AQ_RC_EEXIST */ 108 -EINVAL, /* I40E_AQ_RC_EINVAL */ 109 -ENOTTY, /* I40E_AQ_RC_ENOTTY */ 110 -ENOSPC, /* I40E_AQ_RC_ENOSPC */ 111 -ENOSYS, /* I40E_AQ_RC_ENOSYS */ 112 -ERANGE, /* I40E_AQ_RC_ERANGE */ 113 -EPIPE, /* I40E_AQ_RC_EFLUSHED */ 114 -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */ 115 -EROFS, /* I40E_AQ_RC_EMODE */ 116 -EFBIG, /* I40E_AQ_RC_EFBIG */ 117 }; 118 119 /* aq_rc is invalid if AQ timed out */ 120 if (aq_ret == I40E_ERR_ADMIN_QUEUE_TIMEOUT) 121 return -EAGAIN; 122 123 if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0])))) 124 return -ERANGE; 125 126 return aq_to_posix[aq_rc]; 127 } 128 129 /* general information */ 130 #define I40E_AQ_LARGE_BUF 512 131 #define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */ 132 133 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 134 u16 opcode); 135 136 #endif /* _I40E_ADMINQ_H_ */ 137