1 /*******************************************************************************
2  *
3  * Intel Ethernet Controller XL710 Family Linux Driver
4  * Copyright(c) 2013 - 2014 Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  ******************************************************************************/
26 
27 #ifndef _I40E_ADMINQ_H_
28 #define _I40E_ADMINQ_H_
29 
30 #include "i40e_osdep.h"
31 #include "i40e_adminq_cmd.h"
32 
33 #define I40E_ADMINQ_DESC(R, i)   \
34 	(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
35 
36 #define I40E_ADMINQ_DESC_ALIGNMENT 4096
37 
38 struct i40e_adminq_ring {
39 	struct i40e_virt_mem dma_head;	/* space for dma structures */
40 	struct i40e_dma_mem desc_buf;	/* descriptor ring memory */
41 	struct i40e_virt_mem cmd_buf;	/* command buffer memory */
42 
43 	union {
44 		struct i40e_dma_mem *asq_bi;
45 		struct i40e_dma_mem *arq_bi;
46 	} r;
47 
48 	u16 count;		/* Number of descriptors */
49 	u16 rx_buf_len;		/* Admin Receive Queue buffer length */
50 
51 	/* used for interrupt processing */
52 	u16 next_to_use;
53 	u16 next_to_clean;
54 
55 	/* used for queue tracking */
56 	u32 head;
57 	u32 tail;
58 	u32 len;
59 	u32 bah;
60 	u32 bal;
61 };
62 
63 /* ASQ transaction details */
64 struct i40e_asq_cmd_details {
65 	void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
66 	u64 cookie;
67 	u16 flags_ena;
68 	u16 flags_dis;
69 	bool async;
70 	bool postpone;
71 };
72 
73 #define I40E_ADMINQ_DETAILS(R, i)   \
74 	(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
75 
76 /* ARQ event information */
77 struct i40e_arq_event_info {
78 	struct i40e_aq_desc desc;
79 	u16 msg_size;
80 	u8 *msg_buf;
81 };
82 
83 /* Admin Queue information */
84 struct i40e_adminq_info {
85 	struct i40e_adminq_ring arq;    /* receive queue */
86 	struct i40e_adminq_ring asq;    /* send queue */
87 	u32 asq_cmd_timeout;            /* send queue cmd write back timeout*/
88 	u16 num_arq_entries;            /* receive queue depth */
89 	u16 num_asq_entries;            /* send queue depth */
90 	u16 arq_buf_size;               /* receive queue buffer size */
91 	u16 asq_buf_size;               /* send queue buffer size */
92 	u16 fw_maj_ver;                 /* firmware major version */
93 	u16 fw_min_ver;                 /* firmware minor version */
94 	u16 api_maj_ver;                /* api major version */
95 	u16 api_min_ver;                /* api minor version */
96 	bool nvm_busy;
97 	bool nvm_release_on_done;
98 
99 	struct mutex asq_mutex; /* Send queue lock */
100 	struct mutex arq_mutex; /* Receive queue lock */
101 
102 	/* last status values on send and receive queues */
103 	enum i40e_admin_queue_err asq_last_status;
104 	enum i40e_admin_queue_err arq_last_status;
105 };
106 
107 /**
108  * i40e_aq_rc_to_posix - convert errors to user-land codes
109  * aq_rc: AdminQ error code to convert
110  **/
111 static inline int i40e_aq_rc_to_posix(u16 aq_rc)
112 {
113 	int aq_to_posix[] = {
114 		0,           /* I40E_AQ_RC_OK */
115 		-EPERM,      /* I40E_AQ_RC_EPERM */
116 		-ENOENT,     /* I40E_AQ_RC_ENOENT */
117 		-ESRCH,      /* I40E_AQ_RC_ESRCH */
118 		-EINTR,      /* I40E_AQ_RC_EINTR */
119 		-EIO,        /* I40E_AQ_RC_EIO */
120 		-ENXIO,      /* I40E_AQ_RC_ENXIO */
121 		-E2BIG,      /* I40E_AQ_RC_E2BIG */
122 		-EAGAIN,     /* I40E_AQ_RC_EAGAIN */
123 		-ENOMEM,     /* I40E_AQ_RC_ENOMEM */
124 		-EACCES,     /* I40E_AQ_RC_EACCES */
125 		-EFAULT,     /* I40E_AQ_RC_EFAULT */
126 		-EBUSY,      /* I40E_AQ_RC_EBUSY */
127 		-EEXIST,     /* I40E_AQ_RC_EEXIST */
128 		-EINVAL,     /* I40E_AQ_RC_EINVAL */
129 		-ENOTTY,     /* I40E_AQ_RC_ENOTTY */
130 		-ENOSPC,     /* I40E_AQ_RC_ENOSPC */
131 		-ENOSYS,     /* I40E_AQ_RC_ENOSYS */
132 		-ERANGE,     /* I40E_AQ_RC_ERANGE */
133 		-EPIPE,      /* I40E_AQ_RC_EFLUSHED */
134 		-ESPIPE,     /* I40E_AQ_RC_BAD_ADDR */
135 		-EROFS,      /* I40E_AQ_RC_EMODE */
136 		-EFBIG,      /* I40E_AQ_RC_EFBIG */
137 	};
138 
139 	return aq_to_posix[aq_rc];
140 }
141 
142 /* general information */
143 #define I40E_AQ_LARGE_BUF	512
144 #define I40E_ASQ_CMD_TIMEOUT	100000  /* usecs */
145 
146 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
147 				       u16 opcode);
148 
149 #endif /* _I40E_ADMINQ_H_ */
150