1 // SPDX-License-Identifier: GPL-2.0 2 /******************************************************************************* 3 * 4 * Intel Ethernet Controller XL710 Family Linux Driver 5 * Copyright(c) 2013 - 2016 Intel Corporation. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program. If not, see <http://www.gnu.org/licenses/>. 18 * 19 * The full GNU General Public License is included in this distribution in 20 * the file called "COPYING". 21 * 22 * Contact Information: 23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * 26 ******************************************************************************/ 27 28 #include "i40e_status.h" 29 #include "i40e_type.h" 30 #include "i40e_register.h" 31 #include "i40e_adminq.h" 32 #include "i40e_prototype.h" 33 34 static void i40e_resume_aq(struct i40e_hw *hw); 35 36 /** 37 * i40e_adminq_init_regs - Initialize AdminQ registers 38 * @hw: pointer to the hardware structure 39 * 40 * This assumes the alloc_asq and alloc_arq functions have already been called 41 **/ 42 static void i40e_adminq_init_regs(struct i40e_hw *hw) 43 { 44 /* set head and tail registers in our local struct */ 45 if (i40e_is_vf(hw)) { 46 hw->aq.asq.tail = I40E_VF_ATQT1; 47 hw->aq.asq.head = I40E_VF_ATQH1; 48 hw->aq.asq.len = I40E_VF_ATQLEN1; 49 hw->aq.asq.bal = I40E_VF_ATQBAL1; 50 hw->aq.asq.bah = I40E_VF_ATQBAH1; 51 hw->aq.arq.tail = I40E_VF_ARQT1; 52 hw->aq.arq.head = I40E_VF_ARQH1; 53 hw->aq.arq.len = I40E_VF_ARQLEN1; 54 hw->aq.arq.bal = I40E_VF_ARQBAL1; 55 hw->aq.arq.bah = I40E_VF_ARQBAH1; 56 } else { 57 hw->aq.asq.tail = I40E_PF_ATQT; 58 hw->aq.asq.head = I40E_PF_ATQH; 59 hw->aq.asq.len = I40E_PF_ATQLEN; 60 hw->aq.asq.bal = I40E_PF_ATQBAL; 61 hw->aq.asq.bah = I40E_PF_ATQBAH; 62 hw->aq.arq.tail = I40E_PF_ARQT; 63 hw->aq.arq.head = I40E_PF_ARQH; 64 hw->aq.arq.len = I40E_PF_ARQLEN; 65 hw->aq.arq.bal = I40E_PF_ARQBAL; 66 hw->aq.arq.bah = I40E_PF_ARQBAH; 67 } 68 } 69 70 /** 71 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings 72 * @hw: pointer to the hardware structure 73 **/ 74 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 75 { 76 i40e_status ret_code; 77 78 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 79 i40e_mem_atq_ring, 80 (hw->aq.num_asq_entries * 81 sizeof(struct i40e_aq_desc)), 82 I40E_ADMINQ_DESC_ALIGNMENT); 83 if (ret_code) 84 return ret_code; 85 86 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, 87 (hw->aq.num_asq_entries * 88 sizeof(struct i40e_asq_cmd_details))); 89 if (ret_code) { 90 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 91 return ret_code; 92 } 93 94 return ret_code; 95 } 96 97 /** 98 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings 99 * @hw: pointer to the hardware structure 100 **/ 101 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 102 { 103 i40e_status ret_code; 104 105 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 106 i40e_mem_arq_ring, 107 (hw->aq.num_arq_entries * 108 sizeof(struct i40e_aq_desc)), 109 I40E_ADMINQ_DESC_ALIGNMENT); 110 111 return ret_code; 112 } 113 114 /** 115 * i40e_free_adminq_asq - Free Admin Queue send rings 116 * @hw: pointer to the hardware structure 117 * 118 * This assumes the posted send buffers have already been cleaned 119 * and de-allocated 120 **/ 121 static void i40e_free_adminq_asq(struct i40e_hw *hw) 122 { 123 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 124 } 125 126 /** 127 * i40e_free_adminq_arq - Free Admin Queue receive rings 128 * @hw: pointer to the hardware structure 129 * 130 * This assumes the posted receive buffers have already been cleaned 131 * and de-allocated 132 **/ 133 static void i40e_free_adminq_arq(struct i40e_hw *hw) 134 { 135 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 136 } 137 138 /** 139 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue 140 * @hw: pointer to the hardware structure 141 **/ 142 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) 143 { 144 i40e_status ret_code; 145 struct i40e_aq_desc *desc; 146 struct i40e_dma_mem *bi; 147 int i; 148 149 /* We'll be allocating the buffer info memory first, then we can 150 * allocate the mapped buffers for the event processing 151 */ 152 153 /* buffer_info structures do not need alignment */ 154 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, 155 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); 156 if (ret_code) 157 goto alloc_arq_bufs; 158 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; 159 160 /* allocate the mapped buffers */ 161 for (i = 0; i < hw->aq.num_arq_entries; i++) { 162 bi = &hw->aq.arq.r.arq_bi[i]; 163 ret_code = i40e_allocate_dma_mem(hw, bi, 164 i40e_mem_arq_buf, 165 hw->aq.arq_buf_size, 166 I40E_ADMINQ_DESC_ALIGNMENT); 167 if (ret_code) 168 goto unwind_alloc_arq_bufs; 169 170 /* now configure the descriptors for use */ 171 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 172 173 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 174 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 175 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 176 desc->opcode = 0; 177 /* This is in accordance with Admin queue design, there is no 178 * register for buffer size configuration 179 */ 180 desc->datalen = cpu_to_le16((u16)bi->size); 181 desc->retval = 0; 182 desc->cookie_high = 0; 183 desc->cookie_low = 0; 184 desc->params.external.addr_high = 185 cpu_to_le32(upper_32_bits(bi->pa)); 186 desc->params.external.addr_low = 187 cpu_to_le32(lower_32_bits(bi->pa)); 188 desc->params.external.param0 = 0; 189 desc->params.external.param1 = 0; 190 } 191 192 alloc_arq_bufs: 193 return ret_code; 194 195 unwind_alloc_arq_bufs: 196 /* don't try to free the one that failed... */ 197 i--; 198 for (; i >= 0; i--) 199 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 200 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 201 202 return ret_code; 203 } 204 205 /** 206 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue 207 * @hw: pointer to the hardware structure 208 **/ 209 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) 210 { 211 i40e_status ret_code; 212 struct i40e_dma_mem *bi; 213 int i; 214 215 /* No mapped memory needed yet, just the buffer info structures */ 216 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, 217 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); 218 if (ret_code) 219 goto alloc_asq_bufs; 220 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; 221 222 /* allocate the mapped buffers */ 223 for (i = 0; i < hw->aq.num_asq_entries; i++) { 224 bi = &hw->aq.asq.r.asq_bi[i]; 225 ret_code = i40e_allocate_dma_mem(hw, bi, 226 i40e_mem_asq_buf, 227 hw->aq.asq_buf_size, 228 I40E_ADMINQ_DESC_ALIGNMENT); 229 if (ret_code) 230 goto unwind_alloc_asq_bufs; 231 } 232 alloc_asq_bufs: 233 return ret_code; 234 235 unwind_alloc_asq_bufs: 236 /* don't try to free the one that failed... */ 237 i--; 238 for (; i >= 0; i--) 239 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 240 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 241 242 return ret_code; 243 } 244 245 /** 246 * i40e_free_arq_bufs - Free receive queue buffer info elements 247 * @hw: pointer to the hardware structure 248 **/ 249 static void i40e_free_arq_bufs(struct i40e_hw *hw) 250 { 251 int i; 252 253 /* free descriptors */ 254 for (i = 0; i < hw->aq.num_arq_entries; i++) 255 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 256 257 /* free the descriptor memory */ 258 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 259 260 /* free the dma header */ 261 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 262 } 263 264 /** 265 * i40e_free_asq_bufs - Free send queue buffer info elements 266 * @hw: pointer to the hardware structure 267 **/ 268 static void i40e_free_asq_bufs(struct i40e_hw *hw) 269 { 270 int i; 271 272 /* only unmap if the address is non-NULL */ 273 for (i = 0; i < hw->aq.num_asq_entries; i++) 274 if (hw->aq.asq.r.asq_bi[i].pa) 275 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 276 277 /* free the buffer info list */ 278 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); 279 280 /* free the descriptor memory */ 281 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 282 283 /* free the dma header */ 284 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 285 } 286 287 /** 288 * i40e_config_asq_regs - configure ASQ registers 289 * @hw: pointer to the hardware structure 290 * 291 * Configure base address and length registers for the transmit queue 292 **/ 293 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) 294 { 295 i40e_status ret_code = 0; 296 u32 reg = 0; 297 298 /* Clear Head and Tail */ 299 wr32(hw, hw->aq.asq.head, 0); 300 wr32(hw, hw->aq.asq.tail, 0); 301 302 /* set starting point */ 303 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 304 I40E_PF_ATQLEN_ATQENABLE_MASK)); 305 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); 306 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); 307 308 /* Check one register to verify that config was applied */ 309 reg = rd32(hw, hw->aq.asq.bal); 310 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 311 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 312 313 return ret_code; 314 } 315 316 /** 317 * i40e_config_arq_regs - ARQ register configuration 318 * @hw: pointer to the hardware structure 319 * 320 * Configure base address and length registers for the receive (event queue) 321 **/ 322 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) 323 { 324 i40e_status ret_code = 0; 325 u32 reg = 0; 326 327 /* Clear Head and Tail */ 328 wr32(hw, hw->aq.arq.head, 0); 329 wr32(hw, hw->aq.arq.tail, 0); 330 331 /* set starting point */ 332 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | 333 I40E_PF_ARQLEN_ARQENABLE_MASK)); 334 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); 335 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); 336 337 /* Update tail in the HW to post pre-allocated buffers */ 338 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 339 340 /* Check one register to verify that config was applied */ 341 reg = rd32(hw, hw->aq.arq.bal); 342 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 343 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 344 345 return ret_code; 346 } 347 348 /** 349 * i40e_init_asq - main initialization routine for ASQ 350 * @hw: pointer to the hardware structure 351 * 352 * This is the main initialization routine for the Admin Send Queue 353 * Prior to calling this function, drivers *MUST* set the following fields 354 * in the hw->aq structure: 355 * - hw->aq.num_asq_entries 356 * - hw->aq.arq_buf_size 357 * 358 * Do *NOT* hold the lock when calling this as the memory allocation routines 359 * called are not going to be atomic context safe 360 **/ 361 static i40e_status i40e_init_asq(struct i40e_hw *hw) 362 { 363 i40e_status ret_code = 0; 364 365 if (hw->aq.asq.count > 0) { 366 /* queue already initialized */ 367 ret_code = I40E_ERR_NOT_READY; 368 goto init_adminq_exit; 369 } 370 371 /* verify input for valid configuration */ 372 if ((hw->aq.num_asq_entries == 0) || 373 (hw->aq.asq_buf_size == 0)) { 374 ret_code = I40E_ERR_CONFIG; 375 goto init_adminq_exit; 376 } 377 378 hw->aq.asq.next_to_use = 0; 379 hw->aq.asq.next_to_clean = 0; 380 381 /* allocate the ring memory */ 382 ret_code = i40e_alloc_adminq_asq_ring(hw); 383 if (ret_code) 384 goto init_adminq_exit; 385 386 /* allocate buffers in the rings */ 387 ret_code = i40e_alloc_asq_bufs(hw); 388 if (ret_code) 389 goto init_adminq_free_rings; 390 391 /* initialize base registers */ 392 ret_code = i40e_config_asq_regs(hw); 393 if (ret_code) 394 goto init_adminq_free_rings; 395 396 /* success! */ 397 hw->aq.asq.count = hw->aq.num_asq_entries; 398 goto init_adminq_exit; 399 400 init_adminq_free_rings: 401 i40e_free_adminq_asq(hw); 402 403 init_adminq_exit: 404 return ret_code; 405 } 406 407 /** 408 * i40e_init_arq - initialize ARQ 409 * @hw: pointer to the hardware structure 410 * 411 * The main initialization routine for the Admin Receive (Event) Queue. 412 * Prior to calling this function, drivers *MUST* set the following fields 413 * in the hw->aq structure: 414 * - hw->aq.num_asq_entries 415 * - hw->aq.arq_buf_size 416 * 417 * Do *NOT* hold the lock when calling this as the memory allocation routines 418 * called are not going to be atomic context safe 419 **/ 420 static i40e_status i40e_init_arq(struct i40e_hw *hw) 421 { 422 i40e_status ret_code = 0; 423 424 if (hw->aq.arq.count > 0) { 425 /* queue already initialized */ 426 ret_code = I40E_ERR_NOT_READY; 427 goto init_adminq_exit; 428 } 429 430 /* verify input for valid configuration */ 431 if ((hw->aq.num_arq_entries == 0) || 432 (hw->aq.arq_buf_size == 0)) { 433 ret_code = I40E_ERR_CONFIG; 434 goto init_adminq_exit; 435 } 436 437 hw->aq.arq.next_to_use = 0; 438 hw->aq.arq.next_to_clean = 0; 439 440 /* allocate the ring memory */ 441 ret_code = i40e_alloc_adminq_arq_ring(hw); 442 if (ret_code) 443 goto init_adminq_exit; 444 445 /* allocate buffers in the rings */ 446 ret_code = i40e_alloc_arq_bufs(hw); 447 if (ret_code) 448 goto init_adminq_free_rings; 449 450 /* initialize base registers */ 451 ret_code = i40e_config_arq_regs(hw); 452 if (ret_code) 453 goto init_adminq_free_rings; 454 455 /* success! */ 456 hw->aq.arq.count = hw->aq.num_arq_entries; 457 goto init_adminq_exit; 458 459 init_adminq_free_rings: 460 i40e_free_adminq_arq(hw); 461 462 init_adminq_exit: 463 return ret_code; 464 } 465 466 /** 467 * i40e_shutdown_asq - shutdown the ASQ 468 * @hw: pointer to the hardware structure 469 * 470 * The main shutdown routine for the Admin Send Queue 471 **/ 472 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) 473 { 474 i40e_status ret_code = 0; 475 476 mutex_lock(&hw->aq.asq_mutex); 477 478 if (hw->aq.asq.count == 0) { 479 ret_code = I40E_ERR_NOT_READY; 480 goto shutdown_asq_out; 481 } 482 483 /* Stop firmware AdminQ processing */ 484 wr32(hw, hw->aq.asq.head, 0); 485 wr32(hw, hw->aq.asq.tail, 0); 486 wr32(hw, hw->aq.asq.len, 0); 487 wr32(hw, hw->aq.asq.bal, 0); 488 wr32(hw, hw->aq.asq.bah, 0); 489 490 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ 491 492 /* free ring buffers */ 493 i40e_free_asq_bufs(hw); 494 495 shutdown_asq_out: 496 mutex_unlock(&hw->aq.asq_mutex); 497 return ret_code; 498 } 499 500 /** 501 * i40e_shutdown_arq - shutdown ARQ 502 * @hw: pointer to the hardware structure 503 * 504 * The main shutdown routine for the Admin Receive Queue 505 **/ 506 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) 507 { 508 i40e_status ret_code = 0; 509 510 mutex_lock(&hw->aq.arq_mutex); 511 512 if (hw->aq.arq.count == 0) { 513 ret_code = I40E_ERR_NOT_READY; 514 goto shutdown_arq_out; 515 } 516 517 /* Stop firmware AdminQ processing */ 518 wr32(hw, hw->aq.arq.head, 0); 519 wr32(hw, hw->aq.arq.tail, 0); 520 wr32(hw, hw->aq.arq.len, 0); 521 wr32(hw, hw->aq.arq.bal, 0); 522 wr32(hw, hw->aq.arq.bah, 0); 523 524 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ 525 526 /* free ring buffers */ 527 i40e_free_arq_bufs(hw); 528 529 shutdown_arq_out: 530 mutex_unlock(&hw->aq.arq_mutex); 531 return ret_code; 532 } 533 534 /** 535 * i40e_init_adminq - main initialization routine for Admin Queue 536 * @hw: pointer to the hardware structure 537 * 538 * Prior to calling this function, drivers *MUST* set the following fields 539 * in the hw->aq structure: 540 * - hw->aq.num_asq_entries 541 * - hw->aq.num_arq_entries 542 * - hw->aq.arq_buf_size 543 * - hw->aq.asq_buf_size 544 **/ 545 i40e_status i40e_init_adminq(struct i40e_hw *hw) 546 { 547 u16 cfg_ptr, oem_hi, oem_lo; 548 u16 eetrack_lo, eetrack_hi; 549 i40e_status ret_code; 550 int retry = 0; 551 552 /* verify input for valid configuration */ 553 if ((hw->aq.num_arq_entries == 0) || 554 (hw->aq.num_asq_entries == 0) || 555 (hw->aq.arq_buf_size == 0) || 556 (hw->aq.asq_buf_size == 0)) { 557 ret_code = I40E_ERR_CONFIG; 558 goto init_adminq_exit; 559 } 560 561 /* Set up register offsets */ 562 i40e_adminq_init_regs(hw); 563 564 /* setup ASQ command write back timeout */ 565 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; 566 567 /* allocate the ASQ */ 568 ret_code = i40e_init_asq(hw); 569 if (ret_code) 570 goto init_adminq_destroy_locks; 571 572 /* allocate the ARQ */ 573 ret_code = i40e_init_arq(hw); 574 if (ret_code) 575 goto init_adminq_free_asq; 576 577 /* There are some cases where the firmware may not be quite ready 578 * for AdminQ operations, so we retry the AdminQ setup a few times 579 * if we see timeouts in this first AQ call. 580 */ 581 do { 582 ret_code = i40e_aq_get_firmware_version(hw, 583 &hw->aq.fw_maj_ver, 584 &hw->aq.fw_min_ver, 585 &hw->aq.fw_build, 586 &hw->aq.api_maj_ver, 587 &hw->aq.api_min_ver, 588 NULL); 589 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) 590 break; 591 retry++; 592 msleep(100); 593 i40e_resume_aq(hw); 594 } while (retry < 10); 595 if (ret_code != I40E_SUCCESS) 596 goto init_adminq_free_arq; 597 598 /* get the NVM version info */ 599 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, 600 &hw->nvm.version); 601 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 602 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 603 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 604 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); 605 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), 606 &oem_hi); 607 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), 608 &oem_lo); 609 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; 610 611 if (hw->mac.type == I40E_MAC_XL710 && 612 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 613 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 614 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; 615 } 616 617 /* Newer versions of firmware require lock when reading the NVM */ 618 if (hw->aq.api_maj_ver > 1 || 619 (hw->aq.api_maj_ver == 1 && 620 hw->aq.api_min_ver >= 5)) 621 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 622 623 /* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */ 624 if (hw->aq.api_maj_ver > 1 || 625 (hw->aq.api_maj_ver == 1 && 626 hw->aq.api_min_ver >= 7)) 627 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; 628 629 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { 630 ret_code = I40E_ERR_FIRMWARE_API_VERSION; 631 goto init_adminq_free_arq; 632 } 633 634 /* pre-emptive resource lock release */ 635 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 636 hw->nvm_release_on_done = false; 637 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; 638 639 ret_code = 0; 640 641 /* success! */ 642 goto init_adminq_exit; 643 644 init_adminq_free_arq: 645 i40e_shutdown_arq(hw); 646 init_adminq_free_asq: 647 i40e_shutdown_asq(hw); 648 init_adminq_destroy_locks: 649 650 init_adminq_exit: 651 return ret_code; 652 } 653 654 /** 655 * i40e_shutdown_adminq - shutdown routine for the Admin Queue 656 * @hw: pointer to the hardware structure 657 **/ 658 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) 659 { 660 i40e_status ret_code = 0; 661 662 if (i40e_check_asq_alive(hw)) 663 i40e_aq_queue_shutdown(hw, true); 664 665 i40e_shutdown_asq(hw); 666 i40e_shutdown_arq(hw); 667 668 if (hw->nvm_buff.va) 669 i40e_free_virt_mem(hw, &hw->nvm_buff); 670 671 return ret_code; 672 } 673 674 /** 675 * i40e_clean_asq - cleans Admin send queue 676 * @hw: pointer to the hardware structure 677 * 678 * returns the number of free desc 679 **/ 680 static u16 i40e_clean_asq(struct i40e_hw *hw) 681 { 682 struct i40e_adminq_ring *asq = &(hw->aq.asq); 683 struct i40e_asq_cmd_details *details; 684 u16 ntc = asq->next_to_clean; 685 struct i40e_aq_desc desc_cb; 686 struct i40e_aq_desc *desc; 687 688 desc = I40E_ADMINQ_DESC(*asq, ntc); 689 details = I40E_ADMINQ_DETAILS(*asq, ntc); 690 while (rd32(hw, hw->aq.asq.head) != ntc) { 691 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 692 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); 693 694 if (details->callback) { 695 I40E_ADMINQ_CALLBACK cb_func = 696 (I40E_ADMINQ_CALLBACK)details->callback; 697 desc_cb = *desc; 698 cb_func(hw, &desc_cb); 699 } 700 memset(desc, 0, sizeof(*desc)); 701 memset(details, 0, sizeof(*details)); 702 ntc++; 703 if (ntc == asq->count) 704 ntc = 0; 705 desc = I40E_ADMINQ_DESC(*asq, ntc); 706 details = I40E_ADMINQ_DETAILS(*asq, ntc); 707 } 708 709 asq->next_to_clean = ntc; 710 711 return I40E_DESC_UNUSED(asq); 712 } 713 714 /** 715 * i40e_asq_done - check if FW has processed the Admin Send Queue 716 * @hw: pointer to the hw struct 717 * 718 * Returns true if the firmware has processed all descriptors on the 719 * admin send queue. Returns false if there are still requests pending. 720 **/ 721 static bool i40e_asq_done(struct i40e_hw *hw) 722 { 723 /* AQ designers suggest use of head for better 724 * timing reliability than DD bit 725 */ 726 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; 727 728 } 729 730 /** 731 * i40e_asq_send_command - send command to Admin Queue 732 * @hw: pointer to the hw struct 733 * @desc: prefilled descriptor describing the command (non DMA mem) 734 * @buff: buffer to use for indirect commands 735 * @buff_size: size of buffer for indirect commands 736 * @cmd_details: pointer to command details structure 737 * 738 * This is the main send command driver routine for the Admin Queue send 739 * queue. It runs the queue, cleans the queue, etc 740 **/ 741 i40e_status i40e_asq_send_command(struct i40e_hw *hw, 742 struct i40e_aq_desc *desc, 743 void *buff, /* can be NULL */ 744 u16 buff_size, 745 struct i40e_asq_cmd_details *cmd_details) 746 { 747 i40e_status status = 0; 748 struct i40e_dma_mem *dma_buff = NULL; 749 struct i40e_asq_cmd_details *details; 750 struct i40e_aq_desc *desc_on_ring; 751 bool cmd_completed = false; 752 u16 retval = 0; 753 u32 val = 0; 754 755 mutex_lock(&hw->aq.asq_mutex); 756 757 if (hw->aq.asq.count == 0) { 758 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 759 "AQTX: Admin queue not initialized.\n"); 760 status = I40E_ERR_QUEUE_EMPTY; 761 goto asq_send_command_error; 762 } 763 764 hw->aq.asq_last_status = I40E_AQ_RC_OK; 765 766 val = rd32(hw, hw->aq.asq.head); 767 if (val >= hw->aq.num_asq_entries) { 768 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 769 "AQTX: head overrun at %d\n", val); 770 status = I40E_ERR_QUEUE_EMPTY; 771 goto asq_send_command_error; 772 } 773 774 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); 775 if (cmd_details) { 776 *details = *cmd_details; 777 778 /* If the cmd_details are defined copy the cookie. The 779 * cpu_to_le32 is not needed here because the data is ignored 780 * by the FW, only used by the driver 781 */ 782 if (details->cookie) { 783 desc->cookie_high = 784 cpu_to_le32(upper_32_bits(details->cookie)); 785 desc->cookie_low = 786 cpu_to_le32(lower_32_bits(details->cookie)); 787 } 788 } else { 789 memset(details, 0, sizeof(struct i40e_asq_cmd_details)); 790 } 791 792 /* clear requested flags and then set additional flags if defined */ 793 desc->flags &= ~cpu_to_le16(details->flags_dis); 794 desc->flags |= cpu_to_le16(details->flags_ena); 795 796 if (buff_size > hw->aq.asq_buf_size) { 797 i40e_debug(hw, 798 I40E_DEBUG_AQ_MESSAGE, 799 "AQTX: Invalid buffer size: %d.\n", 800 buff_size); 801 status = I40E_ERR_INVALID_SIZE; 802 goto asq_send_command_error; 803 } 804 805 if (details->postpone && !details->async) { 806 i40e_debug(hw, 807 I40E_DEBUG_AQ_MESSAGE, 808 "AQTX: Async flag not set along with postpone flag"); 809 status = I40E_ERR_PARAM; 810 goto asq_send_command_error; 811 } 812 813 /* call clean and check queue available function to reclaim the 814 * descriptors that were processed by FW, the function returns the 815 * number of desc available 816 */ 817 /* the clean function called here could be called in a separate thread 818 * in case of asynchronous completions 819 */ 820 if (i40e_clean_asq(hw) == 0) { 821 i40e_debug(hw, 822 I40E_DEBUG_AQ_MESSAGE, 823 "AQTX: Error queue is full.\n"); 824 status = I40E_ERR_ADMIN_QUEUE_FULL; 825 goto asq_send_command_error; 826 } 827 828 /* initialize the temp desc pointer with the right desc */ 829 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); 830 831 /* if the desc is available copy the temp desc to the right place */ 832 *desc_on_ring = *desc; 833 834 /* if buff is not NULL assume indirect command */ 835 if (buff != NULL) { 836 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); 837 /* copy the user buff into the respective DMA buff */ 838 memcpy(dma_buff->va, buff, buff_size); 839 desc_on_ring->datalen = cpu_to_le16(buff_size); 840 841 /* Update the address values in the desc with the pa value 842 * for respective buffer 843 */ 844 desc_on_ring->params.external.addr_high = 845 cpu_to_le32(upper_32_bits(dma_buff->pa)); 846 desc_on_ring->params.external.addr_low = 847 cpu_to_le32(lower_32_bits(dma_buff->pa)); 848 } 849 850 /* bump the tail */ 851 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); 852 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, 853 buff, buff_size); 854 (hw->aq.asq.next_to_use)++; 855 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 856 hw->aq.asq.next_to_use = 0; 857 if (!details->postpone) 858 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); 859 860 /* if cmd_details are not defined or async flag is not set, 861 * we need to wait for desc write back 862 */ 863 if (!details->async && !details->postpone) { 864 u32 total_delay = 0; 865 866 do { 867 /* AQ designers suggest use of head for better 868 * timing reliability than DD bit 869 */ 870 if (i40e_asq_done(hw)) 871 break; 872 udelay(50); 873 total_delay += 50; 874 } while (total_delay < hw->aq.asq_cmd_timeout); 875 } 876 877 /* if ready, copy the desc back to temp */ 878 if (i40e_asq_done(hw)) { 879 *desc = *desc_on_ring; 880 if (buff != NULL) 881 memcpy(buff, dma_buff->va, buff_size); 882 retval = le16_to_cpu(desc->retval); 883 if (retval != 0) { 884 i40e_debug(hw, 885 I40E_DEBUG_AQ_MESSAGE, 886 "AQTX: Command completed with error 0x%X.\n", 887 retval); 888 889 /* strip off FW internal code */ 890 retval &= 0xff; 891 } 892 cmd_completed = true; 893 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 894 status = 0; 895 else 896 status = I40E_ERR_ADMIN_QUEUE_ERROR; 897 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 898 } 899 900 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 901 "AQTX: desc and buffer writeback:\n"); 902 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); 903 904 /* save writeback aq if requested */ 905 if (details->wb_desc) 906 *details->wb_desc = *desc_on_ring; 907 908 /* update the error if time out occurred */ 909 if ((!cmd_completed) && 910 (!details->async && !details->postpone)) { 911 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { 912 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 913 "AQTX: AQ Critical error.\n"); 914 status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR; 915 } else { 916 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 917 "AQTX: Writeback timeout.\n"); 918 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; 919 } 920 } 921 922 asq_send_command_error: 923 mutex_unlock(&hw->aq.asq_mutex); 924 return status; 925 } 926 927 /** 928 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function 929 * @desc: pointer to the temp descriptor (non DMA mem) 930 * @opcode: the opcode can be used to decide which flags to turn off or on 931 * 932 * Fill the desc with default values 933 **/ 934 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 935 u16 opcode) 936 { 937 /* zero out the desc */ 938 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 939 desc->opcode = cpu_to_le16(opcode); 940 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); 941 } 942 943 /** 944 * i40e_clean_arq_element 945 * @hw: pointer to the hw struct 946 * @e: event info from the receive descriptor, includes any buffers 947 * @pending: number of events that could be left to process 948 * 949 * This function cleans one Admin Receive Queue element and returns 950 * the contents through e. It can also return how many events are 951 * left to process through 'pending' 952 **/ 953 i40e_status i40e_clean_arq_element(struct i40e_hw *hw, 954 struct i40e_arq_event_info *e, 955 u16 *pending) 956 { 957 i40e_status ret_code = 0; 958 u16 ntc = hw->aq.arq.next_to_clean; 959 struct i40e_aq_desc *desc; 960 struct i40e_dma_mem *bi; 961 u16 desc_idx; 962 u16 datalen; 963 u16 flags; 964 u16 ntu; 965 966 /* pre-clean the event info */ 967 memset(&e->desc, 0, sizeof(e->desc)); 968 969 /* take the lock before we start messing with the ring */ 970 mutex_lock(&hw->aq.arq_mutex); 971 972 if (hw->aq.arq.count == 0) { 973 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 974 "AQRX: Admin queue not initialized.\n"); 975 ret_code = I40E_ERR_QUEUE_EMPTY; 976 goto clean_arq_element_err; 977 } 978 979 /* set next_to_use to head */ 980 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; 981 if (ntu == ntc) { 982 /* nothing to do - shouldn't need to update ring's values */ 983 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; 984 goto clean_arq_element_out; 985 } 986 987 /* now clean the next descriptor */ 988 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 989 desc_idx = ntc; 990 991 hw->aq.arq_last_status = 992 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 993 flags = le16_to_cpu(desc->flags); 994 if (flags & I40E_AQ_FLAG_ERR) { 995 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 996 i40e_debug(hw, 997 I40E_DEBUG_AQ_MESSAGE, 998 "AQRX: Event received with error 0x%X.\n", 999 hw->aq.arq_last_status); 1000 } 1001 1002 e->desc = *desc; 1003 datalen = le16_to_cpu(desc->datalen); 1004 e->msg_len = min(datalen, e->buf_len); 1005 if (e->msg_buf != NULL && (e->msg_len != 0)) 1006 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, 1007 e->msg_len); 1008 1009 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); 1010 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, 1011 hw->aq.arq_buf_size); 1012 1013 /* Restore the original datalen and buffer address in the desc, 1014 * FW updates datalen to indicate the event message 1015 * size 1016 */ 1017 bi = &hw->aq.arq.r.arq_bi[ntc]; 1018 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 1019 1020 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 1021 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 1022 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 1023 desc->datalen = cpu_to_le16((u16)bi->size); 1024 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1025 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1026 1027 /* set tail = the last cleaned desc index. */ 1028 wr32(hw, hw->aq.arq.tail, ntc); 1029 /* ntc is updated to tail + 1 */ 1030 ntc++; 1031 if (ntc == hw->aq.num_arq_entries) 1032 ntc = 0; 1033 hw->aq.arq.next_to_clean = ntc; 1034 hw->aq.arq.next_to_use = ntu; 1035 1036 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc); 1037 clean_arq_element_out: 1038 /* Set pending if needed, unlock and return */ 1039 if (pending) 1040 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); 1041 clean_arq_element_err: 1042 mutex_unlock(&hw->aq.arq_mutex); 1043 1044 return ret_code; 1045 } 1046 1047 static void i40e_resume_aq(struct i40e_hw *hw) 1048 { 1049 /* Registers are reset after PF reset */ 1050 hw->aq.asq.next_to_use = 0; 1051 hw->aq.asq.next_to_clean = 0; 1052 1053 i40e_config_asq_regs(hw); 1054 1055 hw->aq.arq.next_to_use = 0; 1056 hw->aq.arq.next_to_clean = 0; 1057 1058 i40e_config_arq_regs(hw); 1059 } 1060