1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include "i40e_status.h" 28 #include "i40e_type.h" 29 #include "i40e_register.h" 30 #include "i40e_adminq.h" 31 #include "i40e_prototype.h" 32 33 static void i40e_resume_aq(struct i40e_hw *hw); 34 35 /** 36 * i40e_is_nvm_update_op - return true if this is an NVM update operation 37 * @desc: API request descriptor 38 **/ 39 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) 40 { 41 return (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_erase)) || 42 (desc->opcode == cpu_to_le16(i40e_aqc_opc_nvm_update)); 43 } 44 45 /** 46 * i40e_adminq_init_regs - Initialize AdminQ registers 47 * @hw: pointer to the hardware structure 48 * 49 * This assumes the alloc_asq and alloc_arq functions have already been called 50 **/ 51 static void i40e_adminq_init_regs(struct i40e_hw *hw) 52 { 53 /* set head and tail registers in our local struct */ 54 if (hw->mac.type == I40E_MAC_VF) { 55 hw->aq.asq.tail = I40E_VF_ATQT1; 56 hw->aq.asq.head = I40E_VF_ATQH1; 57 hw->aq.asq.len = I40E_VF_ATQLEN1; 58 hw->aq.asq.bal = I40E_VF_ATQBAL1; 59 hw->aq.asq.bah = I40E_VF_ATQBAH1; 60 hw->aq.arq.tail = I40E_VF_ARQT1; 61 hw->aq.arq.head = I40E_VF_ARQH1; 62 hw->aq.arq.len = I40E_VF_ARQLEN1; 63 hw->aq.arq.bal = I40E_VF_ARQBAL1; 64 hw->aq.arq.bah = I40E_VF_ARQBAH1; 65 } else { 66 hw->aq.asq.tail = I40E_PF_ATQT; 67 hw->aq.asq.head = I40E_PF_ATQH; 68 hw->aq.asq.len = I40E_PF_ATQLEN; 69 hw->aq.asq.bal = I40E_PF_ATQBAL; 70 hw->aq.asq.bah = I40E_PF_ATQBAH; 71 hw->aq.arq.tail = I40E_PF_ARQT; 72 hw->aq.arq.head = I40E_PF_ARQH; 73 hw->aq.arq.len = I40E_PF_ARQLEN; 74 hw->aq.arq.bal = I40E_PF_ARQBAL; 75 hw->aq.arq.bah = I40E_PF_ARQBAH; 76 } 77 } 78 79 /** 80 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings 81 * @hw: pointer to the hardware structure 82 **/ 83 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 84 { 85 i40e_status ret_code; 86 87 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 88 i40e_mem_atq_ring, 89 (hw->aq.num_asq_entries * 90 sizeof(struct i40e_aq_desc)), 91 I40E_ADMINQ_DESC_ALIGNMENT); 92 if (ret_code) 93 return ret_code; 94 95 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, 96 (hw->aq.num_asq_entries * 97 sizeof(struct i40e_asq_cmd_details))); 98 if (ret_code) { 99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 100 return ret_code; 101 } 102 103 return ret_code; 104 } 105 106 /** 107 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings 108 * @hw: pointer to the hardware structure 109 **/ 110 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 111 { 112 i40e_status ret_code; 113 114 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 115 i40e_mem_arq_ring, 116 (hw->aq.num_arq_entries * 117 sizeof(struct i40e_aq_desc)), 118 I40E_ADMINQ_DESC_ALIGNMENT); 119 120 return ret_code; 121 } 122 123 /** 124 * i40e_free_adminq_asq - Free Admin Queue send rings 125 * @hw: pointer to the hardware structure 126 * 127 * This assumes the posted send buffers have already been cleaned 128 * and de-allocated 129 **/ 130 static void i40e_free_adminq_asq(struct i40e_hw *hw) 131 { 132 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 133 } 134 135 /** 136 * i40e_free_adminq_arq - Free Admin Queue receive rings 137 * @hw: pointer to the hardware structure 138 * 139 * This assumes the posted receive buffers have already been cleaned 140 * and de-allocated 141 **/ 142 static void i40e_free_adminq_arq(struct i40e_hw *hw) 143 { 144 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 145 } 146 147 /** 148 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue 149 * @hw: pointer to the hardware structure 150 **/ 151 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) 152 { 153 i40e_status ret_code; 154 struct i40e_aq_desc *desc; 155 struct i40e_dma_mem *bi; 156 int i; 157 158 /* We'll be allocating the buffer info memory first, then we can 159 * allocate the mapped buffers for the event processing 160 */ 161 162 /* buffer_info structures do not need alignment */ 163 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, 164 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); 165 if (ret_code) 166 goto alloc_arq_bufs; 167 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; 168 169 /* allocate the mapped buffers */ 170 for (i = 0; i < hw->aq.num_arq_entries; i++) { 171 bi = &hw->aq.arq.r.arq_bi[i]; 172 ret_code = i40e_allocate_dma_mem(hw, bi, 173 i40e_mem_arq_buf, 174 hw->aq.arq_buf_size, 175 I40E_ADMINQ_DESC_ALIGNMENT); 176 if (ret_code) 177 goto unwind_alloc_arq_bufs; 178 179 /* now configure the descriptors for use */ 180 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 181 182 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 183 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 184 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 185 desc->opcode = 0; 186 /* This is in accordance with Admin queue design, there is no 187 * register for buffer size configuration 188 */ 189 desc->datalen = cpu_to_le16((u16)bi->size); 190 desc->retval = 0; 191 desc->cookie_high = 0; 192 desc->cookie_low = 0; 193 desc->params.external.addr_high = 194 cpu_to_le32(upper_32_bits(bi->pa)); 195 desc->params.external.addr_low = 196 cpu_to_le32(lower_32_bits(bi->pa)); 197 desc->params.external.param0 = 0; 198 desc->params.external.param1 = 0; 199 } 200 201 alloc_arq_bufs: 202 return ret_code; 203 204 unwind_alloc_arq_bufs: 205 /* don't try to free the one that failed... */ 206 i--; 207 for (; i >= 0; i--) 208 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 209 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 210 211 return ret_code; 212 } 213 214 /** 215 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue 216 * @hw: pointer to the hardware structure 217 **/ 218 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) 219 { 220 i40e_status ret_code; 221 struct i40e_dma_mem *bi; 222 int i; 223 224 /* No mapped memory needed yet, just the buffer info structures */ 225 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, 226 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); 227 if (ret_code) 228 goto alloc_asq_bufs; 229 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; 230 231 /* allocate the mapped buffers */ 232 for (i = 0; i < hw->aq.num_asq_entries; i++) { 233 bi = &hw->aq.asq.r.asq_bi[i]; 234 ret_code = i40e_allocate_dma_mem(hw, bi, 235 i40e_mem_asq_buf, 236 hw->aq.asq_buf_size, 237 I40E_ADMINQ_DESC_ALIGNMENT); 238 if (ret_code) 239 goto unwind_alloc_asq_bufs; 240 } 241 alloc_asq_bufs: 242 return ret_code; 243 244 unwind_alloc_asq_bufs: 245 /* don't try to free the one that failed... */ 246 i--; 247 for (; i >= 0; i--) 248 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 249 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 250 251 return ret_code; 252 } 253 254 /** 255 * i40e_free_arq_bufs - Free receive queue buffer info elements 256 * @hw: pointer to the hardware structure 257 **/ 258 static void i40e_free_arq_bufs(struct i40e_hw *hw) 259 { 260 int i; 261 262 /* free descriptors */ 263 for (i = 0; i < hw->aq.num_arq_entries; i++) 264 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 265 266 /* free the descriptor memory */ 267 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 268 269 /* free the dma header */ 270 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 271 } 272 273 /** 274 * i40e_free_asq_bufs - Free send queue buffer info elements 275 * @hw: pointer to the hardware structure 276 **/ 277 static void i40e_free_asq_bufs(struct i40e_hw *hw) 278 { 279 int i; 280 281 /* only unmap if the address is non-NULL */ 282 for (i = 0; i < hw->aq.num_asq_entries; i++) 283 if (hw->aq.asq.r.asq_bi[i].pa) 284 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 285 286 /* free the buffer info list */ 287 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); 288 289 /* free the descriptor memory */ 290 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 291 292 /* free the dma header */ 293 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 294 } 295 296 /** 297 * i40e_config_asq_regs - configure ASQ registers 298 * @hw: pointer to the hardware structure 299 * 300 * Configure base address and length registers for the transmit queue 301 **/ 302 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) 303 { 304 i40e_status ret_code = 0; 305 u32 reg = 0; 306 307 /* Clear Head and Tail */ 308 wr32(hw, hw->aq.asq.head, 0); 309 wr32(hw, hw->aq.asq.tail, 0); 310 311 /* set starting point */ 312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | 313 I40E_PF_ATQLEN_ATQENABLE_MASK)); 314 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa)); 315 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa)); 316 317 /* Check one register to verify that config was applied */ 318 reg = rd32(hw, hw->aq.asq.bal); 319 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) 320 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 321 322 return ret_code; 323 } 324 325 /** 326 * i40e_config_arq_regs - ARQ register configuration 327 * @hw: pointer to the hardware structure 328 * 329 * Configure base address and length registers for the receive (event queue) 330 **/ 331 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) 332 { 333 i40e_status ret_code = 0; 334 u32 reg = 0; 335 336 /* Clear Head and Tail */ 337 wr32(hw, hw->aq.arq.head, 0); 338 wr32(hw, hw->aq.arq.tail, 0); 339 340 /* set starting point */ 341 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | 342 I40E_PF_ARQLEN_ARQENABLE_MASK)); 343 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa)); 344 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa)); 345 346 /* Update tail in the HW to post pre-allocated buffers */ 347 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 348 349 /* Check one register to verify that config was applied */ 350 reg = rd32(hw, hw->aq.arq.bal); 351 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) 352 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 353 354 return ret_code; 355 } 356 357 /** 358 * i40e_init_asq - main initialization routine for ASQ 359 * @hw: pointer to the hardware structure 360 * 361 * This is the main initialization routine for the Admin Send Queue 362 * Prior to calling this function, drivers *MUST* set the following fields 363 * in the hw->aq structure: 364 * - hw->aq.num_asq_entries 365 * - hw->aq.arq_buf_size 366 * 367 * Do *NOT* hold the lock when calling this as the memory allocation routines 368 * called are not going to be atomic context safe 369 **/ 370 static i40e_status i40e_init_asq(struct i40e_hw *hw) 371 { 372 i40e_status ret_code = 0; 373 374 if (hw->aq.asq.count > 0) { 375 /* queue already initialized */ 376 ret_code = I40E_ERR_NOT_READY; 377 goto init_adminq_exit; 378 } 379 380 /* verify input for valid configuration */ 381 if ((hw->aq.num_asq_entries == 0) || 382 (hw->aq.asq_buf_size == 0)) { 383 ret_code = I40E_ERR_CONFIG; 384 goto init_adminq_exit; 385 } 386 387 hw->aq.asq.next_to_use = 0; 388 hw->aq.asq.next_to_clean = 0; 389 hw->aq.asq.count = hw->aq.num_asq_entries; 390 391 /* allocate the ring memory */ 392 ret_code = i40e_alloc_adminq_asq_ring(hw); 393 if (ret_code) 394 goto init_adminq_exit; 395 396 /* allocate buffers in the rings */ 397 ret_code = i40e_alloc_asq_bufs(hw); 398 if (ret_code) 399 goto init_adminq_free_rings; 400 401 /* initialize base registers */ 402 ret_code = i40e_config_asq_regs(hw); 403 if (ret_code) 404 goto init_adminq_free_rings; 405 406 /* success! */ 407 goto init_adminq_exit; 408 409 init_adminq_free_rings: 410 i40e_free_adminq_asq(hw); 411 412 init_adminq_exit: 413 return ret_code; 414 } 415 416 /** 417 * i40e_init_arq - initialize ARQ 418 * @hw: pointer to the hardware structure 419 * 420 * The main initialization routine for the Admin Receive (Event) Queue. 421 * Prior to calling this function, drivers *MUST* set the following fields 422 * in the hw->aq structure: 423 * - hw->aq.num_asq_entries 424 * - hw->aq.arq_buf_size 425 * 426 * Do *NOT* hold the lock when calling this as the memory allocation routines 427 * called are not going to be atomic context safe 428 **/ 429 static i40e_status i40e_init_arq(struct i40e_hw *hw) 430 { 431 i40e_status ret_code = 0; 432 433 if (hw->aq.arq.count > 0) { 434 /* queue already initialized */ 435 ret_code = I40E_ERR_NOT_READY; 436 goto init_adminq_exit; 437 } 438 439 /* verify input for valid configuration */ 440 if ((hw->aq.num_arq_entries == 0) || 441 (hw->aq.arq_buf_size == 0)) { 442 ret_code = I40E_ERR_CONFIG; 443 goto init_adminq_exit; 444 } 445 446 hw->aq.arq.next_to_use = 0; 447 hw->aq.arq.next_to_clean = 0; 448 hw->aq.arq.count = hw->aq.num_arq_entries; 449 450 /* allocate the ring memory */ 451 ret_code = i40e_alloc_adminq_arq_ring(hw); 452 if (ret_code) 453 goto init_adminq_exit; 454 455 /* allocate buffers in the rings */ 456 ret_code = i40e_alloc_arq_bufs(hw); 457 if (ret_code) 458 goto init_adminq_free_rings; 459 460 /* initialize base registers */ 461 ret_code = i40e_config_arq_regs(hw); 462 if (ret_code) 463 goto init_adminq_free_rings; 464 465 /* success! */ 466 goto init_adminq_exit; 467 468 init_adminq_free_rings: 469 i40e_free_adminq_arq(hw); 470 471 init_adminq_exit: 472 return ret_code; 473 } 474 475 /** 476 * i40e_shutdown_asq - shutdown the ASQ 477 * @hw: pointer to the hardware structure 478 * 479 * The main shutdown routine for the Admin Send Queue 480 **/ 481 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) 482 { 483 i40e_status ret_code = 0; 484 485 if (hw->aq.asq.count == 0) 486 return I40E_ERR_NOT_READY; 487 488 /* Stop firmware AdminQ processing */ 489 wr32(hw, hw->aq.asq.head, 0); 490 wr32(hw, hw->aq.asq.tail, 0); 491 wr32(hw, hw->aq.asq.len, 0); 492 wr32(hw, hw->aq.asq.bal, 0); 493 wr32(hw, hw->aq.asq.bah, 0); 494 495 /* make sure lock is available */ 496 mutex_lock(&hw->aq.asq_mutex); 497 498 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ 499 500 /* free ring buffers */ 501 i40e_free_asq_bufs(hw); 502 503 mutex_unlock(&hw->aq.asq_mutex); 504 505 return ret_code; 506 } 507 508 /** 509 * i40e_shutdown_arq - shutdown ARQ 510 * @hw: pointer to the hardware structure 511 * 512 * The main shutdown routine for the Admin Receive Queue 513 **/ 514 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) 515 { 516 i40e_status ret_code = 0; 517 518 if (hw->aq.arq.count == 0) 519 return I40E_ERR_NOT_READY; 520 521 /* Stop firmware AdminQ processing */ 522 wr32(hw, hw->aq.arq.head, 0); 523 wr32(hw, hw->aq.arq.tail, 0); 524 wr32(hw, hw->aq.arq.len, 0); 525 wr32(hw, hw->aq.arq.bal, 0); 526 wr32(hw, hw->aq.arq.bah, 0); 527 528 /* make sure lock is available */ 529 mutex_lock(&hw->aq.arq_mutex); 530 531 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ 532 533 /* free ring buffers */ 534 i40e_free_arq_bufs(hw); 535 536 mutex_unlock(&hw->aq.arq_mutex); 537 538 return ret_code; 539 } 540 541 /** 542 * i40e_init_adminq - main initialization routine for Admin Queue 543 * @hw: pointer to the hardware structure 544 * 545 * Prior to calling this function, drivers *MUST* set the following fields 546 * in the hw->aq structure: 547 * - hw->aq.num_asq_entries 548 * - hw->aq.num_arq_entries 549 * - hw->aq.arq_buf_size 550 * - hw->aq.asq_buf_size 551 **/ 552 i40e_status i40e_init_adminq(struct i40e_hw *hw) 553 { 554 i40e_status ret_code; 555 u16 eetrack_lo, eetrack_hi; 556 int retry = 0; 557 558 /* verify input for valid configuration */ 559 if ((hw->aq.num_arq_entries == 0) || 560 (hw->aq.num_asq_entries == 0) || 561 (hw->aq.arq_buf_size == 0) || 562 (hw->aq.asq_buf_size == 0)) { 563 ret_code = I40E_ERR_CONFIG; 564 goto init_adminq_exit; 565 } 566 567 /* initialize locks */ 568 mutex_init(&hw->aq.asq_mutex); 569 mutex_init(&hw->aq.arq_mutex); 570 571 /* Set up register offsets */ 572 i40e_adminq_init_regs(hw); 573 574 /* setup ASQ command write back timeout */ 575 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; 576 577 /* allocate the ASQ */ 578 ret_code = i40e_init_asq(hw); 579 if (ret_code) 580 goto init_adminq_destroy_locks; 581 582 /* allocate the ARQ */ 583 ret_code = i40e_init_arq(hw); 584 if (ret_code) 585 goto init_adminq_free_asq; 586 587 /* There are some cases where the firmware may not be quite ready 588 * for AdminQ operations, so we retry the AdminQ setup a few times 589 * if we see timeouts in this first AQ call. 590 */ 591 do { 592 ret_code = i40e_aq_get_firmware_version(hw, 593 &hw->aq.fw_maj_ver, 594 &hw->aq.fw_min_ver, 595 &hw->aq.api_maj_ver, 596 &hw->aq.api_min_ver, 597 NULL); 598 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) 599 break; 600 retry++; 601 msleep(100); 602 i40e_resume_aq(hw); 603 } while (retry < 10); 604 if (ret_code != I40E_SUCCESS) 605 goto init_adminq_free_arq; 606 607 /* get the NVM version info */ 608 i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version); 609 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 610 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 611 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 612 613 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { 614 ret_code = I40E_ERR_FIRMWARE_API_VERSION; 615 goto init_adminq_free_arq; 616 } 617 618 /* pre-emptive resource lock release */ 619 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); 620 hw->aq.nvm_busy = false; 621 622 ret_code = i40e_aq_set_hmc_resource_profile(hw, 623 I40E_HMC_PROFILE_DEFAULT, 624 0, 625 NULL); 626 ret_code = 0; 627 628 /* success! */ 629 goto init_adminq_exit; 630 631 init_adminq_free_arq: 632 i40e_shutdown_arq(hw); 633 init_adminq_free_asq: 634 i40e_shutdown_asq(hw); 635 init_adminq_destroy_locks: 636 637 init_adminq_exit: 638 return ret_code; 639 } 640 641 /** 642 * i40e_shutdown_adminq - shutdown routine for the Admin Queue 643 * @hw: pointer to the hardware structure 644 **/ 645 i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) 646 { 647 i40e_status ret_code = 0; 648 649 if (i40e_check_asq_alive(hw)) 650 i40e_aq_queue_shutdown(hw, true); 651 652 i40e_shutdown_asq(hw); 653 i40e_shutdown_arq(hw); 654 655 /* destroy the locks */ 656 657 return ret_code; 658 } 659 660 /** 661 * i40e_clean_asq - cleans Admin send queue 662 * @hw: pointer to the hardware structure 663 * 664 * returns the number of free desc 665 **/ 666 static u16 i40e_clean_asq(struct i40e_hw *hw) 667 { 668 struct i40e_adminq_ring *asq = &(hw->aq.asq); 669 struct i40e_asq_cmd_details *details; 670 u16 ntc = asq->next_to_clean; 671 struct i40e_aq_desc desc_cb; 672 struct i40e_aq_desc *desc; 673 674 desc = I40E_ADMINQ_DESC(*asq, ntc); 675 details = I40E_ADMINQ_DETAILS(*asq, ntc); 676 while (rd32(hw, hw->aq.asq.head) != ntc) { 677 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 678 "%s: ntc %d head %d.\n", __func__, ntc, 679 rd32(hw, hw->aq.asq.head)); 680 681 if (details->callback) { 682 I40E_ADMINQ_CALLBACK cb_func = 683 (I40E_ADMINQ_CALLBACK)details->callback; 684 desc_cb = *desc; 685 cb_func(hw, &desc_cb); 686 } 687 memset(desc, 0, sizeof(*desc)); 688 memset(details, 0, sizeof(*details)); 689 ntc++; 690 if (ntc == asq->count) 691 ntc = 0; 692 desc = I40E_ADMINQ_DESC(*asq, ntc); 693 details = I40E_ADMINQ_DETAILS(*asq, ntc); 694 } 695 696 asq->next_to_clean = ntc; 697 698 return I40E_DESC_UNUSED(asq); 699 } 700 701 /** 702 * i40e_asq_done - check if FW has processed the Admin Send Queue 703 * @hw: pointer to the hw struct 704 * 705 * Returns true if the firmware has processed all descriptors on the 706 * admin send queue. Returns false if there are still requests pending. 707 **/ 708 static bool i40e_asq_done(struct i40e_hw *hw) 709 { 710 /* AQ designers suggest use of head for better 711 * timing reliability than DD bit 712 */ 713 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; 714 715 } 716 717 /** 718 * i40e_asq_send_command - send command to Admin Queue 719 * @hw: pointer to the hw struct 720 * @desc: prefilled descriptor describing the command (non DMA mem) 721 * @buff: buffer to use for indirect commands 722 * @buff_size: size of buffer for indirect commands 723 * @cmd_details: pointer to command details structure 724 * 725 * This is the main send command driver routine for the Admin Queue send 726 * queue. It runs the queue, cleans the queue, etc 727 **/ 728 i40e_status i40e_asq_send_command(struct i40e_hw *hw, 729 struct i40e_aq_desc *desc, 730 void *buff, /* can be NULL */ 731 u16 buff_size, 732 struct i40e_asq_cmd_details *cmd_details) 733 { 734 i40e_status status = 0; 735 struct i40e_dma_mem *dma_buff = NULL; 736 struct i40e_asq_cmd_details *details; 737 struct i40e_aq_desc *desc_on_ring; 738 bool cmd_completed = false; 739 u16 retval = 0; 740 u32 val = 0; 741 742 val = rd32(hw, hw->aq.asq.head); 743 if (val >= hw->aq.num_asq_entries) { 744 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 745 "AQTX: head overrun at %d\n", val); 746 status = I40E_ERR_QUEUE_EMPTY; 747 goto asq_send_command_exit; 748 } 749 750 if (hw->aq.asq.count == 0) { 751 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 752 "AQTX: Admin queue not initialized.\n"); 753 status = I40E_ERR_QUEUE_EMPTY; 754 goto asq_send_command_exit; 755 } 756 757 if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) { 758 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n"); 759 status = I40E_ERR_NVM; 760 goto asq_send_command_exit; 761 } 762 763 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); 764 if (cmd_details) { 765 *details = *cmd_details; 766 767 /* If the cmd_details are defined copy the cookie. The 768 * cpu_to_le32 is not needed here because the data is ignored 769 * by the FW, only used by the driver 770 */ 771 if (details->cookie) { 772 desc->cookie_high = 773 cpu_to_le32(upper_32_bits(details->cookie)); 774 desc->cookie_low = 775 cpu_to_le32(lower_32_bits(details->cookie)); 776 } 777 } else { 778 memset(details, 0, sizeof(struct i40e_asq_cmd_details)); 779 } 780 781 /* clear requested flags and then set additional flags if defined */ 782 desc->flags &= ~cpu_to_le16(details->flags_dis); 783 desc->flags |= cpu_to_le16(details->flags_ena); 784 785 mutex_lock(&hw->aq.asq_mutex); 786 787 if (buff_size > hw->aq.asq_buf_size) { 788 i40e_debug(hw, 789 I40E_DEBUG_AQ_MESSAGE, 790 "AQTX: Invalid buffer size: %d.\n", 791 buff_size); 792 status = I40E_ERR_INVALID_SIZE; 793 goto asq_send_command_error; 794 } 795 796 if (details->postpone && !details->async) { 797 i40e_debug(hw, 798 I40E_DEBUG_AQ_MESSAGE, 799 "AQTX: Async flag not set along with postpone flag"); 800 status = I40E_ERR_PARAM; 801 goto asq_send_command_error; 802 } 803 804 /* call clean and check queue available function to reclaim the 805 * descriptors that were processed by FW, the function returns the 806 * number of desc available 807 */ 808 /* the clean function called here could be called in a separate thread 809 * in case of asynchronous completions 810 */ 811 if (i40e_clean_asq(hw) == 0) { 812 i40e_debug(hw, 813 I40E_DEBUG_AQ_MESSAGE, 814 "AQTX: Error queue is full.\n"); 815 status = I40E_ERR_ADMIN_QUEUE_FULL; 816 goto asq_send_command_error; 817 } 818 819 /* initialize the temp desc pointer with the right desc */ 820 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); 821 822 /* if the desc is available copy the temp desc to the right place */ 823 *desc_on_ring = *desc; 824 825 /* if buff is not NULL assume indirect command */ 826 if (buff != NULL) { 827 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); 828 /* copy the user buff into the respective DMA buff */ 829 memcpy(dma_buff->va, buff, buff_size); 830 desc_on_ring->datalen = cpu_to_le16(buff_size); 831 832 /* Update the address values in the desc with the pa value 833 * for respective buffer 834 */ 835 desc_on_ring->params.external.addr_high = 836 cpu_to_le32(upper_32_bits(dma_buff->pa)); 837 desc_on_ring->params.external.addr_low = 838 cpu_to_le32(lower_32_bits(dma_buff->pa)); 839 } 840 841 /* bump the tail */ 842 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); 843 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); 844 (hw->aq.asq.next_to_use)++; 845 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 846 hw->aq.asq.next_to_use = 0; 847 if (!details->postpone) 848 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); 849 850 /* if cmd_details are not defined or async flag is not set, 851 * we need to wait for desc write back 852 */ 853 if (!details->async && !details->postpone) { 854 u32 total_delay = 0; 855 u32 delay_len = 10; 856 857 do { 858 /* AQ designers suggest use of head for better 859 * timing reliability than DD bit 860 */ 861 if (i40e_asq_done(hw)) 862 break; 863 /* ugh! delay while spin_lock */ 864 udelay(delay_len); 865 total_delay += delay_len; 866 } while (total_delay < hw->aq.asq_cmd_timeout); 867 } 868 869 /* if ready, copy the desc back to temp */ 870 if (i40e_asq_done(hw)) { 871 *desc = *desc_on_ring; 872 if (buff != NULL) 873 memcpy(buff, dma_buff->va, buff_size); 874 retval = le16_to_cpu(desc->retval); 875 if (retval != 0) { 876 i40e_debug(hw, 877 I40E_DEBUG_AQ_MESSAGE, 878 "AQTX: Command completed with error 0x%X.\n", 879 retval); 880 881 /* strip off FW internal code */ 882 retval &= 0xff; 883 } 884 cmd_completed = true; 885 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 886 status = 0; 887 else 888 status = I40E_ERR_ADMIN_QUEUE_ERROR; 889 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 890 } 891 892 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 893 "AQTX: desc and buffer writeback:\n"); 894 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff); 895 896 /* update the error if time out occurred */ 897 if ((!cmd_completed) && 898 (!details->async && !details->postpone)) { 899 i40e_debug(hw, 900 I40E_DEBUG_AQ_MESSAGE, 901 "AQTX: Writeback timeout.\n"); 902 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; 903 } 904 905 if (!status && i40e_is_nvm_update_op(desc)) 906 hw->aq.nvm_busy = true; 907 908 asq_send_command_error: 909 mutex_unlock(&hw->aq.asq_mutex); 910 asq_send_command_exit: 911 return status; 912 } 913 914 /** 915 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function 916 * @desc: pointer to the temp descriptor (non DMA mem) 917 * @opcode: the opcode can be used to decide which flags to turn off or on 918 * 919 * Fill the desc with default values 920 **/ 921 void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 922 u16 opcode) 923 { 924 /* zero out the desc */ 925 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 926 desc->opcode = cpu_to_le16(opcode); 927 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI); 928 } 929 930 /** 931 * i40e_clean_arq_element 932 * @hw: pointer to the hw struct 933 * @e: event info from the receive descriptor, includes any buffers 934 * @pending: number of events that could be left to process 935 * 936 * This function cleans one Admin Receive Queue element and returns 937 * the contents through e. It can also return how many events are 938 * left to process through 'pending' 939 **/ 940 i40e_status i40e_clean_arq_element(struct i40e_hw *hw, 941 struct i40e_arq_event_info *e, 942 u16 *pending) 943 { 944 i40e_status ret_code = 0; 945 u16 ntc = hw->aq.arq.next_to_clean; 946 struct i40e_aq_desc *desc; 947 struct i40e_dma_mem *bi; 948 u16 desc_idx; 949 u16 datalen; 950 u16 flags; 951 u16 ntu; 952 953 /* take the lock before we start messing with the ring */ 954 mutex_lock(&hw->aq.arq_mutex); 955 956 /* set next_to_use to head */ 957 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); 958 if (ntu == ntc) { 959 /* nothing to do - shouldn't need to update ring's values */ 960 i40e_debug(hw, 961 I40E_DEBUG_AQ_MESSAGE, 962 "AQRX: Queue is empty.\n"); 963 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; 964 goto clean_arq_element_out; 965 } 966 967 /* now clean the next descriptor */ 968 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 969 desc_idx = ntc; 970 971 flags = le16_to_cpu(desc->flags); 972 if (flags & I40E_AQ_FLAG_ERR) { 973 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 974 hw->aq.arq_last_status = 975 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 976 i40e_debug(hw, 977 I40E_DEBUG_AQ_MESSAGE, 978 "AQRX: Event received with error 0x%X.\n", 979 hw->aq.arq_last_status); 980 } 981 982 e->desc = *desc; 983 datalen = le16_to_cpu(desc->datalen); 984 e->msg_size = min(datalen, e->msg_size); 985 if (e->msg_buf != NULL && (e->msg_size != 0)) 986 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, 987 e->msg_size); 988 989 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); 990 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf); 991 992 /* Restore the original datalen and buffer address in the desc, 993 * FW updates datalen to indicate the event message 994 * size 995 */ 996 bi = &hw->aq.arq.r.arq_bi[ntc]; 997 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 998 999 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 1000 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 1001 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 1002 desc->datalen = cpu_to_le16((u16)bi->size); 1003 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 1004 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 1005 1006 /* set tail = the last cleaned desc index. */ 1007 wr32(hw, hw->aq.arq.tail, ntc); 1008 /* ntc is updated to tail + 1 */ 1009 ntc++; 1010 if (ntc == hw->aq.num_arq_entries) 1011 ntc = 0; 1012 hw->aq.arq.next_to_clean = ntc; 1013 hw->aq.arq.next_to_use = ntu; 1014 1015 clean_arq_element_out: 1016 /* Set pending if needed, unlock and return */ 1017 if (pending != NULL) 1018 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); 1019 mutex_unlock(&hw->aq.arq_mutex); 1020 1021 if (i40e_is_nvm_update_op(&e->desc)) { 1022 hw->aq.nvm_busy = false; 1023 if (hw->aq.nvm_release_on_done) { 1024 i40e_release_nvm(hw); 1025 hw->aq.nvm_release_on_done = false; 1026 } 1027 } 1028 1029 return ret_code; 1030 } 1031 1032 static void i40e_resume_aq(struct i40e_hw *hw) 1033 { 1034 /* Registers are reset after PF reset */ 1035 hw->aq.asq.next_to_use = 0; 1036 hw->aq.asq.next_to_clean = 0; 1037 1038 i40e_config_asq_regs(hw); 1039 1040 hw->aq.arq.next_to_use = 0; 1041 hw->aq.arq.next_to_clean = 0; 1042 1043 i40e_config_arq_regs(hw); 1044 } 1045