1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3 
4 #ifndef _I40E_H_
5 #define _I40E_H_
6 
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/udp_tunnel.h>
39 #include <net/xdp_sock.h>
40 #include "i40e_type.h"
41 #include "i40e_prototype.h"
42 #include <linux/net/intel/i40e_client.h>
43 #include <linux/avf/virtchnl.h>
44 #include "i40e_virtchnl_pf.h"
45 #include "i40e_txrx.h"
46 #include "i40e_dcb.h"
47 
48 /* Useful i40e defaults */
49 #define I40E_MAX_VEB			16
50 
51 #define I40E_MAX_NUM_DESCRIPTORS	4096
52 #define I40E_MAX_CSR_SPACE		(4 * 1024 * 1024 - 64 * 1024)
53 #define I40E_DEFAULT_NUM_DESCRIPTORS	512
54 #define I40E_REQ_DESCRIPTOR_MULTIPLE	32
55 #define I40E_MIN_NUM_DESCRIPTORS	64
56 #define I40E_MIN_MSIX			2
57 #define I40E_DEFAULT_NUM_VMDQ_VSI	8 /* max 256 VSIs */
58 #define I40E_MIN_VSI_ALLOC		83 /* LAN, ATR, FCOE, 64 VF */
59 /* max 16 qps */
60 #define i40e_default_queues_per_vmdq(pf) \
61 		(((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
62 #define I40E_DEFAULT_QUEUES_PER_VF	4
63 #define I40E_MAX_VF_QUEUES		16
64 #define i40e_pf_get_max_q_per_tc(pf) \
65 		(((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
66 #define I40E_FDIR_RING_COUNT		32
67 #define I40E_MAX_AQ_BUF_SIZE		4096
68 #define I40E_AQ_LEN			256
69 #define I40E_MIN_ARQ_LEN		1
70 #define I40E_MIN_ASQ_LEN		2
71 #define I40E_AQ_WORK_LIMIT		66 /* max number of VFs + a little */
72 #define I40E_MAX_USER_PRIORITY		8
73 #define I40E_DEFAULT_TRAFFIC_CLASS	BIT(0)
74 #define I40E_QUEUE_WAIT_RETRY_LIMIT	10
75 #define I40E_INT_NAME_STR_LEN		(IFNAMSIZ + 16)
76 
77 #define I40E_NVM_VERSION_LO_SHIFT	0
78 #define I40E_NVM_VERSION_LO_MASK	(0xff << I40E_NVM_VERSION_LO_SHIFT)
79 #define I40E_NVM_VERSION_HI_SHIFT	12
80 #define I40E_NVM_VERSION_HI_MASK	(0xf << I40E_NVM_VERSION_HI_SHIFT)
81 #define I40E_OEM_VER_BUILD_MASK		0xffff
82 #define I40E_OEM_VER_PATCH_MASK		0xff
83 #define I40E_OEM_VER_BUILD_SHIFT	8
84 #define I40E_OEM_VER_SHIFT		24
85 #define I40E_PHY_DEBUG_ALL \
86 	(I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
87 	I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
88 
89 #define I40E_OEM_EETRACK_ID		0xffffffff
90 #define I40E_OEM_GEN_SHIFT		24
91 #define I40E_OEM_SNAP_MASK		0x00ff0000
92 #define I40E_OEM_SNAP_SHIFT		16
93 #define I40E_OEM_RELEASE_MASK		0x0000ffff
94 
95 #define I40E_RX_DESC(R, i)	\
96 	(&(((union i40e_rx_desc *)((R)->desc))[i]))
97 #define I40E_TX_DESC(R, i)	\
98 	(&(((struct i40e_tx_desc *)((R)->desc))[i]))
99 #define I40E_TX_CTXTDESC(R, i)	\
100 	(&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
101 #define I40E_TX_FDIRDESC(R, i)	\
102 	(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
103 
104 /* BW rate limiting */
105 #define I40E_BW_CREDIT_DIVISOR		50 /* 50Mbps per BW credit */
106 #define I40E_BW_MBPS_DIVISOR		125000 /* rate / (1000000 / 8) Mbps */
107 #define I40E_MAX_BW_INACTIVE_ACCUM	4 /* accumulate 4 credits max */
108 
109 /* driver state flags */
110 enum i40e_state_t {
111 	__I40E_TESTING,
112 	__I40E_CONFIG_BUSY,
113 	__I40E_CONFIG_DONE,
114 	__I40E_DOWN,
115 	__I40E_SERVICE_SCHED,
116 	__I40E_ADMINQ_EVENT_PENDING,
117 	__I40E_MDD_EVENT_PENDING,
118 	__I40E_VFLR_EVENT_PENDING,
119 	__I40E_RESET_RECOVERY_PENDING,
120 	__I40E_TIMEOUT_RECOVERY_PENDING,
121 	__I40E_MISC_IRQ_REQUESTED,
122 	__I40E_RESET_INTR_RECEIVED,
123 	__I40E_REINIT_REQUESTED,
124 	__I40E_PF_RESET_REQUESTED,
125 	__I40E_PF_RESET_AND_REBUILD_REQUESTED,
126 	__I40E_CORE_RESET_REQUESTED,
127 	__I40E_GLOBAL_RESET_REQUESTED,
128 	__I40E_EMP_RESET_INTR_RECEIVED,
129 	__I40E_SUSPENDED,
130 	__I40E_PTP_TX_IN_PROGRESS,
131 	__I40E_BAD_EEPROM,
132 	__I40E_DOWN_REQUESTED,
133 	__I40E_FD_FLUSH_REQUESTED,
134 	__I40E_FD_ATR_AUTO_DISABLED,
135 	__I40E_FD_SB_AUTO_DISABLED,
136 	__I40E_RESET_FAILED,
137 	__I40E_PORT_SUSPENDED,
138 	__I40E_VF_DISABLE,
139 	__I40E_MACVLAN_SYNC_PENDING,
140 	__I40E_TEMP_LINK_POLLING,
141 	__I40E_CLIENT_SERVICE_REQUESTED,
142 	__I40E_CLIENT_L2_CHANGE,
143 	__I40E_CLIENT_RESET,
144 	__I40E_VIRTCHNL_OP_PENDING,
145 	__I40E_RECOVERY_MODE,
146 	__I40E_VF_RESETS_DISABLED,	/* disable resets during i40e_remove */
147 	__I40E_IN_REMOVE,
148 	__I40E_VFS_RELEASING,
149 	/* This must be last as it determines the size of the BITMAP */
150 	__I40E_STATE_SIZE__,
151 };
152 
153 #define I40E_PF_RESET_FLAG	BIT_ULL(__I40E_PF_RESET_REQUESTED)
154 #define I40E_PF_RESET_AND_REBUILD_FLAG	\
155 	BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
156 
157 /* VSI state flags */
158 enum i40e_vsi_state_t {
159 	__I40E_VSI_DOWN,
160 	__I40E_VSI_NEEDS_RESTART,
161 	__I40E_VSI_SYNCING_FILTERS,
162 	__I40E_VSI_OVERFLOW_PROMISC,
163 	__I40E_VSI_REINIT_REQUESTED,
164 	__I40E_VSI_DOWN_REQUESTED,
165 	__I40E_VSI_RELEASING,
166 	/* This must be last as it determines the size of the BITMAP */
167 	__I40E_VSI_STATE_SIZE__,
168 };
169 
170 enum i40e_interrupt_policy {
171 	I40E_INTERRUPT_BEST_CASE,
172 	I40E_INTERRUPT_MEDIUM,
173 	I40E_INTERRUPT_LOWEST
174 };
175 
176 struct i40e_lump_tracking {
177 	u16 num_entries;
178 	u16 list[0];
179 #define I40E_PILE_VALID_BIT  0x8000
180 #define I40E_IWARP_IRQ_PILE_ID  (I40E_PILE_VALID_BIT - 2)
181 };
182 
183 #define I40E_DEFAULT_ATR_SAMPLE_RATE	20
184 #define I40E_FDIR_MAX_RAW_PACKET_SIZE	512
185 #define I40E_FDIR_BUFFER_FULL_MARGIN	10
186 #define I40E_FDIR_BUFFER_HEAD_ROOM	32
187 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
188 
189 #define I40E_HKEY_ARRAY_SIZE	((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
190 #define I40E_HLUT_ARRAY_SIZE	((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
191 #define I40E_VF_HLUT_ARRAY_SIZE	((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
192 
193 enum i40e_fd_stat_idx {
194 	I40E_FD_STAT_ATR,
195 	I40E_FD_STAT_SB,
196 	I40E_FD_STAT_ATR_TUNNEL,
197 	I40E_FD_STAT_PF_COUNT
198 };
199 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
200 #define I40E_FD_ATR_STAT_IDX(pf_id) \
201 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
202 #define I40E_FD_SB_STAT_IDX(pf_id)  \
203 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
204 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
205 			(I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
206 
207 /* The following structure contains the data parsed from the user-defined
208  * field of the ethtool_rx_flow_spec structure.
209  */
210 struct i40e_rx_flow_userdef {
211 	bool flex_filter;
212 	u16 flex_word;
213 	u16 flex_offset;
214 };
215 
216 struct i40e_fdir_filter {
217 	struct hlist_node fdir_node;
218 	/* filter ipnut set */
219 	u8 flow_type;
220 	u8 ipl4_proto;
221 	/* TX packet view of src and dst */
222 	__be32 dst_ip;
223 	__be32 src_ip;
224 	__be32 dst_ip6[4];
225 	__be32 src_ip6[4];
226 	__be16 src_port;
227 	__be16 dst_port;
228 	__be32 sctp_v_tag;
229 
230 	__be16 vlan_etype;
231 	__be16 vlan_tag;
232 	/* Flexible data to match within the packet payload */
233 	__be16 flex_word;
234 	u16 flex_offset;
235 	bool flex_filter;
236 
237 	/* filter control */
238 	u16 q_index;
239 	u8  flex_off;
240 	u8  pctype;
241 	u16 dest_vsi;
242 	u8  dest_ctl;
243 	u8  fd_status;
244 	u16 cnt_index;
245 	u32 fd_id;
246 };
247 
248 #define I40E_CLOUD_FIELD_OMAC		BIT(0)
249 #define I40E_CLOUD_FIELD_IMAC		BIT(1)
250 #define I40E_CLOUD_FIELD_IVLAN		BIT(2)
251 #define I40E_CLOUD_FIELD_TEN_ID		BIT(3)
252 #define I40E_CLOUD_FIELD_IIP		BIT(4)
253 
254 #define I40E_CLOUD_FILTER_FLAGS_OMAC	I40E_CLOUD_FIELD_OMAC
255 #define I40E_CLOUD_FILTER_FLAGS_IMAC	I40E_CLOUD_FIELD_IMAC
256 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN	(I40E_CLOUD_FIELD_IMAC | \
257 						 I40E_CLOUD_FIELD_IVLAN)
258 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID	(I40E_CLOUD_FIELD_IMAC | \
259 						 I40E_CLOUD_FIELD_TEN_ID)
260 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
261 						  I40E_CLOUD_FIELD_IMAC | \
262 						  I40E_CLOUD_FIELD_TEN_ID)
263 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
264 						   I40E_CLOUD_FIELD_IVLAN | \
265 						   I40E_CLOUD_FIELD_TEN_ID)
266 #define I40E_CLOUD_FILTER_FLAGS_IIP	I40E_CLOUD_FIELD_IIP
267 
268 struct i40e_cloud_filter {
269 	struct hlist_node cloud_node;
270 	unsigned long cookie;
271 	/* cloud filter input set follows */
272 	u8 dst_mac[ETH_ALEN];
273 	u8 src_mac[ETH_ALEN];
274 	__be16 vlan_id;
275 	u16 seid;       /* filter control */
276 	__be16 dst_port;
277 	__be16 src_port;
278 	u32 tenant_id;
279 	union {
280 		struct {
281 			struct in_addr dst_ip;
282 			struct in_addr src_ip;
283 		} v4;
284 		struct {
285 			struct in6_addr dst_ip6;
286 			struct in6_addr src_ip6;
287 		} v6;
288 	} ip;
289 #define dst_ipv6	ip.v6.dst_ip6.s6_addr32
290 #define src_ipv6	ip.v6.src_ip6.s6_addr32
291 #define dst_ipv4	ip.v4.dst_ip.s_addr
292 #define src_ipv4	ip.v4.src_ip.s_addr
293 	u16 n_proto;    /* Ethernet Protocol */
294 	u8 ip_proto;    /* IPPROTO value */
295 	u8 flags;
296 #define I40E_CLOUD_TNL_TYPE_NONE        0xff
297 	u8 tunnel_type;
298 };
299 
300 #define I40E_DCB_PRIO_TYPE_STRICT	0
301 #define I40E_DCB_PRIO_TYPE_ETS		1
302 #define I40E_DCB_STRICT_PRIO_CREDITS	127
303 /* DCB per TC information data structure */
304 struct i40e_tc_info {
305 	u16	qoffset;	/* Queue offset from base queue */
306 	u16	qcount;		/* Total Queues */
307 	u8	netdev_tc;	/* Netdev TC index if netdev associated */
308 };
309 
310 /* TC configuration data structure */
311 struct i40e_tc_configuration {
312 	u8	numtc;		/* Total number of enabled TCs */
313 	u8	enabled_tc;	/* TC map */
314 	struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
315 };
316 
317 #define I40E_UDP_PORT_INDEX_UNUSED	255
318 struct i40e_udp_port_config {
319 	/* AdminQ command interface expects port number in Host byte order */
320 	u16 port;
321 	u8 type;
322 	u8 filter_index;
323 };
324 
325 #define I40_DDP_FLASH_REGION 100
326 #define I40E_PROFILE_INFO_SIZE 48
327 #define I40E_MAX_PROFILE_NUM 16
328 #define I40E_PROFILE_LIST_SIZE \
329 	(I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
330 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
331 #define I40E_DDP_PROFILE_NAME_MAX 64
332 
333 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
334 		  bool is_add);
335 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
336 
337 struct i40e_ddp_profile_list {
338 	u32 p_count;
339 	struct i40e_profile_info p_info[];
340 };
341 
342 struct i40e_ddp_old_profile_list {
343 	struct list_head list;
344 	size_t old_ddp_size;
345 	u8 old_ddp_buf[];
346 };
347 
348 /* macros related to FLX_PIT */
349 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
350 				    I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
351 				    I40E_PRTQF_FLX_PIT_FSIZE_MASK)
352 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
353 				     I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
354 				     I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
355 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
356 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
357 				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
358 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
359 					     I40E_FLEX_SET_FSIZE(fsize) | \
360 					     I40E_FLEX_SET_SRC_WORD(src))
361 
362 
363 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
364 
365 /* macros related to GLQF_ORT */
366 #define I40E_ORT_SET_IDX(idx)		(((idx) << \
367 					  I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
368 					 I40E_GLQF_ORT_PIT_INDX_MASK)
369 
370 #define I40E_ORT_SET_COUNT(count)	(((count) << \
371 					  I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
372 					 I40E_GLQF_ORT_FIELD_CNT_MASK)
373 
374 #define I40E_ORT_SET_PAYLOAD(payload)	(((payload) << \
375 					  I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
376 					 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
377 
378 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
379 						I40E_ORT_SET_COUNT(count) | \
380 						I40E_ORT_SET_PAYLOAD(payload))
381 
382 #define I40E_L3_GLQF_ORT_IDX		34
383 #define I40E_L4_GLQF_ORT_IDX		35
384 
385 /* Flex PIT register index */
386 #define I40E_FLEX_PIT_IDX_START_L3	3
387 #define I40E_FLEX_PIT_IDX_START_L4	6
388 
389 #define I40E_FLEX_PIT_TABLE_SIZE	3
390 
391 #define I40E_FLEX_DEST_UNUSED		63
392 
393 #define I40E_FLEX_INDEX_ENTRIES		8
394 
395 /* Flex MASK to disable all flexible entries */
396 #define I40E_FLEX_INPUT_MASK	(I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
397 				 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
398 				 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
399 				 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
400 
401 struct i40e_flex_pit {
402 	struct list_head list;
403 	u16 src_offset;
404 	u8 pit_index;
405 };
406 
407 struct i40e_fwd_adapter {
408 	struct net_device *netdev;
409 	int bit_no;
410 };
411 
412 struct i40e_channel {
413 	struct list_head list;
414 	bool initialized;
415 	u8 type;
416 	u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
417 	u16 stat_counter_idx;
418 	u16 base_queue;
419 	u16 num_queue_pairs; /* Requested by user */
420 	u16 seid;
421 
422 	u8 enabled_tc;
423 	struct i40e_aqc_vsi_properties_data info;
424 
425 	u64 max_tx_rate;
426 	struct i40e_fwd_adapter *fwd;
427 
428 	/* track this channel belongs to which VSI */
429 	struct i40e_vsi *parent_vsi;
430 };
431 
432 struct i40e_ptp_pins_settings;
433 
434 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
435 {
436 	return !!ch->fwd;
437 }
438 
439 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
440 {
441 	if (i40e_is_channel_macvlan(ch))
442 		return ch->fwd->netdev->dev_addr;
443 	else
444 		return NULL;
445 }
446 
447 /* struct that defines the Ethernet device */
448 struct i40e_pf {
449 	struct pci_dev *pdev;
450 	struct i40e_hw hw;
451 	DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
452 	struct msix_entry *msix_entries;
453 	bool fc_autoneg_status;
454 
455 	u16 eeprom_version;
456 	u16 num_vmdq_vsis;         /* num vmdq vsis this PF has set up */
457 	u16 num_vmdq_qps;          /* num queue pairs per vmdq pool */
458 	u16 num_vmdq_msix;         /* num queue vectors per vmdq pool */
459 	u16 num_req_vfs;           /* num VFs requested for this PF */
460 	u16 num_vf_qps;            /* num queue pairs per VF */
461 	u16 num_lan_qps;           /* num lan queues this PF has set up */
462 	u16 num_lan_msix;          /* num queue vectors for the base PF vsi */
463 	u16 num_fdsb_msix;         /* num queue vectors for sideband Fdir */
464 	u16 num_iwarp_msix;        /* num of iwarp vectors for this PF */
465 	int iwarp_base_vector;
466 	int queues_left;           /* queues left unclaimed */
467 	u16 alloc_rss_size;        /* allocated RSS queues */
468 	u16 rss_size_max;          /* HW defined max RSS queues */
469 	u16 fdir_pf_filter_count;  /* num of guaranteed filters for this PF */
470 	u16 num_alloc_vsi;         /* num VSIs this driver supports */
471 	u8 atr_sample_rate;
472 	bool wol_en;
473 
474 	struct hlist_head fdir_filter_list;
475 	u16 fdir_pf_active_filters;
476 	unsigned long fd_flush_timestamp;
477 	u32 fd_flush_cnt;
478 	u32 fd_add_err;
479 	u32 fd_atr_cnt;
480 
481 	/* Book-keeping of side-band filter count per flow-type.
482 	 * This is used to detect and handle input set changes for
483 	 * respective flow-type.
484 	 */
485 	u16 fd_tcp4_filter_cnt;
486 	u16 fd_udp4_filter_cnt;
487 	u16 fd_sctp4_filter_cnt;
488 	u16 fd_ip4_filter_cnt;
489 
490 	u16 fd_tcp6_filter_cnt;
491 	u16 fd_udp6_filter_cnt;
492 	u16 fd_sctp6_filter_cnt;
493 	u16 fd_ip6_filter_cnt;
494 
495 	/* Flexible filter table values that need to be programmed into
496 	 * hardware, which expects L3 and L4 to be programmed separately. We
497 	 * need to ensure that the values are in ascended order and don't have
498 	 * duplicates, so we track each L3 and L4 values in separate lists.
499 	 */
500 	struct list_head l3_flex_pit_list;
501 	struct list_head l4_flex_pit_list;
502 
503 	struct udp_tunnel_nic_shared udp_tunnel_shared;
504 	struct udp_tunnel_nic_info udp_tunnel_nic;
505 
506 	struct hlist_head cloud_filter_list;
507 	u16 num_cloud_filters;
508 
509 	enum i40e_interrupt_policy int_policy;
510 	u16 rx_itr_default;
511 	u16 tx_itr_default;
512 	u32 msg_enable;
513 	char int_name[I40E_INT_NAME_STR_LEN];
514 	u16 adminq_work_limit; /* num of admin receive queue desc to process */
515 	unsigned long service_timer_period;
516 	unsigned long service_timer_previous;
517 	struct timer_list service_timer;
518 	struct work_struct service_task;
519 
520 	u32 hw_features;
521 #define I40E_HW_RSS_AQ_CAPABLE			BIT(0)
522 #define I40E_HW_128_QP_RSS_CAPABLE		BIT(1)
523 #define I40E_HW_ATR_EVICT_CAPABLE		BIT(2)
524 #define I40E_HW_WB_ON_ITR_CAPABLE		BIT(3)
525 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE	BIT(4)
526 #define I40E_HW_NO_PCI_LINK_CHECK		BIT(5)
527 #define I40E_HW_100M_SGMII_CAPABLE		BIT(6)
528 #define I40E_HW_NO_DCB_SUPPORT			BIT(7)
529 #define I40E_HW_USE_SET_LLDP_MIB		BIT(8)
530 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE		BIT(9)
531 #define I40E_HW_PTP_L4_CAPABLE			BIT(10)
532 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE		BIT(11)
533 #define I40E_HW_HAVE_CRT_RETIMER		BIT(13)
534 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE		BIT(14)
535 #define I40E_HW_PHY_CONTROLS_LEDS		BIT(15)
536 #define I40E_HW_STOP_FW_LLDP			BIT(16)
537 #define I40E_HW_PORT_ID_VALID			BIT(17)
538 #define I40E_HW_RESTART_AUTONEG			BIT(18)
539 
540 	u32 flags;
541 #define I40E_FLAG_RX_CSUM_ENABLED		BIT(0)
542 #define I40E_FLAG_MSI_ENABLED			BIT(1)
543 #define I40E_FLAG_MSIX_ENABLED			BIT(2)
544 #define I40E_FLAG_RSS_ENABLED			BIT(3)
545 #define I40E_FLAG_VMDQ_ENABLED			BIT(4)
546 #define I40E_FLAG_SRIOV_ENABLED			BIT(5)
547 #define I40E_FLAG_DCB_CAPABLE			BIT(6)
548 #define I40E_FLAG_DCB_ENABLED			BIT(7)
549 #define I40E_FLAG_FD_SB_ENABLED			BIT(8)
550 #define I40E_FLAG_FD_ATR_ENABLED		BIT(9)
551 #define I40E_FLAG_MFP_ENABLED			BIT(10)
552 #define I40E_FLAG_HW_ATR_EVICT_ENABLED		BIT(11)
553 #define I40E_FLAG_VEB_MODE_ENABLED		BIT(12)
554 #define I40E_FLAG_VEB_STATS_ENABLED		BIT(13)
555 #define I40E_FLAG_LINK_POLLING_ENABLED		BIT(14)
556 #define I40E_FLAG_TRUE_PROMISC_SUPPORT		BIT(15)
557 #define I40E_FLAG_LEGACY_RX			BIT(16)
558 #define I40E_FLAG_PTP				BIT(17)
559 #define I40E_FLAG_IWARP_ENABLED			BIT(18)
560 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(19)
561 #define I40E_FLAG_SOURCE_PRUNING_DISABLED       BIT(20)
562 #define I40E_FLAG_TC_MQPRIO			BIT(21)
563 #define I40E_FLAG_FD_SB_INACTIVE		BIT(22)
564 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER		BIT(23)
565 #define I40E_FLAG_DISABLE_FW_LLDP		BIT(24)
566 #define I40E_FLAG_RS_FEC			BIT(25)
567 #define I40E_FLAG_BASE_R_FEC			BIT(26)
568 /* TOTAL_PORT_SHUTDOWN
569  * Allows to physically disable the link on the NIC's port.
570  * If enabled, (after link down request from the OS)
571  * no link, traffic or led activity is possible on that port.
572  *
573  * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
574  * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
575  * and cannot be disabled by system admin at that time.
576  * The functionalities are exclusive in terms of configuration, but they also
577  * have similar behavior (allowing to disable physical link of the port),
578  * with following differences:
579  * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
580  *   supported by whole family of 7xx Intel Ethernet Controllers
581  * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
582  *   only if motherboard's BIOS and NIC's FW has support of it
583  * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
584  *   by sending phy_type=0 to NIC's FW
585  * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
586  *   the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
587  *   in abilities field of i40e_aq_set_phy_config structure
588  */
589 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED	BIT(27)
590 
591 	struct i40e_client_instance *cinst;
592 	bool stat_offsets_loaded;
593 	struct i40e_hw_port_stats stats;
594 	struct i40e_hw_port_stats stats_offsets;
595 	u32 tx_timeout_count;
596 	u32 tx_timeout_recovery_level;
597 	unsigned long tx_timeout_last_recovery;
598 	u32 tx_sluggish_count;
599 	u32 hw_csum_rx_error;
600 	u32 led_status;
601 	u16 corer_count; /* Core reset count */
602 	u16 globr_count; /* Global reset count */
603 	u16 empr_count; /* EMP reset count */
604 	u16 pfr_count; /* PF reset count */
605 	u16 sw_int_count; /* SW interrupt count */
606 
607 	struct mutex switch_mutex;
608 	u16 lan_vsi;       /* our default LAN VSI */
609 	u16 lan_veb;       /* initial relay, if exists */
610 #define I40E_NO_VEB	0xffff
611 #define I40E_NO_VSI	0xffff
612 	u16 next_vsi;      /* Next unallocated VSI - 0-based! */
613 	struct i40e_vsi **vsi;
614 	struct i40e_veb *veb[I40E_MAX_VEB];
615 
616 	struct i40e_lump_tracking *qp_pile;
617 	struct i40e_lump_tracking *irq_pile;
618 
619 	/* switch config info */
620 	u16 pf_seid;
621 	u16 main_vsi_seid;
622 	u16 mac_seid;
623 	struct kobject *switch_kobj;
624 #ifdef CONFIG_DEBUG_FS
625 	struct dentry *i40e_dbg_pf;
626 #endif /* CONFIG_DEBUG_FS */
627 	bool cur_promisc;
628 
629 	u16 instance; /* A unique number per i40e_pf instance in the system */
630 
631 	/* sr-iov config info */
632 	struct i40e_vf *vf;
633 	int num_alloc_vfs;	/* actual number of VFs allocated */
634 	u32 vf_aq_requests;
635 	u32 arq_overflows;	/* Not fatal, possibly indicative of problems */
636 
637 	/* DCBx/DCBNL capability for PF that indicates
638 	 * whether DCBx is managed by firmware or host
639 	 * based agent (LLDPAD). Also, indicates what
640 	 * flavor of DCBx protocol (IEEE/CEE) is supported
641 	 * by the device. For now we're supporting IEEE
642 	 * mode only.
643 	 */
644 	u16 dcbx_cap;
645 
646 	struct i40e_filter_control_settings filter_settings;
647 	struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
648 	struct i40e_dcbx_config tmp_cfg;
649 
650 /* GPIO defines used by PTP */
651 #define I40E_SDP3_2			18
652 #define I40E_SDP3_3			19
653 #define I40E_GPIO_4			20
654 #define I40E_LED2_0			26
655 #define I40E_LED2_1			27
656 #define I40E_LED3_0			28
657 #define I40E_LED3_1			29
658 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
659 	(1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
660 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
661 	(1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
662 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
663 	(0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
664 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
665 	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
666 #define I40E_GLGEN_GPIO_CTL_RESERVED	BIT(2)
667 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
668 	(1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
669 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
670 	(1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
671 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
672 	(1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
673 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
674 	(1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
675 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
676 	(3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
677 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
678 	(4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
679 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
680 	(0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
681 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
682 	(1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
683 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
684 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
685 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
686 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
687 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
688 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
689 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
690 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
691 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
692 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
693 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
694 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
695 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
696 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
697 	(I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
698 	 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
699 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
700 	 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
701 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
702 	(I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
703 	 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
704 	 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
705 	 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
706 	 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
707 	 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
708 #define I40E_PRTTSYN_AUX_1_INSTNT \
709 	(1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
710 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
711 	(1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
712 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD	(3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
713 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
714 	(I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
715 #define I40E_PTP_HALF_SECOND		500000000LL /* nano seconds */
716 #define I40E_PTP_2_SEC_DELAY		2
717 
718 	struct ptp_clock *ptp_clock;
719 	struct ptp_clock_info ptp_caps;
720 	struct sk_buff *ptp_tx_skb;
721 	unsigned long ptp_tx_start;
722 	struct hwtstamp_config tstamp_config;
723 	struct timespec64 ptp_prev_hw_time;
724 	struct work_struct ptp_pps_work;
725 	struct work_struct ptp_extts0_work;
726 	struct work_struct ptp_extts1_work;
727 	ktime_t ptp_reset_start;
728 	struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
729 	u32 ptp_adj_mult;
730 	u32 tx_hwtstamp_timeouts;
731 	u32 tx_hwtstamp_skipped;
732 	u32 rx_hwtstamp_cleared;
733 	u32 latch_event_flags;
734 	u64 ptp_pps_start;
735 	u32 pps_delay;
736 	spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
737 	struct ptp_pin_desc ptp_pin[3];
738 	unsigned long latch_events[4];
739 	bool ptp_tx;
740 	bool ptp_rx;
741 	struct i40e_ptp_pins_settings *ptp_pins;
742 	u16 rss_table_size; /* HW RSS table size */
743 	u32 max_bw;
744 	u32 min_bw;
745 
746 	u32 ioremap_len;
747 	u32 fd_inv;
748 	u16 phy_led_val;
749 
750 	u16 override_q_count;
751 	u16 last_sw_conf_flags;
752 	u16 last_sw_conf_valid_flags;
753 	/* List to keep previous DDP profiles to be rolled back in the future */
754 	struct list_head ddp_old_prof;
755 };
756 
757 /**
758  * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
759  * @macaddr: the MAC Address as the base key
760  *
761  * Simply copies the address and returns it as a u64 for hashing
762  **/
763 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
764 {
765 	u64 key = 0;
766 
767 	ether_addr_copy((u8 *)&key, macaddr);
768 	return key;
769 }
770 
771 enum i40e_filter_state {
772 	I40E_FILTER_INVALID = 0,	/* Invalid state */
773 	I40E_FILTER_NEW,		/* New, not sent to FW yet */
774 	I40E_FILTER_ACTIVE,		/* Added to switch by FW */
775 	I40E_FILTER_FAILED,		/* Rejected by FW */
776 	I40E_FILTER_REMOVE,		/* To be removed */
777 /* There is no 'removed' state; the filter struct is freed */
778 };
779 struct i40e_mac_filter {
780 	struct hlist_node hlist;
781 	u8 macaddr[ETH_ALEN];
782 #define I40E_VLAN_ANY -1
783 	s16 vlan;
784 	enum i40e_filter_state state;
785 };
786 
787 /* Wrapper structure to keep track of filters while we are preparing to send
788  * firmware commands. We cannot send firmware commands while holding a
789  * spinlock, since it might sleep. To avoid this, we wrap the added filters in
790  * a separate structure, which will track the state change and update the real
791  * filter while under lock. We can't simply hold the filters in a separate
792  * list, as this opens a window for a race condition when adding new MAC
793  * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
794  */
795 struct i40e_new_mac_filter {
796 	struct hlist_node hlist;
797 	struct i40e_mac_filter *f;
798 
799 	/* Track future changes to state separately */
800 	enum i40e_filter_state state;
801 };
802 
803 struct i40e_veb {
804 	struct i40e_pf *pf;
805 	u16 idx;
806 	u16 veb_idx;		/* index of VEB parent */
807 	u16 seid;
808 	u16 uplink_seid;
809 	u16 stats_idx;		/* index of VEB parent */
810 	u8  enabled_tc;
811 	u16 bridge_mode;	/* Bridge Mode (VEB/VEPA) */
812 	u16 flags;
813 	u16 bw_limit;
814 	u8  bw_max_quanta;
815 	bool is_abs_credits;
816 	u8  bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
817 	u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
818 	u8  bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
819 	struct kobject *kobj;
820 	bool stat_offsets_loaded;
821 	struct i40e_eth_stats stats;
822 	struct i40e_eth_stats stats_offsets;
823 	struct i40e_veb_tc_stats tc_stats;
824 	struct i40e_veb_tc_stats tc_stats_offsets;
825 };
826 
827 /* struct that defines a VSI, associated with a dev */
828 struct i40e_vsi {
829 	struct net_device *netdev;
830 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
831 	bool netdev_registered;
832 	bool stat_offsets_loaded;
833 
834 	u32 current_netdev_flags;
835 	DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
836 #define I40E_VSI_FLAG_FILTER_CHANGED	BIT(0)
837 #define I40E_VSI_FLAG_VEB_OWNER		BIT(1)
838 	unsigned long flags;
839 
840 	/* Per VSI lock to protect elements/hash (MAC filter) */
841 	spinlock_t mac_filter_hash_lock;
842 	/* Fixed size hash table with 2^8 buckets for MAC filters */
843 	DECLARE_HASHTABLE(mac_filter_hash, 8);
844 	bool has_vlan_filter;
845 
846 	/* VSI stats */
847 	struct rtnl_link_stats64 net_stats;
848 	struct rtnl_link_stats64 net_stats_offsets;
849 	struct i40e_eth_stats eth_stats;
850 	struct i40e_eth_stats eth_stats_offsets;
851 	u64 tx_restart;
852 	u64 tx_busy;
853 	u64 tx_linearize;
854 	u64 tx_force_wb;
855 	u64 rx_buf_failed;
856 	u64 rx_page_failed;
857 
858 	/* These are containers of ring pointers, allocated at run-time */
859 	struct i40e_ring **rx_rings;
860 	struct i40e_ring **tx_rings;
861 	struct i40e_ring **xdp_rings; /* XDP Tx rings */
862 
863 	u32  active_filters;
864 	u32  promisc_threshold;
865 
866 	u16 work_limit;
867 	u16 int_rate_limit;	/* value in usecs */
868 
869 	u16 rss_table_size;	/* HW RSS table size */
870 	u16 rss_size;		/* Allocated RSS queues */
871 	u8  *rss_hkey_user;	/* User configured hash keys */
872 	u8  *rss_lut_user;	/* User configured lookup table entries */
873 
874 
875 	u16 max_frame;
876 	u16 rx_buf_len;
877 
878 	struct bpf_prog *xdp_prog;
879 
880 	/* List of q_vectors allocated to this VSI */
881 	struct i40e_q_vector **q_vectors;
882 	int num_q_vectors;
883 	int base_vector;
884 	bool irqs_ready;
885 
886 	u16 seid;		/* HW index of this VSI (absolute index) */
887 	u16 id;			/* VSI number */
888 	u16 uplink_seid;
889 
890 	u16 base_queue;		/* vsi's first queue in hw array */
891 	u16 alloc_queue_pairs;	/* Allocated Tx/Rx queues */
892 	u16 req_queue_pairs;	/* User requested queue pairs */
893 	u16 num_queue_pairs;	/* Used tx and rx pairs */
894 	u16 num_tx_desc;
895 	u16 num_rx_desc;
896 	enum i40e_vsi_type type;  /* VSI type, e.g., LAN, FCoE, etc */
897 	s16 vf_id;		/* Virtual function ID for SRIOV VSIs */
898 
899 	struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
900 	struct i40e_tc_configuration tc_config;
901 	struct i40e_aqc_vsi_properties_data info;
902 
903 	/* VSI BW limit (absolute across all TCs) */
904 	u16 bw_limit;		/* VSI BW Limit (0 = disabled) */
905 	u8  bw_max_quanta;	/* Max Quanta when BW limit is enabled */
906 
907 	/* Relative TC credits across VSIs */
908 	u8  bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
909 	/* TC BW limit credits within VSI */
910 	u16  bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
911 	/* TC BW limit max quanta within VSI */
912 	u8  bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
913 
914 	struct i40e_pf *back;	/* Backreference to associated PF */
915 	u16 idx;		/* index in pf->vsi[] */
916 	u16 veb_idx;		/* index of VEB parent */
917 	struct kobject *kobj;	/* sysfs object */
918 	bool current_isup;	/* Sync 'link up' logging */
919 	enum i40e_aq_link_speed current_speed;	/* Sync link speed logging */
920 
921 	/* channel specific fields */
922 	u16 cnt_q_avail;	/* num of queues available for channel usage */
923 	u16 orig_rss_size;
924 	u16 current_rss_size;
925 	bool reconfig_rss;
926 
927 	u16 next_base_queue;	/* next queue to be used for channel setup */
928 
929 	struct list_head ch_list;
930 	u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
931 
932 	/* macvlan fields */
933 #define I40E_MAX_MACVLANS		128 /* Max HW vectors - 1 on FVL */
934 #define I40E_MIN_MACVLAN_VECTORS	2   /* Min vectors to enable macvlans */
935 	DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
936 	struct list_head macvlan_list;
937 	int macvlan_cnt;
938 
939 	void *priv;	/* client driver data reference. */
940 
941 	/* VSI specific handlers */
942 	irqreturn_t (*irq_handler)(int irq, void *data);
943 
944 	unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
945 } ____cacheline_internodealigned_in_smp;
946 
947 struct i40e_netdev_priv {
948 	struct i40e_vsi *vsi;
949 };
950 
951 extern struct ida i40e_client_ida;
952 
953 /* struct that defines an interrupt vector */
954 struct i40e_q_vector {
955 	struct i40e_vsi *vsi;
956 
957 	u16 v_idx;		/* index in the vsi->q_vector array. */
958 	u16 reg_idx;		/* register index of the interrupt */
959 
960 	struct napi_struct napi;
961 
962 	struct i40e_ring_container rx;
963 	struct i40e_ring_container tx;
964 
965 	u8 itr_countdown;	/* when 0 should adjust adaptive ITR */
966 	u8 num_ringpairs;	/* total number of ring pairs in vector */
967 
968 	cpumask_t affinity_mask;
969 	struct irq_affinity_notify affinity_notify;
970 
971 	struct rcu_head rcu;	/* to avoid race with update stats on free */
972 	char name[I40E_INT_NAME_STR_LEN];
973 	bool arm_wb_state;
974 } ____cacheline_internodealigned_in_smp;
975 
976 /* lan device */
977 struct i40e_device {
978 	struct list_head list;
979 	struct i40e_pf *pf;
980 };
981 
982 /**
983  * i40e_nvm_version_str - format the NVM version strings
984  * @hw: ptr to the hardware info
985  **/
986 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
987 {
988 	static char buf[32];
989 	u32 full_ver;
990 
991 	full_ver = hw->nvm.oem_ver;
992 
993 	if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
994 		u8 gen, snap;
995 		u16 release;
996 
997 		gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
998 		snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
999 			I40E_OEM_SNAP_SHIFT);
1000 		release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
1001 
1002 		snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
1003 	} else {
1004 		u8 ver, patch;
1005 		u16 build;
1006 
1007 		ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1008 		build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1009 			 I40E_OEM_VER_BUILD_MASK);
1010 		patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1011 
1012 		snprintf(buf, sizeof(buf),
1013 			 "%x.%02x 0x%x %d.%d.%d",
1014 			 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1015 				I40E_NVM_VERSION_HI_SHIFT,
1016 			 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1017 				I40E_NVM_VERSION_LO_SHIFT,
1018 			 hw->nvm.eetrack, ver, build, patch);
1019 	}
1020 
1021 	return buf;
1022 }
1023 
1024 /**
1025  * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1026  * @netdev: the corresponding netdev
1027  *
1028  * Return the PF struct for the given netdev
1029  **/
1030 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1031 {
1032 	struct i40e_netdev_priv *np = netdev_priv(netdev);
1033 	struct i40e_vsi *vsi = np->vsi;
1034 
1035 	return vsi->back;
1036 }
1037 
1038 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1039 				irqreturn_t (*irq_handler)(int, void *))
1040 {
1041 	vsi->irq_handler = irq_handler;
1042 }
1043 
1044 /**
1045  * i40e_get_fd_cnt_all - get the total FD filter space available
1046  * @pf: pointer to the PF struct
1047  **/
1048 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1049 {
1050 	return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1051 }
1052 
1053 /**
1054  * i40e_read_fd_input_set - reads value of flow director input set register
1055  * @pf: pointer to the PF struct
1056  * @addr: register addr
1057  *
1058  * This function reads value of flow director input set register
1059  * specified by 'addr' (which is specific to flow-type)
1060  **/
1061 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1062 {
1063 	u64 val;
1064 
1065 	val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1066 	val <<= 32;
1067 	val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1068 
1069 	return val;
1070 }
1071 
1072 /**
1073  * i40e_write_fd_input_set - writes value into flow director input set register
1074  * @pf: pointer to the PF struct
1075  * @addr: register addr
1076  * @val: value to be written
1077  *
1078  * This function writes specified value to the register specified by 'addr'.
1079  * This register is input set register based on flow-type.
1080  **/
1081 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1082 					   u16 addr, u64 val)
1083 {
1084 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1085 			  (u32)(val >> 32));
1086 	i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1087 			  (u32)(val & 0xFFFFFFFFULL));
1088 }
1089 
1090 /* needed by i40e_ethtool.c */
1091 int i40e_up(struct i40e_vsi *vsi);
1092 void i40e_down(struct i40e_vsi *vsi);
1093 extern const char i40e_driver_name[];
1094 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1095 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1096 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1097 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1098 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1099 		       u16 rss_table_size, u16 rss_size);
1100 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1101 /**
1102  * i40e_find_vsi_by_type - Find and return Flow Director VSI
1103  * @pf: PF to search for VSI
1104  * @type: Value indicating type of VSI we are looking for
1105  **/
1106 static inline struct i40e_vsi *
1107 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1108 {
1109 	int i;
1110 
1111 	for (i = 0; i < pf->num_alloc_vsi; i++) {
1112 		struct i40e_vsi *vsi = pf->vsi[i];
1113 
1114 		if (vsi && vsi->type == type)
1115 			return vsi;
1116 	}
1117 
1118 	return NULL;
1119 }
1120 void i40e_update_stats(struct i40e_vsi *vsi);
1121 void i40e_update_veb_stats(struct i40e_veb *veb);
1122 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1123 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1124 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1125 				    bool printconfig);
1126 
1127 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1128 		      struct i40e_fdir_filter *input, bool add);
1129 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1130 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1131 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1132 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1133 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1134 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1135 void i40e_set_ethtool_ops(struct net_device *netdev);
1136 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1137 					const u8 *macaddr, s16 vlan);
1138 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1139 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1140 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1141 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1142 				u16 uplink, u32 param1);
1143 int i40e_vsi_release(struct i40e_vsi *vsi);
1144 void i40e_service_event_schedule(struct i40e_pf *pf);
1145 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1146 				  u8 *msg, u16 len);
1147 
1148 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1149 			   bool enable);
1150 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1151 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1152 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1153 void i40e_vsi_stop_rings_no_wait(struct  i40e_vsi *vsi);
1154 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1155 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1156 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1157 				u16 downlink_seid, u8 enabled_tc);
1158 void i40e_veb_release(struct i40e_veb *veb);
1159 
1160 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1161 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1162 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1163 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1164 void i40e_pf_reset_stats(struct i40e_pf *pf);
1165 #ifdef CONFIG_DEBUG_FS
1166 void i40e_dbg_pf_init(struct i40e_pf *pf);
1167 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1168 void i40e_dbg_init(void);
1169 void i40e_dbg_exit(void);
1170 #else
1171 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1172 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1173 static inline void i40e_dbg_init(void) {}
1174 static inline void i40e_dbg_exit(void) {}
1175 #endif /* CONFIG_DEBUG_FS*/
1176 /* needed by client drivers */
1177 int i40e_lan_add_device(struct i40e_pf *pf);
1178 int i40e_lan_del_device(struct i40e_pf *pf);
1179 void i40e_client_subtask(struct i40e_pf *pf);
1180 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1181 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1182 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1183 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1184 void i40e_client_update_msix_info(struct i40e_pf *pf);
1185 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1186 /**
1187  * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1188  * @vsi: pointer to a vsi
1189  * @vector: enable a particular Hw Interrupt vector, without base_vector
1190  **/
1191 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1192 {
1193 	struct i40e_pf *pf = vsi->back;
1194 	struct i40e_hw *hw = &pf->hw;
1195 	u32 val;
1196 
1197 	val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1198 	      I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1199 	      (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1200 	wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1201 	/* skip the flush */
1202 }
1203 
1204 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1205 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1206 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1207 int i40e_open(struct net_device *netdev);
1208 int i40e_close(struct net_device *netdev);
1209 int i40e_vsi_open(struct i40e_vsi *vsi);
1210 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1211 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1212 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1213 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1214 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1215 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1216 					    const u8 *macaddr);
1217 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1218 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1219 int i40e_count_filters(struct i40e_vsi *vsi);
1220 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1221 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1222 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1223 {
1224 	return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1225 }
1226 
1227 #ifdef CONFIG_I40E_DCB
1228 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1229 			   struct i40e_dcbx_config *old_cfg,
1230 			   struct i40e_dcbx_config *new_cfg);
1231 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1232 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1233 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1234 			    struct i40e_dcbx_config *old_cfg,
1235 			    struct i40e_dcbx_config *new_cfg);
1236 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1237 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1238 #endif /* CONFIG_I40E_DCB */
1239 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1240 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1241 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1242 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1243 void i40e_ptp_set_increment(struct i40e_pf *pf);
1244 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1245 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1246 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1247 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1248 void i40e_ptp_init(struct i40e_pf *pf);
1249 void i40e_ptp_stop(struct i40e_pf *pf);
1250 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1251 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1252 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1253 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1254 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1255 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1256 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1257 
1258 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1259 
1260 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1261 {
1262 	return !!READ_ONCE(vsi->xdp_prog);
1263 }
1264 
1265 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1266 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1267 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1268 			      struct i40e_cloud_filter *filter,
1269 			      bool add);
1270 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1271 				      struct i40e_cloud_filter *filter,
1272 				      bool add);
1273 #endif /* _I40E_H_ */
1274