1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2021 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_macvlan.h> 31 #include <linux/if_bridge.h> 32 #include <linux/clocksource.h> 33 #include <linux/net_tstamp.h> 34 #include <linux/ptp_clock_kernel.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_mirred.h> 38 #include <net/udp_tunnel.h> 39 #include <net/xdp_sock.h> 40 #include "i40e_type.h" 41 #include "i40e_prototype.h" 42 #include <linux/net/intel/i40e_client.h> 43 #include <linux/avf/virtchnl.h> 44 #include "i40e_virtchnl_pf.h" 45 #include "i40e_txrx.h" 46 #include "i40e_dcb.h" 47 48 /* Useful i40e defaults */ 49 #define I40E_MAX_VEB 16 50 51 #define I40E_MAX_NUM_DESCRIPTORS 4096 52 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 53 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 54 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 55 #define I40E_MIN_NUM_DESCRIPTORS 64 56 #define I40E_MIN_MSIX 2 57 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 58 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 59 /* max 16 qps */ 60 #define i40e_default_queues_per_vmdq(pf) \ 61 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 62 #define I40E_DEFAULT_QUEUES_PER_VF 4 63 #define I40E_MAX_VF_QUEUES 16 64 #define i40e_pf_get_max_q_per_tc(pf) \ 65 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 66 #define I40E_FDIR_RING_COUNT 32 67 #define I40E_MAX_AQ_BUF_SIZE 4096 68 #define I40E_AQ_LEN 256 69 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 70 #define I40E_MAX_USER_PRIORITY 8 71 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 72 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 73 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 74 75 #define I40E_NVM_VERSION_LO_SHIFT 0 76 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 77 #define I40E_NVM_VERSION_HI_SHIFT 12 78 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 79 #define I40E_OEM_VER_BUILD_MASK 0xffff 80 #define I40E_OEM_VER_PATCH_MASK 0xff 81 #define I40E_OEM_VER_BUILD_SHIFT 8 82 #define I40E_OEM_VER_SHIFT 24 83 #define I40E_PHY_DEBUG_ALL \ 84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 86 87 #define I40E_OEM_EETRACK_ID 0xffffffff 88 #define I40E_OEM_GEN_SHIFT 24 89 #define I40E_OEM_SNAP_MASK 0x00ff0000 90 #define I40E_OEM_SNAP_SHIFT 16 91 #define I40E_OEM_RELEASE_MASK 0x0000ffff 92 93 #define I40E_RX_DESC(R, i) \ 94 (&(((union i40e_rx_desc *)((R)->desc))[i])) 95 #define I40E_TX_DESC(R, i) \ 96 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 97 #define I40E_TX_CTXTDESC(R, i) \ 98 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 99 #define I40E_TX_FDIRDESC(R, i) \ 100 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 101 102 /* BW rate limiting */ 103 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 104 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 105 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 106 107 /* driver state flags */ 108 enum i40e_state_t { 109 __I40E_TESTING, 110 __I40E_CONFIG_BUSY, 111 __I40E_CONFIG_DONE, 112 __I40E_DOWN, 113 __I40E_SERVICE_SCHED, 114 __I40E_ADMINQ_EVENT_PENDING, 115 __I40E_MDD_EVENT_PENDING, 116 __I40E_VFLR_EVENT_PENDING, 117 __I40E_RESET_RECOVERY_PENDING, 118 __I40E_TIMEOUT_RECOVERY_PENDING, 119 __I40E_MISC_IRQ_REQUESTED, 120 __I40E_RESET_INTR_RECEIVED, 121 __I40E_REINIT_REQUESTED, 122 __I40E_PF_RESET_REQUESTED, 123 __I40E_PF_RESET_AND_REBUILD_REQUESTED, 124 __I40E_CORE_RESET_REQUESTED, 125 __I40E_GLOBAL_RESET_REQUESTED, 126 __I40E_EMP_RESET_INTR_RECEIVED, 127 __I40E_SUSPENDED, 128 __I40E_PTP_TX_IN_PROGRESS, 129 __I40E_BAD_EEPROM, 130 __I40E_DOWN_REQUESTED, 131 __I40E_FD_FLUSH_REQUESTED, 132 __I40E_FD_ATR_AUTO_DISABLED, 133 __I40E_FD_SB_AUTO_DISABLED, 134 __I40E_RESET_FAILED, 135 __I40E_PORT_SUSPENDED, 136 __I40E_VF_DISABLE, 137 __I40E_MACVLAN_SYNC_PENDING, 138 __I40E_TEMP_LINK_POLLING, 139 __I40E_CLIENT_SERVICE_REQUESTED, 140 __I40E_CLIENT_L2_CHANGE, 141 __I40E_CLIENT_RESET, 142 __I40E_VIRTCHNL_OP_PENDING, 143 __I40E_RECOVERY_MODE, 144 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */ 145 __I40E_VFS_RELEASING, 146 /* This must be last as it determines the size of the BITMAP */ 147 __I40E_STATE_SIZE__, 148 }; 149 150 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 151 #define I40E_PF_RESET_AND_REBUILD_FLAG \ 152 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED) 153 154 /* VSI state flags */ 155 enum i40e_vsi_state_t { 156 __I40E_VSI_DOWN, 157 __I40E_VSI_NEEDS_RESTART, 158 __I40E_VSI_SYNCING_FILTERS, 159 __I40E_VSI_OVERFLOW_PROMISC, 160 __I40E_VSI_REINIT_REQUESTED, 161 __I40E_VSI_DOWN_REQUESTED, 162 /* This must be last as it determines the size of the BITMAP */ 163 __I40E_VSI_STATE_SIZE__, 164 }; 165 166 enum i40e_interrupt_policy { 167 I40E_INTERRUPT_BEST_CASE, 168 I40E_INTERRUPT_MEDIUM, 169 I40E_INTERRUPT_LOWEST 170 }; 171 172 struct i40e_lump_tracking { 173 u16 num_entries; 174 u16 search_hint; 175 u16 list[0]; 176 #define I40E_PILE_VALID_BIT 0x8000 177 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 178 }; 179 180 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 181 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 182 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 183 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 184 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 185 186 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 187 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 188 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 189 190 enum i40e_fd_stat_idx { 191 I40E_FD_STAT_ATR, 192 I40E_FD_STAT_SB, 193 I40E_FD_STAT_ATR_TUNNEL, 194 I40E_FD_STAT_PF_COUNT 195 }; 196 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 197 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 198 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 199 #define I40E_FD_SB_STAT_IDX(pf_id) \ 200 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 201 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 203 204 /* The following structure contains the data parsed from the user-defined 205 * field of the ethtool_rx_flow_spec structure. 206 */ 207 struct i40e_rx_flow_userdef { 208 bool flex_filter; 209 u16 flex_word; 210 u16 flex_offset; 211 }; 212 213 struct i40e_fdir_filter { 214 struct hlist_node fdir_node; 215 /* filter ipnut set */ 216 u8 flow_type; 217 u8 ipl4_proto; 218 /* TX packet view of src and dst */ 219 __be32 dst_ip; 220 __be32 src_ip; 221 __be32 dst_ip6[4]; 222 __be32 src_ip6[4]; 223 __be16 src_port; 224 __be16 dst_port; 225 __be32 sctp_v_tag; 226 227 __be16 vlan_etype; 228 __be16 vlan_tag; 229 /* Flexible data to match within the packet payload */ 230 __be16 flex_word; 231 u16 flex_offset; 232 bool flex_filter; 233 234 /* filter control */ 235 u16 q_index; 236 u8 flex_off; 237 u8 pctype; 238 u16 dest_vsi; 239 u8 dest_ctl; 240 u8 fd_status; 241 u16 cnt_index; 242 u32 fd_id; 243 }; 244 245 #define I40E_CLOUD_FIELD_OMAC BIT(0) 246 #define I40E_CLOUD_FIELD_IMAC BIT(1) 247 #define I40E_CLOUD_FIELD_IVLAN BIT(2) 248 #define I40E_CLOUD_FIELD_TEN_ID BIT(3) 249 #define I40E_CLOUD_FIELD_IIP BIT(4) 250 251 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 252 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 253 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 254 I40E_CLOUD_FIELD_IVLAN) 255 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_TEN_ID) 257 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 258 I40E_CLOUD_FIELD_IMAC | \ 259 I40E_CLOUD_FIELD_TEN_ID) 260 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 261 I40E_CLOUD_FIELD_IVLAN | \ 262 I40E_CLOUD_FIELD_TEN_ID) 263 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 264 265 struct i40e_cloud_filter { 266 struct hlist_node cloud_node; 267 unsigned long cookie; 268 /* cloud filter input set follows */ 269 u8 dst_mac[ETH_ALEN]; 270 u8 src_mac[ETH_ALEN]; 271 __be16 vlan_id; 272 u16 seid; /* filter control */ 273 __be16 dst_port; 274 __be16 src_port; 275 u32 tenant_id; 276 union { 277 struct { 278 struct in_addr dst_ip; 279 struct in_addr src_ip; 280 } v4; 281 struct { 282 struct in6_addr dst_ip6; 283 struct in6_addr src_ip6; 284 } v6; 285 } ip; 286 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 287 #define src_ipv6 ip.v6.src_ip6.s6_addr32 288 #define dst_ipv4 ip.v4.dst_ip.s_addr 289 #define src_ipv4 ip.v4.src_ip.s_addr 290 u16 n_proto; /* Ethernet Protocol */ 291 u8 ip_proto; /* IPPROTO value */ 292 u8 flags; 293 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 294 u8 tunnel_type; 295 }; 296 297 #define I40E_DCB_PRIO_TYPE_STRICT 0 298 #define I40E_DCB_PRIO_TYPE_ETS 1 299 #define I40E_DCB_STRICT_PRIO_CREDITS 127 300 /* DCB per TC information data structure */ 301 struct i40e_tc_info { 302 u16 qoffset; /* Queue offset from base queue */ 303 u16 qcount; /* Total Queues */ 304 u8 netdev_tc; /* Netdev TC index if netdev associated */ 305 }; 306 307 /* TC configuration data structure */ 308 struct i40e_tc_configuration { 309 u8 numtc; /* Total number of enabled TCs */ 310 u8 enabled_tc; /* TC map */ 311 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 312 }; 313 314 #define I40E_UDP_PORT_INDEX_UNUSED 255 315 struct i40e_udp_port_config { 316 /* AdminQ command interface expects port number in Host byte order */ 317 u16 port; 318 u8 type; 319 u8 filter_index; 320 }; 321 322 #define I40_DDP_FLASH_REGION 100 323 #define I40E_PROFILE_INFO_SIZE 48 324 #define I40E_MAX_PROFILE_NUM 16 325 #define I40E_PROFILE_LIST_SIZE \ 326 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4) 327 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/" 328 #define I40E_DDP_PROFILE_NAME_MAX 64 329 330 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size, 331 bool is_add); 332 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash); 333 334 struct i40e_ddp_profile_list { 335 u32 p_count; 336 struct i40e_profile_info p_info[]; 337 }; 338 339 struct i40e_ddp_old_profile_list { 340 struct list_head list; 341 size_t old_ddp_size; 342 u8 old_ddp_buf[]; 343 }; 344 345 /* macros related to FLX_PIT */ 346 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 347 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 348 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 349 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 350 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 351 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 352 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 353 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 354 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 355 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 356 I40E_FLEX_SET_FSIZE(fsize) | \ 357 I40E_FLEX_SET_SRC_WORD(src)) 358 359 360 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 361 362 /* macros related to GLQF_ORT */ 363 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 364 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 365 I40E_GLQF_ORT_PIT_INDX_MASK) 366 367 #define I40E_ORT_SET_COUNT(count) (((count) << \ 368 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 369 I40E_GLQF_ORT_FIELD_CNT_MASK) 370 371 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 372 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 373 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 374 375 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 376 I40E_ORT_SET_COUNT(count) | \ 377 I40E_ORT_SET_PAYLOAD(payload)) 378 379 #define I40E_L3_GLQF_ORT_IDX 34 380 #define I40E_L4_GLQF_ORT_IDX 35 381 382 /* Flex PIT register index */ 383 #define I40E_FLEX_PIT_IDX_START_L3 3 384 #define I40E_FLEX_PIT_IDX_START_L4 6 385 386 #define I40E_FLEX_PIT_TABLE_SIZE 3 387 388 #define I40E_FLEX_DEST_UNUSED 63 389 390 #define I40E_FLEX_INDEX_ENTRIES 8 391 392 /* Flex MASK to disable all flexible entries */ 393 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 394 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 395 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 396 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 397 398 struct i40e_flex_pit { 399 struct list_head list; 400 u16 src_offset; 401 u8 pit_index; 402 }; 403 404 struct i40e_fwd_adapter { 405 struct net_device *netdev; 406 int bit_no; 407 }; 408 409 struct i40e_channel { 410 struct list_head list; 411 bool initialized; 412 u8 type; 413 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 414 u16 stat_counter_idx; 415 u16 base_queue; 416 u16 num_queue_pairs; /* Requested by user */ 417 u16 seid; 418 419 u8 enabled_tc; 420 struct i40e_aqc_vsi_properties_data info; 421 422 u64 max_tx_rate; 423 struct i40e_fwd_adapter *fwd; 424 425 /* track this channel belongs to which VSI */ 426 struct i40e_vsi *parent_vsi; 427 }; 428 429 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch) 430 { 431 return !!ch->fwd; 432 } 433 434 static inline u8 *i40e_channel_mac(struct i40e_channel *ch) 435 { 436 if (i40e_is_channel_macvlan(ch)) 437 return ch->fwd->netdev->dev_addr; 438 else 439 return NULL; 440 } 441 442 /* struct that defines the Ethernet device */ 443 struct i40e_pf { 444 struct pci_dev *pdev; 445 struct i40e_hw hw; 446 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 447 struct msix_entry *msix_entries; 448 bool fc_autoneg_status; 449 450 u16 eeprom_version; 451 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 452 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 453 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 454 u16 num_req_vfs; /* num VFs requested for this PF */ 455 u16 num_vf_qps; /* num queue pairs per VF */ 456 u16 num_lan_qps; /* num lan queues this PF has set up */ 457 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 458 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 459 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 460 int iwarp_base_vector; 461 int queues_left; /* queues left unclaimed */ 462 u16 alloc_rss_size; /* allocated RSS queues */ 463 u16 rss_size_max; /* HW defined max RSS queues */ 464 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 465 u16 num_alloc_vsi; /* num VSIs this driver supports */ 466 u8 atr_sample_rate; 467 bool wol_en; 468 469 struct hlist_head fdir_filter_list; 470 u16 fdir_pf_active_filters; 471 unsigned long fd_flush_timestamp; 472 u32 fd_flush_cnt; 473 u32 fd_add_err; 474 u32 fd_atr_cnt; 475 476 /* Book-keeping of side-band filter count per flow-type. 477 * This is used to detect and handle input set changes for 478 * respective flow-type. 479 */ 480 u16 fd_tcp4_filter_cnt; 481 u16 fd_udp4_filter_cnt; 482 u16 fd_sctp4_filter_cnt; 483 u16 fd_ip4_filter_cnt; 484 485 u16 fd_tcp6_filter_cnt; 486 u16 fd_udp6_filter_cnt; 487 u16 fd_sctp6_filter_cnt; 488 u16 fd_ip6_filter_cnt; 489 490 /* Flexible filter table values that need to be programmed into 491 * hardware, which expects L3 and L4 to be programmed separately. We 492 * need to ensure that the values are in ascended order and don't have 493 * duplicates, so we track each L3 and L4 values in separate lists. 494 */ 495 struct list_head l3_flex_pit_list; 496 struct list_head l4_flex_pit_list; 497 498 struct udp_tunnel_nic_shared udp_tunnel_shared; 499 struct udp_tunnel_nic_info udp_tunnel_nic; 500 501 struct hlist_head cloud_filter_list; 502 u16 num_cloud_filters; 503 504 enum i40e_interrupt_policy int_policy; 505 u16 rx_itr_default; 506 u16 tx_itr_default; 507 u32 msg_enable; 508 char int_name[I40E_INT_NAME_STR_LEN]; 509 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 510 unsigned long service_timer_period; 511 unsigned long service_timer_previous; 512 struct timer_list service_timer; 513 struct work_struct service_task; 514 515 u32 hw_features; 516 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 517 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 518 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 519 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 520 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 521 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 522 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 523 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 524 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 525 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 526 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 527 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 528 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 529 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 530 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 531 #define I40E_HW_STOP_FW_LLDP BIT(16) 532 #define I40E_HW_PORT_ID_VALID BIT(17) 533 #define I40E_HW_RESTART_AUTONEG BIT(18) 534 535 u32 flags; 536 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 537 #define I40E_FLAG_MSI_ENABLED BIT(1) 538 #define I40E_FLAG_MSIX_ENABLED BIT(2) 539 #define I40E_FLAG_RSS_ENABLED BIT(3) 540 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 541 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 542 #define I40E_FLAG_DCB_CAPABLE BIT(6) 543 #define I40E_FLAG_DCB_ENABLED BIT(7) 544 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 545 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 546 #define I40E_FLAG_MFP_ENABLED BIT(10) 547 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 548 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 549 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 550 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 551 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 552 #define I40E_FLAG_LEGACY_RX BIT(16) 553 #define I40E_FLAG_PTP BIT(17) 554 #define I40E_FLAG_IWARP_ENABLED BIT(18) 555 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 556 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 557 #define I40E_FLAG_TC_MQPRIO BIT(21) 558 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 559 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 560 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 561 #define I40E_FLAG_RS_FEC BIT(25) 562 #define I40E_FLAG_BASE_R_FEC BIT(26) 563 /* TOTAL_PORT_SHUTDOWN 564 * Allows to physically disable the link on the NIC's port. 565 * If enabled, (after link down request from the OS) 566 * no link, traffic or led activity is possible on that port. 567 * 568 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the 569 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true 570 * and cannot be disabled by system admin at that time. 571 * The functionalities are exclusive in terms of configuration, but they also 572 * have similar behavior (allowing to disable physical link of the port), 573 * with following differences: 574 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is 575 * supported by whole family of 7xx Intel Ethernet Controllers 576 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS) 577 * only if motherboard's BIOS and NIC's FW has support of it 578 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down 579 * by sending phy_type=0 to NIC's FW 580 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead 581 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK) 582 * in abilities field of i40e_aq_set_phy_config structure 583 */ 584 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27) 585 586 struct i40e_client_instance *cinst; 587 bool stat_offsets_loaded; 588 struct i40e_hw_port_stats stats; 589 struct i40e_hw_port_stats stats_offsets; 590 u32 tx_timeout_count; 591 u32 tx_timeout_recovery_level; 592 unsigned long tx_timeout_last_recovery; 593 u32 tx_sluggish_count; 594 u32 hw_csum_rx_error; 595 u32 led_status; 596 u16 corer_count; /* Core reset count */ 597 u16 globr_count; /* Global reset count */ 598 u16 empr_count; /* EMP reset count */ 599 u16 pfr_count; /* PF reset count */ 600 u16 sw_int_count; /* SW interrupt count */ 601 602 struct mutex switch_mutex; 603 u16 lan_vsi; /* our default LAN VSI */ 604 u16 lan_veb; /* initial relay, if exists */ 605 #define I40E_NO_VEB 0xffff 606 #define I40E_NO_VSI 0xffff 607 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 608 struct i40e_vsi **vsi; 609 struct i40e_veb *veb[I40E_MAX_VEB]; 610 611 struct i40e_lump_tracking *qp_pile; 612 struct i40e_lump_tracking *irq_pile; 613 614 /* switch config info */ 615 u16 pf_seid; 616 u16 main_vsi_seid; 617 u16 mac_seid; 618 struct kobject *switch_kobj; 619 #ifdef CONFIG_DEBUG_FS 620 struct dentry *i40e_dbg_pf; 621 #endif /* CONFIG_DEBUG_FS */ 622 bool cur_promisc; 623 624 u16 instance; /* A unique number per i40e_pf instance in the system */ 625 626 /* sr-iov config info */ 627 struct i40e_vf *vf; 628 int num_alloc_vfs; /* actual number of VFs allocated */ 629 u32 vf_aq_requests; 630 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 631 632 /* DCBx/DCBNL capability for PF that indicates 633 * whether DCBx is managed by firmware or host 634 * based agent (LLDPAD). Also, indicates what 635 * flavor of DCBx protocol (IEEE/CEE) is supported 636 * by the device. For now we're supporting IEEE 637 * mode only. 638 */ 639 u16 dcbx_cap; 640 641 struct i40e_filter_control_settings filter_settings; 642 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */ 643 struct i40e_dcbx_config tmp_cfg; 644 645 struct ptp_clock *ptp_clock; 646 struct ptp_clock_info ptp_caps; 647 struct sk_buff *ptp_tx_skb; 648 unsigned long ptp_tx_start; 649 struct hwtstamp_config tstamp_config; 650 struct timespec64 ptp_prev_hw_time; 651 ktime_t ptp_reset_start; 652 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 653 u32 ptp_adj_mult; 654 u32 tx_hwtstamp_timeouts; 655 u32 tx_hwtstamp_skipped; 656 u32 rx_hwtstamp_cleared; 657 u32 latch_event_flags; 658 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 659 unsigned long latch_events[4]; 660 bool ptp_tx; 661 bool ptp_rx; 662 u16 rss_table_size; /* HW RSS table size */ 663 u32 max_bw; 664 u32 min_bw; 665 666 u32 ioremap_len; 667 u32 fd_inv; 668 u16 phy_led_val; 669 670 u16 override_q_count; 671 u16 last_sw_conf_flags; 672 u16 last_sw_conf_valid_flags; 673 /* List to keep previous DDP profiles to be rolled back in the future */ 674 struct list_head ddp_old_prof; 675 }; 676 677 /** 678 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 679 * @macaddr: the MAC Address as the base key 680 * 681 * Simply copies the address and returns it as a u64 for hashing 682 **/ 683 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 684 { 685 u64 key = 0; 686 687 ether_addr_copy((u8 *)&key, macaddr); 688 return key; 689 } 690 691 enum i40e_filter_state { 692 I40E_FILTER_INVALID = 0, /* Invalid state */ 693 I40E_FILTER_NEW, /* New, not sent to FW yet */ 694 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 695 I40E_FILTER_FAILED, /* Rejected by FW */ 696 I40E_FILTER_REMOVE, /* To be removed */ 697 /* There is no 'removed' state; the filter struct is freed */ 698 }; 699 struct i40e_mac_filter { 700 struct hlist_node hlist; 701 u8 macaddr[ETH_ALEN]; 702 #define I40E_VLAN_ANY -1 703 s16 vlan; 704 enum i40e_filter_state state; 705 }; 706 707 /* Wrapper structure to keep track of filters while we are preparing to send 708 * firmware commands. We cannot send firmware commands while holding a 709 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 710 * a separate structure, which will track the state change and update the real 711 * filter while under lock. We can't simply hold the filters in a separate 712 * list, as this opens a window for a race condition when adding new MAC 713 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 714 */ 715 struct i40e_new_mac_filter { 716 struct hlist_node hlist; 717 struct i40e_mac_filter *f; 718 719 /* Track future changes to state separately */ 720 enum i40e_filter_state state; 721 }; 722 723 struct i40e_veb { 724 struct i40e_pf *pf; 725 u16 idx; 726 u16 veb_idx; /* index of VEB parent */ 727 u16 seid; 728 u16 uplink_seid; 729 u16 stats_idx; /* index of VEB parent */ 730 u8 enabled_tc; 731 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 732 u16 flags; 733 u16 bw_limit; 734 u8 bw_max_quanta; 735 bool is_abs_credits; 736 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 737 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 738 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 739 struct kobject *kobj; 740 bool stat_offsets_loaded; 741 struct i40e_eth_stats stats; 742 struct i40e_eth_stats stats_offsets; 743 struct i40e_veb_tc_stats tc_stats; 744 struct i40e_veb_tc_stats tc_stats_offsets; 745 }; 746 747 /* struct that defines a VSI, associated with a dev */ 748 struct i40e_vsi { 749 struct net_device *netdev; 750 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 751 bool netdev_registered; 752 bool stat_offsets_loaded; 753 754 u32 current_netdev_flags; 755 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 756 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 757 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 758 unsigned long flags; 759 760 /* Per VSI lock to protect elements/hash (MAC filter) */ 761 spinlock_t mac_filter_hash_lock; 762 /* Fixed size hash table with 2^8 buckets for MAC filters */ 763 DECLARE_HASHTABLE(mac_filter_hash, 8); 764 bool has_vlan_filter; 765 766 /* VSI stats */ 767 struct rtnl_link_stats64 net_stats; 768 struct rtnl_link_stats64 net_stats_offsets; 769 struct i40e_eth_stats eth_stats; 770 struct i40e_eth_stats eth_stats_offsets; 771 u32 tx_restart; 772 u32 tx_busy; 773 u64 tx_linearize; 774 u64 tx_force_wb; 775 u32 rx_buf_failed; 776 u32 rx_page_failed; 777 778 /* These are containers of ring pointers, allocated at run-time */ 779 struct i40e_ring **rx_rings; 780 struct i40e_ring **tx_rings; 781 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 782 783 u32 active_filters; 784 u32 promisc_threshold; 785 786 u16 work_limit; 787 u16 int_rate_limit; /* value in usecs */ 788 789 u16 rss_table_size; /* HW RSS table size */ 790 u16 rss_size; /* Allocated RSS queues */ 791 u8 *rss_hkey_user; /* User configured hash keys */ 792 u8 *rss_lut_user; /* User configured lookup table entries */ 793 794 795 u16 max_frame; 796 u16 rx_buf_len; 797 798 struct bpf_prog *xdp_prog; 799 800 /* List of q_vectors allocated to this VSI */ 801 struct i40e_q_vector **q_vectors; 802 int num_q_vectors; 803 int base_vector; 804 bool irqs_ready; 805 806 u16 seid; /* HW index of this VSI (absolute index) */ 807 u16 id; /* VSI number */ 808 u16 uplink_seid; 809 810 u16 base_queue; /* vsi's first queue in hw array */ 811 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 812 u16 req_queue_pairs; /* User requested queue pairs */ 813 u16 num_queue_pairs; /* Used tx and rx pairs */ 814 u16 num_tx_desc; 815 u16 num_rx_desc; 816 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 817 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 818 819 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 820 struct i40e_tc_configuration tc_config; 821 struct i40e_aqc_vsi_properties_data info; 822 823 /* VSI BW limit (absolute across all TCs) */ 824 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 825 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 826 827 /* Relative TC credits across VSIs */ 828 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 829 /* TC BW limit credits within VSI */ 830 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 831 /* TC BW limit max quanta within VSI */ 832 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 833 834 struct i40e_pf *back; /* Backreference to associated PF */ 835 u16 idx; /* index in pf->vsi[] */ 836 u16 veb_idx; /* index of VEB parent */ 837 struct kobject *kobj; /* sysfs object */ 838 bool current_isup; /* Sync 'link up' logging */ 839 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 840 841 /* channel specific fields */ 842 u16 cnt_q_avail; /* num of queues available for channel usage */ 843 u16 orig_rss_size; 844 u16 current_rss_size; 845 bool reconfig_rss; 846 847 u16 next_base_queue; /* next queue to be used for channel setup */ 848 849 struct list_head ch_list; 850 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 851 852 /* macvlan fields */ 853 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */ 854 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */ 855 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS); 856 struct list_head macvlan_list; 857 int macvlan_cnt; 858 859 void *priv; /* client driver data reference. */ 860 861 /* VSI specific handlers */ 862 irqreturn_t (*irq_handler)(int irq, void *data); 863 864 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */ 865 } ____cacheline_internodealigned_in_smp; 866 867 struct i40e_netdev_priv { 868 struct i40e_vsi *vsi; 869 }; 870 871 /* struct that defines an interrupt vector */ 872 struct i40e_q_vector { 873 struct i40e_vsi *vsi; 874 875 u16 v_idx; /* index in the vsi->q_vector array. */ 876 u16 reg_idx; /* register index of the interrupt */ 877 878 struct napi_struct napi; 879 880 struct i40e_ring_container rx; 881 struct i40e_ring_container tx; 882 883 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 884 u8 num_ringpairs; /* total number of ring pairs in vector */ 885 886 cpumask_t affinity_mask; 887 struct irq_affinity_notify affinity_notify; 888 889 struct rcu_head rcu; /* to avoid race with update stats on free */ 890 char name[I40E_INT_NAME_STR_LEN]; 891 bool arm_wb_state; 892 } ____cacheline_internodealigned_in_smp; 893 894 /* lan device */ 895 struct i40e_device { 896 struct list_head list; 897 struct i40e_pf *pf; 898 }; 899 900 /** 901 * i40e_nvm_version_str - format the NVM version strings 902 * @hw: ptr to the hardware info 903 **/ 904 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 905 { 906 static char buf[32]; 907 u32 full_ver; 908 909 full_ver = hw->nvm.oem_ver; 910 911 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 912 u8 gen, snap; 913 u16 release; 914 915 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 916 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 917 I40E_OEM_SNAP_SHIFT); 918 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 919 920 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 921 } else { 922 u8 ver, patch; 923 u16 build; 924 925 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 926 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 927 I40E_OEM_VER_BUILD_MASK); 928 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 929 930 snprintf(buf, sizeof(buf), 931 "%x.%02x 0x%x %d.%d.%d", 932 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 933 I40E_NVM_VERSION_HI_SHIFT, 934 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 935 I40E_NVM_VERSION_LO_SHIFT, 936 hw->nvm.eetrack, ver, build, patch); 937 } 938 939 return buf; 940 } 941 942 /** 943 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 944 * @netdev: the corresponding netdev 945 * 946 * Return the PF struct for the given netdev 947 **/ 948 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 949 { 950 struct i40e_netdev_priv *np = netdev_priv(netdev); 951 struct i40e_vsi *vsi = np->vsi; 952 953 return vsi->back; 954 } 955 956 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 957 irqreturn_t (*irq_handler)(int, void *)) 958 { 959 vsi->irq_handler = irq_handler; 960 } 961 962 /** 963 * i40e_get_fd_cnt_all - get the total FD filter space available 964 * @pf: pointer to the PF struct 965 **/ 966 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 967 { 968 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 969 } 970 971 /** 972 * i40e_read_fd_input_set - reads value of flow director input set register 973 * @pf: pointer to the PF struct 974 * @addr: register addr 975 * 976 * This function reads value of flow director input set register 977 * specified by 'addr' (which is specific to flow-type) 978 **/ 979 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 980 { 981 u64 val; 982 983 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 984 val <<= 32; 985 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 986 987 return val; 988 } 989 990 /** 991 * i40e_write_fd_input_set - writes value into flow director input set register 992 * @pf: pointer to the PF struct 993 * @addr: register addr 994 * @val: value to be written 995 * 996 * This function writes specified value to the register specified by 'addr'. 997 * This register is input set register based on flow-type. 998 **/ 999 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 1000 u16 addr, u64 val) 1001 { 1002 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 1003 (u32)(val >> 32)); 1004 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 1005 (u32)(val & 0xFFFFFFFFULL)); 1006 } 1007 1008 /* needed by i40e_ethtool.c */ 1009 int i40e_up(struct i40e_vsi *vsi); 1010 void i40e_down(struct i40e_vsi *vsi); 1011 extern const char i40e_driver_name[]; 1012 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 1013 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 1014 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1015 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 1016 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 1017 u16 rss_table_size, u16 rss_size); 1018 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 1019 /** 1020 * i40e_find_vsi_by_type - Find and return Flow Director VSI 1021 * @pf: PF to search for VSI 1022 * @type: Value indicating type of VSI we are looking for 1023 **/ 1024 static inline struct i40e_vsi * 1025 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 1026 { 1027 int i; 1028 1029 for (i = 0; i < pf->num_alloc_vsi; i++) { 1030 struct i40e_vsi *vsi = pf->vsi[i]; 1031 1032 if (vsi && vsi->type == type) 1033 return vsi; 1034 } 1035 1036 return NULL; 1037 } 1038 void i40e_update_stats(struct i40e_vsi *vsi); 1039 void i40e_update_veb_stats(struct i40e_veb *veb); 1040 void i40e_update_eth_stats(struct i40e_vsi *vsi); 1041 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 1042 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 1043 bool printconfig); 1044 1045 int i40e_add_del_fdir(struct i40e_vsi *vsi, 1046 struct i40e_fdir_filter *input, bool add); 1047 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 1048 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 1049 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 1050 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 1051 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 1052 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 1053 void i40e_set_ethtool_ops(struct net_device *netdev); 1054 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 1055 const u8 *macaddr, s16 vlan); 1056 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 1057 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 1058 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 1059 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 1060 u16 uplink, u32 param1); 1061 int i40e_vsi_release(struct i40e_vsi *vsi); 1062 void i40e_service_event_schedule(struct i40e_pf *pf); 1063 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 1064 u8 *msg, u16 len); 1065 1066 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 1067 bool enable); 1068 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 1069 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 1070 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 1071 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 1072 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 1073 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 1074 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 1075 u16 downlink_seid, u8 enabled_tc); 1076 void i40e_veb_release(struct i40e_veb *veb); 1077 1078 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1079 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1080 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1081 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1082 void i40e_pf_reset_stats(struct i40e_pf *pf); 1083 #ifdef CONFIG_DEBUG_FS 1084 void i40e_dbg_pf_init(struct i40e_pf *pf); 1085 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1086 void i40e_dbg_init(void); 1087 void i40e_dbg_exit(void); 1088 #else 1089 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1090 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1091 static inline void i40e_dbg_init(void) {} 1092 static inline void i40e_dbg_exit(void) {} 1093 #endif /* CONFIG_DEBUG_FS*/ 1094 /* needed by client drivers */ 1095 int i40e_lan_add_device(struct i40e_pf *pf); 1096 int i40e_lan_del_device(struct i40e_pf *pf); 1097 void i40e_client_subtask(struct i40e_pf *pf); 1098 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1099 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1100 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1101 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1102 void i40e_client_update_msix_info(struct i40e_pf *pf); 1103 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1104 /** 1105 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1106 * @vsi: pointer to a vsi 1107 * @vector: enable a particular Hw Interrupt vector, without base_vector 1108 **/ 1109 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1110 { 1111 struct i40e_pf *pf = vsi->back; 1112 struct i40e_hw *hw = &pf->hw; 1113 u32 val; 1114 1115 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1116 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1117 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1118 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1119 /* skip the flush */ 1120 } 1121 1122 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1123 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1124 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1125 int i40e_open(struct net_device *netdev); 1126 int i40e_close(struct net_device *netdev); 1127 int i40e_vsi_open(struct i40e_vsi *vsi); 1128 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1129 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1130 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1131 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1132 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1133 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1134 const u8 *macaddr); 1135 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1136 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1137 int i40e_count_filters(struct i40e_vsi *vsi); 1138 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1139 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1140 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) 1141 { 1142 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP); 1143 } 1144 1145 void i40e_set_lldp_forwarding(struct i40e_pf *pf, bool enable); 1146 #ifdef CONFIG_I40E_DCB 1147 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1148 struct i40e_dcbx_config *old_cfg, 1149 struct i40e_dcbx_config *new_cfg); 1150 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1151 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1152 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1153 struct i40e_dcbx_config *old_cfg, 1154 struct i40e_dcbx_config *new_cfg); 1155 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); 1156 int i40e_dcb_sw_default_config(struct i40e_pf *pf); 1157 #endif /* CONFIG_I40E_DCB */ 1158 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1159 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1160 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1161 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1162 void i40e_ptp_set_increment(struct i40e_pf *pf); 1163 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1164 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1165 void i40e_ptp_save_hw_time(struct i40e_pf *pf); 1166 void i40e_ptp_restore_hw_time(struct i40e_pf *pf); 1167 void i40e_ptp_init(struct i40e_pf *pf); 1168 void i40e_ptp_stop(struct i40e_pf *pf); 1169 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1170 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1171 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1172 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1173 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1174 1175 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags); 1176 1177 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1178 { 1179 return !!READ_ONCE(vsi->xdp_prog); 1180 } 1181 1182 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1183 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1184 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1185 struct i40e_cloud_filter *filter, 1186 bool add); 1187 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1188 struct i40e_cloud_filter *filter, 1189 bool add); 1190 #endif /* _I40E_H_ */ 1191