1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4 #ifndef _I40E_H_ 5 #define _I40E_H_ 6 7 #include <net/tcp.h> 8 #include <net/udp.h> 9 #include <linux/types.h> 10 #include <linux/errno.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/aer.h> 14 #include <linux/netdevice.h> 15 #include <linux/ioport.h> 16 #include <linux/iommu.h> 17 #include <linux/slab.h> 18 #include <linux/list.h> 19 #include <linux/hashtable.h> 20 #include <linux/string.h> 21 #include <linux/in.h> 22 #include <linux/ip.h> 23 #include <linux/sctp.h> 24 #include <linux/pkt_sched.h> 25 #include <linux/ipv6.h> 26 #include <net/checksum.h> 27 #include <net/ip6_checksum.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/if_bridge.h> 31 #include <linux/clocksource.h> 32 #include <linux/net_tstamp.h> 33 #include <linux/ptp_clock_kernel.h> 34 #include <net/pkt_cls.h> 35 #include <net/tc_act/tc_gact.h> 36 #include <net/tc_act/tc_mirred.h> 37 #include "i40e_type.h" 38 #include "i40e_prototype.h" 39 #include "i40e_client.h" 40 #include <linux/avf/virtchnl.h> 41 #include "i40e_virtchnl_pf.h" 42 #include "i40e_txrx.h" 43 #include "i40e_dcb.h" 44 45 /* Useful i40e defaults */ 46 #define I40E_MAX_VEB 16 47 48 #define I40E_MAX_NUM_DESCRIPTORS 4096 49 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024) 50 #define I40E_DEFAULT_NUM_DESCRIPTORS 512 51 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32 52 #define I40E_MIN_NUM_DESCRIPTORS 64 53 #define I40E_MIN_MSIX 2 54 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */ 55 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */ 56 /* max 16 qps */ 57 #define i40e_default_queues_per_vmdq(pf) \ 58 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1) 59 #define I40E_DEFAULT_QUEUES_PER_VF 4 60 #define I40E_MAX_VF_QUEUES 16 61 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */ 62 #define i40e_pf_get_max_q_per_tc(pf) \ 63 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64) 64 #define I40E_FDIR_RING 0 65 #define I40E_FDIR_RING_COUNT 32 66 #define I40E_MAX_AQ_BUF_SIZE 4096 67 #define I40E_AQ_LEN 256 68 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */ 69 #define I40E_MAX_USER_PRIORITY 8 70 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0) 71 #define I40E_DEFAULT_MSG_ENABLE 4 72 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10 73 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16) 74 75 #define I40E_NVM_VERSION_LO_SHIFT 0 76 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) 77 #define I40E_NVM_VERSION_HI_SHIFT 12 78 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT) 79 #define I40E_OEM_VER_BUILD_MASK 0xffff 80 #define I40E_OEM_VER_PATCH_MASK 0xff 81 #define I40E_OEM_VER_BUILD_SHIFT 8 82 #define I40E_OEM_VER_SHIFT 24 83 #define I40E_PHY_DEBUG_ALL \ 84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \ 85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW) 86 87 #define I40E_OEM_EETRACK_ID 0xffffffff 88 #define I40E_OEM_GEN_SHIFT 24 89 #define I40E_OEM_SNAP_MASK 0x00ff0000 90 #define I40E_OEM_SNAP_SHIFT 16 91 #define I40E_OEM_RELEASE_MASK 0x0000ffff 92 93 /* The values in here are decimal coded as hex as is the case in the NVM map*/ 94 #define I40E_CURRENT_NVM_VERSION_HI 0x2 95 #define I40E_CURRENT_NVM_VERSION_LO 0x40 96 97 #define I40E_RX_DESC(R, i) \ 98 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) 99 #define I40E_TX_DESC(R, i) \ 100 (&(((struct i40e_tx_desc *)((R)->desc))[i])) 101 #define I40E_TX_CTXTDESC(R, i) \ 102 (&(((struct i40e_tx_context_desc *)((R)->desc))[i])) 103 #define I40E_TX_FDIRDESC(R, i) \ 104 (&(((struct i40e_filter_program_desc *)((R)->desc))[i])) 105 106 /* default to trying for four seconds */ 107 #define I40E_TRY_LINK_TIMEOUT (4 * HZ) 108 109 /* BW rate limiting */ 110 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */ 111 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */ 112 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */ 113 114 /* driver state flags */ 115 enum i40e_state_t { 116 __I40E_TESTING, 117 __I40E_CONFIG_BUSY, 118 __I40E_CONFIG_DONE, 119 __I40E_DOWN, 120 __I40E_SERVICE_SCHED, 121 __I40E_ADMINQ_EVENT_PENDING, 122 __I40E_MDD_EVENT_PENDING, 123 __I40E_VFLR_EVENT_PENDING, 124 __I40E_RESET_RECOVERY_PENDING, 125 __I40E_MISC_IRQ_REQUESTED, 126 __I40E_RESET_INTR_RECEIVED, 127 __I40E_REINIT_REQUESTED, 128 __I40E_PF_RESET_REQUESTED, 129 __I40E_CORE_RESET_REQUESTED, 130 __I40E_GLOBAL_RESET_REQUESTED, 131 __I40E_EMP_RESET_REQUESTED, 132 __I40E_EMP_RESET_INTR_RECEIVED, 133 __I40E_SUSPENDED, 134 __I40E_PTP_TX_IN_PROGRESS, 135 __I40E_BAD_EEPROM, 136 __I40E_DOWN_REQUESTED, 137 __I40E_FD_FLUSH_REQUESTED, 138 __I40E_FD_ATR_AUTO_DISABLED, 139 __I40E_FD_SB_AUTO_DISABLED, 140 __I40E_RESET_FAILED, 141 __I40E_PORT_SUSPENDED, 142 __I40E_VF_DISABLE, 143 __I40E_MACVLAN_SYNC_PENDING, 144 __I40E_UDP_FILTER_SYNC_PENDING, 145 __I40E_TEMP_LINK_POLLING, 146 __I40E_CLIENT_SERVICE_REQUESTED, 147 __I40E_CLIENT_L2_CHANGE, 148 __I40E_CLIENT_RESET, 149 /* This must be last as it determines the size of the BITMAP */ 150 __I40E_STATE_SIZE__, 151 }; 152 153 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED) 154 155 /* VSI state flags */ 156 enum i40e_vsi_state_t { 157 __I40E_VSI_DOWN, 158 __I40E_VSI_NEEDS_RESTART, 159 __I40E_VSI_SYNCING_FILTERS, 160 __I40E_VSI_OVERFLOW_PROMISC, 161 __I40E_VSI_REINIT_REQUESTED, 162 __I40E_VSI_DOWN_REQUESTED, 163 /* This must be last as it determines the size of the BITMAP */ 164 __I40E_VSI_STATE_SIZE__, 165 }; 166 167 enum i40e_interrupt_policy { 168 I40E_INTERRUPT_BEST_CASE, 169 I40E_INTERRUPT_MEDIUM, 170 I40E_INTERRUPT_LOWEST 171 }; 172 173 struct i40e_lump_tracking { 174 u16 num_entries; 175 u16 search_hint; 176 u16 list[0]; 177 #define I40E_PILE_VALID_BIT 0x8000 178 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2) 179 }; 180 181 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20 182 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512 183 #define I40E_FDIR_BUFFER_FULL_MARGIN 10 184 #define I40E_FDIR_BUFFER_HEAD_ROOM 32 185 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4) 186 187 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4) 188 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4) 189 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4) 190 191 enum i40e_fd_stat_idx { 192 I40E_FD_STAT_ATR, 193 I40E_FD_STAT_SB, 194 I40E_FD_STAT_ATR_TUNNEL, 195 I40E_FD_STAT_PF_COUNT 196 }; 197 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT) 198 #define I40E_FD_ATR_STAT_IDX(pf_id) \ 199 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR) 200 #define I40E_FD_SB_STAT_IDX(pf_id) \ 201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB) 202 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \ 203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL) 204 205 /* The following structure contains the data parsed from the user-defined 206 * field of the ethtool_rx_flow_spec structure. 207 */ 208 struct i40e_rx_flow_userdef { 209 bool flex_filter; 210 u16 flex_word; 211 u16 flex_offset; 212 }; 213 214 struct i40e_fdir_filter { 215 struct hlist_node fdir_node; 216 /* filter ipnut set */ 217 u8 flow_type; 218 u8 ip4_proto; 219 /* TX packet view of src and dst */ 220 __be32 dst_ip; 221 __be32 src_ip; 222 __be16 src_port; 223 __be16 dst_port; 224 __be32 sctp_v_tag; 225 226 /* Flexible data to match within the packet payload */ 227 __be16 flex_word; 228 u16 flex_offset; 229 bool flex_filter; 230 231 /* filter control */ 232 u16 q_index; 233 u8 flex_off; 234 u8 pctype; 235 u16 dest_vsi; 236 u8 dest_ctl; 237 u8 fd_status; 238 u16 cnt_index; 239 u32 fd_id; 240 }; 241 242 #define I40E_CLOUD_FIELD_OMAC 0x01 243 #define I40E_CLOUD_FIELD_IMAC 0x02 244 #define I40E_CLOUD_FIELD_IVLAN 0x04 245 #define I40E_CLOUD_FIELD_TEN_ID 0x08 246 #define I40E_CLOUD_FIELD_IIP 0x10 247 248 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC 249 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC 250 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \ 251 I40E_CLOUD_FIELD_IVLAN) 252 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 253 I40E_CLOUD_FIELD_TEN_ID) 254 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \ 255 I40E_CLOUD_FIELD_IMAC | \ 256 I40E_CLOUD_FIELD_TEN_ID) 257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \ 258 I40E_CLOUD_FIELD_IVLAN | \ 259 I40E_CLOUD_FIELD_TEN_ID) 260 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP 261 262 struct i40e_cloud_filter { 263 struct hlist_node cloud_node; 264 unsigned long cookie; 265 /* cloud filter input set follows */ 266 u8 dst_mac[ETH_ALEN]; 267 u8 src_mac[ETH_ALEN]; 268 __be16 vlan_id; 269 u16 seid; /* filter control */ 270 __be16 dst_port; 271 __be16 src_port; 272 u32 tenant_id; 273 union { 274 struct { 275 struct in_addr dst_ip; 276 struct in_addr src_ip; 277 } v4; 278 struct { 279 struct in6_addr dst_ip6; 280 struct in6_addr src_ip6; 281 } v6; 282 } ip; 283 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 284 #define src_ipv6 ip.v6.src_ip6.s6_addr32 285 #define dst_ipv4 ip.v4.dst_ip.s_addr 286 #define src_ipv4 ip.v4.src_ip.s_addr 287 u16 n_proto; /* Ethernet Protocol */ 288 u8 ip_proto; /* IPPROTO value */ 289 u8 flags; 290 #define I40E_CLOUD_TNL_TYPE_NONE 0xff 291 u8 tunnel_type; 292 }; 293 294 #define I40E_ETH_P_LLDP 0x88cc 295 296 #define I40E_DCB_PRIO_TYPE_STRICT 0 297 #define I40E_DCB_PRIO_TYPE_ETS 1 298 #define I40E_DCB_STRICT_PRIO_CREDITS 127 299 /* DCB per TC information data structure */ 300 struct i40e_tc_info { 301 u16 qoffset; /* Queue offset from base queue */ 302 u16 qcount; /* Total Queues */ 303 u8 netdev_tc; /* Netdev TC index if netdev associated */ 304 }; 305 306 /* TC configuration data structure */ 307 struct i40e_tc_configuration { 308 u8 numtc; /* Total number of enabled TCs */ 309 u8 enabled_tc; /* TC map */ 310 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS]; 311 }; 312 313 #define I40E_UDP_PORT_INDEX_UNUSED 255 314 struct i40e_udp_port_config { 315 /* AdminQ command interface expects port number in Host byte order */ 316 u16 port; 317 u8 type; 318 u8 filter_index; 319 }; 320 321 /* macros related to FLX_PIT */ 322 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \ 323 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \ 324 I40E_PRTQF_FLX_PIT_FSIZE_MASK) 325 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \ 326 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \ 327 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) 328 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \ 329 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \ 330 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) 331 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \ 332 I40E_FLEX_SET_FSIZE(fsize) | \ 333 I40E_FLEX_SET_SRC_WORD(src)) 334 335 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \ 336 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \ 337 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 338 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \ 339 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \ 340 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 341 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \ 342 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \ 343 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 344 345 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F 346 347 /* macros related to GLQF_ORT */ 348 #define I40E_ORT_SET_IDX(idx) (((idx) << \ 349 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \ 350 I40E_GLQF_ORT_PIT_INDX_MASK) 351 352 #define I40E_ORT_SET_COUNT(count) (((count) << \ 353 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \ 354 I40E_GLQF_ORT_FIELD_CNT_MASK) 355 356 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \ 357 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \ 358 I40E_GLQF_ORT_FLX_PAYLOAD_MASK) 359 360 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \ 361 I40E_ORT_SET_COUNT(count) | \ 362 I40E_ORT_SET_PAYLOAD(payload)) 363 364 #define I40E_L3_GLQF_ORT_IDX 34 365 #define I40E_L4_GLQF_ORT_IDX 35 366 367 /* Flex PIT register index */ 368 #define I40E_FLEX_PIT_IDX_START_L2 0 369 #define I40E_FLEX_PIT_IDX_START_L3 3 370 #define I40E_FLEX_PIT_IDX_START_L4 6 371 372 #define I40E_FLEX_PIT_TABLE_SIZE 3 373 374 #define I40E_FLEX_DEST_UNUSED 63 375 376 #define I40E_FLEX_INDEX_ENTRIES 8 377 378 /* Flex MASK to disable all flexible entries */ 379 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \ 380 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \ 381 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \ 382 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK) 383 384 struct i40e_flex_pit { 385 struct list_head list; 386 u16 src_offset; 387 u8 pit_index; 388 }; 389 390 struct i40e_channel { 391 struct list_head list; 392 bool initialized; 393 u8 type; 394 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */ 395 u16 stat_counter_idx; 396 u16 base_queue; 397 u16 num_queue_pairs; /* Requested by user */ 398 u16 seid; 399 400 u8 enabled_tc; 401 struct i40e_aqc_vsi_properties_data info; 402 403 u64 max_tx_rate; 404 405 /* track this channel belongs to which VSI */ 406 struct i40e_vsi *parent_vsi; 407 }; 408 409 /* struct that defines the Ethernet device */ 410 struct i40e_pf { 411 struct pci_dev *pdev; 412 struct i40e_hw hw; 413 DECLARE_BITMAP(state, __I40E_STATE_SIZE__); 414 struct msix_entry *msix_entries; 415 bool fc_autoneg_status; 416 417 u16 eeprom_version; 418 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */ 419 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */ 420 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */ 421 u16 num_req_vfs; /* num VFs requested for this PF */ 422 u16 num_vf_qps; /* num queue pairs per VF */ 423 u16 num_lan_qps; /* num lan queues this PF has set up */ 424 u16 num_lan_msix; /* num queue vectors for the base PF vsi */ 425 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */ 426 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */ 427 int iwarp_base_vector; 428 int queues_left; /* queues left unclaimed */ 429 u16 alloc_rss_size; /* allocated RSS queues */ 430 u16 rss_size_max; /* HW defined max RSS queues */ 431 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */ 432 u16 num_alloc_vsi; /* num VSIs this driver supports */ 433 u8 atr_sample_rate; 434 bool wol_en; 435 436 struct hlist_head fdir_filter_list; 437 u16 fdir_pf_active_filters; 438 unsigned long fd_flush_timestamp; 439 u32 fd_flush_cnt; 440 u32 fd_add_err; 441 u32 fd_atr_cnt; 442 443 /* Book-keeping of side-band filter count per flow-type. 444 * This is used to detect and handle input set changes for 445 * respective flow-type. 446 */ 447 u16 fd_tcp4_filter_cnt; 448 u16 fd_udp4_filter_cnt; 449 u16 fd_sctp4_filter_cnt; 450 u16 fd_ip4_filter_cnt; 451 452 /* Flexible filter table values that need to be programmed into 453 * hardware, which expects L3 and L4 to be programmed separately. We 454 * need to ensure that the values are in ascended order and don't have 455 * duplicates, so we track each L3 and L4 values in separate lists. 456 */ 457 struct list_head l3_flex_pit_list; 458 struct list_head l4_flex_pit_list; 459 460 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; 461 u16 pending_udp_bitmap; 462 463 struct hlist_head cloud_filter_list; 464 u16 num_cloud_filters; 465 466 enum i40e_interrupt_policy int_policy; 467 u16 rx_itr_default; 468 u16 tx_itr_default; 469 u32 msg_enable; 470 char int_name[I40E_INT_NAME_STR_LEN]; 471 u16 adminq_work_limit; /* num of admin receive queue desc to process */ 472 unsigned long service_timer_period; 473 unsigned long service_timer_previous; 474 struct timer_list service_timer; 475 struct work_struct service_task; 476 477 u32 hw_features; 478 #define I40E_HW_RSS_AQ_CAPABLE BIT(0) 479 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1) 480 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2) 481 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3) 482 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4) 483 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5) 484 #define I40E_HW_100M_SGMII_CAPABLE BIT(6) 485 #define I40E_HW_NO_DCB_SUPPORT BIT(7) 486 #define I40E_HW_USE_SET_LLDP_MIB BIT(8) 487 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9) 488 #define I40E_HW_PTP_L4_CAPABLE BIT(10) 489 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11) 490 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12) 491 #define I40E_HW_HAVE_CRT_RETIMER BIT(13) 492 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14) 493 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15) 494 #define I40E_HW_STOP_FW_LLDP BIT(16) 495 #define I40E_HW_PORT_ID_VALID BIT(17) 496 #define I40E_HW_RESTART_AUTONEG BIT(18) 497 #define I40E_HW_STOPPABLE_FW_LLDP BIT(19) 498 499 u32 flags; 500 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0) 501 #define I40E_FLAG_MSI_ENABLED BIT(1) 502 #define I40E_FLAG_MSIX_ENABLED BIT(2) 503 #define I40E_FLAG_RSS_ENABLED BIT(3) 504 #define I40E_FLAG_VMDQ_ENABLED BIT(4) 505 #define I40E_FLAG_SRIOV_ENABLED BIT(5) 506 #define I40E_FLAG_DCB_CAPABLE BIT(6) 507 #define I40E_FLAG_DCB_ENABLED BIT(7) 508 #define I40E_FLAG_FD_SB_ENABLED BIT(8) 509 #define I40E_FLAG_FD_ATR_ENABLED BIT(9) 510 #define I40E_FLAG_MFP_ENABLED BIT(10) 511 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11) 512 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12) 513 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13) 514 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14) 515 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15) 516 #define I40E_FLAG_LEGACY_RX BIT(16) 517 #define I40E_FLAG_PTP BIT(17) 518 #define I40E_FLAG_IWARP_ENABLED BIT(18) 519 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19) 520 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20) 521 #define I40E_FLAG_TC_MQPRIO BIT(21) 522 #define I40E_FLAG_FD_SB_INACTIVE BIT(22) 523 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23) 524 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24) 525 526 struct i40e_client_instance *cinst; 527 bool stat_offsets_loaded; 528 struct i40e_hw_port_stats stats; 529 struct i40e_hw_port_stats stats_offsets; 530 u32 tx_timeout_count; 531 u32 tx_timeout_recovery_level; 532 unsigned long tx_timeout_last_recovery; 533 u32 tx_sluggish_count; 534 u32 hw_csum_rx_error; 535 u32 led_status; 536 u16 corer_count; /* Core reset count */ 537 u16 globr_count; /* Global reset count */ 538 u16 empr_count; /* EMP reset count */ 539 u16 pfr_count; /* PF reset count */ 540 u16 sw_int_count; /* SW interrupt count */ 541 542 struct mutex switch_mutex; 543 u16 lan_vsi; /* our default LAN VSI */ 544 u16 lan_veb; /* initial relay, if exists */ 545 #define I40E_NO_VEB 0xffff 546 #define I40E_NO_VSI 0xffff 547 u16 next_vsi; /* Next unallocated VSI - 0-based! */ 548 struct i40e_vsi **vsi; 549 struct i40e_veb *veb[I40E_MAX_VEB]; 550 551 struct i40e_lump_tracking *qp_pile; 552 struct i40e_lump_tracking *irq_pile; 553 554 /* switch config info */ 555 u16 pf_seid; 556 u16 main_vsi_seid; 557 u16 mac_seid; 558 struct kobject *switch_kobj; 559 #ifdef CONFIG_DEBUG_FS 560 struct dentry *i40e_dbg_pf; 561 #endif /* CONFIG_DEBUG_FS */ 562 bool cur_promisc; 563 564 u16 instance; /* A unique number per i40e_pf instance in the system */ 565 566 /* sr-iov config info */ 567 struct i40e_vf *vf; 568 int num_alloc_vfs; /* actual number of VFs allocated */ 569 u32 vf_aq_requests; 570 u32 arq_overflows; /* Not fatal, possibly indicative of problems */ 571 572 /* DCBx/DCBNL capability for PF that indicates 573 * whether DCBx is managed by firmware or host 574 * based agent (LLDPAD). Also, indicates what 575 * flavor of DCBx protocol (IEEE/CEE) is supported 576 * by the device. For now we're supporting IEEE 577 * mode only. 578 */ 579 u16 dcbx_cap; 580 581 struct i40e_filter_control_settings filter_settings; 582 583 struct ptp_clock *ptp_clock; 584 struct ptp_clock_info ptp_caps; 585 struct sk_buff *ptp_tx_skb; 586 unsigned long ptp_tx_start; 587 struct hwtstamp_config tstamp_config; 588 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */ 589 u32 ptp_adj_mult; 590 u32 tx_hwtstamp_timeouts; 591 u32 tx_hwtstamp_skipped; 592 u32 rx_hwtstamp_cleared; 593 u32 latch_event_flags; 594 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */ 595 unsigned long latch_events[4]; 596 bool ptp_tx; 597 bool ptp_rx; 598 u16 rss_table_size; /* HW RSS table size */ 599 u32 max_bw; 600 u32 min_bw; 601 602 u32 ioremap_len; 603 u32 fd_inv; 604 u16 phy_led_val; 605 606 u16 override_q_count; 607 u16 last_sw_conf_flags; 608 u16 last_sw_conf_valid_flags; 609 }; 610 611 /** 612 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key 613 * @macaddr: the MAC Address as the base key 614 * 615 * Simply copies the address and returns it as a u64 for hashing 616 **/ 617 static inline u64 i40e_addr_to_hkey(const u8 *macaddr) 618 { 619 u64 key = 0; 620 621 ether_addr_copy((u8 *)&key, macaddr); 622 return key; 623 } 624 625 enum i40e_filter_state { 626 I40E_FILTER_INVALID = 0, /* Invalid state */ 627 I40E_FILTER_NEW, /* New, not sent to FW yet */ 628 I40E_FILTER_ACTIVE, /* Added to switch by FW */ 629 I40E_FILTER_FAILED, /* Rejected by FW */ 630 I40E_FILTER_REMOVE, /* To be removed */ 631 /* There is no 'removed' state; the filter struct is freed */ 632 }; 633 struct i40e_mac_filter { 634 struct hlist_node hlist; 635 u8 macaddr[ETH_ALEN]; 636 #define I40E_VLAN_ANY -1 637 s16 vlan; 638 enum i40e_filter_state state; 639 }; 640 641 /* Wrapper structure to keep track of filters while we are preparing to send 642 * firmware commands. We cannot send firmware commands while holding a 643 * spinlock, since it might sleep. To avoid this, we wrap the added filters in 644 * a separate structure, which will track the state change and update the real 645 * filter while under lock. We can't simply hold the filters in a separate 646 * list, as this opens a window for a race condition when adding new MAC 647 * addresses to all VLANs, or when adding new VLANs to all MAC addresses. 648 */ 649 struct i40e_new_mac_filter { 650 struct hlist_node hlist; 651 struct i40e_mac_filter *f; 652 653 /* Track future changes to state separately */ 654 enum i40e_filter_state state; 655 }; 656 657 struct i40e_veb { 658 struct i40e_pf *pf; 659 u16 idx; 660 u16 veb_idx; /* index of VEB parent */ 661 u16 seid; 662 u16 uplink_seid; 663 u16 stats_idx; /* index of VEB parent */ 664 u8 enabled_tc; 665 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */ 666 u16 flags; 667 u16 bw_limit; 668 u8 bw_max_quanta; 669 bool is_abs_credits; 670 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS]; 671 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 672 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 673 struct kobject *kobj; 674 bool stat_offsets_loaded; 675 struct i40e_eth_stats stats; 676 struct i40e_eth_stats stats_offsets; 677 struct i40e_veb_tc_stats tc_stats; 678 struct i40e_veb_tc_stats tc_stats_offsets; 679 }; 680 681 /* struct that defines a VSI, associated with a dev */ 682 struct i40e_vsi { 683 struct net_device *netdev; 684 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 685 bool netdev_registered; 686 bool stat_offsets_loaded; 687 688 u32 current_netdev_flags; 689 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__); 690 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0) 691 #define I40E_VSI_FLAG_VEB_OWNER BIT(1) 692 unsigned long flags; 693 694 /* Per VSI lock to protect elements/hash (MAC filter) */ 695 spinlock_t mac_filter_hash_lock; 696 /* Fixed size hash table with 2^8 buckets for MAC filters */ 697 DECLARE_HASHTABLE(mac_filter_hash, 8); 698 bool has_vlan_filter; 699 700 /* VSI stats */ 701 struct rtnl_link_stats64 net_stats; 702 struct rtnl_link_stats64 net_stats_offsets; 703 struct i40e_eth_stats eth_stats; 704 struct i40e_eth_stats eth_stats_offsets; 705 u32 tx_restart; 706 u32 tx_busy; 707 u64 tx_linearize; 708 u64 tx_force_wb; 709 u32 rx_buf_failed; 710 u32 rx_page_failed; 711 712 /* These are containers of ring pointers, allocated at run-time */ 713 struct i40e_ring **rx_rings; 714 struct i40e_ring **tx_rings; 715 struct i40e_ring **xdp_rings; /* XDP Tx rings */ 716 717 u32 active_filters; 718 u32 promisc_threshold; 719 720 u16 work_limit; 721 u16 int_rate_limit; /* value in usecs */ 722 723 u16 rss_table_size; /* HW RSS table size */ 724 u16 rss_size; /* Allocated RSS queues */ 725 u8 *rss_hkey_user; /* User configured hash keys */ 726 u8 *rss_lut_user; /* User configured lookup table entries */ 727 728 729 u16 max_frame; 730 u16 rx_buf_len; 731 732 struct bpf_prog *xdp_prog; 733 734 /* List of q_vectors allocated to this VSI */ 735 struct i40e_q_vector **q_vectors; 736 int num_q_vectors; 737 int base_vector; 738 bool irqs_ready; 739 740 u16 seid; /* HW index of this VSI (absolute index) */ 741 u16 id; /* VSI number */ 742 u16 uplink_seid; 743 744 u16 base_queue; /* vsi's first queue in hw array */ 745 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */ 746 u16 req_queue_pairs; /* User requested queue pairs */ 747 u16 num_queue_pairs; /* Used tx and rx pairs */ 748 u16 num_desc; 749 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */ 750 s16 vf_id; /* Virtual function ID for SRIOV VSIs */ 751 752 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */ 753 struct i40e_tc_configuration tc_config; 754 struct i40e_aqc_vsi_properties_data info; 755 756 /* VSI BW limit (absolute across all TCs) */ 757 u16 bw_limit; /* VSI BW Limit (0 = disabled) */ 758 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */ 759 760 /* Relative TC credits across VSIs */ 761 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; 762 /* TC BW limit credits within VSI */ 763 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; 764 /* TC BW limit max quanta within VSI */ 765 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; 766 767 struct i40e_pf *back; /* Backreference to associated PF */ 768 u16 idx; /* index in pf->vsi[] */ 769 u16 veb_idx; /* index of VEB parent */ 770 struct kobject *kobj; /* sysfs object */ 771 bool current_isup; /* Sync 'link up' logging */ 772 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */ 773 774 /* channel specific fields */ 775 u16 cnt_q_avail; /* num of queues available for channel usage */ 776 u16 orig_rss_size; 777 u16 current_rss_size; 778 bool reconfig_rss; 779 780 u16 next_base_queue; /* next queue to be used for channel setup */ 781 782 struct list_head ch_list; 783 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS]; 784 785 void *priv; /* client driver data reference. */ 786 787 /* VSI specific handlers */ 788 irqreturn_t (*irq_handler)(int irq, void *data); 789 } ____cacheline_internodealigned_in_smp; 790 791 struct i40e_netdev_priv { 792 struct i40e_vsi *vsi; 793 }; 794 795 /* struct that defines an interrupt vector */ 796 struct i40e_q_vector { 797 struct i40e_vsi *vsi; 798 799 u16 v_idx; /* index in the vsi->q_vector array. */ 800 u16 reg_idx; /* register index of the interrupt */ 801 802 struct napi_struct napi; 803 804 struct i40e_ring_container rx; 805 struct i40e_ring_container tx; 806 807 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 808 u8 num_ringpairs; /* total number of ring pairs in vector */ 809 810 cpumask_t affinity_mask; 811 struct irq_affinity_notify affinity_notify; 812 813 struct rcu_head rcu; /* to avoid race with update stats on free */ 814 char name[I40E_INT_NAME_STR_LEN]; 815 bool arm_wb_state; 816 } ____cacheline_internodealigned_in_smp; 817 818 /* lan device */ 819 struct i40e_device { 820 struct list_head list; 821 struct i40e_pf *pf; 822 }; 823 824 /** 825 * i40e_nvm_version_str - format the NVM version strings 826 * @hw: ptr to the hardware info 827 **/ 828 static inline char *i40e_nvm_version_str(struct i40e_hw *hw) 829 { 830 static char buf[32]; 831 u32 full_ver; 832 833 full_ver = hw->nvm.oem_ver; 834 835 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) { 836 u8 gen, snap; 837 u16 release; 838 839 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT); 840 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >> 841 I40E_OEM_SNAP_SHIFT); 842 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK); 843 844 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release); 845 } else { 846 u8 ver, patch; 847 u16 build; 848 849 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT); 850 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) & 851 I40E_OEM_VER_BUILD_MASK); 852 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK); 853 854 snprintf(buf, sizeof(buf), 855 "%x.%02x 0x%x %d.%d.%d", 856 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >> 857 I40E_NVM_VERSION_HI_SHIFT, 858 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >> 859 I40E_NVM_VERSION_LO_SHIFT, 860 hw->nvm.eetrack, ver, build, patch); 861 } 862 863 return buf; 864 } 865 866 /** 867 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev 868 * @netdev: the corresponding netdev 869 * 870 * Return the PF struct for the given netdev 871 **/ 872 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev) 873 { 874 struct i40e_netdev_priv *np = netdev_priv(netdev); 875 struct i40e_vsi *vsi = np->vsi; 876 877 return vsi->back; 878 } 879 880 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi, 881 irqreturn_t (*irq_handler)(int, void *)) 882 { 883 vsi->irq_handler = irq_handler; 884 } 885 886 /** 887 * i40e_get_fd_cnt_all - get the total FD filter space available 888 * @pf: pointer to the PF struct 889 **/ 890 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf) 891 { 892 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count; 893 } 894 895 /** 896 * i40e_read_fd_input_set - reads value of flow director input set register 897 * @pf: pointer to the PF struct 898 * @addr: register addr 899 * 900 * This function reads value of flow director input set register 901 * specified by 'addr' (which is specific to flow-type) 902 **/ 903 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr) 904 { 905 u64 val; 906 907 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1)); 908 val <<= 32; 909 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0)); 910 911 return val; 912 } 913 914 /** 915 * i40e_write_fd_input_set - writes value into flow director input set register 916 * @pf: pointer to the PF struct 917 * @addr: register addr 918 * @val: value to be written 919 * 920 * This function writes specified value to the register specified by 'addr'. 921 * This register is input set register based on flow-type. 922 **/ 923 static inline void i40e_write_fd_input_set(struct i40e_pf *pf, 924 u16 addr, u64 val) 925 { 926 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1), 927 (u32)(val >> 32)); 928 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0), 929 (u32)(val & 0xFFFFFFFFULL)); 930 } 931 932 /* needed by i40e_ethtool.c */ 933 int i40e_up(struct i40e_vsi *vsi); 934 void i40e_down(struct i40e_vsi *vsi); 935 extern const char i40e_driver_name[]; 936 extern const char i40e_driver_version_str[]; 937 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags); 938 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired); 939 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 940 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 941 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, 942 u16 rss_table_size, u16 rss_size); 943 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id); 944 /** 945 * i40e_find_vsi_by_type - Find and return Flow Director VSI 946 * @pf: PF to search for VSI 947 * @type: Value indicating type of VSI we are looking for 948 **/ 949 static inline struct i40e_vsi * 950 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type) 951 { 952 int i; 953 954 for (i = 0; i < pf->num_alloc_vsi; i++) { 955 struct i40e_vsi *vsi = pf->vsi[i]; 956 957 if (vsi && vsi->type == type) 958 return vsi; 959 } 960 961 return NULL; 962 } 963 void i40e_update_stats(struct i40e_vsi *vsi); 964 void i40e_update_eth_stats(struct i40e_vsi *vsi); 965 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi); 966 int i40e_fetch_switch_configuration(struct i40e_pf *pf, 967 bool printconfig); 968 969 int i40e_add_del_fdir(struct i40e_vsi *vsi, 970 struct i40e_fdir_filter *input, bool add); 971 void i40e_fdir_check_and_reenable(struct i40e_pf *pf); 972 u32 i40e_get_current_fd_count(struct i40e_pf *pf); 973 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf); 974 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf); 975 u32 i40e_get_global_fd_count(struct i40e_pf *pf); 976 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features); 977 void i40e_set_ethtool_ops(struct net_device *netdev); 978 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, 979 const u8 *macaddr, s16 vlan); 980 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f); 981 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan); 982 int i40e_sync_vsi_filters(struct i40e_vsi *vsi); 983 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, 984 u16 uplink, u32 param1); 985 int i40e_vsi_release(struct i40e_vsi *vsi); 986 void i40e_service_event_schedule(struct i40e_pf *pf); 987 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id, 988 u8 *msg, u16 len); 989 990 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp, 991 bool enable); 992 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable); 993 int i40e_vsi_start_rings(struct i40e_vsi *vsi); 994 void i40e_vsi_stop_rings(struct i40e_vsi *vsi); 995 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi); 996 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi); 997 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count); 998 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid, 999 u16 downlink_seid, u8 enabled_tc); 1000 void i40e_veb_release(struct i40e_veb *veb); 1001 1002 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc); 1003 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid); 1004 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi); 1005 void i40e_vsi_reset_stats(struct i40e_vsi *vsi); 1006 void i40e_pf_reset_stats(struct i40e_pf *pf); 1007 #ifdef CONFIG_DEBUG_FS 1008 void i40e_dbg_pf_init(struct i40e_pf *pf); 1009 void i40e_dbg_pf_exit(struct i40e_pf *pf); 1010 void i40e_dbg_init(void); 1011 void i40e_dbg_exit(void); 1012 #else 1013 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {} 1014 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {} 1015 static inline void i40e_dbg_init(void) {} 1016 static inline void i40e_dbg_exit(void) {} 1017 #endif /* CONFIG_DEBUG_FS*/ 1018 /* needed by client drivers */ 1019 int i40e_lan_add_device(struct i40e_pf *pf); 1020 int i40e_lan_del_device(struct i40e_pf *pf); 1021 void i40e_client_subtask(struct i40e_pf *pf); 1022 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi); 1023 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset); 1024 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs); 1025 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id); 1026 void i40e_client_update_msix_info(struct i40e_pf *pf); 1027 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id); 1028 /** 1029 * i40e_irq_dynamic_enable - Enable default interrupt generation settings 1030 * @vsi: pointer to a vsi 1031 * @vector: enable a particular Hw Interrupt vector, without base_vector 1032 **/ 1033 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector) 1034 { 1035 struct i40e_pf *pf = vsi->back; 1036 struct i40e_hw *hw = &pf->hw; 1037 u32 val; 1038 1039 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1040 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1041 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1042 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val); 1043 /* skip the flush */ 1044 } 1045 1046 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf); 1047 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf); 1048 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 1049 int i40e_open(struct net_device *netdev); 1050 int i40e_close(struct net_device *netdev); 1051 int i40e_vsi_open(struct i40e_vsi *vsi); 1052 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi); 1053 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1054 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid); 1055 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid); 1056 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid); 1057 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, 1058 const u8 *macaddr); 1059 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr); 1060 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi); 1061 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr); 1062 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi); 1063 #ifdef CONFIG_I40E_DCB 1064 void i40e_dcbnl_flush_apps(struct i40e_pf *pf, 1065 struct i40e_dcbx_config *old_cfg, 1066 struct i40e_dcbx_config *new_cfg); 1067 void i40e_dcbnl_set_all(struct i40e_vsi *vsi); 1068 void i40e_dcbnl_setup(struct i40e_vsi *vsi); 1069 bool i40e_dcb_need_reconfig(struct i40e_pf *pf, 1070 struct i40e_dcbx_config *old_cfg, 1071 struct i40e_dcbx_config *new_cfg); 1072 #endif /* CONFIG_I40E_DCB */ 1073 void i40e_ptp_rx_hang(struct i40e_pf *pf); 1074 void i40e_ptp_tx_hang(struct i40e_pf *pf); 1075 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf); 1076 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index); 1077 void i40e_ptp_set_increment(struct i40e_pf *pf); 1078 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1079 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr); 1080 void i40e_ptp_init(struct i40e_pf *pf); 1081 void i40e_ptp_stop(struct i40e_pf *pf); 1082 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi); 1083 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf); 1084 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf); 1085 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf); 1086 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup); 1087 1088 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi) 1089 { 1090 return !!vsi->xdp_prog; 1091 } 1092 1093 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch); 1094 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate); 1095 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, 1096 struct i40e_cloud_filter *filter, 1097 bool add); 1098 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, 1099 struct i40e_cloud_filter *filter, 1100 bool add); 1101 #endif /* _I40E_H_ */ 1102